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[CUTLASS][WIP] Gate rowwise matmul CUTLASS kernels by compute capability #152642
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/152642
Note: Links to docs will display an error until the docs builds have been completed. ❗ 1 Active SEVsThere are 1 currently active SEVs. If your PR is affected, please view them below: ❌ 4 New FailuresAs of commit c474c5b with merge base b6c5886 ( NEW FAILURES - The following jobs have failed:
This comment was automatically generated by Dr. CI and updates every 15 minutes. |
@@ -498,6 +502,7 @@ void f8f8bf16_rowwise_impl_sm89( | |||
at::Tensor w_scale, | |||
std::optional<at::Tensor> bias, | |||
at::Tensor out) { | |||
#if (defined(__CUDA_ARCH__)) && (__CUDA_ARCH__ == 890) |
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The test failures are really strange. As if this condition was evaluated as false
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Looks like this PR hasn't been updated in a while so we're going to go ahead and mark this as |
Does this abate some compile-time warning spam?
cc @ptrblck @msaroufim @jerryzh168 @yanbing-j @vkuzo @albanD @kadeng @penguinwu