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F0 patches that rename registers should modify the existing register #538

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Merged
merged 1 commit into from
Apr 13, 2021
Merged

F0 patches that rename registers should modify the existing register #538

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9 changes: 4 additions & 5 deletions devices/common_patches/f0_adc_fixes.yaml
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
# Renames a few fields in the F0 ADC and adds the WAIT file which was missed
# Renames a few fields in the F0 ADC and replaces AUTDLY with WAIT

ADC:
ISR:
Expand All @@ -10,10 +10,9 @@ ADC:
EOSIE:
name: "EOSEQIE"
CFGR1:
_add:
WAIT:
bitOffset: 14
bitWidth: 1
_modify:
AUTDLY:
name: "WAIT"
description: "Wait conversion mode"
SMPR:
_modify:
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7 changes: 3 additions & 4 deletions devices/common_patches/f0_dmaen.yaml
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
RCC:
AHBENR:
_add:
DMAEN:
_modify:
DMA1EN:
name: DMAEN
description: DMA clock enable
bitOffset: 0
bitWidth: 1