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Add patches and descriptions for STM32WLE5xx #559

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Merged
merged 47 commits into from
Jul 19, 2021
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jorgeig-space
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@jorgeig-space jorgeig-space commented May 30, 2021

This PR adds patches and field descriptions for the STM32WLE5xx (single-core) chips. Most of it is probably applicable to STM32WL55xx (dual-core), and the non-LoRa versions (WLE4 and WL54) although that will only be considered after all peripherals are implemented.

As this is our first contribution, we are looking for feedback from the maintainers and the community.

The following peripherals are implemented (as listed in the ref. manual):

  • FLASH
  • SUBGHZ (N/A, this will go in a HAL)
  • PWR
  • RCC
  • HSEM
  • GPIO
  • SYSCFG
  • DMA
  • DMAMUX
  • NVIC (nothing to do here)
  • EXTI
  • CRC
  • ADC
  • DAC
  • VREFBUF
  • COMP
  • RNG
  • AES
  • PKA
  • TIM1
  • TIM2
  • TIM16/17
  • LPTIM
  • IWDG
  • WWDG
  • RTC
  • TAMP
  • I2C
  • USART/UART
  • LPUART
  • SPI/I2S
  • DBG

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github-actions bot commented Jun 7, 2021

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@jorgeig-space
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Added some more peripherals today, hopefully will finish by the end of the week.

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I did a quick check over everything with the reference manual; looks good!
I also tested it with a nucleo dev board and my half-baked HAL, and it works for what is currently implemented.

Thanks for the monumental amount of effort here @jorgeig-space !

One request I have is that adding patches only for the stm32wle does make this difficult to use with other STM32WL MCUs (lots of warnings because some fields no longer require unsafe). It would be nice to add the stm32wl5x_cm0p.yaml and the stm32wl5x_cm4.yaml at the same time (provided below); but this is scope creep and I am happy to make the contribution after the fact if you do not want to make this PR any larger.

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Amazing, thank you for the review and the new work!

We are in the same situation: using the Nucleo board to develop but having the WLE in production (although we might switch given the single-core version shortage!!). I was planning on adding the dual-core versions soon, but since you've taken the time to do that, I'll add it to the PR.

Let me get through your suggestions this week and then I think it'll be ready to merge.

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Re the split fields,

I am not aware of a seamless way to handle this. We'll have to keep CHMOD2 and indicate in the description that CHMOD must be changed to 00. That's what I did with the timer fields.

The other solution is to change the autogenerated functions by svd2rust, which I am happy to do, but I think it breaks the way the repo works. And lastly, we could handle this at a HAL level, but that wouldn't work for whoever doesn't use the HAL.

Changing the svd2rust output isn't really an option so I think you will just have to keep CHMOD2 and document it, as with the timer fields. It's annoying, but there's no method in the SVD file format to represent this situation, so it's not an easy thing to add to svd2rust or even annotate here.

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@jorgeig-space jorgeig-space marked this pull request as ready for review July 14, 2021 03:42
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I found out svd2rust 0.19.0 has additional validation, I used that to find a few more bugs, I left the fixes as suggestions.

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I found out svd2rust 0.19.0 has additional validation, I used that to find a few more bugs, I left the fixes as suggestions.

All patched. Many thanks for the review!

newAM
newAM previously approved these changes Jul 18, 2021
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Thank you for this PR @jorgeig-space and all the work that went into it, and thanks @newAM for reviewing it so carefully too.

All I've got is some suggestions on variant names to better match the rest of the convention (camel case for variants where possible, and counters like Bits128). Note that svd2rust will generate Rust-appropriate method and variant names including underscores automatically when the input follows this convention, so for example NormalPinBuffer will get a normal_pin_buffer() method.

The one thing I didn't leave a comment on is the ADC resolution which is currently like EightBit. Most of the ADCs in stm32-rs follow this because it predates using Bits8 etc everywhere, though some of the newer v3 ADCs use Bits8 instead. I don't mind if you'd rather keep it as EightBit or move to Bits8.

Let me know what you think about these suggestions, if you have a particular reason in any specific case for it to be like it then it can stay.

Other than that, looks good to merge.

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Thank you for this PR @jorgeig-space and all the work that went into it, and thanks @newAM for reviewing it so carefully too.

All I've got is some suggestions on variant names to better match the rest of the convention (camel case for variants where possible, and counters like Bits128). Note that svd2rust will generate Rust-appropriate method and variant names including underscores automatically when the input follows this convention, so for example NormalPinBuffer will get a normal_pin_buffer() method.

The one thing I didn't leave a comment on is the ADC resolution which is currently like EightBit. Most of the ADCs in stm32-rs follow this because it predates using Bits8 etc everywhere, though some of the newer v3 ADCs use Bits8 instead. I don't mind if you'd rather keep it as EightBit or move to Bits8.

Let me know what you think about these suggestions, if you have a particular reason in any specific case for it to be like it then it can stay.

Other than that, looks good to merge.

Thanks for the review. I agree with your suggestions. I've changed the ADC resolution fields plus some other typos I found too.

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Great, thanks, let's merge this!

bors merge

@bors bors bot merged commit 071a2b4 into stm32-rs:master Jul 19, 2021
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