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Add patches and descriptions for STM32WLE5xx #559

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Merged
merged 47 commits into from
Jul 19, 2021
Merged

Add patches and descriptions for STM32WLE5xx #559

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82f7d5b
Add GPIO and SPI peripherals for STM32WL family
Apr 18, 2021
fc48771
Add ADC
Apr 18, 2021
accbca4
Add Flash and I2C
Apr 18, 2021
f39644e
Add CRC
Apr 18, 2021
327c359
Add RNG
Apr 18, 2021
8d9a5b3
Fix EXTI and ADC
Apr 18, 2021
f82e40d
Merge branch 'master' of https://github.com/stm32-rs/stm32-rs
May 29, 2021
babc3d8
Add PWR peripheral
May 29, 2021
a9fcf09
Fix RRS enums in PWR
May 29, 2021
8a081fd
Add RCC peripheral
May 29, 2021
a46cab5
Add HSEM
May 29, 2021
ba2c0dd
Fix HSEM bits
May 29, 2021
5e846d8
Add DMA and DMAMUX
May 29, 2021
9cd1a89
Add RTC
May 30, 2021
aa010c1
Add AES
May 30, 2021
d18e127
Add AES file
May 30, 2021
8ef4448
Rename files to match WL family
May 30, 2021
14c9946
Correction of VOS range values
May 30, 2021
2df7589
Add AES mode 4 (undocumented, see PR #559)
Jun 7, 2021
4164115
Add PKA
Jun 28, 2021
42b3a89
Add DAC. PKA fixes.
Jun 28, 2021
5085438
Add TIM1 and TIM2
Jun 28, 2021
cd4f5eb
Fix AES CHMOD naming and descriptions
Jun 29, 2021
4ded69f
Add TIM16/17
Jun 29, 2021
b0e6844
Add mission TIM16/17 file
Jun 29, 2021
8a8bd8a
Add IWDG and WWDG
Jun 29, 2021
ef83113
Add LPTIM
Jun 29, 2021
a34260a
Change OC?M nomenclature to match #546
Jun 29, 2021
42e2e5e
Add COMP
Jun 29, 2021
7c07704
Add TAMP
Jun 29, 2021
afcbfdc
Add USART
Jul 3, 2021
089ed5a
Add LPUART, refactor USART for commonality
Jul 4, 2021
56486a8
Add SYSCFG
Jul 4, 2021
823c7fe
Mode HSEM to its own directory
Jul 4, 2021
5bf219d
Add VREFBUF
Jul 4, 2021
d62b633
Add DBGMCU
Jul 4, 2021
363238c
Remove duplicate register entries in DAC and TIM
Jul 5, 2021
4d0e101
Fix MAMP field of DAC CR register
Jul 5, 2021
ee3e20f
RCC usability improvement
Jul 6, 2021
810f7f2
Fix typos
Jul 12, 2021
4bdab1f
EXTI changes for compatibility with WL5
Jul 12, 2021
a43c27d
Refactor HSEM for compatibility with dual-core
Jul 12, 2021
267015c
Add dual core MCU WL5x
Jul 12, 2021
712dd07
Split ADC SMPSEL
Jul 16, 2021
242de72
Fixed bugs found by @newAM in #559
Jul 18, 2021
ab5120f
Correct names to match convention
Jul 19, 2021
06459ae
More name and typo correction
Jul 19, 2021
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Correction of VOS range values
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Jorgeig committed May 30, 2021
commit 14c99463cf484894e8d82ff937e4ce4d8f2856ee
4 changes: 2 additions & 2 deletions peripherals/pwr/pwr_wl.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@ PWR:
MAIN_MODE: [0, "Voltage regulator in Main mode in Low-power run mode"]
LOW_POWER_MODE: [1, "Voltage regulator in low-power mode in Low-power run mode"]
VOS:
V1_8: [1, "1.8 V (range 1)"]
V1_5: [2, "1.5 V (range 2)"]
V1_2: [1, "1.2 V (range 1)"]
V1_0: [2, "1.0 V (range 2)"]
DBP:
Disabled: [0, "Access to RTC and backup registers disabled"]
Enabled: [1, "Access to RTC and backup registers enabled"]
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