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STM32L4xx: Add GPIOx ASCR & BRR registers #680
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Thanks for the PR! Couple of comments:
- The RM describes the BRR / ASCR registers with a series of one-bit fields
BRR0
,BRR1
, ... and this is the case for all the other GPIO register definitions also. I think this would be preferred instead of a 16-bit field for consistency if nothing else - BRR is also missing on stm32l4x1, stm32l4x2, stm32l412, stm32l4x3. These are parts that don't have ASCR, so it would make sense to split the patch file and apply the BRR section to stm32l4x1.. also
@richardeoin Thanks for the feedback. I believe this should address all your points? |
…3 aswell. Add enum variants to both files
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Perfect, thanks!
bors r+
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Tidied merge conflict
bors r+
680: STM32L4xx: Add GPIOx ASCR & BRR registers r=richardeoin a=MathiasKoch Also corrects naming on L4x5 ADC `Mult` to `Dual` field, as per the reference manual, and adds prescaler field under ADC_CRR. Fixes #342 Co-authored-by: Mathias <mk@blackbird.online> Co-authored-by: Richard Meadows <richardeoin@gmail.com>
Build failed: |
Not sure why CI failed. Let's retry bors retry |
Enums in common_patches |
Also corrects naming on L4x5 ADC
Mult
toDual
field, as per the reference manual, and adds prescaler field under ADC_CRR.Fixes #342