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STM32L4xx: Add GPIOx ASCR & BRR registers #680

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Merged
merged 3 commits into from
Jan 16, 2022

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MathiasKoch
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@MathiasKoch MathiasKoch commented Dec 21, 2021

Also corrects naming on L4x5 ADC Mult to Dual field, as per the reference manual, and adds prescaler field under ADC_CRR.

Fixes #342

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@newAM newAM added the stm32l4 label Dec 21, 2021
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@richardeoin richardeoin left a comment

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Thanks for the PR! Couple of comments:

  • The RM describes the BRR / ASCR registers with a series of one-bit fields BRR0, BRR1, ... and this is the case for all the other GPIO register definitions also. I think this would be preferred instead of a 16-bit field for consistency if nothing else
  • BRR is also missing on stm32l4x1, stm32l4x2, stm32l412, stm32l4x3. These are parts that don't have ASCR, so it would make sense to split the patch file and apply the BRR section to stm32l4x1.. also

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@richardeoin Thanks for the feedback.

I believe this should address all your points?

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@MathiasKoch MathiasKoch changed the title STM32L4x5: Add GPIOx ASCR & BRR registers STM32L4xx: Add GPIOx ASCR & BRR registers Jan 15, 2022
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richardeoin
richardeoin previously approved these changes Jan 16, 2022
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Perfect, thanks!

bors r+

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Tidied merge conflict

bors r+

bors bot added a commit that referenced this pull request Jan 16, 2022
680: STM32L4xx: Add GPIOx ASCR & BRR registers r=richardeoin a=MathiasKoch

Also corrects naming on L4x5 ADC `Mult` to `Dual` field, as per the reference manual, and adds prescaler field under ADC_CRR.

Fixes #342

Co-authored-by: Mathias <mk@blackbird.online>
Co-authored-by: Richard Meadows <richardeoin@gmail.com>
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bors bot commented Jan 16, 2022

Build failed:

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Not sure why CI failed. Let's retry

bors retry

@bors bors bot merged commit 20480f3 into stm32-rs:master Jan 16, 2022
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Enums in common_patches

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STM32L4x5/6 Missing Registers
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