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GPIOx cleanup and improvement #717

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Merged
merged 17 commits into from
May 30, 2022
Merged

GPIOx cleanup and improvement #717

merged 17 commits into from
May 30, 2022

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larchuto
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@larchuto larchuto commented Apr 9, 2022 •
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  • STM32WL family does not depend on gpio_v2_common directly anymore
  • Make it clear that STM32G0 depends on the same file as STM32L0
  • Single matching pattern for GPIOx.LCKR.LCK[0-15] and GPIOx.BRR.BR[0-15]
  • Apply GPIOx.BRR patch to STM32G0 and STM32L0 and STM32L5

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github-actions bot commented Apr 9, 2022

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@larchuto larchuto changed the title GPIOx cleanup and improvement WIP: GPIOx cleanup and improvement Apr 12, 2022
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Please, rebase your branch on master.

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larchuto commented Apr 21, 2022 •
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New modifications :

  • STM32WL is handled in a single file (removing gpio_wl_with_brr.yaml)
  • Separation of gpio peripheral styles into 3 dedicated folders: v1, v2 and v3. v1 correspond to the F1 style and v3 to the G0, L0 and L5 style (it is basically the same as v2 but ST changed some names).
  • gpio_go_l0 and gpio_l5 now share some code. This as the effect of slightly modifying the GPIOx.MODER.MODE* fields (removing the "(reset state)" mention, which carries information already given in the resetValue field).

@larchuto larchuto changed the title WIP: GPIOx cleanup and improvement GPIOx cleanup and improvement Apr 21, 2022
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It may be better to put the v1,v2,v3 stuff into a separate PR ?

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@adamgreig or @newAM, would you possibly have some spare time to review this ?

larchuto added 7 commits May 27, 2022 15:47
@larchuto
remove useless space
3d7a267
@larchuto
use coma separated pattern to match against GPIOx.LCKR.LCKx fields
2ce456c
@larchuto
use coma separated pattern to match against GPIOx.BRR.BRx fields
050d73f
@larchuto
use a single file for STM32WL gpio
2e3b443 
gpio_wl_with_brr.yaml is removed and its content is moved into
gpio_wl.yaml
@larchuto
use "v1" to refer to STM32F1 family gpio style
2d8df16
@larchuto
move gpio v2 related stuff into dedicated folder
f0fa47f
@larchuto
use "v3" to refer to STM32GO,L0 and L5 families gpio style
2500848 
This allows to do some factorisation between STM32G0 and L0 on one side
and STM32L5 on the other.

Note: v3 is basically the same as v2 but ST seems to have decided to
change some names starting from STM32L0.
@larchuto larchuto force-pushed the dev/gpio_cleanup branch from 8549c41 to 2500848 Compare May 27, 2022 13:53
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I just rebased it on top of master and resolved conflicts.

newAM
newAM previously approved these changes May 28, 2022
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Thanks for the pull-request!

This looks good to me; I will wait for another person to review because there are a lot of changes here.

burrbull
burrbull reviewed May 28, 2022
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@larchuto
use numeric range instead of list
a1b7ff3 
change is done to:
- GPIOx.BRR.BRx match patterns
- GPIOx.LCKR.LCKx match patterns
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newAM
newAM approved these changes May 30, 2022
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Checked the generated output, overall much less code; 10107 insertions(+), 16189 deletions(-); lots more variants alias each other. That's really great because GPIOs take the longest to compile because they have the largest volume of code.

bors r+

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bors bot commented May 30, 2022

Build succeeded:

@bors bors bot merged commit 1d4a1c5 into stm32-rs:master May 30, 2022
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@larchuto @burrbull @newAM