Several projects have developed compiler tools that translate high-level languages down to hardwa... more Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
ACM Transactions on Design Automation of Electronic Systems, 2006
The Cameron Project has developed a system for compiling codes written in a high-level language c... more The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, since the area on an FPGA is limited, the compiler needs to know the effect of compiler optimizations on the FPGA area; this information is typically not available until after the synthesis and place and route stage, which can take hours. In this article, we present a compile-time area estimation technique to guide SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique predicts the area required for a design to within 2.5% of actual for small image processing operators and to within 5.0% for larger benchmarks. The estimation time is in the order of milli...
This paper presents the high level, machine independent, algorithmic, single-assignment programmi... more This paper presents the high level, machine independent, algorithmic, single-assignment programming language SA-C and its optimizing compiler targeting reconfigurable systems. SA-C is intended for Image Processing applications. Language features are introduced and discussed. The intermediate forms DDCF, DFG and AHA, used in the optimization and code-generation phases, are described. Conventional and reconfigurable system specific optimizations are introduced. The code generation
This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and th... more This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and the mapping of the DFGs to reconfigurable systems.
and conclusions or recommendations expressed in this material are those of the author(s) and do n... more and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the DoD. **DRAFT** This report outlines an approach to formal modelling and reasoning about security of multi-partition execution environments (MPS). Several different models of MPS are pre-sented, starting with a simple two-partition system where the partitions are completely isolated from one another to a full n-partition system, where specific partitions are permit-ted to interact with other partitions under given constraints. Examples of real-world systems that could be modelled by these MPSes are provided. The formal models of selected systems are implemented in the ACL2 system [KMM00] and theorems are proven regarding the se-curity of the models. For these selected systems, models have been generated of the example systems as well and the integrating of the examples with the models and security proofs is demonstrated. This culmination of this wor...
This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and th... more This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and the mapping of the DFGs to reconfigurable systems.
Several projects have developed compiler tools that translate high-level languages down to hardwa... more Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
Several projects have developed compiler tools that translate high-level languages down to hardwa... more Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
This paper presents a high-level language for expressing image processing algorithms, and an opti... more This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient ...
This report outlines an approach to formal modelling and reasoning about security of multi-partit... more This report outlines an approach to formal modelling and reasoning about security of multi-partition execution environments (MPS). Several different models of MPS are presented, starting with a simple two-partition system where the partitions are completely isolated from one another to a full n-partition system, where specific partitions are permitted to interact with other partitions under given constraints. Examples of real-world systems that could be modelled by these MPSes are provided. The formal models of selected systems are implemented in the ACL2 system [KMM00] and theorems are proven regarding the security of the models. For these selected systems, models have been generated of the example systems as well and the integrating of the examples with the models and security proofs is demonstrated. This culmination of this work is the presentation of a system security model based on the concept of software firewalls built on top of an n-partition MPS. This document can be used as a reference for those wishing to build and verify secure multi-partition execution environments.
This paper describes a process of dual certification for software that meets both FAA safety requ... more This paper describes a process of dual certification for software that meets both FAA safety requirements and NIST/NSA security requirements. The commercial avionics industry depends on RTCA DO-178B, for software assurance while security products are evaluated according to the Common Criteria. The two sets of requirements from DO-178B and the Common Criteria are assessed for similarity of function with non-corresponding parts identified. Each certification process is outlined and a merged certification procedure is presented.
This paper describes a process of dual certification for software that meets both FAA safety requ... more This paper describes a process of dual certification for software that meets both FAA safety requirements and NIST/NSA security requirements. The commercial avionics industry depends on RTCA DO-178B, for software assurance while security products are evaluated according to the Common Criteria. The two sets of requirements from DO-178B and the Common Criteria are assessed for similarity of function with non-corresponding parts identified. Each certification process is outlined and a merged certification procedure is presented.
Abstract. This paper presents the high level, machine independent, algorithmic, single-assignment... more Abstract. This paper presents the high level, machine independent, algorithmic, single-assignment pro-gramming language SA-C and its optimizing compiler targeting reconfigurable systems. SA-C is intended for Image Processing applications. Language features are introduced ...
This paper presents a high level, machine independent, algorithmic, single-assignment programming... more This paper presents a high level, machine independent, algorithmic, single-assignment programming language SA-C and its optimizing compiler targeting reconfigurable systems, and intended for Image Processing applications. Language features are introduced and discussed. The intermediate forms DDCF and DFG, used in the optimization and code-generation phases are described. Conventional and reconfigurable system specific optimizations are briefly introduced. The code generation process,
ACM Transactions on Design Automation of Electronic Systems, 2006
The Cameron Project has developed a system for compiling codes written in a high-level language c... more The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, since the area on an FPGA is limited, the compiler needs to know the effect of compiler optimizations on the FPGA area; this information is typically not available until after the synthesis and place and route stage, which can take hours. In this article, we present a compile-time area estimation technique to guide SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique predicts the area required for a design to within 2.5% of actual for small image processing operators and to within 5.0% for larger benchmarks. The estimation time is in the order of milliseconds, compared with minutes for the synthesis tool.
Several projects have developed compiler tools that translate high-level languages down to hardwa... more Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
ACM Transactions on Design Automation of Electronic Systems, 2006
The Cameron Project has developed a system for compiling codes written in a high-level language c... more The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, since the area on an FPGA is limited, the compiler needs to know the effect of compiler optimizations on the FPGA area; this information is typically not available until after the synthesis and place and route stage, which can take hours. In this article, we present a compile-time area estimation technique to guide SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique predicts the area required for a design to within 2.5% of actual for small image processing operators and to within 5.0% for larger benchmarks. The estimation time is in the order of milli...
This paper presents the high level, machine independent, algorithmic, single-assignment programmi... more This paper presents the high level, machine independent, algorithmic, single-assignment programming language SA-C and its optimizing compiler targeting reconfigurable systems. SA-C is intended for Image Processing applications. Language features are introduced and discussed. The intermediate forms DDCF, DFG and AHA, used in the optimization and code-generation phases, are described. Conventional and reconfigurable system specific optimizations are introduced. The code generation
This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and th... more This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and the mapping of the DFGs to reconfigurable systems.
and conclusions or recommendations expressed in this material are those of the author(s) and do n... more and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the DoD. **DRAFT** This report outlines an approach to formal modelling and reasoning about security of multi-partition execution environments (MPS). Several different models of MPS are pre-sented, starting with a simple two-partition system where the partitions are completely isolated from one another to a full n-partition system, where specific partitions are permit-ted to interact with other partitions under given constraints. Examples of real-world systems that could be modelled by these MPSes are provided. The formal models of selected systems are implemented in the ACL2 system [KMM00] and theorems are proven regarding the se-curity of the models. For these selected systems, models have been generated of the example systems as well and the integrating of the examples with the models and security proofs is demonstrated. This culmination of this wor...
This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and th... more This paper introduces SA-C, its optimizing compiler that generates dataflow graphs (DFGs), and the mapping of the DFGs to reconfigurable systems.
Several projects have developed compiler tools that translate high-level languages down to hardwa... more Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
Several projects have developed compiler tools that translate high-level languages down to hardwa... more Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
This paper presents a high-level language for expressing image processing algorithms, and an opti... more This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient ...
This report outlines an approach to formal modelling and reasoning about security of multi-partit... more This report outlines an approach to formal modelling and reasoning about security of multi-partition execution environments (MPS). Several different models of MPS are presented, starting with a simple two-partition system where the partitions are completely isolated from one another to a full n-partition system, where specific partitions are permitted to interact with other partitions under given constraints. Examples of real-world systems that could be modelled by these MPSes are provided. The formal models of selected systems are implemented in the ACL2 system [KMM00] and theorems are proven regarding the security of the models. For these selected systems, models have been generated of the example systems as well and the integrating of the examples with the models and security proofs is demonstrated. This culmination of this work is the presentation of a system security model based on the concept of software firewalls built on top of an n-partition MPS. This document can be used as a reference for those wishing to build and verify secure multi-partition execution environments.
This paper describes a process of dual certification for software that meets both FAA safety requ... more This paper describes a process of dual certification for software that meets both FAA safety requirements and NIST/NSA security requirements. The commercial avionics industry depends on RTCA DO-178B, for software assurance while security products are evaluated according to the Common Criteria. The two sets of requirements from DO-178B and the Common Criteria are assessed for similarity of function with non-corresponding parts identified. Each certification process is outlined and a merged certification procedure is presented.
This paper describes a process of dual certification for software that meets both FAA safety requ... more This paper describes a process of dual certification for software that meets both FAA safety requirements and NIST/NSA security requirements. The commercial avionics industry depends on RTCA DO-178B, for software assurance while security products are evaluated according to the Common Criteria. The two sets of requirements from DO-178B and the Common Criteria are assessed for similarity of function with non-corresponding parts identified. Each certification process is outlined and a merged certification procedure is presented.
Abstract. This paper presents the high level, machine independent, algorithmic, single-assignment... more Abstract. This paper presents the high level, machine independent, algorithmic, single-assignment pro-gramming language SA-C and its optimizing compiler targeting reconfigurable systems. SA-C is intended for Image Processing applications. Language features are introduced ...
This paper presents a high level, machine independent, algorithmic, single-assignment programming... more This paper presents a high level, machine independent, algorithmic, single-assignment programming language SA-C and its optimizing compiler targeting reconfigurable systems, and intended for Image Processing applications. Language features are introduced and discussed. The intermediate forms DDCF and DFG, used in the optimization and code-generation phases are described. Conventional and reconfigurable system specific optimizations are briefly introduced. The code generation process,
ACM Transactions on Design Automation of Electronic Systems, 2006
The Cameron Project has developed a system for compiling codes written in a high-level language c... more The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, since the area on an FPGA is limited, the compiler needs to know the effect of compiler optimizations on the FPGA area; this information is typically not available until after the synthesis and place and route stage, which can take hours. In this article, we present a compile-time area estimation technique to guide SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique predicts the area required for a design to within 2.5% of actual for small image processing operators and to within 5.0% for larger benchmarks. The estimation time is in the order of milliseconds, compared with minutes for the synthesis tool.
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Papers by Bob Rinker