Papers by Rita Rooyackers
Meeting Abstracts, Apr 29, 2015
These authors contributed equally to this work.
Proceedings of Spie the International Society For Optical Engineering, Mar 1, 2008
Multiple Gate Field Effect Transistors (MuGFETs) have been proposed to enable downsizing, when sc... more Multiple Gate Field Effect Transistors (MuGFETs) have been proposed to enable downsizing, when scaling the transistors to the 32nm technology node. The dimension of the gate on the surface of fin determines the effective channel length of the device. So, the characterization of the gate profiles at fin sidewalls becomes extremely critical. It is especially important to quantify the rounded intersection (etch residual) at the intersection of the fin and gate. In this report, we show top down images of a MuGFET taken with critical-dimension scanning electron microscopy (CD-SEM) and the results that were measured and characterized by measuring various portions of the pattern which will impact the MuGFET performance i.e. gate length, fin width. We will introduce a quantified relation between fin length and "its effect on the etch residue at the intersection of fin and gate". Next we discuss our approaches to analyze the variation of the shape of the gate at the fin sidewall.
Crystal Growth & Design, 2015
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Metrology, Inspection, and Process Control for Microlithography XXIII, 2009
In the previous study, we reported on the CD measurement of multi gate field effect transistors (... more In the previous study, we reported on the CD measurement of multi gate field effect transistors (MuGFETs) by using CD-SEM. We focused on the etching residue at the fin-gate intersection, which causes gate length variation and affects the device performance. Therefore we proposed a technique to quantify the amount of etching residues from CD-SEM top-down images. The increment of the
ECS Transactions, 2009
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ECS Transactions, 2008
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Metrology, Inspection, and Process Control for Microlithography XXII, 2008
Multiple Gate Field Effect Transistors (MuGFETs) have been proposed to enable downsizing, when sc... more Multiple Gate Field Effect Transistors (MuGFETs) have been proposed to enable downsizing, when scaling the transistors to the 32nm technology node. The dimension of the gate on the surface of fin determines the effective channel length of the device. So, the characterization of the gate profiles at fin sidewalls becomes extremely critical. It is especially important to quantify the rounded
ECS Transactions, 2009
ABSTRACT We report a comprehensive evaluation and overview of the latest developments and technol... more ABSTRACT We report a comprehensive evaluation and overview of the latest developments and technology challenges of FinFET-based devices. They offer improved electrostatics and steeper sub-threshold slopes, attractive for enabling further CMOS scaling, but can also suffer from higher parasitic resistance and parasitic capacitance for narrow Fin devices. Critical solutions to minimize the impact of the latter are here addressed, demonstrating their viability for replacing planar CMOS devices. Multiple-VT CMOS can be achieved with capping technology, with aggressively scaled Ring Oscillators (RO) and SRAM cells showing excellent performance and matching behavior.
Journal of Applied Physics, 2014
ABSTRACT Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there... more ABSTRACT Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET.
Journal of Applied Physics, 2014
ABSTRACT Band-to-band tunneling parameters of strained indirect bandgap materials are not well-kn... more ABSTRACT Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k·p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transistors are made by simulations with the calibrated model.
Technical Digest - International Electron Devices Meeting, IEDM, 2008
The ESD performance of gated FinFET diodes and multi-gate NMOS devices in both active MOS-diode a... more The ESD performance of gated FinFET diodes and multi-gate NMOS devices in both active MOS-diode and parasitic-bipolar mode are investigated, highlighting the impact of strained SiN layers. Strain improves the ESD robustness up to 30% in multi-fin FinFETs. A different failure mechanism is discovered in strained NMOS FinFETs for the parasitic-bipolar mode.
ECS Transactions, 2007
Temperature Influences on FinFETs with Undoped Body. [ECS Meeting Abstracts 701, 733 (2007)]. Mar... more Temperature Influences on FinFETs with Undoped Body. [ECS Meeting Abstracts 701, 733 (2007)]. Marcelo A. Pavanello, Joao Antonio A. Martino, Eddy Simoen, Rita Rooyackers, Nadine Collaert, Cor Claeys.
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005., 2005
Abstract This paper discusses experimental characterization of the gate-to-channel capacitance an... more Abstract This paper discusses experimental characterization of the gate-to-channel capacitance and the effective mobility in two types of FinFET structures: 1) with poly-Si/SiO 2 and 2) TaN/high-k dielectric gate stacks. Surprisingly, these two systems exhibit the same common features in terms of mobility and capacitance behavior of narrow-fin devices vs. quasi-planar wide-fin devices in spite of their rather different fabrication processes. Specific features revealed in effective capacitance and mobility behaviors of narrow-fin devices are ...
ECS Transactions, 2008
ABSTRACT FinFET is a promising device concept towards the 32 nm CMOS technology node and beyond a... more ABSTRACT FinFET is a promising device concept towards the 32 nm CMOS technology node and beyond as it combines the benefits of multi-gated architecture, intrinsically having superior scaling behavior, with a highly manufacturable process. The present paper will deal with material aspects of the SOI FinFET integration. We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. The effect of gate stack conformality on device performance is studied. The use of ion implantation for extension and the selective epitaxial growth of Si to achieve larger contact area on the source/drain areas are discussed from a materials perspective.
IEEE Transactions on Electron Devices, 2014
ABSTRACT The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approa... more ABSTRACT The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby a dummy source is replaced at the end of the process flow by the final source material to form an heterojunction. We show that the source can be successfully replaced while maintaining the gate dielectric integrity in the gate-source overlap (GS-OL) region and selectively to the exposed materials. Due to the in situ-doped epitaxial-grown source and the low thermal budget, this integration scheme leads to the formation of a highly doped source and an abrupt tunnel heterojunction and allows the integration of complementary devices. Electrical characterization of the devices shows performance improvement over their SiGe-source heterojunction and Si homojunction vertical TFET counterparts. Temperature dependence indicates that the subthreshold region of the devices is degraded due to trap-assisted tunneling (TAT). Band-to-band tunneling (BTBT) contribution is, however, revealed at low temperature (78 K) with a minimum point slope of ~50 mV/decade. The impact on performance of different device parameters is assessed. The amount of GS-OL or crystalline Ge (c-Ge) thickness in the source does not affect the device characteristics owing to the fact that the devices are dominated by point tunneling. On the other hand, the thickness of the gate dielectric as well as the doping profile at the tunnel junction modifies the device performance. The gate-drain underlap is shown to reduce the ambipolar behavior of the devices without affecting their ON-characteristics. Very low variability is measured for the ON-current in the devices where BTBT dominates, while variability increases in the TAT region.
Solid-State Electronics, 2011
This paper analyzes the influence of negative charges (NC) located at the gate edges on the advan... more This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gmmax, and analog figures of merit, such as transconductance over drain current ratio, Gm/ID, output conductance, GD, Early voltage, VEA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data ...
Solid-State Electronics, 2008
This work shows a comparison between the analog performance of standard and strained Si n-type tr... more This work shows a comparison between the analog performance of standard and strained Si n-type triplegate FinFETs with high-j dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.
Microelectronic Engineering, 2006
We present a new method to enlarge the process window for gate patterning on a surface with high ... more We present a new method to enlarge the process window for gate patterning on a surface with high topography. We have compared two approaches for the patterning of a poly-Si gate with oxide hard mask (HM) as used in multi-gate field effect transistors. In the first approach, referred to as 'direct deposition', a poly-Si layer of 60 nm is deposited on the substrate, whereas in the second, and new approach 200 nm poly-Si is deposited and anisotropically etched back to 60 nm. All subsequent process steps (i.e. HM deposition, lithography and gate etch) are identical. From ellipsometric thickness measurements, we conclude that for the etchback case the poly-Si film has a larger within-wafer-non-uniformity due to the deposition of a thicker film. On the other hand, top down and cross-section SEM after gate etch show that for the etchback approach there is a larger process window with respect to avoiding micro-masking by the oxide HM at topography steps. We demonstrate that less over-etch is needed during the HM opening step to achieve residue free patterning of the poly-Si film. For a poly-Si thickness of 100 nm, we were able to obtain a residue free gate etch process for both the direct deposition and the etchback approach. Electrical evaluation shows that device performance is not compromised when using the etchback approach.
IEEE Transactions on Electron Devices, 2000
ABSTRACT This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojuncti... more ABSTRACT This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-μm gate length device shows ON current in excess of 20 μA/μm at VGS = VDS = 1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.
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Papers by Rita Rooyackers