Low power Schmitt trigger circuit

zyxwvutsrqp zyxwvuts has one dominant pole at the output of the opamp. A folded cascode opamp has been used to ensure stability. With proper design of the loop parameters, wide frequency range of operation can be achieved. SIDROPOULOS, S., et al.: ‘A 700 Mbps/pin CMOS signaling interface using current integrating receivers’. Symp. on VLSI Circuits, Honolulu, Hawaii, USA, June 1996, pp. 142-143 DJEMOUAI, A,, et al.: ‘High performance integrated CMOS frequency to voltage converter’. ICM 1998, Berlin, Germany, 1998 MINEATIS, J., and HOROWTZ, M.: ‘Precise delay generation using coupled oscillations’, IEEE . I Solid-state Circuits, 1993, 28, (12) Low power Schmitt trigger circuit S.F. Al-Sarawi Three new Schmitt trigger circuits are described. The first circuit is a truly low power, while the second and third circuits are derived from the first circuit and provide smaller hysteresis width. Measurement results for the new Schmitt trigger circuits are presented. 21- 0 Introduction: In most published Schmitt trigger circuits [ 1-71 the aspect of low power operation is not considered, this being sometimes due to the methodology used in designing such circuits or because this aspect is irrelevant to the targeted application. Such circuits are suitable for medium power applications, but the emergence of applications which can be sustained for many years on the energy available from a small battery or from a rectified RF signal, means that truly low power circuits must be developed. All the designed circuits are simulated using HSPICE with level 28 model parameters for a 1.2 pm standard CMOS technology. zyxwvutsrqponm zyxwvutsrqpon zyxwvutsrqpon I I I I Low power prototype CMOS Schmitt trigger circuit: The prototype lower power Schmitt trigger circuit is shown in Fig. l a . The prototype circuit consists of six transistors arranged in a complementary CMOS structure. Fig. Ib and c represent two variants of the first type with less hysteresis width. 10- 0 I I I I zyxwvutsrq %, Conclusion: A novel approach based on a PWLL for the generation of a.50% duty cycle clock from an input clock with arbitrary duty cycle has been described. It can also be used to generate an output clock with duty cycles from 25 to 75%. The design has been shown to achieve this performance without affecting the jitter on one (sampling) edge of the input clock, which is very important for high-performance switched capacitor-based designs. zyxwvutsrq zyxwvutsrqponm zyx 414 Acknowledgments: The author would like to thank E. Soenen for providing the opporhmity to fabricate the design, K. Rao for the layout, and K. Nguyen for performing the measurements. 0 IEE 2002 Electronics Letters Online No: 20020657 Dol: IO. 1049/e1:20020657 28 May 2002 S. Karthikeyan (Texas Instruments, Inc, Dallas, Texas 75243, USA) References 1X on-chip clock generation with zero skew and 50% duty cycle’ US Patent No. 5,317,202 2 NAKAMURA, K., et al.: ‘A CMOS 50% duty cycle repeater using complementary phase blending’. Symp. on VLSI Circuits Dig. Tech. Papers, Honolulu, Hawaii, USA, 2000 1 WEIZMAN, A,: ‘Delay line loop for ELECTRONICS LETTERS 29th August 2002 Fig. 1 Three different Schmitt trigger circuits Number next to each transistor represents width to length ratio in microns a Prototype low power circuits b Circuit derived from a c Second circuit derived from a The operation of the prototype circuit can be understood as follows. When at first En is low, mn2 is OFF, mp2 is ON, which forces m n 3 to be ON, m p 3 OFF, and mp, ON. As the input voltage rises, the input voltage V,, at which the output switches from high to low then depends on the voltage at node V, and Vol. 38 No. 18 1009 zyxwvutsrqpon zyxwvut zyxwvutsrqponm zyxwvu zyx zyxwvutsrqp zyx switching point of the inverter structure which consists of mn2 and mp2. The result is where R = , / w i , bin corresponds to the transconductance of transistor type i and number n in the schematic diagram. To simplify the analysis vrh = I Vral= 1 Vr,,l,where Vt, corresponds to the threshold voltage of a transistor n. The voltage at V, can be found as a function of R, and can be written as 4iGDJ. where R, = Substituting (2) and Vi, = v h , in (I), we obtain (3) states the relation between the switching and supply voltage and the dependence of vhl on the nMOS transistors geometry. From (3) it is possible to cancel the threshold voltage effect on the hysteresis by making Pn = A . The hysteresis width of the fully synmetrical, low power Schmitt trigger circuit can be calculated by subtracting (4) from ( 3 ) and letting R, = Rp, resulting in Experimental work: The circuit shown in Fig. l a was fabricated in a 2 pm double poly, double metal standardp-well process through Orbit Semiconductor. The Schmitt trigger circuit was buffered with one inverter to drive the output node. The measured results using 3 V supply voltage are shown in Fig. 2. The designed switching points for the Schmitt trigger can be calculated using (3), (4) and (5) with R, = Rp = R = 1, resulting in Vhl= v d d / 3 , vlh = 2 v d d / 3 and V,, = Vdd/2.The measured switching point is slightly shifted from v d d / 2 due to the difference in the ratio of the mobility of the fabricated n and p MOS transistors from the values used in the design. Although, direct measurement of the current was not possible, simulations show the short circuit current behveen the supply rails during switching is very small (of the order of 200 nA) using the transistor sizes shown in the schematic diagram, resulting in low fanout. The fan-out of the Schmitt trigger circuit can be improved by buffering the output node and increasing the width of mn2, mp2, mn3 and mp3. Conclusion: Three new Schmitt trigger circuits have been discussed, with one type having low power characteristics. Measured results verified the principle of operation and the characteristics of this low power Schmitt trigger circuit. The circuit has been used in the design of low power, very low frequency integrator oscillators. 0 IEE 2002 Electronics Letters Online No: 20020687 DOI: 10.1049/el:20020687 22 November 2001 zyxwvu zyxwvutsrqponmlkji zyxwvutsrqponmlkjihg - zyxwvu S.F. Al-Sarawi (The Centre f o r High Performance Integrated Technology & Systems (CHiPTec), Department of Electrical and Electronic Engineering, Adelaide Universi& North Terrace, Adelaide 5005, Australia) 0.58 V .2 m5 1 58 aV DC 8 2 58 RV OC II c 163.22 ns lL I E-mail: alsarawi@eleceng.adelaide.edu.au DC 2.48 V 1 DC 2.48 V a References 1 2 3 E.58 V 4 5 6 7 .2 p1s 1 58 nV DC fi 2 50 RV oc NAGARAJ, M., and SATYAM, K.: ‘Novel CMOS Schmitt trigger’, Electron. Lett., September 1981, 17, (19), pp. 693-694 STEYAERT,M., and SANSEN, W.: ‘Novel CMOS Schmitt trigger’, Electron. Lett., February 1986, 22, (4), pp. 203-205 DOKIC, B.L., ILISKOVIC, A.J., and BLJNDALO, Z,V: ‘CMOS gates with regenerative action at one of the inputs’. Microelectron. 1, May-June 1988, 19, (3), pp. 17-20 ENNING, 8.: ‘A novel Schmitt-trigger circuit with GaAs MESFETs’, Frequenz, May 1990,44, (S), pp. 155-157 PFISTER, A,: ‘Novel CMOS Schmitt trigger with controllable hysteresis’, Electron. Lett., March 1992, 28, (7), pp. 639-641 IBM. CMOS Schmitt trigger buffer. IBM Tech. Discl. Bull. August 1986, 29, (3), pp. 1353-1354. DOKIC, B.L.: ‘CMOS NAND and NOR Schmitt circuits’, Microelectron. 1,November 1996, 27, (8), pp. 757-765 +- 163.22 RS a A 1 DC 2.48 V 1 DC 2.48 V b Fig. 2 Measured characteristics of fabricated low power Schmitt trigger circuit at 3 V supply voltage and input-output characteristics against time a Measured characteristics b Input-output characteristics Efficient implementation of lifting-based discrete wavelet transform Hongyu Liao, M.K. Mandal and B.F. Cockburn recursive architecture for implementing the lifting-based discrete wavelet transform is proposed. Processing of the transform stages is interleaved, improving the hardware utilisation and efficiency. A A similar analysis can be performed to find the switching voltage from low to high. The answer can, however, be obtained directly by subtracting Vhl from v d d which is given in (4) and introducing appropriate new definitions for the R and R, factors. v/h I010 = vdd Rp(R + 1) Rp(R+ 1) 1 - + Rp(2R - 1) - 1 Rp(R + 1) + 1 (4) Introduction: Factoring discrete wavelet transforms (DWT) into lifting steps can reduce ‘the computational coniplexity by up to 50% [l]. Several lifting-based architectures have been proposed. Andra et al. [2] proposed an architecture (ACT) that uses simple functional blocks. ELECTRONICS LETTERS 29th August 2002 Vol. 38 No. 18