Low Power Electronics

The current-mode instrumentation amplifier based on second-generation current conveyors (CCII) offers many benefits over conventional instrumentation amplifier architectures. It does not need any matched components to achieve high CMRR and its bandwidth is not gain-bandwidth product limited. Therefore, the wideband CMOS current conveyor has been used in this structure. HSPICE simulations have shown that its performance is quite satisfactory for wideband current-mode signal processing. Furthermore, different CMRR enhancement techniques of current-mode instrumentation amplifiers are discussed. The new simulated instrumentation amplifier provides approximately 40 dB of improvement on the high-frequency CMRR up to the 3-dB corner frequency and even higher. In addition, composite conveyor techniques improving the instrumentation amplifier performance are presented

Michitaka OKUNO †a) , Shinji NISHIMURA †b) , Members, Shin-ichi ISHIDA † †c) , Nonmember, and Hiroaki NISHI † †d) , Member SUMMARY A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all tablelookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10-to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.

A single-ISA heterogeneous multi-core architecture is a chip multiprocessor composed of cores of varying size, performance, and complexity. This paper demonstrates that this architecture can provide significantly higher performance in the same area than a conventional chip multiprocessor. It does so by matching the various jobs of a diverse workload to the various cores. This type of architecture covers a spectrum of workloads particularly well, providing high single-thread performance when thread parallelism is low, and high throughput when thread parallelism is high.

Abstract: Specification of a concurrent system using CAOS (Concurrent Action Oriented Specifications)(CAOS) as illustrated by Bluespec Inc.'s Bluespec System Verilog provides a high abstraction level, effective concurrency management through atomicity, and powerful compilation to efficient RTL hardware. In this paper, we present two algorithms that make CAOS to RTL synthesis power-aware and produce RTL that can be synthesized into hardware competitive in terms of power/area/slack trade-off against the well-known ...

In this paper, we explore and evaluate multicore processor architecture and floorplans in light of performance, power, and thermal issues. Cores-out-caches-inside and both interleaved and non-interleaved versions of cores-sandwichedbetween-caches approaches are considered, with 3 levels of cache memories and ring and bus-based interconnects.

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6 T) SRAM and proposes an alternative bitcell that functions to much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.

This work addresses the problem of low power design in high-level synthesis in the scenario of the resources operating at multiple voltages. The problem of resource-and-latency constrained scheduling is tackled and a novel methodology for scheduling as well as design space exploration is proposed. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal parallelism of power hungry operators in resource-constrained/time-constrained designs. A novel scheme is devised for recognizing the ''zones'' of parallel operators that result in maximal power savings when rescheduled to lower voltages. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in Oðn 2 Þ; where n is the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resourceand-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3-5% of the integer-linear-programming based (i.e., exponential-timecomplexity) method. The details and the analysis of the results on the standard high-level synthesis benchmarks are provided. Further, analysis of schedules is given for considering generation of control signals for switching the resources. This is the first work to consider such analysis besides proposing an efficient algorithm. r

A new design methodology is presented for outputting digital information from asynchronous analogue circuits, which allows signed frequency encoded signal transfer along a single channel. The circuit outputs data as a series of rate and pulse-width encoded spikes: pulsewidth modulation is used to represent vector and pulse frequency modulation is used to represent magnitude symbiotically. This technique can be used to increase the bandwidth of multiplexed neural signals, such as for address event registration, or by using a time-tofirst-spike system, to multiplex signals on a single channel. Additionally, feedback has been used to improve the switching speed of current starved inverters, reducing their power consumption by over an order of magnitude.

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8X over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5X. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7X using a 200 mV swing.

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Wireless distributed microsensor systems will enable fault tolerant monitoring and control of a variety of applications. Due to the large number of microsensor nodes that may be deployed and the long required system lifetimes, replacing the battery is not an option. Sensor systems must utilize the minimal possible energy while operating over a wide range of operating scenarios. This paper presents an overview of the key technologies required for low-energy distributed microsensors. These include power aware computation/communication component technology, low-energy signaling and networking, system partitioning considering computation and communication trade-offs, and a power aware software infrastructure.

This paper presents a new low-power test-data-compression scheme based on linear feedback shift register (LFSR) reseeding. A drawback of compression schemes based on LFSR reseeding is that the unspecified bits are filled with random values, which results in a large number of transitions during scan-in, thereby causing high-power dissipation. A new encoding scheme that can be used in conjunction with any LFSR-reseeding scheme to significantly reduce test power and even further reduce test storage is presented. The proposed encoding scheme acts as the second stage of compression after LFSR reseeding. It accomplishes two goals. First, it reduces the number of transitions in the scan chains (by filling the unspecified bits in a different manner). Second, it reduces the number of specified bits that need to be generated via LFSR reseeding. Experimental results indicate that the proposed method significantly reduces test power and in most cases provides greater test-data compression than LFSR reseeding alone.

We have assessed the use of commercial silicon-onsapphire CMOS electronics in control circuits, which could be used to interface with quantum bits at low temperatures. We have characterized n-type MOSFETs, p-type MOSFETs, and an n + -diffusion resistor at 300 K and 4.2 K and extended these studies into the millikelvin regime. Our measurements of dc responses at 300 K, 4.2 K, and subkelvin and transient responses at 300 K and 4.2 K show that these devices favorably operate at low temperatures with minor changes to their 300-K characteristics and no appreciable change to their operating speed. Our results indicate that control circuits based on commercial CMOS devices may successfully be operated at low temperatures for the control and readout of quantum bits.

Design of power-efficient and highspeed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.

The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is shown that, while the doped extension region adjacent to the S/D Schottky barrier (SB) improves drive current by shrinking the SB, it is fundamentally limited by its dual role as a heavily doped S/D contact region to improve drive current and as a more lightly doped S/D extension region to reduce BTBT leakage. This restricts the design space for meeting low-standby-power leakage specifications, and so, the RSD structure ends up prevailing both in terms of leakage design space and ON-state performance. For highperformance (HP) design, where the higher leakage specification permits heavier extension doping, the performances of optimized DSS and RSD MOSFETs are shown to be very similar. Thus, the optimal S/D design for HP is more likely to be decided by practical considerations such as process integration.

This article presents the design of a novel quadband LNA operating in the GSM 0.9GHz/GSM l.8GHz and ZigBee 0.9GHz/WLAN 2.4GHz communication standards. This pseudo-concurrent architecture uses a two bit mode switch for selecting between the frequency bands. An RF switch is implemented before the Low Noise Amplifier (LNA) module to improve the insertion loss and isolation between the frequency bands. The pseudo-concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. The current design is especially suitable for use in multi-standard wireless receiver frontends as it saves die area and reduces power consumption by replacing parallel LNAs for each channel frequency. Simulation results indicate a Noise Figure below 4dB and S 21 above 14 dB in all frequency bands while drawing 10mA current from a 1.2V power supply.

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.

A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and predicts energy consumption to within 3% accuracy for a set of benchmark programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors. The tool, JouleTrack, is available as an online resource and has various estimation levels. It also isolates the switching and leakage components of the energy consumption.

Sustaining Moore's Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore's Law will continue at least through early next decade. By combining silicon innovations with other novel nanotechnologies on the same Si platform, it is expected that Moore's Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotube field-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications.

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59 • with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84 • , DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81 • , DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59 • with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

This paper presents an adaptive grid-voltage sensorless control scheme for inverter-based distributed generation units based on an adaptive grid-interfacing model. An adaptive gridinterfacing model is proposed to estimate, in real time, the interfacing parameters seen by the inverter and the grid-voltage vector simultaneously. A reliable solution to the present nonlinear estimation problem is presented by combining a grid-voltage estimator with an interfacing parameter estimator in a parallel structure. Both estimators adjust the grid-interfacing model in a manner that minimizes the current error between the grid model and the actual current dynamics, which acts as a reference model. The estimated quantities are utilized within the inner high-bandwidth current control loop and the outer power controller to realize an adaptive grid-voltage sensorless interfacing scheme. Theoretical analysis and simulation results are provided to demonstrate the validity and usefulness of the proposed interfacing scheme.

This paper presents a standalone closed loop wireless power transmission system that is built around a commercial off-the-shelf (COTS) radio frequency identification (RFID) transceiver (MLX90121) operating at 13.56 MHz. It can be used for inductively powering implantable biomedical devices in a closed loop fashion. Any changes in the distance and misalignment between transmitter and receiver coils in near-field wireless power transmission can cause a significant change in the received power, which can cause either malfunction or excessive heat dissipation. RFID transceivers are often used open loop. However, their back telemetry capability can be utilized to stabilize the received voltage on the implant. Our measurements showed that the delivered power to the transponder was maintained at 1.48 mW over a range of 6 to 12 cm, while the transmitter power consumption changed from 0.3 W to 1.21 W. The closed loop system can also oppose voltage variations as a result of sudden changes in load current.

This paper proposes a new transistor topology to design gates required by Null Convention Logic for low voltage operation. The new topology enables implement all functionalities required by this design style. Extensive simulation results conducted in a 65 nm CMOS technology allow comparing the new topology to popular static and semi-static ones and indicate that the former presents better speed, energy and leakage trade-offs for different voltage levels, demonstrating the suitability of the new topology for low voltage applications. Drawbacks are an area of 4 minimum size transistors and reduced robustness against soft errors, when operating at non-minimum voltages.

We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands. The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (i.e., voltage has dropped below 1.3 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died. When powered by a battery, the current consumption is 700 nA at 1.5 V (400 nA if internal signals are not brought out on testpads). This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible. The chip is built on a 1m digital CMOS process with dual poly layers, EEPROM and Schottky diodes. The RF threshold power at 2.45 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 3.5 m under FCC unlicensed operation at the 2.4-GHz microwave band. The low threshold is achieved with architectural choices and low-power circuit design techniques. At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m. The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode. The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode. We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator. Other than the antenna board and a battery, no external components are used.

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I D DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

This paper presents a programmable digital finiteimpulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the lowcomplexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm 2 area.

The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device. I. Jian-Hsing Lee 303 7-1

The overall operation of a direct digital frequency synthesiser (DDFS) is based on a look-up table method, which performs functional mapping from phase to sine amplitude. The spectral purity of the conventional DDFS is determined by the resolution of the values stored in the sine table ROM. However, large ROM storage means higher power consumption, increased silicon area, lower reliability, lower speed and increased costs. A novel systematic design methodology for implementing a DDFS architecture with reduced memory size is introduced. Describing the proposed architecture using the hardware description language VHDL, it is possible to generate a plethora of alternative realisations in terms of the number of input and output bits, the memory size, the number of gates, the memory segmentation parameters and the spectral purity. In other words, the designer can perform extensive architecture exploration to reach an optimal solution. The experimental results prove that the new DDFS architecture can be realised with a smaller hardware complexity and total power consumption and improved performance compared to many existing approaches.

In this paper, we present a new sense amplifier based flip-flop that exploits input data activity, to achieve reduced power consumption. The internal nodes of the proposed flip-flop are charged/discharged only when the input data changes state. Simulations show that the power consumption of proposed flip-flop is reduced by 20% to 70% compared to standard sense-amplifier flip-flop. An FIR-filter based on the proposed flip-flop, implemented in 45nm ST process, shows more than 42% improvement in power consumption (with 5% delay penalty) compared standard sense-amplifier flip-flops.

As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today's SRAM design from perspectives of both process technology optimization and design innovation. Key process tradeoff and optimization along with the advanced circuit design techniques for power management and low-voltage operation are discussed.

The out-of-order issue queue (IQ), used in modern superscalar processors is a considerable source of energy dissipation. We consider design alternatives that result in significant reductions in the power dissipation of the IQ (by as much as 75%) through the use of comparators that dissipate energy mainly on a tag match, 0-B encoding of operands to imply the presence of bytes with all zeros and, bitline segmentation. Our results are validated by the execution of SPEC 95 benchmarks on a true hardware level, cycle-by-cycle simulator for a superscalar processor and SPICE measurements for actual layouts of the IQ in a 0.18-m CMOS process.

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

A dual-mode direct-conversion transceiver integrates the transmitter of 0dBm output power and the receiver for both Bluetooth with -87dBm sensitivity and 802.11b with -86dBm sensitivity in a single chip with all building blocks shared for low cost and low power solution. Fabricated in 0.25µm CMOS process, die size is 8.4mm 2 including pads and current consumption in RX is 50mA for Bluetooth and 65mA for 802.11b.

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low-and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of 15 dB or greater at a bit-error rate of 10 15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.

The impact of hot-carrier injection (HCI) due to repetitive unclamped inductive switching (UIS) on the electrical performance of low voltage trench power nMOSFETs is assessed. Trench power nMOSFETs in TO-220 packages have been fabricated and subjected to over 100 million cycles of repetitive UIS with different avalanche currents (I AV ) at a mounting base temperature (T MB ) of 150 °C. Impact ionization during avalanche conduction in the channel causes hot-hole injection into the gate dielectric which results in a reduction of the threshold voltage (V GSTX ) as the number of avalanche cycles (N) increase. The experimental data reveals a power law relationship between the change in threshold voltage (ΔV GSTX ) and N. The results show that the power law pre-factor is directly proportional to the avalanche current. After 100 million cycles, it was observed that the power law pre-factor increased by 30% when the I AV was increased from 160 A to 225 A thereby approximating a linear relationship. Stable subthreshold slope with avalanche cycling indicates that interface trap generation is not an active degradation mechanism. The impact of the cell pitch on avalanche ruggedness is also investigated by testing 2.5 µm and 4 µm cell pitch 30 V rated MOSFETs. Measurements showed that the power law pre-factor reduced by 40% when the cell pitch was reduced by 37.5%. The improved V GSTX stability with the smaller cell pitch MOSFETs is attributed to a lower avalanche current per unit cell resulting in less hot-hole injection and hence, smaller V GSTX shift. The 2.5 µm cell pitch MOSFETs also show 25% improved on-state resistance (R DSON ), better R DSON stability and 20% less subthreshold slope compared to the 4 µm cell pitch MOSFETs however with 100% higher initial I DSS and less I DSS stability with avalanche cycling. These results are important for manufacturers of automotive MOSFETs where multiple avalanche occurrences over the lifetime of the MOSFET are expected.

The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 m 2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures.

There are many applications that use low power wireless sensors to monitor people's vital signs or the environment around people. For mobile applications, smartphones with Internet access have become a commonly used tool to make this data remotely accessible. However, the yet presented architectures are quite complex and lack flexibility. Our aim was to investigate how existing communication architectures for smartphone/WPAN sensor ensembles can be simplified and to provide a transparent solution where the smartphone doesn't require knowledge about sensors for which it serves as an Internet gateway. We therefore present an IP-based communication architecture, that allows applications to easily integrate remote sensor data of mobile users based on existing Internet standards. In particular, our solution provides simple Web service-based APIs and does not require the smartphone to process sensor data. Instead, the smartphone becomes a transparent gateway as it only forwards IP packets.

Many circuits are subject to excessive heating such as digital and power switching circuits. Overheating may cause permanent damage to the circuits and devices. In this article we present a temperature monitor the temperature variation and once a certain limit is reached, a protection mechanism could shut off the circuit operation or at least signalize for a specific operation. The circuit offers linear operation from -25 ºC to +120ºC, and it can be adjusted to detect any temperature in that range. The proposed circuit was developed for low voltage and low power operation, and the prototyped was designed in TSMC 0.35um technology.

This article presents a resonant DC-DC converter suitable for ultra-low power and low voltage sources. This original topology allows a self-starting and a self-operation under harsh conditions of input voltage and power without any additional start-up assistance. A global theoretical modeling of the converter which includes start-up and steady-state phases is presented and a methodology for optimal design is detailed. It is based on the combination of both theoretical calculations and circuit simulations. Experimental tests based on discrete prototypes are carried out in order to demonstrate the good operation of the converter. Experimental tests have been achieved using an RF energy harvesting source. Ultra-low power and low voltage conditions as low as 3µW and 100mV respectively can be achieved as demonstrated by the experimental measurements. The input low voltage is stepped-up to a conventional level of some volts, what allows to power autonomously and solely low power circuits from energy harvesting sources.

Power consumption is one of the main design challenges in very-low-voltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in low-voltage fastsettling operational amplifiers for switched-capacitor applications are discussed. These techniques include the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-mm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers. r

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 mm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/1C (after individual resistor trimming) for the À20 to +80 1C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V. r

Due to the quadratic reduction in the switching power dissipation, lowering supply voltage is obviously one of the most e ective ways to reduce p ower consumption. However, the performance will degrade. In order to satisfy the high performance r equirements, threshold voltage has to be s c aled. Unfortunately, such scaling leads to a dramatic increase in leakage current, which becomes a new concern for low voltage and high performance circuit designs. Multiple transistor threshold and supply voltages can be used to achieve low power and high performance while maintaining low leakage current. In this tutorial, di erent multiple-V th , multiple-V dd and standby leakage control techniques are presented.

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.