Mosfet en Detalle

[ 3 ] Power MOSFET in Detail

1. Part Number Format (transistors and accessories)
1.1
Transistors
(example)
2SK
1st
2232
2nd
A
3rd
1st group: transistor types are indicated as shown in the table immediately below.
1st character group 2SJ 2SK
Type P-channel field effect transistor N-channel field effect transistor
2nd group: serial numbers starting at 11 (JEITA) 3rd group: suffix indicating changes (alphabetical order)
1.2
Multipin Transistors
TPC 8 0 01 A Suffix indicating changes Serial numbers starting at 00 0: N-ch 1 chip 3: P-ch 2 chip SOP-8 Series TPCS 8001A TSSOP-8 Series TPC 6001A VS-6 Series TPCF 8 0 0 1 VS-8 Series TPCA 8001 SOP Advance Series 1: P-ch 1 chip 4: N-ch/P-ch 2 chip 2: N-ch 2 chip A: MOSFET/SBD chip
1.3
Accessories
(example)
AC 23
1st 2nd
A
3rd
1st group: AC.... accessory 2nd group: serial numbers 3rd group: suffix indicating changes
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2.
Construction and Characteristics

Since Power MOSFETs operate principally as majority carrier devices, adverse influences are relatively small magnitude or importance. This is in contrast to the situation with minority carrier devices, bipolar transistors, where such effects create more serious design problems. Also, the input impedance of power MOSFETs is basically higher than that of junction type FETs. Even though the power MOSFETs have high speed, at the beginning of their development it was thought to be difficult to make devices characterized by low resistance, high breakdown voltage and high power. However, in recent years power MOSFETs from 60 V/70 A to 1000 V/12 A become available and are widely used as ideal switching devices.
2.1
Power MOSFET Construction

Power MOSFETs are classified into three major types as shown in Figure 2.1. Figure 2.1 (a) shows a type of construction which is an extension of the small-signal MOSFET and with which high breakdown voltage is obtained using ion junction technology and the offset gate construction. However, this approach is disadvantageous from the viewpoint of the long channel required and the consequent loss in efficiency of surface area utilization. Figure 2.1 (b) shows the product of a method called D-MOS (double diffusion MOS) which is used to form the channels by using double diffusion. High breakdown voltage can be obtained by using this technology. This D-MOS construction uses double diffusion on a high-resistance drain substrate, which diffuses the gate area and the source area. The difference in depth of diffusion between the gate and the source area is used as the channel. When the gate-drain junction is formed in this way, there are fewer impurities on the drain side. When drain voltage is applied, the depletion area extends considerably to the drain side but cannot easily extend to the channel side; therefore, breakdown voltage drop due to punch-through is prevented, and this structure makes possible high breakdown voltage even with an extremely short channel. D-MOS takes the drain electrode from the back surface of the substrate, achieving high integration and high power. In addition, the cascade connection of a power MOSFET and a junction FET makes it possible to reduce the reverse transfer capacitance of the power MOSFET.
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High breakdown voltage and large current are easier to achieve with this D-MOS construction than with the former two methods Figure 2.1 (a) and (c). Mass production at low cost is also possible; therefore, the technique portrayed in Figure 2.1 (b) is now widely used as the basic construction for power MOSFETs for ordinary power amplification applications. Figure 2.1 (c) is the trench power MOSFET structure. High-integration is achieved by connecting channel vertically and this structure is capable of low ON-resistance. Low-voltage power MOSFETs use this structure. (a) Lateral construction (b) Double diffusion construction (c) Trench construction
Gate
Source Source Gate Drain P n+ n+ P n+ n+
Gate
Source
P n
n+ P
n+
n+ P n n+ Drain
n+ Drain
Figure 2.1
Power MOSFET Construction
2.2
Power MOSFET Features

Main features of power MOSFETs are shown as follows: a) b) MOS type FETs are basically majority carrier devices; consequently, they differ greatly from bipolar transistors which are minority carrier devices. MOS type FETs are not current controlled devices as are bipolar transistors. They are voltage controlled devices and are controlled by the voltage applied between the gate and source. c) d) Since they are majority carrier devices, high-frequency switching operation is possible because there is no storage time-lag due to the carrier storage effect. With bipolar transistors, current concentration occurs in the high-voltage area and junction failure occurs due to secondary breakdown. Therefore, bipolar transistors require considerable derating. Power MOSFETs, on the other hand, have a negative temperature coefficient which makes it difficult for secondary breakdown to occur, making these devices highly resistant to failure and thus enabling use right up to the maximum rating. e) When power MOSFETs are used for switching operations, their switching times, that is, the rise and fall times, of power MOSFETs are one order of magnitude faster than those of bipolar transistors; therefore, turn-ON and turn-OFF loss are much smaller than those of bipolar transistors. Incidentally, the ON resistance of power MOSFETs has a positive temperature coefficient; therefore, heat sink and thermal expansion design is necessary, taking into consideration the RDS (ON) at high temperatures. Table 2.1 shows a comparison between bipolar transistor and MOSFET as to drive method, switching time, safe operation area, breakdown voltage, ON voltage, parallel connection and temperature stability.
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Table 2.1 Comparison between Bipolar Power Transistors and Power MOSFETs
Bipolar Power Transistor Power MOSFET
C Symbol B G E
Products in use Product cost
Very numerous Construction is relatively simple, an advantage in the long term. Fairly complex due to current drive. Also it influences switching time and makes selection of drive conditions difficult. Minority carrier device, therefore slow. Restricted due to risk of secondary breakdown. Determined by VCEX (VCBO) for most circuits. Rating is 1.2 to 2.0 VCE. Extremely low, even for high breakdown voltage devices. Temperature coefficient is normally negative. Difficult due to current balance relationship. hFE rises and VBE falls along with temperature rise, so some caution is required.
Growing rapidly Construction is more complex than that of bipolar transistors. This and the slightly larger chip size increases cost. Voltage drive, so extremely simple. Load current and safe operation range are unrelated. Much faster than bipolar transistors. No storage time and no influence from temperature. Basically restricted by power dissipation (equal power lines). Limited by VDSS except when the gate of a trench-structure MOSFET is inversely biased with VGS (limited by VDSX) Can be extremely low for low breakdown voltage devices, but is somewhat higher for high breakdown voltage devices. Positive temperature coefficient. Some caution required, including equalization of oscillation or switching time, but parallel connection is possible. Extremely high stability in relation to the temperatures of various parts.
Drive
Switching time Safe operation area Breakdown voltage (collector-emitter, drain-source) ON voltage
Parallel connection
Temperature stability
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3.
Maximum Ratings
3.1
Definition
The maximum current, voltage, and allowable power dissipation are specified as maximum ratings for power MOSFETs. When designing a circuit, it is very important to understand the maximum ratings to ensure the most effective operation and reliability of the power MOSFETs for the required period of time. The maximum ratings are the values which must not be exceeded to ensure the power MOSFETs life and reliability. Note that the maximum ratings mean the absolute maximum ratings. The absolute maximum ratings are the values which must never be exceeded during operation even for a moment. If the maximum ratings are exceeded, some characteristics may be deteriorated in an unrecoverable manner. Therefore, pay much attention to fluctuations of supply voltage, characteristics of electrical components, ambient temperature, and input voltage, as well as maximum rating violation during circuit adjustment so that no maximum rating value is exceeded. Parameters that must be specified for the maximum ratings include current for power MOSFETs drain, voltage between each pair of pins, power dissipation, channel temperature, and storage temperature. These parameters cannot be considered individually since they are closely related to each other, and they are subject to change due to the circuits environmental conditions.
3.2
Voltage Ratings
3.2.1
Maximum Drain-Source Voltage Rating

There are four methods of specifying the drain-source breakdown voltage of a power MOSFET in accordance with gate-source bias conditions. Figure 3.1 shows the various drain-source breakdown voltage modes. (1) VDSS: the drain-source voltage with zero gate-source bias (the last S means short). (2) VDSX: the drain-source voltage with reverse bias (for example, when a voltage of VGS = 3 V is applied with an N-channel MOSFET). (3) VDSR: the drain-source voltage with resistance shunted between the gate and source (the R means shunt resistance).
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When a Power MOSFET, except a trench type MOSFET, is the enhanced type, the relationship VDSS VDSX is established in the above three breakdown voltage modes. In addition, there is almost no difference in breakdown voltage from the VDSX mode, even when the drain-source breakdown voltage (VDSR mode) is measured with a large resistance inserted between the gate and source, and the relationship VDSS VDSX VDSR is established. For a trench type MOSFET, the relationship VDSS > VDSX is established because breakdown = voltage at VDSX mode fall depending on applied voltage to gate-source. Consequently, there is no method for regulating a drain-source breakdown voltage larger than the VDSS value, which is therefore used as the maximum rating. Thus, caution must be exercised to avoid exceeding the VDSS value, even instantaneously. (4) VDSO: drain-source voltage with the gate open The input impedance of a power MOSFET is extremely high; therefore, bias is applied between the gate and source by static electricity inductance, etc., and the device is destructed because of malfunction. Avoid use in this mode. (a) VDSS mode (b) VDSX mode (c) VDSR mode (d) VDSO mode The device can sometimes fail
D G S VGS G
D G S R
D G S
Figure 3.1
Drain-Source Breakdown Voltage
3.2.2
Maximum Gate-Source Voltage Rating

VGSS: the gate-source voltage when the drain and source are shorted, which is determined by the degree of withstand of the gate oxide film. The maximum rating for a MOSFET should be based on the side of the maximum sustainable practical voltage or, in consideration of reliability.
3.3
Current Ratings
For power MOSFETs, the DC current that flows in the forward direction is referred to as ID and the pulse current that flows is referred to as IDP. The values of the reverse-direction (diode direction) DC current (IDR) and pulse current (IDRP) are defined as the same as the corresponding currents flowing in the forward direction under the ideal heat radiation condition. The forward-direction DC and pulse currents are subject to the effects of the power loss caused by drain-source ON-resistance. The reverse-direction currents are subject to the effects of power dissipation caused by the diodes forward voltage. Hence, current ratings are determined by the heat radiation conditions; the channel temperature maximum rating value (Tch) must not exceed 150C.
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3.4
Temperature Ratings
Maximum channel temperature Tch is defined according to the constituent material and reliability requirements. It must be considered not only in terms of device operation, but also in conjunction with such factors as allowable
(%/1000 h) Defect rate
0.6 0.4 0.3 0.2 0.15 0.1 0.08 0.06 0.04 0.03 0.02 0.015 0.01 0.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0 Silicon NPN Silicon PNP
degradation and minimum service life. Degradation of power MOSFETs generally accelerates as the channel temperature increases. The following relationship is known to exist between the mean service life Lm (hours) and channel temperature Tch (K) og Lm A +
B .........................................(1) Tj
Where A and B are constants inherent to power MOSFETs For a power MOSFET required to have a long-term guaranteed service life, the upper limit of the allowable channel temperature is defined according to the power MOSFET defect rate and reliability. Generally, the channel temperature is below 150C. Storage temperature Tstg is the temperature range within which non-operating power MOSFETs can be safely stored. This rating is
Junction temperature Ta normalized by reference temperature To
Ta =
Tj To Tjmax To
Figure 3.2 Relationship between Lifespan and Junction Temperature of Bipolar Transistor (source: MIL-HDBK-217A)
also defined by the power MOSFETs constituent material and reliability. Figure 3.2 shows a typical relationship between the lifespan and junction temperature of a bipolar transistor.
3.5
Power Ratings
The power dissipation in a power MOSFET is converted into thermal energy which in turn causes the power MOSFET internal temperature to rise. Internal power dissipation of a power MOSFET operating at a certain point is represented by the equation PD = (IDVDS). The primary parameters limiting maximum power dissipation PDmax in a power MOSFET are maximum channel temperature Tchmax, described above, and reference temperature To (ambient temperature Ta or case temperature Tc). These parameters are known to be correlated by thermal resistance (or Rth).
T To PDmax = chmax ....................................................................... (2)
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Thermal resistance represents the ratio at which the channel temperature increases per unit amount of power dissipation. That is, it is a physical quantity that indicates a difficulty in radiating heat. To allow for large power dissipation, therefore, it is necessary to choose a power MOSFET with a large PDmax. Knowing how to design for heat radiation in power MOSFETs is especially important. The rated value of PDmax is normally defined with respect to Ta = 25C, or with respect to Tc = 25C when the use of a heat sink is anticipated. In either case, Equation (2) can be used to determine thermal resistance between a power MOSFET channel and the external air or between the channel and the case.
3.6
Safe Operating Area
3.6.1
Forward Bias Safe Operating Area (SOA)

Because current concentration does not readily occur in power MOSFETs due to their structure, in principle, unlike in bipolar transistors, secondary breakdown does not occur in the high-voltage area. Thus, for power MOSFETs the safe operating area (SOA) can be expressed by a constant-power line which is limited by thermal resistance with pulse width as a parameter (Figure 3.3). The device can be safely operated over a very wide range within the breakdown voltage between the drain and source without narrowing the high-voltage area in the SOA. Along with the higher precision of cells developed, some power MOSFETs exhibit a phenomenon similar to secondary breakdown. The safe operating areas of these power MOSFETS are defined individually. Figure 3.4 shows the safe operating areas which are different from the typical safe opeating areas limited by the constant-power lines as shown in Figure 3.3.
Safe Operating Area

100 50 30 ID max (pulsed)* ID max (continuous) 1 ms* 100 s* 10 100
Safe Operating Area

ID max (pulsed)*
1 ms*
(A)
10 5 3
ID
Drain current
Drain current
DC operation (Tc = 25C)
ID
10 ms*
(A)
10 ms*
1 0.5 0.3 *: Single pulse Tc = 25C Curves must be derated linearly with increase in temperature. 0.1 0.1 0.3 1 3 10 VDSS max 30 100
0.1
*: Single pulse Ta = 25C Curves must be derated linearly with increase in temperature.
VDSS max 1 10 100
0.01 0.01
0.1
Drain-source voltage
VDS (V)
VDS (V)
Figure 3.3 Power MOSFET Safe Operating Area (2SK2782)
Figure 3.4
Power MOSFET Safe Operating Area (TPC8009-H)
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3.6.2 Reverse Bias Safe Operating Area
When a switching device is used in the field of power switching for applications such as switching power supplies, the load becomes inductive. In this case, both the forward and reverse safe operation ranges become a problem. Normally, when bipolar transistors are
IC (A)
6 VCEX (sus) mode L (coil) = 200 H IB1 = 2 A IB2 = variable Duty < 1% =
(a) Reverse safe operating area
used in switching power supplies, forced reverse bias is applied between the base and emitter to reduce switching loss, base reverse current IB2 is applied, and tstg and tf are shortened. However, if IB2 is increased, the reverse bias safe operating area becomes narrow, as shown in Figure 3.5, and the load curve operation range is restricted during turn OFF. With power MOSFETs, on the other hand, tf and toff can be shortened by applying reverse bias between the gate and source. However, since power MOSFETs are majority carrier devices
5 IB2 = 1 A 2 A 4 The reverse safe operating area of power MOSFETs 3 does not become narrower with VGS as is the case with bipolar transistors. 2 Power MOSFET reverse safe operating area (for the 2SK2610) Measurement conditions: L = 200 H VGS = 15 V 200 400 600 800 3 A
Collector current
0 0
VCEX (sus) (V)
Figure 3.5
Reverse Safe Operating Area
and there is essentially no carrier storage effect, the reverse bias SOA does not become narrow even if gate reverse voltage VGS increases. (However, breakdown voltage for trench type power MOSFET falls depending on an applied VG; hence, reverse bias SOA becomes narrow.)
L
(A)
VDS P.G. ZDi Di
VDD
Drain current
D.U.T.
ID
ID
VDSS = VZ
VDS
Figure 3.6
Measurement Circuit for Reverse Safe Operating Area
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3.7
Derating
When designing power MOSFET circuits, you determine the appropriate heat radiation condition from the absolute maximum ratings (maximum ratings) listed in the technical datasheets to ensure that the parameters-voltage, current and power (channel temperature)-are each within the maximum rating. However, it is a common practice to derate these maximum values in consideration of reliability requirements prior to using them in a circuit design. To balance maximum ratings against reliability and economy, the following derating methods are generally recommended: Voltage: The worst-case voltage (including surge) must be no greater than 80% of the maximum rated voltage. Current: The worst-case current (including surge) must be no greater than 80% of the maximum rated current. Power: The worst-case power (including surge) must be no greater than 50% of the derated maximum power dissipation at the maximum ambient temperature of the equipment in which the device is used. Temperature: The maximum operating channel temperature Tch (including surge) must be 70% to no greater of the 80% of the Tchmax. The power dissipation of power MOSFETs used in switching circuits must be such that the peak values (including surges) of voltage, current, power and channel temperature do not exceed the absolute maximum ratings (maximum rating). However, when using these power MOSFETs under derated conditions, with respect to reliability, power dissipation can be considered in terms of average values. Safe operating areas before and after derating are expressed as the formulas shown in Figure 3.7.
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100 1
y = cx
(A)
10
ID
y = cdTx
dT b
Drain current
y = ax b
y = adTx
bd T
0.1 0.1 1 10 100
VDS (V)
Figure 3.7
Temperature Derating in Safe Operating Range
The derating ratio dT of the constant-power line is expressed by using the following definition equation: Ta T PD = chmax .................................................................................... (3) rth (ch a )
as follows: dT = PD(Tch C ) PD(25C ) T Tch = chmax ............................................................... (4) Tchmax 25
When Tch = 25C, the constant-power line is:
y = cx 1 ..................................................................................................... (5) The constant-power line after derating is: y = cd T x 1 ................................................................................................ (6) When the line limited by the phenomenon similar to secondary breakdown at Tch = 25C is: y = ax b .................................................................................................... (7) The derating ratio and the equation after derating are expressed as follows: d PS/B = b d T ............................................................................................ (8) y = ad T x b ............................................................................................... (9)
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<Example of derating (TPC8108)> Using TPC8108 as an example, derate the safe operating area from Ta (= Tch) = 25C to Ta = 125C. Read the coordinates of the points marked with a circle (o) in the safe operating area (in the individual technical data) at Ta = 25C. Substitute the read coordinates for the values in equations (3) and (5). The constant-power lines are calculated as follows: y = 470x 1 (Ta = 25C, t = 1 ms) ............ (8) y = 76.2x 1 (Ta = 25C, t = 10 ms) .......... (9) Lines limited by the phenomenon similar to secondary breakdown are calculated as follows: y = 1500x 1.73 y = 282x dT = 0.2. Constant-power lines at Ta = 125C are calculated as follows: y = 407x 1 = 81.4x 1 y = 76.2x
1 1.73
0.1 0.1 100
ID max (pulse) 1 ms
(A) Drain current ID
10
10 ms
1
VDSS max
1 10 100
VDS
(V)
Figure 3.8
TPC8108 Safe Operating Area (Ta = 25C)
(Ta = 25C, t = 1 ms) ................. (10) (Ta = 25C, t = 10 ms) ............... (11)
When derating from Ta = 25C to Ta = 125C, the derating ratio dT of the constant-power line is
(Ta = 125C, t = 1 ms) ............... (8) (Ta = 125C, t = 10 ms) ............. (9) (Ta = 125C, t = 1 ms) ............... (10) (Ta = 125C, t = 10 ms) ............. (11)
= 15.2x
Lines limited by the phenomenon similar to secondary breakdown are calculated as follows: y = 1500d x 1.73 = 300x 1.73 y = 282d x
1.73
= 56.4x
1.73
Figure 3.9 shows the safe operating area plotted using equations from (8) to (10).
(A)
100
ID max (pulse)
10
ID
1 ms 10 ms
1
Drain current
0.1 0.1
VDSS max
1 10 100
VDS (V)
Figure 3.9
TPC8108 Safe Operating Area (Ta = 125C)
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4.
Electrical Characteristics
4.1
Terminology
The following is an explanation of main items used to evaluate power MOSFET performance. (1) |Yfs|: forward transfer admittance |Yfs| = ID/VGS |Yfs| expresses power MOSFET amplification factor (2) Vth: gate threshold voltage If VGS (OFF) is the gate-source voltage in the cut-off state, and VGS (ON) is the gate-source bias voltage when drain current is flowing, then the following relationship can be established. VGS (OFF) < Vth < VGS (ON) (3) RDS (ON): drain-source ON resistance This is the equivalent of the collector-emitter saturation voltage VCE (sat) of a bipolar transistor, and is used as a criterion for determining dissipation in the ON status. (4) VDS (ON): drain-source ON voltage This is a criterion for determining dissipation in the ON status, as with RDS (ON), and is expressed as a voltage value. (5) Ciss, Crss, Coss: capacitances Ciss, Crss and Coss are input capacitance, reverse transfer capacitance and output capacitance, respectively. These capacitances restrict the usable frequency and switching speed when a power MOSFET is used for switching operations. The index = |Yfs|/Ciss (s1) is the equivalent of the cutoff frequency fT of a bipolar transistor. However, normally the following expression is used to define the theoretical cutoff frequency: f (max) = |Yfs|/2 {Ciss + (1 + Av) Crss}
4.2
Power MOSFET Temperature Characteristics

The transfer function of power MOSFETs is shown by the differential coefficient of the ID VGS curves shown in Figure 4.1. In the large current area, the temperature coefficient of the transfer function is negative, therefore, the forward transfer admittance |Yfs| decreases when the internal (channel) temperature increases; so current concentration and failure due to thermal run-away dont occur easily even if a large drain current flows due to the output fluctuates. Caution must be exercised concerning the temperature dependence of the drain-source ON resistance. This ON resistance approximately doubles for a temperature increase of 100C (Figure 4.2). Thus, it is necessary to account for an induced temperature increase to select a heat sink with an appropiate thermal resistance f.
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12 14 12 10 8 6 4 2 0 1 Common source VDS = 10 V

55
25
(V)
70 Tc = 100C
Common source 10 VGS = 10 V 15
VDS (ON)
(A)
8 12 6 10
ID
Drain-source on voltage
Drain current
4 5 2 ID = 1 A 0 60
40 20
10
20
40
60
80
100
Gate-source voltage VGS
(V)
Case temperature
Tc
(C)
Figure 4.1
ID VGS Characteristics
Figure 4.2
VDS (ON) Tc Characteristics
4.3
Power MOSFET Electrostatic Capacitance Characteristics

The physical construction of a power MOSFET is such that the gate is completely isolated from the silicon oxide film; therefore, the capacitances between the drain, gate and source terminals are as shown in Figure 4.3 (a). Gate-drain capacitance Cgd and gate-source capacitance Cgs are determined by the gate electrode construction. In addition, drain-source capacitance Cds is determined by the junction capacitance of the PN junction based on the double diffusion construction. Input capacitance Ciss = Cgd + Cgs, output capacitance Coss Cds + Cgd, and reverse transfer capacitance Crss = Cgd are important characteristics for power MOSFETs. Figure 4.4 shows the dependence of Ciss, Crss and Coss on drain-source voltage VDS. (a) Power MOSFET capacitance (b) Simple equivalent circuit including parasitic devices
rg Gate Cgd Gate (G) Cgs Cds r1 Cgs gmVG r3 r2 Cds Crss = Cgd Drain
Drain (D)
Source (S)
Source
Input capacitance: Ciss = Cgd + Cgs Output capacitance: Coss = Cds + Cgd Reverse transfer: Crss = Cgd
rg: gate electrode parasitic resistance r1: equivalent resistance of the source and channel areas r2: equivalent resistance of the high resistance layer adjacent to the drain r3: modulated part of the channel resistance Input capacitance: Cin = Cgs + (1 + AV) Crss
Figure 4.3
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In the driving of a power MOSFET, the switching characteristics fluctuate due to the input capacitance Ciss and the drive circuit impedance. Since gate current flows between the capacitor, the lower the drive circuit impedance the faster the switching speed. Also, there is almost no temperature dependence of the capacitors (Ciss, Crss, Coss).
(pF)
10000 6000 4000 2000 1000 600 400 Coss 200 Common source 100 VGS = 0 60 f = 1 MHz 40 Tc = 25C 0.3 6 1 2 4 6 10 20 40 100 Crss
gate and source to charge the input
Ciss
4.4
Power MOSFET Switching Characteristics

Since power MOSFETs are majority carrier devices, switching performance
Capacitance
VDS (V)
Figure 4.4
Capacitance VDS Characteristics
is their main characteristic of interest. The switching speed of a power MOSFET is much faster than that of a bipolar transistor and its high-speed, high-frequency operation is outstanding. This characteristic is utilized in switching regulators (f = 1 kHz to 1 MHz) and in motor controls. As mentioned before, two important features of power MOSFETs are that they have no storage time dependence, and that their capacitance doesnt depend on temperature; therefore, their switching characteristics are not hardly influenced by temperature fluctuations. Figure 4.5 shows a typical switching time measurement circuit and input/output waveforms. (a) Measurement circuit
VDD RL Pulse generator RG 50 FB
(b) Input/output waveforms

Pulse width 90% Output VOUT Input Waveform 0 50% 10% 90% Output Waveform 10% 0 td (on) tr ton td (off) tf toff 10% 90% 50%
VIN
Figure 4.5
Switching Time Measurement Circuit and Input/Output Waveforms
50
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The definitions of the symbols used for input and output waveforms for switching time are explained below. (1) td (on): turn-ON delay time The charging time required to raise the voltage of input capacitance Ciss to the value of the threshold voltage Vth. (2) tr: rise time The charging time required to raise the gate-source voltage from the value of gate threshold voltage Vth to the specified VGS level. (3) td (off): turn-OFF delay time The discharge time required to lower the gate-source voltage from the drive voltage of the saturation area to the specified VGS level of the linear area. (4) tf: fall time The time required to lower the gate-source voltage from the level of the drive voltage of the saturation area to the value of the gate threshold voltage level Vth, and to raise the output voltage to the supply voltage level. As described above, the switching time can be divided into four different times. In addition, it should be noted that ton is expressed by adding the turn-ON delay time td (on) to the rise time tr, and that tOFF is expressed by adding the turn-OFF delay time td (off) to the fall time tf. td (on) + tr = ton td (off) + tf = toff Figure 4.6 shows the switching characteristics (switching time versus drain current ID).
1000 800 600 toff 400
10 V 0 10 s
Measurement ID Outcircuit put Input

50
(ns)
RL
Switching time
200
VDD Repetitive Duty < 0.5% =
100 80 60 40
tf ton tr
Common source VDD 200 V Tc = 25C
20 0.3
6 8 10
20
40
Drain current ID (A)
Figure 4.6
Switching Characteristics
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4.5
Gate Charge
4.5.1
Gate Charge Characteristics

Power MOSFETs are driven by a voltage applied between the gate and source, and the ease with which a power MOSFET can be driven is expressed by the size of the charge stored in the gate. td (on) is the time required for an input signal to be applied, the input capacitor to be charged through the signal and gate resistors, and the gate voltage VGS to exceed the threshold voltage. This is expressed as td (on) Cgs (rg + RG) Here RG is the signal resistance and rg is the gate electrode parasitic resistance. At td (on), the gate charge is expressed as Qgs (on) CgsVGS During the interval tr, the power MOSFET starts to operate; the input capacitance increases due to the mirror effect and tr becomes longer than td (on), as follows: tr {Cgs + (1 + AV) Crss} (rg + RG) During the tr interval, the gate charge increases by the amount of reverse transfer capacitance Crss, as follows: Qon {Cgs + (1 + AV) Crss}VG If the transient flow of gate charging current is iG (t), then the total charge Qtotal can be determined by using the following equation:
t Qtotal = 0 i G (t) dt
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4.5.2 Calculating the Total Gate Charge
When the power MOSFET is switched ON, the gate current iG (t) flows to charge the gate-source and gate-drain capacitors. To determine the total gate charge under the circuit conditions shown in Figure 4.7, consider allowing a small gate current of iG (t) = 1 mA (constant) to flow for 12 s and then stopping the flow of this gate current. (a) Total gate charge measurement circuit (b) iG (t), VGS (t), VDS (t) waveforms
Set VGG so that a certain drain current flows.
VDD = 200 V Driver FET
Gate Current iG (t) 0 ton = 12 s Gate-Source Voltage VGS (t)
1 mA
VG
VGG
VG VDS Constant-current power supply
200 V Drain-Source Voltage VDS (t) 0 Drain-Source ON Voltage VDS (on)
Figure 4.7
Total Gate Charge
The total gate-source charge Qtotal will be as follows: Qtotal = 0 on i G (t) dt From the constant current iG (t) = 1 mA, the gate current is determined as follows.
Also, if ton = 12 s = 12 10 6 s, then iG (t) = IG = 1 mA = 1 10 3 A t'
Qtotal = 0 on i G (t) dt = IG t'on

= 1 10 3 12 10 6 = 12 10 9 (C)
t'
This Qtotal indicates the charge required to switch the MOSFET ON.
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4.6
Source-Drain Diode
Due to their construction, double-diffusion-construction power MOSFETs have a parastic diode between the source and drain.
Drain reverse current IDR (A)
10 Common source T = 25C 8 D
The ratings for the forward current IDR (Figure 4.8) and the reverse breakdown voltage for this parastic diode are the same as for drain current ID and drain-source voltage VDSS for a power MOSFET under the ideal heat radiation condition. The reverse recovery time trr for this diode is similar to that for a Fast Recovery Diode (FRD). Figure 4.9 shows a reverse recovery time measurement circuit for the parastic diodes of power MOSFETs. (a) Reverse recovery time measurement circuit
G S
IDR
VGS = 3 V
1 0
1
0 0
0.2
0.4
0.6
0.8
1.0
1.2
VDS (V)
Figure 4.8
IDR VDS Characteristics
D.U.T. IDR L1
C1
Rg P.G. VGS
(b) Reverse recovery time (trr) and charge (Qrr)

+15 V VGS: 0 15 V
C2
IDR di/dt = 50 A/s VF Qrr 10% Irr Vrr IDR: 0
IDR: 0
*Qrr
1 trr Irr 2
trr
Figure 4.9
Reverse Recovery Time Measurement Circuit for the Parastic Diodes of Power MOSFETs
55
5.
Application Precautions
5.1
Precautions Concerning Drive Conditions for Shortening Switching Time

Bipolar transistors require a large base current to maintain the saturation area; however, power MOSFETs are voltage-controlled devices and can therefore be driven by merely applying a small power to the gate. However, since the input capacitance Ciss of power MOSFETs is somewhat high, it is necessary to quickly charge the input capacitor with low-impedance signal sources, especially for high-speed switching. Low-impedance drive is necessary to shorten the turn-ON time; however, the input capacitance Ciss is overcharged when the voltage applied is increased and, conversely, td (off) becomes longer. It is possible to turn OFF power MOSFETs by dropping the gate voltage to zero but, as with bipolar transistors, it is also possible to turn a Power MOSFET OFF quickly by reducing the value of the charge Q to zero. The charge Q which is built up by the gate-source and gate-drain voltage, will quickly fall to zero after applying a reverse bias between the gate and source voltage (ig = dQ/dt). Figure 5.1 shows the relationship between the magnitude of the reverse bias and the switching time. In the case of N-channel MOSFETs, it is possible to decrease the switching times tf and toff by using a negative power supply, that is, by configuring a low-impedance circuit. To operate power MOSFETs at high speed, it is necessary to add a speed-up circuit to increase the speed at which the
(ns)
1000 600 400
Test circuit IG waveform 10 s 5V 0 VG IG
VDD (= 200 V) 40 ID = 5 A Output
equivalent input capacitance between the gate and source is charged. Figure 5.2 shows a speed-up circuit.
200 toff 100 60 40 20 tf
Switching time
10
VG
(V)
Figure 5.1
Switching Time VG Characteristics
56

(a) Speed-up circuit
Speed-up circuit configured with C1, Q2, D1, and D2.
(b) Current path at rise

Current flows in the direction of the arrow when the power MOSFET is turned ON, instantaneously charging the input capacitor (Cin) Q1 D1 T1 R1
(c) Current path at fall

When the power MOSFET is turned OFF, the voltage accumulated in C1 is used to turn on Q2 and rapidly extract the charge between the gate and source. D1 Q1 R1 R2 R3 R4 D2 NS T3 NP
Q1
D1 T1 R3 R4 D2
R1
R2
NS
NP
R3 R4
NS
NP
C1
C1
D2
Figure 5.2
Gate Drive Speed-Up Circuit
5.2
The Influence of Wiring Inductance

Since the switching time for power MOSFETs is at least one order of magnitude faster than that of bipolar transistors, they are very effective in fields where high-speed switch is required. However, unless some countermeasure is taken in the circuitry, this high-speed switching characteristic may give rise to a voltage surge due to stray inductance LS, which is impressed on the MOSFET. The magnitude of this surge, Vsurge, is determined as follows: Vsurge = (LS + LS)di/dt + VDD It is necessary that this value be given sufficient margin in relation to drain-source breakdown voltage VDSS. To reduce this surge voltage, it is necessary to reduce either di/dt or the stray inductance; however, since the reduction of di/dt does not agree with the original purpose of high-speed switching, it is necessary to reduce the stray inductance. This can be done by using copper plates instead of wires, because copper has lower inductance. Inserting the capacitors shown in Figure 5.3 is also an effective way of reducing the magnitude of the generated voltage surge.
LS VDD LS
Figure 5.3
Circuit Stray Inductance
57
C1
Q2
R5
Q2
R5
5.3
Parasitic Oscillation
Parasitic oscillation is more prone to occur with power MOSFETs than with bipolar transistors. This is caused by the high-frequency gain which is characteristically high with power MOSFETs. Parasitic oscillation may occur when impedance became negative resistance for input which is caused by strong coupling of input and output depending on gate-drain capacitance and stray capacitance. The following methods can be used to avoid this situation.
Cs
Lower the gain by inserting a resistor.
Insert a ferrite bead.
Make the wires thick and short.
Figure 5.4
How to Prevent Parasitic Oscillation
(1) Make the wires thick and short. Twisted wires should be used not to connect the circuit to other wiring. (2) Insert a ferrite bead as close to the gate as possible. (3) Insert a series resistor at the gate.
5.4
Source-Drain Diode Withstand Capability

Normally, for motor control circuits, power MOSFETs are used in a bridge configuration in which the top and bottom power MOSFETs are turned ON and OFF alternately. Now, Q1 and Q4 of the power MOSFETs shown in Figure 5.5 are turned ON and the current flows as indicated by A. Next, when FET Q1 is turned OFF to control the motor speed, the current is fed back through the freewheeling diode of FET Q2, as indicated by B. If FET Q1 is again turned ON after that, a shorting current flows from FET Q1 to FET Q2 during the time (trr) until the freewheeling diode of FET Q2 reverse recovers, and heat is generated due to the resulting power dissipation. Thus, when a power MOSFET is used for motor control, the trr of the parasitic diode should be minimized. Basically, it is possible to use the parasitic diode of a power MOSFET as a freewheeling diode; however, depending on the usage conditions, it may be necessary to install an external diode, as shown in Figure 5.6.
58
Q1
Q3
M
Q2 B Q4
Figure 5.5
Motor Control Circuit Using Power MOSFET

D
SBD
FRD
Di R
Figure 5.6 External Diode Connection Method
Figure 5.7 Parasitic Transistor of a Power MOSFET
Also, in a power MOSFET, the equivalent of a parasitic bipolar transistor exists between drain and source (see Figure 5.7). Note that this parasitic transistor may be turned ON by the base-emitter resistor Rs voltage drop, during the transitional state while a power MOSFET switches from ON to OFF, and the device may break down. As illustrated in Figure 5.5, when using parasitic diodes between drain and source in motor control circuits, power supply circuits and illumination circuits, it is recommended to use high-breakdown-voltage devices (example: -MOS V series and similar).
Parasitic Diode Breakdown Voltage (for high-performance parasitic-diode type device)
Testing Circuit
600
*D.U.T. L1 C1 IDR
(A/s)
500 400 300 200 100 0
-MOS V (2SK2543) No destruction
-MOS V (2SK2543)
VDS = 200 V/div
VDD
di/dt
C2
VGS +15 V VCS = 0 15 V IDR = 0
Current type destruction
ID = 10 A/div di/dt = 500 A/s
100
200 300
VDD (V)
200 ns/div @IDR = 8 A
*: D.U.T. = Device under test
59
5.5
Avalanche Resistance
At turn-OFF in power MOSFETs used as high-speed switching devices, high surge voltage can occur between the drain and the source, caused by the inductance of the circuits themselves and by drifting inductance. This voltage can exceed the maximum ratings of the MOSFET. Previously, a surge absorption circuit was required to protect the MOSFET. Now, however, the reduction in the number of components and the miniaturization of equipment are creating a growing need to eliminate the absorption circuit and to absorb any surge in a power MOSFET even if it exceeds the maximum ratings. In response to this need, Toshiba has developed a product line of power MOSFETs usable up to the point of self-breakdown voltage. (1) Avalanche resistance guaranteed series The following series guarantees avalanche resistance.
Voltage
2
Series L --MOS V
16 to 200 V
-MOS V U-MOS I to IV
400 to 600 V 800 to 1000 V
-MOS V to VI -MOS III to IV
(2) Guarantee method The avalanche energy when Tch (max) reaches 150C is listed in the maximum ratings column of the individual product specifications. When using the product, check that the actual energy impinging on the device does not exceed its maximum rating. Use the following procedure to check. a) Calculate the channel temperature Tch (max) Calculate the total rise at avalanche in the channel temperature resulting from steady power loss and switching loss according to the following equations, and confirm that the maximum channel temperature value at avalanche doesnt exceed Tch (max) = 150C. A. For a single pulse: Tch = 0.473V (BR) DSSIARch-a in which V (BR) DSS: Breakdown voltage between drain and source IAR: Avalanche current ch-a: Thermal resistance from channel to ambient air at avalanche
60

B. For a continuous pulse: T T Tchpeak = P0 1 ch-a + 1 1 rth (T+ T1 ) rth (T ) + rth (T1 ) T T in which P0: Peak value T1: Pulse width T: Cycle ch-a : Thermal resistance from channel to ambient air Note 1: For details of how to calculate Tchpeak of the continuous pulse see 6, Heat Sink Design. b) Calculating avalanche energy EAS Check that the energy at avalanche during actual operation does not exceed the maximum rating, using the following equation:
1 E AS L I 2 AR 2 in which
V (BR ) DSS V (BR ) DSS VDD
EAS: Avalanche energy IAR: Avalanche current V (BR) DSS: Breakdown voltage between drain and source VDD: Power supply voltage Satisfying equations a) and b) above ensures that the device is used within its maximum ratings.
Avalanche Voltage
Test result
@L = 200 H, VDD = 90 V 2SK1352
Test circuit L
Test waveform 2SK2543
2SK2543
IO VDS VDD
VDS = 100 V/div
(A)
25 20 15 10 5 0 ID max
Peak avalanche current
ID = 2 A/div
Rg = 25
+15 V 15 V
5 s/div
61
5.6
Parallel Connections
Power MOSFETs have outstanding thermal stability and do not suffer thermal runaway; therefore, parallel connection of them is easier than that of bipolar transistors. Bipolar transistors are operated by the flow of base current; therefore, the current balance is disrupted by fluctuations of the base-emitter voltage VBE, making parallel connections difficult. Power MOSFETs, on the other hand, are voltage driven. Therefore it is only necessary to supply drive voltage to each FET connected in parallel, making parallel connections relatively easy. However, when controlling high power at high speeds, it is necessary to carefully consider selection of devices and the range of possible fluctuations in their characteristics. The most important things to remember when making parallel connections are to avoid current concentration, including overcurrent during the transitional state, and to assure a well balanced, uniform flow of current to all devices under all possible load conditions. Normally, current imbalance appears during switching ON and OFF; however, this is caused by differences in the switching times of the power MOSFETs. It is known that fluctuations in switching times are largely dependent on the value of the gate-source threshold voltage Vth. That is, the smaller the value of Vth the faster the switching ON; and the larger the value of Vth the slower the switching ON. Conversely, when turning OFF, the larger the value of Vth the faster the cutoff. Because of this, current imbalance occurs during both switching ON and OFF when the current concentrates in an FET with a small Vth. This current imbalance can apply an excessive load to a device and result in failure. Thus, when considering fluctuation in switching time during transition, it is preferable that the Vth values of all power MOSFETs connected in parallel should be the same.
Due to smaller Vth of Q1 than the Vth of Q2.
VDD
Circuit with symmetrical wiring is preferable. ID2 Q2 Input and output should be separated.
Q1
ID1
ID1 0 ID2 0
Figure 5.8
Imbalance of Current in Parallel Connection
62
6.
Heat Sink Design
6.1
Maximum Allowable Power Dissipation and Radiation Equivalent Circuits

When the circuit has been designed for fully adequate thermal stability, the maximum allowable power dissipation (PDmax) for power MOSFETs can be determined based on the power MOSFETs ambient (external) air temperature (Ta), the maximum temperature in the power MOSFETs channel section (Tchmax), and the total thermal resistance (ch-a, sometimes denoted as Rth) from the channel to ambient air, that is determined by the radiating condition described below, as shown in the following equation (1).
Ta Tc T T PDmax (Ta ) = chmax , PDmax (Tc ) = chmax ..................................... (1) ch-a ch-c With regard to the path by which thermal energy produced in the power MOSFETs channel section is transferred to the outside, we can think of such thermal transfer as similar to the conduction of electrical current except that the thermal conditions are expressed in terms of thermal resistance and thermal capacitance. Figure 6.1 shows a radiation equivalent circuit under normal thermal conditions.
Tch
i Tch
Tc
s b c f
i: Internal thermal resistance (from channel to case) b: External thermal resistance (from case direct to ambient air) s: Isolation plates thermal resistance c: Contact thermal resistance (at point of contact with heat sink)
Ta
Figure 6.1
Equivalent Circuit
f: Heat sinks thermal resistance (from the heat sink to ambient)
The total thermal resistance (ch-a) from channel to ambient air can be determined for the equivalent circuit shown in Figure 6.1 via equation (2) below.
ch-a = i +
b (s + c + f ) ................................................................................ (2) b + s + c + f
Because medium-output and low-output transistors generally do not use heat sinks, in such cases
ch-a is expressed as shown in equation (3) below. ch-a = i + b ....................................................................................................... (3)

In catalogs for medium-output and low-output transistors, the maximum allowable power dissipation is specified at Ta = 25C. However, when this power dissipation value is not specified, we can calculate it using the ch-a value from equation (3) and the Tchmax value, as shown below.
25 T PDmax (Ta = 25C ) = chmax ch-a

The thermal resistance b from the case to ambient air depends on the material and configuration of the case, but it is a considerably larger value than those of i, c, s and f. Therefore, expression (2) is simplified and the following expression can be used in practice.
ch-a = i + c + s + f.......................................................................................... (4)

In dealing with direct current dissipation, it is possible to realize a radiation design satisfying the maximum rating by finding expression (4). In using power MOSFETs in a pulse circuit or similarly fluctuating application, great care must be taken so that the peak value of Tch never exceeds Tchmax.
63
6.2
Pulse Response of Channel Temperature

In general, the thermal impedance of a power MOSFET is given by a distributed constant circuit as shown in Figure 6.2.
Tch (t) Rm m 1 Rm 1 n Rn 3 R3 2 1 R1
Pch (t) Ta
Cm
Cm 1
Cn
C3
C2
C1
Figure 6.2
Power MOSFET Thermal Impedance
If pulse loss Pch (t) shown in Figure 6.3 is added to the circuit shown in Figure 6.2, the thermal variation Tch (t)
Pch (t) T1 P0 T2
that occurs in the m-th CR parallel circuit under stable thermal conditions can be calculated as follows: (1) In areas where Pch (t) = P0, m Tch (t) = (P0Rn ) Tn (min ) n 1 {1 exp ( t/CnRn ) } + Tn (min ) ....................................(5)
0 Tch (t) Tch (max) (1) (2) Tch (av.) Tch (min) Ta
Time t
(2) In areas where Pch (t) = 0, m Tch (t ) = Tn (max ) exp ( t/Cn Rn ) .........................(6) n 1
T1
Time t
Figure 6.3 Temperature Change when Pulse Loss is Applied.
For ordinary power MOSFETs, we can approximate the actual value of Tch (t) by assuming that n = approximately 4, but it is difficult to determine the Tch value if the C and R values are not clear. Therefore, we generally estimate the Tchpeak using transient thermal resistance as described below. In Figure 6.4, the characteristics of the 2SK2698 are shown as a typical example of transient thermal resistance characteristics. When a single rectangular pulse (with pulse width T1 and peak value P0) is added to this circuit, we can determine the Tch peak by using the transient thermal resistance rth (T1) for the pulse width T1. The Tchpeak is expressed according to equation (7) below.
Tchpeak = rth (T1 ) P0 + Ta ................................................................................... (7) When continuous pulses of cycle T are added (as shown in Figure 6.3), the Tchpeak under stable thermal conditions can be determined as indicated in equation (8) below. T T Tchpeak = P0 1 ch-a + 1 1 rth (T+ T1 ) rth (T ) + rth (T1 ) + Ta ...................... (8) T When carrying out radiation design for pulse circuits, we must be careful so that the Tchpeak value shown in equation (8) does not exceed the power MOSFETs Tchmax value.
64
Transient thermal resistance (normalized) rth (t)/Rth (ch-c)
1 0.5 0.3
Duty = 0.5 0.2 0.1
0.1 0.05 0.03
0.05 0.02 0.01
PDM t
Single pulse Duty = t/T Rth (ch-c) = 0.833C/W 100 1m 10 m 100 m 1 10
0.01 0.005 0.003 10
Pulse width tw (s)
Figure 6.4
Transient Thermal Resistance (2SK2698)
The above analysis assumes that a rectangular wave is being applied. When using power MOSFETs in real equipment, in most cases the Pch (t) is not a rectangular wave. Usually in such cases the dissipation waveform approaches to a rectangular wave as shown in Figure 6.5, so that the Tchpeak value can still be obtained by using equation (8).
Actual Dissipation Waveform PD (t) Pp PD (t)
Approximate Waveform Pp T
T=
1 T1 PD (t ) dt Pp T1 '
T1
T1 T2
T2
Figure 6.5
Approximate Power Loss Waveform
Calculation Example
The data needed for the calculation are: the waveform of the voltage between the drain and source, the drain current waveform, the ambient temperature, the heat sink thermal resistance data, and the operating conditions. Based on the formula (8), this data can be used to calculate the channel temperature. If the calculated temperature is within the maximum rating (Tch (max) = 150C), the device can be used. The following is a calculation example based on a typical waveform obtained under continuous operation for a switching power supply for example.
65

< Typical Waveform> Device Used: 2SK2837 (no heat sink)
VDS waveform
ID waveform ON period tw Sw period tsw Cycle T
Note 2: PD = ID VDS
Using a rectangular approximation of the power loss (Note 2) of the above waveform, calculate the channel temperature by using formula (8). The loss waveform obtained from the above waveform and the rectangular approximation derived from the loss waveform are shown below.
(loss waveform) PD = 264 W (rectangular approximation) PD2 = 184.8 W T = 15 s PD = 22 W PD1 = 15.4 W
200 ns 450 ns T1 = 320 ns
T2 = 142 ns
Applying a regularly repeating rectangular wave like the one in Figure 6.3, the peak of the channel temperature rise can be calculated by using formula (8). However, as mentioned the above, if multiple rectangular waves are applied cyclically, the calculation formula must be used with a different model. In this model, repeating rectangular waves are treated as the sun of the average power dissipation and other two waves. Accordingly, in the case of the above rectangular wave, use the following type of approximation model to calculate the power loss.
T2
PD2 PD1 T
T1
Pav. =
1 1 0 (PD1 + PD2 ) dt = (T PD1 + T2PD2 ) 1 T T
66

Calculate as below; that is, consider that the repetitive waveforms for two cycles follow the average power loss Pav applied for an infinite period.
(5)
(9)
PD2
(1)
(3)
(7)
PD1 Pav.
(2) (4) (8)
Pav. PD1
(6)
PD2
Tch-a (peak ) = Pav. R th (ch-a ) Pav. rth (T + T1 + T2 ) + PD1 rth (T + T1 + T2 ) (1) (2) (3) PD1 rth (T + T2 ) + PD2 rth (T + T2 ) PD2 rth (T ) + PD1 rth (T1 + T2 ) (4) (5) (6) (7) PD1 rth (T2 ) + PD2 rth (T2 ) ..................................................................................... (9) (8) in formula (9). rth (t) value: Use the value derived from the transient thermal resistance graph included in the individual technical datasheet. Use the following formula to calculate the short pulse whose value is not included in the individual technical datasheet. rth (t ) = rth (1ms ) t/1ms Read the values from datasheet 2SK2837 and calculate a rise in the channel temperature. Tch-a (peak ) = Pav. R th (ch-a ) Pav. rth (T + T1 + T2 ) + PD1 rth (T + T1 + T2 ) PD1 rth (T + T2 ) + PD2 rth (T + T2 ) PD2 rth (T) + PD1 rth (T1 + T2 ) PD1 rth (T2 ) + PD2 rth (T2 ) 104C Pav. PD1 PD2 Rth (ch-a) rth (T + T2 ) rth (T) rth (T1 + T2 ) rth (T2 ) = 2.08 W = 15.4 W = 184.8 W = 50C/W = 0.0067C/W = 0.0066C/W = 0.0012C/W = 0.0006C/W (9) To calculate the channel temperature, the Rth (ch-a), rth (t) thermal resistances are required, as
rth (T + T1 + T2 ) = 0.0068C/W
At an ambient temperature of 25C, the peak channel temperature is: Tch-a (peak) 104 + 25 = 129C
67

The thermal resistance in the radiation equivalent circuit shown in Figure 6.1 is explained as follows: (1) Thermal resistance between channel and case (internal resistance) i Because the internal thermal resistance (i) between the channel and case is directly determined by factors such as the power MOSFETs structure and materials, methods of mounting the power MOSFET chip in its case, and kind of case filler materials, each power MOSFET has its own thermal resistance characteristics. To actually measure this value, the power MOSFETs case must be force-cooled to maintain a constant temperature. Assuming that the case is force-cooled to a constant 25C, the maximum allowable dissipation (PDmax) can be calculated as shown in equation (10) below. Tc chmax 25 = PDmax = chmax ........................................................... (10) i i
In catalogs for large-output power MOSFETs, the maximum allowable drain dissipation is given for a constant case temperature of 25C on the assumption of using infinite heat sinks. As was clearly demonstrated in equation (10), this value can also be based on the power MOSFETs internal thermal resistance value. (2) Contact thermal resistance (c) The contact thermal resistance (c) is determined by the condition of the contact surface between the power MOSFET case and the heat sink. This contact surface condition is greatly influenced by factors such as flatness, coarseness, contact area, and fastening method. For example, if silicon grease is applied to the contact surface, it can reduce the influence of factors such as surface flatness and coarseness. If the case is designed to be attached directly to the heat sink, such as in the TO-3 (L), TO-3P (N), and TO-220 types, to fasten a screw after applying silicon grease will reduce the contact thermal resistance to 0.5C per W. However, medium-output and low-output power MOSFETs are not designed to be attached directly to heat sinks, due to their smaller size and the costs of their fabrication. Therefore even though heat sinks are used for these smaller power MOSFETs, they have a relatively high contact thermal resistance in case of poor attachment to the heat sink.
6.3
Insulation Plates Thermal Resistance ( s)

In cases in which the power MOSFET must be insulated from the heat sink, we must insert an isolation material between the two. The thermal resistance (s) of this insulation barrier is determined by factors such as the type of insulation material and the materials surface area and thickness. Sometimes the thermal resistance value (s) can be appreciable, so it must not be ignored. Mica is the best type of insulation material in view of its high thermal transfer rate, and it can be used under high-temperature conditions. However, mica insulation material has disavantage in that it is fragile and difficult to fabricate in even thickness. Mylar is somewhat inferior to mica in terms of its thermal transfer rate, but it can be fabricated in thin plates of uniform thickness.
68

Table 6.1 Values of Thermal Resistance between Case and Heat Sink (c + s)
c + s [C/W]
Case
Insulation Plate
Silicon Grease Greased Ungreased 1.5 to 2.0 4.0 to 6.0 1.0 to 1.5 0.5 to 0.9 2.0 to 3.0 0.4 to 1.0 1.2 to 1.5
TO-220AB TO-220 (IS) (TO-3P) 2-16C1B (TO-3P (L)) 2-21F1B
No insulation plate Mica (50 to 100 ) No insulation plate No insulation plate Mica (50 to 100 ) No insulation plate Mica (50 to 100 )
0.3 to 0.5 2.0 to 2.5 0.4 to 0.6 0.1 to 0.2 0.5 to 0.8 0.1 to 0.2 0.5 to 0.7
6.4
30 2 mm steel plate
Heat Sink Thermal Resistance (f)

The thermal resistance of a heat sink can be thought of as the distributed constant thermal resistance along the path of thermal transfer from the surface of the heat sink to the ambient air. Although the thermal resistance is influenced by factors such as the ambient air conditions, the temperature difference between
(C/W)
10
1 mm steel plate
Thermal resistance
5 3
2 mm aluminum plate
1 mm copper plate 1 0.5 5 1 mm aluminum plate
the sink and the ambient air, and the heat sinks effective surface area, it is difficult to express these factors in a mathematical
1000
10
30
50
100
2
300 500
equation, and so the effects of these factors are currently determined by actual measurement. Figure 6.6 shows the thermal resistance values of a heat sink measured with one power MOSFET standing vertically at the center of the heat sink.
Heat sink area
(cm )
Figure 6.6 Heat Sink Area and Thermal Resistance (f)
Recently, manufacturers of heat sinks have announced various new heat sink models, and the above data may prove useful when putting these new models to practical use. For descriptions of accessories required for mounting power MOSFETs on heat sinks, and of the correct mounting method, please refer to Section 6, Accessories.
69
6.5
Attaching the Heat Sink

It is recommended to attach the heat sink in accordance with the following points. If these are ignored, for example if the heat sink has burrs, bumps or hollows, if its attachment profile is the wrong size, or if it is attached with the wrong torque, the device can be skewed, the pellet or resin can be damaged, or the adhesion between the resin and the frame can be weakened. (1) Heat sink The surface where the device is attached must be sufficiently smooth. Warps, large bumps or hollows in the surface, or foreign bodies such as punching burrs or chips lodged between the device and the attachment face can cause device failure in the worst case. To avoid these problems, the flatness of the surface where the device is attached should be within 50 m.
Within 50 m
(2) Attachment holes Intrusion resulting from punch processing around attachment holes should be no more than 50
m. The holes for attaching the device should be no larger than necessary. If intrusion does occur
around a hole or if the diameter of the hole is larger than normal, be sure to fit a square washer.
Intrusion
Heat sink
Burr
Protrusion
(3) Screws The screws to attach the device are generally classified as machine screws and tapping screws. If tapping screws are used, note that it is easy to exceed the maximum tightening torque. Also, avoid using special screws such as countersunk screws and round countersunk screws as these may place excessive stress on the device. (4) Insulating spacers Use mica or mechanically strong insulating spacers. (5) Insulating washers Use insulating washers that snugly fit the devices. (6) Grease Use Toshibas silicon YG6260 grease as this does not easily separate from its base oil and will not adversely affect the interior of the devices.
70

(7) Tightening torque Use torque values less than those shown in Table 6.2 to obtain good thermal resistance and to avoid applying stress to the device.
Table 6.2
Package JEDEC TO-220AB TO-220 (IS) TO-3P (N) TO-3P (NIS) TO-3P (L)
Package Mounting Torque Values

Screw Tightening Torque (max, Unit: N m) 0.6 0.6 0.8 0.6 0.8
Toshiba Name 2-10P1B 2-10L1B 2-10R1B 2-16C1B 2-16F1B 2-21F1B
Screws, insulation spacers and insulation washers are also available from Toshiba as accessories.
71
7.
7.1
Power Dissipation
Cautions About Drain Power Dissipation (constant state)

Power dissipation varies according to mounting conditions such as board sizes, materials and pad areas. Changes in drain power dissipation with respect to temperature for representative package types are described below.
7.1.1
PW-MINI Package
100 Single pulse
(W)
50 30
Ta = 25C
Allowable power dissipation
PC
10 5 3 20 20 0.8 15 15 0.8 Single device 0.3 10 m 100 m 1 10 100 1000 Mounted on ceramic board of 40 50 0.8 mm
1 0.5
PDmax is a value within the area limited by the thermal resistance.
Pulse width
tw
(s)
Figure 7.1
Allowable Power Dissipation in the Transient State (2SK2615)
7.1.2
PW-MOLD Package
The allowable power dissipation in a transient state is higher for pulse operation than in a saturation state. Allowable power dissipation vs. pulse width characteristic for the 2SK2399 is shown in Figure 7.2.
300 Single pulse Ta = 25C 100
PDmax Allowable power dissipation
(W)
30 10
Mounted on ceramic board of 50 50 0.8 mm PDmax is a value within the area limited by the thermal resistance.
3 1
30 30 Single device
0.3 0.1 10 m
100 m
10
100
Pulse width
tw
(s)
Figure 7.2
Allowable Power Dissipation vs. Pulse Width (2SK2399)
72
8.
Minimum Pad Dimensions
8.1
PW-MINI
Figure 8.1 shows minimum pad dimensions and lead-attachment layout of a PW-MINI package. Drain power dissipation is greatly affected by the size of the drain-connection pad area; the largest size should be used for effective heat radiation.
Unit: mm
Figure 8.1
Minimum Pad Dimensions for a PW-MINI Package
8.2
PW-MOLD and DP
Thermal radiation from PW-MOLD and DP packages occurs mainly from the drain-fin, and if the conductive area of the device that contacts the fin is increased, drain power dissipation will also increase. Therefore, the conductive pattern of the drain section should be as large as possible. Figure 8.2 shows the minimum pad dimensions for PW-MOLD and DP packages.
Unit: mm
Figure 8.2
Minimum Pad Dimensions for PW-MOLD and DP Packages
73
8.3
TFP
The mounting-pad area of the drain fin should be as large as possible because the TFP package disperses heat mainly through the drain fin. Thus, the larger the mounting-pad area, the larger the power dissipation. Figure 8.3 shows the minimum pad dimensions for a TFP package.
Unit: mm
8.0
1.5
1.2
1.2
3.8
1. Gate: G 2. Source1: S1 3. Source2: S2 4. Drain: D
Figure 8.3
Minimum Pad Dimensions for a TFP Package
8.4
TO-220SM
The mounting-pad area of the drain fin should be as large as possible because the TO-220SM package disperses heat mainly through the drain fin. Thus, the larger the mounting-pad area, the larger the power dissipation. Figure 8.4 shows the minimum pad dimensions for a TO-220SM package.
2.0 2.0
2.0
2.0
6.0
Unit: mm
Figure 8.4
Minimum Pad Dimensions for a TO-220SM Package
74
9.
Tape Specifications
9.1
TPS Tape
9.1.1
Product Naming
Symbols indicated after product numbers are for specifying packing classification. A typical indication is given immediately below. (however, this classification does not apply to products that are not subject to Toshiba standard specifications for their electrical characteristics.) [Indicative Example]
2SK2200 (TP) Tape specification Toshiba part number
9.1.2
Tape Specification
9.1.2.1
Tape Dimensions
The tape dimensions are as shown in Figure 9.1 and Table 9.1.
T P h
A1 P A H1 W2 d H0 H L1 1 F1F2 F P0 t P2
d1 W0 W1 D0 W
Figure 9.1
Tape Layout
75

Table 9.1
Name Product width
Product height Product thickness
Tape Dimensions
Note Tape width
Attaching tape width Carrier hole dislocation
Unit: mm
Symbol W
W0 W1
Symbol A1
A T
Dimension 8.00.2
7.00.2 3.50.2
Name
Dimension
18.0 + 1. 0 0.5
Note
6.00.5
9.0
+ 0.75 0.5
Lead width Lead thickness Lead length attached to tape Product pitch Feed hole pitch Feed hole center to lead center Lead spacing Product misalignment (1) Product misalignment (2)
d d1 1 P P0 P2 F1/F2 h P
0.5 0.5
+ 0.15 0.05 + 0.15 0.05
Attaching tape dislocation Product bottom surface position Lead clinch height Product upper-limit position 3 Carrier hole diameter Tape thickness Off-spec item cutting position
W2 H H0 H1 D0 t L1
1.0 max 17.5 + 0.75 0.5
4.0 min 12.71.0 12.70.2 6.350.5 2.5 + 0.4 0.1
16.00.5 32.25 max 4.00.2 0.60.3 11.0 max 4
02.0 01.3
Note 3: Cumulative pitch error tolerance is 1 mm for 20 pitches. Note 4: Board thickness is 0.4 0.1 mm.
Exclude at least five devices
9.1.2.2
Packed Device Quantity

2000/pack
9.1.2.3
Ammo Pack Instruction

Devicebearing tapes are folded in an ammo pack with 24 devices in each row as shown in Figure 9.2.
1 row includes 24 devices
Exclude at least five devices
Figure 9.2
9.1.2.4
Leader and Trailer

There must be empty sections for at least 5 devices at the beginning and end of the tape. *: Indicates polarity of first-out the lead. S: source first out 326 4 G: gate first out
G* S* 334 3
45 2
9.1.2.5
Polarity of First-out of the Lead

The polarity of first-out of the lead is as shown in Figure 9.3.
(unit: mm)
Figure 9.3
Ammo Pack Package
9.1.2.6
Ammo Pack Package

1: Material = paper 2: Dimensions are shown as in Figure 9.3.
76

9.1.2.7 Tape Splicing Method
The tape splicing method (at the end of a tape or when one is cut) is shown in the figure belowcut the tape and connect the ends with the splicing tape.
<Front> Location of cut <Rear> Location of cut
Splicing tape
Splicing tape
Figure 9.4
How to Splice a Tape
Dimension a must be within 1 mm/20 pitches.
9.1.2.9
Fall-out
Device fall-out should be not more than three consecutively.
Figure 9.5
Joint Accuracy
9.1.2.10 Taped Device Attachment Security Test
Item
Testing Method
Required Performance
(a)
Lengthwise direction Apply 1 N load in the direction of the arrow for 3 1 seconds.
0.98 N Fixation
H 19 mm
Fulfills tape packing specifications.
Skew resistance (b) Transverse direction Apply 1 N load in the direction of the arrow for 3 1 seconds. Fixation 0.98 N
H 19 mm
(a)
Intensity test Apply a load of at least 4.9 N in the direction of the arrow. Fixation
There should be no lead dislocation.
Extraction resistance
(b)
Life test Leave open for 6 months in a normal temperature and normal humidity.
Required to satisfy extraction resistance performance standard (a) above.
9.1.3
Others
The electrical characteristics of taped devices are given in relevant technical datasheets.
77
9.1.2.8
Joint Alignment
20 pitches
9.2
TO-92 MOD Type Ammo Tape
9.2.1
Product Naming
Symbols indicated after product numbers are for specifying packing classification. A typical indication is listed below. (however, this classification does not apply to products that are not subject to Toshiba standard specifications for their electrical characteristics.) [Indicative Example]
2SK940 (TPE6) Tape specification Toshiba part number
9.2.2
Tape Specifications
9.2.2.1
Tape Dimensions
The tape dimensions are as shown in Figure 9.6 and Table 9.2.
A1 P P T h
H1 H
W0 W1
D0
L1
H0
W2 W
P2 F1 F2 P0
Figure 9.6
Tape Layout
78

Table 9.2
Name Product width Product height Product thickness Lead width Lead length attached to tape Product pitch Feed hole pitch Feed hole center to lead center Lead spacing
Product misalignment (1) Product misalignment (2)
Tape Dimensions
Note Tape width Attaching tape width Carrier hole dislocation Attaching tape dislocation Product bottom surface position Lead clinch height 5 Product upper-limit position Carrier hole diameter
Tape thickness Off-spec item cutting position (total thickness) Length of overlap between center lead and cover tape
Unit: mm
Symbol W W0 W1 W2 H H0 H1 D0
t L1 2
Symbol A1 A T d 1 P P0 P2 F1/F2
h P
Dimension 5.1 max 8.2 max 4.1 max 0.65 max 3.5 min 12.7 0.5 12.7 0.15 6.35 0.4
2.5 +0.5 0.3 0 2.0 0 1.0
Name
Dimension 18.0 + 1.0 0. 5
Note
6.0 0.3 9.0 0.5 0.5 max 20.0 max 16.3 + 0. 2 0. 8
28.0 max 4.0 0.2

0.6 0.2 11.0 max 2.1 typ. 6
Note 5: Cumulative pitch dimension error tolerance is 1 mm for 20 pitches. Note 6: Board thickness is 0.4 0.1 mm.
Exclude at least four devices
9.2.2.2
Packed Device Quantity

2000/pack
9.2.2.3

Devicebearing tapes are folded in an ammo pack with 25 devices in each row as shown in Figure 9.7.
1 row includes 25 devices Exclude at least four devices
Figure 9.7
Ammo Pack Instructions
9.2.2.4
Leader and Trailer

There must be empty sections for at least 4 devices at the beginning and end of the tape. *:
190 3 G* S*
Indicates polarity of first-out the lead. S: source first out G: gate first out
336 3
47 3
9.2.2.5
Polarity of First-out of the Lead

The polarity of first-out of the lead is as shown in Figure 9.8.
(unit: mm)
Figure 9.8
Ammo Pack Package
9.2.2.6
Ammo Pack Package

1: Material = paper 2: Dimensions are shown as in Figure 9.8.
79

9.2.2.7 Tape Splicing Method
The tape splicing method (at the end of a tape or when one is cut) is shown in the figure belowcut the tape and connect the ends with the splicing tape.
<Front> Location of cut <Rear> Location of cut
Splicing tape
Splicing tape
Figure 9.9
How to Splice a Tape
Dimension a must be within 1 mm/20 pitches.
9.2.2.9
Fall-out
Device fall-out should be not more than three consecutively.
Figure 9.10
Joint Accuracy
9.2.2.10 Taped Device Attachment Security Test
Item
Testing Method
Required Performance
H 20 mm
(a)
Lengthwise direction Apply 0.9 N load in the direction of the arrow for 3 1 seconds.
0.98 N
Skew resistance 0.98 N
H 20 mm
(b)
Transverse direction Apply 0.9 N load in the direction of the arrow for 3 1 seconds. Fixation
(c)
Extraction resistance
Intensity test Apply a load of at least 4.9 N in the direction of the arrow. Fixation
At least 4.9 N. There should be no lead dislocation.
(d)
Life test Leave open for 6 months in a normal temperature and normal humidity.
Required to satisfy extraction resistance performance standard (a) above.
9.2.3
Others
The electrical characteristics of taped devices are given in relevant technical datasheets.
80
9.2.2.8
Joint Alignment
20 pitches
9.3
Tape Specifications for PW-MINI Package
9.3.1
Product Naming
Symbols indicated after product numbers are for specifying packing classification. A typical indication is listed below. (However, this classification does not apply to products that are not subject to Toshiba standard specifications for their electrical characteristics.) [Indicative Example]
2SK2615 (TE12L) Tape specification Toshiba part number
9.3.2
Tape Specification
9.3.2.1
Tape Specification is as Shown in Table 9.3.
Table 9.3
Tape Type TE12L TE12R
Tape Specification
L or R L R
9.3.2.2
Device Orientation
Device orientation on the carrier tape is as shown in Figure 9.11.
L: TE12L R: TE12R
Figure 9.11
Device Orientation
81

9.3.2.3 Tape Dimensions
1: 2: 3: Cumulative pitch error tolerance is 0.2 mm or less / 10 pitches The tape material is plastic with carbon (black). The tape dimensions are as shown in Figure 9.12.
1.5 0.1
4.0 0.1 2.0

2.0 1.5 +0.1 0 0.3 0.05
Unit: mm
12.0 0.3
5.65 0.05
5.1 0.2 4.9 0.2 4.5 0.2 4.7 0.2 9.5 0.5
4.85
0.9 2.3 8.0 0.1 1.65 0.1 1.8 0.1
Figure 9.12
Tape Form and Dimensions
9.3.2.4
Packing Quantity
1000/reel
9.3.2.5
Empty Device Recesses Are as Shown in Table 9.4.
Table 9.4
Parameters
Empty Device Recess

Specification 0 0.2% max/reel
Occurrences of 2 or more successive empty device recesses Single empty device recesses
82

9.3.2.6 Reel
1: 2: Material: Plastic Dimensions are as shown in Figure 9.13
A A-A
Front
Unit: mm
Rib structure
2 0.5
41.5
13 0.2
75
120
41.5
Sensor hole
0.9
98
+ 0.2 0. 0
1.1 0.2
9.5 A
Rear 30 Rib structure 60
21 0.8
R40 R77 18
R37.5
Sensor hole
4.5 12
Figure 9.13
Reel Form and Dimensions
83
75 0.5 178 1.0
46
30

9.3.3 Label
The label markings may include the product number; tape type, quantity, lot number, Toshiba logo and country of origin. The position of the label is as shown in Figure 9.14. Label example: 2SK2615 (TE12L)
Position of label
TYPE ADDC NOTE (TE12L)
2SK2615 Qty pcs
Figure 9.14
Reel Front
9.3.4
Leader and Trailer
Trailer section: at least 10 empty pockets
Note 1 Note 2
Note 1: Leader section: at least 100 mm of carrier tape Note 2: Leader: 300 mm min
9.3.5
Others
The electrical characteristics of taped devices are given in the relevant technical datasheets.
84
9.4
Tape Specifications for PW-MOLD Package
9.4.1
Product Naming
Symbols indicated after product numbers are for specifying packing classification. A typical indication is listed below. (However, this classification does not apply to products that are not subject to Toshiba standard specifications for their electrical characteristics.) [Indicative Example]
2SK2231 (TE16L1,N) Tape specification Toshiba part number
9.4.2
Tape Specification
9.4.2.1
Table 9.5
Tape Type TE16L1 TE16R1
Tape Specification
L or R L R
9.4.2.2
Device Orientation
L: TE16L1 R: TE16R1
Figure 9.15
Device Orientation
85

Unit: mm 1.5 + 0.1 0 1.5 + 0.1 0 0.3 0.05
1.75 0.1
4.0 0.1 2.0 0.1
16.0 0.3
7.5 0.1
6.75
6.8 0.1 8.0 0.1 2.8 0.1
Figure 9.16
9.4.2.4
Packing Quantity
2000/reel
9.4.2.5
Table 9.6
Parameters
Empty Device Recess

86
10.1 0.2

9.4.2.6 Reel
1: 2: Material: Plastic with carbon Dimensions are as shown in Figure 9.17
Unit: mm
17.5 1.5 40
2.0 R5 0.5 R120 2
120 3
2 0.5
13 0.5
3 0.5
10 1
2 0.5
2 0.5
Figure 9.17
87
330 2
80 1

9.4.3 Label
The label markings may include the product number; tape type, quantity, lot number, Toshiba logo and country of origin. The position of the label is as shown in Figure 9.18. Label example
TYPE ADDC NOTE (TE161, N)
2SK Qty pcs
Label on the reel may also include ADD.CODE PART Number.

Position of label
Figure 9.18 9.4.4 Leader and Trailer
Reel Front
Note 1 Note 2
9.4.5
Others
88
9.5
Tape Specifications for DP Package
9.5.1
Product Naming
Symbols indicated after product numbers are for specifying packing classification. A typical indication is listed below. (However, this classification does not apply to products that are not subject to Toshiba standard specifications for their electrical characteristics.) [Example]
2SK2614 (TE16L1) Tape specification Toshiba part number
9.5.2
Tape Specification
9.5.2.1
Table 9.7
Tape Type TE16L1 TE16R1
Tape Specification
L or R L R
9.5.2.2
Device Orientation
L: TE16L1 R: TE16R1
Figure 9.19
Device Orientation
89

4.0 0.1 2.0 0.1 1.5 + 0.1 0 1.5 + 0.1 0 Unit: mm 0.3 0.05
16.0 0.3
7.5 0.1
1.75 0.1
6.75
6.8 0.1 8.0 0.1 2.8 0.1
Figure 9.20
9.5.2.4
Packing Quantity
2000/reel
9.5.2.5
Table 9.8
Parameters
Empty Device Recess

90
10.1 0.2

9.5.2.6 Reel
Unit: mm
17.5 1.5 40
3 0.5
10 1
2 0.5
2 0.5
Figure 9.21
9.5.3
Label
TYPE ADDC NOTE (TE161)
2SK Qty pcs
Position of label
Figure 9.22
Reel Front
91
330 2
80 1
2 0.5
R120 2
13 0.5
2.0 R5 0.5
120 3

9.5.4 Leader and Trailer
Note 1 Note 2
9.5.5
Others
92
9.6
Tape Specifications for TFP Package
9.6.1
Product Naming
9.6.2
Tape Specification
9.6.2.1
Tape Specification Is as Shown in Table 9.9.
Table 9.9
Tape Specification
L or R L R
9.6.2.2
Device Orientation
L: TE24L Recommended R: TE24R
Figure 9.23
Device Orientation
93

Unit: mm 1.75 0.1
4.0 0.1
12.0 0.1
2.0 0.1
1.5 0.1
0.30 0.05
11.5 0.1 9.5 0.1 2.0 0.1 10.5 0.1
21.5 0.3
24.0 0.3
3.0 0.1
Figure 9.24
9.6.2.4
Packing Quantity
1500/reel
9.6.2.5
Table 9.10
Parameters
Empty Device Recess

94

9.6.2.6 Reel
120 3 25.5 2
Unit: mm
4.0 0.5
R6.5
R135
60
100 1
13 0.5
2 0.5
Figure 9.25
95
330 2

9.6.3 Label
2SK Qty pcs
Position of label
Figure 9.26
Reel Front
9.6.4
Leader and Trailer
Note 1 Note 2 Trailer section: at least 10 empty pockets
9.6.5
Others
96
9.7
Tape Specifications for TO-220SM Package
9.7.1
Product Naming
9.7.2
Tape Specification
9.7.2.1
Table 9.11
Tape Specification
L or R L R
9.7.2.2
Device Orientation
L: TE24L R: TE24R
Figure 9.26
Device Orientation
97

Unit: mm 1.5 + 0.1 0 2.0 + 0.1 0.4 0.05
1.75 0.1
4.0 0.1 2.0 0.1
24.0 0.3
11.5 0.1
10.75
10.8 0.1 12.0 0.1 5.2 0.1
Figure 9.27
9.7.2.4
Packing Quantity
1000/reel
9.7.2.5
Table 9.12
Parameters
Empty Device Recess

98
13.9 0.1
21.5

9.7.2.6 Reel
120 3
25.4 2
Unit: mm
4.0 0.5
R6.5
R135
60
4.0 0.5
100 1
2.0 0.5
13 0.5
2 0.5
Figure 9.28
9.7.3
Label
2SK Qty pcs
330 2
Position of label
Figure 9.29
Reel Front
99

9.7.4 Leader and Trailer
Note 1 Note 2 Trailer section: at least 10 empty pockets
9.7.5
Others
100
10.
Letter Symbols and Graphical Symbols
10.1
Power MOSFET Characteristics
Letter Symbol
Symbol Ciss Coss Crss ID IDP IDR IDRP IDSS IGSS PD Qg Qgd Qgs RDS (ON) Rth (ch-a) Rth (ch-c) SOA Tch Tstg Explanation Input capacitance Output capacitance Reverse transfer capacitance Drain current Drain current (pulse) Drain reverse current Drain reverse current (pulse) Drain cutoff current Gate leakage current Drain power dissipation Total gate charge Gate-drain (Miller) charge Gate-source charge Drain-source ON resistance Channel-ambient thermal resistance Channel-case thermal resistance Safe operating area Channel temperature Storage temperature Symbol td (on) tr ton td (off) tf toff VDGR VDS (ON) VDS VDSX VDSF VDSS VGS VGSS V (BR) DSS Vth Yfs trr Qrr Turn-ON delay time Rise time Turn-ON time Turn-OFF delay time Fall time Turn-OFF time Drain-gate voltage Drain-source ON voltage Drain-source voltage Drain-source voltage Drain-source forward voltage (diode) Drain-source voltage Gate-source voltage Gate-source voltage Drain-source breakdown voltage Gate threshold voltage Forward transfer admittance Reverse recovery time Reverse recovery charge Explanation
Graphic Symbols
Device Graphic Symbol Device Graphic Symbol
D N-channel MOS enhancement-type field effect transistor P-channel MOS enhancement-type field effect transistor S
G S
The characters and numerals included in the graphic symbols are for explanation purposes and are not part of the symbols. The characters are defined as follows. D: Drain G: Gate S: Source
The following package symbols are omitted when confusion might not result, and when a device is not connected to an external package.
Envelope
Symbols
101

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[ 3 ] Power MOSFET in Detail

[ 3 ] Power MOSFET in Detail

[ 3 ] Power MOSFET in Detail

Type P-channel field effect transistor N-channel field effect transistor

[ 3 ] Power MOSFET in Detail

Construction and Characteristics

Power MOSFET Construction

[ 3 ] Power MOSFET in Detail

Source Source Gate Drain P n+ n+ P n+ n+

Power MOSFET Construction

Power MOSFET Features

[ 3 ] Power MOSFET in Detail

Products in use Product cost

[ 3 ] Power MOSFET in Detail

Maximum Drain-Source Voltage Rating

[ 3 ] Power MOSFET in Detail

Drain-Source Breakdown Voltage

Maximum Gate-Source Voltage Rating

[ 3 ] Power MOSFET in Detail

Junction temperature Ta normalized by reference temperature To

T To PDmax = chmax ....................................................................... (2)

[ 3 ] Power MOSFET in Detail

Safe Operating Area

Forward Bias Safe Operating Area (SOA)

Safe Operating Area

Safe Operating Area

DC operation (Tc = 25C)

VDSS max 1 10 100

Figure 3.3 Power MOSFET Safe Operating Area (2SK2782)

Power MOSFET Safe Operating Area (TPC8009-H)

[ 3 ] Power MOSFET in Detail

(a) Reverse safe operating area

VCEX (sus) (V)

Reverse Safe Operating Area

VDS P.G. ZDi Di

Measurement Circuit for Reverse Safe Operating Area

[ 3 ] Power MOSFET in Detail

[ 3 ] Power MOSFET in Detail

0.1 0.1 1 10 100

Temperature Derating in Safe Operating Range

as follows: dT = PD(Tch C ) PD(25C ) T Tch = chmax ............................................................... (4) Tchmax 25

When Tch = 25C, the constant-power line is:

[ 3 ] Power MOSFET in Detail

(A) Drain current ID

TPC8108 Safe Operating Area (Ta = 25C)

TPC8108 Safe Operating Area (Ta = 125C)

[ 3 ] Power MOSFET in Detail

Power MOSFET Temperature Characteristics

[ 3 ] Power MOSFET in Detail

12 14 12 10 8 6 4 2 0 1 Common source VDS = 10 V

Common source 10 VGS = 10 V 15

Gate-source voltage VGS

VDS (ON) Tc Characteristics

Power MOSFET Electrostatic Capacitance Characteristics

[ 3 ] Power MOSFET in Detail

gate and source to charge the input

Power MOSFET Switching Characteristics

Capacitance VDS Characteristics

(b) Input/output waveforms

Switching Time Measurement Circuit and Input/Output Waveforms