T91F161642

CMOS 2-Bank 524,288-Word 16 Bit Synchronous Dynamic Random Access

■ DESCRIPTION
The TIWIN SD11620HGT device is a CMOS Synchronous Dynamic Random Access
Memory (SDRAM) containing 16,777,216 memory cells accessible in a 16-bit format.
The SD11620HGT device features a fully synchronous operation referenced to a
positive edge clock hereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The SD11620HGT
SDRAM is designed to reduce the complexity of using a standard dynamic RAM
(DRAM) which requires many control signal timing constraints, and may improve
data bandwidth of memory as much as 5 times more than a conventional DRAM.
The SD11620HGT device is ideally suited for personal computers, high resolution
graphic adapters/accelerators, VCD/MP3 player and other applications where an
extremely large memory and bandwidth are required and where a simple interface is
needed. The SD11620HGT device is available in 50-pin 400 mil TSOP-II package.

■ FEATURES
• Single +3.3 V Supply ±0.3 V tolerance
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Two bank operation
• Burst read/write operation and burst read/single write operation capability
• Programmable burst type, burst length, and CAS latency
• Auto-and Self-refresh
• CKE power down mode
• Output Enable and Input Data Mask

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■ PRODUCT FAMILY
SD11620HGT
Parameter
-6 -7

CL - tRCD - tRP 3 - 3 - 3 clk min. 3 - 3 - 3 clk min.

Clock Frequency 166 MHz max. 133 MHz max.

CL=2 8 ns min 9 ns min

Burst Mode Cycle Time
CL=3 6 ns min. 7 ns min.

CL=2 6 ns max. 7 ns max.

Access Time From Clock
CL=3 5.5 ns max. 6 ns max

Operating Current (single bank) 120 mA max 110 mA max

Operating Current (dual bank) 170 mA max 150 mA max

Power Down Mode Current (ICC2P) 2 mA max. 2 mA max.

Self Refresh Current (ICC6) 1 mA max. 1 mA max

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■PIN CONFIGURATION
50-Pin TSOP(II)
(TOP VIEW)

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■ LOGIC BLOCK DIAGRAM

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■ PIN DESCRIPTION
Pin Number Symbol Function

1, 7, 13, 25, 38, 44 VCC, VCCQ Supply Voltage

Data I/O
2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42,
DQ0 to DQ15 •Lower Byte : DQ0 to DQ7
43, 45, 46, 48, 49
•Upper Byte : DQ8 to DQ15

4, 10, 26, 41, 47, 50 VSS, VSSQ Ground

33, 37 N.C. No Connection

15 /WE Write Enable

16 /CAS Column Address Strobe

17 /RAS Row Address Strobe

18 /CS Chip Select

19 BA Bank Select (Bank Address)

Address Input

20, 21, 22, 23, 24, 27, 28, 29, 30, •Row: A0 to A10
A0 to A10
31, 32 •Column: A0 to A7

( A10 : Auto Precharge Enable )

34 CKE Clock Enable

35 CLK Clock Input

14, 36 DQML, DQMU DQ MASK

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*1
■ FUNCTIONAL TRUTH TABLE
*2, *3, and *4
C O M M AN D T R U T H TAB L E
A9
CKE
Function Symbol /CS /RAS /CAS /WE BA A10 To
n-1 n
A0
*5
Device Deselect DESL H X H X X X X X X
*5
No Operation NOP H X L H H H X X X

Burst Stop BST H X L H H L X X X

*6
Read READ H X L H L H V L V
*6
Read with Auto-precharge READA H X L H L H V H V
*6
Write WRIT H X L H L L V L V
*6
Write with Auto-precharge WRITA H X L H L L V H V
*7
Bank Active ACTV H X L L H H V V V

Precharge Single Bank Bank PRE H X L L H L V L X

Precharge All Banks PALL H X L L H L X H X

*8,9
Mode Register Set MRS H X L L L L X L V

Notes:
*1.V = Valid, L = Logic Low, H = Logic High, X = either L or H.
*2. All commands assume no CSUS command on previous rising edge of clock.
*3. All commands are assumed to be valid state transitions.
*4. All inputs are latched on the rising edge of clock.
*5. NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will represent both NOP
and DESL command in later descriptions.
*6. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has been
activated (ACTV command). Refer to STATE DIAGRAM.
*7. ACTV command should only be issued after corresponding bank has been recharged (PRE or PALL command).
*8. Required after power up. Refer to POWER-UP INITIALIZATION.
*9. MRS command should only be issued after all banks have been recharged (PRE or PALL command)

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■ D Q M T R U T H TA B L E
CKE
Function Symbol DQML DQMU
n-1 n

Data Write/Output Enable for Lower Byte ENBL L H X L X

Data Write/Output Enable for Upper Byte ENBL U H X X L

Data Mask/Output Disable for Lower Byte MASK L H X H X

Data Mask/Output Disable for Upper Byte MASK U H X X H

■ C K E T R U T H TA B L E
CKE A9
Current A10
Function Symbol /CS /RAS /CAS /WE BA To
State n-1 n (AP)
A0
Bank Active Clock Suspend Mode Entry *1 CSUS H L X X X X X X X

Any (Except
Clock Suspend Continue*1 L L X X X X X X X
Idle)

Clock
Clock Suspend Mode Exit L H X X X X X X X
Suspend

Idle Auto-refresh Command*2 REF H H L L L H X X X

Idle Self-refresh Entry*2,3 SELF H L L L L H X X X

L H L H H H X X X
Self Refresh Self-refresh Exit SELFX
L H H X X X X X X

H L L H H H X X X
Idle Power Down Entry*3 PD
H L H X X X X X X

Power L H L H H H X X X
Power Down Exit
Down L H H X X X X X X

Notes:
*1.The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM.
NOP or DESL command should be issued after CSUS and PRE (or PALL) commands asserted at the same time.
*2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL command). Refer to
STATE DIAGRAM.
*3. SELF and PD commands should only be issued after the last read data have been appeared on DQ.

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*1
■ O P ERAT ION C OM MAND TAB LE (Ap p l ic ab l e to s in gl e ba nk)
Current
/CS /RAS /CAS /WE Ad d r Command Function
State

H X X X X DESL NOP

L H H H X NOP NOP

L H H L X BST NOP

L H L H BA, CA, AP READ/READA Illegal*2

L H L H BA, CA, AP WRIT/WRITA Illegal*2

Idle
L L H H BA, RA ACTV Bank Active after tRCD

L L H L BA, AP PRE/PALL NOP

L L L H X REF/SELF Auto-refresh or Self-refresh*3, 6

L L L L MODE MRS Mode Register Set*3, 7

(Idle after t RSC)

H X X X X DESL NOP

L H H H X NOP NOP

L H H L X BST NOP

L H L H BA, CA, AP READ/READA Begin Read; Determine AP

Bank
L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP
Adive
L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE/PALL Precharge; Determine Precharge Type

L L L H X REF/SELF Illegal

L L L L MODE MRS Illegal

(Continued)

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Current
/CS /RAS /CAS /WE Ad d r Command Function
State

H X X X X DESL NOP (Continue Burst to

NOP (Continue Burst to End Æ

L H H H X NOP
Precharge ÆIdle)

L H H L X BST Illegal
Read with L H L H BA, CA, AP READ/READA Illegal*2

Auto-
L H L L BA, CA, AP WRIT/WRITA Illegal*2
precharge
L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE/PALL Illegal*2

L L L H X REF/SELF Illegal

L L L L MODE MRS Illegal

NOP (Continue Burst to

H X X X X DESL
EndÆPrecharge ÆIdle)

NOP (Continue Burst to

L H H H X NOP
EndÆPrechargeÆ Idle)

Write with L H H L X BST Illegal

Auto- L H L H BA, CA, AP READ/READA Illegal*2

precharge L H L L BA, CA, AP WRIT/WRITA Illegal*2

L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE/PALL Illegal*2

L L L H X REF/SELF Illegal

L L L L MODE MRS Illegal

(Continued)

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Current State /CS /RAS /CAS /WE Ad d r Command Function

H X X X X DESL NOP (Idle after tRP)

L H H H X NOP NOP (Idle after tRP)

L H H L X BST NOP (Idle after tRP)

L H L H BA, CA, AP READ/READA Illegal*2

L H L L BA, CA, AP WRIT/WRITA Illegal*2

Precharging
L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE/PALL NOP (PALL may affect other bank)*5

L L L H X REF/SELF Illegal

L L L L MODE MRS Illegal

H X X X X DESL NOP (Bank Active after tRCD)

L H H H X NOP NOP (Bank Active after tRCD)

L H H L X BST NOP (Bank Active after tRCD)

L H L H BA, CA, AP READ/READA Illegal*2

Bank Activating L H L L BA, CA, AP WRIT/WRITA Illegal*2

L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE/PALL Illegal*2

L L L H X REF/SELF Illegal

L L L L MODE MRS Illegal

(Continued)

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Current State /CS /RAS /CAS /WE Ad d r Command Function

H X X X X DESL NOP (Idle after tRC)

L H H X X NOP/BST NOP (Idle after tRC)

READ/READA/
L H L X X Illegal
Refreshing WRIT/WRITA

L L H X X ACTV/PRE/PALL Illegal

REF/SELF/
L L L X X Illegal
MRS

H X X X X DESL NOP(Idle after tRC)

L H H H X NOP NOP (Idle after tRC)

L H H L X BST Illegal
Mode
Register READ/READA/
L H L X X Illegal
Setting WRIT/WRITA

ACTV/PRE/
L L X X X PALL/REF/ Illegal
SELF/MRS

ABBREVIATIONS:
RA = Row Address BA= Bank Address
CA = Column Address AP=Auto Precharge

Notes : *1. All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock cycle and the
current clock cycle.
Illegal means don't used command. If used, power up sequence be asserted after power shut down.
*2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank.
*3. Illegal if any bank is not idle.
*4. Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to TIMING DIAGRAM
-11 & -12.
*5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*6. SELF command should only be issued after the last read data have been appeared on DO.
*7. MRS command should only be issued on condition that all DO are in Hi-Z.

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*1
■ C O M M A N D T R U T H TA B L E F O R C K E
Current CKE CKE
/CS /RAS /CAS /WE Ad d r Function
State n-1 n

H X X X X X X Invalid

Exit Self-refresh
L H H X X X X
(Self-refresh RecoveryÆIdle after tRC)

Exit Self-refresh
L H L H H H X
(Self-refresh RecoveryÆIdle after tRC)
Self-refresh
L H L H H L X Illegal

L H L H L X X Illegal

L H L L X X X Illegal

L L X X X X X NOP (Maintain Self-refresh)

L X X X X X X Invalid

H H H X X X X Idle after tRC

H H L H H H X Idle after tRC

Self-

refresh H H L H H L X Illegal

Recovery
H H L H L X X Illegal

H H L L X X X Illegal

H L X X X X X Illegal*2

(Continued)

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Current CKE CKE

/CS /RAS /CAS /WE Ad d r Function
State n-1 n

H X X X X X X Invalid

L H H X X X X
Exit Power Down Mode Æ Idle
L H L H H H X

Power Down L L X X X X X NOP (Maintain Power Down Mode)

L H L L X X X Illegal

L H L H L X X Illegal

L H L H H X X Illegal

H H H X X X MODE Refer to the Operation Command

H H L H X X MODE Refer to the Operation Command

H H L L H X MODE Refer to the Operation Command

H H L L L H X Auto-refresh

H H L L L L MODE Refer to the Operation Command

H L H X X X X Power Down

All Banks Idle H L L H H H X Power Down

H L L H H L X Illegal

H L L H L X X Illegal

H L L L H X X Illegal

H L L L L H X Self-refresh*3

H L L L L L X Illegal

L X X X X X X Invalid

(Continued)

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CKE CKE
Current State /CS /RAS /CAS /WE Ad d r Function
N- 1 n

Bank Active Bank Refer to the Operation Command

H H X X X X X
Activating Table.

Read/Write
Read with Auto- H L X X X X X Begin Clock Suspend next cycle
precharge/
Write with
Auto-precharge L X X X X X X Invalid

H X X X X X X Invalid

Clock Suspend L H X X X X X Exit Clock Suspend next cycle

L L X X X X X Maintain Clock Suspend

L X X X X X X Invalid

Any State Other

Than Refer to the Operation Command
H H X X X X X
Listed Above Table.

H L X X X X X Illegal

Notes:
*1. All entries in COMMAND TRUTH TABLE FOR CKE are specified at CKE(n) state and CKE input from CKE(n-1) to CKE(n) state
must satisfy corresponding set up and hold time for CKE.
*2. CKE should be held High for tRC period.
*3. SELF command should only be issued after the last data have been appeared on DQ.

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■ FUNCTIONAL DESCRIPTION

SDRAM B ASIC FUNCTION

Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode,
and mode register.
The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the
synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks,
/RAS and /CAS. Each operation of DRAM is determined by their timing phase differences while each operation
of SDRAM is determined by commands and all operations are referenced to a positive clock edge. Fig 2 shows
the basic timing diagram differences between SDRAMs and DRAMS.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a
column addresses for the first access is set, following addresses are automatically generated by the internal
column address counter.
The mode register is to justify the SDRAM operation and function into desired system conditions. MODE
REGISTER TABLE shows how S DRAM can be configured for system requirement by mode register
programming.

CLOCK(CLK) and CLOCK EN ABLE (CKE)

All input and output signals of SD RAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by
the CLK. CKE is a high active clock enable signal. When CKE= Low is latched at a clock input during active
cycle, the next clock will be internally masked. During idle state (all banks have been precharged), the
Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current.

CHIP SELECT (/CS)

/CS enables all commands inputs, /RAS, /CAS, and /WE, and address input. When /CS is High, command
signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't
needed, /CS can be tied to ground level.

COMMAND INPUT (/RAS, /CAS and /WE)

Unlike a conventional DRAM, /RAS, /CAS, and /WE do not directly imply SDRAM operation, such as Row
address strobe by RAS. Instead, each combination of /RAS, /CAS, and /WE input in conjunction with /CS input
at a rising edge of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5.

ADDRESS INPUT (A0 to A10)

Address input selects an arbitrary location of a total of 1,048 576 words of each memory cell matrix. A total of
twenty address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in
order to reduce the pin count of the address line. At a Bank Active command (ACTV), twelve Row addresses are
initially latched and the remainder of eight Column addresses are then latched by a Column address strobe
command of either a Read command (READ or READA) or Write command (WRIT or W RITA).

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BANK SELECT (BA)

This SDRAM has two banks and each bank is organized as 512K words by 16-bit.
Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and precharge command (PRE).

DATA INPUTS AND OUTPUTS (DQ0 to DQ15)

Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (min) is satisfied (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
tAC ; from the clock edge after tRAC o and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH).

DATA I/O MASK (DQML/DQMU)

DQML and DOMU are an active high enable input and has an output disable and input mask function. During
burst cycle and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output
will be masked at the second clock later while internal burst counter will increment by one or will go to the next
stage depending on burst type.

BURST MODE OPERATION AND BURST TYPE

The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row
address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as
tAC and tCK ,respectively. The internal column address counter operation is determined by a mode register
which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move
from the current burst mode to the next stage while the remaining burst count is more than 1, the following
combinations will be required:

Current Stage Next Stage Method (Assert the following command)

Burst Read Burst Read Read Command

1st Step Mask Command (Normally 3 clock cycles)

Burst Read Burst Write
2nd Step Write Command after lOWD

Burst Write Burst Write Write Command

Burst Write Burst Read Read Command

Burst Read Precharge Precharge Command

Burst Write Precharge Precharge Command

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The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential
mode is an incremental decoding scheme within a boundary address to be determined by count length, it
assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to
least significant address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2 If the first
access of column address is even (0), the next address will be odd (1), or vice-versa.
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation.
The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column
burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length,
it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least
significant address (= 0).

Burst Starting ColumnAddress

Sequential Mode Interleave
Length A2 A 1 A0
XX0 0-1 0-1
2
XX1 1-0 1-0
X00 0-1-2-3 0-1-2-3
X01 1-2-3-0 1-0-3-2
4
X10 2-3-0-1 2-3-0-1
X11 3-0-1-2 3-2-1-0
000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
8
100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

FULL COLUMN BURST AND BURST STOP COMMAND (BST)

The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is
repeatedly access to the same column. If burst mode reaches end of column address, then it wraps round to first column
address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT), precharge (PRE), or burst stop
(BST) command. The selection of Auto-precharge option is illegal during the full column burst operation except write
command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its
operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to TIMING DIAGRAM-8.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored.

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BURST READ & SINGLE WRITE

The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst
read operation does not be affected by this mode.

PRECHARGE AND PRECHARGE OPTION (PRE, PALL)

SDRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations.
Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge
command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge
time (tRP).
The precharged bank is selected by combination of AP and BA when Precharge command is asserted. If AP
=High, all banks are precharged regardless of BA (PALL). If AP =Low, a bank to be selected by BA is
precharged (PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge
command assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTIONAL
TRUTH TABLE.

AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command.
The Auto-refresh command should also be asserted every 16 ps or a total 4096 refresh commands within a 64 ms
period.

SELF-REFRESH ENTRY (SELF)

Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF).
Once SDRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or
low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be
maintained. SELF command should only be issued after last read data has been appeared on DQ.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted poor to the
self-refresh mode entry.

SELF-REFRESH EXIT (SELF)

To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No operation command (NOP)
or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one
tRC period after tCKSP. Refer to Timing Diagram-16 for the detail.
It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted after the
self-refresh exit.

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MODE REGISTER SET (MRS)

The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields, Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power). MRS command should only be issued on condition that all
DO is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM . Refer to POWER-UP INITIALIZATION below.

POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh commands (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode
Register Set command (MRS) can be set before 2 Auto-refresh commands (REF).

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■ MODE REGISTER TABLE

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■ ABSOLUTE MAXIMUM RATINGS (See WARNING)

Parameter Symbol Value Unit

Voltage of VCC Supply Relative to VSS VCC, VCCQ –0.5 to +4.6 V

Voltage at Any Pin Relative to VSS VIN, VOUT –0.5 to +4.6 V

Short Circuit Output Current IOUT –50 to +50 mA

Power Dissipation PD –1.3 W

Storage Temperature TSTG –55 to +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS (Referenced to VSS)

Parameter Notes Symbol Min. Typ. Max. Unit

VCC, VCCQ 3.0 3.3 3.6 V

Supply Voltage
VSS, VSSQ 0 0 0 V
*1
Input High Voltage VIH 2.0 — VCC + 0.3 V
*2
Input Low Voltage VIL –0.3 — 0.8 V

Ambient
SD11620HGT-6 TA 0 — +70 °C
Temperature

Notes:

WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use
semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely
affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their TIWIN representatives beforehand.

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 T91F161642

■ CAPACITANCE
Parameter Symbol Min. Typ. Max. Unit
Input Capacitance, Except for CLK CIN1 2.5 — 5.0 pF

Input Capacitance for CLK CIN2 2.5 — 5.0 pF

I/O Capacitance CI/O 4.0 — 7.0 pF

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■ DC CHARACTERISTICS
Value
Parameter Symbol Condition Unit
Min. Max.
Output High Voltage VOH(DC) IOH = –2 mA 2.4 — V

Output Low Voltage VOL(DC) IOL = 2 mA — 0.4 V

0 V ≤ VIN ≤ VCC;
Input Leakage Current (Any Input) ILI All other pins not under –10 10 µA
test = 0 V

0 V ≤ VIN ≤ VCC;
Output Leakage Current ILO –10 10 µA
Data out disabled
Burst Length = 1
tRC = min
tCK = min
110
Operating Current One bank active Output pin
ICC1S — / mA
(Average Power Supply Current) open Addresses changed up
120
to one time during tCK (min)
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
All banks idle
tCK = min
ICC2P Power down mode 1 mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
All banks idle
CLK = VIH or VIL mA
ICC2PS 1
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Precharge Standby Current (Power
Supply Current) CKE = VIH
All banks idle, tCK = 15 ns
NOP command only,
Input signals (except to
ICC2N 15 mA
CMD) are changed one
time during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
All banks idle
CLK =VIH or VIL
ICC2NS Input signal are stable — 2 mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC

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Value
Parameter Symbol Condition Unit
Min. Max.
CKE = VIL, Any bank active
tCK = min
ICC3P — 2 mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL, Any bank active
CLK = VIH or VIL
ICC3PS — 1 mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH, Any bank active
Active Standby Current (Power
tCK = 15 ns
Supply Current)
NOP command only, Input
signals (except to CMD) are
ICC3N — 25 mA
changed one time during 30
ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH, Any bank active
CLK = VIH or VIL
ICC3NS Input signals are stable — 2 mA
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
tCK = min
Burst Length = 4
Output pin open 170
Burst mode Current(Average Power
ICC4 All-banks active — / mA
Supply Current)
Gapless data 180
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Auto-refresh;
tCK = min 100
Refresh Current #1(Average Power
ICC5 tRC = min — / mA
Supply Current)
0 V ≤ VIN ≤ VIL max 110
VIH min ≤ VIN ≤ VCC
Self-refresh;
tCK = min
Refresh Current #2(Average Power
ICC6 CKE ≤ 0.2 V — 1 mA
Supply Current)
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
Notes:
*1.All voltage are referenced to VSS.
*2.DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3.ICC depends on the output termination or load conditions, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination register.
*4.This value is for reference only.

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AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2, *3

SD11620HGT SD11620HGT
Parameter Symbol Unit
Min. Max. Min. Max.
CL = 2 tCK2 8 9 ns
Clock Period － －
CL = 3 tCK3 6 7 ns
*5
Clock High Time tCH 2.5 － 3.0 － ns
*5
Clock Low Time tCL 2.5 － 3.0 － ns
Input Setup Time*5 tSi 2 － 2.5 － ns
*5
Input Hold Time tHi 1 － 1 － ns

CL = 2 tAC2 6 7 ns
Access Tim from ClocK*5,6,7 － －
(tCK = min)
CL = 3 tAC3 5.5 6 ns
*5
Output in Low-Z tLZ 1 － 1 － ns
CL = 2 tHZ2 3 6 3 7 ns
Output in High-Z*5,8
CL = 3 tHZ3 3 5.5 3 6 ns
CL = 2 2.5 3 ns
Output Hold Time*5,7 tOH － －
CL = 3 2.5 3 ns
Time between Auto-Refresh command tREFI － 16 － 16 µs
interval*4
Time between Refresh tREF － 65 － 65 ms
Transition Time tT 0.5 10 0.5 10 ns
CKE *5Setup Tim for Power Down Exit tCKSP 2.0 － 2.0 － ns
Time

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BASE VALUES FOR CLOCK COUNT/LATENCY

SD11620HGT SD11620HGT

-6 -7
Parameter Symbol Unit
Min. Min.
Max. Max.
CL=3 CL=2 CL=3 CL=2

/RAS Cycle Time*9 tRC 58 60 — 68 70 — ns

/RAS Precharge Time tRP 22 18 — 23 20 — ns

/RAS Active Time tRAS 42 45 110000 45 50 110000 ns

/RAS to /CAS Delay Time tRCD 20 18 — 22.5 20 — ns

Write Recovery Time tWR 6 8 — 7.5 10 — ns

/RAS to /RAS Bank Active Delay

tRRD 13 18 — 15 20 — ns
Time

Data-in to Precharge Lead Time tDPL 15 10 — 15 10 — ns

1 cyc+ 1 cyc+
CL=2 tDAL2 — — — — ns
Data-in to tRP tRP

Active/Refresh 2 2
Command Period CL=3 tDAL3 cyc+ — — cyc+ — — ns

tRP tRP

Mode Resister Set Cycle Time tRSC 15 20 — 15 20 — ns

CLOCK COUNT FORMULA Note *10

Base Value
Clock ≥ (Round off a whole number )
Clock Period

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 T91F161642

LATENCY - FIXED VALUES

(The latency values on these parameters are fixed regardless of clock period.)

Parameter Symbol SD11620HGT Unit

CKE to Clock Disable lCKE 1 Cycle

DQM to Output in High-Z lDQZ 2 Cycle
DQM to Input Data Delay lDQD 0 Cycle
Last Output to Write Command Delay lOWD 2 Cycle
Write Command to Input Data Delay lDWD 0 Cycle
CL = 2 lROH2 2 Cycle
Precharge to Output in High-Z Delay
CL = 3 lROH3 3 Cycle
Burst Stop Command to Output in CL = 2 lBSH2 2 Cycle
High-Z Delay CL = 3 lBSH3 3 Cycle
/CAS to /CAS Delay (min) lCCD 1 Cycle

/CAS Bank Delay (min) lCBD 1 Cycle

Notes:
*1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*2. AC characteristics assume tT = 1 ns and 50 pF of capacitive load.
*3. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL
(max). (See Fig. 5)
*4. This value is for reference only.
*5. If input signal transition time (tT) is longer than 1 ns; [(tT/2) –0.5] ns should be added to tAC (max), tHZ (max), and tCKSP
(min) spec values, [(tT/2) –0.5] ns should be subtracted from tLZ (min), tHZ (min), and tOH (min) spec values, and (tT –1.0)
ns should be added to tCH (min), tCL (min), tSI (min), and tHI (min) spec values.
*6. tAC also specifies the access time at burst mode .
*7. tAC and tOH are the specs value under AC test load circuit shown in Fig. 4.
*8. Specified where output buffer is no longer driven.
*9. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
*10. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All
clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole
number).

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 T91F161642

Fig.4 － OUTPUT LOAD CIRCUIT

Output

CL=30pF

LVTTL

Note: By adding appropriate correlation factors to the test conditions, tAC and tOH measured
when the output is coupled to the Output Load Circuit are within specifications.

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TIMING DIAGRAMS

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PACKAGE DIMENSION
50-pin plastic TSOP(II)

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