Compact Na V triode-MOSFET Transconductor: J.A. de Lima and W.A. Serdijn

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Compact nA=V triode-MOSFET transconductor

J.A. De Lima and W.A. Serdijn


A simple nA=V CMOS transconductor for low-frequency gm-C lters is presented. To benet from the lowest gm=ID ratio, input transistors operate in the triode region, with gm adjusted by their (W=L) and VDS, the latter a tuning-voltage replica. Since VDS surmounts the equivalent noise of the replica circuit, excellent control of gm is attained. Simulations support theoretical analysis. A 5Hz bandpass lter was designed, featuring SNR 59.2 dB for THD < 1% at 150 mV and 17 nW consumption.

P-type input-transistors were chosen owing to lower mobility and 1=f-noise coefcients compared to similar parameters of n-MOSFETs. Except for M1A-M1B that stay in SI-TR, remaining devices work in WI-S.

Introduction: On-chip realisations of large time constants are often required to design very low cutoff-frequency continuous-time lters in applications such as integrated sensors, biosignal ampliers and neural networks. Owing to their low-voltage low-power (LVLP) compatibility, gm-C structures are a natural choice to perform the desired ltering. However, to limit capacitors to practicable size, gm values in the range of a few nA=V are typically needed. Previous LVLP CMOS techniques to obtain such a very low gm essentially combine different strategies of voltage attenuation, source degeneration and current splitting. The intrinsic attenuating properties of oating-gate and bulk-driven techniques are exploited in [1]. The latter solution implies in a nite input-impedance transconductor and lack of precision, as the bulk transconductance gmb is very processdependent. In the source-degeneration scheme presented in [2], a triodebiased transistor simply mimics a voltage-controlled resistor. Matching is a crucial problem in current splitting, since a large number of unitycell transistors compose the current mirrors to implement very high division factors [3, 4]. In this Letter we discuss the advantages of a strong-inversion triode (SI-TR) transconductor in designing gm-C lters in the hertz and subhertz range. Contrary to previous approaches, gm is now controlled by a voltage rather than by a current. In an SI-TR MOSFET, by connecting the source terminal to one of the supply rails, a control voltage applied to the drain linearly adjusts gm. Since (W=L) offers a degree of freedom in size gm, VDS values well above the equivalent noise of the replica circuit can be imposed. Consequently, lters with more predictable frequency characteristics can be implemented.

Fig. 1 Compact triode transconductor

Bias generator: Bias voltages VB and VC are derived from the circuit shown in Fig. 2. The generator is structurally like the transconductor, with M1G, M2G and M3G ideally matched to their counterparts. A servo-amplier (SA) regulates M1G drain voltage to external voltage VTUNE, so that VC VTUNE jVGS2Gj. Since VGS2G VGS2A VGS2B, the expected value of VC is achieved. Properly setting the current gain B (B > 1) in M4G-M5G ensures class-A operation of the transconductor, while tracking down parameter variations on M1A (M1B).

Transconductor description: The gm=ID ratio is listed in Table 1, for distinct MOSFET regions: SI-TR, weak-inversion saturation (WI-S) and strong-inversion saturation (SI-S). The gate-overdrive voltage is VGO VGS VTO, where VTO is the threshold voltage. UT and n are the thermal voltage and the weak-inversion slope factor, respectively. As it can be noted, for a source-grounded device and VDS small, the lowest gm=ID occurs for SI-TR operation, as VGO can be set much higher than nUT.

Fig. 2 Bias generator

Table 1: gm=ID and NID ratios in different operation regions


WI-S SI-TR SI-S gm=ID 1=nUT 1=VGO (nVDS=2) 2=VGO nVs

For a given gm, the current level in WI-S may easily become one order of magnitude lower than the one in SI-TR. Although WI-S operation reduces power consumption, the ID required to obtain gm in the nA=V interval is bounded by the junction leakage and its variation with temperature. Therefore, generating such a very low current reliably is difcult to achieve. The proposed compact triode transconductor is depicted in Fig. 1. Input transistors M1A-M1B have their drain voltages regulated by an auxiliary amplier that comprises M2A-M2B, M3A-M3B and bias current sources M5A-M5B, while M4A-M4B provides the single-ended output. The gate-voltage of M2A-M2B is set to VC VTUNE jVGS2j, whereas VB imposes a bias current IB through M5A-M5B. Both voltages VB and VC are derived from the bias generator. Referring VTUNE to VDD, denoting b1 (W=L)1 mpCox and assuming transistors pair-wise matched, the transconductance of the entire circuit is g m gm1 b1 V TUNE 1

Transconductor and lter design: An SI-TR transconductor was designed and used as a building part in a gyrator-capacitor bandpass lter. The design complies with VDD 1.5 V and a standard 0.35 mm n-well CMOS process, with typical parameters VTHN 0.50 V, VTHP 0.60 V, gn 0.58 V1=2, gp 0.45 V1=2, mn 403 cm2=Vs, mp 129 cm2=Vs and Cox 446 nF=cm2. For 10 mV VTUNE 50 mV, it turns out 1.1 nA=V gm1 5.5 nA=V. Optimal VAGND is 0.6 V, which limits the signal amplitude to 185 mV. Transistor dimensions (in mm=mm) are (W=L)1 (1.2=600), (W=L)2 (10=100), (W=L)3 (12=2.4) and (W=L)4 (W=L)5 (40=40). Such a sizing trades-off 1=f-noise and layout area. At nominal VTUNE 20 mV, the calculated gm1 and common-mode current ID1CM are 2.2 nA=V and 0.63 nA, respectively. A lossless integrator with CLOAD 60 pF has a unity-gain frequency f int of 5.8 Hz. Setting B 1.5 results in IB 0.25 nA, a good compromise between signal swing, 1=f-noise of M2A-M2B and M5A-M5B, thermal noise and power consumption in the auxiliary amplier. Assuming identical transconductors with gm1 2.2 nA=V in the bandpass lter, the calculated centre frequency fc is 5.8 Hz. Owing to the large M1 gate-area, the integrating capacitors should account for the transconductor input capacitance Cin. For an SI-TR MOSFET, CGS CGD (1=2)WLCox, and, since ja1j ( 1, the Miller effect can be neglected, yielding Cin W1L1Cox. Since VTUNE is shared by all stages, a single bias-generator circuit can be used.

ELECTRONICS LETTERS 29th September 2005 Vol. 41 No. 20

Simulation results: Simulations were carried out using PSPICE 9.2 and Bsim3v3 models. The basic integrator exhibits f int 5.0 Hz and an excess phase of 0.6 , which indicates that the phase error is due to stray capacitances rather than to a nite rout. The transconductor equivalent noise voltage for a 100 mHz10 Hz bandwidth is 260 mVRMS. Similarly, the input-referred noise of the VC generator is 42 mVRMS, so that for the lowest VTUNE of 10 mV, a tuning-to-noise ratio (TNR) of 47 dB is obtained. Given that transistor geometries are well dened in modern fabrication processes, gm can be controlled to a good extent, as it relies only on (W=L)1 and VTUNE. The frequency response of the lter against VTUNE is shown in Fig. fc 13.2 Hz. A 3. For 10 mV VTUNE 50 mV, one has 2.46 Hz linear control of fc by VTUNE is observed, at a rate of 0.27 Hz=mV. For comparison, the calculated fc range and tuning rate are 2.9 Hz fc 14.5 Hz and 0.30 Hz=mV, respectively. The lter maximum stand-by consumption is as low as 17 nW.

Conclusion: A compact CMOS transconductor as a building part for ultra-low power gm-C lters suitable for operation in the hertz and subhertz ranges is proposed. Input transistors are kept in the stronginversion triode region to prot from the lowest gm=ID. Because their drain voltages are regulated to VTUNE by an auxiliary amplier, gm scales directly with (W=L) and VTUNE. Such a voltage-controlled approach offers improved accuracy in obtaining gm values of the order of nA=V, as the required ID can be set well above expected values of leakage current. A bandpass lter was designed in accordance with VDD 1.5 V and a 0.35 mm n-well CMOS process. The tuning voltage VTUNE spans from 10 to 50 mV, yielding 1.1 nA=V gm 5.5 nA=V. Since the tuning-tonoise ratio equals 47 dB, accurate gm control is achieved. The lter can be tuned from 2.46 to 13.2 Hz, featuring an SNR of 59.2 dB for THD 1% at 150 mV peak-value. Maximum stand-by consumption is limited to 17 nW. # IEE 2005 Electronics Letters online no: 20052551 doi: 10.1049/el:20052551 14 July 2005

J.A. De Lima (Brazil Semiconductor Technological Center, Freescale Semiconductor, 13820-000 Jaguariuna, SP Brazil) E-mail: jader.delima@freescale.com W.A. Serdijn (Electronics Research Laboratory, Faculty of Electrical Engineering, Delft University of Technology, Delft, The Netherlands) References
1 Veeravalli, A., Sa nchez-Sinencio, E., and Silva-Mart nez, J.: Transconductance amplier structures with very small transconductances: a comparative design approach, IEEE J. Solid-State Circuits, 2002, 37, (6), pp. 770775 Silva-Mart nez, J., and Salcedo-Suner, J.: IC voltage to current transducers with very small transconductances, Analog Integr. Circuits Signal Process., 1997, 13, pp. 285293 Steyaert, M., Kinget, P., Sansen, W., and Van Der Spigel, J.: Full integration of extremely large time constants in CMOS, Electron. Lett., 1991, 27, (10), pp. 790791 Arnaud, A., and Galup-Montoro, C.: A fully integrated 0.57 Hz CMOS bandpass amplier. Proc. IEEE ISCAS, Vancouver, Canada, 2004, Vol. 1, pp. 445448

2 Fig. 3 Frequency response of bandpass lter against tuning voltage 3

At nominal tuning, the in-band equivalent noise is 116 mVRMS. Large-signal distortion corresponds to THD 1% for an amplitude of 150 mV, so that an SNR of 59.2 dB is attained. Since HD2 dominates, one may assume that a balanced version of the proposed transconductor would present better linearity. Monte-Carlo analysis for a spread of 0.5% on both (W=L) and VTO parameters on every transistor of the lter revealed that the amplitude should be limited to 137 mV to retain THD 1%.

ELECTRONICS LETTERS 29th September 2005 Vol. 41 No. 20

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