SamplingCircuits

Nan Sun NanSun

UniversityofTexasatAustin
nansun@mail.utexas.edu
1 EE382V
ADC Big Picture ADCBigPicture
How to build a sampling circuit in the realworld? Howtobuildasamplingcircuitinthereal world?
IdealDiracsamplingisimpractical
Buildatrackandholdcircuit
2 EE382V
Ideal TrackandHold Circuit IdealTrack and HoldCircuit
InfinitelyfastandaccuratetrackingofV
in
Noerrorintheholdphase
3
p
EE382V
Circuit with MOS Switch CircuitwithMOSSwitch
Trackingerror
Pedestalerror
4 EE382V
Nonidealities Nonidealities
h Switchresistance
Finiteacquisitiontime
Thermal noise Thermalnoise
Nonlinearresistance
Switchcapacitance
Samplingclockjitter
Othernonidealities
5 EE382V
Finite Acquisition Time FiniteAcquisitionTime
l d d Case1:Inputisasampleddata
signal,e.g.theoutputofa
switchedcapacitorcircuit
Case2:Inputisavarying
continuoustimesignal
|
Track Hold
|
Track Hold
|
t
V
Track Hold
t
t
V
in
V
in
0
t
t
6 EE382V
Finite Acquisition Time Case 1 FiniteAcquisitionTime Case1
Forsimplicity,letusignorethefiniterisetimeofV
in in
Considertheworstcase:V
out
settlesfrom0toV
FS
1
st
orderMOSswitchmodel
) e (1 V (t) V
t/
FS out

=
/2 T
FS FS t
s
e V V /2) (T V V

= =
7
FS FS s out err
e V V /2) (T V V
EE382V
Finite Acquisition Time Case 1 FiniteAcquisitionTime Case1
h l | | ? Wewantthesettlingerror|V
err
|<LSB?
1 B
FS
/2 T
FS
/2 V /2 e V
s
+
= s
Therequired#timeconstantN:
B N
6 >4 9
( )
1 B
S
2 ln
T
N
+
>
Doessettlingerrorcausedistortion?
6 >4.9
10 >7.6
14 >10.4
( ) 2 ln
2
N >
14 10.4
18 >13.2
8 EE382V
Finite Acquisition Time Case 2 FiniteAcquisitionTime Case2
Considerasinusoidalinputwithzerooffset
( ) t Acos (t) V
in
=
Delay
( ) ( )
2 2
t/
out
1
t cos
A Ae (t) V
+

+ ~

1+
Initial
discontinuity
settling
Steadystate
Amplitude
attenuation
RCfilterresponse
attenuation
9 EE382V
Finite Acquisition Time Case 2 FiniteAcquisitionTime Case2
h / f Theerroratt=T
s
/2consistsoftwoparts:
Errorduetotheexponentialdecayoftheinitialdiscontinuity
Similar to Case 1 it decays with time SimilartoCase1,itdecayswithtime
Errorinthesteadystateterm
ResultofRCLPF
Magnitudeattenuationandphaseshift
ItdependsonRC(filterresponse)andtheinputfrequency
It does not decay with time Itdoesnotdecaywithtime
Willthiserrorcausedistortion?
Howlargeistheamplitudeattenuation?
10 EE382V
Finite Acquisition Time Case 2 FiniteAcquisitionTime Case2
Letuscalculatethepercentamplitudeerror
2
f
| |
( ) s
in
2
in
2
err
f
f
N

2
1
f
1
1
1
1
1
1 A
|
|
.
|

\
|
~
|
|
|

|
+
=
+
=
Amplitudeerrorincreaseswithf
in
,butdecreaseswithN.
s
f N
1
|
|
.

\
+
B N A
err
(f=f
s
/10) A
err
(f
in
=f
s
/2)
6 4 9 0 20% 5% 6 4.9 0.20% 5%
10 7.6 0.08% 2%
14 10 4 0 05% 1% 14 10.4 0.05% 1%
18 13.2 0.03% 0.7%
11 EE382V
Summary Finite Acquisition Time Summary FiniteAcquisitionTime
Forsampleddatainput,wecanachieveaccuratetrackinggivena
sufficientamountoftime.
Forcontinuousinput,weneedtoconsidertheerrorsduetoboththe
initial settling and the filter response initialsettlingandthefilterresponse.
Inapplicationswhereattenuationisintolerable,wemayneedto
furtherreducetheRCtimeconstant.
Inapplicationswhereattenuationistolerable,theRCtime
constantisusuallysetbythedistortionspecs.
The larger the attenuation the larger the instantaneous Thelargertheattenuation,thelargertheinstantaneous
voltagedropacrossthenonlinearMOSFETundesired
harmonics.
Whataboutthephasedelay?
Thesampledinputisalwaysadelayed(t)version.
12 EE382V
Thermal Noise ThermalNoise
h l d Transistorthermalnoisedominates
1/fnoisecanbeignored(why?)
2
2
1
1
4
sRC
kTR
f
v
out
+
=
Af
( )
C
kT
df
fRC
kTR n v
out
= =
}

0
2
2
2 1
1
4 ] [
( )
C
fRC
out
+
}
0
2
2 1 t
13 EE382V
Equipartition Theorem EquipartitionTheorem
Equipartitiontheoreminstatisticalphysicsstatesthatinthermal
ilib i h d f f d h ld h l equilibriumeachdegreeoffreedomholdsonaveragethermalenergy
ofkT/2.
Inanelectroniccircuit,eachindependentcapacitorholdsanelectric , p p
energyofkT/2andeachindependentinductorholdsamagnetic
energyofkT/2.
This theorem can help reduce the complexity of noise analysis Thistheoremcanhelpreducethecomplexityofnoiseanalysis.
Usethistheoremcautiously!
kT
kT v C
out
=
2
2
2
1
2
1
C
kT
v
out
=
2
14 EE382V
kT/C Noise kT/CNoise
AssumingthatwemakethekT/Cnoiseequaltothequantization
i f B bi ADC noiseofaBbitADC

2
12
12
2
2
|
|
.
|

\
|
=
A
=
B
V
kT C
C
kT
Forexample:
12
|
.

\ FS
V C
B C [pF]
8 0.003
10 0.052 10 0.052
12 0.834
14 13.3
16 213
18 3,416
15 EE382V
RealWorld Example Real WorldExample
LTC2242
12bitADC
Why2pF?
16 EE382V
Voltage Dependence of R VoltageDependenceofR
on
V
| |
DS
DS
th GS ox D
V
V
V V C I
|
.
|

\
|
=
2

) (
1
1
0
h GS
V
DS
D
ON
V V
W
C
V
I
R
DS

=
(
(

c
c
~

) (
0
th GS ox
V
V V
L
C
DS


1
ON
W
R ~
) (
th IN ox
ON
V V
L
W
C |
R
ON
isdependentonV
in
17 EE382V
Track Mode Nonlinearity TrackModeNonlinearity
[Razavi,Data ConversionSystemDesign,p.16]
V
out
tracksV
in
wellforsmallV
in
LargeV
in
largeR
on
distortion
18 EE382V
Analysis Analysis
( )
2
V
K
V V V K I ~ ( )
2
DS DS th GS D
V V V V K I ~
( ) ( )
2
) (
out
V V
K
V V V V K I
dV
C ~ = |
WecansolvetheaboveequationuseVolterraSeriesanalysis
( ) ( )
2
) (
out in out in th out D
V V V V V V K I
dt
C ~ = |
q y
Generalmethodthatallowsustocalculatethefrequencydomain
responseofnonlinearcircuitswithmemory
S [Y TCAS II 2/1999] See[Yu,TCASII,2/1999]
19 EE382V
Result Result
h i hi d h f li d
2

) V (V
A
4
1
l fundamenta the of Amplitude
harmonic third the of Amplitude
HD
2
th GS
2
3

~ =
V
GS
isthevalueofthegatesourcevoltage whenACinputiszero.
Forlowdistortion
MakeamplitudeAsmallerthan(V
GS
V
th
)
LowswingSNRdecreases
Make e smaller Makee smaller
Lowfrequencyspeeddecreases
Maket smaller
Bigswitchparasiticcapsincreasesanddrivingpowergoesup
20 EE382V
Example Example
Parameters Parameters
V
DD
=V
CLK
=1.8V
V
in
iscenteredatV
DD
/2=0.9V
V
GS
V
th
=1.8V 0.9V 0.45V=0.45V
A=0.4V
N 0 5T / 10 N=0.5T
s
/t =10
f
in
=f
s
/2
2
| |
dB 30
20
1
) 45 . 0 (
4 . 0
4
2
2
3
=
|
.
|

\
|
~
t
HD
Thenonlinearityishuge!Howcanwereduceit?
21 EE382V
CMOS Switch CMOSSwitch
AddingaPMOScanreducetheresistancevariation
As V
IN
increases,NMOSresistancegoesup,butPMOSresistance
goesdown
1
||
1
R
( (
~
) (
||
) (
thp GSp
p
ox p thn GSn
n
ox n
V V
L
W
C V V
L
W
C
R

22 EE382V
Analysis Analysis
) (
1
thp ox p in ox p ox n thn GSn ox n
V
W
C V
W
C
W
C V V
W
C
R
(

|
|
|

|
(

~

1
) (
thp
p
ox p in
p
ox p
n
ox n thn GSn
n
ox n
W
L L L L
(
~
(

|
.

\
(

(
(

(
(

) (
thp thn DD
n
ox n
V V V
L
W
C
(

n
p
n
n
L

=
(

if
R isindependentfromV
in
;however,thismodelisoversimplified.
Missingfactors
Shortchanneleffects
Backgateeffect
23 EE382V
Real CMOS Switch RealCMOSSwitch
80
100

NMOS
PMOS
NMOS || PMOS
40
60
R

[
O
]
NMOS || PMOS
0 0.5 1 1.5
0
20

h ll l h b f l d
0 0.5 1 1.5
V
in
[V] FromB.Murmann,EE315,Ch.5
Therearestilllargeresistancevariations.Thebenefitislimited.
24 EE382V
Clock Bootstrapping ClockBootstrapping
Holdphase Trackphase
+
V
+
V
V V t V
DD

V
DD

V
in
V
GS
=V
DD
=const.
C
boot
C
boot
Holdphase
A.Abo,"DesignforReliabilityofLowvoltage, SwitchedcapacitorCircuits,"PhDThesis,UCBerkeley,1999.
Samplingswitchisoff
C
boot
isprechargedtoV
DD
Track phase Trackphase
SamplingswitchisonwithV
GS
=V
DD
=const
Thus,R
on
issignalindependent
25 EE382V
Waveforms Waveforms
A.Abo,"DesignforReliabilityofLowvoltage, SwitchedcapacitorCircuits,"PhDThesis,UCBerkeley,1999.
26 EE382V
Implementation Issues ImplementationIssues
PMOS thick NMOS thick PMOSthick
oxideswitch
NMOSthick
oxideswitch
M d Mayexceed
V
DD
V
GS
orV
GD
mayexceedV
DD
,causingtransistorbreakdown.
Thickoxidedevicescanbeusedtoensurereliability,leadingto
increasedcost,largerparasiticcapacitance,andlargerresistance.
27 EE382V
With ThickOxide Devices WithThick OxideDevices
Siragusa andGalton,Adigitallyenhanced1.8V15bit40Msample/sCMOS
i li d ADC " JSSC D 2004
28 EE382V
pipelinedADC,"JSSC,Dec.2004.
Without ThickOxide Devices WithoutThick OxideDevices
DessoukyandKaiser,"Inputswitchconfigurationsuitableforrailtorailoperationofswitched
opampcircuits,"ElectronicsLetters,Jan.1999.
29 EE382V
p p , ,
Another Implementation AnotherImplementation
Switch Switch
A.Aboetal.,A1.5V,10bit,14.3MS/sCMOSPipelineAnalogto
DigitalConverter,IEEEJ.SolidStateCircuits,pp.599,May1999
30 EE382V
Limitation of Bootstrap Technique LimitationofBootstrapTechnique
h f h l h Parasiticcapacitanceatthegateofthesamplingswitch
CapacitivedividerV
GS
notaconstant
Can be alleviated by increasing the size of the bootstrap capacitor Canbealleviatedbyincreasingthesizeofthebootstrapcapacitor
However,limitedbytheintrinsicparasiticcapassociatedwiththe
bootstrapcap
Backgateeffect
Canbealleviatedbyusingtriplewellprocess
31 EE382V
PerformanceofBootstrappedSamplers
Bootstrappedsamplingtendstoworkverywellupto60dBlinearity
Nowthelinearitybottleneckisrelatedtotheswitchcapacitance.
Example
[Louwsma,JSSC4/2008] [ , / ]
32 EE382V
Nonidealities Nonidealities
h Switchresistance
Switchcapacitance
Clock feedthrough Clockfeedthrough
Channelchargeinjection
Samplingclockjitter
Othernonidealities
33 EE382V
ChargeInjection&ClockFeedthrough
|
Track Hold
|
t
C
ol
Clock
feedthrough
T
f
V
in
V
out
t
V
in
e
-
Charge
g
t
V
out
ideal
e
Charge
injection
C
Analyzetwoextremecases
t
actual
Pedestalerror
SlowgatingwithalargeT
f
FastgatingwithasmallT
f
t
34 EE382V
Slow Gating SlowGating
Allchannelchargeshave
disappeared by T They are disappearedbyT
off
.Theyare
absorbedbytheinputsource,
andthus,donotintroduceerror.
Pedestalerrorisonlyduetoclock
feedthrough.
35 EE382V
Slow Gating Model for t > t
ff
SlowGatingModelfort>t
off
V
in
+V
th
0
th in
ol
in in out
) V (V
C
V V V V + = =
C
ol
Clock
feedthrough switchopen
os in
th in
ol
in in out
V ) (1 V
) (
C C
+ + =
+
V
out
C
C C
C

ol
ol
+
=
th
ol
ol
OS
V
C C
C
V
+
=
GainError OffsetError
Example:C=1pF,C
ol
=2fF,andV
th
=0.45V
0 2% =
1mV V ~
Doesthiscausenonlinearity?
0.2%
1mV V
OS
~
36 EE382V
Fast Gating FastGating
ChannelchargeQ
ch
hastoflowtotheinputandtheoutputnodes
Underfastgating,weassumea50/50split
37 EE382V
Fast Gating Model for t > t
ff
FastGatingModelfort>t
off
|
Q C
V
in
V
out
C
ol
Clock
feedthrough
T
f
os in
ch
DD
ol
ol
in out
V ) (1 V
2C
Q
V
C C
C
V V + + = +
+
=
e
-
Charge
injection
C
) V V WL(V C Q where
th in DD ox ch
=
C
WL C
2
1

ox
=
) V (V
C
WL C
2
1
V
C C
C
V
th DD
ox
DD
ol
ol
OS
+
+
=
Example:C=1pF,V
DD
=1.8V,V
th
=0.45V,W=20m,LC
ox
=2fF/m,andC
ol
=2fF
Doesthiscausenonlinearity?
2% = 31mV V
OS
~
38
oes s cause o ea y
EE382V
Charge Split Ratio Data ChargeSplitRatioData
LargerC
2
SmallerC
2
2
f
on
T
R C
[G.Wegmannetal.,IEEEJSSC,1987]
Inpractice,R
on
C
2
andT
f
areusuallycomparable
Chargesplitdependsontheimpedancesonbothsides
More charge ill go to the side ith lo er impedance
39
Morechargewillgotothesidewithlowerimpedance
EE382V
Summary Summary
h b l d f Inpractice,thesituationisinbetweenslowgatingandfastgating.
Slowgatingshowslessgainandoffseterror
Unsuitable for highspeed Unsuitableforhigh speed
Morelater
Arethegainerrorandtheoffseterrorreallyconstant?
No,ourfirstordermodelisnotaccurateenough.
Wehaveignoredbackgateeffectandshortchanneleffect
I i b 20% 30% f h l l d li Inpractice,about20%or30%ofwhatwecalculatedarenonlinear
errors
40 EE382V
Does CMOS Scaling Help? DoesCMOSScalingHelp?
C
Q
2
1
V
ch
~
2
Q
L
) V (V
W
C
1
R = ~
2C
L
R V
2
~
ch
th GS ox
Q
) V (V
L
W
C
ForthesameR(speed),channelchargeinducederrorAVdecreases
astechnologyadvances
S ll L d l SmallerLandlarger
ForthesameAV,Rissmaller,leadingtofasterspeed.
In general switches benefit from CMOS scaling! Ingeneral,switchesbenefitfromCMOSscaling!
41 EE382V
Charge Cancellation ChargeCancellation
1
ov1 ch1 1
Q Q
2
1
Q + ~
2Q Q Q +
ov2 ch2 2
2Q Q Q + ~
1 2 1 2
L L /2, W W = =
[Eichenberger and Guggenbhl JSSC 8/89]
Perfectcancellationrelieson
l h l h l
[EichenbergerandGuggenbhl,JSSC8/89]
Exactly50%channelchargesplitting
Limitedimprovement
42 EE382V
Differential Sampling DifferentialSampling
OS in1 out1
V )V (1 V + + =
OS in2 out2
V )V (1 V + + =
( )
in out
V 1 V + =
Offsetwillbecancelled,butthegainerrorremainsthesame.
Differentialcircuitonlycancelsoutthecommonmode.
43
y
EE382V
CMOS Switch CMOSSwitch
) V V (V C L W Q
thn in DD ox n n chn
~
) V (V C L W Q
thp in ox p p chp
~
2C
Q Q
V
chp chn
0
+
~
f l h l d d d l b dd! Unfortunately,thesignaldependentpartsdonotcancel,butadd!
44 EE382V
Bottom Plate Sampling BottomPlateSampling
Keyidea:sampleV
in
atthe"grounded"sideofthecapacitorto
achievesignalindependentsampling
Thistechniqueallowsustoachievehighlinearityincombinationwith
bootstrap technique bootstraptechnique
Originalpapers:
D.J.AllstotandW.C.Black,TechnologicalDesignConsiderations
forMonolithicMOSSwitchedCapacitorFilteringSystems,Proc.
IEEE,pp.967986,Aug.1983.
K.L.LeeandR.G.Meyer,LowDistortionSwitchedCapacitor y , p
FilterDesignTechniques,IEEEJ.SolidStateCircuits,pp.1103
1113,Dec.1985.
45 EE382V
Bottom Plate Sampling Analysis (1) BottomPlateSamplingAnalysis(1)
ff " l h l " b f TurnM
2
off"slightly"beforeM
1
Typically100ps difference
When M
2
is off it injects charge WhenM
2
isoff,itinjectscharge
( )
th DD ox 2
V V WLC Q ~
To1storder,thechargeinjectedby
M
2
issignalindependent
Assuming R is constant AssumingR
1
isconstant
VoltageacrossC(50%split)
Q A
C
Q
V V
in C
2
2
A
=
46 EE382V
Bottom Plate Sampling Analysis (2) BottomPlateSamplingAnalysis(2)
h h l h f l ThechannelchargeofM
1
issignal
dependent:
However,whenM
1
isoff,it
i j h C b
) (
1 th in ox
V V WLC Q ~ A |
cannotinjectchargetoCbecause
itsbottomsideisopen.
Waitaminute,thismodelistoo ,
ideal
47 EE382V
Bottom Plate Sampling Analysis (3) BottomPlateSamplingAnalysis(3)
h Thereareparasiticcaps.
M1willinjectsignaldependent
chargeontotheseries g
combinationofCandthe
parasiticcapacitanceatits
bottom plate C bottomplateC
par
Thisseemsthattheimprovement
willbequitelimited,asV
out
will
b ff d notbeaffected.
Nevertheless,ifweconsiderthe
sampledchargeinsteadofthe p g
voltage
48 EE382V
Bottom Plate Sampling Analysis (4) BottomPlateSamplingAnalysis(4)
Key observation: Keyobservation:
EventhoughM
1
injects
chargetoC,thetotalcharge
atnodeXcannotchange!
Letusprocesstotalcharge at
node X instead of looking at nodeXinsteadoflookingat
voltageacrossC.
X in 2
Q CV Q = A
Thechargecanbeprocessedin
two ways
X in 2
twoways
Openloop
Closedloop
49 EE382V
OpenLoop Charge Processing Open LoopChargeProcessing
During|
1
,V
in
issampledatX.Qx is
1 in
linearityproportionaltoV
in
.
Duetochargeconservation,Qx
does not change when M is on doesnotchangewhenM
3
ison
x par in x
Q C
V C C Q CV Q
A
+ = A + =
2 /
) ( 2 /
2

par
in
par
x out
C C
Q
V
C C
C
V V
+
A
+
+
= =
2 /
2
Signalflow:V
in
Q
x
V
x
Remainingdrawback
C includes transistor parasitic C
par
includestransistorparasitic
cap.Itisnonlinearandwill
introducedistortion.
50 EE382V
ClosedLoop Charge Processing Closed LoopChargeProcessing
The opamp forces voltage at node X to zero The opamp forcesvoltageatnodeXto zero
MeansthatchargeatnodeXmustredistributeontofeedback
capacitorC
F
51 EE382V
Charge Conservation Analysis ChargeConservationAnalysis
Ch t d X d i |
2 / Q CV Q A
ChargeatnodeXduring|
1
:
ChargeatnodeXduring|
2
:
2 /
2 1
Q CV Q
in x
A + =
out F x
V C Q =
2
ChargeConservation:
x x
Q Q
2 1
=
F
in
F
out
C
Q
V
C
C
V
2
2
A
+ =
C
F
canbemadehighlylinear(morelater)
Gaincanalsobeprovided.
Offsettermcanbeeasilyremovedbyusingadifferentialarchitecture.
Linearitymaybelimitedbyopampnonidealities(offset,insufficient
gain etc) gain,etc)
52 EE382V
Clock Generation ClockGeneration
[A.Abo,"DesignforReliabilityofLowvoltage, SwitchedcapacitorCircuits,"
PhDThesis,UCBerkeley,1999]
53 EE382V
Fully Differential Circuit FullyDifferentialCircuit
54 EE382V
Analysis (1) Analysis(1)
During|
1
During|
2
Q CV Q
Q CV Q
inm p
inp m
A + =
A + =
1
1
(2) ) (
(1) ) (
1 2
1 2
p om xp F xp p
m op xm F xm m
Q V V C CV Q
Q V V C CV Q
= + =
= + =

Q Q
inm p 1
1 2 p om xp F xp p
xp xm
V V =
55 EE382V
Analysis (2) Analysis(2)
Subtracting1)and2),weobtain:
Adding 1) and 2) we obtain
in
F
inm inp
F
om op out
V
C
C
V V
C
C
V V V = = = ) (
Adding1)and2),weobtain:
om op f xm xp F inm inp
V V C V V C C Q V V C + + + = A + + ) ( ) )( ( 2 ) (
cmo F cmx F cmi
V C V C C Q CV + = A + ) (
F
V
C Q
V
C
V +
A
+ =
V
cmi
(input common mode) shows up at the opamp input
cmo
F F
cmi
F
cmx
V
C C C C
V
C C
V
+
+
+
+
+
=
V
cmi
(inputcommonmode)showsupattheopampinput
Opampmusthavewideinputcommonmoderange
OpampmusthavegoodCMRR
56 EE382V
T/H with Common Mode Cancellation T/HwithCommonModeCancellation
Shortingswitchallowstoredistributeonlydifferentialcharge
CommonmodeatopampinputbecomesindependentofVcmi
57 EE382V
Analysis (1) Analysis(1)
Charge conservation at the left plate of C: ChargeconservationattheleftplateofC:
F xm float xp float im ip
V V V
C V V C V V C V V + = + ) ( ) ( ) (
xc float ic
V V V =
58 EE382V
Analysis (2) Analysis(2)
Commonmodechargeconservationattheopampinputnode:
F cmx cmo cmx float F cmo cmi
C V C V V V C V
C V V C V V C V C V
+ + =
+ =
] ) [(
) ( ) (
cmx
F cmx cmx cmx cmi cmi
V
C V C V V V C V
=
+ + =
0
] ) [(
Thus,opampinputcommonmodeV
cmx
isindependentof
InputcommonmodeV
cmi
O t t d V OutputcommonmodeV
cmo
Usuallysetbycommonmodefeedbackcircuit
59 EE382V
FlipAround T/H Flip AroundT/H
Thesamecapusedforbothsamplingandopampfeedback
Largerfeedbackfactor(lowernoise,higherspeed)
OTAissubjectedtoinputcommonmodevariations
60 EE382V
Sampling Network Design SamplingNetworkDesign
M
1
ismoreeffectiveinsamplingthedifferentialcommonmode
M
1
has half channel length M
1
hashalfchannellength
IdeallyturnoffM
2
andM
3
beforeM
1
Usuallyturnoffsimultaneouslyforsimplicity
d h ld b l h h l d d
61
M
4
andM
5
shouldbelargerthanM
1
astheirresistancesaresignaldependent
EE382V
SchematicandLayoutofM
1
y
1
From B Murmann EE 315 Ch 5
M
1
isusuallyimplementedusingantiparalleldevicestoensure
FromB.Murmann,EE315,Ch.5
symmetry
Drainandsourcearenotnecessarilysymmetricincircuitmodels
Drainandsourcearenotsymmetricduetoprocessartifacts a a d sou ce a e o sy e c due o p ocess a ac s
62 EE382V
What Ultimately Limits Linearity? WhatUltimatelyLimitsLinearity?
Bottomplate sampling plus clock bootstrapping solve majority Bottom platesamplingplusclockbootstrappingsolvemajority
nonlinearityproblems.Wecanachieve80~100dBlinearityuptoafew
hundredsofMHz.
Li it ti f l k b t t i R i ith V d t b k t Limitationofclockbootstrapping:R
top,SW
varieswithV
in
duetobackgate
effectsandparasiticcapacitances (especiallyathighfrequency)
Inthetrackphase,itcausesnonlinearfilterresponse
Bottomplatesamplingdoesnothelp.
Intheholdphase,itcausesinputdependentchargeinjection because
th h litti d d th i d thechargesplittingdependsontheimpedance
WecanmitigatethisissuebyreducingR
top,SW
Limitation of bottomplate sampling Limitationofbottom platesampling
Openloopchargetransfer:nonlinearparasiticcap
Closeloopchargetransfer:opampnonlinearity
63 EE382V
Capacitors Capacitors
MetalInsulatorMetal(MIM) MetalOxideMetal(MOM)
BothMIMandMOMcapacitorshavegoodelectricalproperties
[Ng,Trans.ElectronDev.,7/2005] [Aparicio,JSSC3/2002]
Seriesandparallelresistancesareusuallynotaconcern
Mostlyworryaboutparasiticcaps
MOM caps are preferred in advanced processes due to higher density MOMcapsarepreferredinadvancedprocessesduetohigherdensity.
Thedensityincreasesasprocessscales.
MIMcapdensityisusually12fF/m
2
For1fF/m
2
,a10pFcapacitoroccupies100mx100m
64 EE382V
Plate Parasitics PlateParasitics
Thetwoplatesofarealcapacitorareusuallyunsymmetrical
We usually use the fat plate to indicate the plate that has larger Weusuallyusethefatplatetoindicatetheplatethathaslarger
parasiticcapacitance.
ForaMIMcapacitor,theplatethatisawayfromthesubstratehas
ll iti it (t i l l 1% | 10%) smallerparasiticcapacitance(typicalvalue:o=1%,|=10%).
ForaMOMcapacitor,o and| canvary.
We can change the effective o and | through layout design. Wecanchangetheeffectiveo and| throughlayoutdesign.
65 EE382V
Proper Connection of Capacitors ProperConnectionofCapacitors
Themoreidealplateshouldfacethevirtualgroundnodes
Avoidreductionoffeedbackfactor
Reduce potential noise coupling Reducepotentialnoisecoupling
66 EE382V
Nonidealities Nonidealities
h Switchresistance
Switchcapacitance
Sampling clock jitter Samplingclockjitter
Othernonidealities
67 EE382V
Sampling Clock Jitter SamplingClockJitter
l k d l Clockjitterintroducessamplingerrors.
ItsmagnitudeisproportionaltothevariationofV
in
.
t
dt
dV
V
in
in
A ~ A
LetusconsiderasinewaveinputsignalandassumeAt followsnormal
distributionwithzeromeanandstandarddeviationo
t
68 EE382V
Analysis Analysis
{ } { }
2 2
2 2 2
in in
dV dV
E V E t E E t

| | | |
A A A
` `
| |
{ } { }
2 2 2
in in
in
2
2
E V E t E E t
dt dt
d 1
| | | |
A ~ A = A
` `
| |
\ . \ .

) )

| |
| | ( )
2
2 2
in t in t
d 1
E Acos 2 f t 2 A f
dt 2

| |
~ t o ~ t o
`
|
\ .

)
( )
2
aperture
2
in t
i t
1
A
1
2
SNR [dB] 10 log 20 log
1
2 f
2 A f
(
( (
~ =
( (
t o

(
t o
For an input signal whose power is evenly distributed in [0, f
s
/2], the
( )
in t
in t
2 A f
2

(
t o

Foraninputsignalwhosepowerisevenlydistributedin[0,f
s
/2],the
aboveresultimprovesby4.8dB
Seee.g.[DaDalt,TCAS1,9/2002]
69 EE382V
Analysis Analysis
2
2
2
2
2
] [ ] [
in in
t E
dV
E t
dV
E V E A
(
(

|
|

|
(
(

A
|
|

|
~ A
2 2 2
2
1 ) 2 cos(
] [ ] [
t
i
in in
in
t f dA
t E
dt
E t
dt
E V E
(
(

|
|

|
A
(
(

|
.

\
=
(
(

A
|
.

\
~ A
2 2 2
) 2 (
2
1 ) 2 cos(

t t
o t o
t
in
in
Af
dt
t f dA
E =
(
(

|
.
|

\
|
=
| |
1
|
|
.
|

\
|
=
|
|
|
|
|

|
=
t
o t
o t
in
jitter
f
Af
A
SNR
2
1
log 20
) 2 (
1
2
1
log 10
2 2
2
NotethatthisjitterlimitedSNRdoesnotdependonsignalamplitude!
. \
|
.

\
t
t
o t
in
in
f
Af ) 2 (
2
Thejitterinducederrorincreasesassignalamplitudeincreases.
Intesting,ifSNRremainsconstantforvarioussignalamplitudes,it
ishighlypossiblethattheSNRislimitedbyclockjitter. s g y poss b e a e S s ed by c oc j e
70 EE382V
Result Result
71 EE382V
ADCPerformanceSurveyy
FromB.Murmann,EE315,Ch.5
1 E 11
1.E+10
1.E+11
ISSCC 2010
VLSI 2010
ISSCC 1997-2009
VLSI 1997 2009
1.E+08
1.E+09
H
z
]
VLSI 1997-2009
J itter=1psrms
J itter=0.1psrms
1.E+06
1.E+07
B
W

[
H
1.E+04
1.E+05
1.E+03
10 20 30 40 50 60 70 80 90 100 110 120
SNDR[dB] SNDR [dB]
72 EE382V
Nonidealities Nonidealities
h Switchresistance
Switchcapacitance
Sampling clock jitter Samplingclockjitter
Othernonidealities
Signaldependentsamplinginstants
Holdmodefeedthrough
Holdmodeleakage
73 EE382V
Signal Dependent Sampling Instant (1) SignalDependentSamplingInstant(1)
(|) (|)
[Razavi,Data ConversionSystemDesign,p.17]
T
f
MustmakeT
f
muchsmallerthanmaximumdV
in
/dt
Thismeansthatweareinthefastgatingscenario.
74 EE382V
Signal Dependent Sampling Instant (2) SignalDependentSamplingInstant(2)
Distortionanalysisresult(seeYu,TCASII,2/1999] y (
2
3
8
3
|
|
.
|

\
|
=
F
CLK
T
V
A
HD e
Example#1:V
CLK
=1.8V,A=0.5V,T
f
=100ps,e =2t100MHz
. \
5 0 3
2
| |
Example #2: V = 1 8V A = 0 5V T = 100ps e = 2t1GHz
dB 79 12 100e 100e6 2
8 . 1
5 . 0
8
3
3
=
|
.
|

\
|
= - HD t
Example#2:V
CLK
=1.8V,A=0.5V,T
f
=100ps,e =2t1GHz
dB 39 12 100e 1e9 2
8 1
5 . 0
8
3
2
3
=
|
.
|

\
|
= - HD t
ShortT
f
isamustforsamplinghighfrequencysignal
Note that a realistic T
f
should be set in simulation
8 . 1 8
. \
NotethatarealisticT
f
shouldbesetinsimulation
75 EE382V
Hold Mode Feedthrough HoldModeFeedthrough
[Razavi,Data ConversionSystemDesign,p.17]
C
DS
Toattenuateholdmodefeedthrough g
ReduceR
out
Useaswitcharray(pathresistanceincreases)
76 EE382V
Hold Mode Leakage HoldModeLeakage
77 EE382V
Gate Leakage Data GateLeakageData
A.Annema,etal.,AnalogcircuitsinultradeepsubmicronCMOS,IEEEJ.SolidStateCircuits, pp.132143,Jan.2005.
f
gate
indicateshowfastchargeleaks
Gateleakagedependsondielectricthicknessandgatevoltage
TheuseofhighKdielectric(Hf)reducesgateleakage
Gateleakageismoretroublesomeforlowspeedoperation!
Avoid holding charges for a long time Avoidholdingchargesforalongtime
78 EE382V