Dual-Phase, Quick-PWM Controllers For IMVP-IV CPU Core Power Supplies

General Descript ion
The M AX1987/M AX1988 are dual-phase, Q uick-PWM ,

step-down controllers for IM VP-IV CPU core supplies.
D ual-phase operati on reduces i nput ri pple current
requirements and output voltage ripple, while easing
component selection and layout difficulties. The Q uick-
PWM control scheme provides instantaneous response to
fast load-current steps. The M AX1987/M AX1988 include
active voltage positioning with adjustable gain and offset,
reducing power dissipation and bulk output capacitance
requirements.
The M AX1987/M AX1988 are intended for two different
notebook C PU core applications: stepping down the
battery directly or stepping down the 5V system supply
to create the core voltage. The single-stage conversion
method allows these devices to directly step down high-
voltage batteri es for the hi ghest possi ble effi ci ency.
Alternatively, two-stage conversion ( stepping down the
5V system supply i nstead of the battery) at hi gher
swi tchi ng frequency provi des the mi ni mum possi ble
physical size.
The M AX1987/M AX1988 meet the I M VP-I V specifica-
tions and can directly interface with the C PU power-
good signals from the V
C C P
and V
C C M C H
rails within
the system. The switching regulator features power-up
sequenci ng, automati cally rampi ng up to the I ntel-
specified boot voltage. The M AX1987/M AX1988 also
feature independent four-level logic inputs for setting
the boot voltage ( B0 to B2) and the suspend voltage
( S0 to S2) .
The M AX1987/M AX1988 include output undervoltage
protection, thermal protection, and system power-O K
( SYSPO K ) input. When any of these protection features
detect a fault, the controller shuts down. Additionally,
the M AX1987 includes overvoltage protection.
The M AX1987/M AX1988 are available in a low-profile
48-pin 7mm 7mm Thin Q FN package.
Applicat ions
I M VP-I V Notebook Computers
M ultiphase CPU Core Supply
Voltage-Positioned Step-Down Converters
Servers/Desktop Computers
Feat ures
o Dual-Phase, Quick-PWM Controllers
o 0.75% V
OUT
Accuracy Over Line, Load, and
Temperature
o Active Voltage Positioning with Adjustable Gain
and Offset
o 6-Bit On-Board DAC (16mV Increments)
o 0.492V to 1.708V Output Adjust Range
o Selectable 200kHz/300kHz/550kHz Switching
Frequency
o 2V to 28V Battery Input Voltage Range
o Adjustable Slew Rate Control
o Drives Large Synchronous Rectifier MOSFETs
o Output Overvoltage Protection (MAX1987 Only)
o Undervoltage and Thermal Fault Protection
o IMVP-IV Power Sequencing and Timing
o Selectable Boot and Suspend Voltages
o Low-Profile 7mm 7mm 48-Pin Thin QFN
Package
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Dual-Phase, Quick-PWM Cont rollers for I MVP-I V
CPU Core Power Supplies
________________________________________________________________ Maxim Integrated Products 1
Ordering I nformat ion
19-2559; Rev 0; 7/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxims website at www.maxim-ic.com.
Typical Operating Circuit appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1987ETM -40C to + 100C 48 Thin Q FN 7mm 7mm
MAX1988ETM -40C to + 100C 48 Thin Q FN 7mm 7mm
V
DD
DLM
LXM
BSTM
D1
D2
D3
D5
D4
D0
DHM B0
B1
B2
S0
S1
S2
V
CC
REF
ILIM
TON
TIME 1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
C
C
I
F
B
O
A
I
N
-
O
A
I
N
+
P
S
I
I
M
V
P
O
K
S
Y
S
O
K
N
E
G
P
O
S
C
C
V
G
N
D
C
S
N
C
M
N
C
M
P
S
U
S
V
+
B
S
T
S
L
X
S
D
H
S
P
G
N
D
D
L
S
C
S
P
7mm x 7mm THIN QFN
MAX1987
MAX1988
TOP VIEW
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SHDN
C
L
K
E
N
DD0
D
P
S
L
P
Pin Configurat ion
Q uick-PW M is a tradem ark of M axim Integrated Products, Inc.
IM VP-IV is a tradem ark of Intel C orp.
CONFIDENTIAL INFORMATIONRESTRICTED TO INTEL IMVP LICENSEES
PRELI MI NARY
PRELI MI NARY
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
( Circuit of Figure1, V+ = 15V, V
CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
= 0C to +85C, unless otherwise specified.)
Stresses beyond those listed under Absolute M axim um Ratings m ay cause perm anent dam age to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not im plied. Exposure to
absolute m axim um rating conditions for extended periods m ay affect device reliability.
V+ to G ND ..............................................................-0.3V to + 30V
V
CC
to G ND ..............................................................-0.3V to + 6V
V
DD
to PG ND ............................................................-0.3V to + 6V
PSI, SUS, I M VPO K , CLKEN, DPSLP,
SYSO K , D0D5 to G ND ........................................-0.3V to + 6V
I LI M , FB, PO S, NEG , CCV, CCI , REF, O AI N+ ,
O AI N- to G ND.........................................-0.3V to ( V
CC
+ 0.3V)
CM P, CSP, CM N, CSN to G ND ..................-0.3V to ( V
CC
+ 0.3V)
DDO, TO N, TI M E, B0, B1, B2,
S0, S1, S2 to G ND ..................................-0.3V to ( V
CC
+ 0.3V)
SHDN to G ND ( Note 1) ...........................................-0.3V to + 18V
DLM , DLS to PG ND ....................................-0.3V to ( V
DD
+ 0.3V)
BSTM , BSTS to G ND ..............................................-0.3V to + 36V
DHM to LXM ...........................................-0.3V to ( V
BSTM
+ 0.3V)
LXM to BSTM ............................................................-6V to + 0.3V
DHS to LXS..............................................-0.3V to ( V
BSTS
+ 0.3V)
LXS to BSTS .............................................................-6V to + 0.3V
G ND to PG ND .......................................................-0.3V to + 0.3V
REF Short-Circuit Duration ( T
A
= + 70C) ...................Continuous
Continuous Power Dissipation
48-Pin Q FN ( derate 26.3mW/C above + 70C) ...........2.105W
O perating Temperature Range ...........................-40C to + 85C
Junction Temperature......................................................+ 150C
Storage Temperature Range .............................-65C to + 150C
Lead Temperature ( soldering, 10s) .................................+ 300C
Note 1: SHDN may be forced to 12V, for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and disables overlapping operation.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLER
Battery voltage, V+ 2 28
I nput-Voltage Range
V
CC
, V
DD
4.5 5.5
V
DAC codes from
1.276V to 1.708V
-0.75 + 0.75
DAC codes from
0.844V to 1.260V
-1.25 + 1.25
DC O utput-Voltage Accuracy
( Note 2)
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from
0.492V to 0.828V
-3.00 + 3.00
%
Line Regulation Error V
CC
= 4.5V to 5.5V, V+ = 4.5V to 28V 5 mV
I
FB
FB -2 + 2
I nput Bias Current
I
PO S,
I
NEG
PO S, NEG -0.2 + 0.2
A
PO S, NEG Common-M ode Range DPSLP = G ND 0 2 V
PO S, NEG Differential Range V
PO S
- V
NEG
, DPSLP = G ND -200 + 200 mV
PO S, NEG O ffset G ain A
O S
V
FB
/( V
PO S
- V
NEG
) ,
( V
PO S
- V
NEG
) = 100mV, DPSLP = G ND
0.95 1.00 1.05 mV/mV
PO S, NEG Enable Time t
O S
M easured from the time DPSLP goes low to
the time in which PO S, NEG affect a change
in the set point ( V
DAC
)
0.1 s
640kHz nominal, R
TI M E
= 23.5k 580 640 700
320kHz nominal, R
TI M E
= 47k 295 320 345 TI M E Frequency Accuracy f
TI M E
64kHz nominal, R
TI M E
= 235k 58 64 70
kHz
PRELI MI NARY
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ELECTRICAL CHARACTERISTICS (continued)
CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
TO N = REF
( 550kHz)
155 180 205
TO N = open
( 300kHz)
320 355 390 O n-Time ( Note 3) t
O N
V+ = 12V,
V
FB
= V
CCI
= 1.2V
TO N = V
CC
( 200kHz)
475 525 575
ns
TO N = REF ( 550kHz) 330 375
M inimum O ff-Time ( Note 3) t
O FF( M I N)
TO N = V
CC
or open ( 200kHz or 300kHz) 435 500
ns
DDO Delay Time t
DDO
M easured from the time FB reaches the
voltage set by S0 to S2. Clock speed set by
R
TI M E
.
32 clks
SK I P Delay Time t
SK I P
M easured from the time when DDO is
asserted to the time in which the controller
begins pulse-skipping operation
30 clks
BIAS AND REFERENCE
Q uiescent Supply Current ( V
CC
) I
CC
M easured at V
CC
, FB forced above the
regulation point
1.70 2.70 mA
DD
) I
DD
M easured at V
DD
regulation point
<1 5 A
Q uiescent Battery Supply
Current ( V+ )
I
V+
M easured at V+ 25 50 A
Shutdown Supply Current ( V
CC
) M easured at V
CC
, SHDN = G ND 2 5 A
DD
) M easured at V
DD
, SHDN = G ND <1 5 A
Shutdown Battery Supply
Current ( V+ )
M easured at V+ , SHDN = G ND,
V
CC
= V
DD
= 0 or 5V
<1 5 A
Reference Voltage V
REF
V
CC
= 4.5V to 5.5V, I
REF
= 0 1.990 2.000 2.010 V
Reference Load Regulation V
REF
I
REF
= -10A to + 100A -10 + 10 mV
FAULT PROTECTION
O utput O vervoltage Protection
Threshold ( M AX1987 O nly)
V
O VP
M easured at FB 1.95 2.00 2.05 V
O utput O vervoltage Propagation
Delay ( M AX1987 O nly)
t
O VP
FB forced above 2.05V 10 s
O utput Undervoltage Protection
Threshold
V
UVLO
M easured at FB with respect to unloaded
output voltage
67 70 73 %
O utput Undervoltage Propagation
Delay
t
UVP
FB forced 2% below trip threshold 10 s
PRELI MI NARY
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CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
Lower threshold
( undervoltage)
-13 -10 -7
I M VPO K , CLKEN Threshold
V
SYSPO K
= 5V;
measured at FB with
respect to unloaded
output voltage
Upper threshold
( overvoltage)
+ 7 + 10 + 13
%
CLKEN Delay t
CLKEN
FB in regulation, measured from the rising
edge of SYSPO K
30 50 90 s
O utput Fault, I M VPO K , and
CLKEN Transition Blanking Time
t
BLANK
M easured from the time when FB reaches
the voltage set by the DAC code, clock
speed set by R
TI M E
( Note 4)
32 clks
I M VPO K Delay t
I M VPO K
FB in regulation, measured from the falling
edge of CLKEN
3 5 7 ms
I M VPO K , CLKEN O utput Low
Voltage
I
SI NK
= 3mA 0.3 V
I M VPO K , CLKEN Leakage
Current
High state, I M VPO K , CLKEN forced to 5.5V 1 A
V
CC
Undervoltage Lockout
Threshold
V
UVLO
( VCC)
Rising edge, hysteresis = 90mV, PWM
disabled below this level
4.0 4.2 4.4 V
Thermal Shutdown Threshold T
SHDN
Hysteresis = 15C 160 C
CURRENT LIMIT AND BALANCE
Current-Limit Threshold Voltage
( Positive, Default)
V
LI M I T
CM P - CM N, CSP - CSN; I LI M = V
CC
27 30 33 mV
V
I LI M
= 1V 47 50 53
( Positive, Adjustable)
V
LI M I T
CM P - CM N,
CSP - CSN
V
I LI M
= 1.5V 72 75 78
mV
( Negative)
V
LI M I T
( NEG )
CC
,
SUS = G ND, and DPSLP = PSI = V
CC
-30 -36 -42 mV
( Zero-Crossing)
V
ZERO
CM P - CM N, CSP - CSN; SUS = V
CC
or
DPSLP = G ND or PSI = G ND
1.5 mV
CM P, CM N, CSP,
CSN I nput Ranges
0 2 V
CM P, CM N, CSP,
CSN I nput Current
V
CSP
= V
CSN
= 0 to 5V -2 + 2 A
I LI M I nput Current I
I LI M
V
I LI M
= 0 to 5V 0.1 200 nA
Current-Limit Default Switchover
Threshold
I LI M 3
V
CC
-
1
V
CC
-
0.4
V
Current-Balance O ffset V
O S( I BAL)
( V
CM P
- V
CM N
) - ( V
CSP
- V
CSN
) ;
I
CCI
= 0, -20mV < ( V
CM P
- V
CM N
) <+ 20mV,
0.5V < V
CCI
< 2.8V
-2.0 + 2.0 mV
PRELI MI NARY
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CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
Current-Balance
Transconductance
g
M ( I BAL)
400 S
GATE DRIVERS
DH_ G ate-Driver O n-Resistance R
O N( DH)
BST_ - LX_ forced to 5V 1.0 4.5
High state ( pullup) 1.0 4.5
DL_ G ate-Driver O n-Resistance R
O N( DL)
Low state ( pulldown) 0.4 2.0

DH_ G ate-Driver Source/Sink
Current
I
DH
DH_ forced to 2.5V,
BST_ - LX_ forced to 5V
1.6 A
DL_ G ate-Driver Sink Current I
DL( SI NK )
DL_ forced to 5V 4 A
DL_ G ate-Driver Source Current I
D L( S OU RC E )
DL_ forced to 2.5V 1.6 A
DL_ rising 35
Dead Time t
DEAD
DH_ rising 26
ns
VOLTAGE-POSITIONING AMPLIFIER
I nput O ffset Voltage V
O S
-1.5 + 1.5 mV
I nput Bias Current I
BI AS
O AI N+ , O AI N- 0.1 200 nA
O p Amp Disable Threshold O AI N- 3
V
CC
-
1
V
CC
-
0.4
V
Common-M ode I nput-Voltage
Range
V
CM
G uaranteed by CM RR test 0 2.5 V
Common-M ode Rejection Ratio CM RR V
O AI N+
= V
O AI N-
= 0 to 2.5V 70 100 dB
Power-Supply Rejection Ratio PSRR V
CC
= 4.5V to 5.5V 75 100 dB
Large-Signal Voltage G ain A
O A
R
L
= 1k to V
CC
/2 70 112 dB
V
CC
- V
FBH
77 300
O utput-Voltage Swing
( V
O AI N+
- V
O AI N-
) 10mV,
R
L
= 1k to V
CC
/2
V
FBL
47 200
mV
I nput Capacitance 11 pF
G ain-Bandwidth Product 3 M Hz
Slew Rate 0.3 V/s
Capacitive Load Stability No sustained oscillations 400 pF
LOGIC AND I/O
Logic-I nput High Voltage V
I H
SUS, DPSLP, SHDN, SYSPO K 2.4 V
Logic-I nput Low Voltage V
I L
Logic-I nput Current SUS, DPSLP, SHDN, SYSPO K -1 + 1 A
PRELI MI NARY
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CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
SHDN No-Fault Threshold To enable no-fault mode 12 15 V
1V Logic-I nput High Voltage D0D5, PSI 0.7 V
1V Logic-I nput Low Voltage D0D5, PSI 0.3 V
DAC I nput Current D0D5, PSI -1 + 1 A
Driver Disable O utput High
Voltage
DDO, I
LO AD
= 1mA 2.4 V
Driver Disable O utput Low
Voltage
DDO, I
LO AD
= 1mA 0.3 V
High V
CC
- 0.4
O pen 3.15 3.85
REF 1.65 2.35
Four-Level I nput Logic Levels
TO N, S0 to S2,
B0 to B2
Low 0.5
V
Four-Level I nput Current
TO N, S0 to S2, B0 to B2 forced to
G ND or V
CC
-4 + 4 A
ELECTRICAL CHARACTERISTICS
( Circuit of Figure 1, V+ = 15V, V
CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
= -40C to +100C, unless otherwise specified.) ( Note 5)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
PWM CONTROLLER
Battery voltage, V+ 2 28
I nput-Voltage Range
V
CC
, V
DD
4.5 5.5
V
DAC codes from
1.276V to 1.708V
-1.00 + 1.00
DAC codes from
0.844V to 1.260V
-1.50 + 1.50
DC O utput-Voltage Accuracy
( Note 2)
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from
0.492V to 0.828V
-3.5 + 3.5
%
PO S, NEG O ffset G ain A
O FF
V
FB
/( V
PO S
- V
NEG
) ,
( V
PO S
- V
NEG
) = 100mV, DPSLP = G ND
0.95 1.05 mV/mV
640kHz nominal, R
TI M E
= 23.5k 580 700
320kHz nominal, R
TI M E
= 47k 295 345 TI M E Frequency Accuracy f
TI M E
64kHz nominal, R
TI M E
= 235k 58 70
kHz
TO N = REF ( 550kHz) 155 205
TO N = open ( 300kHz) 320 390 O n-Time ( Note 3) t
O N
V+ = 12V,
V
FB
= V
CCI
= 1.2V
TO N = V
CC
( 200kHz) 475 575
ns
PRELI MI NARY
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CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
TO N = REF ( 550kHz) 375
M inimum O ff-Time
( Note 3)
t
O FF( M I N) TO N = V
CC
or open
( 200kHz or 300kHz)
500
ns
BIAS AND REFERENCE
CC
) I
CC
M easured at V
CC
regulation point
3.00 mA
DD
) I
DD
M easured at V
DD
regulation point
30 A
Q uiescent Battery Supply
Current ( V+ )
I
V+
M easured at V+ 50 A
CC
) M easured at V
CC
, SHDN = G ND 20 A
DD
) M easured at V
DD
, SHDN = G ND 20 A
Shutdown Battery Supply
Current ( V+ )
M easured at V+ , SHDN = G ND,
V
CC
= V
DD
= 0 or 5V
20 A
Reference Voltage V
REF
V
CC
= 4.5V to 5.5V, I
REF
= 0 1.985 2.015 V
FAULT PROTECTION
O utput O vervoltage Protection
Threshold ( M AX1987 O nly)
M easured at FB 1.95 2.05 V
O utput Undervoltage Protection
Threshold
M easured at FB with respect to unloaded
output voltage
67 73 %
Lower threshold
( undervoltage)
-13 -7
I M VPO K , CLKEN Threshold
V
SYSPO K
= 5V;
measured at FB with
respect to unloaded
output voltage
Upper threshold
( overvoltage)
7 13
%
CLKEN Delay t
CLKEN
FB in regulation, measured from the rising
edge of SYSPO K
30 s
I M VPO K Delay t
I M VPO K
FB in regulation, measured from the falling
edge of CLKEN
3 ms
V
CC
Undervoltage Lockout
Threshold
V
UVLO
( VCC)
Rising edge, hysteresis = 90mV, PWM
disabled below this level
3.95 4.45 V
CURRENT LIMIT AND BALANCE
( Positive, Default)
V
LI M I T
CC
25 35 mV
V
I LI M
= 1V 45 55
( Positive, Adjustable)
V
LI M I T
CM P - CM N,
CSP - CSN
V
I LI M
= 1.5V 70 80
mV
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
8 _______________________________________________________________________________________
CC
= V
DD
= V
SHDN
= V
TO N
= V
DPSLP
= V
PSI
= V
B1
= V
O AI N-
= 5V, V
B2
= 2V, V
FB
= V
CM P
= V
CM N
=
V
C SP
= V
C SN
= V
O AI N+
= V
NEG
= V
PO S
= 1. 26V, V
D4
= V
D3
= V
D2
= 1. 0V, V
SUS
= V
D5
= V
D1
= V
D0
= V
S0
= V
S1
= V
S2
=
V
B0
= 0, T
A
( Negative)
V
LI M I T
( NEG )
CC
,
SUS = G ND and DPSLP = V
CC
-27 -45 mV
Current-Balance O ffset V
O S( I BAL)
( V
CM P
- V
CM N
) - ( V
CSP
- V
CSN
) ; I
CCI
= 0,
-20mV < ( V
CM P
- V
CM N
) < 20mV,
0.5V < V
CCI
< 2.8V
-3 + 3 mV
GATE DRIVERS
DH_G ate-Driver O n-Resistance R
O N( DH)
BST_ - LX_forced to 5V 4.5
High state ( pullup) 4.5
DL_G ate-Driver O n-Resistance R
O N( DL)
Low state ( pulldown) 2.0

I nput O ffset Voltage V
O S
-2.5 + 2.5 mV
Common-M ode I nput
Voltage Range
V
CM
G uaranteed by CM RR test 0 2.5 V
V
CC
- V
FBH
300
O utput-Voltage Swing
( V
O AI N+
- V
O AI N-
) 10mV,
R
L
= 1k to V
CC
/2
V
FBL
200
mV
LOGIC AND I/O
Logic-I nput High Voltage V
I H
Logic-I nput Low Voltage V
I L
1V Logic-I nput High Voltage D0D5, PSI 0.7 V
1V Logic-I nput Low Voltage D0D5, PSI 0.3 V
High V
CC
-

0.4
O pen 3.15 3.85
REF 1.65 2.35
Four-Level I nput Logic Levels
TO N, S0 to S2,
B0 to B2
Low 0.5
V
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher
than the trip level by 50% of the output ripple. When pulse-skipping, the output rises by approximately 1.5% when transition-
ing from continuous conduction to no load.
Note 3: O n-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to
G ND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external M O SFET gate capacitance. Actual in-
circuit times can be different due to M O SFET switching speeds.
Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.
During power-up, the regulation voltage is set by the boot DAC code ( B0 to B2) . During normal operation ( SUS = G ND) , the
regulation voltage is set by the VI D DAC inputs ( D0D5) . During suspend mode ( SUS = V
CC
) , the regulation voltage is set
by the suspend DAC inputs ( S0 to S2) .
Note 5: Specifications to T
A
= -40C to + 100C are guaranteed by design and are not production tested.
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
_______________________________________________________________________________________ 9
OUTPUT VOLTAGE vs. LOAD CURRENT
(V
OUT
= 1. 356V)
M
A
X
1
9
8
7
/
8
8
to
c
0
1
LOAD CURRENT (A)
O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
30 20 10
1.20
1.25
1.30
1.35
1.40
1.15
0 40
EFFICIENCY vs. LOAD CURRENT
(V
OUT
= 1. 356V)
M
A
X
1
9
8
7
/
8
8
to
c
0
2
LOAD CURRENT (A)
E
F
F
I
C
I
E
N
C
Y

(
%
)
10 1
60
70
80
90
100
50
0.1 100
V
IN
= 12V
V
IN
= 8V
V
IN
= 20V
PSI = GND
PSI = V
CC
(V
OUT
= 0. 844V)
M
A
X
1
9
8
7
/
8
8
to
c
0
3
LOAD CURRENT (A)
O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
25 20 15 10 5
0.75
0.78
0.80
0.83
0.85
0.88
0.73
0 30
(V
OUT
= 0. 844V)
M
A
X
1
9
8
7
/
8
8
to
c
0
4
LOAD CURRENT (A)
E
F
F
I
C
I
E
N
C
Y

(
%
)
10 1
60
70
80
90
100
50
0.1 100
V
IN
= 12V
V
IN
= 8V
V
IN
= 20V
PSI = GND
PSI = V
CC
(V
OUT
= 0. 748V)
M
A
X
1
9
8
7
/
8
8
to
c
0
5
LOAD CURRENT (A)
O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
15 10 5
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.67
0 20
SUS = V
CC
(V
OUT
= 0. 748V)
M
A
X
1
9
8
7
/
8
8
to
c
0
6
LOAD CURRENT (A)
E
F
F
I
C
I
E
N
C
Y

(
%
)
10 1
60
70
80
90
100
50
0.1 100
V
IN
= 12V
V
IN
= 8V
V
IN
= 20V
PSI = GND
PSI = V
CC
- 5
- 2
- 3
- 4
0
- 1
4
3
2
1
5
- 40 - 20 0 20 40 60 80 100
REFERENCE VOLTAGE SHIFT
vs. TEMPERATURE
M
A
X
1
9
8
7
/
8
8
to
c
0
7
TEMPERATURE (C)
V
R
E
F

(
m
V
)
SWITCHING FREQUENCY
vs. LOAD CURRENT
M
A
X
1
9
8
7
/
8
8
to
c
0
8
LOAD CURRENT (A)
S
W
I
T
C
H
I
N
G

F
R
E
Q
U
E
N
C
Y

(
k
H
z
)
30 20 10
100
200
300
400
0
0 40
FORCED- PWM (V
PSI
= 5V)
SKIP MODE (V
PSI
= 0)
220
240
280
260
300
320
0 10 5 15 20 25 30
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
M
A
X
1
9
8
7
/
8
8
to
c
0
9
INPUT VOLTAGE (V)
F
R
E
Q
U
E
N
C
Y

(
k
H
z
)
I
OUT
= 20A
NO LOAD
Typical Operat ing Charact erist ics
CC
= V
DD
= 5V, SUS = G ND, SHDN = DPSLP = PSI = V
CC
, B0 to B2 set for 1.372V, S0 to S2 set for
0.748V, T
A
= + 25C, unless otherwise specified.)
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
10 ______________________________________________________________________________________
OUTPUT OFFSET VOLTAGE vs.
POS-NEG DIFFERENTIAL VOLTAGE
M
A
X
1
9
8
7
/
8
8
to
c
1
4
POS- NEG DIFFERENTIAL VOLTAGE (mV)
O
U
T
P
U
T

O
F
F
S
E
T

V
O
L
T
A
G
E

(
m
V
)
400 200 0 - 200 - 400
- 400
- 200
0
200
400
600
- 600
- 600 600
60
- 40
0.1 10 100 1000 1 10,000
GAIN AND PHASE vs. FREQUENCY
- 20
- 10
0
- 30
MAX1987/ 88 toc18
FREQUENCY (kHz)
G
A
I
N

(
d
B
)
P
H
A
S
E

(
D
E
G
R
E
E
S
)
10
20
30
40
50
180
- 180
- 108
- 72
- 36
- 144
0
36
72
108
144
GAIN
PHASE
Typical Operat ing Charact erist ics (cont inued)
CC
= V
DD
CC
0.748V, T
A
200
240
220
280
260
320
300
340
- 40 0 20 - 20 40 60 80 100
SWITCHING FREQUENCY
vs. TEMPERATURE
M
A
X
1
9
8
7
/
8
8
to
c
1
0
TEMPERATURE (C)
F
R
E
Q
U
E
N
C
Y

(
k
H
z
)
NO LOAD
20A NO LOAD
V
OUT
= 1.356V
35
36
38
37
39
40
- 40 0 - 20 20 40 60 80 100
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATURE
M
A
X
1
9
8
7
/
8
8
to
c
1
1
TEMPERATURE (C)
M
A
X
I
M
U
M

L
O
A
D

C
U
R
R
E
N
T

(
A
)
0
20
60
40
80
100
0 10 5 15 20 25 30
NO LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
(FORCED-PWM MODE)
M
A
X
1
9
8
7
/
8
8
to
c
1
2
INPUT VOLTAGE (V)
S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
I
CC
+ I
DD
I+
PSI = V
CC
0
0.5
1.5
1.0
2.0
2.5
0 10 5 15 20 25 30
NO LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
(PULSE SKIPPING)
M
A
X
1
9
8
7
/
8
8
to
c
1
3
INPUT VOLTAGE (V)
S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
I
CC
+ I
DD
I+
PSI = GND
0
10
20
30
40
50
0.834 0.839 0.844 0.849 0.854
0. 844V OUTPUT-VOLTAGE DISTRIBUTION
M
A
X
1
9
8
7
/
8
8
to
c
1
5
OUTPUT VOLTAGE (V)
S
A
M
P
L
E

P
E
R
C
E
N
T
A
G
E

(
%
)
0
5
15
10
20
25
1.995 1.999 1.997 2.001 2.003 2.005
REFERENCE VOLTAGE DISTRIBUTION
M
A
X
1
9
8
7
/
8
8
to
c
1
6
REFERENCE VOLTAGE (V)
S
A
M
P
L
E

P
E
R
C
E
N
T
A
G
E

(
%
)
0
10
5
20
15
25
30
0.98 1.00 0.99 1.01 1.02
POS-NEG OFFSET GAIN
DISTRIBUTION
M
A
X
1
9
8
7
/
8
8
to
c
1
7
POS- NEG OFFSET GAIN
S
A
M
P
E

P
E
R
C
E
N
T
A
G
E

(
%
)
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 11
VPS AMPLIFIER OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGE
M
A
X
1
9
8
7
/
8
8
to
c
1
9
COMMON- MODE VOLTAGE (V)
O
F
F
S
E
T

V
O
L
T
A
G
E

(
V
)
4 3 2 1
20
40
60
80
100
120
140
160
180
0
0 5
VPS AMPLIFIER
DISABLED
POWER-UP SEQUENCE
MAX1987/ 88 toc21
100s/ di v
0
A
B
C
D
5V
0
5V
0
0
5V
BOOT
VID
A. V
SHDN
= 0 TO 5V, 5V/ di v
B. V
OUT
= 0 TO 1.372V TO 0.844V, 500mV/ di v
C. CLKEN, 5V/ di v
D. DDO, 5V/ di v
R
LOAD
= 80m
SOFT-START
MAX1987/ 88 toc22
100s/ di v
0
A
B
C
D
5V
0
10A
0
0
BOOT
VID
A. V
SHDN
= 0 TO 5V, 5V/ di v
B. V
OUT
= 0 TO 1.372V TO 0.844V, 500mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
R
LOAD
= 80m
SYSTEM POWER-OK
MAX1987/ 88 toc23
20s/ di v
0
A
B
C
D
5V
0
5V
BOOT
(1.372V)
HIGH FREQ VID
(1.356V)
LOW FREQ VID
(0.844V)
A. V
SYSPOK
= 0 TO 5V, 5V/ di v
B. HIGH FREQ: V
OUT
= 1.356V, 200mV/ di v
C. LOW FREQ: V
OUT
= 0.844V, 200mV/ di v
D. CLKEN, 5V/ di v
IMVPOK DELAY
MAX1987/ 88 toc24
1ms/ di v
0
0
A
B
C
D
5V
0
0
5V
5V
BOOT
(1.372V)
A. V
SHDN
= 0 TO 5V, 5V/ di v
B. V
OUT
= 0 TO 0.844V, 1V/ di v
C. CLKEN, 5V/ di v
D. IMVPOK, 5V/ di v
CC
= V
DD
CC
0.748V, T
A
0
0.2
0.6
0.4
0.8
1.0
INDUCTOR CURRENT DIFFERENCE
vs. LOAD CURRENT
M
A
X
1
9
8
7
/
8
8
to
c
2
0
LOAD CURRENT (A)
I
L
(
C
S
)

-

I
L
(
C
M
)

(
A
)
0 20 10 30 40
PSI = GND
PSI = V
CC
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
12 ______________________________________________________________________________________
SHUTDOWN SEQUENCE
MAX1987/ 88 toc25
40s/ di v
0
0.84V
0
0
A
B
C
D
E
5V
5V
0
5V
0
5V
A. V
SHDN
= 5V TO 0, 5V/ di v
B. V
OUT
= 0.844V TO 0, 500mV/ di v
C. CLKEN, 5V/ di v
D. IMVPOK, 5V/ di v
E. DDO, 5V/ di v
R
LOAD
= 80m
SOFT SHUTDOWN
MAX1987/ 88 toc26
40s/ di v
0
0.84V
0
A
B
C
D
5V
0
0
A. V
SHDN
= 5V TO 0, 5V/ di v
B. V
OUT
= 0.844V TO 0, 500mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
R
LOAD
= 80m
LOAD TRANSIENT
(V
OUT
= 1. 356V)
MAX1987/ 88 toc27
40s/ di v
0
1.356V
A
B
C
D
25A
0
0
A. I
OUT
= 0 TO 25A, 20A/ di v
B. V
OUT
= 1.356V TO 1.281V, 50mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
LOAD TRANSIENT
(V
OUT
= 0. 844V)
MAX1987/ 88 toc28
40s/ di v
0
0.844V
A
B
C
D
10A
0
0
A. I
OUT
= 0 TO 10A, 10A/ di v
B. V
OUT
= 0.844V TO 0.814V, 20mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
ENTERING DEEP-SLEEP MODE
MAX1987/ 88 toc29
20s/ di v
0
1.350V
1.318V
A
B
C
D
5V
0
0
A. V
DPSLP
= 5V TO 0, 5V/ di v
B. V
OUT
= 1.350V TO 1.318V, 50mV/ di v
C. LXM, 10V/ di v
D. LXS, 10V/ di v
SUS = GND, I
OUT
= 1A
EXITING DEEP-SLEEP MODE
MAX1987/ 88 toc30
20s/ di v
0
1.351V
1.318V
A
B
C
D
5V
0
0
A. V
DPSLP
= 0 TO 5V, 5V/ di v
B. V
OUT
= 1.318V TO 1.351V, 50mV/ di v
C. LXM, 10V/ di v
D. LXS, 10V/ di v
SUS = GND, I
OUT
= 1A
CC
= V
DD
CC
0.748V, T
A
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 13
DEEP-SLEEP TRANSITION
MAX1987/ 88 toc31
40s/ di v
0
1.350V
1.318V
A
B
C
D
5V
0
0
A. V
DPSLP
= 5V TO 0, 5V/ di v
B. V
OUT
= 1.350V TO 1.318V, 50mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
SUS = GND, I
OUT
= 1A
ENTERING SUSPEND MODE
MAX1987/ 88 toc32
40s/ di v
0
0.751V
1.318V
A
B
C
D
5V
0
0
A. V
SUS
= 0 TO 5V, 5V/ di v
B. V
OUT
= 1.318V TO 0.751V, 500mV/ di v
C. LXM, 10V/ di v
D. LXS, 10V/ di v
DPSLP = GND, I
OUT
= 1.0A
EXITING SUSPEND MODE
MAX1987/ 88 toc33
40s/ di v
0
0.751V
1.318V
A
B
C
D
5V
0
0
A. V
SUS
= 5V TO 0, 5V/ di v
B. V
OUT
= 0.751V TO 1.318V, 500mV/ di v
C. LXM, 10V/ di v
D. LXS, 10V/ di v
DPSLP = GND, I
OUT
= 1A
SUSPEND TRANSITION
MAX1987/ 88 toc34
100s/ di v
0
0.751V
1.318V
A
B
C
D
5V
0
0
A. V
SUS
= 0 TO 5V, 5V/ di v
B. V
OUT
= 1.318V TO 0.751V, 500mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
DPSLP = GND, I
OUT
= 1A
MAX1987/ 88 toc35
20s/ di v
0
1.356V
A
B
C
D
5V
0
0
A. V
PSI
= 5V TO 0, 5V/ di v
B. V
OUT
= 1.356V, 50mV/ di v
C. LXM, 10V/ di v
D. LXS, 10V/ di v
I
OUT
= 1A
PSI TRANSITION
CC
= V
DD
CC
0.748V, T
A
PRELI MI NARY
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Pin Descript ion
MAX1987/ 88 toc37
20s/ di v
0
1.356V
1.228V
A
B
C
D
1V
0
0
A. V
D3
= 0 TO 1V, 1V/ di v
B. V
OUT
= 1.356V TO 1.228V, 100mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
DYNAMIC VID TRANSITION
(D3 = 128mV)
CC
= V
DD
CC
0.748V, T
A
MAX1987/ 88 toc36
20s/ di v
0
1.356V
1.340V
A
B
C
D
1V
0
0
A. V
D0
= 0 TO 1V, 1V/ di v
B. V
OUT
= 1.356V TO 1.340V, 20mV/ di v
C. I
LM
, 10A/ di v
D. I
LS
, 10A/ di v
DYNAMIC VID TRANSITION
(D0 = 16mV)
PIN NAME FUNCTION
1 TI M E
Slew-Rate Adjustment Pin. Connect a resistor from TI M E to G ND to set the internal slew-rate clock. A 235k
to 23.5k resistor sets the clock from 64kHz to 640kHz, f
SLEW
= 320kHz 47k/R
TI M E
.
2 TO N
O n-Time Selection Control I nput. This four-level input sets the K -factor value ( Table 3) used to determine the
DH on-time ( see the O n-Tim e O ne-Shot section) : G ND = 1000kHz ( untested) , REF = 550kHz,
open = 300kHz, V
CC
= 200kHz per phase
3, 4, 5
B0, B1,
B2
Boot-M ode Voltage Select I nputs. B0 to B2 are four-level digital inputs that select the boot-mode VI D code
( Table 6) for the boot-mode multiplexer inputs. During power-up, the boot-mode VI D code is delivered to the
DAC ( see the Internal M ultiplexers section) .
6, 7, 8
S0, S1,
S2
Suspend-M ode Voltage Select I nputs. S0 to S2 are four-level digital inputs that select the suspend-mode VI D
code ( Table 5) for the suspend-mode multiplexer inputs. I f SUS is high, the suspend-mode VI D code is
delivered to the DAC ( see the Internal M ultiplexers section) , overriding any other voltage setting ( Figure 9) .
9 SHDN
Shutdown Control I nput. This input cannot withstand the battery voltage. Connect to V
CC
for normal
operation. Connect to ground to put the I C into its 1A shutdown state. During the transition from normal
operation to shutdown, the output voltage is ramped down at the output voltage slew rate programmed by
the TI M E pin. I n shutdown mode, DLM and DLS are forced to V
DD
to clamp the output to ground. Forcing
SHDN to 12V~ 15V disables both overvoltage protection and undervoltage protection circuits, disables
overlap operation, and clears the fault latch. Do not connect SHDN to >15V.
10 REF
2V Reference O utput. Bypass to G ND with a 0.22F or greater ceramic capacitor. The reference can source
100A for external loads. Loading REF degrades output-voltage accuracy according to the REF load
regulation error.
11 I LI M
Current-Limit Adjustment. The current-limit threshold defaults to 30mV if I LI M is connected to V
CC
. I n
adjustable mode, the current-limit threshold voltage is precisely 1/20th the voltage seen at I LI M over a
200mV to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately V
CC
- 1V.
PRELI MI NARY
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Pin Descript ion (cont inued)
PIN NAME FUNCTION
12 V
CC
Analog Supply Voltage I nput for PWM Core. Connect V
CC
to the system supply voltage ( 4.5V to 5.5V) with a
series 10 resistor. Bypass to G ND with a 1F or greater ceramic capacitor, as close to the I C as possible.
13 G ND Analog G round. Connect the M AX1987/M AX1988s exposed pad to analog ground.
14 CCV
Voltage I ntegrator Capacitor Connection. Connect a 47pF to 1000pF ( 270pF typ) capacitor from CCV to
analog ground ( G ND) to set the integration time constant.
15 PO S
Feedback O ffset Adjust Positive I nput. The output shifts by 100% ( typ) of the differential input voltage
appearing between PO S and NEG when DPSLP is low. The common-mode range of PO S and NEG is 0 to
2V. PO S and NEG should be generated from resistor-dividers from the output.
16 NEG
Feedback O ffset Adjust Negative I nput. The output shifts by 100% ( typ) of differential input voltage
appearing between PO S and NEG when DPSLP is low. The common-mode range of PO S and NEG is 0 to
2V. PO S and NEG should be generated from resistor-dividers from the output.
17 CCI
Current Balance Compensation. Connect a 470pF capacitor between CCI and FB ( see the C urrent Balance
C om pensation section) . An additional 470k to 1M resistor between CCI and FB for low-frequency
operation.
18 FB
Feedback I nput. FB is internally connected to both the feedback input and the output of the voltage-
positioning op amp ( Figure 2) . Connect a resistor between FB and O AI N- ( Figure 1) to set the voltage-
positioning gain ( see the Setting Voltage Positioning section) .
19 O AI N-
Dual-M ode O p Amp I nverting I nput and O p Amp Disable I nput. When using the internal op amp for
additional voltage-positioning gain ( Figure 1) , connect to the negative terminal of the current-sense resistor
through a 1.0k 1% resistor as described in the Setting Voltage Positioning section. Connect O AI N- to V
CC
to disable the op amp. The logic threshold to disable the op amp is approximately V
CC
- 1V.
20 O AI N+
O p Amp Noninverting I nput. When using the internal op amp for additional voltage-positioning gain
( Figure 1) , connect to the positive terminal of the current-sense resistor through a resistor as described in the
Setting Voltage Positioning section.
21 PSI
Power-Status I ndicator I nput. When PSI is pulled low, the M AX1987/M AX1988 immediately enter pulse-
skipping operation, blank the I M VPO K output high, and blank the CLKEN output low.
22 SYSPO K
System Power-G ood I nput. Primarily, SYSPO K serves as the wired NO R junction of the open-drain power-
good signals for the V
CCP
and V
CCM CH
supplies. A falling edge on SYSPO K shuts down the
M AX1987/M AX1988 and sets the fault latch. Toggle SHDN or cycle V
CC
power below 1V to restart the
controller.
23 I M VPO K
O pen-Drain Power-G ood O utput. After output voltage transitions, except during power-up and power-down,
if O UT is in regulation, then I M VPO K is high impedance. I M VPO K is high impedance whenever the slew rate
control is active ( output voltage transitions) . I M VPO K is forced low in shutdown. A pullup resistor on I M VPO K
causes additional finite shutdown current. I M VPO K also reflects the state of SYSPO K and includes a 3ms
( min) delay for power-up.
24 CLKEN
Clock Enable Logic O utput. This inverted logic output indicates when SYSPO K is high and the output voltage
sensed at FB is in regulation. CLKEN is forced low during VI D transitions.
2530 D5D0
Low-Voltage VI D DAC Code I nputs. D0 is the LSB, and D5 is the M SB of the internal 6-bit VI D DAC ( Table 4) .
The D0D5 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with
the CPU. I n all normal active modes ( modes other than suspend mode and boot mode) , the output voltage is
set by the VI D code indicated by the D0D5 logic-level voltages on D0D5. I n suspend mode ( SUS = high) ,
the decoded state of the four-level S0 to S2 inputs sets the output voltage. I n boot mode ( see the Pow er-U p
Sequence section) , the decoded state of the four-level B0 to B2 inputs set the output voltage.
PRELI MI NARY
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Pin Descript ion (cont inued)
PIN NAME FUNCTION
31 DDO
Driver-Disable O utput. This TTL logic output can be used to disable the driver outputs on slave-switching
regulator controllers, such as the M AX1980 forcing a high-impedance condition and making it possible for
the M AX1987/M AX1988 master controller to operate in low-current SK I P mode. DDO goes low 32 R
TI M E
clock cycles after the M AX1987/M AX1988 complete a transition to the suspend mode or deep-sleep voltage
( see the Low -Pow er Pulse Skipping section) . Another 32 clock cycles later, the M AX1987/M AX1988 enter
automatic pulse-skipping operation.
32 BSTM
M ain Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM pullup
current to be adjusted.
33 LXM M ain I nductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver.
34 DHM M ain High-Side G ate-Driver O utput Swings LXM to BSTM
35 DLM
M ain Low-Side G ate Driver O utput. DLM swings from PG ND to V
DD
. DLM is forced high after the
M AX1987/M AX1988 power down ( SHDN = G ND) or when the M AX1987 detects an overvoltage fault. The
M AX1988 does not include overvoltage protection.
36 V
DD
Supply Voltage I nput for the DLM and DLS G ate Drivers. Connect to the system supply voltage ( 4.5V to
5.5V) . Bypass V
DD
to PG ND with a 2.2F or greater ceramic capacitor, as close to the I C as possible.
37 PG ND Power G round. G round connection for the low-side gate drivers DLM and DLS.
38 DLS
Secondary Low-Side G ate Driver O utput. DLS swings from PG ND to V
DD
. DLS is forced high after the
M AX1987/M AX1988 power down ( SHDN = G ND) or when the M AX1987 detects an overvoltage fault. The
M AX1988 does not include overvoltage protection.
39 DHS Secondary High-Side G ate-Driver O utput Swings LXS to BSTS
40 LXS Secondary I nductor Connection. LXS is the internal lower supply rail for the DHS high-side gate driver.
41 BSTS
Secondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the DHS pullup
current to be adjusted.
42 V+
Battery Voltage Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely proportional
to input voltage over a range of 2V to 28V.
43 SUS
Suspend-M ode Control I nput. When SUS is high, the regulator slews to the suspend voltage level. This level
is set with four-level logic signals at the S0 to S2 inputs. 32 clock cycles after the transition to the suspend-
mode voltage is completed, DDO goes low ( see the Low -Pow er Pulse Skipping section) . Another 32 clock
cycles later, the M AX1987/M AX1988 are allowed to enter pulse-skipping operation.
44 DPSLP
Deep-Sleep Control I nput. When DPSLP is low, the system enters the deep-sleep state and the regulator
applies the appropriate deep-sleep offset. The M AX1987/M AX1988 add the offset measured at the PO S and
NEG pins to the output. 32 clock cycles after the deep-sleep transition is completed, DDO goes low ( see the
Low -Pow er Pulse Skipping section) . Another 32 clock cycles later, the M AX1987/M AX1988 are allowed to
enter pulse-skipping operation.
45 CM P M ain I nductor Positive Current-Sense I nput
46 CM N M ain I nductor Negative Current-Sense I nput
47 CSN Secondary I nductor Negative Current-Sense I nput
48 CSP Secondary I nductor Positive Current-Sense I nput
PRELI MI NARY
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Table 1. Component Selection for Standard Multiphase Applications (Figure 1)
DESIGNATION COMPONENT
I nput Voltage Range* 7V to 24V
VI D O utput Voltage ( D5D0) 1.356V ( D5D0 = 010110)
Boot Voltage ( B0 to B2) 1.372V ( B2 = REF, B1 = REF, B0 = REF)
Suspend Voltage ( S0 to S2) 0.748V ( S2 = V
CC
, S1 = V
CC
, S0 = G ND)
Deep-Sleep O ffset Voltage ( PO S, NEG ) 2.7%
M aximum Load Current ( typ) 40A
I nductor ( L
M
, L
S
)
0.6H
Panasonic ETQ P1H0R6BFA or Sumida CDEP134H-0R6
Switching Frequency 300kHz ( TO N = float)
High-Side M O SFET ( N
H
, per phase) Fairchild ( 2) FDS6694 or Siliconix ( 2) Si4860DY
Low-Side M O SFET ( N
L
, per phase) Fairchild ( 2) FDS6688 or Siliconix ( 2) Si4362DY
I nput Capacitance ( C
I N
)
( 6) 10F, 25V
Taiyo Yuden TM K 432BJ106K M or TDK C4532X5R1E106M
O utput Capacitance ( C
O UT
)
( 3) 470F, 2.5V Sanyo 2R5TPD470M or
( 4) 330F, 2.5V Panasonic EEFUEO D33I XR
Current-Sense Resistor ( R
SENSE
, per phase)
1.5m
Panasonic ERJM 1WTJ1M 5U
*Input voltages less than 7V require additional input capacitance.
Table 2. Component Suppliers
MANUFACTURER PHONE WEBSITE
BI Technologies 714-447-2345 ( USA) www.bitechnologies.com
Central Semiconductor 631-435-1110 ( USA) www.centralsemi.com
Coilcraft 800-322-2645 ( USA) www.coilcraft.com
Coiltronics 561-752-5000 ( USA) www.coiltronics.com
Fairchild Semiconductor 888-522-5372 ( USA) www.fairchildsemi.com
I nternational Rectifier 310-322-3331 ( USA) www.irf.com
K emet 408-986-0424 ( USA) www.kemet.com
Panasonic 847-468-5624 ( USA) www.panasonic.com
Sanyo
65-281-3226 ( Singapore)
408-749-9714 ( USA)
www.secc.co.jp
Siliconix ( Vishay) 203-268-6261 ( USA) www.vishay.com
Sumida 408-982-9660 ( USA) www.sumida.com
Taiyo Yuden
03-3667-3408 ( Japan)
408-573-4150 ( USA)
www.t-yuden.com
TDK
847-803-6100 ( USA)
81-3-5201-7241 ( Japan)
www.component.tdk.com
Toko 858-675-8013 ( USA) www.tokoam.com
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PRELI MI NARY
OFF
ON
BSTM
DHM
LXM
DLM
V
DD
V
CC
D0
D1
D3
D4
FB
DAC INPUTS
(1V LOGIC)
REF
C
REF
0.22F
C
CCV
270pF
PGND
V+
CCV
NEG
CCI
S0
S1
SUSPEND INPUTS
(FOUR- LEVEL LOGIC)
POS
CSP
ILIM
TIME
SUS
PSI
MODE
CONTROL
C3
100pF
R
TIME
28k
R8
100k
POWER GROUND
ANALOG GROUND
GND
D5
S2
B0
B1
BOOT INPUTS
(FOUR- LEVEL LOGIC)
B2
OAIN-
OAIN+
CMN
CMP
IMVPOK
SYSPOK
R12
100k
R13
100k
R11
100k
C2
1F
TON
FLOAT
(300kHz)
P
O
W
E
R
-
G
O
O
D
L
O
G
I
C

S
I
G
N
A
L
S
R2
750
R3
1.0k
C
CCI
470pF
R9
30.1k
INPUT*
8V TO 24V
L
M
C
IN
N
H(M)
N
L(M)
R
CM
C
BST(M)
0.1F
R10
10
5V BIAS
SUPPLY
C1
2.2F
DDO
SHDN
DPSLP
CLKEN
MAX1987
MAX1988
L
S
C
IN
N
H(S)
N
L(S)
R
CS
C
BST(S)
0.1F
BST
DIODES
R1
1.5k
R7
100k R4
750
R5
1.0k
R6
2.74k
CSN
BSTS
DHS
LXS
DLS
R
CCI
1M
OUTPUT
C
OUT
C
OUT
* LOWER INPUT VOLTAGES
REQUIRE ADDTIONAL
INPUT CAPACITANCE
D2
R14
4.7k
C4
4.7nF
Figure 1. Standard Application C ircuit (M aster)
Det ailed Descript ion
5V Bias Supply (V
CC
and V
DD
)
The M AX1987/M AX1988 require an external 5V bias sup-
ply in addition to the battery. Typically, this 5V bias sup-
ply is the notebooks 95% efficient 5V system supply.
K eeping the bias supply external to the IC improves effi-
ciency and eliminates the cost associated with the 5V lin-
ear regulator that would otherwise be needed to supply
the PWM circuit and gate drivers. If standalone capability
is needed, the + 5V bias supply can be generated with
an external linear regulator.
The 5V bias supply must provide V
CC
( PWM controller)
and V
DD
( gate-drive power) , so the maximum current
drawn is:
I
BI AS
= I
CC
+ f
SW
( Q
G ( LO W)
+ Q
G ( HI G H)
)
= 10mA to 100mA ( typ)
where I
CC
is 1.7mA ( typ) , f
SW
is the switching frequency,
and Q
G ( LO W)
and Q
G ( HIG H)
are the M O SFET data sheets
total gate-charge specification limits at V
G S
= 5V.
V+ and V
DD
can be connected together i f the i nput
power source is a fixed 4.5V to 5.5V supply. I f the 5V
bias supply is powered up prior to the battery supply,
the enable signal ( SHDN going from low to high) must
be delayed until the battery voltage is present to ensure
startup.
Free-Running, Const ant On-Time PWM
Cont roller wit h I nput Feedforward
The Q uick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-ti me, current-mode regulator
with voltage feedforward ( Figure 2) . This architecture
relies on the output filter capacitors ESR to act as the
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined sole-
ly by a one-shot whose period is inversely proportional
to input voltage, and directly proportional to output volt-
age and the di fference between the mai n and sec-
ondary inductor currents ( see the O n-Tim e O ne-Shot
section) . Another one-shot sets a minimum off-time. The
on-time one-shot is triggered if the error comparator is
low, the low-side switch currents are below the current-
limit threshold, and the minimum off-time one-shot has
timed out. The controller maintains 180 out-of-phase
operation by alternately triggering the main and sec-
ondary phases after the error comparator drops below
the output voltage set point.
On-Time One-Shot (TON)
T he core of each phase contai ns a fast, low-j i tter,
adjustable one-shot that sets the high-side M O SFETs
on-time. The one-shot for the main phase simply varies
the on-time in response to the input and feedback volt-
ages. The main high-side switch on-time is inversely
proportional to the input voltage as measured by the V+
input, and proportional to the feedback voltage ( V
FB
) :
where K is set by the TO N pin-strap connection ( Table
3) and 0.075V is an approximation to accommodate the
expected drop across the low-side M O SFET switch.
The one-shot for the secondary phase varies the on-
time in response to the input voltage and the difference
between the mai n and secondary i nductor currents.
Two identical transconductance amplifiers integrate the
difference between the master and slave current-sense
signals. The summed output is internally connected to
C C I , allowing adjustment of the integration time con-
stant with a compensation network connected between
C C I and FB. The resulting compensation current and
voltage are determined by the following equations:
where Z
CCI
is the impedance at the CCI output.
The secondary on-time one-shot uses this integrated
signal ( V
CCI
) to set the secondary high-side M O SFETs
on-time. When the main and secondary current-sense
signals ( V
CM
= V
CM P
- V
CM N
and V
CS
= V
CSP
- V
CSM
)
become unbalanced, the transconductance amplifiers
adj ust the secondary on ti me, whi ch i ncreases or
decreases the secondary inductor current until the cur-
rent-sense signals are properly balanced:
This algorithm results in a nearly constant switching fre-
quency and balanced inductor currents, despite the
lack of a fixed-frequency clock generator. The benefits
of a constant switching frequency are twofold: first, the
t K
V V
V
K
V V
V
K
I Z
V
M ain O n time SecondaryCurrent
Balance Correction
O N ND
CCI
I N
FB
I N
CCI CCI
I N
( )
.

.
( ) (
)
2
0 075
0 075
_
,
_
,
_
,
+
I g V V g V V
V V I Z
CCI M CM P CM N M CSP CSN
CCI FB CCI CCI
+
( ) ( )
t
K V V
V
O N M AI N
FB
I N
( )
( . )
+ 0 075
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PRELI MI NARYCONFIDENTIAL INFORMATIONRESTRICTED TO INTEL IMVP LICENSEES
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frequency can be selected to avoi d noi se-sensi ti ve
regi ons such as the 455kHz I F band; second, the
inductor ripple-current operating point remains relative-
ly constant, resulting in easy design methodology and
predi ctable output-voltage ri pple. T he on-ti me one-
shots have good accuracy at the operati ng poi nts
speci fi ed i n the Electrical C haracteristics ( 10% at
200kHz and 300kHz, 12% at 550kHz) . O n-ti mes at
operating points far removed from the conditions speci-
fi ed i n the Electrical C haracteristics can vary over a
wider range. For example, the 550kHz setting typically
runs about 10% slower with inputs much greater than
12V due to the very short on-times required.
O n-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical C haracteristics
are influenced by switching delays in the external high-
side M O SFET. Resistive losses, including the inductor,
both M O SFETs, output capacitor ESR, and PC board
copper losses in the output and ground tend to raise
the switching frequency at higher output currents. Also,
the dead-time effect increases the effective on-time,
reduci ng the swi tchi ng frequency. I t occurs only i n
PWM mode ( SU S = low, DPSLP = low) and duri ng
dynamic output voltage transitions when the inductor
current reverses at light or negative load currents. With
reversed inductor current, the inductors EM F causes
LX to go high earlier than normal, extending the on-time
by a period equal to the DH-rising dead time. For loads
above the critical conduction point, where the dead-
time effect is no longer a factor, the actual switching
frequency ( per phase) is:
where V
DRO P1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V
DRO P2
is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and t
O N
is the on-time as deter-
mined above.
Current Balance
Wi thout acti ve current-balance ci rcui try, the current
matching between phases depends on the M O SFETs
on-resistance ( R
DS( O N)
) , thermal ballasting, on-/off-time
matching, and inductance matching. For example, vari-
ation in the low-side M O SFET on-resistance ( ignoring
thermal effects) results in a current mismatch that is
proportional to the on-resistance difference:
Thermal ballasti ng as the loaded M O SFETs heat up
actually i mproves the current balance. The stronger
M O SFET ( the phase with the lower R
DS( O N)
) pulls more
current, whi ch heats up the M O SFET more than the
other phase, increasing the thereby reducing the current
mismatch. Taking thermal effects into account, the on-
resistance of the switching M O SFETs can be determined
by the following equation:
where R
TA( 25)
is the on-resistance at room temperature,
I
L
is the inductor current through the M O SFET, R
JA
( C/W) is the junction-to-ambient thermal resistance of
the M O SFET package, and R
TEM PCO
( 0.5% /C) is the
temperature coefficient of the M O SFET. Thermal ballast-
ing can typically reduce the current mismatch by as
much as a third. Unfortunately, mismatches between on-
times, off-times, and inductor values increase the worst-
case current i mbalance mak i ng i t i mpossi ble to
passively guarantee accurate current balancing.
T he M A X 1987/M A X 1988 i ntegrate the di fference
between the current-sense voltages and adjusts the on-
time of the secondary phase to maintain current bal-
ance. The current balance now relies on the accuracy
of the current-sense resistors instead of the inaccurate,
thermally sensitive on-resistance of the low-side tracking
M O SFETs. With active current balancing, the current
mismatch is simply determined by the current-sense
resistor values and the offset voltage of the transconduc-
tance amplifiers:
where R
SENSE
= R
C M
= R
C S
and V
O S( I BA L)
i s the
current-balance offset speci fi cati on i n the Electrical
C haracteristics.
I I I
V
R
O S BAL LM LS
O S I BAL
SENSE
( )
( )

R
R
R I R R
DS O N
TA
TA L JA TEM PCO
( )
( )
( )
(
25
25
2
1

I I I
R
R
M AI N ND M AI N
M AI N
ND

_
,
1
]
1
1
2
2
1
f
V V
t V V V
SW
O UT DRO P
O N I N DRO P DRO P
+
( )
+
1
1 2
( )
20 ______________________________________________________________________________________
PRELI MI NARY
TON
CONNECTION
FREQUENCY
SETTING
(kHz)
K-FACTOR
(s)
MAX
K-FACTOR
ERROR (%)
V
CC
200 5 10
Float 300 3.3 10
REF 550 1.8 12.5
G ND 1000 1.0 12.5
Table 3. Approximate K-Factor Errors
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different dI /dt for the two phases. The time it
takes the current-balance loop to correct the transient
i mbalance depends on the mi smatch between the
inductor values and switching frequency.
Dual 180Out -of-Phase Operat ion
The two phases in the M AX1987/M AX1988 operate 180
out-of-phase to mi ni mi ze i nput and output fi lteri ng
requirements, reduce electromagnetic interference ( EM I) ,
and improve efficiency. This effectively lowers component
count reducing cost, board space, and component
power requirements making the M AX1987/M AX1988
ideal for high-power, cost-sensitive applications.
Typically, switching regulators provide transfer power
usi ng only one phase i nstead of di vi di ng the power
among several phases. I n these applications, the input
capaci tors must support hi gh-i nstantaneous current
requirements. The high RM S ripple current can lower
efficiency due to I
2
R power loss associated with the
i nput capaci tor s effecti ve seri es resi stance ( ESR ) .
Therefore, the system typi cally requi res several low-
ESR input capacitors in parallel to minimize input volt-
age ripple, to reduce ESR-related power losses, and to
meet the necessary RM S ripple-current rating.
With the M AX1987/M AX1988, the controller shares the
current between two phases that operate 180 out-of-
phase, so the high-side M O SFETs never turn on simulta-
neously duri ng normal operati on. The i nstantaneous
input current of either phase is effectively halved, result-
ing in reduced input-voltage ripple, ESR power loss, and
RM S ripple current ( see the Input C apacitor Selection
secti on) . T herefore, the same performance can be
achieved with fewer or less expensive input capacitors.
Transient Overlap Operat ion
When a transient occurs, the response time of the con-
troller depends on how quickly it can slew the inductor
current. M ultiphase controllers that remain 180 out-of-
phase when a transient occurs actually respond slower
than an equivalent single-phase controller. I n order to
provi de fast transi ent response, the M A X 1987/
M AX1988 support a phase overlap mode that allows
the individual phases to operate simultaneously when
heavy load transients are detected, effectively reducing
the response time. After either high-side M O SFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the con-
troller simultaneously turns on both high-side M O SFETs
during the next on-time cycle. This maximizes the total
i nductor current slew rate. The phases remai n over-
lapped until the output voltage exceeds the regulation
voltage after the minimum off-time expires.
After the phase overlap mode ends, the controller automat-
ically begins with the opposite phase. For example, if the
secondary phase provided the last on-time pulse before
overlap operation began, the controller starts switching
with the main phase when overlap operation ends.
I nt egrat or Amplifiers/Out put
Volt age Offset s
Two transconductance amplifiers provide a fine adjust-
ment to the output regulati on poi nt ( Fi gure 2) . O ne
amplifier forces the DC average of the feedback volt-
age to equal the VI D DAC setting. The second amplifier
is used to create small positive or negative offsets from
the VI D DAC setting, using the PO S and NEG pins.
The feedback amplifier integrates the feedback volt-
age, allowing accurate DC output voltage regulation
regardless of the output ripple voltage. The feedback
amplifier has the ability to shift the output voltage by
8% . The di fferenti al i nput voltage range i s at least
80mV total, including DC offset and AC ripple. The
i ntegrati on ti me constant can be set easi ly wi th one
capaci tor at the C C V pi n. Use a capaci tor value of
47pF to 1000pF ( 270pF typ) .
The PO S/NEG amplifier is used to add small offsets to
the VI D DAC setti ng i n deep-sleep mode ( DPSLP =
low) . The offset amplifier is summed directly with the
feedback voltage, making the offset gain independent
of the DAC code. This amplifier has the ability to offset
the output by 200mV. To create an output offset, bias
PO S and NEG to a voltage ( typically V
O UT
or REF) with-
in their 0 to 2V common-mode range, and offset them
from one another with a resistive divider ( Figure 1) . I f
V
PO S
is higher than V
NEG
, then the output is shifted in
the positive direction. I f V
NEG
is higher than V
PO S
, then
the output is shifted in the negative direction. The out-
put offset equals the voltage difference from PO S to
NEG .
Forced-PWM Operat ion (Normal Mode)
During normal mode, when the CPU is actively running
( SUS = low, DPSLP = high, PSI = high) , the M AX1987/
M AX1988 operate with the low-noise forced-PWM con-
trol scheme. Forced-PWM operation disables the zero-
crossing comparator, forcing the low-side gate-drive
waveform to constantly be the complement of the high-
side gate-drive waveform. The benefit of forced-PWM
mode is to keep the switching frequency fairly constant.
Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 100mA,
dependi ng on the external M O SFET s and swi tchi ng
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 21
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
22 ______________________________________________________________________________________
MAX1987
MAX1988
CSN
CSP
CMP
CMN
VCC
REF
GND
CCV
POS
NEG
FB
OAIN+
OAIN-
TIME
6 BITS
BLANK
SKIP
ILIM
19R
R
REF
(2.0V)
SHDN
REF
G
m
G
m
DPSLP
R- 2R
DAC
INTERNAL MULTIPLEXERS, MODE
CONTROL, AND SLEW- RATE CONTROL
B
0

T
O

B
2
S
0

T
O

S
2
D
0
D
5
S
U
S
S
Y
S
P
O
K
P
S
I
D
D
0
0.9 x REF 1.1 x REF
SYSPOK
CLKEN
IMVPOK
STARTUP
DELAY
Q
Q
T
CMP
CMN
SKIP
FAULT
1.5mV
S
R
Q
R
S
Q
MAIN
MAIN
ON- TIME
ONE- SHOT
TRIG Q
ON- TIME
ONE- SHOT
TRIG Q
BSTM
TON
V+
CCI
DHM
LXM
V
DD
DLM
PGND
MAIN PHASE
DRIVERS
TRIG
Q
ONE- SHOT
MINIMUM
OFF- TIME
SECONDARY PHASE
DRIVERS
FB
G
m
G
m
CMP
CSP
CMN
CSN
BSTS
DHS
LXS
DLS
Figure 2. M AX1987/M AX1988 Functional D iagram
frequency. To maintain high efficiency under light-load
conditions, the M AX1987/M AX1988 automatically switch
to the low-power pulse-skipping control scheme after
entering suspend or deep-sleep mode.
Duri ng output voltage and mode transi ti ons ( PSI =
high) , the M AX1987/M AX1988 use forced-PWM opera-
tion to ensure fast, accurate transitions. Since forced-
PWM operation disables the zero-crossing comparator,
the inductor current reverses under light loads, quickly
discharging the output capacitors. The controller main-
tains forced-PWM operation for 32 clock cycles ( set by
R
TI M E
) after the controller sets the last DAC code value
to guarantee the output voltage settles properly before
entering pulse-skipping operation.
Low-Power Pulse Skipping
Duri ng deep-sleep mode ( DPSLP = low) , low-power
suspend ( SUS = high) , or pulse-skipping override mode
( PSI = low) , the M AX1987/M AX1988 use an automatic
pulse-ski ppi ng control scheme, alternately swi tchi ng
both phases in order to maintain the current balance.
For deep-sleep mode, when the CPU pulls DPSLP low,
the M A X1987/M A X1988 shi ft the output voltage to
incorporate the offset voltage set by the PO S and NEG
inputs ( Figure 3) . 32 R
TI M E
clock cycles after DPSLP
goes low, the controller pulls the driver-disable output
( DDO) low. An additional 30 R
TI M E
clock cycles later,
the M A X1987/M A X1988 enter low-power operati on,
allowi ng automati c pulse ski ppi ng under li ght loads.
When the C P U dri ves DPSLP hi gh, the M A X1987/
M AX1988 i mmedi ately enter forced-PWM operati on,
force DDO high, and eliminate the output offset, slew-
i ng the output to the operati ng voltage set by the
D0D5 inputs. When either DPSLP transition occurs,
the M A X 1987/M A X 1988 force I M VP O K hi gh and
CLK EN low for 32 R
TI M E
clock cycles.
When entering suspend mode ( SUS driven high) , the
M AX1987/M AX1988 slew the output down to the sus-
pend output voltage set by S0 to S2 inputs ( Figure 4) .
32 R
T I M E
clock cycles after the slew-rate controller
reaches the last DAC code ( see the O utput Voltage
Transition Tim ing secti on) , the DDO i s asserted low.
A fter an addi ti onal 30 R
T I M E
clock cycles, the
M AX1987/M AX1988 enter low-power operation, allow-
ing pulse skipping under light loads. When the C PU
pulls SUS low, the M A X1987/M A X1988 i mmedi ately
enter forced-PWM operation, force DDO high, and slew
the output up to the operating voltage set by the D0D5
i nputs. When ei ther SU S transi ti on occurs, the
M AX1987/M AX1988 blank I M VPO K and CLKEN, pre-
venting I M VPO K from going low and CLKEN from going
high. The blanking remains active until the slew rate
controller has reached the last DAC code and 32 addi-
tional R
TI M E
clock pulses have passed.
When PSI is pulled low, the M AX1987/M AX1988 over-
ri de forced-PWM operati on and use the automati c
pulse-skipping control scheme regardless of the state
of the SU S and DPSLP control i nputs. O nce PSI i s
pulled low, the controller asserts the driver-disable out-
put ( DDO = low) , forces I M VPO K hi gh, and forces
CLKEN low. When PSI is used during mode transitions,
the constant I M VPO K and CLKEN blanki ng allows
indefinite settling times.
I n applications with more than two phases, the driver-
disable signal is used to force one or more slave regula-
tors into a high-impedance state. When the masters
DDO output is driven low, the slave controller with driver
disable ( M AX1980) forces its DL
( SLAVE)
and DH
( SLAVE)
gate dri vers low, effecti vely di sabli ng the slave con-
troller. D i sabli ng the slave controller allows the
M AX1987/M AX1988 to enter low-power pulse skipping
operation under low-power conditions, improving light-
load efficiency. When DDO is driven high, the slave con-
troller ( M AX1980) enables the drivers, allowing normal
forced-PWM operation. For detailed operation with slave
controllers, refer to the M AX1980 data sheet.
Aut omat ic Pulse-Skipping Swit chover
I n skip mode ( PSI = low, SUS = high, or DPSLP = low) ,
an inherent automatic switchover to PFM takes place at
light loads ( Figure 5) . This switchover is affected by a
comparator that truncates the low-side switch on time at
the inductor currents zero crossing. The zero-crossing
comparator senses the inductor current across the cur-
rent-sense resistors. O nce V
C _P
- V
C _N
drops below
1.5mV ( typ) , the comparator forces DL_ low ( Figure 2) .
This mechanism causes the threshold between pulse-
skipping PFM and nonskipping PWM operation to coin-
ci de wi th the boundary between conti nuous and
discontinuous inductor-current operation. The PFM /PWM
crossover occurs when the load current of each phase is
equal to 1/2 the peak-to-peak ripple current, which is a
function of the inductor value ( Figure 6) . For a battery
input range of 7V to 20V, this threshold is relatively con-
stant, with only a minor dependence on the input voltage
due to the typically low duty cycles.
T he total load current at the P FM /P WM crossover
threshold ( I
LO AD( SK I P)
) is approximately:
where K is the on-time scale factor ( Table 3) .
I
V K
L
V V
V
LO AD SK I P
O UT I N O UT
I N
( )

_
,
_
,
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 23
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
24 ______________________________________________________________________________________
V
OUT
TIME
CLOCK
IMVPOK
LX_
PULSE
SKIPPING
AUTOMATIC PULSE-
SKIPPING
SWITCHOVER
OUTPUT TRANSITION
AND SETTLING
OUTPUT TRANSITION
AND SETTLING
DPSLP
DDO
CLKEN
t
DD0
= 32 CLKS t
SKIP
= 30 CLKS t
BLANK
= 32 CLKS
IMVPOK AND CLKEN
BLANKING
IMVPOK AND CLKEN
BLANKING
V
POS
- V
NEG
OFFSET
Figure 3. M AX1987/M AX1988 D eep Sleep Transition
SUS
V
OUT
TIME
CLOCK
IMVPOK
LX_
PULSE
SKIPPING
AUTOMATIC PULSE-
SKIPPING
SWITCHOVER
OUTPUT SETTLING OUTPUT
TRANSITION
OUTPUT SETTLING OUTPUT
TRANSITION
OUTPUT SET BY S0 TO S2
OUTPUT SET BY D0D5
CLKEN
DDO
16mV PER R
TIME
CYCLE
t
BLANK
= 32 CLKS t
SKIP
= 30 CLKS t
SLEW
t
SLEW t
DD0
= 30 CLKS
IMVPOK AND CLKEN
BLANKING
IMVPOK AND CLKEN
BLANKING
Figure 4. M AX1987/M AX1988 Suspend Transition
For example, i n the standard appli cati on ci rcui t thi s
becomes:
The switching waveforms can appear noisy and asyn-
chronous when light loading activates pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs between
PFM noise and light-load efficiency are made by varying
the inductor value. G enerally, low inductor values pro-
duce a broader efficiency vs. load curve, while higher
values result in higher full-load efficiency ( assuming that
the coil resistance remains fixed) and less output volt-
age ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response, especially at low-input voltage levels.
Current -Limit Circuit
The current-limit circuit employs a unique valley cur-
rent-sensing algorithm that uses current-sense resistors
from CM P to CM N and from CSP to CSN as the current-
sensing elements ( Figure 1) . I f the current-sense signal
of the selected phase is above the current-limit thresh-
old, the PWM controller does not initiate a new cycle
( Fi gure 2) unti l the i nductor current of the selected
phase drops below the valley current-limit threshold.
When either phase trips the current limit, both phases
are effectively current limited since the interleaved con-
troller does not initiate a cycle with either phase.
Si nce only the valley current i s acti vely li mi ted, the
actual peak current i s greater than the current-li mi t
threshold by an amount equal to the i nductor ri pple
current. Therefore, the exact current-limit characteristic
and maximum load capability are a function of the cur-
rent-sense resistance, inductor value, and battery volt-
age. When combined with the undervoltage protection
circuit, this current-limit method is effective in almost
every circumstance.
T here i s also a negati ve current li mi t that prevents
excessive reverse inductor currents when V
O UT
is sink-
ing current. The negative current-limit threshold is set to
approximately 120% of the positive current limit, and
therefore tracks the positive current limit when I LI M is
adjusted. When a phase drops below the negative cur-
rent limit, the controller immediately activates an on-
time pulse DL_ turns off, and DH_ turns on allowing
the inductor current to remain above the negative cur-
rent threshold.
The current-limit threshold is adjusted with an external
resistive voltage-divider at ILIM . The current-limit thresh-
old voltage adjustment range is from 10mV to 75mV. In
the adjustable mode, the current-limit threshold voltage
is precisely 1/20th the voltage seen at ILIM . The thresh-
old defaults to 30mV when I LI M is connected to V
CC
.
The logic threshold for switchover to the 30mV default
value is approximately V
CC
- 1V.
C arefully observe the PC board layout gui deli nes to
ensure that noise and DC errors do not corrupt the cur-
rent-sense si gnals seen by the current-sense i nputs
( CM P, CM N, CSP, CSN) .
MOSFET Gat e Drivers (DH, DL)
T he DH_ and DL_ dri vers are opti mi zed for dri vi ng
moderately sized, high-side and larger, low-side power
M O SFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
V
I N
- V
O UT
differential exists. An adaptive dead-time
circuit monitors the DL_ output and prevents the high-
side FET from turning on until DL_ is fully off. There must
1 3 3 3
0 6
12 1 3
12
6 4
. .
.
.
.
V s
H
V V
V
A

_
,
_
,
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 25
PRELI MI NARY
I
N
D
U
C
T
O
R

C
U
R
R
E
N
T
I
LOAD
= I
PEAK
/ 2
ON- TIME 0 TIME
I
PEAK
L
V
BATT
- V
OUT
i
t
=
Figure 5. Pulse-Skipping/D iscontinuous C rossover Point
I
N
D
U
C
T
O
R

C
U
R
R
E
N
T
I
LIMIT(VALLEY)
= I
LOAD(MAX)

2 - LIR
2
( )
TIME
0
I
PEAK
I
LOAD
I
LIMIT
Figure 6. Valley C urrent-Lim it Threshold Point
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
be a low-resistance, low-inductance path from the DL_
dri ver to the M O SFET gate i n order for the adapti ve
dead-ti me ci rcui t to work properly. O therwi se, the
sense circuitry in the M AX1987/M AX1988 interprets the
M O SFET gate as off while there is actually charge still
left on the gate. Use very short, wide traces ( 50mils to
100mils wide if the M O SFET is 1in from the device) . The
dead time at the other edge ( DH_ turning off) is deter-
mined by a fixed 35ns internal delay.
The internal pulldown transistor that drives DL_ low is
robust, with a 0.4 ( typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive cou-
pli ng from the drai n to the gate of the low-si de
M O SFET s when LX_ swi tches from ground to V
I N
.
Applications with high input voltages and long, induc-
tive DL_ traces can require additional gate-to-source
capacitance to ensure fast rising LX_ edges do not pull
up the low-side M O SFETs gate voltage, causing shoot-
through currents. The capacitive coupling between LX_
and D L_ created by the M O SFET s gate-to-drai n
capacitance ( C
RSS
) , gate-to-source capacitance ( C
I SS
- C
RSS
) , and addi ti onal board parasi ti cs should not
exceed the minimum threshold voltage:
Lot-to-lot variation of the threshold voltage can cause
problems i n margi nal desi gns. T ypi cally, addi ng a
4700pF between DL_ and power ground ( C
NL
in Figure
7) , close to the low-si de M O SFETs, greatly reduces
coupling. Do not exceed 22nF of total gate capacitance
to prevent excessive turn-off delays.
Alternatively, shoot-through currents can be caused by
a combination of fast high-side M O SFETs and slow low-
side M O SFETs. I f the turn-off delay time of the low-side
M O SFET is too long, the high-side M O SFETs can turn
on before the low-side M O SFETs have actually turned
off. Adding a resistor less than 5 in series with BST_
slows down the high-side M O SFET turn-on time, elimi-
nati ng the shoot-through currents wi thout degradi ng
the turn-off time ( R
BST
in Figure 7) . Slowing down the
high-side M O SFET also reduces the LX node rise time,
thereby reduci ng EM I and hi gh-frequency coupli ng
responsible for switching noise.
Volt age-Posit ioning Amplifier
The M AX1987/M AX1988 i nclude an i ndependent op
amp for adding gain to the voltage positioning sense
path. The voltage-posi ti oni ng gai n allows the use of
low-value, current-sense resistors in order to minimize
power dissipation. This 3M Hz gain-bandwidth amplifier
was designed with low offset voltage ( 70V typ) to meet
the I M VP-I V output accuracy requirements.
The inverting ( O AI N-) and noninverting ( O AI N+ ) inputs
are used to differentially sense the voltage across the
voltage-positioning sense resistor. The op amps output is
internally connected to the regulators feedback input
( FB) . The op amp should be configured as a noninvert-
ing, differential amplifier as shown in Figures 1 and 10.
The voltage-positioning slope is set by properly selecting
the feedback resistor connected from FB to O AIN- ( see
the Setting Voltage Positioning section) . For applications
using a slave controller, additional differential input resis-
tors ( summing configuration) should be connected to the
slaves voltage-positioning sense resistor ( Figures 1 and
10) . Summing together both the master and slave cur-
rent-sense signals ensures that the voltage-positioning
slope remains constant when the slave controller is dis-
abled.
I n applications that do not require voltage positioning
gain, the amplifier can be disabled by connecting the
O AI N- pin directly to V
CC
. The disabled amplifiers out-
put becomes high impedance, guaranteeing that the
unused amplifier does not corrupt the FB input signal.
The logic threshold to disable the op amp is approxi -
mately V
CC
- 1V.
Power-Up Sequence
The M AX1987/M AX1988 are enabled when SHDN is dri-
ven high ( Figure 8) . First, the reference powers up. O nce
V V
C
C
G S TH I N
RSS
I SS
( )
<

_
,

26 ______________________________________________________________________________________
MAX1987
MAX1988
V
DD
BST
DH
LX
(R
BST
)*
(C
NL
)*
D
BST
C
BST
C
BYP
INPUT
(V
IN
)
N
H
L
V
DD
DL
PGND
N
L
(R
BST
)* OPTIONAL THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING
NODE RISE TIME.
(CNL)* OPTIONAL THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT
CAN CAUSE SHOOT THROUGH CURRENTS.
Figure 7. O ptional G ate D river C ircuitry
the reference exceeds its undervoltage lockout thresh-
old, the PWM regulator becomes active. The slew-rate
controller ramps up the output voltage in 16mV incre-
ments to the selected boot code value ( B0 to B2, Table
7) . The ramp rate is set with the R
TI M E
resistor ( see the
O utput Voltage Transition Tim ing section) .
SYSPO K serves as the combined power-good input for
V
C C P
and V
C C M C H
. O nce these suppli es are wi thi n
10% of their output voltage, their power-good outputs
become hi gh i mpedance, allowi ng SY SP O K to be
pulled hi gh. Approxi mately 50s after the M AX1987/
M AX1988 detect both a logic high voltage on SYSPO K
and the slew-rate controller reaches the DAC code set
by B0 to B2, the controller pulls CLKEN low and slews
the output to the proper operating voltage ( Table 4) .
When CLKEN goes low, the M AX1987/M AX1988 keep
I M VPO K low for an additional 3ms ( min) , guaranteeing
that the CPU has time to start properly. If the M AX1987/
M AX1988 do not detect a fault, then I M VPO K is pulled
high once the 3ms timer expires.
Power-On Reset
Power-on reset ( PO R) occurs when V
C C
rises above
approximately 2V, resetting the fault latch, activating
boot mode, and preparing the PWM for operation. V
CC
undervoltage lockout ( UVLO ) circuitry inhibits switch-
ing, and forces the DL gate driver high ( to enforce out-
put overvoltage protecti on) . When V
C C
ri ses above
4.25V, the DAC inputs are sampled and the output volt-
age begins to slew to the boot voltage ( Table 7) .
For automatic startup, the battery voltage should be
present before V
CC
. I f the M AX1987/M AX1988 attempt
to bring the output into regulation without the battery
voltage present, the fault latch trips. The SHDN pin can
be toggled to reset the fault latch.
I nput Undervolt age Lockout
During startup, the V
C C
UVLO circuitry forces the DL
gate driver high and the DH gate driver low, inhibiting
switching until an adequate supply voltage is reached.
O nce V
CC
rises above 4.25V, valid transitions detected
at the trigger input initiate a corresponding on-time pulse
( see the O n-Tim e O ne-Shotsection) .
I f the V
C C
voltage drops below 4. 25V, it is assumed
that there is not enough supply voltage to make valid
decisions. To protect the output from overvoltage faults,
DL is forced high in this mode, to force the output to
ground. This results in large negative inductor current
and possibly small negative output voltages. I f V
CC
is
likely to drop in this fashion, the output can be clamped
with a Schottky diode to PG ND to reduce the negative
excursion.
Shut down
When SHDN or SY SP O K goes low, the M A X1987/
M AX1988 enter low-power shutdown mode. I M VPO K is
pulled low and CLKEN is driven high immediately. The
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PRELI MI NARY
VID (D0D5)
V
CCP
V
CORE
V
CCP
POWER- OK
V
CC_MCH
SYSPOK
IMVPOK t
IMVPOK
- 12%
- 12%
V
CC_MCH POWER- OK
SOFT- START
SHDN
CLKEN
t
CLKEN
Figure 8. Pow er-U p Sequence Tim ing D iagram
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output voltage ramps down to 0V in 16mV steps at the
clock rate set by R
TI M E
. When the DAC reaches the 0V
setting, DL goes high, DH goes low, the reference is
turned off, the boot mode latch is cleared, and the sup-
ply current drops to about 1A. When a fault condition
( output undervoltage lockout, thermal shutdown, or a
falli ng edge on SY SP O K ) acti vates the shutdown
sequence, the controller sets the fault latch to prevent
the controller from restarting. To clear the fault latch
and reactivate the M AX1987/M AX1988, toggle SHDN or
cycle V
CC
power below 1V.
When SHDN goes high, the reference powers up, and
after the reference UVLO is passed, the DAC target is
evaluated and swi tchi ng begi ns. The slew-rate con-
troller ramps up from 0V in 16mV steps to the currently
selected boot-code value ( see the Pow er-U p Sequence
section) . There is no traditional soft-start ( variable cur-
rent limit) circuitry, so full output current is available
immediately.
I nt ernal Mult iplexers
The M AX1987/M AX1988 have two unique internal DAC
input multiplexers ( muxes) that can select one of three
di fferent DA C code setti ngs for di fferent processor
states, depending on the power-up sequence and SUS
state. O n startup, the controller selects the DAC code
from the B0 to B2 ( SUS = low) or S0 to S2 ( SUS = high)
input decoder ( Figure 9) . O nce SYSPO K goes high and
the M AX1987/M AX1988 properly regulate to the boot
voltage, a second multiplexer selects the DAC code
from either D0D5 ( SUS = low) or S0 to S2 ( SUS = high) .
DAC I nput s (D0D5)
During normal operation ( SUS = low) , the digital-to-ana-
log converter ( DAC) programs the output voltage using
the D0D5 i nputs. D0D5 are low-voltage ( 1V) logi c
inputs, designed to interface directly with the I M VP-I V
CPU. Do not leave D0D5 unconnected. D0D5 can be
changed while the M AX1987/M AX1988 are active, initi-
ating a transition to a new output voltage level. Change
D 0D 5 together, avoi di ng greater than 1s sk ew
between bits. O therwise, incorrect DAC readings can
cause a partial transition to the wrong voltage level fol-
lowed by the intended transition to the correct voltage
level, lengthening the overall transition time. The avail-
able DAC codes and resulting output voltages ( Table 5)
are compatible with I M VP-I V specification.
Four-Level Logic I nput s
TO N, B0 to B2, and S0 to S2 are four-level logic inputs.
These inputs help expand the functionality of the con-
troller without adding an excessive number of pins. The
four-level inputs are intended to be static inputs. When
left open, an internal resistive voltage-divider sets the
input voltage to approximately 3.5V. Therefore, connect
the four-level logic inputs directly to VCC, REF, or G ND
when selecting one of the other logic levels. See the
Electrical C haracteristics for exact logic-level voltages.
28 ______________________________________________________________________________________
PRELI MI NARY
D0
D1
D2
D3
D4
D5
S0
S1
S2
S0 TO S2
DECODER
IN
OUT
B0
B1
B2
B0 TO B2
DECODER
IN OUT
SUS
SYSPOK
SUSPEND
MUX
BOOT
MUX
OUT 1
0
1
0
SEL
SEL
TRIG Q
t
SYSPOK
ONE- SHOT
OUT DAC
Figure 9. Internal M ultiplexers Block D iagram
PRELI MI NARY
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Table 4. Operating Mode Truth Table
SHDN SYSPOK SUS DPSLP DDO PSI
OUTPUT
VOLTAGE
OPERATING MODE
0 x x x 0 x G ND
Low-Power Shutdown M ode. DL is forced high, DH is
forced low, and the PWM controller is disabled. The
supply current drops to 1A.
1 0 0 x 1 x
B0 to B2
( No offset)
Power-Up M ode. When enabled, the M AX1987/
M AX1988 softly ramp up the output voltage to the
selected boot voltage ( B0 to B2, Table 7) . The
controller remains at the boot voltage until SYSPO K is
driven high ( see the Pow er-U p Sequence section) .
1 1 0 1 1 1
D0D5
( No offset)
Normal O peration. The no-load output voltage is
determined by the selected VI D DAC code ( D0D5,
Table 5) .
1 1 0 1 0 0
D0D5
( No offset)
Pulse-Skipping O verride. When PSI is pulled low, the
M AX1987/M AX1988 immediately enter pulse-skipping
operation allowing automatic PWM /PFM switchover
under light loads. The I M VPO K output is forced high,
and the CLKEN output is forced low as long as PSI is
pulled low.
1 1 0 0 0 x
D0D5
( Plus
offset)
Deep-Sleep M ode. The no-load output voltage is
determined by the selected VI D DAC code ( D0D5,
Table 5) plus the offset voltage set by PO S and NEG .
O peration with automatic PWM /PFM switchover for
pulse-skipping under light loads.
1 x 1 x 0 x
S0 to S2
( No offset)
Suspend M ode. The no-load output voltage is
determined by the selected suspend code ( S0 to S2,
Table 6) , overriding all other active modes of
operation. O peration with automatic PWM /PFM
switchover for pulse-skipping under light loads.
1 0 x x 0 x G ND
Fault M ode. The fault latch has been set by either
UVP, O VP ( M AX1987 only) , thermal shutdown, or a
falling edge on SYSPO K . The controller remains in
FAULT mode until V
CC
power is cycled or SHDN
toggled.
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PRELI MI NARY
Table 5. Output Voltage VID DAC Codes (SUS = Low)
D5 D4 D3 D2 D1 D0
OUTPUT
VOLTAGE (V)
0 0 0 0 0 0 1.708
0 0 0 0 0 1 1.692
0 0 0 0 1 0 1.676
0 0 0 0 1 1 1.660
0 0 0 1 0 0 1.644
0 0 0 1 0 1 1.628
0 0 0 1 1 0 1.612
0 0 0 1 1 1 1.596
0 0 1 0 0 0 1.580
0 0 1 0 0 1 1.564
0 0 1 0 1 0 1.548
0 0 1 0 1 1 1.532
0 0 1 1 0 0 1.516
0 0 1 1 0 1 1.500
0 0 1 1 1 0 1.484
0 0 1 1 1 1 1.468
0 1 0 0 0 0 1.452
0 1 0 0 0 1 1.436
0 1 0 0 1 0 1.420
0 1 0 0 1 1 1.404
0 1 0 1 0 0 1.388
0 1 0 1 0 1 1.372
0 1 0 1 1 0 1.356
0 1 0 1 1 1 1.340
0 1 1 0 0 0 1.324
0 1 1 0 0 1 1.308
0 1 1 0 1 0 1.292
0 1 1 0 1 1 1.276
0 1 1 1 0 0 1.260
0 1 1 1 0 1 1.244
0 1 1 1 1 0 1.228
0 1 1 1 1 1 1.212
D5 D4 D3 D2 D1 D0
OUTPUT
VOLTAGE (V)
1 0 0 0 0 0 1.196
1 0 0 0 0 1 1.180
1 0 0 0 1 0 1.164
1 0 0 0 1 1 1.148
1 0 0 1 0 0 1.132
1 0 0 1 0 1 1.116
1 0 0 1 1 0 1.100
1 0 0 1 1 1 1.084
1 0 1 0 0 0 1.068
1 0 1 0 0 1 1.052
1 0 1 0 1 0 1.036
1 0 1 0 1 1 1.020
1 0 1 1 0 0 1.004
1 0 1 1 0 1 0.988
1 0 1 1 1 0 0.972
1 0 1 1 1 1 0.956
1 1 0 0 0 0 0.940
1 1 0 0 0 1 0.924
1 1 0 0 1 0 0.908
1 1 0 0 1 1 0.892
1 1 0 1 0 0 0.876
1 1 0 1 0 1 0.860
1 1 0 1 1 0 0.844
1 1 0 1 1 1 0.828
1 1 1 0 0 0 0.812
1 1 1 0 0 1 0.796
1 1 1 0 1 0 0.780
1 1 1 0 1 1 0.764
1 1 1 1 0 0 0.748
1 1 1 1 0 1 0.732
1 1 1 1 1 0 0.716
1 1 1 1 1 1 0.700
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PRELI MI NARY
Table 6. Suspend Mode DAC Codes (SUS = High)
S2 S1 S0
OUTPUT
VOLTAGE (V)
G ND G ND G ND 1.452
G ND G ND REF 1.436
G ND G ND O PEN 1.420
G ND G ND V
CC
1.404
G ND REF G ND 1388
G ND REF REF 1.372
G ND REF O PEN 1.356
G ND REF V
CC
1.340
G ND O PEN G ND 1.324
G ND O PEN REF 1.308
G ND O PEN O PEN 1.292
G ND O PEN V
CC
1.276
G ND V
CC
G ND 1.260
G ND V
CC
REF 1.244
G ND V
CC
O PEN 1.228
G ND V
CC
V
CC
1.212
REF G ND G ND 1.196
REF G ND REF 1.180
REF G ND O PEN 1.164
REF G ND V
CC
1.148
REF REF G ND 1.132
REF REF REF 1.116
REF REF O PEN 1.100
REF REF V
CC
1.084
REF O PEN G ND 1.068
REF O PEN REF 1.052
REF O PEN O PEN 1.036
REF O PEN V
CC
1.020
REF V
CC
G ND 1.004
REF V
CC
REF 0.988
REF V
CC
O PEN 0.972
REF V
CC
V
CC
0.956
S2 S1 S0
OUTPUT
VOLTAGE (V)
O PEN G ND G ND 0.940
O PEN G ND REF 0.924
O PEN G ND O PEN 0.908
O PEN G ND V
CC
0.892
O PEN REF G ND 0.876
O PEN REF REF 0.860
O PEN REF O PEN 0.844
O PEN REF V
CC
0.828
O PEN O PEN G ND 0.812
O PEN O PEN REF 0.796
O PEN O PEN O PEN 0.780
O PEN O PEN V
CC
0.764
O PEN V
CC
G ND 0.748
O PEN V
CC
REF 0.732
O PEN V
CC
O PEN 0.716
O PEN V
CC
V
CC
0.700
V
CC
G ND G ND 0.684
V
CC
G ND REF 0.668
V
CC
G ND O PEN 0.652
V
CC
G ND V
CC
0.636
V
CC
REF G ND 0.620
V
CC
REF REF 0.604
V
CC
REF O PEN 0.588
V
CC
REF V
CC
0.572
V
CC
O PEN G ND 0.556
V
CC
O PEN REF 0.540
V
CC
O PEN O PEN 0.524
V
CC
O PEN V
CC
0.508
V
CC
V
CC
G ND 0.492
V
CC
V
CC
REF 0.476
V
CC
V
CC
O PEN 0.460
V
CC
V
CC
V
CC
0.444
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PRELI MI NARY
Table 7. Boot Mode DAC Codes (Power-Up)
B2 B1 B0
OUTPUT
VOLTAGE (V)
G ND G ND G ND 1.708
G ND G ND REF 1.692
G ND G ND O PEN 1.676
G ND G ND V
CC
1.660
G ND REF G ND 1.644
G ND REF REF 1.628
G ND REF O PEN 1.612
G ND REF V
CC
1.596
G ND O PEN G ND 1.580
G ND O PEN REF 1.564
G ND O PEN O PEN 1.548
G ND O PEN V
CC
1.532
G ND V
CC
G ND 1.516
G ND V
CC
REF 1.500
G ND V
CC
O PEN 1.484
G ND V
CC
V
CC
1.468
REF G ND G ND 1.452
REF G ND REF 1.436
REF G ND O PEN 1.420
REF G ND V
CC
1.404
REF REF G ND 1.388
REF REF REF 1.372
REF REF O PEN 1.356
REF REF V
CC
1.340
REF O PEN G ND 1.324
REF O PEN REF 1.308
REF O PEN O PEN 1.292
REF O PEN V
CC
1.276
REF V
CC
G ND 1.260
REF V
CC
REF 1.244
REF V
CC
O PEN 1.228
REF V
CC
V
CC
1.212
B2 B1 B0
OUTPUT
VOLTAGE (V)
O PEN G ND G ND 1.196
O PEN G ND REF 1.180
O PEN G ND O PEN 1.164
O PEN G ND V
CC
1.148
O PEN REF G ND 1.132
O PEN REF REF 1.116
O PEN REF O PEN 1.100
O PEN REF V
CC
1.084
O PEN O PEN G ND 1.068
O PEN O PEN REF 1.052
O PEN O PEN O PEN 1.036
O PEN O PEN V
CC
1.020
O PEN V
CC
G ND 1.004
O PEN V
CC
REF 0.988
O PEN V
CC
O PEN 0.972
O PEN V
CC
V
CC
0.956
V
CC
G ND G ND 0.940
V
CC
G ND REF 0.924
V
CC
G ND O PEN 0.908
V
CC
G ND V
CC
0.892
V
CC
REF G ND 0.876
V
CC
REF REF 0.860
V
CC
REF O PEN 0.844
V
CC
REF V
CC
0.828
V
CC
O PEN G ND 0.812
V
CC
O PEN REF 0.796
V
CC
O PEN O PEN 0.780
V
CC
O PEN V
CC
0.764
V
CC
V
CC
G ND 0.748
V
CC
V
CC
REF 0.732
V
CC
V
CC
O PEN 0.716
V
CC
V
CC
V
CC
0.700
Suspend Mode
When the processor enters low-power suspend mode,
the processor sets the regulator to a lower output volt-
age to reduce power consumpti on. T he M A X1987/
M AX1988 include independent suspend mode output
voltage codes set by the four-level i nputs S0 to S2.
When the CPU suspends operation, SUS is driven high,
overriding the 6-bit VI D DAC code set by either D0D5
( normal operation) or B0 to B2 ( power-up) . The master
controller slews the output to the selected suspend
mode voltage. Duri ng the transi ti on, the M A X1987/
M AX1988 assert forced-PWM operation until 62 R
TI M E
clock cycles ( t
DDO
+ t
SK I P
) after the slew-rate controller
reaches the suspend mode voltage.
When SUS is low during normal operation ( SYSPO K =
high) , the output voltage is dynamically controlled by
the 6-bit VI D DAC inputs ( D0D5) .
Out put Volt age Transit ion Timing
The M AX1987/M AX1988 are designed to perform mode
transitions in a controlled manner, automatically mini -
mizing input surge currents. This feature allows the cir-
cui t desi gner to achi eve nearly i deal transi ti ons,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the I C ideal for
I M VP-I V CPUs.
At the begi nni ng of an output voltage transi ti on, the
M AX1987/M AX1988 blank the IM VPO K and CLKEN out-
puts, preventing them from changing states. I M VPO K
and CLKEN remain blanked during the transition and are
re-enabled 32 clock cycles after the slew-rate controller
has set the final DAC code value. The slew-rate clock
frequency ( set by the resistor R
TI M E
) must be set fast
enough to ensure that the transition is completed within
the maximum allotted time.
The slew-rate controller transitions the output voltage in
16mV increments during soft-start, soft shutdown, and
suspend mode transitions. The total time for a transition
depends on R
TI M E
, the voltage difference, and the accu-
racy of the M AX1987/M AX1988s slew-rate clock, and is
not dependent on the total output capaci tance. The
greater the output capacitance, the higher the surge cur-
rent required for the transition. The M AX1987/M AX1988
automatically control the current to the minimum level
required to complete the transition in the calculated time,
as long as the surge current is less than the current limit
set by I LI M . The transition time is given by:
where f
SLEW
= 320kHz 47k / R
TI M E
, V
O LD
i s the
original DAC setting, and V
NEW
is the new DAC setting.
The additional 2 clock cycles on the falling edge time
are due to internal synchronization delays. See TI M E
Frequency Accuracy in the Electrical C haracteristics for
f
SLEW
limits.
The practical range of R
TI M E
is 23.5k to 235k corre-
sponding with 1.6s to 15.6s per 16mV step. Although
the DAC takes discrete 16mV steps, the output filter
makes the transitions relatively smooth. The average
i nductor current requi red to make an output-voltage
transition is:
I
L
C
O UT
16mV f
SLEW
Out put Overvolt age Prot ect ion
(MAX1987 Only)
The overvoltage protection ( O VP) circuit is designed to
protect the CPU against a shorted high-side M O SFET
by drawing high current and blowing the battery fuse.
The output voltage is continuously monitored for over-
voltage. I f the actual FB voltage exceeds 2V, the O VP
circuit immediately forces the DL low-side gate-driver
high, pulls the DH high-side gate-driver low, sets the
fault latch, and shuts down the PWM controller. This
action turns on the synchronous-rectifier M O SFET with
100% duty and, in turn, rapidly discharges the output fil-
ter capacitor and forces the output to ground. I f the con-
dition that caused the overvoltage ( such as a shorted
hi gh-si de M O SFET) persi sts, the battery fuse blows.
When the fault latch is activated, the controller pulls
I M VPO K low and dri ves CLKEN hi gh. The controller
remains shut down until the fault latch is cleared by tog-
gling SHDN or cycling the V
CC
power supply below 1V.
O vervoltage protecti on can be di sabled through the
NO FAULT test mode ( see the N O FAU LT Test M ode
section) .
Out put Undervolt age Shut down
The output UVP function is similar to foldback-current-
limiting, but employs a timer rather than a variable cur-
rent limit. I f the M AX1987/M AX1988 output voltage is
under 70% of the nominal value, the controller activates
the shutdown sequence and sets the fault latch. O nce
the controller ramps down to the 0V DAC code setting,
it forces the DL low-side gate-driver high, and pulls the
t
f
V V
mV
for V ri g
t
f
V V
mV
for V falling
SLEW
SLEW
NEW O LD
O UT
SLEW
SLEW
O LD NEW
O UT
_
,
_
,
1
]
1
1
16
1
16
2
sin
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DH high-side gate-driver low. Toggle SHDN or cycle
the V
CC
power supply below 1V to clear the fault latch
and reactivate the controller. UVP is ignored during out-
put voltage transi ti ons and remai ns blanked for an
additional 32 clock cycles after the controller reaches
the final DAC code value.
UVP can be disabled through the NO FAULT test mode
( see the N O FAU LT Test M ode section) .
Thermal Fault Prot ect ion
The M AX1987/M AX1988 feature a thermal fault protec-
tion circuit. When the junction temperature rises above
+ 160C, a thermal sensor activates the fault latch and
activates the soft shutdown sequence. O nce the con-
troller ramps down to the 0V DAC code setting, it forces
the DL low-si de gate-dri ver hi gh, and pulls the DH
high-side gate-driver low. Toggle SHDN or cycle the
V
CC
power supply below 1V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15C.
T hermal shutdown can be di sabled through the NO
FAULT test mode ( see the N O FAU LT Test M ode section) .
NO FAULT Test Mode
The latched fault protection features and overlap mode
can compli cate the process of debuggi ng prototype
breadboards since there are ( at most) a few milliseconds
in which to determine what went wrong. Therefore, a No
Fault test mode is provided to disable the overvoltage
protection ( M AX1987) , undervoltage protection, thermal
shutdown, and overlap mode. Additionally, the test mode
clears the fault latch if it has been set. The NO FAULT
test mode is entered by forcing 12V to 15V on SHDN.
Design Procedure
Firmly establish the input-voltage range and maximum
load current before choosi ng a swi tchi ng frequency
and inductor operating point ( ripple-current ratio) . The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
Input-Voltage Range: The maximum value ( V
I N( M AX)
)
must accommodate the worst-case hi gh AC -adapter
voltage. The minimum value ( V
I N( M I N)
) must account for
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. I f there is a choice
at all, lower input voltages result in better efficiency.
Maximum Load Current: There are two values to con-
sider. The peak load current ( I
LO AD( M AX)
) determines
the i nstantaneous component stresses and fi lteri ng
requirements, and thus drives output capacitor selec-
tion, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current ( I
LO AD
)
determi nes the thermal stresses and thus dri ves the
selection of input capacitors, M O SFETs, and other criti-
cal heat-contri buti ng components. M odern notebook
CPUs generally exhibit I
LO AD
= I
LO AD( M AX)
80% .
For multiphase systems, each phase supports a frac-
tion of the load, depending on the current balancing.
When properly balanced, the load current is evenly dis-
tributed among each phase:
Switching Frequency: T hi s choi ce determi nes the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to M O SFET switching losses that are pro-
portional to frequency and V
I N
2
. The optimum frequen-
cy is also a moving target, due to rapid improvements
in M O SFET technology that are making higher frequen-
cies more practical.
Inductor Operating Point: This choice provides trade-
offs between size vs. efficiency and transient response
vs. output noise. Low inductor values provide better
transient response and smaller physical size, but also
result in lower efficiency and higher output noise due to
increased ripple current. The minimum practical induc-
tor value is one that causes the circuit to operate at the
edge of critical conduction ( where the inductor current
just touches zero with every cycle at maximum load) .
I nductor values lower than this grant no further size-
reduction benefit. The optimum operating point is usu-
ally found between 20% and 50% ripple current.
I nduct or Select ion
The switching frequency and operating point ( % ripple
or LI R) determine the inductor value as follows:
Example: I
LO AD( M AX)
= 40A, V
I N
= 12V, V
O UT
= 1.3V,
f
SW
= 300kHz, 30% ripple current or LI R = 0.3.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
L
V V V
V kHz A
H

2 1 3 12 1 3
12 300 40 0 3
0 64
. ( . )
.
.
L
V V
f I LI R
V
V
I N O UT
SWLO AD M AX
O UT
I N
_
,
_
,
2
( )
I I
I
LO AD M AI N LO AD ND
LO AD
( ) ( )

2
2
34 ______________________________________________________________________________________
PRELI MI NARY CONFIDENTIAL INFORMATIONRESTRICTED TO INTEL IMVP LICENSEES
core must be large enough not to saturate at the peak
inductor current ( I
PEAK
) .
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low V
I N
- V
O UT
differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty fac-
tor, which can be calculated from the on time and mini-
mum off-time:
where t
O FF( M I N )
i s the mi ni mum off-ti me ( see the
Electrical C haracteristics section) and K is from Table 3.
The amount of overshoot due to stored inductor energy
can be calculated as:
Set t ing t he Current Limit
T he mi ni mum current-li mi t threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
LO AD( M AX)
minus
half the ripple current; therefore:
where I
LI M I T ( LO W)
equals the mi ni mum current-li mi t
threshold voltage divided by the current-sense resistor
( R
SENSE
) . For the 30mV default setting, the minimum
current-limit threshold is 27mV.
C onnect I LI M to V
C C
for a default 30mV current-limit
threshold. I n adjustable mode, the current-limit thresh-
old is precisely 1/20th the voltage seen at I LI M . For an
adjustable threshold, connect a resistive divider from
REF to G ND with I LI M connected to the center tap. The
external 200mV to 1.5V adjustment range corresponds
to a 10mV to 75mV current-limit threshold. When adjust-
ing the current limit, use 1% tolerance resistors with
approximately 10A of divider current to prevent a sig-
nificant increase of errors in the current-limit tolerance.
Out put Capacit or Select ion
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
I n CPU V
CO RE
converters and other applications where
the output is subject to large load transients, the output
capacitors size typically depends on how much ESR is
needed to prevent the output from di ppi ng too low
under a load transient. I gnoring the sag due to finite
capacitance:
I n non-C PU appli cati ons, the output capaci tors si ze
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tors ESR. When operating multiphase systems out-of-
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For 180 out-
of-phase operation, the maximum ESR to meet ripple
requirements is:
where f
SW
is the switching frequency per phase. The
actual capacitance value required relates to the physical
size needed to achieve low ESR, as well as to the chem-
istry of the capacitor technology. Thus, the capacitor is
usually selected by ESR and voltage rating rather than
by capacitance value ( this is true of polymer types) .
When usi ng low-capaci ty cerami c fi lter capaci tors,
capacitor size is usually determined by the capacity
needed to prevent V
SA G
and V
SO A R
from causi ng
problems duri ng load transi ents. G enerally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem ( see the V
SAG
and V
SO AR
equations
in the Transient Response section) .
R
V
V V
f L
V
V
ESR
RI PPLE
I N O UT
SW
O UT
I N
_
,
_
,
2
R
V
I
ESR
STEP
LO AD M AX
( )
I
I
LI R
LI M I T LO W
LO AD M AX
( )
( )
>

_
,
_
,
2
1
2
V
I L
C V
SO AR
LO AD M AX
O UT O UT
( )
( )
2
2
V
L I
V K
V
t
C V
V V K
V
t
I
C
V K
V
t
SAG
LO AD M AX
O UT
I N
O FF M I N
O UT O UT
I N O UT
I N
O FF M I N
LO AD M AX
O UT
O UT
I N
O FF M I N
_
,
1
]
1
1
_
,
1
]
1
1
+
_
,
1
]
1
1
( )
( )
( ) ( )
( )
( )
( )
2
2
2
2
2
I
I
LI R
PEAK
LO AD M AX
_
,
_
,
( )
2
1
2
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 35
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
Out put Capacit or St abilit y
Considerat ions
For Q uick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
where C
O UT
is the total output capacitance, R
ESR
is the
total equivalent-series-resistance, R
SENSE
is the current-
sense resistance ( R
CM
= R
CS
) , A
VPS
is the voltage posi-
tioning gain, and R
PCB
is the parasitic board resistance
between the output capacitors and sense resistors.
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo PO SC AP, and Panasonic SP
capacitors, in wide-spread use at the time of publica-
tion, have typical ESR zero frequencies below 50kHz.
I n the standard application circuit, the ESR needed to
support a 30mV
P-P
ripple is 30mV/( 40A 0.3) = 2.5m.
Four 330F/2.5V Panasonic SP ( type XR) capacitors in
parallel provide 2.5m ( max) ESR. Their typical com-
bined ESR results in a zero at 40kHz.
C eramic capacitors have a high ESR zero frequency,
but applications with significant voltage positioning can
take advantage of thei r si ze and low ESR. Dont put
high-value ceramic capacitors directly across the out-
put without verifying that the circuit contains enough
voltage positioning and series PC board resistance to
ensure stabi li ty. When only usi ng cerami c output
capacitors, output overshoot ( V
SO AR
) typically deter-
mines the minimum output capacitance requirement.
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load con-
di ti ons, unless a small i nductor value i s used ( hi gh
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
The efficiency penalty for operating at 550kHz is about
3% when compared to the 300kHz circuit, primarily due
to the high-side M O SFET switching losses.
Unstable operation manifests itself in two related but dis-
tinctly different ways: double pulsing and feedback-loop
instability. Double pulsing occurs due to noise on the out-
put or because the ESR is so low that there is not enough
voltage ramp in the output voltage signal. This fools the
error comparator into triggering a new cycle immediately
after the minimum off-time period has expired. Double
pulsing is more annoying than harmful, resulting in noth-
ing worse than increased output ripple. However, it can
indicate the possible presence of loop instability due to
insufficient ESR. Loop instability can result in oscillations
at the output after line or load steps. Such perturbations
are usually damped, but can cause the output voltage to
rise above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transi ent and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. I t can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ri ngi ng after the i ni ti al
step-response under/overshoot.
I nput Capacit or Select ion
T he i nput capaci tor must meet the ri pple current
requirement ( I
RM S
) imposed by the switching currents.
T he M AX1987/M AX1988 operate 180 out-of-phase,
alternating the turn-on times of each phase. This mini-
mizes the input ripple current by dividing the load cur-
rent between the two phases. The I
RM S
requirements
can be determined by the following equation:
The worst-case RM S current requirement occurs when
operating with a 25% duty cycle ( V
I N
= 4V
O UT
) . At this
point, the above equation simplifies to I
RM S
= 0. 25
I
LO AD
. When compared to a single-phase regulator, the
multiphase converter reduces the RM S input current by
at least 30% .
For most applications, nontantalum chemistries ( ceram-
ic, aluminum, or O S-C O N) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. I f the M AX1987/M AX1988 are operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. I n either con-
figuration, choose an input capacitor that exhibits less
than + 10C temperature rise at the RM S input current
for optimal circuit longevity.
Power MOSFET Select ion
M ost of the following M O SFET guidelines focus on the
challenge of obtaining high load-current capability when
using high-voltage ( > 20V) AC adapters. Low-current
applications usually require less attention.
The high-side M O SFET ( N
H
) must be able to dissipate
the resistive losses plus the switching losses at both
V
I N( M I N)
and V
I N( M AX)
. C alculate both of these sums.
I
I
V
V V V
RM S
LO AD
I N
O UT I N O UT
_
,

2
2 2 ( )
f
f
where f
R C
and R R A R R
ESR
SW
ESR
EFF O UT
EFF ESR VPS SENSE PCB
+ +

1
2
36 ______________________________________________________________________________________
Ideally, the losses at V
IN( M IN)
should be roughly equal to
losses at V
I N( M AX)
, with lower losses in between. I f the
losses at V
IN( M IN)
are significantly higher than the losses
at V
I N ( M A X)
, consi der i ncreasi ng the si ze of N
H
.
C onversely, if the losses at V
I N( M AX)
are significantly
higher than the losses at V
IN( M IN)
, consider reducing the
size of N
H
. If V
IN
does not vary over a wide range, the
minimum power dissipation occurs where the resistive
losses equal the switching losses.
Choose a low-side M O SFET that has the lowest possible
on-resistance ( R
DS( O N)
) , comes in a moderate-sized
package ( i.e., one or two 8-pin SO s, DPAK , or D
2
PAK ) ,
and is reasonably priced. M ake sure that the DL gate dri-
ver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-to-
drain capacitor caused by the high-side M O SFET turning
on; otherwise, cross-conduction problems can occur.
MOSFET Power Dissipat ion
Worst-case conduction losses occur at the duty factor
extremes. For the high-side M O SFET ( N
H
) , the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
G enerally, a small hi gh-si de M O SFET i s desi red to
reduce switching losses at high input voltages. However,
the R
DS( O N)
required to stay within package power dis-
si pati on often li mi ts how small the M O SFET can be.
Again, the optimum occurs when the switching losses
equal the conducti on ( R
D S( O N)
) losses. Hi gh-si de
switching losses do not usually become an issue until
the input is greater than approximately 15V.
C alculati ng the power di ssi pati on i n the hi gh-si de
M O SFET ( N
H
) , due to switching losses, is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PC board layout characteristics.
The following switching-loss calculation provides only a
very rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a ther-
mocouple mounted on N
H
:
where C
RSS
is the reverse transfer capacitance of N
H
and I
G ATE
is the peak gate-drive source/sink current
( 1A typ) .
Switching losses in the high-side M O SFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
C V
I N
2
f
SW
switching-loss equation. I f the high-side
M O SFET chosen for adequate R
DS( O N)
at low-battery
voltages becomes extraordinarily hot when biased from
V
I N( M A X)
, consi der choosi ng another M O SFET wi th
lower parasitic capacitance.
For the low-side M O SFET ( N
L
) , the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for M O SFET power dissipation occurs
under heavy overloads that are greater than I
LO AD( M AX)
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, you can over design the circuit to tolerate:
where I
VALLEY( M AX)
is the maximum single-phase val-
ley current allowed by the current-limit circuit, including
threshold tolerance and on-resi stance vari ati on. The
M O SFETs must have a good size heatsink to handle
the overload power dissipation.
C hoose a Schottky diode ( D1) with a forward voltage
low enough to prevent the low-si de M O SFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/6th of the total load current. This diode is optional
and can be removed if efficiency is not critical.
Boost Capacit ors
The boost capacitors ( C
BST
) must be selected large
enough to handle the gate charging requirements of
the hi gh-si de M O SFET s. T ypi cally, 0. 1F cerami c
capacitors work well for low-power applications driving
medium-sized M O SFETs. However, high-current appli-
cations driving large, high-side M O SFETs require boost
capacitors larger than 0. 1F. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side M O SFETs gates:
where N is the number of high-side M O SFETs used for
one regulator, and Q
G ATE
is the gate charge specified
C
N Q
mV
BST
G ATE

200
I I
I LI R
LO AD VALLEY M AX
LO AD M AX
+

_
,
2
2
( )
( )
PD N sistive
V
V
I
R
H
O UT
I N M AX
LO AD
DS O N
( Re )
( )
( )
_
,
1
]
1
1
_
,
1
2
2
PD N Switching
V C f I
I
H
I N M AX RSS SWLO AD
G ATE
( )
( )
( )
2
2
PD N sistive
V
V
I
R
H
O UT
I N
LO AD
DS O N
( Re )
( )
_
,
_
,
2
2
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 37
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
in the M O SFETs data sheet. For example, assume ( 2)
FDS6694 N-channel M O SFETs are used on the hi gh
side. According to the manufacturers data sheet, a sin-
gle FDS6694 has a typical gate charge of 13nC ( V
G S
=
5V) . U si ng the above equati on, the requi red boost
capacitance would be:
Selecti ng the closest standard value, thi s example
requires a 0.1F ceramic capacitor.
Current Balance Compensat ion (CCI )
The current-balance compensati on capaci tor ( C
C C I
)
integrates the difference between the main and sec-
ondary current-sense voltages. This capacitor allows
the user to optimize the dynamics of the current-bal-
ance loop. Large capacitor values increase the integra-
tion time constant, resulting in larger current differences
between the phases during transients. Small capacitor
values allow the current loop to respond cycle-by-cycle,
but can result in small DC current variations between
the phases. For most applications, a 470pF capacitor
from CCI to FB works well.
In pulse-skipping operation, the integration time becomes
much smaller than the off-time. This allows the offset cur-
rent to charge up the C C I compensati on capaci tor,
extending the secondary on-time so that a current imbal-
ance occurs. Add a 470k to 1M resistor between CCI
and FB ( R
CCI
) to cancel the offset current.
Set t ing Volt age Posit ioning
Voltage positioning dynamically lowers the output voltage
in response to the load current, reducing the processors
power dissipation. When the output is loaded, an internal
op amp ( Figures 2 and 10) increases the signal fed back
to the M A X1987/M A X1988s feedback i nput. T he
adjustable amplification allows the use of standard, low-
value, current-sense resistors, significantly reducing the
power dissipated in the current-sense resistors when
compared to connecting the feedback voltage directly to
the current-sense resistor. The load transient response of
this control loop is extremely fast yet well controlled, so
the amount of voltage change can be accurately con-
fined within the limits stipulated in the microprocessor
power-supply guidelines. To understand the benefits of
dynamically adjusting the output voltage, see the Voltage
Positioning and Effective Efficiency section.
The voltage-positioned circuit determines the load current
from the voltage across the current-sense resi stors
( R
SENSE
= R
CM
= R
CS
) connected between the inductors
and output capacitors, as shown in Figure 10. The volt-
age drop can be determined by the following equation:
T he current-sense summati on mai ntai ns the proper
180 out-of-phase operation. Select the positive input
summing resistors using the following equation:
R
A
= R
B
// ( 2R
F
)
Minimum I nput Volt age Requirement s and
Dropout Performance
The output voltage adj ustable range for conti nuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot and the number of phases.
For best dropout performance, use the slower ( 200kHz)
on-time settings. When working with low input voltages,
the duty-factor limit must be calculated using worst-
case values for on- and off-times. M anufacturing toler-
ances and i nternal propagati on delays i ntroduce an
error to the TO N K -factor. This error is greater at higher
frequencies ( Table 3) . Also, keep in mind that transient
response performance of buck regulators operated too
close to dropout is poor, and bulk output capacitance
must often be added ( see the V
SAG
equati on i n the
D esign Procedure section) .
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time ( I
DO WN
)
as much as it ramps up during the on-time ( I
UP
) . The
ratio h = I
UP
/I
DO WN
is an indicator of the ability to slew
the inductor current higher in response to increased
load, and must always be greater than 1. As h approach-
es 1, the absolute minimum dropout point, the inductor
current cannot increase as much during each switching
cycle and V
SAG
greatly increases unless additional out-
put capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between V
SAG
, output
capaci tance, and mi ni mum operati ng voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
V
R
R
I
R
V
R
R
I R
V A I R
VPS
F
B
LO AD
SENSE
VPS
F
B
LO AD SENSE
VPS VPS LO AD SENSE
+
_
,
_
,
_
,
1
2
2
1
2
C
nC
mV
F
BST

2 13
200
0 13 .
38 ______________________________________________________________________________________
where is the number of phases, V
VPS
is the voltage-
positioning droop, V
DRO P1
and V
DRO P2
are the para-
sitic voltage drops in the discharge and charge paths
( see the O n-Tim e O ne-Shot section) , t
O FF( M I N)
is from
the Electrical C haracteristics, and K is taken from Table
3. The absolute minimum input voltage is calculated
with h = 1.
I f the calculated V
I N( M I N)
is greater than the required
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
SAG
. I f operati on near dropout i s anti ci pated,
calculate V
SA G
to be sure of adequate transi ent
response.
Dropout Design Example:
V
FB
= 1.4V
K
M I N
= 3.0s for f
SW
= 300kHz
t
O FF( M I N)
= 400ns
V
VPS
= 3mV/A 30A = 90mV
V
DRO P1
= V
DRO P2
= 150mV ( 30A load)
h = 1.5 and = 2
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
I N
must be greater than 4.1V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 5V.
V
V mV mV
s s
mV mV mV V
I N M I N ( )
.
( . . / . )
.
1
]
1
+
+
2
1 4 90 150
1 2 0 4 1 0 3 0
150 150 90 4 07
V
V mV mV
s s
mV mV mV V
I N M I N ( )
.
( . . / . )
.
1
]
1
+
+
2
1 4 90 150
1 2 0 4 1 5 3 0
150 150 90 4 96
V
V V V
h t
K
V V V
I N M I N
FB VPS DRO P
O FF M I N
DRO P DRO P VPS
( )
( )
_
,
1
]
1
1
1
1
1
1
+
+
1
2 1
1
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 39
R
CM
L
M
MAIN
PHASE
SECONDARY
PHASE
PC BOARD TRACE
RESISTANCE
ERROR
COMPARATOR
R
F

L
S
= L
M R
CS
= R
CM
MAX1987
MAX1988
R
A
R
B
R
A
R
B
OAIN+
OAIN-
FB
Figure 10. Voltage Positioning G ain
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
Applicat ions I nformat ion
Volt age Posit ioning and
Effect ive Efficiency
P oweri ng new mobi le processors requi res careful
attention to detail to reduce cost, size, and power dissi-
pation. As C PUs became more power hungry, it was
recogni zed that even the fastest DC -DC converters
were inadequate to handle the transient power require-
ments. A fter a load transi ent, the output i nstantly
changes by ESR
CO UT
I
LO AD
. Conventional DC-DC
converters respond by regulati ng the output voltage
back to its nominal state after the load transient occurs
( Figure 11) . However, the C PU only requires that the
output voltage remai n above a speci fi ed mi ni mum
value. Dynamically positioning the output voltage to this
lower limit allows the use of fewer output capacitors
and reduces power consumption under load.
For a conventional ( nonvoltage-positioned) circuit, the
total voltage change is:
V
P-P1
= ( ESR
CO UT
I
LO AD
) + V
SAG
+ V
SO AR
where V
SA G
and V
SO A R
are defi ned i n Fi gure 12.
Setti ng the converter to regulate at a lower voltage
when under load allows a larger voltage step when the
output current suddenly decreases ( Figure 11) . So the
total voltage change for a voltage-positioned circuit is:
V
P-P2
= ( ESR
CO UT
I
LO AD
) + V
SAG
+ V
SO AR
where V
SA G
and V
SO A R
are defi ned i n the D esign
Procedure section. Since the amplitudes are the same
for both circuits ( V
P-P1
= V
P-P2
) , the voltage-positioned
circuit tolerates twice the ESR. Since the ESR specifica-
tion is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumpti on at hi gh load currents. Si nce the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the CPU,
although some extra power is dissipated in R
SENSE
. For a
nominal 1.4V, 30A output ( R
LO AD
= 46.7m) , reducing
the output voltage 7.1% gives an output voltage of 1.3V
and an output current of 27.8A.
G i ven these values, C P U power consumpti on i s
reduced from 42W to 36.1W. The additional power con-
sumption of R
SENSE
is:
1.5m x ( 27.8A)
2
= 1.16W
which results in an overall power savings of:
42W - ( 36.1W + 1.16W) = 4.7W
I n effect, 5. 9W of C PU di ssi pati on i s saved and the
power supply dissipates much of the savings, but both
the net savi ngs and the transfer of di ssi pati on away
from the hot CPU are beneficial. Effective efficiency is
defined as the efficiency required of a nonvoltage-posi-
tioned circuit to equal the total dissipation of a voltage-
positioned circuit for a given CPU operating condition.
Calculate effective efficiency as follows:
1) Start with the efficiency data for the positioned cir-
cuit ( V
I N
, I
I N
, V
O UT
, I
O UT
) .
2) M odel the load resistance for each data point:
R
LO AD
= V
O UT
/ I
O UT
3) Calculate the output current that would exist for each
R
LO AD
data point in a nonpositioned application:
I
NP
= V
NP
/ R
LO AD
where V
NP
= 1.6V ( in this example) .
4) Calculate effective efficiency as:
Effective efficiency = ( V
NP
I
NP
) / ( V
I N
I
I N
)
= calculated nonposi ti oned power output
divided by the measured voltage-positioned
power input.
5) Plot the efficiency data point at the nonpositioned
current, I
NP
.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
ing losses and clean, stable operation. The switching
power stage requires particular attention ( Figure 13) . I f
possible, mount all of the power components on the top
si de of the board wi th thei r ground termi nals flush
against one another. Follow these guidelines for good
PC board layout:
1) K eep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
40 ______________________________________________________________________________________
2) C onnect all analog grounds to a separate soli d
copper plane, which connects to the G ND pin of
the M A X1987/M A X1988. T hi s i ncludes the V
C C
bypass capacitor, REF bypass capacitor, compen-
sati on ( C C V) components, and the resi sti ve-
dividers connected to I LI M and PO S/NEG .
3) K eep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards ( 2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces i s a di ffi cult task that must be
approached i n terms of fracti ons of centi meters,
where a single m of excess trace resistance causes
a measurable efficiency penalty.
4) K eep the high-current gate-driver traces ( DL_, DH_,
LX_, and BST_) short and wide to minimize trace
resi stance and i nductance. T hi s i s essenti al for
high-power M O SFETs that require low-impedance
gate drivers to avoid shoot-through currents.
5) C_P, C_N, O AI N+ , and O AI N- connections for cur-
rent limiting and voltage positioning must be made
using K elvin sense connections to guarantee the
current-sense accuracy.
6) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side M O SFET than to
allow distance between the inductor and the low-
side M O SFET or between the inductor and the out-
put filter capacitor.
7) Route high-speed switching nodes away from sen-
sitive analog areas ( REF, CCV, CCI , FB, C_P, C_N,
etc. ) . M ake all pin-strap control input connections
( SHDN, I LI M , B0 to B2, S0 to S2, TO N) to analog
ground or V
CC
rather than power ground or V
DD
.
Layout Procedure
1) Place the power components first, with ground ter-
mi nals adj acent ( low-si de M O SFET source, C
I N
,
C
O UT
, and D1 anode) . I f possible, make all these
connecti ons on the top layer wi th wi de, copper-
filled areas.
2) M ount the controller I C adj acent to the low-si de
M O SFET. The DLM and DLS gate traces must be
short and wide ( 50mils to 100mils wide if the M O SFET
is 1in from the controller IC) .
3) G roup the gate-dri ve components ( BST _ di odes
and capaci tors, V
DD
bypass capaci tor) together
near the controller I C.
4) M ake the DC-DC controller ground connections as
shown in Figures 1 and 13. This diagram can be
vi ewed as havi ng three separate ground planes:
input/output ground, where all the high-power com-
ponents go; the power ground plane, where the
PG ND pin and V
DD
bypass capacitor go; and the
analog ground plane where sensitive analog com-
ponents, the G ND pin, and V
CC
bypass capacitor
go. The G ND plane must meet the PG ND plane only
at a single point directly beneath the I C. The respec-
ti ve ground planes should connect to the hi gh-
power output ground with a short metal trace from
PG ND to the source of the low-side M O SFET ( the
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 41
B
1.4V
1.4V
A
A. CONVENTIONAL CONVERTER (50mV/ di v)
B. VOLTAGE- POSITIONED OUTPUT (50mV/ di v)
VOLTAGE POSITIONING THE OUTPUT
Figure 11. Voltage Positioning the O utput
V
OUT
ESR VOLTAGE STEP
(I
STEP
x R
ESR
)
CAPACITIVE SOAR
(dV/ dt = I
OUT
/ C
OUT
)
RECOVERY
CAPACITIVE SAG
(dV/ dt = I
OUT
/ C
OUT
)
I
LOAD
Figure 12. Transient Response Regions
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
middle of the star ground) . This point must also be
very close to the output capacitor ground terminal.
5) Connect the output power planes ( V
CO RE
and sys-
tem ground planes) di rectly to the output fi lter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC -DC converter circuit
as close to the CPU as is practical.
Chip I nformat ion
TRANSI STO R CO UNT: 9559
PRO CESS: BiCM O S
42 ______________________________________________________________________________________
PRELI MI NARY
5V BIAS
SUPPLY
INPUT
OUTPUT
ACTIVE
VOLTAGE
POSITIONING
IMVP- IV
CPU
MAIN
PHASE
MAIN I
SENSE
SECONDARY I
SENSE
MAX1987
MAX1988
SECONDARY
PHASE
Typical Operat ing Circuit
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
______________________________________________________________________________________ 43
PRELI MI NARY
VIA TO ANALOG
GROUND
VIAS TO POWER
GROUND
POWER GROUND
(2nd LAYER)
POWER GROUND
(2nd LAYER)
CONNECT THE
EXPOSED PAD TO
ANALOG GND
CONNECT GND
AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
PLACE CONTROLLER ON
BACK SIDE WHEN POSSIBLE,
USING THE GROUND PLANE
TO SHIELD THE IC FROM EMI
MAIN PHASE
INDUCTOR
POWER
GROUND
OUTPUT
SECONDARY PHASE
INPUT
CPU
KELVIN SENSE VIAS UNDER
THE SENSE RESISTOR
(REFER TO THE EVALUATION KIT)
C
O
U
T
C
I
N
C
I
N
C
I
N
C
I
N
C
I
N
C
I
N
C
O
U
T
C
O
U
T
C
O
U
T
C
O
U
T
C
O
U
T
INDUCTOR
R
SENSE
R
SENSE
MAX1987/ MAX1988
Figure 13. PC Board Layout Exam ple
Package I nformat ion
( The package drawing( s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
44 ______________________________________________________________________________________
PRELI MI NARY
3
2
,

4
4
,

4
8
L

Q
F
N

.
E
P
S
PROPRIETARY INFORMATION
APPROVAL
TITLE:
DOCUMENT CONTROL NO.
21-0144
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
1
A
REV.
2
e
L
e
L
A1
A
A2
E/2
E
D/2
D
DETAIL A
D2/2
D2
b
L
k
E2/2
E2 (NE-1) X e
(ND-1) X e
e
C
L
C
L
C
L
C
L
k
PRELI MI NARY
M
A
X
1
9
8
7
/
M
A
X
1
9
8
8
M axim cannot assum e responsibility for use of any circuitry other than circuitry entirely em bodied in a M axim product. N o circuit patent licenses are
im plied. M axim reserves the right to change the circuitry and specifications w ithout notice at any tim e.
Maxim I nt egrat ed Product s, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 45
2002 M axim I ntegrated Products Printed USA is a registered trademark of M axim I ntegrated Products.
Package I nformat ion (cont inued)
( The package drawing( s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PROPRIETARY INFORMATION
DOCUMENT CONTROL NO. APPROVAL
TITLE:
A
REV.
2
2
EXPOSED PAD VARIATIONS
21-0144
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
COMMON DIMENSIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.

Dual-Phase, Quick-PWM Controllers For IMVP-IV CPU Core Power Supplies

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Dual-Phase, Quick-PWM Controllers For IMVP-IV CPU Core Power Supplies

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General Descript ion

The M AX1987/M AX1988 are dual-phase, Q uick-PWM ,

Dual-Phase, Quick-PWM Cont rollers for I MVP-I V

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