Chapter 5

CMOS Compatible Bulk Micromachining

John Ojur Dennis, Farooq Ahmad and M. Haris Khir
Additional information is available at the end of the chapter http://dx.doi.org/10.5772/55526

1. Introduction
The last two decades have seen the emergence and prevalence of Micro-Electro-Mechanical Systems (MEMS) technology. The reduction in size, low power consumption and low cost is the ultimate goals of application specific MEMS devices. One way to achieve these goals is the monolithic integration of MEMS technology with the standard integrated circuit (IC) technol ogy. The utilization of the conventional IC technology as a platform for design of the fastgrowing MEMS technology has led to development of numerous devices and technologies in the past years. Much effort has been made and large capital has been invested into mainstream Complementary Metal-Oxide Semiconductor (CMOS) compatible MEMS technology. This approach has enabled MEMS devices to be directly integrated with CMOS circuits, allowing smaller device sizes and higher performances. This integration of MEMS technology with the mainstream CMOS technology is referred to as CMOS-MEMS technology [1]. 1.1. Bulk micromachining technologies Among all micromachining technologies, Bulk micromachining is the oldest one. To make small mechanical components using bulk micromachining technology, substrate material such as silicon wafer is selectively etched. There are two major classes of bulk micromachining: wet bulk micromachining (WBM) and dry bulk micromachining (DBM).WBM gives nice feature resolution and vertical sidewalls for deep trenches in the substrate but have numerous disadvantages such as incompatibility with microelectronic circuits and higher cost due to mask requirement. The fabrication cost, time and simplification of micromachining for MEMS devices is reduced by using dedicated MEMS foundry and making the prototyping develop ment cycle much shorter by reducing number of masks and photolithography steps. CMOS MEMS technology is a good solution for post micromachining because in this technology CMOS circuitry is protected completely by the top metal layer and the same top metal layer

2013 Dennis et al.; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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is used as mask to define MEMS structures in MEMS region during the post-CMOS micro machining. That is why this post micromachining process is known as CMOS-compatible. 1.1.1. Wet bulk micromachining Wet bulk micromachining is done normally with the help of chemicals. In chemical wet etching, the silicon substrate is immersed into the solution of reactive chemicals which etches the exposed regions of substrate at measureable rates. Wet etching typically uses alkaline liquid solvents, such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) to dissolve silicon which has been left exposed by the photolithography masking step. These alkali solvents dissolve the silicon in a highly anisotropic way, with some crystallo graphic orientations dissolving up to 1000 times faster than others. Fig. 1 shows the three major crystal planes in a cubic unit of silicon.

For example in silicon anisotropic etching, planes <111> are etched at slower rate than all other normal to the plane planes. The reasons for the slow etch rate of planes <111> are, high density of silicon atoms For example in silicon anisotropic planes <111> are etched at slower rate than all other exposed to the etchant solutionetching, in this direction and three silicon bonds laying below the plane. example in silicon anisotropic etching, planes<111> <111> are, are etched at slower rate than atoms all other planes. For The reasons for the slow etch rate of planes high density of silicon exposed Fig. 2The (a) shows a schematic and (b) rate three dimensional photo of a typical wet anisotropic etching planes. reasons for the slow etch of planes <111> are, high density of silicon atoms exposed to the etchant solution in this direction and three silicon bonds laying below the plane. Fig. 2 (a) a silicon to of the etchantsubstrate. solution in this direction and three silicon bonds laying below the plane. Fig. 2 (a)

Figure 1. The The three orientations <110>, <111> and <100> are the respective directions normal to the plane Fig. 1: three orientations <110>, <111> and <100> are the respective directions normal to the plane Fig. 1: The three orientations <110>, <111> and <100> are the respective directions

shows a schematic and (b) dimensional of aa typical typical wet anisotropic etching of a silicon shows a schematic and three (b) three dimensionalphoto photo of wet anisotropic etching of a silicon substrate. substrate. (100) (100) (111) (111) Boron-doped Si Boron-doped Si (100) (100) (111) membrane (111) membrane

(111) Backside mask

(111)
(a)

Boron-doped Si membrane Boron-doped Si (b)

membrane (b)
of Si

Backside mask (a)

Fig. 2:2-D (a) 2-D Schematic and (b) 3-D of a typical wet bulk Figure 2. a) Schematic and (b) 3-D diagram of adiagram typical wet bulk micromachining ofmicromachining Si

Fig. 2: (a) 2-D Schematic and (b) 3-D is diagram a typical wet bulk micromachining Si Wet chemical micromachining technology popular of in MEMS industry because of high etch rate of and
selectivity. There is one drawback and that is the mask is also etched during normal etching process so it is suggested to find a mask that doesnt dissolvein orMEMS at least dissolves a much slower rate than Wet chemical micromachining technology is popular industryat because of high etch rate and the silicon substrate. In wet etching, etch rates and selectivity can be modified by various methods selectivity. There is one drawback and that is the mask is also etched during normal etching process such as: (a) chemical composition of etching solution, (b) dopant concentration in the substrate, (c) so it is suggested to find a mask that solution doesntand dissolve least dissolves at a much slower rate than adjusting temperature of etching finally or (d)at Modifying crystallographic planes of the the silicon substrate. In wet etching, etch rates and selectivity can be modified by various methods substrate.

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Wet chemical micromachining technology is popular in MEMS industry because of high etch rate and selectivity. There is one drawback and that is the mask is also etched during normal etching process so it is suggested to find a mask that doesnt dissolve or at least dissolves at a much slower rate than the silicon substrate. In wet etching, etch rates and selectivity can be modified by various methods such as: (a) chemical composition of etching solution, (b) dopant concentration in the substrate, (c) adjusting temperature of etching solution and finally (d) Modifying crystallographic planes of the substrate. Chemical wet etching in bulk micromachining may be further subdivided into two parts: isotropic wet etching where the etch rate is not dependent on crystallographic orientation of the substrate and etching proceeds in all directions at equal rates as shown in Fig.3 (a) and anisotropic wet etching where the etch rate is dependent on crystallographic orientation of substrate as shown in Fig. 3 (b). Often in order to control etching process and uniform etch depths across the wafer, etch stops are used. Generally three types of etch stops are used in micromachining: Dopant etch stops, Electrochemical etch stops and Dielectric etch stop.

Etch masks

Slow w etching rate of (111) planes

(a) Is sotropic
Figure 3. Difference between (a) isotropic and (b) anisotropic wet etching

(b) Anisotropic

Usually in order to control etching process and uniform etch depths across the wafer, etch stops are used. Generally three types of etch stops are used in micromachining: Dopant etch stops, Electrochemical etch stops and Dielectric etch stop [2]. 1.1.2. Dry bulk micromachining Dry etching in bulk micromachining is classified into three groups: Reactive ion etching (RIE), Vapor phase etching and Sputter etching. Reactive ion etching (RIE) uses both physical and chemical mechanisms to achieve high levels of resolution. The process is one of the most diverse and most widely used processes in industry and research. Since the process combines both physical and chemical interactions, the process is much faster. The high energy collision from the ionization helps to dissociate the etchant molecules into more reactive species. In the RIE-process, cations are produced from reactive gases which are accelerated with high energy to the substrate and chemically react with the silicon. The typical RIE gasses for Si are CF4, SF6 and BCl2 + Cl2.

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Both physical and chemical reaction is taking place with the physical part similar to the sputtering deposition. If the ions have high enough energy, they can knock atoms out of the material to be etched without a chemical reaction. It is very complex task to develop dry etch processes that balance chemical and physical etching, since there are many parameters to adjust. By changing the balance it is possible to influence the anisotropy of the etching with the chemical part being isotropic and the physical part highly anisotropic and therefore the combination can form side walls that have shapes from rounded to vertical. A special subclass of RIE which continues to grow rapidly in popularity is deep RIE (DRIE). In this process, etch depths of hundreds of microns can be achieved with almost vertical sidewalls. The primary technology is based on the so-called "Bosch process", named after the German company Robert Bosch which filed the original patent, where two different gas compositions are alternated in the reactor. The first gas composition etches the substrate, and the second gas composition creates a polymer on the surface of the substrate. The polymer is immediately sputtered away by the physical part of the etching, but only on the horizontal surfaces and not the sidewalls. Since the polymer only dissolves very slowly in the chemical part of the etching, it builds up on the sidewalls and protects them from etching and working as pasivation, as illustrated in fig. 4. In fig.4 (a) SF6 is etching the silicon while in fig. 4 (b) C4F8 is playing the role of passivation and in fig. 4 (c) again SF6 is etching. As a result, etching aspect ratios of 1 to 50 can be achieved. The process can easily be used to etch completely through a silicon substrate, and etch rates are 3-4 times higher than wet etching. In the following part more details are given on DRIE. Under our MEMS research group in Universiti Teknologi PETRONAS, high aspect ratio of 3 to 50 m and complete etch through is achieved as shown in fig.5.

mask Substrat e (a)

mask

mask Polymer (b)

mask

mask

mask

(c)

Fig. Illustration of Figure 4. Illustration of etching and4: passivation in DRIE

etching and passivation in DRIE

Vapor phase etching (also called Chemical dry etching) does not use liquid chemicals or etchants. This process involves a chemical reaction between etchant gases to attack the silicon 50 m surface. The chemical dry etching process is usually isotropic and exhibits high selectively. Anisotropic dry etching has the ability to etch with finer resolution and higher aspect ratio than isotropic etching. Due to the directional nature of dry etching, undercutting can be avoided. Some of the ions that are used in chemical dry etching is tetrafluoromethane (CH4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), chlorine gas (Cl2), or fluorine (F2) [3]. Vapor phase etching can be done with simpler equipment than what RIE requires. The two most common vapor phase etching technologies are silicon dioxide etching using hydrogen fluoride (HF) and silicon etching using xenon diflouride (XeF2), both of which are isotropic in nature.

Fig.5: FESEM image of a high aspect ratio plasma etching using DRIE with inhibitor Vapor phase etching (also called Chemical dry etching) does not use liquid chemicals or etchants. This process involves a chemical reaction between etchant gases to attack the silicon surface. The chemical dry etching process is usually isotropic and exhibits high selectively. Anisotropic dry etching has the ability to etch with finer resolution and higher aspect ratio than isotropic etching. Due to the directional nature of dry etching, undercutting can be avoided. Some of the ions that are used in

e (a) (b) (c)

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CMOS Compatible Bulk Micromachining Fig. 4: Illustration of etching and passivation in DRIE

50 m

Fig.5: FESEM image of a high aspect ratio plasma etching using Figure 5. FESEM image of a high aspect ratio plasma etching using DRIE with inhibitor

DRIE with inhibitor

care must becalled taken in the design ofetching) a vapor phase process to not have bi-products Vapor Usually, phase etching (also Chemical dry does not use liquid chemicals or etchants. formedinvolves in the chemical reaction that condense the surface with the etching This process a chemical reaction betweenon etchant gasesand to interfere attack the silicon surface. The process. chemical dry etching process is usually isotropic and exhibits high selectively. Anisotropic dry etching has the ability to etch with finer resolution and higher aspect ratio than isotropic etching. Due Sputter etching is essentially RIE without reactive ions. The systems used are very similar in to the directional nature of dry etching, undercutting can be avoided. Some of the ions that are used in principle to sputtering deposition systems. The big difference is that the substrate is now chemical dry etching is tetrafluoromethane (CH4), sulfur hexafluoride (SF6), nitrogen trifluoride subjected to ion bombardment instead of the material target used in sputter deposition [4]. (NF3), chlorine gas (Cl2), or fluorine (F2) [3]. Vapor phase etching can be done with simpler equipment than what RIE requires. The two most common vapor phase etching technologies are silicon dioxide etching using hydrogen fluoride (HF) and silicon etching using xenon diflouride (XeF2), both of which are isotropic in nature. Usually, care must be taken in the design of a vapor 2. CMOS compatible micromachining phase process to not have bi-products formed in the chemical reaction that condense on the surface and interfere with the etching process. CMOS compatible micromachining is now commonly known as CMOS MEMS technology. During post processing in CMOS MEMS technology, the top metal layer acts as mask to define SputterMEMS etching is essentially RIE without reactive ions. The systems used are very similar in principle structures. For the front side processing of the die no photolithographic steps are to sputtering deposition systems. The big difference is that the substrate is now subjected to ion required. CMOS MEMS technology facilitates the wiring of MEMS structures to integrated bombardment instead of the material target used in sputter deposition [4]. circuits due to many metal layers. Through monolithic integration of the CMOS-MEMS devices with circuits, the parasitic capacitances is reduced and overall high performance devices is 2. CMOS Compatible Micromachining achieved. Dry post CMOS MEMS technologies are divided into two classes: Thin film micro machining technology (Thin-film Post-CMOS MEMS Technology) and DRIE bulk microma CMOSchining compatible micromachining is now MEMS commonly known as CMOS MEMS technology. During technology (DRIE Post-CMOS Technology).

post processing in CMOS MEMS technology, the top metal layer acts as mask to define MEMS structures. For the front side processing of the die no photolithographic steps are required. CMOS 2.1. Thin-film post-CMOS MEMS technology MEMS technology facilitates the wiring of MEMS structures to integrated circuits due to many metal layers. The Through monolithic integration of the CMOS-MEMS circuits, parasitic process flow of thin-film CMOS-MEMS with three metaldevices layers iswith shown in Fig. the 6. The
CMOS circuit region is designed to be covered by the top metal layer and the MEMS structures are also pre-defined by the top metal layer or the other interconnect metal layers. Fig.6 (a) shows the cross-section of the original chip after CMOS foundry fabrication, with a passivation layer on top. Two processing steps are performed only on the front side of the chip. First, the pre-defined MEMS structure is opened by etching the SiO2 dielectric stack layer as shown in Fig.6 (b). This is done by an anisotropic SiO2 plasma etch using Tegal SS110 A DRIE system

Technology). 2.1
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Thin-film Post-CMOS MEMS Technology

Advances in Micro/Nano Systems with and Fabrication Technologies The process flow ofElectromechanical thin-film CMOS-MEMS three metal layers is shown in Fig. 6. The CMOS

circuit region is designed to be covered by the top metal layer and the MEMS structures are also predefined by the top metal layer or the other interconnect metal layers. Fig.6 (a) shows the cross-section of the original chip after CMOS foundry fabrication, with a passivation layer on top. Two processing based onare Bosch technology an anisotropic silicon is performed using the steps performed only on[5]. the Next, front side of the chip. First, theDRIE pre-defined MEMS structure is same opened bysystem etching the SiO2 dielectric stack layer as shown in isotropic Fig.6 (b). This is done by an anisotropic Tegal DRIE as shown in Fig.6 (c), followed by silicon etch, which releases the SiO2 plasma etch using Tegal SS110 A DRIE system based on Bosch technology [5]. Next, an MEMS structure by undercutting the silicon beneath as shown in Fig.6 (d). The depth of the anisotropic silicon DRIE is performed using the same Tegal DRIE system as shown in Fig.6 (c), anisotropic into the silicon controls the gap between the released structure and the silicon followed etch by isotropic silicon etch, which releases the MEMS structure by undercutting the silicon beneath as shown in Fig.6 (d). The depth of the anisotropic etch into the silicon controls the gap substrate. This gap should be large enough to eliminate the parasitic capacitance between the between the released structure and the silicon substrate. This gap should be large enough to eliminate MEMS structures and the silicon substrate. In practice, it is normally on the order of 30 m [6]. the parasitic capacitance between the MEMS structures and the silicon substrate. In practice, it is normally on the order of 30 m [6]. CMOS circuit region MEMS structural region Metal 3 Metal 2 Metal 1

SiO2

(a) Original CMOS-chip Vias

(b) Anisotropic dielectric (SiO2) etch Moveable MEMS structures

(c) Anisotropic silicon etch

(d) Isotropic silicon etch for undercut to release structure.

Figure 6. The process-flow for thin film DRIE post-CMOS micromachining

Fig.6: The process-flow for thin film DRIE post-CMOS micromachining

A resonant field and piezoresistive accelerometer are examples ofas devices using this magnetic technology [7, 8]. sensor This simple fabrication process yields much smaller parasitic effects fabricated using this technology [7, 8]. This simple fabrication process yields much smaller parasitic effects as compared to the other processes such as poly MUMPs and it provides flexible wiring by using the multiple metal layers. However, there are some drawbacks in this technology, which limit the performance of the fabricated accelerometers. First, there is large vertical curling in the comb fingers of the suspended MEMS structures caused by the residual stress gradient existing in the composite SiO2/Al layers as shown in Fig. 7. Additionally, due to different thermal expansion coefficients (TEC) of Al and SiO2, the curled MEMS devices exhibit a strong temperature dependence, which limits their utility. Although particular compensation technology was employed to reduce the structure mismatch by using a specially designed frame, the device fabricated using this thin film process still has a stringent size limit. Second, for sensors which require proof mass like inertial sensors fabricated using this technology, the requirement of holes on the proof mass reduces the proof mass, resulting in a lower mechanical sensitivity of the sensors. To achieve a capacitance change large enough for

A resonant magnetic field sensor and piezoresistive accelerometer are examples of devices fabricated

multiple metal layers. However, there are some drawbacks in this technology, which limit the performance of the fabricated accelerometers. First, there is large vertical curling in the comb fingers of the suspended MEMS structures caused by the residual stress gradient existing in the composite SiO2/Al layers as shown in Fig. 7. Additionally, due to different thermal expansion coefficients (TEC) of Al and SiO2, the curled MEMS devices exhibit a strong temperature dependence, which limits their CMOS Compatible utility. Although particular compensation technology was employed to reduce the structure mismatch Bulk Micromachining http://dx.doi.org/10.5772/55526 by using a specially designed frame, the device fabricated using this thin film process still has a stringent size limit.

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curling in the comb fingers

Fig. 7: FESEM image of typical comb fingers fabricated using thin film CMOS-MEMS technology

Figure 7. FESEM image of typical comb fingers fabricated using thin film CMOS-MEMS technology

Second, for sensors which require proof mass like inertial sensors fabricated using this technology, the requirement of holes on the proof massthe reduces the proof of mass, inmay a lower mechanical the readout circuit to detect, dimension theresulting sensors need to be considerably large, sensitivity of the sensors. To achieve a capacitance change large enough for the readout circuit to which is in conflict with the dimensional limit imposed by the possibility of structure curling. detect, the dimension of the sensors may need to be considerably large, which is in conflict with the Third, in-plane of the thin film structures due to fabrication variations also limits the dimensional limit imposed curling by the possibility of structure curling. Third, in-plane curling of the thin film structures due tosize fabrication variations maximum of the device.also limits the maximum size of the device.

Although therespecific are some specific processes designed for low residual stress thin films [9], Although there are some processes designed for low residual stress thin films [9], Farooq et al utilized the Institute of Microelectronic Systems (MIMOS Bhd) 0.35 m CMOS Farooq etMalaysian al utilized the Malaysian Institute of Microelectronic Systems (MIMOS Bhd) 0.35 m foundry processes to reduce the curling of the MEMS structures by proper design of the structures as CMOS foundry processes to reduce the curling the of MEMS structures by proper design of described in [10]. Fig. 8 shows the successfully released central of shuttle magnetic field sensor theusing structures as described in [10]. Fig. 8 shows the successfully fabricated this process. It can be clearly observed that the curling in the structure released has been central shuttle of significantly reduced as indicated the minor curling theprocess. fingers. InIt addition toclearly the collection of magnetic field sensor by fabricated using in this can be observed that the curling technological data directly from the employed CMOS foundries, systematic post-CMOS process in the structure has to been significantly reduced as indicated by the curling in the fingers. calibration must be conducted characterize the process variations and their effects on minor the MEMS In addition to the collection of technological data directly from the employed CMOS foundries, devices. systematic post-CMOS process calibration must be conducted to characterize the process variations and their effects on the MEMS devices.

Fig. 8: FESEM image showing comb fingers of the central part of a magnetic field sensor
Figure 8. FESEM image showing comb fingers of the central part of a magnetic field sensor

Lastly, since the last release step is an isotropic etch, it undercuts the silicon close to the circuit and structure anchors. The ratiostep of theis vertical and lateral etching rate is approximately 3:5. close To protect the circuit Lastly, since the last release an isotropic etch, it undercuts the silicon to the silicon underneath the circuit region from being etched away during the structure release, the CMOS and structure anchors. The ratio of the vertical and lateral etching rate is approximately 3:5. circuitry must be placed far away from the microstructures, especially when a large separation between the silicon microstructures and substrate needed. region As a result, significant chip area is away wasted due to To protect the underneath the is circuit from being etched during the the protection margin around the MEMS structures. Since the silicon underneath the mechanical anchors of the MEMS structures is also etched away, the suspension of the mechanical structures is softened, which results in a lower mechanical performance and less robustness of the device [10]. 2.2 DRIE Post-CMOS MEMS Technology

To reduce the disadvantages of the above thin-film post-CMOS MEMS process, DRIE post-CMOS MEMS technology is developed to incorporate bulk single crystal silicon (SCS) into the MEMS structures that are formed by CMOS thin films. Due to the improvement in DRIE technology, high

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structure release, the CMOS circuitry must be placed far away from the microstructures, especially when a large separation between the microstructures and substrate is needed. As a result, significant chip area is wasted due to the protection margin around the MEMS struc tures. Since the silicon underneath the mechanical anchors of the MEMS structures is also Fig. 8: FESEM image showing comb fingers of the central part of a magnetic field sensor etched away, the suspension of the mechanical structures is softened, which results in a lower Lastly, since the last release an isotropic etch, it undercuts the silicon close to the circuit and mechanical performance and step lessisrobustness of the device [10].
structure anchors. The ratio of the vertical and lateral etching rate is approximately 3:5. To protect the silicon underneath the circuit region from being etched away during the structure release, the CMOS circuitry must be placed far away from the microstructures, especially when a large separation 2.2. DRIE post-CMOS MEMS technology between the microstructures and substrate is needed. As a result, significant chip area is wasted due to the the protection margin around the MEMS structures. Since post-CMOS the silicon underneath the mechanical To reduce disadvantages of the above thin-film MEMS process, DRIE postanchors of the MEMS structures is also etched away, the suspension of the mechanical structures is CMOS MEMS technology is developed to incorporate bulk single crystal silicon (SCS) into the softened, which results in a lower mechanical performance and less robustness of the device [10].

MEMS structures that are formed by CMOS thin films. Due to the improvement in DRIE 2.2 DRIE Post-CMOS MEMS Technology technology, high aspect ratio CMOS MEMS structures have been exhibited as shown in Fig. 9. The achievement of maximum in DRIE system is an DRIE important factor in the To reduce the disadvantages of the aspect-ratio above thin-film post-CMOS MEMS process, post-CMOS MEMS technology is[5]. developed to incorporate bulk single crystal into the fabricated MEMS MEMS structure design It decides the dimensional limit silicon of the(SCS) structures using structures that are formed by CMOS thin films. Due to the improvement in DRIE technology, high that DRIE system. Once a lateral feature toexhibited be etched is fixed, the maximum thickness is aspect ratio CMOS MEMS structures have been as shown in Fig. 9. The achievement of maximum aspect-ratio in DRIE system is an important factor in the MEMS structure design [5]. It uniquely defined.
decides the dimensional limit of the structures fabricated using that DRIE system. Once a lateral feature to be etched is fixed, the maximum thickness is uniquely defined.

CMOS thin films Bulk single crystal silicon (SCS)

Fig. 9: FESEM image showing the incorporation of bulk SCS to the CMOS thin films. Figure 9. FESEM image showing the incorporation of bulk SCS to the CMOS thin films.

2.2.1. Process flow The DRIE post-CMOS MEMS technology branches from the thin film technology described in the previous section. DRIE CMOS-MEMS provides an approach to implement thick and flat MEMS structures with improved mechanical performance and device strength due to advant age of both flexible wiring with multiple metal layers in CMOS technology and the capability of high aspect ratio etching. Fig.10 shows the process flow of the DRIE post-CMOS MEMS technology. To define the MEMS structure thickness (thin film plus substrate), the process starts with backside silicon DRIE etching by the selective application of photoresist at the back-side as shown in Fig.10 (a). The maximum thickness of this structure is limited by the smallest etching pattern on the front side of the MEMS structure and the maximum etch aspect-ratio. Next, to

The DRIE post-CMOS MEMS technology branches from the thin film technology described in the previous section. DRIE CMOS-MEMS provides an approach to implement thick and flat MEMS structures with improved mechanical performance and device strength due to advantage of both flexible wiring with multiple metal layers in CMOS technology and the capability of high aspect ratio CMOS Compatible Bulk Micromachining etching. Fig.10 shows the process flow of the DRIE post-CMOS MEMS technology. http://dx.doi.org/10.5772/55526 MEMS structural region

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SiO2

CMOS circuit region

Surface passivation Photoresist

Metal 3 Metal 2 Metal 1

50 m

(a) CMOS-chip with back side etch

(b) Front side anisotropic SiO2 etch

CMOS layers

Moveable MEMS structures

SCS

(c) Front side anisotropic silicon etch

(d) Final released structure.

Figure 10. The process-flow for 10: DRIE CMOS micromachining Fig. The process-flow for DRIE CMOS micromachining

define the MEMS structures, an anisotropic SiO2 etch is performed on the front side of the chip To define the MEMS structure thickness (thin film plus substrate), the process starts with backside as shown in Fig. 10 (b) similar to the thin film process. In the following step, the structure is silicon DRIE etching by the selective application of photoresist at the back-side as shown in released by etching through the remaining SCS is substrate. step differs the Fig.10 (a). The maximum thickness of this structure limited by This the smallest etching from pattern on thin the film frontin side of an the anisotropic MEMS structure and the maximum etch aspect-ratio. Next, to define the MEMS process that DRIE, instead of isotropic Si etch, is performed to release the structures, an anisotropic SiO2 etch is performed on the front side of the chip as shown in Fig. 10 (b) structure as shown in Fig.10 (c). Flat and large MEMS structures can be obtained by incorpo similar to the thin film process. In the following step, the structure is released by etching through the rating SCS underneath the CMOS interconnect layers because stresses remaining SCS substrate. This step differs from the thin film process in the that residual an anisotropic DRIE,in the instead of isotropic Si etch, is performed to release the structure as shown in Fig.10 (c). Flat and SiO2/Al thin-films are mitigated by the thick SCS, showing very little out-of-plane large curling as MEMS structures can be obtained by incorporating SCS underneath the CMOS interconnect layers shown in Fig. 11 where it can be seen that the sense fingers are perfectly flat and aligned.
because the residual stresses in the SiO2/Al thin-films are mitigated by the thick SCS, showing very little out-of-plane curling as shown in Fig. 11 where it can be seen that the sense fingers are perfectly flat and aligned.

Metal 3 on top of CMOS interconnect layers SCS underneath the interconnect layers

Figure 11. FESEM image showing comb fingers with thick SCS underneath

Fig. 11: FESEM image showing comb fingers with thick SCS underneath

In some MEMS structures isotropic silicon etch can be added to create nice mechanical structures which only consist of CMOS thin films. A resonant magnetic field sensor fabricated under University Technology PETRONAS (UTP) MEMS Research group incorporates both CMOS thin-film layers for the beams and silicon substrate along with CMOS thin films in the side torsional coils as shown in Fig. 12.

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Fig. structures 11: FESEM image showing comb fingers with SCSto underneath In some MEMS isotropic silicon etch can bethick added create nice mechanical structures which only consist of CMOS thin films. A resonant magnetic field sensor fabricated In some MEMS structures isotropic silicon etch can be added to create nice mechanical structures under University Technology PETRONAS (UTP) MEMS Research group incorporates which only consist of CMOS thin films. A resonant magnetic field sensor fabricated under Universityboth Technology PETRONAS (UTP) group incorporates both CMOS thin-film layers CMOS thin-film layers for theMEMS beamsResearch and silicon substrate along with CMOS thin filmsfor in the the beams and coils silicon along with side torsional assubstrate shown in Fig. 12. CMOS thin films in the side torsional coils as shown in Fig. 12.

Thin film CMOS layers as beams Side torsional coils with SCS substrate

Figure 12. FESEM image of CMOS thin layers and incorporation structures of SCS with thin layers as MEMS structures

Fig. 12: FESEM image of CMOS thin layers and incorporation of SCS with thin layers as MEMS

Double alignment is required inbackside the backside DRIE to define the of thickness of the Double side side alignment is required in the DRIE step to step define the thickness the MEMS structures. It is observed that normally the remaining silicon for bulk silicon MEMS for structures is on the order MEMS structures. It is observed that normally the remaining bulk MEMS structures tens oforder microns byof the substrateand thinning there is no apparent circuit performance degradation. isof on the ofand tens microns by the substrate thinning there is no apparent circuit Therefore, there is no hard and fast constraints for alignment in the backside etch. A reliable sensing performance degradation. Therefore, there is no hard and fast constraints for alignment in the and actuation is achieved with the flat MEMS microstructures enabled by the DRIE CMOS MEMS backside etch. A reliable sensing and actuation is achieved with the flat MEMS microstructures technology. A resonant magnetic field sensor with piezoresistive sensing is fabricated using this technology The technology is very technology. suitable for the in particular, enabled by [11]. the DRIE CMOS MEMS A fabrication resonant of, magnetic field thermally sensor with actuated micromirrors bimorphs are used to elevate the mirror Numerous resonant piezoresistive sensingwhere is fabricated using this technology [11]. Theplate. technology is very suitable chemical sensors, electrothermal micromirrors and accelerometers have been fabricated using this for the fabrication technology [12]. of, in particular, thermally actuated micromirrors where bimorphs are used to elevate the mirror plate. Numerous resonant chemical sensors, electrothermal micromirrors and accelerometers have been fabricated using this technology [12]. 2.2.2. Design rules for MEMS devices For CMOS circuit designs, there are different ways to break up a layout into basic elements. Designers usually divide and analyze a circuit by the function of individual components, devices and interconnect. The devices may be active (e.g. transistors, diodes) or passive devices (e.g. resistors, capacitors and inductors). The interconnects include in-plane wires, pads and vias which connect multiple metal layers. The critical information on the geometric patterns includes the size of each feature, the spacing between features and the overlap of features. These geometric data, required in the design, leads to evolutions of processes and ensures successful fabrication of microelectronic circuitry. In order to fulfill the requirements of successful MEMS device designs, processing information, which quantitatively describes the capabilities and limitations of the process under predetermined processing conditions and

interconnect. The devices may be active (e.g. transistors, diodes) or passive devices (e.g. resistors, capacitors and inductors). The interconnects include in-plane wires, pads and vias which connect multiple metal layers. The critical information on the geometric patterns includes the size of each feature, the spacing between features and the overlap of features. These geometric data, required in CMOS Compatible Bulk Micromachining the design, leads to evolutions of processes and ensures successful fabrication of microelectronic http://dx.doi.org/10.5772/55526 circuitry. In order to fulfill the requirements of successful MEMS device designs, processing information, which quantitatively describes the capabilities and limitations of the process under predetermined processing conditions and parameter settings, is necessary and crucial. This parameter settings, is necessary and design crucial. This information is abstracted as MEMS design information is abstracted as MEMS rules and is verified in the design environment as illustrated in Fig. 13.in the design environment as illustrated in Fig. 13. rules and is verified

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Submit design

DRC Check

MEMS Designers

Design
Implement Design Rules

Rules

Fabrication Information

Processing Engineers

13: rules Design rules between function MEMS between MEMS designers and MEMS fabrication engineers. Figure 13.Fig. Design function designers and MEMS fabrication engineers.

This section explains how to construct concise and conclusive design rules. We used MIMOS This section explains how to construct concise and conclusive design rules. We used MIMOS Berhad Berhad Malaysia standard 0.35 m CMOS rules forof the fabrication of CMOS MEMS Malaysia standard 0.35 m CMOS design rules design for the fabrication CMOS MEMS devices and only devices and only the design rules for mechanical structures are discussed in this section. These the design rules for mechanical structures are discussed in this section. These MEMS design rules add further constraints to add layouts. Similar to CMOS design rules, a Similar complex micromechanical layout is a MEMS design rules further constraints to layouts. to CMOS design rules, fragmented into small pieces, and MEMS design rulesinto contain only fundamental geometries directly complex micromechanical layout is fragmented small pieces, and MEMS design rules related to the post CMOS micromachining process. A set of geometric constraints and design rules contain only fundamental geometries directly related to the post CMOS micromachining are then based on the final process. process. A set of geometric constraints and design rules are then based on the final process. Design rules Mentor are expressed in the design-rule used layout tools such as Cadence Virtuoso, Magicor, Graphic, layout tool etc. file After allinprocessing completion, a post-CMOS micromachined can be partitioned into a released areaprocessing (containing free standing parts and free Magicor, Mentorchip Graphic, layout tool etc. After all completion, a post-CMOS moving parts) and acan non-released area (anchored parts) according to the mechanical behavior. Theand micromachined chip be partitioned into a released area (containing free standing parts objective of post CMOS processing is the final result of releasing microstructures and maintaining freecritical moving parts) and a are non-released area (anchored parts) toprocess the mechanical dimensions. There practical difficulties in monitoring eachaccording intermediate stages. behavior. The objective of post CMOS processing is therules final result of releasing microstructures Therefore characterization of the process to extract design is performed at the end of the entire flow. An overview of a typical postThere CMOS are MEMS magneticdifficulties sensor is shown Fig. 14. andprocess maintaining critical dimensions. practical in in monitoring each intermediate process stages. Therefore characterization of the process to extract design rules is performed at the end of the entire process flow. An overview of a typical post CMOS MEMS magnetic sensor is shown in Fig. 14. The anchored part is the area outside of the red dash-line box on FESEM, whereas the released part is the area inside the red border. The close-up FESEM view of circled portion is shown in Fig. 14 (b). Sufficient paths for the gas flow are required in order to allow the reactive radicals in the plasma to undercut MEMS structures. These paths can surround mechanical structures, so that the undercut can happen from the periphery of the structures. The gas flow can also pass through structures via etch release holes. Fig. 14 illustrates various situations for reactive species undercut: from one side of the structures toward the anchor region, from both sides of beam structures, or outward through etch release holes on plates. Theoretically, any shape of the feature which opens a gas flow path from the top of the chip to the substrate is suitable for the purpose of undercut. However, currently in CMOS foundries, Manhattan layout is preferred, or at least convenient. The majority of CMOS foundries only accept patterns with edges which are parallel, perpendicular or 45 with respect to the horizontal/vertical alignment lines. Non-Manhattan features require more and smaller rectangular patterns to approximate the geometry, and therefore, require a larger data base and longer exposure time, which leads to higher cost. Today, raster-scanning mask-making
Design rules are expressed in the design-rule file used in layout tools such as Cadence Virtuoso,

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Non Released part

Non Released part Non Released part

Released part
Non Released part Non Released part

Non Released part

(a)
Figure 14. Partitioning of a MEMS sensor for design-rule checking

(b)

Fig. 14: Partitioning of a MEMS sensor for design-rule checking

The anchored part is the area outside of the red dash-line box on FESEM, whereas the released part is such as e-beam or close-up laser systems canview overcome the difficulties mentioned above thetechnologies area inside the red border. The FESEM of circled portion is shown in Fig. 14 (b). but non-Manhattan approximated a smaller raster-beam size still require more time to Sufficient paths for theshapes gas flow are required by in order to allow the reactive radicals in the plasma undercut MEMS structures. These paths can surround mechanical structures, that only the undercut can in fabrication [13]. Following the practice of CMOS fabrication, this so work explores happen from the periphery themajor structures. The gas flow can is also pass through structures via etch rectangular design rules.of The purpose of this section to ensure the release of moving/ release holes. Fig. 14 illustrates various situations for reactive speciesparts. undercut: from one side of the free-standing parts and to guarantee the integration of anchor Other process related structures toward the anchor region, from both sides of beam structures, or outward through etch rules are not included. According to situations described in Fig. 14, there have been three release holes on plates. features encountered in the MEMS structure layout for the purpose of undercut: large openings, gaps and holes. To control the etch rates in these opening, dummy structures are Theoretically, any shape of the feature which opens a gas flow path from the top of the chip to the used as infor Fig.15 (a) while figure 15 (b) shows the fully released structure. substrate isshown suitable the purpose of undercut. However, currently in CMOS foundries, Manhattan layout is preferred, or at least convenient. The majority of CMOS foundries only accept patterns with Test structures are used to extract design rules. A large opening undercut rule specifies the edges which are parallel, perpendicular or 45 with respect to the horizontal/vertical alignment lines. maximum undercut that can be achieved by the process. Any microstructure wider than this Non-Manhattan features require more and smaller rectangular patterns to approximate the geometry, value will not be released. the minimum size requirement of the anchor and therefore, require a largerThis data rule basealso andspecifies longer exposure time, which leads to higher cost. Today, layout, and the skirt for bonding pads. Bonding pads are usually on systems the periphery of the chip raster-scanning mask-making technologies such as e-beam or laser can overcome the for easy mentioned access during bonding and no crossing ofapproximated bonding wires the top of the chip. difficulties above but non-Manhattan shapes by on a smaller raster-beam size Therefore, at least one of bonding pads faces large is lateral undercut this during still require more time inside fabrication [13]. Following the opening practice and of CMOS fabrication, work only explores design rules. The major purpose this section is avoid to ensure the release of the release. rectangular The sites that experience forces during wire of bonding should these undercut moving/free-standing parts and to guarantee integration this of anchor Other process related regions and bonding pads need extra area the to compensate lateral parts. undercut. Moreover, this rules are not included. According to situations described in Fig. 14, there have been features large opening rules specifies the minimum space required from the edge of the three etch pit to encountered inarea the containing MEMS structure layout for micromachining. the purpose of undercut: large openings, gaps is and preserve Si circuitry during One way to obtain this data holes. To control the etch rates in these opening, dummy structures are used as shown in Fig.15 (a) to use FESEM to measure the undercut from the periphery of the chip. Another way is to use while figure 15 (b) shows the fully released structure. an optical microscope to check which size of square pattern has been released as illustrated in Fig. 16 (a).
The undercut value is half the size of square width. A gap undercut rule is required for releasing MEMS structures such as a comb finger or a spring. The test structure for this rule is a set of cantilevers with the undercut mainly determined from the sides of the beams. To follow the situation in real layout, such as comb fingers, multiple cantilever beams with equal space

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Dummy structures

Dummy structures

Debris from dummy

(a)

(b) Fig. 15: FESEM images of (a) unreleased device showing dummy structure at a large etch holes and Figure 15. FESEM images of (a) unreleased device showing structure at a large etch holes and (b) fully re (b) fully releaseddummy structure. leased structure.

between them are as shown 16 Any (b). microstructure The beam width (w) represents the undercut thatused can be achieved by in theFig. process. wider than this value will not be width of released. This rule also specifies the minimum size requirement of the anchor layout, andthe the skirt for the structure to be released. The gap (g) represents the separation between structures. The bonding pads. Bonding pads are usually on the periphery of the chip for easy access during bonding beam should be long enough undercut the tip of the one cantilever doesnt and no crossing of bondingthat wiresthe on the top of the from chip. Therefore, at least side of bonding padsdominate faces large and stress is lateral undercut during the release.curling The sites upon that experience forces the etch. Since theopening residual induces out-of-plane release, the during release can be wire bonding should avoid these undercut regions and bonding pads need extra area to compensate easily detected by an interferometric measurement. A hole undercut rule is required this lateral undercut. Moreover, this large opening rules specifies the minimum space required fromto release the edge of the test etch structure pit to preserve Sithis area design containing circuitry during One way to plate structures. The for rule is a set of micromachining. plates with release holes. These obtain this data is to use FESEM to measure the undercut from the periphery of the chip. Another way plates are anchored by four thin beams as shown in Fig. 16 (c). Such plates should be large is to use an optical microscope to check which size of square pattern has been released as illustrated in ensure Fig. 16 (a). enough to that the release of the plate is determined by the etch release holes and not from the periphery of the plate. Similar to the cantilever test structures, the curling after the release of plates can be detected by the interferometric measurement. Extra processing time requires layouts to be modified such that the circuitry is far away from the edge of the mask, all the anchors are wide enough, and all bond pads have enough margins for bonding and probing. The spacing between the squares and the spacing from a square to the surrounding anchor mask area are the size of the square. This is to ensure that squares are uniformly etched from all directions. For each group of cantilever test structures, as in Fig. 16 (b), the widths of all cantilever beams are the same value. The spacing between beams and from tips of cantilever beams to anchor mask areas are the same value [14].

Test structures are used to extract design rules. A large opening undercut rule specifies the maximum

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Beam width (w)

gap (g)

Square width (w)

(a) The square structure illustrating the large opening undercut rule

Beam width (w) gap (g)

(b) The cantilever structure illustrating the gap undercut rule

Hole separation

Hole size

(c) The plate structure illustrating the hole undercut rule

Figure 16. Layout of three test structures used for extracting MEMS design rules for post-CMOS micromachining.

Fig. 16: Layout of three test structures used for extracting MEMS design rules for post-CMOS micromachining.

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3. DRIE based CMOS-MEMS devices

In this section, two devices fabricated using CMOS-MEMS bulk micromachining technology are described. The devices are a resonant MEMS magnetic field sensor and a resonant MEMS chemical sensor. 3.1. Resonant MEMS magnetic field sensor The post-CMOS process steps of the resonant magnetic field sensor using DRIE were designed to successfully release the sensor structure. The first step in the post-CMOS process was at wafer level with the selective application of photoresist at the back-side of the 8" inch silicon wafer to etch from the back-side to produce a substrate thickness of approximately 50 m as shown in Fig.17. DRIE was performed using SS110A Tegal plasma etcher to anisotropically etch the silicon substrate to the desired thickness.

(a)

(b)

(c)

Fig. (a) Optical image of side back Si etching at wafer (b) optical Backside optical of(c) a chip Figure 17.17: a) Optical image of back Siside etching at wafer level, (b)level, Backside image of a image chip and FESEM of and (c) FESEM of backside of a sensor. backside of a sensor.

Optical microscope was used to estimate the thickness of the Si substrate during the etching Fig.17 (c) shows the back-side view of one of the sensors that has been successfully etched to process. Fig.17 (c) shows the back-side view ofm one of the sensors that has layers. been successfully approximately 284 m depth leaving a about 50 thickness under the CMOS From the back-side etching of the bulk the silicon etching rate was found to be ~3.66 m/min. The etched to approximately 284 silicon, m depth leaving a about 50 m thickness under the CMOS second stepthe was dicing the etching wafer as of shown in Fig. 18 (a). Dicing of the wafer has to be done before layers. From back-side the bulk silicon, the silicon etching rate was found to be the front side RIE of SiO2 and DRIE of silicon is implemented. This sequence was followed in order ~3.66 m/min. The second step was dicing the wafer as shown in Fig. 18 (a). Dicing of the wafer to prevent the breakage of the released structures. has to be done before the front side RIE of SiO2 and DRIE of silicon is implemented. This sequence was followed in order to prevent the breakage of the released structures. The third process was SiO2 RIE on the diced chip shown in Fig. 18 (b), which was performed Pads from the front-side of the chip using Tegal plasma etcher. Front side RIE process opened the Test structure pattern of the resonant magnetic sensor by removing the SiO 2 layer and thus exposing the silicon underneath while the MEMS sensor pattern was maintained by metal 3 acting as a mask

Optical microscope was used to estimate the thickness of the Si substrate during the etching process.

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approximately 284 m depth leaving a about 50 m thickness under the CMOS layers. From the back-side etching of the bulk silicon, the silicon etching rate was found to be ~3.66 m/min. The second step was dicing the wafer as shown in Fig. 18 (a). Dicing of the wafer has to be done before the front in side RIE of SiO silicon isFabrication implemented. This sequence was followed in order Advances Micro/Nano Electromechanical Systems and Technologies 2 and DRIE of to prevent the breakage of the released structures.

Pads Test structure

(a)

(b)

5 mm chip. The third process was SiO2 RIE on the diced chip shown in Fig. 18 (b), which was performed from for the pattern.of The at chip started by flipping overprocess the chips such that the thin the front-side the process chip using Tegallevel plasma etcher. Front side RIE opened the pattern of the resonant magnetic sensor removing the were SiO2 layer thus exposing silicon coated underneath while film was now on the frontby side. The chips then and attached to the 8"the platinum carrier the MEMS pattern was maintained by metal 3 acting a mask for the pattern. The process wafer using sensor kapton tape as illustrated in Fig.19. After 13as minutes of etching, a gray colour at chip level started by flipping over the chips that the thin film was of now onetching. the front side. The (silicon colour) appeared in the trenches thatsuch indicated the completion SiO The test 2 chips were then attached to the 8" platinum coated carrier wafer using kapton tape as illustrated in structures to the right of the sensor beam were used to estimate SiO2 etching rate and to avoid Fig.19. After 13 minutes of etching, a gray colour (silicon colour) appeared in the trenches that over-etch SiO2 material as shown Fig.18 (b). to The SiO depth was 2 etching indicated of thethe completion of SiO2 etching. Thein test structures thetotal right of the sensor beam were used approximately 5 to estimate SiO etching rate and to avoid over-etch of the SiO2 material as shown in Fig.18 (b) . The 2 m. total SiO2 etching depth was approximately 5 m.

Fig. 18: (a) Optical image ofdiced the diced (b)image optical image ofof front side of a5 mm Figure 18. a) Optical image of the wafer wafer and (b) and optical of front side a 5 mm 5 mm chip.

8" platinum coated carrier wafer

Kapton tape Chips

Fig. 19: Sample preparation for front side etching

Figure 19. Sample preparation for front side etching

Next, front-side bulk silicon DRIE process step was performed using the etching rate of 3.66 m/min obtained from previous backside DRIE etching of silicon. The thickness of the central shuttle and long beams was approximately 50 m, which was observed under optical microscope during backside etching. Therefore the test structures on the chip were used as reference. Fig.20 shows FESEM micrograph of the fabricated sensor with inset showing a close-up of the comb fingers and part of dummy structure close to the beams that has fallen out while others still remain intact on the substrate [10]. Additional 3 more minutes were required to fully etch-through. This happened when all the dummy structures dropped and indicated that the etched-through process was completed.

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Next, front-side bulk silicon DRIE process step was performed using the etching rate of 3.66 m/min obtained from previous backside DRIE etching of silicon. The thickness of the central shuttle and long beams was approximately 50 m, which was observed under optical micro scope during back-side etching. Therefore the test structures on the chip were used as reference. Fig.20 shows FESEM micrograph of the fabricated sensor with inset showing a closeup of the comb fingers and part of dummy structure close to the beams that has fallen out while others still remain intact on the substrate [10]. Additional 3 more minutes were required to fully etch-through. This happened when all the dummy structures dropped and indicated that the etched-through process was completed.

Dummy Structures

Fig. 20: FESEM image of the fabricated CMOS-MEMS resonant magnetic field sensor with
Figure 20. FESEM image of the fabricated resonant magnetic inset CMOS-MEMS showing shuttle and stator fingers. field sensor with inset showing shuttle and stator fingers.

3.2. Resonant MEMS chemical sensor

3.2

Resonant MEMS Chemical sensor

gaseous specieschemical is based on the change in resonant frequency of sensors, the microresonator membrane or In resonant MEMS sensors, known as gravimetric the principle of detection plate. This frequency change results from a change in the mass of the microresonator due to of the gaseous species is based on the change in resonant frequency of the microresonator absorption/adsorption of an analyte molecule onto the surface of the active material deposited on it. membrane orshows plate. This frequency change results from a change in the mass of the microresona Fig. 21 2-D schematic diagram of the chemical microsensor device. tor due to absorption/adsorption of an analyte molecule onto the surface of the active material deposited on it. Fig. 21 shows 2-D schematic diagram of the chemical microsensor device.

In resonant MEMS chemical sensors, known as gravimetric sensors, the principle of detection of the

The post-CMOS micromachining process steps of the resonant MEMS chemical sensor were similar to the process steps of the resonant MEMS magnetic field sensor. The process started with the selective application of photoresist at the back-side of the die around the sensor followed by sample placement on the platinum coated carrier wafer. The second step of the process was to perform back-side silicon DRIE to achieve proof mass thickness of approxi mately 40 m. The same plasma silicon etcher was used to anisotropically etch the silicon substrate to the desired thickness. Fig. 22 shows the FESEM image of the successfully released MEMS chemical sensor with the inset showing a close-up view of the perfectly flat sensing comb fingers with the SCS underneath [15].
Fig. 21: 2-D Schematic of the resonant MEMS chemical sensor The post-CMOS micromachining process steps of the resonant MEMS chemical sensor were similar to the process steps of the resonant MEMS magnetic field sensor. The process started with the selective application of photoresist at the back-side of the die around the sensor followed by sample

In resonant MEMS chemical sensors, known as gravimetric sensors, the principle of detection of the gaseous species is based on the change in resonant frequency of the microresonator membrane or plate. This frequency change results from a change in the mass of the microresonator due to 136 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies absorption/adsorption of an analyte molecule onto the surface of the active material deposited on it. Fig. 21 shows 2-D schematic diagram of the chemical microsensor device.

placement on the platinum coated carrier wafer. The second step of the process was to perform backside silicon DRIE to achieve proof mass thickness of approximately 40 m. The same plasma silicon etcher was used to anisotropically etch the silicon substrate to the desired thickness. Fig. 22 shows the FESEM image of the successfully released MEMS chemical sensor with the inset showing a close-up Figure 21. D Schematic of the resonant MEMS chemical sensor Fig.flat 21: 2-D Schematic of the resonant chemical view of the perfectly sensing comb fingers with the SCSMEMS underneath [15]. sensor

The post-CMOS micromachining process steps of the resonant MEMS chemical sensor were similar to the process steps of the resonant MEMS magnetic field sensor. The process started with the selective application of photoresist at the back-side of the die around the sensor followed by sample
SCS underneath the interconnect layers

Fig. 22: FESEM image of fabricated device with inset showing a close-up view of the fingers with the SCS underneath Conclusion

Figure 22. FESEM image of fabricated device with inset showing a close-up view of the fingers with the SCS underneath

4. Conclusion

This chapter discussed bulk micromachining technology with particular emphases on DRIE post CMOS micromachining. The chapter technology was dividedwith into particular three sections. In the first section This MEMS chapterbulk discussed bulk micromachining emphases on DRIE an post introduction to bulkbulk micromachining of silicon and isotropic and anisotropic wet and dry etching CMOS MEMS micromachining. The chapter was divided into three sections. In the was given. Thean second section to discussed briefly DRIE of post-CMOS micromachining process with first section introduction bulk micromachining silicon and isotropic and anisotropic particular emphasis on DRIE post-CMOS bulk micromachining process briefly and theDRIE third and last section wet and dry etching was given. The second section discussed post-CMOS provides a few examples of devices fabricated by our research group using the DRIE CMOS-MEMS micromachining process with particular emphasis on DRIE post-CMOS bulk micromachining process. These were MEMS magnetic field sensor of and resonant MEMS by chemical process and devices the third and resonant last section provides a few examples devices fabricated our sensor. The aim of the chapter was to discuss and analyze practical processes involved in the design of micromechanical devices using 0.35 m CMOS technology. Acknowledgment The authors would like to thank MIMOS Bhd Malaysia for facilitating the microfabrication of the sensors and MOSTI Malaysia for financially supporting this research under E-Science project No.04-02-02-SF0095.

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research group using the DRIE CMOS-MEMS process. These devices were resonant MEMS magnetic field sensor and resonant MEMS chemical sensor. The aim of the chapter was to discuss and analyze practical processes involved in the design of micromechanical devices using 0.35 m CMOS technology.

Acknowledgements
The authors would like to thank MIMOS Bhd Malaysia for facilitating the microfabrication of the sensors and MOSTI Malaysia for financially supporting this research under E-Science project No.04-02-02-SF0095.

Author details
John Ojur Dennis, Farooq Ahmad and M. Haris Khir Department of Fundamental and Applied Sciences, Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, Perak, Malaysia

References
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[8] Haris, M, Qu, H, & Cmos-mems, A. Piezoresistive Accelerometer with Large Proof Mass", IEEE NEMS (2010). Xiamen, China, Jan 2010. [9] Xie, H. Gyroscope and micromirror design using vertical-axis CMOS-MEMSsensing and actuation," Ph. D. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburg, PA, (2002). [10] Ahmad, F, Dennis, J. O, Khir, M. H. M, & Hamid, N. H. Lorentz force based CMOS Resonant Piezoresistive Magnetic Sensor with differential electrostatic actuation" MY. Patent, Jan.16, (2012). [11] Farooq AhmadDesign and simulation of mechanical behavior of MEMS-based reso nant magnetic field sensor with piezoresistive output", (2010). International Confer ence on Mechanical and Electrical Technology, 09/2010 [12] Fedder, G. K. Tri-axial high-g CMOS-MEMS capacitive accelerometer array", (2008). IEEE 21st International Conference on Micro Electro Mechanical Systems, 01/2008. [13] Zhu, X. Post-CMOS Micromachining of Surface and Bulk Structures," Ph. D. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburg, PA, (2002). [14] Brand, O. CMOS-Based Resonant Sensors", IEEE Sensors (2005). [15] Ahmed, A. Y, Dennis, J. O, Khir, M. H. M, Saad, M. N. M, & Method, A. Apparatus and Sensor for Reversible Detection of Analyte Molecule" MY. Patent, Dec.16, (2011).