Hesketh, P.J.

"Micromachining"
The VLSI Handbook.
Ed. Wai-Kai Chen
Boca Raton: CRC Press LLC, 2000

2000 by CRC PRESS LLC

10
Micromachining
10.1 Introduction
10.2 Micromachining Processes
10.3 Bulk Micromachining of Silicon
Etch Stop Methods Electrochemical Machining and
Porous Silicon

10.4 Surface Micromachining

Stiction Materials Properties of Thin Films

10.5 Advanced Processing

Chemical Mechanical Polishing Electroplating into
Molds LIGA Process GaAs Micromachining

10.6 CMOS and MEMS Fabrication

Process Integration
Post-processing Mixed Processing Pre-processing

10.7 Wafer Bonding

10.8 Optical MEMS
Components Modulators and Active Gratings Scanning
Mirrors Spectrometer on a Chip Micromechanical
Displays Optical Disk Pick-up Head

10.9 Actuators for MEMS Optics

Electrostatic Comb Drive Actuators Linear
Microvibromotor Scratch Drive Thermal
Actuator Magnetically Driven Actuators

10.10 Electronics
RF and Microwave Passive Components Microwave
Waveguides Tuning Fork Oscillator Thermal
Devices Microrelays Integrated Ink-Jet Printers

Peter J. Hesketh
The Georgia Institute of Technology

10.11 Chemical Sensors

ISFET Hydrogen Sensor Gas Sensors Artifical
Nose Neural Probes

10.1 Introduction
There has been a tremendous growth in activity over the past seven years in exploring the use of
micromachining for the fabrication of novel microstructures, microsensors, and microdevices and also
their integration with electronic circuits. Specific application areas have developed to such an extent
that there are specialist meetings on the following topics: sensors and actuators,1 microelectromechanical system (MEMS),2 microchemical analysis systems (TAS),3 optical-MEMS,4 MEMS-electronics,5
chemical sensors,7 and microstructures and microfabricated systems.7 Early examples of MEMS devices
and innovations are reviewed in Petersons8 classic paper. Up until recently, the MEMS micromachining
processes were developed outside the realm of a CMOS line although the advantages of IC fabrication
processes and the economies of batch fabrication have been used for production of microdevices at low

2000 by CRC Press LLC

cost and high volume. The tremendous successes of microfabricated silicon pressure sensors used for
blood pressure monitoring and automotive air intake manifold pressure sensing, ink-jet printer heads,
and the air bag accelerometer sensors, and most recently projection overhead display systems, demonstrate the tremendous success of this technology. There are several important differences between MEMS
processing and IC processing that make this an exciting and rapidly evolving field:

Wider range of materials

Wider range of fabrication processes utilized
Use of three-dimensional structures
Material properties are not fully characterized
Interdisciplinary expertise necessary for successful technology implementation
CAD tools are not yet fully developed for integrated thermal/mechanical, magnetic, optical, and
electronic design

In keeping with the general philosophy of this volume, I will emphasize the fundamental principles
and discuss CMOS-compatible processing methods. Selected examples of MEMS devices will be given
to illustrate some of exciting applications of this technology. The reader is referred to the comprehensive
survey by Gpel et al.9 and the vast diversity of micromachining and micromanufacturing methods
described in recent books by Kovacs,10 Madou,11 and Sze.12 In addition, reference materials include a
collection of classic papers by Trimmer,13 texts on sensors by Middlehoek and Audet,14 Ristic,15 Gardener,16
and bio and chemical sensors texts by Janata,17 Madou and Morrison,18 Moseley et al.,19 and Wilson et al.20

10.2 Micromachining Processes

There are a wide range of MEMS processing methods for 2-D and 3-D structures, many of which are
incompatible with CMOS fabrication. Micromachining is the process of forming such structures by
processes of chemical etching, physical machining, and layering of materials by a diverse range of
processes, as listed in Table 10.1. A range of processes for material removal has been developed, including
chemical etching,21 laser ablation,22 precison machining,23 focused ion beam etching,24 ultrasonic drilling
and electrodischarge machining,25 and others. Historically, surface and bulk micromachining have developed independently to produce novel structures and microdevices in two different ranges of dimensional
scales. A great deal of work has addressed hybrid approaches that combine bulk and surface processes
in novel ways, which will be discussed in the next section. A major obstacle to the further development
of MEMS devices is the compatibility of micromachining processes with CMOS circuit processing if
integration of electronics is desired. A recent review of micromachining methods for a range of materials
of interest is given by Williams and Muller.26

10.3 Bulk Micromachining of Silicon

Bulk machining involves etching the bulk single-crystal silicon wafer with respect to a patterned insoluble
masking layer that defines the structure on the wafer surface. These methods are either isotropic-independent of direction, or anisotropic-crystal plane selective. Silicon has a diamond lattice as shown in Fig. 10.1(a).
The dimensions of the structure in the bulk of the wafer are defined by the crystal plane locations. In
particular, the etch rate of the (111) planes are slower than other crystalline directions by typically 35 to 50
times.27 An SiO2 or Si3N4 mask is used in on etching solution, as shown in Fig. 10.1(b).
Anisotropic etching which is a function of the crystal planes of the Si substrate, occurs in strong
bases. The (111) close-packed silicon lattice plane etches slower than other directions of the crystal.
Examples of commonly used formulations are given in Table 10.2. This process has been extremely
successful for the fabrication of diaphragms for pressure sensors and other devices, aligning the [110]
flat of a (100) wafer to a mask opening a rectangular opening which is produced. Etching into the
2000 by CRC Press LLC

TABLE 10.1 MEMS Processing Technologies

Process

Physical
Dimension
Range/Aspect
Ratio

Materials

Etch Stop Techniques

Through-put

Cost

Ref.

Dopant-selective electrochemical
Buried layer
Buried layer
Timed
Timed
Tool position
Timed
Timed
Tool position

High

Low

911, 2749

Low
Low
Low
Low
Low
High
Moderate

High
High
Med
High
High
Low
Moderate

6264
22
25
23
24
21,26,50

Moderate

High

26

Selectivity of sacrificial etch to

sacrificial layer to structural layer

High

Moderate

6771,

Low
Low
Low
High
High
High
High

High
Very High
High
Low
Moderate
Low
Low

51,101

Subtractive processes
Bulk micromachining

m-cm/1:400

Reactive ion etch

Laser ablation
Electrodischarge machining
Precision mechanical cutting
Focussed ion beam machining
Chemical etching
Ultrasonic machining

m-mm/1:100
1-100 m/1:50
2 m-mm/*
nm-cm/*
nm-m
m/1:10
25 m-mm/*

Single-crystal silicon, GaAs glass

etching
Wide range of materials
Various
Si, metals
PMMA
various
Metals, semiconductors, insulators
Glass, ceramic, semiconductor, metals
Additive processes

Physical vapor depositon

Chemical vapor deposition
Laser-assisted CVD
Molecular beam epitaxy
LIGA
Electroplating into a mold:

* function of total geometry.

2000 by CRC Press LLC

Wide range of
materials
Surface
micromachining
nm-m
nm
m-cm
m-mm
m-mm/1:10
m-mm
m-mm

Electron beam or thermal

evaporation/sputtering
LPCVD of polysilicon/PSG or
sputtered aluminum/photoresist
Various
Semiconductors
PMMA
Cu, Ag, Au, Fe, permalloy
Polyimide
SU-8
Thick photoresist

96,98100
97

(a)

(b)
FIGURE 10.1(a-b) (a) Diamond lattice of silicon with principle axis indicated; (b) schematic cross-section of bulk
micromachining processing steps to form a cavity in a (100) silicon wafer.

bulk of the silicon crystal the dimensions of the resulting structure is defined by the slow etching {111}
planes (see Fig. 10.1c), which are parallel and perpendicular to the [011] flat on a (100) silicon wafer.
Alternatively, on a (110) silicon wafer, a slot is produced, as shown in Fig. 10.1(d). Note here that the
shape is bounded by the {111} crystal planes in the vertical direction and the {100} planes or {311}
planes at the base of the groove. There is insufficient space here to describe the mechanism of etch
chemistry, and the reader is referred to the work of Seidel,28 Kendall,29 Palik et al.,30 Hesketh et al.,31
and Allongue et al.,32 the recent review given by Kovacs et al.,33 and a recent workshop of Wet Chemical
Etching of Silicon.34
KOH is perhaps the most widely used bulk micromachining wet chemical etchant, although it is a
strong ionic contaminant to the CMOS process. Despite these difficulties, it has been demonstrated
in post- and pre-processing formalisms with stringent chemical cleaning. The etch has been charac 2000 by CRC Press LLC

(c)

(d)
FIGURE 10.1(c-d) (c) Electron micrograph of a cavity etched in (100) silicon wafer dimensional marker is 100 m;
(d) slots etched in (110) silicon wafer, dimensional marker is 10 m.

terized extensively.3537 Table 10.2 lists the plane selectivity of useful concentrations that in additon to
the surface roughness, are a function of the solution composition. However, roughness appears to be
related to hydrogen bubble release from the surface, and work by Bressers et al.38 has demonstrated
that the addition of ferricyanide ions reduces hillock formation. Note that selectivity to oxide masking
layers is not as high as CsOH and TMAH. Alcohol can be added to the etch to improve the surface
finish and uniformity.39
CsOH etchant has been characterized,4042 and the results are summarized in Table 10.2. It has high
selectivity to silicon dioxide and is dopant selective, producing smooth membranes at high concentrations.
Surface roughness is often a key parameter in device design and is of key importance for technologically
useful etches to obtain controlled surface conditions.

2000 by CRC Press LLC

TABLE 10.2 Bulk Etching Solutions for Silicon

Selectivity

Anisotropyb
Concentration
(wt%)

Etching Solution

Temp.
(C)

Etch rate of
(100) plane
(m/hr)a,b

Rate(110)
-----------------------Rate(100)

Anisotropy b
Rate(100)
-----------------------Rate(111)

Rate Si(100)
-----------------------------Rate SiO 2
(Thermal)

Selectivity
Rate Si(100)
-----------------------------Rate Si 3 N 4
(LPCVD)

Metals

Etch stop on p+
silicon

Com.

Ref.

Isotropic etches
HNA

250 ml HF/
500 ml HNO3/
800ml CH3COOH

20

420
[function of
stirring]

KOH

45

85

55

~1.5

200

300

40,000

Au

Yes

26/4

80

66

~0.6

~200

High

Very high

Au

>10 1020/cm3
decreases rate
by 20

50

70

19

0.22.5b

50

2000

Very high

Au

Yes

255cc/ 45grm/
120cc

100

66

<1

35

3500

Very high

Au, Cu Cr,
Ag, Ta, Ni

4
20

80

54

25

5000

Very high

Al [Si
doping of
solution]

>7 1019/cm3
decreases rate
by 50
Yes

1525

7090

1140

1537

5000

>21,000

50

Anisotropic etches

KOH/isopropyl
alcohol

CsOH

Ethylenediamine/
pyrocatechol/water
TMAH

TMAH/alcohol
a
b

Function of temperature.
Function of solution concentration.

2000 by CRC Press LLC

Yes

Not CMOS
compatible,
inexpensive,
safe, widely used
Not CMOS
compatible,
inexpensive,
safe, widely used
Expensive
material, good
selectivity with
SiO2
Carcinogenic,
widely used, low
anisotropy
Flammable, low
anisotropy

2734,
3638

39

4042

4344

4547,
49
48

(a)

(b)

FIGURE 10.2 (a) Schematic diagram of isotropic etching, indicating undercut of mask and definition of isotropy;
(b) effect of isotropic etching on grooves sawed into silicon wafer. The etching has rounded the tops of the grooves.
(Kasapbasioglu, H. et al., J. Electrochem. Soc., 140, 2319, 1993. With permission.)
2000 by CRC Press LLC

EDP has been demonstrated as compatible with CMOS processing. It has high selectivity to dielectic
and metallization layers and contains no ionic contaminants. Etch has been characterized by Reisman et
al.43 and Finne and Klein.44 The popular formulations are as follows: Type-S is 1000 ml ethylenediamine,
160 g pyrocatechol, 133 ml water, and 6 g pyrazine; Type-F is 1000 ml ethylenediamine, 320 g pyrocatechol, 320 ml water, and 6 g pyrazine. These solutions etch thermal oxide at about 55 /h at 115C, there
is no detectable attack of LPCVD silicon nitride, and the following metals Au, Cr, Ag, and Cu are
resistant to EDP. The plane selectivity is listed in Table 10.2.
TMAH has been studied extensively due to its low ionic contamination with CMOS. The early work
on etch characterization was carried out by Tabata.45 Characteristics are listed in Table 10.2 and the plane
selectivity is markedly lower than KOH; however, selectivity to SiO2 is quite high. The solution also
passivates aluminum surfaces when the pH is adjusted into a suitable range.46 This makes it a strong
candidate for CMOS post-processing; however, the etch rate is reduced with silicon doping and there are
unresolved issues regarding the solution stability. Ammonium persulphonate was added to the TMAH
bath to reduce surface roughness by limiting the formation of hydrogen bubbles, specifically for a 5 wt
% solution, 40 g/l silicic acid, and 5 to 10 g/l ammonium persulphate.47 Changes in the surface morphology and high index plane selectivity are observed with the addition of alcohol48 and hillock formation
has been studied.49
Isotropic etching in a mixtures of hydrofluoric acid (HF) and nitric acid (HNO3) produces typically
rounded profiles.50 Figure 10.2 shows a schematic diagram of the profile produced during isotropic
etching. The etching takes place in a two-step process, the first being oxidation of the silicon by the
HNO3, and the second being dissolution of the oxidized layer into a soluble H2SiF6 silicate. These two
processes have different reaction rates and, hence, polishing occurs at low concentrations of HF where
it defines the rate-limiting step in the reaction. The etchant can be stabilized by the addition of acetic
acid, which helps prevent the dissociation of the nitric acid into NO3 and NO2. The etch is dopant
selective, having a lower etch rate for lightly doped region (<1017/cm3) of silicon relative to heavier doping
regions.21 Figure 10.2(b) shows the application of this etching mixture to the rounding of pins that have
been produced by mechanical sawing of the silicon.

Etch Stop Methods

There are various methods that have been developed for membrane fabrication at a defined doped layer
as shown in Fig. 10.3(a). The heavily doped etch stop occurs when the doping level of p-type silicon is
greater than 25 1019/cm3 for all of the principle etching solutions listed in Table 10.2. It is believed
that the etch mechanism is related to the availability of electrons at the surface, which is a participant in
the silicon dissolution process. Thus, high p+ doping results in electron-hole recombination. Doping and
etch back has been very successful in producing capacitive pressure sensors and neural recording probes.52
The etch rate of the heavily doped material has an n4 dependence on the concentration of the dopant;
however, there are some differences in the abruptness of this dependence as indicated in Fig. 10.3(b).
This is in agreement with the four electrons per silicon atom dissolution process. The mechanism for
dopant-selective behavior is discussed by Collins.53
Other methods are listed in Table 10.3. The electrochemical etch stop relies on the formation of an
anodic oxide on the silicon, which stops the etching process. The process was first demonstrated by
Waggener and has been developed for silicon microstructures by Jackson et al.54 and Kloeck et al.55
Figure 10.4 shows a typical experimental set-up in which an n/p junction is reverse-biased in the
etching tank and protected in a Teflon holder so that only the p-type surface is exposed to the solution.
Because the junction is reverse-biased, the potential on the silicon is close to the open-circuit potential
and so etching continues uninhibited. However, once the n-type material is reached, the potential
becomes that applied by the external circuit. Care must be taken to ensure that the reverse-bias leakage
current is not high enough to allow the potential on the exposed silicon to reaching a point more
positive than the passivation potential, as indicated in the figure by the operating potential for the
silicon surface. The passivation potential is the potential at which oxide forms rather than dissolution
2000 by CRC Press LLC

(a)

(b)

FIGURE 10.3 (a) Schematic diagram of a heavily doped layer diaphragm formation; (b) etch stop of heavily doped silicon
for KOH and EDP anisotropic etching solutions. (Collins, S. D., J. Electrochem. Soc., 144, 2242, 1997. With permission.)
TABLE 10.3 Silicon Membrane Fabrication Methods
Method
Timed etch
p+ heavy doping
Electrochemical
etch stop
Buried oxide layer
Si-Si bonding

2000 by CRC Press LLC

Thickness
Range
5100s m
0.15 m
0.1100 m
0.11 m

Process
Observation of diaphram
thickness as a function of time
Boron doping of ion implant to
define location of membrane
p/n junction location of
membrane
SIMOX implant of O2 dose
above 1018/cm3

Comments

Ref.
53

Membrane is highly compressive

state
Electrical contact is necessary to
wafer so special fixturing is required
Expensive; annealing damage from
surface region after implant critical
Alignment of two wafers is required

52,53

Inaccurate

5355
53
117119

(a)

(b)

FIGURE 10.4 (a) Typical experimental set-up for electrochemical etch stop method for formation of thin silicon
diaphragms (SCE is the Standard Calomel Electrode); (b) currentvoltage characteristics of the p-type (solid line)
and n-type (dashed line) silicon in 40 wt. % KOH solution at 60C, where OCP is the open circuit potential and PP
passivation potential. (Kloeck, B., et al., IEEE Trans. Electron. Dev., 36, 663, 1989. With permission.)

2000 by CRC Press LLC

takes place. The current is used as a diagnostic to indicate when the layer is removed in practical
etching procedures because a current peak occurs when the oxidation reaction occurs due to the
additional electrons required by the reaction. Once a passivating layer of oxide has formed, the current
drops to a low level of leakage current through the oxide layer. The oxide dissolution process is slow
in these solutions, and hence, if the bias is removed, after a finite time the oxide layer is removed and
etching of the silicon continues.

Electrochemical Machining and Porous Silicon

Tuller and Mlcak56 have demonstrated that anodic dissolution of silicon offers a controllable method
for the fabrication of cantilever beams, membranes, and other structures. Dopant-selective etch stop
can be achieved because p-type Si etches in HF solutions under anodic bias, whereas the n-type is
stable. However, under strong illumination, porous silicon is formed on the n-type material. Hence,
the etch rate and surface morphology are a function of the doping level, current density, and illumination level. The anodic current is a direct measure of the dissolution rate and, by defining an optically
opaque insoluble mask on the silicon surface, high aspect ratio structures have been defined in the
surface. Porous silicon is under investigation as a MEMS material as discussed by Schning et al.57 for
its extremely high surface area.
Xenon Difluoride Etching
This dry gas-phase isotropic etch process relies on sublimation of solid XeF2 at room temperature into
a vapor that selectively attacks Si over SiO2, Si3N4, and several metals.58 Hoffman et al.59 demonstrated
its use for sensors and for CMOS-compatible processing. Chu et al.60 later confirmed the minimal etch
rate of Al, Cr, TiN, and SiC. Alternatively, gas-phase isotropic etching in xenon difluoride, or reactive
ion etching methods may be selected. Tea et al.61 has studied several of these methods and concluded
that EDP can attach the Al bonding pads, whereas XeF2 shows excellent compatibility. Microheaters for
chemical sensors and microwave transmission lines were successfully fabricated; however, there was a
lack of compatibility with catalytic metals such as Pt, Ir, and Au.
RIE Etching
Dry etching offers the advantages of controlled dimensions independent of the crystal planes in the
substrate, in addition to higher dimensional control to sub-micron over wet chemical methods. The
process utilized either a dc, RF, microwave, or inductively coupled energy to excite a plasma of reactive
ions and accelerate them to the substrate. Depending on the ion acceleration potential utilized and
the gas pressure, there are very different process characteristics. Figure 10.5 shows the different
processes of (a) sputtering by physical bombardment of the surface, (b) chemical etching which is
isotropic, and (c) reactive ion etching in which the ion bombardment enhances the chemical etching
rate. This ion-assisted mechanism provides anisotropy, which is useful technologically for the fabrication of high aspect ratio structures. Ion milling represents the processes at high potentials where
sputtering is dominant and at the other extreme at low substrate bias plasma etching where chemistry
plays the dominant role. The reader is referred to excellent texts on dry etching equipment and
processing methods.62,63 Key factors in the design of dry etching processes for films are the selectivity
with respect to the masking layer and with respect to the substrate material. The etch rate, uniformity,
and anisotropy are other key process parameters.
Deep-RIE Etching
Deep-RIE etching was developed by the application of a novel etch chemistry and high-density plasmas
created by either microwave or inductively coupled sources. Mixed gas chemistries can be utilized to
provide sidewall passivation and further increase the anisotropy of the process. Selectivities with respect
to a photoresist mask of 200:1 can be reached, allowing one to etch completely through a silicon wafer.
Bhardwaj et al.64 have demonstrated deep reactive ion etching by alternating between deposition of a

2000 by CRC Press LLC

FIGURE 10.5 (a) Sputtering, (b) plasma etching, and (c) reactive ion etching.

passivating film and etch chemistry. The surface is coated with a Teflon-like material and the material
remains on the sidewalls; however, ion bombardment removes it from the horizontal surfaces. Typically,
a low bias voltage is utilized so that the mask erosion rate is minimized. An example of grooves etched
with this process is given in Fig. 10.6.
Corner Compensation
Corner compensation of the bulk etched structure is important to maintain the shape of a micromachined structure. For example, microchambers for DNA sequencing by hybridization have been fabricated with corner compensation structures oriented in the [110] direction.65 A great deal of work
has examined the compensation of exposed corners for etching in KOH solutions under different
conditions.66 The shape of the compensation structure is shown in Fig. 10.7. There are several commercially available CAD tools for silicon bulk etching. Figure 10.7(c) is an example of a etched cantilever
in CsOH solution. The CAD simulation shows the faceting high-index planes and the general features
of the structure.

10.4 Surface Micromachining

Surface micromachining involves depositing thin layers of polysilicon as a structural layer and phosphosilicate glass as a sacrificial layer (see Fig. 10.8), as first demonstrated by Howe and Muller.67 These
layers are typically less than 2 m in thickness, and etching away the PSG layer in a HF-based etching
process. Undercut etch rates have been characterized, and the maximum dimensions of the thin
polysilicon beams are limited due to internal stresses and the mechanical strength of the polysilicon.68
Fine-grained polysilicon deposited at 580C is subsequently annealed for surface micromachining to

2000 by CRC Press LLC

(a)

(b)

FIGURE 10.6 (a) Method of side-wall passivation during RIE etching; (b) slot produced by deep RIE etching process.
(Bhardwaj, J. et al. in Microstructures and Microfabricated Systems-III, Proceedings of the Electrochemical Society, 975, 118, 1997. With permission.)

produce low stress polysilicon. Guckel et al.69 have demonstrated that post-deposition anneal conditions are key to defining the low stress characteristics of polysilicon, as shown in Fig. 10.9. Conductive
regions are defined by ion implantation. An alternative process is to carry out in situ doping with
phosphourus and a relatively rapid deposition rate, followed by an RTA at 950C to produce a low
tensile stress film with a small stress gradient through the film.70 Polysilicon is an extremely stable
and good-quality material for producing micromechanical elements, as demonstrated by the success
of these devices (examples are given in the next section). Sealing of surface micromachined structures
has been developed for absolute pressure sensors by reactive sealing of small openings in the surface
or by dry deposition of another layer of material like silicon nitride.71 Surface micromachining is not
limited to poly-Si and PSG. A wide range of material combinations have been studied.15 Machining
with aluminum as the structural layer and a photoresist as the sacrificial layer is discussed by Westerberg et al.72

2000 by CRC Press LLC

(a)

(b)
FIGURE 10.7(a-b) (a) Exposed corner etched in 50 wt% CsOH for 4 hours; (b) corner compensation structure 20m wide after etching for 3 hours in 49 wt% KOH.

2000 by CRC Press LLC

(c)

(d)
FIGURE 10.7(c-d) (c) Etched cantilever beams in silicon dioxide by etching in CsOH solution; (d) example of CAD
simulation of etched cantilever structures in silicon. (Shih, B. et al., submitted to J. Electrochem Soc., 1998. With
permission.)

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FIGURE 10.8 Cross-sectional diagram of processing steps in the surface micromachining process. (Courtesy of Tong,
W. C. et al. Sensors and Actuators, 20, 25, 1989. With permission.)

Stiction
Stiction in surface micromachined structures is an issue that must be addressed due to the very small gaps
present between surfaces. Tas et al.73 investigated the origins of stiction in surface micromachined devices
2000 by CRC Press LLC

and found that roughness plays an important role. The critical dimensions for the mechanical force to snap
back a cantilever beam against the stiction force was investigated. The energy of adhesion by liquid bridging
found that if the tip touches the substrate, the surface energy plus the deformation energy has a minimum
for a detachment length smaller than the beam length. Stiction can occur during processing or during device
operation. Various methods have been developed to avoid stiction during processing. Carbon dioxide drying
is used because, below the critical temperature of the supercritical carbon dioxide, no liquid vapor interface
exists that could cause contact. During device operation, the fail-safe requires that these surfaces do not
make contact or an adequate release force can be applied. Surface energy is only partially successful in
modifying these interactions and it is important to limit the contact area. Specifically, dimples, bumps,
sidewall spacers, or increased surface roughness can define smaller contact areas.

Materials Properties of Thin Films

The properties of thin films differ from bulk material, and measurement techniques have been developed
for in situ determination of these properties on a silicon wafer. Properties of interest are Youngs modulus,
Poisson ratio, residual stress, tensile strength, fracture toughness, thermal conductivity, density, and
optical aborbance and optical reflectivity. Finding mechanical properties of thin films as a function of
deposition conditions has been cataloged for many materials in a properties database available from
Intellisense Inc.74 Table 10.4, summarizes properties of thin-film CMOS and MEMS materials. However,
this information should be used with caution given that there is considerable variation in materials
properties as a function of the specific growth conditions due to variations in the microstructure and
the film thickness. Low-stress polysilicon has been deposited in an epitaxy reactor in a process compatible
with bipolar electronics by Gennissen et al.75 In addition, more recent work by Wenk76 has demonstrated
thick low-stress polysilicon films grown in an epitaxial growth reactor from DCS at 1000C for a
microfabricated accelerometer and inertial gyroscope. Figure 10.9(b) shows a typical biaxial stress plot
for the 3-m polysilicon tested from the MUMPS process by Sharpe et al.77 Other studies include those
of Kahn et al.,78 Maier-Schneider et al.,79 and Biebl et al.80
Silicon Nitride
Stoichiometric silicon nitride has high tensile stress and this limits the maximum film thickness that can
be fabricated on a wafer.81 Stress relaxation occurs in silicon-rich nitride as a function of the film
stoichiometry and has been characterized by Gardemoers et al.,82 Chu et al.,83 French et al.,84 and
Habermehl.85 Figure 10.10(a) shows the intrinsic stress as a function of deposition conditions for siliconrich nitride growth at several different temperatures and pressures and Fig. 10.10(b) for PECVD material.86 Other materials have been studied, including SiC87 and diamond like carbon.88

10.5 Advanced Processing

We have discussed both surface and bulk machining processes and these offer certain advantages and
limitations, as contrasted by French and Sarro.89 Due to the space limitation, there is only an opportunity
to mention a few examples of mixed-technology processes that have combined aspects of surface and
bulk machining with other processes like chemical mechanical polishing for planarization.

Chemical Mechanical Polishing

Chemical mechanical polishing is well-known in the lapping and polishing of wafers prior to fabrication.
It has been recently demonstrated as a key process for achieving multilayers of polysilicon and metallization
by Rogers and Sniegowski.90 They have achieved up to five levels of polysilicon fabrication for micromechanical actuators, linkages, gears, and mechanisms. Examples of interconnected gears, locking pins, and
movable elements are shown in Fig. 10.11. The key to this process is planarization of the surface between
polysilicon layer deposition processes by chemical mechanical polishing.91 In this process, planarization is

2000 by CRC Press LLC

TABLE 10.4 Materials Properties of LPCVD Deposited MEMS Materials

Material

Growth Conditions

Film Thickness

Property

Value

Comments

Ref.

Youngs modulus
Tensile strength
Youngs modulus
Fracture toughness
As-deposited residual stress

1696.15 GPa
1.200.15 GPa
1503- GPa 2.30.1
MPa m 280 MPa

77

undoped film

78

Youngs modulus
Tensile strength
Youngs modulus
Intrinsic stress
Intrinsicties

1687 GPa 2.110.10

GPa
162.86 GPa
35012 GPa
162.86 GPa

80

As deposited
After 1000C anneal

79

~1.2 GPa
(See Figure 10.10)

Polysilicon
3 m

MUMPS process
Thick polysilicon
Thin polysilicon

1100C, SiH4/B2H6 or 610C,

Sitty
565C, SiH4, 620C, SiH4,
100 mTorr

2.5-10 m
1 m
0.33 m

CMOS

Silicon Nitride
Standard process
Si-rich, variable
stoichiometry
Silicon-rich, variable
stoichiometry
PECVD

2000 by CRC Press LLC

800C, SiCl2H2lNH3
800, 850C 200, 410 mTorr
SiCl2H2/ NH3
850C 200 mTorr
SiCl2H2/NH3

~0.1 m

Intrinsic stress
Intrinsic stress

0.250.45 m

Youngs modulus

81
8284
85

(190 GPa)

(a)

(b)
FIGURE 10.9 (a) Stress in fine-grained polysilicon as a function of post-deposition annealing temperature and time
(Guckel, H., et al., Sensors and Actuators A, 21, 346, 1990. With permission); (b) biaxial stress for polysilicon fabricated
in the MUMPS process. (Sharpe, W. N., et al., in Proceedings of the Tenth Annual Internations Workshop on Micro
Electro Mechanical Systems, Nagoya, Japan, January, 1997, IEEE, New Jersey, Catalog Number 97CH36021, 424. With
permission.)

2000 by CRC Press LLC

(a)

(b)

FIGURE 10.10 (a) The effect of deposition parameters on the residual stress of LPCVD deposited silicon rich silicon
nitride where R is the ratio of dichlorosilone to amnoia gas flow (Gardeniers, J. G. E. et al., J. Vac. Sci. Tech. A., 14,
2879, 1996. With permission.); (b) intrinsic stress of PECVD Si3N4 as a function of processing conditions. (Classen,
W. A. P. et al., J. Electrochem. Soc., 132, 893, 1985. With permission.)
2000 by CRC Press LLC

(a)

(b)

FIGURE 10.11 (a-b) SEM micrographs of decices fabricated by the SUMMIT process: (a) gears; (b) linear spring.

2000 by CRC Press LLC

(c)

(d)

FIGURE 10.11 (c-d) (c) Mechanism; (d) hook. (Courtesy of Sandia National Laboratories Intelligent Micromachine
Initiative; www.mdl.sandia.gov/Micromachine. With permission.)

2000 by CRC Press LLC

achieved by depositing a thick layer of silicon dioxide over the polysilicon layer and polishing back to
achieve planarization.92 The process flow is shown schematically in Fig. 10.12. The key advantages of this
process are: (1) the removal of stringers without the necessity for an over-etch; (2) improvement in line
width control given that topographic features are removed; (3) removal of mechanical protrusions between
layers that can cause interference; and (4) the possibility to carry out integration by placing the mechanical
elements in a etched well in the silicon substrate (as discussed in the next section). Finally, these processing
improvements lead to higher process yield.
SCREAM processing utilizes the advantages of the properties of single-crystal silicon for producing a
wide range of elegant devices.93 This method was derived from a process to make isolated islands of
submicron silicon by local oxidation. Suspended high aspect ratio structure are fabricated by SF6 RIE
step, followed by sidewall oxidation and isotropic silicon etch to undercut the structure (see Fig. 10.13).
Both suspended structures and structures with metallized sides for electrostatic drives can be realized by
varying the width of the structure and processes, each with high out-of-plane stiffness, as defined by the
ratio of beam height to length, [h3/l3]. Examples of devices realized by this elegant process include tipon-tip sensors, microaccelerometers, electrostatic drives, torsional actuators, microloading machines, and
STM tips with integrated drive. In addition, beams filled with spin on glass isolation have been demonstrated with high thermal isolation. The planarity of large aspect ratio structures has been investigated
by Saif and MacDonald.94
HEXSIL is an RIE-etched channel and fill process that utilizes polishing for planarization.95 The trench
with controls the material that fills the grooves defined by RIE process. After the groove is coated with
an oxide layer, the body of the device is made from undoped polysilicon, followed by a doped layer, and
finally, Ni is electrolytically deposited into grooves to define highly conducting regions (see Fig. 10.14
for a process overview). The different groove width provide discrimination between different materials;
hence, three types of material combinations are defined. Once the sacrificial oxide is removed, the HEXIL
structure is released, micro-tweezers, and other structures have been defined by this method, as shown
in Fig. 10.14(b).

Electroplating into Molds

A variety of materials have been utilized for a mold into which metals can be electroplated. These include
the LIGA process, thick photoresists, polyimide,96 and SU-8.97 Photoresists often have a limited sidewall
profile; however, polyimide structures with vertical wall profiles can be processed up to 100 m in
thickness.98 The process flow is shown in Fig. 10.15 that utilizes a standard optical mask and standard
UV exposure system. A spiral inductor structure produced by Ahn et al.99 is shown in Fig. 10.15(b). A
30-m thick nickel-iron permalloy magnetic core is wrapped with 40-m thick multilevel copper conductor lines. [The magnetic circuit consists of an inductor 4 1 0.13 mm3 having 33 turns, with an
inductance of 0.4 H at 1 kHz to 1 MHz.] Applications of inductive components are for microsensors,
microactuators, and magentic power devices such as dc-to-dc converters. Layers of copper conductor
and high-permeability NiFe are electroplated to form a high-value inductance with parallel and spiral
coils.100 The process SU-8 is a negative-acting epoxy resin that has been fabricated up to 100 m thick
layers in a standard alignment system (see example in Fig. 10.16). Multiple levels of metallization have
been developed of ULSI copper plating by the metal is formed by the Damascene process with a
photoresist mold. Planarization is achieved by chemical mechanical polishing, which relies on the materials (metals and dielectics) having similar abrasion rates.

LIGA Process
LIGA is an acronym from the German Lithographie, Galvanoformung, und Abformung, denoting the
use of X-ray lithography from a synchrotron source, in thick PMMA layers to define structures with very
high aspect ratios, followed by nickel electroplating, and subsequent replication by injection molding.101
Because LIGA is based on X-ray radiation, it is not compatible with CMOS processing. The intensity of

2000 by CRC Press LLC

FIGURE 10.12 Schematic diagram of processing steps in the SUMMIT process for polysilicon MEMS. (Courtesy
of Sandia National Laboratories Intelligent Micromachine Initiative; www.mdl.sandia.gov/Micromachine. With
permission.)
2000 by CRC Press LLC

FIGURE 10.13 Cross-sectional diagram of the SCREAM process for the formation of silicon cantilevers with
aluminum electrodes adjacent to each side of the beam. The undercut of the silicon sidewalls isolate the aluminum
from the substrate. (McDonald, N. C., Microelectroic Engineering, 32, 49, 1996. With permission.)

2000 by CRC Press LLC

(a)

(b)

FIGURE 10.14 (a) Cross-sectional schematic of the HEXIL process; (b) micro-tweezers produced by the HEXIL
process. (Keller, C., Microfabricated High Aspect Ratio Silicon Flexures, ISBN 0-9666376-0-7. With permission.)

2000 by CRC Press LLC

FIGURE 10.15 Schematic representation of the process sequence for fabricating metallic electroplated microstructures using photosensitive polyimide. (Frazier, A. B., et al., Sensors and Actuators A., 45, 47, 1994. With permission.)

the X-rays produces damage in the dielectric components of the CMOS circuit. An excellent review of
recent development in LIGA processing is given by Friedrich et al.51 Optical gratings have been made by
the LIGA process by Cox et al.102; specifically, infrared tunable filters driven by magnetic actuators, features
30 m in height and a filter period of 8 to 17 m. (See Fig. 10.17.)

GaAs Micromachining
The properties of GaAs as a MEMS material have been investigated by Hjort et al.103 The key advantages
of GaAs are that it is a direct-bandgap semiconductor also having high electron mobility, so that optoelectronic devices can be realized, and the piezoelectric properties are comparable to that of quartz.
Finally, electronic devices can be operated at temperatures up to 350C. Although the mechanical strength
of the material is lower than silicon, the material can be bulk micromachined with HNO3/HF solutions.
Surface-type micromachining processes have also been developed, based on the advanced state-of-theart in modulated material doping and selective etching of AlGaAs. Interdigitated electrostatic actuators
have been realized in addition to surface acoustic wave sensors (SAW) optical sensors, and piezoelectric
sensors (see later section on optical devices).

2000 by CRC Press LLC

FIGURE 10.16 SEM photomicrograph of a high aspect ratio 100-micron thick SU-8 photoresist structure formed
by a single spin coating and contact lithography exposure. (Photo courtesy of Electronic Visions, Phoenix, Arizona.
With permission.)

10.6 CMOS and MEMS Fabrication Process Integration

One of the key challenges in micromachining processes is combining the electronic devices with the
mechanical, optical, or chemical function of the MEMS device. Although most work has utilized a hybrid
approach in which the MEMS device is fabricated independently of the interface electronics, there are
several examples of integrated sensors and other devices. The early work of Parameswaran et al.104
demonstrated a post-CMOS processing anisotropic etching in KOH solutions that was feasible under
limited conditions. The circuit elements and the MEMS devices were defined by a standard CMOS process
and then the structures were released from the substrate or thermally isolated from the silicon substrate
by a post-processing step. Requirements for such an etch are that it is compatible with exposed silicon
dioxide, and silicon nitride, on the chip. Other etching chemistry may be more suitable such as XeF2 or
TMAH. Another issue is ionic contamination which leads to failure of the CMOS devices through mobile
ions present in the gate dielectric,105 producing instability in threshold voltages.
There have been several approaches for combining CMOS circuits with MEMS structures, summarized
as follows:
Post-processing : protecting the CMOS circuit with a chemically resistant film(s) and carrying out
the micromachining after the circuits are complete and avoiding any high-temperature steps.
Combined processing: integration in a custom MEMS/CMOS process or utilizing the CMOS layers
themselves for MEMS devices.

2000 by CRC Press LLC

FIGURE 10.17

Schematic diagram of the LIGA process modified for MEMS.

Pre-processing: etching wells in the wafer of a depth equal to the total height for the formation
of the MEMS device. Fabrication of MEMS devices and protection with an encapsulation layer
that is planar with the silicon surface. CMOS circuit fabrication then follows, and removal of the
encapsulating film releases the MEMS structure.

Post-processing
Micromachined thermally isolated regions have been developed by Parameswaran et al.106 in a CMOScompatible process for infrared emitter arrays. Post-processing was carried out following a commercial
Northern Telecom Canada Ltd. COMS3 DLM (3-m 13 mask) process. Openings are defined in layers
so that the silicon surface is exposed for the EDP etching. The active devices, both p-MOS and n-MOS,
were tested after etching and there was no change in device performance.
Fedder et al.107 have demonstrated the fabrication of intricate structures with a standard CMOS process.
Structures are designed in the metal and polysilicon layers and aligned so that a post-processing dry etch
step defines the dimensions and a post-processing etch undercuts the structure. Releasing it from the
substrate is carried out by RIE etching (see Fig. 10.18). Electrostatic comb drives actuate microstructures
that are 107 m wide and 109 m long show a resonance amplitude of 1 m with an ac drive voltage
of 11 V. The effective Youngs modulus of the structure was found to be 63 GPa. The design rules are as
follows. The scaling factor for the 0.8-m process is = 0.4 m. The minimum beam width is 3 (1.2
m), and the minimum gap is 3 (1.2 m); however, for holes, a minimum dimension of 4 m is required
for release. The CMOS circuit is protected by metal-3 to prevent etching. The metal-1 and -2 collar is
inserted underneath the break in metal-3 to prevent the etch from reaching the surface and facilitating
electrical interconnects to the MEMS structure.
Finally, planarization techniques have been developed by Lee et al.108 to prepare a foundry-fabricated
chip for post-processing by other low-temperature methods, including electroforming, LIGA, and reactive
ion etching.

2000 by CRC Press LLC

FIGURE 10.18 Example of the use of variable anisotropy dry etch on prefabricated CMOS integrated circuit using
the upper level of metallization as the mask: (1) CMOS cross-section, (2) anisotropic CHF3/O2 RIE process, (3)
anisotropic SF6/O2 RIE process, and (4) isotropic SF6/O2 RIE process. (Fedder, G. K. et al., in Proceedings of the
International Meeting on MicroElectroMechanical Systems, IEEE, p. 13, 1996. With permission.)

Mixed Processing
The surface micromachined accelerometer manufactured at analog devices utilizes an integrated process.
The BiCMOS process is interleaved with the micromachining so that the higher-temperature steps are
completed first; then the lower temperature steps and metallization complete the device fabrication.
A different approach has been taken by the group at the Univesity of California at Berkeley, using
high-temperature metallization of tungsten and titanium silicide and TiN barrier layers to replace the
aluminum.109 A double polysilicon single metal, n-well CMOS technology is fabricated first, encapsulated
with PSG and low-stress nitirde, as shown schematically in Fig. 10.19.

Pre-processing
Smith et al.110 pioneered the pre-processing of fabricating the MEMS device in a buried well and then
encapsulation with a protective passivation film, which is later be removed once the CMOS process is
complete. The key to this process is the use of CMP to planarize the surface after MEMS device fabrication
and before the CMOS fabrication is begun. The release etch must be highly selective to materials in the
MEMS structure and not damage the CMOS outer layers of material (see Fig. 10.19). This process has
been very successful in fabricating structures such as pressure sensors, electronic oscillators, microaccelerometers, and gyroscopes. Also, Gianchandani et al.111 have demonstrated pre-processing integration of
thick polysilicon microstructures with a CMOS process. Silicon-to-silicon bonding has been utilized for
sensor integration with a pre-etched sealed cavity process,112 shown in Fig. 10.19(b). The thin membrane
formed undergoes plastic deformation, and as a result, the proper design of the cavity geometry is critical
to control the gas pressures during bonding. Pressure sensors, accelerometers, and gas flow shear stress
sensors have been demonstrated with and without integrated electronics. Lowering the bonding temperature is of key interest to allow more widespread use of this bonding method because of its incompatibility with many materials and processes.

2000 by CRC Press LLC

(a)

(b)
FIGURE 10.19 (a) Schematic cross-section of the modular integration of CMOS and microstructures technology
using post-IC MEMS fabrication with tungsten interconnect technology; (b) a cross-sectional schematic of the
subsurface, embedded MEMS integrated technology. (Sniegowski, J. J., in Microstructures and Microfabricated SystemsIV, Vol. 98-14, Ed: P.J. Hesketh, H. Hughes, and W. E. Bailey, The Electrochemical Society, Pennington, New Jersey,
1998. With permission.)

10.7 Wafer Bonding

Anodic bonding was first demonstrated by Wallis and Pemerantz113 and can be carried out between a
range of glass/metal sealing combinations. The key to obtaining a reliable to bond is to minimize the
stress; thus, the glass must be selected very carefully to match the expansion coefficient with the silicon.
For example, the expansion coefficient of silicon is a function of temperature and that of Pyrex glass is
much less so (Fig. 10.20). Sodium ions that become mobile at elevated temperatures (>300C) produce
a depletion layer at the silicon/glass interface.114 The resulting electrostatic attraction between these two
charge layers brings the surfaces into intimate contact, and a chemical bonding takes place that is
irreversible and strong. This bond is hermetic and is widely used in microsensor technology for pressure
sensors and other devices, such as fluid pumps and valves.115 The process compatibility with CMOS is

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TABLE 10.5 Wafer Bonding Techniques

Bonding
Technique
Anodic
bonding
Siliconsilicon
Borosilicate
glass
Eutectic

Materials
Silicon/7740
Pyrex glass
Si-Si
SiO2-Si and
SiO2/SiO2
Si/Si02 and
Si3N4
Si-Au-SiO2

Solder

SiO2Pb/Sn/AgSiO2

Glass frit

SiO2-glass Ag
mixture-SiO2

Surface
Treatment
Clean
Hydrophobic
Hydrophilic

Clean and
oxide-free
Needs solder
flux

Clean

Process

Time

350450C
~500-1000V
5001100

~1-10 min

450

30 min

~350

250400

min

~350

<hr

Hrs

Bond
Strength/Comments
1-3 MPaa/uniform reliable
hermetic bond formed
Difficult to avoid voids
unless processed at
higher temperatures

148 MPab/Nonuniform
bonding area
Large difference in
thermal expansion
coefficient can lead to
mechanical fracture
Difficult to form thin
layers

Ref.
113,116
117,118

120,122
119
119

121

under investigation.116 The circuit is protected from the large electrostatic fields by shorting the gate
regions together with a polysilicon strip. After bonding, regions were opened up in this area to facilitate
etching. In addition, cavities were drilled ultrasonically in the Pyrex wafer to reduce the electric field
over the active circuits.
The key advantage of silicon-silicon direct bonding is that the same material is used so there are
minimal thermal stresses after bonding. The wafers must be flat, scrupulously clean, and in prime
condition to achieve a reliable bond. First, the wafers are chemically cleaned and surface-activated in a
nitric acid solution. Then the wafers are bonded at room temperature in a special jig that has been
demonstrated to improve the bonding yield, as shown in Fig. 10.21.117 A subsequent anneal step increases
the bonding strength through a chemical reaction that grows a very thin silicon dioxide layer at the
interface (Fig. 10.21(b)). The wafers can be inspected for voids utilizing an infrared microscope or an
ultrasonic microscope. High yield has been achieved and the community that develop silicon-on-insulator
technology have published conference proceedings on these methods.118
Other bonding methods are listed in Table 10.6; these include eutectic,119 low-temperature glass,120
glass frit,121 and borosilicate glass.122 Materials are selected to minimize the stresses in the bond by selecting
a match in the thermal expansion coefficients, or a compliant layer is utilized at the interface.

10.8 Optical MEMS

There is great interest in taking advantage of MEMS devices for the manipulation of optical beams
for which they are naturally suited, because of the ease of batch fabrication into large arrays, the small
forces required, and the high speed of operation. Examples of devices that have been demonstrated
include chopper beam steering, diffraction gratings, optical scanners, Fabre-Perot interferometer,
sensors, and spectrometers on a chip. This demonstrates the high speed of operation that is achievable
with MEMS technology. A recent excellent review of MEMS devices is given by Wu123 and an earlier
paper by Motamedi.124

Components
In the first generation of microfabricated optical components, hybrid assembly into optical devices was
carried out rather than integrated functionality. Various optical components were reviewed by Motamedi
et al.,125 including diffractive optical components integrated with infrared detectors, refractive micro-optics,

2000 by CRC Press LLC

(a)

(b)

FIGURE 10.20 (a) Schematic diagram showing anodic bonding process and potential distribution; (b) thermal
expansion coefficient of Si and Pyrex glass as a function of temperature. (Peeters, E., Process Development for 3D
Silicon Microstructures with Application to Mechanical Sensors Design, Ph.D. thesis, Catholic University of Louvain,
Belgium, 1994. With permission.)

2000 by CRC Press LLC

(a)

(b)

(c)

FIGURE 10.21 (a) Schematic diagram of set-up for direct silicon-to-silicon wafer bonding process (Cha, G. et al.,
in Proc. First Int. Symp. Semicond. Wafer Bonding Sci. Tech. Appl., Eds, Gsele, U. et al., The Electromechanical Society,
Pennington, NJ, p. 249, 1992 and Masgara, W. P. et al., J. Appl. Phys., 64, 4943, 1989. With permission.); (b) bond
strength versus anneal temperature for silicon-silicon direct bond (Mitani, K. and Gsele, U.M., J. Electron. Mat., 21,
669, 1992. With permission.); (c) method for formation of silicon diaphragm by silicon to silicon bonding.
(Parameswaran L. et al., in Meeting Abstracts of the 194th Meeting of the Electrochemical Society, Boston, Nov. 1-6th,
Abst #1144, 1998. With permission.)

2000 by CRC Press LLC

and microlenses. However, the integration of optical components into a micro-optical bench offers several
advantages over guided wave approaches; in particular, high spatial bandwidth, independent optical routing
3-D interconnects, and optical signal processing. Moving the individual optical elements out of the plane
has greatly expanded the utility of this method.126 Micro-electrostatic deformable mirrors have also been
demonstrated as an effective method for reducing aberrations.127
Tunable semiconductor laser diodes have been demonstrated by Uenishi et al.128 with anisotropically
etched (110) silicon substrates and hybrid assembly. A cantilever 1.7 mm long and 8 m wide defines a
(111) surface reflecting mirror normal to the substrate provided modulation from 856 to 853 nm, with
a drive of 12.5 V. The etching conditions in KOH solutions were optimized for minimum surface
roughness of the (111) surface.
External mirrors for edge emitting lasers can also be produced in GaAs by micromachining. Larson
et al.129 have demonstrated a Fabry-Perot mirror interferometer by combining a GaAs-AlAs vertical cavity
laser VCSEL with a suspended movable top mirror membrane. The bottom mirror is a 12.5 period
GaAs/AlAs distributed Bragg reflector of 640 /775 thickness with a center wavelength of 920 nm. The
GaAs laser had a center wavelength of 950 nm and a cavity of 2580 thick GaAs layer. The top electrode
was 2230 SiNxHy with a nominal 200- Au reflector. The air gap thickness is modulated around 3/4
with electrostatic means to provide a 40-nm tuning range with an 18-V drive. Figure 10.22(b) shows the
reflectance spectra from the device.

(a)

(b)

FIGURE 10.22 (a) Schematic diagram of coupled-cavity microinterferometer; (b) membrane voltage and reflected
photocurrent traces for the device acting as an intensity modulator for an active wavelength of 933 nm. (Larson, M.
C. et al., IEEE Phot. Tech. Lett., 7, 382, 1995. With permission.)

2000 by CRC Press LLC