TCI6636K2H Datamanual

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
Data Manual
PRODUCT PREVIEW information applies to products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Literature Number: SPRS835D August 2013
TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

SPRS835DAugust 2013
www.ti.com
Release History
Release SPRS835D Date August 2013 Description/Comments Added SRIOSGMIICLK clocking info to the table. (Page 305) Corrected USBVBUS terminal designation. It is not reserved. (Page 58) Added the bridge numbers to the Interconnect tables in the System Interconnect chapter (Page 194) Added the TeraNet drawings to the System Interconnect chapter (Page 190) Updated the Power-Up Sequence information in the Peripheral Information and Electrical Specifications chapter (Page 271) Corrected Event (48-80) Names (Page 116) Changed SerDes field to Reserved as it is not implemented (Page 224) Added DEVSPEED address (Page 241) Removed PLLLOCK LOCK, STAT and EVAL registers (Page 241) Changed CPTS_RFTCLK_SEL from three bits to four bits (Page 326) SPRS835C May 2013 Updated BOOTMODE pins and MIN information (Page 192) Added the Boot Parameter Table section (Page 207) Changed bit to pin (Page 208) Updated the PWRSTATECTL register (Page 229) Updated the ALNCTL Register in the Peripheral Information and Electrical Specifications chapter. (Page 268) Updated the DCHANGE Register in the Peripheral Information and Electrical Specifications chapter. (Page 268) Corrected rise and fall time of all differential clock pairs (Page 275) Added ARMCLK specification (Page 275) Corrected rise and fall time of differential clock pairs (Page 276) Changed to not support external charge pump for 5V (Page 305) Added additional information (Page 309) Updated BOOTMODE pins and MIN information (Page 192) SPRS835B November 2012 Added Terminal Functions Reorganized memory content in Memory, Interrupts, and EDMA for TCI6636K2H Added device Pin Map SPRS835A August 2012 Added C66x CorePac chapter. Added ARM CorePac chapter. Added Memory Map and Terminals chapter. Added System Interconnect chapter. Added Device Boot and Configuration chapter. Added Security section Added Device Operating Conditions chapter. Added Peripheral Information and Electrical Specifications chapter. Added Mechanical Data chapter. Added thermal values into the Thermal Resistance Characteristics table. SPRS835 February 2012 Initial Release
Release History
Copyright 2013 Texas Instruments Incorporated

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SPRS835DAugust 2013
Contents
1 TCI6636K2H Features and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Enhancements in KeyStone II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 C66x DSP CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 ARM CorePac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.9.2 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.9.3 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.10 Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.1.4 Multicore Shared Memory SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.5 C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.6 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
ARM CorePac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.2 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3 ARM Cortex-A15 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3.3 ARM Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.4 Endianess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.4 CFG Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.5 Main TeraNet Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.6 Clocking and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.6.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.1 4.2 4.3 4.4 Package Terminals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Memory, Interrupts, and EDMA for TCI6636K2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.1 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.2 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 5.2.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.2.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.2 CIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.3.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.4 Enhanced Direct Memory Access (EDMA3) Controller for TCI6636K2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Contents

SPRS835DAugust 2013 5.4.1 5.4.2 5.4.3 5.4.4
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EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
178 178 178 179 188 189 198 208 209 209 211 233 233 235 235 236 236 261 262 263 264 265 265 266 272 273 273 275 275 276 277 282 282 283 284 284 285 285 285 285 286 288 291 297 298 299 302 302 303 304 304 305 305 306
System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

6.1 6.2 6.3 6.4 Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Fabric Connections Matrix - Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Fabric Connections Matrix - Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Boot and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.1 Device Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Boot Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 SoC Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 System PLL Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Device Configuration at Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Device State Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.1 8.2 8.3 8.4 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCI6636K2H Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

9.1 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.5 ARM CorePac Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.6 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.7 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.8 Reset Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.3 Main PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.4 ARM PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.5 Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 DDR3A PLL and DDR3B PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.1 DDR3A PLL and DDR3B PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.3 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 PASS PLL Local Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.2 PASS PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.3 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents

www.ti.com
SPRS835DAugust 2013 306 307 307 308 308 309 309 309 309 310 311 313 313 316 318 319 319 320 320 322 323 323 323 324 324 324 324 324 325 325 325 325 325 326 326 327 329 329 329 329 330 330 330 333 333 334 336 337 338 339 339 341 342 342
9.7.4 PASS PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.1 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9 DDR3A and DDR3B Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9.2 DDR3 Slew Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9.3 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10.2 I2C Peripheral Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.11 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.11.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.12 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.13 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.14 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.15 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.16 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.18 SGMII Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.19 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.19.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.19.2 Timers Electrical Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.20 Rake Search Accelerator (RSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.21 Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.22 Turbo Decoder Coprocessor (TCP3d). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.23 Turbo Encoder Coprocessor (TCP3e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.24 Bit Rate Coprocessor (BCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.25 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.25.1 Serial RapidIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.26 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.26.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.26.2 GPIO Peripheral Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.26.3 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.27 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.28 Antenna Interface Subsystem 2 (AIF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.29 Receive Accelerator Coprocessor (RAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.30 Transmit Accelerator Coprocessor (TAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.31 Fast Fourier Transform Coprocessor (FFTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.32 Universal Serial Bus 3.0 (USB 3.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.33 Universal Subscriber Identity Module (USIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.34 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.34.1 EMIF16 Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.35 Emulation Features and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.35.1 Chip Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.35.2 ICEPick Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36 Debug Port (EMUx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.1 Concurrent Use of Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.2 Master ID for HW and SW Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.3 SoC Cross-Triggering Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.4 Peripherals-Related Debug Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.5 Advance Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.6 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.36.7 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

B.1 B.2 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Contents

SPRS835DAugust 2013
www.ti.com
List of Figures
Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Figure 7-20 Figure 7-21 Figure 7-22 Figure 7-23 Figure 7-24 6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 C66x DSP Device Nomenclature (including the TCI6636K2H DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CorePac Revision ID Register (MM_REVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 KeyStone II ARM CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 ARM Interrupt Controller for Four Cortex-A15 Processor Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 AAW 1517-PIN BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Pin Map Panels (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 TCI6636K2K Pin Map Left Side Panel (A) Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 TCI6636K2K Pin Map Left Center Panel (B) Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 TCI6636K2K Pin Map Right Center Panel (C) Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 TCI6636K2K Pin Map Right Side Panel (D) Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 TeraNet 3_A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 TeraNet 3_A-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 TeraNet 3_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 TeraNet C66x to SDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 TeraNet 3P_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 TeraNet 3P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 TeraNet 6P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 TeraNet 3P_Tracer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 DEVSTAT Boot Mode Pins ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 Sleep Boot Mode Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 I2C Passive Mode Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 I2C Master Mode Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 SPI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 EMIF Boot Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 NAND Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 Serial Rapid I/O Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 Ethernet (SGMII) Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 PCIe Boot Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 UART Boot Mode Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 NMI Generation Register (NMIGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 IPC Acknowledgement Registers (IPCARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Copyright 2013 Texas Instruments Incorporated
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SPRS835DAugust 2013 IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 Reset Mux Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 Device Speed Register (DEVSPEED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Chip Miscellaneous Control Register (CHIP_MISC_CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Chip Miscellaneous Control Register (CHIP_MISC_CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 System Endian Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 SYNECLK_PINCTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 IO-Before-Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 SmartReflex 4-Pin 6-bit VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Soft/Hard Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 PLL Secondary Control Register (SECCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 Main PLL Control Register 0 (MAINPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Main PLL Control Register 1 (MAINPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 ARM PLL Control Register 0 (ARMPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 ARM PLL Control Register 1 (ARMPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 Main PLL Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 DDR3A PLL and DDR3B PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 DDR3A PLL and DDR3B PLL Control Register 0 (DDR3APLLCTL0/DDR3BPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 DDR3A PLL and DDR3B PLL Control Register 1 (DDR3APLLCTL0/DDR3BPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 PASS PLL Control Register 0 (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 PASS PLL Control Register 1 (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 NMI and LRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 SPI Master Mode Timing Diagrams Base Timings for 3-Pin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 SPI Additional Timings for 4-Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 UART CTS (Clear-to-Send Input) Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 List of Figures 7
Figure 7-25 Figure 7-26 Figure 7-27 Figure 7-28 Figure 7-29 Figure 7-30 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 9-7 Figure 9-8 Figure 9-9 Figure 9-10 Figure 9-11 Figure 9-12 Figure 9-13 Figure 9-14 Figure 9-15 Figure 9-16 Figure 9-17 Figure 9-18 Figure 9-19 Figure 9-20 Figure 9-21 Figure 9-22 Figure 9-23 Figure 9-24 Figure 9-25 Figure 9-26 Figure 9-27 Figure 9-28 Figure 9-29 Figure 9-30 Figure 9-31 Figure 9-32 Figure 9-33 Figure 9-34 Figure 9-35 Figure 9-36 Figure 9-37 Figure 9-38 Figure 9-39 Figure 9-40 Figure 9-41

SPRS835DAugust 2013 Figure 9-42 Figure 9-43 Figure 9-44 Figure 9-45 Figure 9-46 Figure 9-47 Figure 9-48 Figure 9-49 Figure 9-50 Figure 9-51 Figure 9-52 Figure 9-53 Figure 9-54 Figure 9-55 Figure 9-56 Figure 9-57 Figure 9-58 Figure 9-59 Figure 9-60 Figure 9-61
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UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 UART RTS (Request-to-Send Output) Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 MACID1 Register (MMR Address 0x02620110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 MACID2 Register (MMR Address 0x02620114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 RFTCLK Select Register (CPTS_RFTCLK_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 AIF2 RP1 Frame Synchronization Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 AIF2 RP1 Frame Synchronization Burst Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 AIF2 Physical Layer Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 AIF2 Radio Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 AIF2 Timer External Frame Event Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 EMIF16 Asynchronous Memory Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 EMIF16 Asynchronous Memory Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 EMIF16 EM_WAIT Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 EMIF16 EM_WAIT Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
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SPRS835DAugust 2013
List of Tables
Table 1-1 Table 2-1 Table 2-2 Table 3-1 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20 Table 5-21 Table 5-22 Table 5-23 Table 5-24 Table 5-25 Table 5-26 Table 5-27 Table 5-28 Table 5-29 Table 5-30 Table 5-31 Table 5-32 Table 5-33 Table 5-34 Table 5-35 Table 5-36 Table 5-37 Table 5-38 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Characteristics of the TCI6636K2H Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Cortex-A15 Processor Core Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Terminal Functions Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Terminal Functions Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Terminal Functions By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Terminal Functions By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Device Memory Map Summary for TCI6636K2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 MPU0-MPU5 Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 MPU6-MPU11 Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 MPU12-MPU14 Default Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 MPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Programmable Range n Start Address Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 MPU0-MPU5 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . .103 MPU6-MPU11 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values. . . . . . . . . . . . . . . . . . . . . . .103 MPU12-MPU14 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values . . . . . . . . . . . . . . . . . . . . .104 Programmable Range n End Address Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 MPU0-MPU5 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values. . . . . . . . . . . . . . . . . . . . . . . . .105 MPU6-MPU11 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . .105 MPU12-MPU14 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values . . . . . . . . . . . . . . . . . . . . . .106 Programmable Range n Memory Protection Page Attribute Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 MPU0-MPU5 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values. . .108 MPU6-MPU11 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values. .109 MPU12-MPU14 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values 109 System Event Mapping C66x CorePac Primary Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 System Event Mapping ARM CorePac Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 CIC0 Event Inputs C66x CorePac Secondary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 CIC1 Event Inputs C66x CorePac Secondary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 CIC2 Event Inputs (Secondary Events for EDMA3CC0 and HyperLinks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 CIC0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 CIC1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 CIC2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 EDMA3 Transfer Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 EDMA3CC0 Events for TCI6636K2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 EDMA3CC1 Events for TCI6636K2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 EDMA3CC2 Events for TCI6636K2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 EDMA3CC3 Events for TCI6636K2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 EDMA3CC4 Events for TCI6636K2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Data Space Interconnect -Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Data Space Interconnect - Section 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Configuration Space Interconnect - Section 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 Configuration Space Interconnect -Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Configuration Space Interconnect - Section 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 List of Tables 9

SPRS835DAugust 2013 Table 6-6 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table 7-23 Table 7-24 Table 7-25 Table 7-26 Table 7-27 Table 7-28 Table 7-29 Table 7-30 Table 7-31 Table 7-32 Table 7-33 Table 7-34 Table 7-35 Table 7-36 Table 7-37 Table 7-38 Table 7-39 Table 7-40 Table 7-41 Table 7-42 Table 7-43 Table 7-44 Table 7-45 Table 7-46 Table 7-47 Table 7-1 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 10
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Packed DMA Priority Allocation Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 C66x DSP Boot RAM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 ARM Boot RAM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Sleep Boot Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 I2C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 EMIF Boot Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 NAND Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 Serial Rapid I/O Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 Ethernet (SGMII) Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 PCIe Boot Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 UART Boot Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Boot Parameter Table Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 EMIF16 Boot Parameter Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 SRIO Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 Ethernet Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 PCIe Boot Parameter Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 I2C Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 SPI Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 HyperLink Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 UART Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 NAND Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 DDR3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 ARM PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 LRESETNMI PIN Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 LRESETNMI PIN Status Clear Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Reset Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 Reset Status Clear Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 Boot Complete Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 Power State Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 NMI Generation Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 IPC Generation Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 IPC Acknowledgement Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 IPC Generation Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 IPC Acknowledgement Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 Timer Input Selection Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 Timer Output Selection Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 Device Speed Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 ARM Endian Configuration Register 0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 ARM Endian Configuration Register 1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 ARM Endian Configuration Register 2 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 Copyright 2013 Texas Instruments Incorporated
List of Tables

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SPRS835DAugust 2013 System Endian Status Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 SYNECLK_PINCTL Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Power Supply Rails on the TCI6636K2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 IO-Before-Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 PLL Secondary Control Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 PLL Controller Divider Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 PLL Controller Clock Align Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 PLLDIV Divider Ratio Change Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 SYSCLK Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 Reset Type Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Reset Control Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Reset Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 Reset Isolation Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 ARM PLL Control Register 0 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 ARM PLL Control Register 1Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 DDR3 PLL DDRCLK(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 PASS PLL Clock Domain Module Internal Clock Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 PASS PLL Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 NMI and LRESET Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 I2C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 I2C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 List of Tables 11
Table 7-6 Table 7-7 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 9-1 Table 9-2 Table 9-3 Table 9-4 Table 9-5 Table 9-6 Table 9-7 Table 9-8 Table 9-9 Table 9-10 Table 9-11 Table 9-12 Table 9-13 Table 9-14 Table 9-15 Table 9-16 Table 9-17 Table 9-18 Table 9-19 Table 9-20 Table 9-21 Table 9-22 Table 9-23 Table 9-24 Table 9-25 Table 9-26 Table 9-27 Table 9-28 Table 9-29 Table 9-30 Table 9-31 Table 9-32 Table 9-33 Table 9-34 Table 9-35 Table 9-36 Table 9-37 Table 9-38 Table 9-39 Table 9-40 Table 9-41 Table 9-42 Table 9-43 Table 9-44 Table 9-45 Table 9-46 Table 9-47 Table 9-48

SPRS835DAugust 2013 Table 9-49 Table 9-50 Table 9-51 Table 9-52 Table 9-53 Table 9-54 Table 9-55 Table 9-56 Table 9-57 Table 9-58 Table 9-59 Table 9-60 Table 9-61 Table 9-62 Table 9-63 Table 9-64 Table 9-65 Table 9-66 Table 9-67 Table 9-68 Table 9-69 Table 9-70 Table 9-71 Table B-1
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RFTCLK Select Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 MDIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 AIF2 Timer Module Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 AIF2 Timer Module Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328 EMIF16 Asynchronous Memory Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 ICEPick Debug Secondary TAPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 Emulation Interface with Different Debug Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 MSTID mapping for Hardware Instrumentation (CPTRACERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 MSTID Mapping for Software Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 Cross-Triggering Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 TI XTRIG Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Peripherals Emulation Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341 EMUSUSP Core Summary (for EMUSUSP handshake to DEBUGSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341 Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 Thermal Resistance Characteristics (PBGA Package) AAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
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1 TCI6636K2H Features and Description

1.1 Features
Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point DSP Core 38.4 GMacs/Core for Fixed Point @ 1.2 GHz 19.2 GFlops/Core for Floating Point @ 1.2 GHz Memory 32K Byte L1P Per CorePac 32K Byte L1D Per CorePac 1024K Byte Local L2 Per CorePac ARM CorePac Four ARM Cortex-A15 MPCore Processors at Up To 1.4 GHz 4MB L2 Cache Memory Shared by Four ARM Cores Full Implementation of ARMv7-A Architecture Instruction Set 32KB L1 Instruction and Data Caches per Core AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low Latency Access to Shared MSMC SRAM Multicore Shared Memory Controller (MSMC) 6 MB MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac Memory Protection Unit for Both MSM SRAM and DDR3_EMIF Hardware Coprocessors Two Turbo Decoders Supports WCDMA/HSPA/HSPA+/TD-SCDMA, LTE, LTE-A and WiMAX Supports Up To 282 Mbps for LTE at Block Size 6144, 8 Iterations and Up To 206 Mbps for WCDMA at Block Size 5114, 8 Iterations Low DSP Overhead HW Interleaver Table Generation and CRC Check Four Viterbi Decoders Supports Up To 50 Mbps (Length 9, Rate 1/3, Block Size 2500) Two WCDMA Receive Acceleration Coprocessors Supports Up To 8192 Correlators WCDMA Transmit Acceleration Coprocessor Supports Up To 2304 Spreaders Four Fast Fourier Transform Coprocessors Support Up To 2400 Mscps at FFT Size 1024 Bit Rate Coprocessor WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A and WiMAX Uplink and Downlink Bit Processing Includes Encoding, Rate Matching/Dematching, Segmentation, Multiplexing, and More Supports Up To DL 1525 Mbps and UL 1030 Mbsp for LTE and DL 784 Mbps and UL 216 Mbsp for WCDMA/TD-SCDMA Multicore Navigator 16k Multi-Purpose Hardware Queues with Queue Manager Packet-Based DMA for Zero-Overhead Transfers Network Coprocessor Packet Accelerator Enables Support for Transport Plane IPsec, GTP-U, SCTP, PDCP L2 User Plane PDCP (RoHC, Air Ciphering) 1 Gbps Wire Speed at 1.5 MPackets Per Second Security Accelerator Engine Enables Support for IPSec, SRTP, 3GPP and WiMAX Air Interface, and SSL/TLS Security ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5 Up To 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering Ethernet Subsystem Five-Port Switch (four SGMII ports) Sixteen Rake/Search Accelerators (RSA) for Chip Rate Processing for WCDMA Rel'99, HSDPA, and HSDPA+ Reed-Muller Decoding Peripherals Six-Lane SerDes-Based Antenna Interface (AIF2) Operating at Up To 6.144 Gbps Compliant with OBSAI RP3 and CPRI Standards for 3G / 4G (WCDMA, LTE TDD, LTE FDD, TD-SCDMA, and WiMAX) Four Lanes of SRIO 2.1 Supports Up To 5 GBaud Supports Direct I/O, Message Passing Two Lanes PCIe Gen2 Supports Up To 5 GBaud Two HyperLinks Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability Supports Up To 50 GBaud Five Enhanced Direct Memory Access (EDMA) Modules Two 72-Bit DDR3 Interfaces with Speeds Up To 1600 MHz EMIF16 Interface USB 3.0 USIM Interface Two UART Interfaces 2 Three I C Interfaces 32 GPIO Pins Three SPI Interfaces Semaphore Module Twenty 64-Bit Timers Five On-Chip PLLs Commercial Case Temperature: 0C to 100C Extended Case Temperature: - 40C to 100C
PRODUCT PREVIEW information applies to products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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1.2 KeyStone Architecture

TIs KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. KeyStone is the first of its kind in that it provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink. Multicore Navigator is an innovative packet-based manager that controls 16k queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the 2-Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from the TeraNets capacity, so packet movement cannot be blocked by memory access. HyperLink provides a 50-GBaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.
PRODUCT PREVIEW
1.3 Device Description

The TCI6636K2H Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture designed specifically for high performance wireless infrastructure applications. The TCI6636K2H provides a very high performance macro basestation platform for developing all wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX. TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling. The addition of the ARM CorePac in the TCI6636K2H enables the ability for layer 2 and layer 3 processing on-chip. Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor. TI's new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for algorithms like MIMO and beamforming. The TCI6636K2H contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 basestation processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP), which handles the entire downlink bit-processing chain and much of the receive bit processing. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.
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TCI6636K2H Features and Description
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TI's scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse across all basestation platforms from Femto to Macro. The TCI6636K2H device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
1.4 Enhancements in KeyStone II

The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core cluster to enable Layer 2 (MAC/RLC) and higher layer processing. The number of DSP cores and FFTC accelerators has been doubled for 2 improvement in Layer 1 processing. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC V2 architecture improvements. Multicore Navigator supports 2 the number of queues, descriptors and packet DMA, 4 the number of micro RISC engines and a significant increase in the number of push/pops per second, compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller, USIM interface controller, and Asynchronous EMIF controller for NAND/NOR memory access. The 2-port Gigabit Ethernet switch in KeyStone I has been replaced with a 4-port Gigabit Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs and serial interface peripherals like I2C and SPI have been increased to enable more board level control functionality.
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1.5 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.
Figure 1-1 Functional Block Diagram
Memory Subsystem
72-Bit DDR3 EMIF 72-Bit DDR3 EMIF
Debug & Trace
6MB MSM SRAM
MSMC
32KBL1 L1 32KB 32KBL1 L1 32KB 32KB L1 32KB 32KB L1 32KB L1 L1 P-Cache D-Cache 32KB L1 32KB L1 P-Cache D-Cache 32KB L1 32KB L1 P-Cache D-Cache 32KB L1 32KB L1 P-Cache D-Cache P-Cache D-Cache D-Cache P-Cache P-Cache D-Cache 1024KB L2Cache Cache P-Cache D-Cache 1024KB L2 1024KB L2 Cache 1024KB L2 Cache 1024KB L2 Cache 1024KBL2 L2Cache Cache 1024KB 1024KB L2 Cache
C66x C66x C66x C66x C66x C66x C66x C66x CorePac CorePac CorePac CorePac CorePac CorePac CorePac CorePac 32KB L1 32KB L1
RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA RSA
TCI6636K2H
Coprocessors
RAC
TAC VCP2
GPIO 32
2 UART
PCIe 2
SRIO 4
AIF2 6
USB 3.0
EMIF16
Others
3 SPI
3 I2C
USIM
1GBE
1GBE
1GBE
1GBE
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Boot ROM Semaphore Power Management

32KB L1 32KB L1 32KB L1 32KB L1 P-Cache D-Cache P-Cache D-Cache
4 2 4
ARM A15 ARM A15
ARM A15 ARM A15
TCP3d
4MB L2 Cache
FFTC
PLL
5
EDMA
32KB L1 32KB L1 32KB L1 32KB L1 P-Cache D-Cache P-Cache D-Cache
BCP
8 C66x DSP Cores @ up to 1.2 GHz 4 ARM Cores @ up to 1.4 GHz
2 HyperLink
TeraNet
Multicore Navigator
Queue Manager
5-Port Ethernet Switch
Packet DMA
Security Accelerator Packet Accelerator
Network Coprocessor

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1.6 Device Characteristics

The following table provides an overview of the TCI6636K2H SoC. The table shows the significant features of the device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
Table 1-1 Characteristics of the TCI6636K2H Processor (Part 1 of 2)
HARDWARE FEATURES Cores C66x DSP ARM Cortex-A15 MPCore DDR3 memory controller (72-bit bus width) [1.5 V I/O] (clock source = DDRREFCLKN|P) 16-bit ASYNC EMIF EDMA3 (64 independent channels) [CPU/3 clock rate] High-speed 1/2/4 Serial RapidIO port (4 lanes) HyperLink (4 lanes) AIF2 (Second generation Antenna Interface) (6 lanes) IC Peripherals SPI PCIe (2 lanes) USB 3.0 USIM (1) UART 10/100/1000 Ethernet Management Data Input/Output (MDIO) 64-bit timers (configurable) (internal clock source = CPU/6 clock frequency) General-Purpose Input/Output port (GPIO) VCP2 (clock source = CPU/3 clock frequency) Encoder/Decoder Coprocessors TCP3d (clock source = CPU/2 clock frequency) FFTC (clock source = CPU/3 clock frequency) BCP (clock source = CPU/3 clock frequency) Receive Accelerator (RAC) Transmit Accelerator (TAC) Accelerators Rake/Search Accelerator (RSA) Packet Accelerator Security Accelerator
(2) 2
TCI6636K2H 8 4 2 1
1 2 1 3 3 1 1 1 2 4 1 Twenty 64-bit or Forty 32-bit 32 4 2 4 1 2 1 16 1 1 256KB 256KB 8192KB 128KB 128KB 128KB 4096KB 256KB 6MB 0x0009_0000 (PG 1.0) 0x0009_0002 (PG 1.1)
L1 program memory controller (C66x) L1 data memory controller (C66x) Shared L2 Cache (C66x) L3 ROM (C66x) On-Chip Memory Organization L1 program memory controller (ARM Cortex-A15) L1 data memory controller (ARM Cortex-A15) Shared L2 Cache (ARM Cortex-A15) L3 ROM (ARM Cortex-A15) MSMC C66x CorePac Revision ID CorePac Revision ID Register (address location: 0181 2000h)
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HARDWARE FEATURES JTAG BSDL_ID JTAGID Register (address location: 0x02620018) C66x ARM Cortex-A15 Core (V) I/O (V) 40 mm 40 mm m Product Preview (PP), Advance Information (AI), or Production Data (PD) TCI6636K2H 0x0b98102f (PG 1.0) 0x1b98102f (PG 1.1) Up to 1.2 GHz Up to 1.4 GHz SmartReflex variable supply 0.85 V, 1.0 V, 1.35 V, 1.5 V, 1.8 V, and 3.3 V AAW 1517-pin flip-chip plastic BGA 0.028 m PP
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Frequency
Voltage BGA Package Process Technology Product Status

(3)
PRODUCT PREVIEW
End of Table 1-1

1 The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details 2 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments. 3 PRODUCT PREVIEW information applies to products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice
1.7 C66x DSP CorePac

The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. The C66x CPU also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g., execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler. Each C66x DSP CorePac has two Rake and Search Accelerators (RSA) integrated on-chip. The tightly coupled accelerator RSA can be used for: Chip rate spreading of WCDMA Rel99, CDMA2000, HSDPA, and HSDPA+ Chip rate despreading and correlation of WCDMA Rel99, HSDPA, and HSDPA+ (e.g., Rake receiver, preamble detection) Reed-Muller decoding For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following documents (1.10 Related Documentation from Texas Instruments on page 21): C66x CPU and Instruction Set Reference Guide C66x DSP Cache User Guide C66x CorePac User Guide
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1.8 ARM CorePac

The ARM CorePac of the TCI6636K2H integrates an ARM Cortex-A15 Cluster (4 ARM Cortex-A15 processors) with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The ARM Cortex-A15 processor is an ARMv7A-compatible, dual-issue, out-of-order pipeline with integrated L1 caches. The implementation also supports advanced SIMDV2 (Neon technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE (Large Physical Address Extension), and multiprocessing extensions. The quad core cluster includes a 4MB L2 cache and support for AMBA4 AXI and AXI Coherence Extension (ACE) protocols.
1.9 Development Tools

1.9.1 Development Support In case the customer would like to develop their own features and software on the TCI6636K2H device, TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). The following products support development of KeyStone devices: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE), including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application Hardware Development Tools: Extended Development System (XDS) Emulator (supports multiprocessor system debug) EVM (Evaluation Module) 1.9.2 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each family member has one of two prefixes: X or [blank]. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices/tools. Device development evolutionary flow: X: Experimental device that is not necessarily representative of the final device's electrical specifications [Blank]: Fully qualified production device Support tool development evolutionary flow: X: Development-support product that has not yet completed Texas Instruments internal qualification testing. [Blank]: Fully qualified development-support product Experimental (X) and fully qualified [Blank] devices and development-support tools are shipped with the following disclaimer: Developmental product is intended for internal evaluation purposes. Fully qualified and production devices and development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that experimental devices (X) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, AAW), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]). For device part numbers and further ordering information for TCI6636K2H in the AAW package type, see the TI website www.ti.com or contact your TI sales representative. 1.9.3 Device Nomenclature Figure 1-2 provides a legend for reading the complete device name for any C66x+ DSP generation member.
PRODUCT PREVIEW
Figure 1-2
C66x DSP Device Nomenclature (including the TCI6636K2H DSP)

( _ ) TCI 66 36 K2 H ( _ ) ( _ ) AAW ( _ ) ( _ )
PREFIX X = Experimental device Blank = Qualified device DEVICE FAMILY TCI = System on Chip DEVICE CORE 66 = C66 DSP Family DEVICE NUMBER 36 ARCHITECTURE K2 = KeyStone II PLATFORM H SILICON REVISION Blank = Initial 1.0 silicon A = Silicon Revision 1.1
DEVICE SPEED RANGE Blank = 1 GHz 2 = 1.2 GHz 24 = 1.2 GHz DSP / 1.4 GHz ARM TEMPERATURE RANGE Blank = 0C to +100C (default case temperature) A = Extended temperature range (-40C to +100C) PACKAGE TYPE AAW = 1517-pin plastic ball grid array, with Pb-free solder balls and die bumps SECURITY Blank = No Security Accelerator / No SOC security X = Security Accelerator enabled D = Security Accelerator and SOC security enabled with TI developmental keys S = Security Accelerator and SOC security enabled with production keys
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1.10 Related Documentation from Texas Instruments

These documents describe the TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC). Copies of these documents are available on the Internet at www.ti.com.
64-bit Timer (Timer 64) for KeyStone Devices User Guide ARM CorePac User Guide for KeyStone II Devices User Guide Antenna Interface 2 (AIF2) for KeyStone Devices User Guide AIF1-to-AIF2 Antenna Interface Migration Guide for KeyStone Devices Bit Coprocessor (BCP) for KeyStone Devices User Guide BCP-TCP3d for KeyStone Devices Bootloader for the C66x DSP User Guide C66x CorePac User Guide C66x CPU and Instruction Set Reference Guide C66x DSP Cache User Guide Chip Interrupt Controller (CIC) for KeyStone Devices User Guide Connecting AIF2 with FFTC Debug and Trace for KeyStone Devices User Guide DDR3 Memory Controller for KeyStone Devices User Guide DSP Power Consumption Summary for KeyStone Devices External Memory Interface (EMIF16) for KeyStone Devices User Guide Emulation and Trace Headers Technical Reference Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide General Purpose AIF2 Traffic for KeyStone Devices General Purpose Input/Output (GPIO) for KeyStone Devices User Guide Gigabit Ethernet (GbE) Switch Subsystem (1 GB) for KeyStone Devices User Guide HyperLink for KeyStone Devices User Guide Inter Integrated Circuit (I C) for KeyStone Devices User Guide Interrupt Controller (INTC) for KeyStone Devices User Guide Memory Protection Unit (MPU) for KeyStone Devices User Guide Multicore Navigator for KeyStone Devices User Guide Multicore Shared Memory Controller (MSMC) for KeyStone II Devices User Guide Multicore Programming Guide Network Coprocessor (NETCP) for KeyStone Devices User Guide Optimizing Application Software on KeyStone Devices Optimizing Loops on the C66x DSP Packet Accelerator (PA) for KeyStone Devices User Guide Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide Power Sleep Controller (PSC) for KeyStone Devices User Guide Security Accelerator (SA) for KeyStone Devices User Guide Security Addendum for KeyStone II Devices
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SPRUGV5 SPRUHJ4 SPRUGV7 SPRABH8 SPRUGZ1 SPRABH6 SPRUGY5 SPRUGW0 SPRUGH7 SPRUGY8 SPRUGW4 SPRABF3 SPRUGZ2 SPRUGV8 SPRABL4 SPRUGZ3 SPRU655 SPRUGS5 SPRUGS2 SPRABH3 SPRUGV1 SPRUGV9 SPRUGW8 SPRUGV3 SPRUGW4 SPRUGW5 SPRUGR9 SPRUHJ6 SPRAB27 SPRUGZ6 SPRABG8 SPRABG7 SPRUGS4 SPRUGS6 SPRUGV2 SPRUGV4 SPRUGY6 SPRABS4 SPRUGS3 SPRUGP2 SPRUGW1 SPRUGS0
Semaphore2 Hardware Module for KeyStone Devices User Guide Serial Peripheral Interface (SPI) for KeyStone Devices User Guide Serial RapidIO (SRIO) for KeyStone Devices User Guide Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide
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Turbo Encoder Coprocessor 3 (TCP3e) for KeyStone Devices User Guide Universal Serial Bus 3 (USB3) for KeyStone II Devices User Guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide
1 Contact a TI sales office to obtain this document.
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SPRUGS1 SPRUHJ7 SPRUGP1 SPRUGV6
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22 Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback

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2 C66x CorePac
The C66x CorePac consists of several components: Level-one and level-two memories (L1P, L1D, L2) Data Trace Formatter (DTF) Embedded Trace Buffer (ETB) Interrupt controller Power-down controller External memory controller Extended memory controller A dedicated local power/sleep controller (LPSC) The C66x CorePac also provides support for big and little endianness, memory protection, and bandwidth management (for resources local to the CorePac). Figure 2-1 shows a block diagram of the C66x CorePac.
Figure 2-1 C66x CorePac Block Diagram
32KB L1P
Unified Memory Controller (UMC)
Memory Controller (PMC) With Memory Protect/Bandwidth Mgmt
C66x DSP Core Instruction Fetch 16-/32-bit Instruction Dispatch Control Registers Boot Controller In-Circuit Emulation Instruction Decode Data Path A PLLC LPSC A Register File A31-A16 A15-A0 .M1 xx xx Data Path B B Register File B31-B16 B15-B0 .M2 xx xx
L2 Cache/ SRAM 1024KB
Interrupt and Exception Controller
Extended Memory Controller (XMC)
MSM SRAM 6144KB DDR3 SRAM
GPSC .L1 .S1
RSA
RSA Data Memory Controller (DMC) With Memory Protect/Bandwidth Mgmt
External Memory Controller (EMC)
.D1
.D2
.S2
.L2
DMA Switch Fabric
CFG Switch Fabric
32KB L1D
C66x CorePac
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For more detailed information on the C66x CorePac in the TCI6636K2H device, see the C66x CorePac User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
2.1 Memory Architecture

Each C66x CorePac of the TCI6636K2H device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 6144KBmulticore shared memory (MSM). All memory on the TCI6636K2H has a unique location in the memory map (see the Memory, Interrupts, and EDMA chapter). After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.
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The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader for the C66x DSP User Guide in 1.10 Related Documentation from Texas Instruments on page 21. For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 2.1.1 L1P Memory The L1P memory configuration for the TCI6636K2H device is as follows: Region 0 size is 0K bytes (disabled) Region 1 size is 32K bytes with no wait states Figure 2-2 shows the available SRAM/cache configurations for L1P.
Figure 2-2 L1P Memory Configurations
L1P Mode Bits 000 001 010 011 100 L1P Memory
Block Base Address 00E0 0000h
1/2 SRAM 7/8 SRAM 3/4 SRAM Direct Mapped Cache
16K bytes
All SRAM
00E0 4000h 8K bytes
DM Cache
Direct Mapped Cache
Direct Mapped Cache
00E0 6000h 4K bytes 00E0 7000h 4K bytes 00E0 8000h
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2.1.2 L1D Memory The L1D memory configuration for the TCI6636K2H device is as follows: Region 0 size is 0K bytes (disabled) Region 1 size is 32K bytes with no wait states Figure 2-3 shows the available SRAM/cache configurations for L1D.
Figure 2-3 L1D Memory Configurations
L1D Mode Bits 000 001 010 011 100 L1D Memory
Block Base Address 00F0 0000h
1/2 SRAM 7/8 SRAM 3/4 SRAM 2-Way Cache
16K bytes
All SRAM
00F0 4000h 8K bytes
2-Way Cache 2-Way Cache 2-Way Cache
00F0 6000h 4K bytes 00F0 7000h 4K bytes 00F0 8000h
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2.1.3 L2 Memory The L2 memory configuration for the TCI6636K2H device is as follows: Total memory size is 8192KB Each CorePac contains 1024KB of memory Local starting address for each CorePac is 0080 0000h L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C66x CorePac. Figure 2-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.
Figure 2-4 L2 Memory Configurations
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L2 Mode Bits 000 001 010 011 100 101 110 L2 Memory
Block Base Address 0080 0000h
1/2 SRAM
512K bytes
3/4 SRAM 31/32 SRAM 15/16 SRAM 7/8 SRAM 4-Way Cache 0088 0000h
ALL SRAM
256K bytes
4-Way Cache 128K bytes 4-Way Cache 4-Way Cache 4-Way Cache
008C 0000h
008E 0000h 64K bytes 32K bytes 32K bytes 008F 0000h 008F 8000h 008F FFFFh
4-Way Cache
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Global addresses that are accessible to all masters in the system are in all memory local to the processors. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for CorePac0's L2 memory. CorePac0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the C66x CorePacs as their own L2 base addresses. For CorePac0, as mentioned, this is equivalent to 0x10800000, for CorePac1 this is equivalent to 0x11800000, and for CorePac2 this is equivalent to 0x12800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular CorePac should always use the global address only. 2.1.4 Multicore Shared Memory SRAM
The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in L1P and L1D. When configured in shared L3 mode, its contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 2.1.5 L3 Memory The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.
2.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (32KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page. Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access. The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify only whether memory pages are locally or globally accessible.
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The MSM SRAM configuration for the TCI6636K2H device is as follows: Memory size of 6144KB Can be configured as shared L2 or shared L3 memory Allows extension of external addresses from 2GB up to 8GB Has built-in memory protection features

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The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 2-1.
Table 2-1
AIDx 0 0 1 1
(1)
Available Memory Page Protection Schemes

Local Bit 0 1 0 1 Description No access to memory page is permitted. Only direct access by DSP is permitted. Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP). All accesses permitted.
Bit
End of Table 2-1

1 x = 0, 1, 2, 3, 4, 5
Faults are handled by software in an interrupt (or an exception, programmable within the CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will: Block the access reads return 0, writes are ignored Capture the initiator in a status register ID, address, and access type are stored Signal the event to the DSP interrupt controller The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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2.3 Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the bandwidth management control hardware: Level 1 Program (L1P) SRAM/Cache Level 1 Data (L1D) SRAM/Cache Level 2 (L2) SRAM/Cache Memory-mapped registers configuration bus The priority level for operations initiated within the C66x CorePac are declared through registers in the CorePac. These operations are: DSP-initiated transfers User-programmed cache coherency operations IDMA-initiated transfers The priority level for operations initiated outside the CorePac by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC). System peripherals with no fields in PRI_ALLOC have their own registers to program their priorities. More information on the bandwidth management features of the CorePac can be found in the C66x CorePac Reference Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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2.4 Power-Down Control

The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down controller (PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire CorePac. These power-down features can be used to design systems for lower overall system power requirements.
NoteThe TCI6636K2H does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the C66x CorePac Reference Guide in 1.10 Related Documentation from Texas Instruments on page 21
2.5 C66x CorePac Revision
Figure 2-5
31
CorePac Revision ID Register (MM_REVID)

16 VERSION R-n 15 REVISION R-n 0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 2-2
Bit 31-16 15-0 Name
CorePac Revision ID Register (MM_REVID) Field Descriptions

Value xxxxh 0000h Description Version of the C66x CorePac implemented on the device will depend on the silicon being used. Revision of the C66x CorePac version implemented on this device.
VERSION REVISION
End of Table 2-2
2.6 C66x CorePac Register Descriptions

See the C66x CorePac User Guide in 1.10 Related Documentation from Texas Instruments on page 21 for register offsets and definitions.
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The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Table 2-2 and described in Table 2-2. The C66x CorePac revision is dependent on the silicon revision being used.

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3 ARM CorePac
The ARM CorePac is added in the TCI6636K2H to enable the ability for layer 2 and layer 3 processing on-chip. Operations such as traffic control, local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor core. The ARM CorePac of the TCI6636K2H integrates one or more Cortex-A15 processor clusters with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order superscalar execution engine with integrated L1 caches. The implementation also supports advanced SIMDv2 (NEON technology) and VFPv4 (vector floating point) architecture extensions, security, virtualization, LPAE (large physical address extension), and multiprocessing extensions. The ARM CorePac includes a 4MB L2 cache and support for AMBA4 AXI and AXI coherence extension (ACE) protocols. An interrupt controller is included in the ARM CorePac to handle host interrupt requests in the system. The ARM CorePac has three functional clock domains, including a high-frequency clock domain used by the Cortex-A15. The high-frequency domain is isolated from the rest of the device by asynchronous bridges. Figure 3-1 shows an overall view of the Quad ARM CorePac.
Figure 3-1 KeyStone II ARM CorePac Block Diagram
4 MB L2 Cache
480 SPI Interrupts
L2 Cache Control and Snoop Control Unit
Timer 0 - 3
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KeyStone II ARM CorePac (Quad Core)

ARM
ARM INTC
Generic Interrupt Controller 400 16 PPI TeraNet (CFG) VBUSP2AXI Bridge IRQ, FIQ, VIRQ, VFIQ
ARM Cluster
STM
ATB VBUSP OCP ATB APB
ARM A15
32KB L1 P-Cache 32KB L1 D-Cache
TeraNet (DMA)
ARM Trace
APB MUX
ARM A15
APB
PTM (4) Debug CTI/CTM ARM VBUSP Registers

APB
ATB
Debug SubSystem
ARM A15
Global Time Base Counter
64 Bits
ARM A15
CTM CTI (4)
VBUSP
TeraNet (CFG)
AXI-VBUS Master
256b VBUSM
MSMC DDR3
Endian CFG Boot Config
ARM CorePac Clock Main PLL
ARM A15 Core Clock ARM PLL PSC
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3.1 Features
The key features of the Quad Core ARM CorePac are as follows: One or more Cortex-A15 processors, each containing: Cortex-A15 processor revision R2P4. ARM architecture version 7 ISA. Multi-issue, out-of-order, superscalar pipeline. L1 and L2 instruction and data cache of 32 KB, 2-way, 16 word line with 128 bit interface. Integrated L2 cache of 4MB, 16-way, 16 word line, 128-bit interface to L1 along with ECC/parity. Includes the NEON media coprocessor (NEON), which implements the advanced SIMDv2 media processing architecture and the VFPv4 Vector Floating Point architecture. The external interface uses the AXI protocol configured to 128-bit data width. Includes the System Trace Macrocell (STM) support for non-invasive debugging. Implements the ARMv7 debug with watchpoint and breakpoint registers and 32-bit advanced peripheral bus (APB) slave interface to CoreSight debug systems. Interrupt controller Supports up to 480 interrupt requests Emulation/debug Compatible with CoreSight architecture Clock generation Through the dedicated ARM PLL
3.2 System Integration

The ARM CorePac integrates the following group of submodules. Cortex-A15 Processors: Provides a high processing capability, including the NEON technology for mobile multimedia acceleration. The Cortex-A15 communicates with the rest of the ARM CorePac through an AXI bus with an AXI2VBUSM bridge and receives interrupts from the ARM CorePac interrupt controller (ARM INTC). Interrupt Controller: Handles interrupts from modules outside of the ARM CorePac (for details, see ARM Interrupt Controller). Clock Divider: Provides the required divided clocks to the internal modules of the ARM CorePac and has a clock input from the ARM PLL and the Main PLL In-Circuit Emulator: Fully compatible with CoreSight architecture and enables debugging capabilities.
ARM CorePac
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3.3 ARM Cortex-A15 Processor

3.3.1 Overview The ARM Cortex-A15 processor incorporates the technologies available in the ARM7 architecture. These technologies include NEON for media and signal processing and Jazelle RCT for acceleration of real-time compilers, Thumb-2 technology for code density, and the VFPv4 floating point architecture. For details, see the ARM Cortex-A15 Processor Technical Reference Manual. 3.3.2 Features Table 3-1 shows the features supported by the Cortex-A15 processor core.
Table 3-1
Features
Cortex-A15 Processor Core Supported Features

Description Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and media extensions Backward compatible with previous ARM ISA versions
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ARM version 7-A ISA
Cortex-A15 processor version Integer core NEON core Architecture Extensions L1 Lcache and Dcache L2 cache
R2P4 Main core for processing integer instructions Gives greatly enhanced throughput for media workloads and VFP-Lite support Security, virtualization and LPAE (40bit virtual address) extensions 32KB, 2-way, 16 word line, 128 bit interface 4096KB, 16-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported shared between cores L2 valid bits cleared by software loop or by hardware
Cache Coherency Branch target address cache Enhanced memory management unit Buses Non-invasive Debug Support Misc Debug Support Clocking Voltage Power End of Table 3-1
Support for coherent memory accesses between A15 cores and other non-core master peripherals (Ex: EDMA) in the DDR3A and MSMC SRAM space. Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return stack, and an indirect predictor Mapping sizes are 4KB, 64KB, 1MB, and 16MB 128b AXI4 internal bus from Cortex-A15 converted to a 256b VBUSM to interface (through the MSMC) with MSMC SRAM, DDR EMIF, ROM, Interrupt controller and other system peripherals Processor instruction trace using 4x Program Trace Macrocell (Coresight PTM), Data trace (print-f style debug) using System Trace Macrocell (Coresight STM) and Performance Monitoring Units (PMU) JTAG based debug and Cross triggering Dedicated ARM PLL for flexible clocking scenarios SmartReflex voltage domain for automatic voltage scaling Support for standby modes and separate core power domains for additional leakage power reduction
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3.3.3 ARM Interrupt Controller The ARM CorePac interrupt controller (AINTC) is responsible for prioritizing all service requests from the system peripherals and the Secondary interrupt controller CIC2 and then generating either nIRQ or nFIQ to the Cortex-A15 processor. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. The AINTC interfaces to the Cortex-A15 processor via the AXI port through an VBUS2AXI bridge and runs at half the processor speed. It has the capability to handle up to 480 requests, which can be steered/prioritized as A15 nFIQ or nIRQ interrupt requests. The general features of the AINTC are: Up to 480 level sensitive shared peripheral interrupts (SPI) inputs Individual priority for each interrupt input Each interrupt can be steered to nFIQ or nIRQ Independent priority sorting for nFIQ and nIRQ Secure mask flag On the chip level, there is a dedicated chip level interrupt controller to serve the ARM interrupt controller. See the Interrupt section for more details. The figure below shows an overall view of the ARM CorePac Interrupt Controller.
Figure 3-2 ARM Interrupt Controller for Four Cortex-A15 Processor Cores
FIQ, IRQ, Virtual FIQ, Virtual IRQ
ARM INTC
Peripherals 480 SPI Interrupts Generic Interrupt Controller 400
CIC2
16 PPIs
CPU/6 Clock GTB Counter Clock Power On Reset
Global Time Base Counter
64 Bits
Cortex A15
VBUSP Interface
VBUSP2AXI Bridge
16 Software Generated Inputs
3.3.4 Endianess The ARM CorePac can operate in either little endian or big endian mode. When the ARM CorePac is in little endian mode and the rest of the system is in big endian mode, the bridges in the ARM CorePac are responsible for performing the endian conversion.
3.4 CFG Connection

The ARM CorePac has two slave ports. The TCI6636K2H masters cannot access the ARM CorePac internal memory space. 1. Slave port 0 (TeraNet 3P_A) is a 32 bit wide port used for the ARM Trace module. 2. Slave port 1 (TeraNet 3P_B) is a 32 bit wide port used to access the rest of the system configuration.
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3.5 Main TeraNet Connection

There is one master port coming out of the ARM CorePac. The master port is a 256 bit wide port for the transactions going to the MSMC and DDR_EMIF data spaces.
3.6 Clocking and Reset

3.6.1 Clocking The ARM CorePac includes a dedicated embedded DPLL (ARM PLL). The Cortex-A15 processor core clocks are sourced from this ARM PLL Controller. The Cortex-A15 processor core clock has a maximum frequency of 1.4 Ghz. The ARM CorePac subsytem also uses the SYSCLK1 clock source from the main PLL is locally divided (/1, /3 and /6) and provided to certain sub-modules inside the ARM CorePac. AINTC sub module runs at a frequency of SYSCLK1/6.
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3.6.2 Reset The ARM CorePac does not support local reset. It is reset whenever the device is under reset. In addition, the interrupt controller (AINTC) can only be reset during POR and RESETFULL. For the complete programming model, refer to the KeyStone II ARM CorePac User Guide.
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4 Terminals
4.1 Package Terminals
Figure 4-1 shows the AAW ball grid array package (bottom view).
Figure 4-1 AAW 1517-PIN BGA Package (Bottom View)
4.2 Pin Map

The following figures show the pin assignments in four quadrants (A, B, C, and D).
Figure 4-2 Pin Map Panels (Bottom View)
A B C D
Terminals
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SPRS835DAugust 2013 Figure 4-3
1 AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
(nopin) VSS VSS RP1FBN RP1FBP TSRXCLKOUT0N TSRXCLKOUT0P TSREFCLKP TSREFCLKN SYSCLKOUT HYP0TXPMDAT HYP1TXPMCLK TDI TDO TCK TRST TSPUSHEVT1 TSCOMPOUT USBRESREF USBRX0M USBRX0P USBTX0M USBTX0P USBVBUS USBID0 RSV001 SCL0 TIMI1 UART0CTS UART1CTS VSS DDR3AD04 DDR3AD00 DDR3AD02 DDR3ADQS0P DDR3ADQS0N VSS VSS (nopin) www.ti.com
TCI6636K2K Pin Map Left Side Panel (A) Bottom View

2
VSS VSS VSS VSS RP1CLKP RP1CLKN VSS ALTCORECLKP ALTCORECLKN VSS HYP0RXPMCLK HYP1TXFLDAT HYP1RXFLDAT HYP1TXPMDAT TMS RESET TSPUSHEVT0 EMU01 EMU00 VSS USBCLKP USBCLKM USBDP USBDM VSS RSV000 SDA1 TIMI0 UART1RXD UART0TXD VSS DDR3AD01 DDR3AD03 DDR3AD06 DDR3AD05 DDR3AD07 DDR3ADQM0 VSS VSS
3
VSS HYP1RXN3 VSS HYP1TXN3 VSS TSRXCLKOUT1N TSRXCLKOUT1P VSS SYSCLKP SYSCLKN HYP0TXFLCLK HYP1TXFLCLK HYP0RXPMDAT HYP1RXPMCLK VSS RESETFULL TSSYNCEVT EMU14 EMU11 EMU02 EMU04 VSS EMU08 EMU09 EMU15 SDA0 SDA2 TIMO0 USBDRVVBUS UART1TXD VSS DDR3AD13 DDR3AD10 DDR3ADQM1 VSS DDR3AD14 DDR3ADQS1N DDR3ADQS1P VSS
4
HYP1CLKP HYP1RXP3 HYP1RXN2 HYP1TXP3 HYP1TXN2 VSS RSV002 RSV003 CORECLKSEL POR HYP0RXFLDAT HYP1RXFLCLK VSS HYP1RXPMDAT LRESET LRESETNMIEN EXTFRAMEEVENT EMU10 EMU18 EMU03 EMU05 EMU06 EMU07 EMU13 EMU17 SCL2 SCL1 TIMO1 UART0RTS UART0RXD VSS VSS DDR3AD16 DDR3AD09 DDR3AD08 DDR3AD15 VSS DDR3AD12 DDR3AD11
5
HYP1CLKN VSS HYP1RXP2 VSS HYP1TXP2 HYP1TXN1 VSS CVDD VSS RSV012 HYP0RXFLCLK HYP0TXPMCLK HYP0TXFLDAT BOOTCOMPLETE HOUT NMI RESETSTAT DVDD18 VSS DVDD18 VSS DVDD18 EMU12 EMU16 VSS VSS VSS UART1RTS VSS VSS VSS DDR3AD17 DDR3AD20 DDR3AD19 VSS DDR3AD18 DDR3AD22 DDR3ADQS2N DDR3ADQS2P
6
VSS HYP1RXN1 VSS HYP1TXN0 VSS HYP1TXP1 VSS HYP1REFRES CVDD VSS VSS VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS CVDD VSS CVDD VSS DVDD15 VSS DDR3AD29 DDR3AD26 DDR3ADQM3 DDR3AD21 VSS DDR3AD23 DDR3ADQM2
7
HYP0RXN3 HYP1RXP1 HYP1RXN0 HYP1TXP0 HYP0TXN3 VSS VSS RSV020 VSS CVDD VSS VSS VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 DDR3AD30 DDR3AD25 VSS DDR3AD31 DDR3AD24 DDR3ADQS3P DDR3ADQS3N
8
HYP0RXP3 VSS HYP1RXP0 VSS HYP0TXP3 HYP0TXN2 VSS VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 VSS DDR3AA02 DDR3AA05 DDR3AA00 DDR3AA09 VSS DDR3AD28 DDR3AD27
9
VSS HYP0RXN2 VSS HYP0CLKP VSS HYP0TXP2 VSS HYP0REFRES VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 DDR3AA01 DDR3AA04 VSS DDR3AA07 DDR3AA06 DDR3AA08 DDR3AA11
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HYP0RXN0 HYP0RXP2 HYP0RXN1 HYP0CLKN HYP0TXN1 VSS RSV019 VSS VDDAHV VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 DDR3ARQ1 DDR3AA03 DDR3AA10 DDR3AA12 DDR3AA15 VSS DDR3AA14 DDR3AA13
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SPRS835DAugust 2013 TCI6636K2K Pin Map Left Center Panel (B) Bottom View
11 12
VSS AIFRXN5 VSS AIFTXN5 VSS HYP0TXP0 VSS VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS VP VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 VSS DDR3ACKE0 DDR3AWE DDR3AODT0 RSV027 VSS
Figure 4-4
AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
HYP0RXP0 VSS HYP0RXP1 VSS HYP0TXP1 HYP0TXN0 VSS AIFREFRES1 VSS VDDAHV VSS VDDALV VSS AVDDA1 VSS VNWA2 VSS CVDD VSS VPTX VSS VNWA4 VSS CVDD VSS AVDDA6 VSS DVDD15 VSS DVDD15 VSS DVDD15 DDR3ABA2 DDR3ACE1 VSS DDR3ACE0 DDR3ABA1 DDR3ABA0 DDR3ACKE1
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AIFRXN3 AIFRXP5 AIFRXN4 AIFTXP5 AIFTXN4 VSS VSS VSS VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS VDDUSB VSS VPH VSS CVDD1 VSS CVDD1 VSS CVDD VSS AVDDA7 VSS DVDD15 VSS DVDD15 DDR3AODT1 RSV029 VSS RSV028 DDR3ACAS
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AIFRXP3 VSS AIFRXP4 VSS AIFTXP4 AIFTXN3 VSS RSV025 VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS DVDD33 VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 VSS DDR3AVREFSSTL DDR3ACB05 DDR3ADQM8 DDR3ACB06 VSS DDR3ARESET DDR3ARAS
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VSS AIFRXN2 VSS AIFTXN2 VSS AIFTXP3 VSS AIFREFRES0 VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS AVDDA8 VSS DVDD15 VSS DVDD15 DDR3ACB07 DDR3ACB03 VSS DDR3ACB04 DDR3ACB01 DDR3ADQS8P DDR3ADQS8N
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AIFRXN0 AIFRXP2 AIFRXN1 AIFTXP2 AIFTXN1 VSS RSV068 RSV024 VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 DDR3ARQ0 DDR3AD33 DDR3AD34 DDR3AD32 DDR3AD36 VSS DDR3ACB02 DDR3ACB00
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AIFRXP0 VSS AIFRXP1 VSS AIFTXP1 AIFTXN0 VSS VSS VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 VSS DVDD15 DDR3AD35 DDR3AD38 VSS DDR3AD37 DDR3ADQM4 DDR3ADQS4N DDR3ADQS4P
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VSS RSV061 VSS RSV063 VSS AIFTXP0 VSS VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA9 DVDD15 VSS DVDD15 VSS DDR3AD42 DDR3AD47 DDR3AD39 DDR3AD46 VSS DDR3AD45 DDR3ADQM5
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RSV065 RSV060 RSV070 RSV062 RSV067 VSS RSV026 RSV069 VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 VSS DVDD15 DDR3AD44 DDR3AD43 VSS DDR3AD41 DDR3AD40 DDR3ADQS5P DDR3ADQS5N
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RSV064 VSS RSV071 VSS RSV066 VSS VSS VSS VDDAHV
VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS AVDDA2 AVDDA10 DVDD15 VSS DVDD15 VSS DDR3AD51 DDR3AD54 DDR3AD53 DDR3AD50 VSS DDR3AD49 DDR3AD48
DDR3ACLKOUTN0 DDR3ACLKOUTN1 DDR3ACLKOUTP0 DDR3ACLKOUTP1
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VSS

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VSS RIORXN3 VSS RIOTXN3 VSS VSS VSS RIOREFRES VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS VPP VSS DVDD15 VSS DVDD15 DDR3AD55 DDR3AD62 VSS DDR3ADQM6 DDR3AD52 DDR3ADQS6N DDR3ADQS6P www.ti.com
TCI6636K2K Pin Map Right Center Panel (C) Bottom View

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RIORXN2 RIORXP3 RIORXN1 RIOTXP3 VSS RIOTXN2 VSS VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDDT1 VSS CVDDT1 VSS CVDDT1 VSS CVDD VSS VPP VSS DVDD15 DDR3ARQ2 DDR3AD57 DDR3AD59 DDR3AD60 DDR3AD63 VSS DDR3AD61 DDR3ADQM7
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RIORXP2 VSS RIORXP1 VSS RIOTXN1 RIOTXP2 VSS RSV021 VSS VDDAHV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDDT VSS CVDDT VSS CVDDT VSS VNWA3 VSS DVDD15 VSS DVDD15 VSS RSV013 RSV014 DDR3AD58 DDR3AD56 DDR3ADQS7N DDR3ADQS7P
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VSS RIORXN0 VSS RIOTXN0 RIOTXP1 VSS VSS SGMIIREFRES VDDAHV VSS VDDALV VSS VNWA1 VSS CVDD VSS CVDD VSS CVDD VSS CVDDT VSS CVDDT VSS CVDDT VSS CVDDT VSS DVDD18 VSS VSS VSS CORESEL3 CORESEL0 CORESEL1 CORESEL2 VSS RSV004 RSV005
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SGMII3RXN RIORXP0 SGMII2RXN RIOTXP0 VSS SGMII3TXN VSS RSV023 VSS VDDAHV VSS VDDALV VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDDT VSS CVDDT VSS CVDDT VSS CVDD VSS DVDD18 VSS DVDD18 VSS SPI0SCS0 SPI2SCS3 SPI2CLK SPI0SCS1 DDR3ACLKP DDR3ACLKN
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SGMII3RXP VSS SGMII2RXP VSS SGMII2TXN SGMII3TXP VSS PCIEREFRES DVDD18 VSS DVDD18 VSS AVDDA5 VSS CVDD VSS CVDD VSS CVDD VSS CVDDT VSS CVDDT VSS CVDDT VSS CVDDT VSS DVDD18 VSS DVDD18 VSS RSV018 RSV017 SPI0SCS2 SPI0SCS3 VSS SPI0CLK SPI0DIN
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VSS SGMII1RXN VSS SGMII1TXN SGMII2TXP VSS VSS DVDD18 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDDT VSS DVDD18 VSS DVDD18 VSS SPI1DIN SPI1SCS3 SPI1SCS2 SPI1SCS1 SPI1SCS0 SPI0DOUT
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SGMII0RXN SGMII1RXP SGMII0TXN SGMII1TXP VSS VSS VSS RSV022 DVDD18 VSS CVDD VSS CVDD VSS AVDDA15 AVDDA14 AVDDA13 AVDDA12 DVDD15 AVDDA11 DVDD15 VSS DVDD15 VSS DVDD15 VSS AVDDA3 VSS CVDDT VSS DVDD18 VSS SPI2DOUT SPI2DIN VSS SPI2SCS1 SPI1CLK SPI2SCS0 SPI1DOUT
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SGMII0RXP VSS SGMII0TXP VSS PCIETXN1 VSS VSS DVDD18 VSS CVDD VSS AVDDA4 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD18 VSS CVDDT VSS VSS VSS GPIO00 GPIO05 GPIO02 VSS GPIO04 SPI2SCS2
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VSS PCIERXN1 VSS PCIETXN0 PCIETXP1 VSS PACLKSEL RADSYNC CVDD VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD18 VSS DVDD18 VSS CVDDT VSS GPIO09 GPIO12 GPIO11 GPIO06 GPIO07 GPIO01 GPIO08
AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
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SPRS835DAugust 2013 TCI6636K2K Pin Map Right Side Panel (D) Bottom View
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PCIECLKN VSS PCIERXP0 VSS MDIO USIMRST USIMCLK VSS DVDD15 DDR3BRQ2 VSS DDR3BD40 DDR3BD39 DDR3BCB00 DDR3BCB02 DDR3BRAS DDR3BRESET RSV032 DDR3BA00 DDR3BA09 DDR3BA02 DDR3BD30 DDR3BDQM3 DDR3BD08 DDR3BD09 DDR3BRQ1 DDR3BD13 EMIFD00 DVDD15 VSS DVDD18 VSS EMIFCE1 RSV016 GPIO14 GPIO27 VSS GPIO19 GPIO17
Figure 4-6
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PCIECLKP PCIERXP1 PCIERXN0 PCIETXP0 VSS MDCLK VSS CVDD VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 DDR3BVREFSSTL DVDD15 DDR3BRQ0 DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD18 VSS CVDDT VSS GPIO10 GPIO25 GPIO22 GPIO18 GPIO15 GPIO13
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VSS PASSCLKP VSS RSV072 VSS USIMIO DDR3BD58 VSS DDR3BD55 VSS DDR3BD41 VSS DDR3BDQM4 VSS DDR3BCB04 VSS DDR3BODT0 VSS DDR3BA08 VSS DDR3BA01 VSS DDR3BD29 VSS DDR3BD14 VSS DDR3BD04 VSS EMIFD02 EMIFA07 VSS EMIFBE1 EMIFCE0 EMIFRNW RSV015 GPIO21 GPIO28 GPIO24 GPIO20
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SRIOSGMIICLKP PASSCLKN RSV008 RSV009 RSV073 PHYSYNC DDR3BD56 DDR3BD59 DDR3BD52 DDR3BDQM6 DDR3BD43 DDR3BD37 DDR3BD35 DDR3BCB01 DDR3BCB07 DDR3BODT1 RSV031 DDR3BCE0 DDR3BBA1 DDR3BA03 DDR3BA04 DDR3BA05 DDR3BD26 DDR3BD16 DDR3BD17 DDR3BDQM1 DDR3BD01 EMIFD13 EMIFD03 EMIFA16 EMIFA05 EMIFBE0 EMIFCE2 EMIFA00 EMIFA04 VSS GPIO29 GPIO31 GPIO26
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SRIOSGMIICLKN VSS VCNTL4T VDT VCNTL5 VD VSS DDR3BD60 VSS DDR3BD51 VSS DDR3BD38 VSS DDR3BCB03 VSS RSV030 VSS DDR3BBA2 VSS DDR3BA12 VSS DDR3BD24 VSS DDR3BD18 VSS DDR3BD10 VSS EMIFD15 EMIFD12 VSS EMIFA18 EMIFA06 VSS EMIFA17 EMIFA13 EMIFA11 EMIFA08 GPIO23 GPIO03
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VCNTL5T VCNTL3T VCNTL0T VSS VCNTL2 VCL DDR3BD57 DDR3BD62 DDR3BD53 DDR3BD50 DDR3BD44 DDR3BD42 DDR3BD36 DDR3BD33 DDR3BCB05 DDR3BCB06 DDR3BCAS VSS DDR3BCE1 DDR3BA15 DDR3BA06 DDR3BD31 DDR3BD25 DDR3BD22 DDR3BD20 DDR3BD15 DDR3BD06 EMIFD14 EMIFD11 EMIFD10 EMIFA21 EMIFA12 EMIFA02 EMIFWE EMIFCE3 EMIFA23 EMIFA20 GPIO30 GPIO16
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VSS VCNTL1T VCNTL2T VCLT VCNTL1 VSS DDR3BD63 VSS DDR3BD54 VSS DDR3BD47 VSS DDR3BD32 VSS DDR3BDQM8 VSS DDR3BWE VSS DDR3BBA0 VSS DDR3BA07 VSS DDR3BD21 VSS DDR3BD19 VSS DDR3BD05 DDR3BD02 VSS EMIFD06 EMIFD01 VSS EMIFA09 EMIFA01 EMIFOE VSS ARMCLKP ARMCLKN VSS
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VSS VSS VCNTL4 VCNTL3 DDR3BCLKP RSV006 DDR3BDQS7P DDR3BD61 DDR3BDQS6N DDR3BD49 DDR3BDQS5N DDR3BD46 DDR3BD34 DDR3BDQS4P DDR3BDQS8N DDR3BCLKOUTP0 DDR3BCLKOUTN1 DDR3BCKE1 DDR3BA14 DDR3BA10 DDR3BD27 DDR3BDQS3N DDR3BD23 DDR3BDQS2N DDR3BD12 DDR3BDQS1N DDR3BD07 DDR3BDQS0P DDR3BD00 EMIFD09 EMIFD05 EMIFA22 EMIFA14 EMIFA10 EMIFWAIT0 RSV011 RSV010 VSS VSS
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(nopin) VSS VSS VCNTL0 DDR3BCLKN RSV007 DDR3BDQS7N DDR3BDQM7 DDR3BDQS6P DDR3BD48 DDR3BDQS5P DDR3BD45 DDR3BDQM5 DDR3BDQS4N DDR3BDQS8P DDR3BCLKOUTN0 DDR3BCLKOUTP1 DDR3BCKE0 DDR3BA11 DDR3BA13 DDR3BD28 DDR3BDQS3P DDR3BDQM2 DDR3BDQS2P DDR3BD11 DDR3BDQS1P DDR3BDQM0 DDR3BDQS0N DDR3BD03 EMIFD08 EMIFD07 EMIFD04 EMIFA19 EMIFA15 EMIFA03 EMIFWAIT1 VSS VSS (nopin)
AW AV AU AT AR AP AN AM AL
AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
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AK

SPRS835DAugust 2013
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4.3 Terminal Functions

The terminal functions table (Table 4-2) identifies the external signal names, the associated pin (ball) numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin descriptions. This table is arranged by function. The power terminal functions table (Table 4-3) lists the various power supply pins and ground pins and gives functional pin descriptions. Table 4-4 shows all pins arranged by signal name. Table 4-5 shows all pins arranged by ball number. There are 30 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (). For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see section 7.2 Device Configuration on page 235 and section 4.4 Pullup/Pulldown Resistors on page 82. Use the symbol definitions in Table 4-1 when reading Table 4-2.
Table 4-1
Functional Symbol
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I/O Functional Symbol Definitions

Definition Internal 100-A pulldown or pullup is provided for this terminal. In most systems, a 1-k resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see the Hardware Design Guide for KeyStone Devices in 1.10 Related Documentation from Texas Instruments on page 21. Analog signal Ground Input terminal Output terminal Supply voltage Three-state terminal or high impedance Table 4-2 Column Heading
IPD or IPU
IPD/IPU
A GND I O S Z End of Table 4-1
Type Type Type Type Type Type
Table 4-2
Signal Name
Terminal Functions Signals and Control by Function (Part 1 of 19)

Ball No. Type IPD/IPU Description AIF
AIFRXN0 AIFRXP0 AIFRXN1 AIFRXP1 AIFRXN2 AIFRXP2 AIFRXN3 AIFRXP3 AIFRXN4 AIFRXP4 AIFRXN5 AIFRXP5
AW16 AW17 AU16 AU17 AV15 AV16 AW13 AW14 AU13 AU14 AV12 AV13
I I I I I I I I I I I I Antenna Interface receive data (6 links)
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SPRS835DAugust 2013 Terminal Functions Signals and Control by Function (Part 2 of 19)
Ball No. AP17 AP18 AR16 AR17 AT15 AT16 AP14 AP15 AR13 AR14 AT12 AT13 AM15 AM11 Type O O O O O O O O O Antenna Interface transmit data (6 links) IPD/IPU Description
Table 4-2
Signal Name AIFTXN0 AIFTXP0 AIFTXN1 AIFTXP1 AIFTXN2 AIFTXP2 AIFTXN3 AIFTXP3 AIFTXN4 AIFTXP4 AIFTXN5 AIFTXP5 AIFREFRES0 AIFREFRES1
O O A A Antenna SERDES0 reference resistor input (3 k +/- 1%) Antenna SERDES1 reference resistor input (3 k +/- 1%) Antenna Timer Down Down Down Frame sync clock output Alternate frame sync clock input (vs. FSYNCCLK(N|P) Alternate frame sync input (vs. FRAMBURST (N|P) Frame sync interface clock used to drive the frame synchronization interface (OBSAI RP1 clock)
EXTFRAMEEVENT PHYSYNC RADSYNC RP1CLKN RP1CLKP RP1FBN RP1FBP
AC4 AP34 AM30 AP2 AR2 AT1 AR1
OZ I I I I I I
Frame burst to drive frame indicators to the frame synchronization module (OBSAI RP1) Boot Configuration Pins
ARM_LENDIAN ARMAVSSHARED AVSIFSEL0 AVSIFSEL1 BOOTMODE00 BOOTMODE01 BOOTMODE02 BOOTMODE03 BOOTMODE04 BOOTMODE05 BOOTMODE06 BOOTMODE07 BOOTMODE08 BOOTMODE09 BOOTMODE10 BOOTMODE11 BOOTMODE12 BOOTMODE13 BOOTMODE14 BOOTMODE15
B31 G24 M2 M1 B30 D29 A35 B29 E29 D30 C30 A30 G30 F31 E30 F30 A31 F24 E24 D24
I I I I I I I I I I I I I I I I I I I I
Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down
ARM little endian configuration pin. Pin shared with GPIO15. Boot strapped pin to share ARM AVS with SoC. Pin shared with CORESEL3. Default value (Boot Strapped) for SR PINMUX register (SR_PINCTL). Pins shared with TIMI0 and TIMI1.
User defined Boot Mode pins See 7.1.2 Boot Modes Supported on page 211 for more details. ( Pins are secondary functions and are shared with GPIO[01:13])
User defined Boot Mode pins See 7.1.2 Boot Modes Supported on page 211 for more details. ( Pins are secondary functions and are shared with CORESEL[0:2])
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SPRS835DAugust 2013 Table 4-2
Signal Name BOOTCOMPLETE DDR3A_REMAP_EN LENDIAN MAINPLLODSEL
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Ball No. AF5 A36 F29 E32 Type OZ I I I IPD/IPU Down Down Up Down Description Boot progress indication output Control ARM remapping of DDR3A address space in the lower 4 GB (32b space) Mode select. Secondary function. Pin shared with GPIO16. Little endian configuration pin. Pin shared with GPIO00 Main PLL Output divider select. Pin shared with GPIO14. Clock / Reset
ALTCORECLKN ALTCORECLKP ARMCLKN ARMCLKP
AL2 AM2 B37 C37 AL4 F24 E24 D24 G24 A25 B25 AR39 AR38 AE5 AT10 AT9 AW5 AW4 AE4 AD4 AD5 AN30 AV34 AV33 AW32 AW31 AK4 AD3 AD2 AC5 AW35 AW34 AK3 AL3 AK1 AL1 AM1
I I I I I I I I I I I I I OZ I I I I I I I I I I I I I I I O I I I I OZ I I Down Up Up Up Up Up Up Down Up Down Down Down Down Down
Alternate clock input to Main PLL
Reference clock to drive ARM CorePac PLL Core clock select to select between SYSCLK(N|P) and ALTCORECCLK to the main PLL
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CORECLKSEL CORESEL0 CORESEL1 CORESEL2 CORESEL3 DDR3ACLKN DDR3ACLKP DDR3BCLKN DDR3BCLKP HOUT HYP0CLKN HYP0CLKP HYP1CLKN HYP1CLKP LRESET LRESETNMIEN NMI PACLKSEL PASSCLKN PASSCLKP PCIECLKN PCIECLKP POR RESETFULL RESET RESETSTAT SRIOSGMIICLKN SRIOSGMIICLKP SYSCLKN SYSCLKP SYSCLKOUT TSREFCLKN TSREFCLKP
Select for the target core for LRESET and NMI
DDR3A reference clock input to DDR PLL
DDR3B reference clock input to DDR PLL Interrupt output pulse created by IPCGRH HyperLink reference clock to drive HyperLink0 SerDes
HyperLink reference clock to drive HyperLink1 SerDes Warm reset Enable for core selects Non-maskable interrupt PA clock select to choose between core clock and PASSCLK pins Packet Accelerator subsystem reference clock
PCIe clock input to drive PCIe SerDes Power-on reset Full reset Warm reset of non isolated portion of the device Reset status output RapidIO/SGMII reference clock to drive the RapidIO and SGMII SerDes
System clock input to antenna interface and Main PLL (Main PLL optional vs. ALTCORECLK) System clock output to be used as a general purpose output clock for debug purposes External precision clock source for SyncE
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Ball No. AP1 AN1 AP3 AN3 Type O O O O IPD/IPU Description SerDes recovered clock output for SyncE.
Table 4-2
Signal Name TSRXCLKOUT0N TSRXCLKOUT0P TSRXCLKOUT1N TSRXCLKOUT1P
SerDes recovered clock output for SyncE. DDR3A
DDR3ADQM0 DDR3ADQM1 DDR3ADQM2 DDR3ADQM3 DDR3ADQM4 DDR3ADQM5 DDR3ADQM6 DDR3ADQM7 DDR3ADQM8 DDR3ADQS0P DDR3ADQS0N DDR3ADQS1P DDR3ADQS1N DDR3ADQS2P DDR3ADQS2N DDR3ADQS3P DDR3ADQS3N DDR3ADQS4P DDR3ADQS4N DDR3ADQS5P DDR3ADQS5N DDR3ADQS6P DDR3ADQS6N DDR3ADQS7P DDR3ADQS7N DDR3ADQS8P DDR3ADQS8N DDR3ACB00 DDR3ACB01 DDR3ACB02 DDR3ACB03 DDR3ACB04 DDR3ACB05 DDR3ACB06 DDR3ACB07
C2 F3 A6 E6 C17 A18 D21 A22 E14 E1 D1 B3 C3 A5 B5 B7 A7 A17 B17 B19 A19 A21 B21 A23 B23 B15 A15 A16 C15 B16 F15 D15 F14 D14 G15
OZ OZ OZ OZ
OZ OZ OZ OZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ DDR3A EMIF check bits DDR3A EMIF data strobe
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OZ
DDR3A EMIF data masks

Signal Name DDR3AD00 DDR3AD01 DDR3AD02 DDR3AD03 DDR3AD04 DDR3AD05 DDR3AD06 DDR3AD07 DDR3AD08 DDR3AD09 DDR3AD10 DDR3AD11 DDR3AD12 DDR3AD13 DDR3AD14 DDR3AD15 DDR3AD16 DDR3AD17 DDR3AD18 DDR3AD19 DDR3AD20 DDR3AD21 DDR3AD22 DDR3AD23 DDR3AD24 DDR3AD25 DDR3AD26 DDR3AD27 DDR3AD28 DDR3AD29 DDR3AD30 DDR3AD31
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Ball No. G1 H2 F1 G2 H1 E2 F2 D2 E4 F4 G3 A4 B4 H3 D3 D4 G4 H5 D5 F5 G5 D6 C5 B6 C7 F7 F6 A8 B8 G6 G7 D7 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ DDR3A EMIF data bus DDR3A EMIF data bus IPD/IPU Description
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Ball No. E16 G16 F16 G17 D16 D17 F17 E18 C19 D19 G18 F19 G19 B18 D18 F18 A20 B20 D20 G20 C21 E20 F20 G21 C23 G22 D23 F22 E22 B22 F21 D22 D11 F11 B11 C11 G11 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ OZ OZ OZ OZ OZ DDR3A EMIF bank address DDR3A EMIF chip enable DDR3A EMIF chip enable DDR3A EMIF data bus DDR3A EMIF data bus IPD/IPU Description
Table 4-2
Signal Name DDR3AD32 DDR3AD33 DDR3AD34 DDR3AD35 DDR3AD36 DDR3AD37 DDR3AD38 DDR3AD39 DDR3AD40 DDR3AD41 DDR3AD42 DDR3AD43 DDR3AD44 DDR3AD45 DDR3AD46 DDR3AD47 DDR3AD48 DDR3AD49 DDR3AD50 DDR3AD51 DDR3AD52 DDR3AD53 DDR3AD54 DDR3AD55 DDR3AD56 DDR3AD57 DDR3AD58 DDR3AD59 DDR3AD60 DDR3AD61 DDR3AD62 DDR3AD63 DDR3ACE0 DDR3ACE1 DDR3ABA0 DDR3ABA1 DDR3ABA2
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Signal Name DDR3AA00 DDR3AA01 DDR3AA02 DDR3AA03 DDR3AA04 DDR3AA05 DDR3AA06 DDR3AA07 DDR3AA08 DDR3AA09 DDR3AA10 DDR3AA11 DDR3AA12 DDR3AA13 DDR3AA14 DDR3AA15 DDR3ACAS DDR3ARAS DDR3AWE DDR3ACKE0 DDR3ACKE1 DDR3ACLKOUTP0 DDR3ACLKOUTN0 DDR3ACLKOUTP1 DDR3ACLKOUTN1 DDR3AODT0 DDR3AODT1 DDR3ARESET DDR3ARZQ0 DDR3ARZQ1 DDR3ARZQ2
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Ball No. E8 G9 G8 G10 F9 F8 C9 D9 B9 D8 F10 A9 E10 A10 B10 D10 C13 A14 F12 G12 A11 A12 B12 A13 B13 E12 G13 B14 H16 H10 H22 Type OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ A A A DDR3A EMIF column address strobe DDR3A EMIF row address strobe DDR3A EMIF write enable DDR3A EMIF clock enable0 DDR3A EMIF clock enable1 DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM) for Rank0 DDR3A EMIF address bus IPD/IPU Description
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DDR3A EMIF output clocks to drive SDRAMs (one clock pair per SDRAM) for Rank1 DDR3A EMIF on die termination outputs used to set termination on the SDRAMs for Rank0 DDR3A EMIF on die termination outputs used to set termination on the SDRAMs for Rank1 DDR3A reset signal PTV compensation pin for DDR3A PTV compensation pin for DDR3A PTV compensation pin for DDR3A DDR3B
DDR3BDQM0 DDR3BDQM1 DDR3BDQM2 DDR3BDQM3 DDR3BDQM4 DDR3BDQM5 DDR3BDQM6 DDR3BDQM7 DDR3BDQM8
N39 P34 U39 U32 AG33 AG39 AK34 AM39 AE37
OZ OZ OZ OZ OZ OZ OZ OZ OZ DDR3B EMIF data masks
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Ball No. M38 M39 P39 P38 T39 T38 V39 V38 AF38 AF39 AJ39 AJ38 AL39 AL38 AN38 AN39 AE39 AE38 AF32 AF34 AE32 AF35 AE33 AE36 AD36 AE34 L38 N34 M37 L39 N33 N37 N36 N38 T32 R32 P35 R39 R38 N32 R33 P36 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ DDR3B EMIF data bus DDR3B EMIF check bits DDR3B EMIF data strobe IPD/IPU Description
Table 4-2
Signal Name DDR3BDQS0P DDR3BDQS0N DDR3BDQS1P DDR3BDQS1N DDR3BDQS2P DDR3BDQS2N DDR3BDQS3P DDR3BDQS3N DDR3BDQS4P DDR3BDQS4N DDR3BDQS5P DDR3BDQS5N DDR3BDQS6P DDR3BDQS6N DDR3BDQS7P DDR3BDQS7N DDR3BDQS8P DDR3BDQS8N DDR3BCB00 DDR3BCB01 DDR3BCB02 DDR3BCB03 DDR3BCB04 DDR3BCB05 DDR3BCB06 DDR3BCB07 DDR3BD00 DDR3BD01 DDR3BD02 DDR3BD03 DDR3BD04 DDR3BD05 DDR3BD06 DDR3BD07 DDR3BD08 DDR3BD09 DDR3BD10 DDR3BD11 DDR3BD12 DDR3BD13 DDR3BD14 DDR3BD15
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Signal Name DDR3BD16 DDR3BD17 DDR3BD18 DDR3BD19 DDR3BD20 DDR3BD21 DDR3BD22 DDR3BD23 DDR3BD24 DDR3BD25 DDR3BD26 DDR3BD27 DDR3BD28 DDR3BD29 DDR3BD30 DDR3BD31 DDR3BD32 DDR3BD33 DDR3BD34 DDR3BD35 DDR3BD36 DDR3BD37 DDR3BD38 DDR3BD39 DDR3BD40 DDR3BD41 DDR3BD42 DDR3BD43 DDR3BD44 DDR3BD45
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Ball No. T34 R34 T35 R37 R36 U37 T36 U38 V35 U36 U34 W38 W39 U33 V32 V36 AG37 AF36 AG38 AG34 AG36 AH34 AH35 AG32 AH32 AJ33 AH36 AJ34 AJ36 AH39 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ DDR3B EMIF data bus DDR3B EMIF data bus IPD/IPU Description
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Ball No. AH38 AJ37 AK39 AK38 AK36 AK35 AL34 AL36 AL37 AL33 AN34 AN36 AN33 AM34 AM35 AM38 AM36 AN37 AB34 AA36 AA37 AA34 AB35 AA32 W33 W32 Y34 W34 V34 W36 W37 AA33 Y32 Y38 AA39 Y35 Y39 AA38 Y36 AC36 AD32 AC37 AB39 AB38 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ DDR3B EMIF column address strobe DDR3B EMIF row address strobe DDR3B EMIF write enable DDR3B EMIF clock enable0 DDR3B EMIF clock enable1 DDR3B EMIF address bus DDR3B EMIF bank address DDR3B EMIF chip enable DDR3B EMIF chip enable DDR3B EMIF data bus IPD/IPU Description
Table 4-2
Signal Name DDR3BD46 DDR3BD47 DDR3BD48 DDR3BD49 DDR3BD50 DDR3BD51 DDR3BD52 DDR3BD53 DDR3BD54 DDR3BD55 DDR3BD56 DDR3BD57 DDR3BD58 DDR3BD59 DDR3BD60 DDR3BD61 DDR3BD62 DDR3BD63 DDR3BCE0 DDR3BCE1 DDR3BBA0 DDR3BBA1 DDR3BBA2 DDR3BA00 DDR3BA01 DDR3BA02 DDR3BA03 DDR3BA04 DDR3BA05 DDR3BA06 DDR3BA07 DDR3BA08 DDR3BA09 DDR3BA10 DDR3BA11 DDR3BA12 DDR3BA13 DDR3BA14 DDR3BA15 DDR3BCAS DDR3BRAS DDR3BWE DDR3BCKE0 DDR3BCKE1
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Signal Name DDR3BCLKOUTP0 DDR3BCLKOUTN0 DDR3BCLKOUTP1 DDR3BCLKOUTN1 DDR3BODT0 DDR3BODT1 DDR3BRESET DDR3BRZQ0 DDR3BRZQ1 DDR3BRZQ2
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Ball No. AD38 AD39 AC39 AC38 AC33 AD34 AC32 AA31 P32 AK32 Type OZ OZ OZ OZ OZ OZ OZ A A A IPD/IPU Description DDR3B EMIF output clocks to drive SDRAM (one clock pair for Rank0)
DDR3B EMIF output clocks to drive SDRAM (one clock pair for Rank1) DDR3B EMIF on-die termination outputs used to set termination on the SDRAMs DDR3B EMIF on-die termination outputs used to set termination on the SDRAMs DDR3B reset signal PTV compensation pin for DDR3B PTV compensation pin for DDR3B PTV compensation pin for DDR3B EMIF16
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EMIFBE0 EMIFBE1 EMIFCE0 EMIFCE1 EMIFCE2 EMIFCE3 EMIFOE EMIFRW EMIFWAIT0 EMIFWAIT1 EMIFWE EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14 EMIFA15
H34 H33 G33 G32 G34 E36 E37 F33 E38 D39 F36 F34 F37 G36 E39 E34 J34 H35 K33 C35 G37 F38 D35 H36 E35 G38 F39
O O O O O O O O I I O O O O O O O O O O O O O O O O O
Up Up Up Up Up Up Up Up Down Down Up Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down EMIF address EMIF control signals
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Ball No. K34 F35 J35 G39 C36 J36 H38 D36 M32 J37 L33 L34 H39 J38 K37 J39 K39 K38 K36 L36 L35 M34 M36 M35 Type O O O O O O O O IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IPD/IPU Down Down Down Down Down Down Down Down Down EMIF address Description
Table 4-2
Signal Name EMIFA16 EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 EMIFD00 EMIFD01 EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD06 EMIFD07 EMIFD08 EMIFD09 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15
Down Down Down Down Down Down Down Down Down Down Down Down Down Down EMU EMIF data
EMU00 EMU01 EMU02 EMU03 EMU04 EMU05 EMU06 EMU07 EMU08 EMU09 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18
AA2 AB2 Y3 Y4 W3 W4 V4 U4 U3 T3 AB4 AA3 U5 T4 AB3 R3 T5 R4 AA4
IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ
Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up Up Emulation and trace port
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Down

Signal Name EMU19 EMU20 EMU21 EMU22 EMU23 EMU24 EMU25 EMU26 EMU27
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Ball No. A32 C31 B32 A33 D33 D31 B35 B33 E31 A34 D32 C33 C34 B36 B34 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IPD/IPU Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down General Purpose Input/Output (GPIO) Emulation and trace port ( Pins shared with GPIO[17:31]) Description
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EMU28 EMU29 EMU30 EMU31 EMU32 EMU33
GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15
F29 B30 D29 A35 B29 E29 D30 C30 A30 G30 F31 E30 F30 A31 E32 B31
IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ
Up Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down GPIO
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Ball No. A36 A32 C31 B32 A33 D33 D31 B35 B33 E31 A34 D32 C33 C34 B36 B34 Type IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IOZ IPD/IPU Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down Down HyperLink0 GPIO Description
Table 4-2
Signal Name GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31
HYP0RXN0 HYP0RXP0 HYP0RXN1 HYP0RXP1 HYP0RXN2 HYP0RXP2 HYP0RXN3 HYP0RXP3 HYP0TXN0 HYP0TXP0 HYP0TXN1 HYP0TXP1 HYP0TXN2 HYP0TXP2 HYP0TXN3 HYP0TXP3 HYP0RXFLCLK HYP0RXFLDAT HYP0TXFLCLK HYP0TXFLDAT HYP0RXPMCLK HYP0RXPMDAT HYP0TXPMCLK HYP0TXPMDAT HYP0REFRES
AW10 AW11 AU10 AU11 AV9 AV10 AW7 AW8 AP11 AP12 AR10 AR11 AP8 AP9 AR7 AR8 AJ5 AJ4 AJ3 AG5 AJ2 AG3 AH5 AJ1 AM9
I I I I I I I I O O O O O O O O O O I I I I O O A Down Down Down Down Down Down Down Down HyperLink0 SerDes reference resistor input (3 k +/- 1%) HyperLink0 sideband signals HyperLink0 transmit data HyperLink0 receive data
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Signal Name
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Ball No. Type IPD/IPU Description HyperLink1
HYP1RXN0 HYP1RXP0 HYP1RXN1 HYP1RXP1 HYP1RXN2 HYP1RXP2 HYP1RXN3 HYP1RXP3 HYP1TXN0 HYP1TXP0 HYP1TXN1 HYP1TXP1 HYP1TXN2 HYP1TXP2 HYP1TXN3 HYP1TXP3 HYP1RXFLCLK HYP1RXFLDAT HYP1TXFLCLK HYP1TXFLDAT HYP1RXPMCLK HYP1RXPMDAT HYP1TXPMCLK HYP1TXPMDAT HYP1REFRES
AU7 AU8 AV6 AV7 AU4 AU5 AV3 AV4 AT6 AT7 AP5 AP6 AR4 AR5 AT3 AT4 AH4 AG2 AH3 AH2 AF3 AF4 AH1 AF2 AM6
I I I I I I I I O O O O O O O O O O I I I I O O A Down Down Down Down Down Down Down Down HyperLink1 SerDes reference resistor input (3 k +/- 1%) I C
2
HyperLink1 receive data
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HyperLink1 transmit data
HyperLink1 sideband signals
SCL0 SCL1 SCL2 SDA0 SDA1 SDA2
N1 N4 P4 P3 N2 N3
IOZ IOZ IOZ IOZ IOZ IOZ
I C0 clock I2C1 clock I C2 clock I C0 data I2C1 data I C2 data JTAG

2 2 2
TCK TDI TDO TMS TRST
AE1 AG1 AF1 AE2 AD1
I I OZ I I
Up Up Up Up Down
JTAG clock input JTAG data input JTAG data output JTAG test mode input JTAG reset MDIO
MDCLK MDIO
AP31 AR32
O IOZ
Down Up
MDIO clock MDIO data
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Ball No. Type IPD/IPU Description PCIe
Table 4-2
Signal Name
PCIERXN0 PCIERXP0 PCIERXN1 PCIERXP1 PCIETXN0 PCIETXP0 PCIETXN1 PCIETXP1 PCIEREFRES
AU31 AU32 AV30 AV31 AT30 AT31 AR29 AR30 AM26
I I I I O O O O A
PCIexpress lane 0 receive data
PCIexpress lane 1 receive data
PCIexpress lane 0 transmit data
PCIexpress lane 1 transmit data PCIexpress SerDes reference resistor input (3 k +/- 1%) Serial RapidIO
RIORXN0 RIORXP0 RIORXN1 RIORXP1 RIORXN2 RIORXP2 RIORXN3 RIORXP3 RIOTXN0 RIOTXP0 RIOTXN1 RIOTXP1 RIOTXN2 RIOTXP2 RIOTXN3 RIOTXP3 RIOREFRES
AV24 AV25 AU22 AU23 AW22 AW23 AV21 AV22 AT24 AT25 AR23 AR24 AP22 AP23 AT21 AT22 AM21
I I I I I I I I O O O O O O O O A
Serial RapidIO lane 0 receive data
Serial RapidIO lane 0 transmit data
Serial RapidIO lane 3 transmit data Serial RapidIO SerDes reference resistor input (3 k +/- 1%) SGMII
SGMII0RXN SGMII0RXP SGMII0TXN SGMII0TXP SGMII1RXN SGMII1RXP SGMII1TXN SGMII1TXP SGMII2RXN SGMII2RXP SGMII2TXN SGMII2TXP SGMII3RXN SGMII3RXP
AW28 AW29 AU28 AU29 AV27 AV28 AT27 AT28 AU25 AU26 AR26 AR27 AW25 AW26
I I O O I I O O I I O O I I
Ethernet MAC SGMII port 0 receive data
Ethernet MAC SGMII port 0 transmit data
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Signal Name SGMII3TXN SGMII3TXP SGMIIREFRES
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Ball No. AP25 AP26 AM24 Type O O A IPD/IPU Description Ethernet MAC SGMII port 3 transmit data SGMII SerDes reference resistor input (3 k +/- 1%) SmartReflex Voltage control I C clock Voltage control I2C clock for ARM CorePac domain
2
VCL VCLT VCNTL0 VCNTL1 VCNTL2 VCNTL3 VCNTL4 VCNTL5 VCNTL0T VCNTL1T VCNTL2T VCNTL3T VCNTL4T VCNTL5T VD VDT
AP36 AT37 AT39 AR37 AR36 AT38 AU38 AR35 AU36 AV37 AU37 AV36 AU35 AW36 AP35 AT35
IOZ IOZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ OZ IOZ IOZ
Voltage control outputs to variable core power supply
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Voltage control outputs to variable core power supply for ARM CorePac Domain
Voltage control I C data Voltage control I2C data for ARM CorePac domain SPI0
SPI0CLK SPI0DIN SPI0DOUT SPI0SCS0 SPI0SCS1 SPI0SCS2 SPI0SCS3
B26 A26 A27 F25 C25 E26 D26
OZ I OZ OZ OZ OZ OZ
Down Down Down Up Up Up Up
SPI0 clock SPI0 data in SPI0 data out SPI0 interface enable 0 SPI0 interface enable 1 SPI0 interface enable 2 SPI0 interface enable 3 SPI1
C28 F27 A28 B27 C27 D27 E27
OZ I OZ OZ OZ OZ OZ
SPI1 clock SPI1 data in SPI1 data out SPI1 interface enable 0 SPI1 interface enable 1 SPI1 interface enable 2 SPI1 interface enable 3 SPI2
D25 F28 G28 B28 D28 A29 E25
OZ I OZ OZ OZ OZ OZ
SPI2 clock SPI2 data in SPI2 data out SPI2 interface enable 0 SPI2 interface enable 1 SPI2 interface enable 2 SPI2 interface enable 3
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Ball No. Type IPD/IPU Description Sync-Ethernet / IEEE1588
Table 4-2
Signal Name
TSCOMPOUT TSPUSHEVT0 TSPUSHEVT1 TSSYNCEVT
AB1 AC2 AC1 AC3
O IOZ IOZ O
Down Down Down Down
IEEE1588 compare output. PPS push event from GPS for IEEE1588 Push event from BCN for IEEE1588 IEEE1588 sync event output. Timer
TIMI0 TIMI1 TIMO0 TIMO1
M2 M1 M3 M4
I I OZ OZ
Down Down Down Down
Timer inputs
Timer outputs UART0
UART0CTS UART0RTS UART0RXD UART0TXD
L1 L4 K4 K2
I OZ I OZ
Down Down Down Down UART1 UART0
UART1CTS UART1RTS UART1RXD UART1TXD
K1 M5 L2 K3
I OZ I OZ
Down Down Down Down USB 3.0 UART1
USBCLKM USBCLKP USBDM USBDP USBDRVVBUS USBID0 USBRX0M USBRX0P USBTX0M USBTX0P USBVBUS USBRESREF
V2 W2 T2 U2 L3 R1 Y1 W1 V1 U1 T1 AA1
I I IOZ IOZ O A I I O O A P Down
USB ref clock USB DUSB D+ Used to enable an external charge pump to provide +5V on the VBUS pin of the USB connector. USB ID USB receive data
USB transmit data Connect to VBUS pin on USB connector through protection switch Reference resistor connection for USB PHY USIM
USIMCLK USIMIO USIMRST
AN32 AP33 AP32
OZ IOZ OZ
Down Up Down
USIM clock USIM data USIM reset Reserved
RSV000 RSV001 RSV002 RSV003 RSV004 RSV005
P2 P1 AN4 AM4 B24 A24
OZ OZ O O O O
Down Down
Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected
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Signal Name RSV006 RSV007 RSV008 RSV009 RSV010 RSV011 RSV012 RSV013 RSV014 RSV015 RSV016 RSV017 RSV018 RSV019 RSV020 RSV021 RSV022 RSV023 RSV024 RSV025 RSV026 RSV027 RSV028 RSV029 RSV030 RSV031 RSV032 RSV060 RSV061 RSV062 RSV063 RSV064 RSV065 RSV066 RSV067 RSV068 RSV069 RSV070 RSV071 RSV072 RSV073 End of Table 4-2
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Ball No. AP38 AP39 AU34 AT34 C38 D38 AK5 F23 E23 E33 F32 F26 G26 AN10 AM7 AM23 AM28 AM25 AM16 AM14 AN19 D12 D13 F13 AD35 AC34 AB32 AV19 AV18 AT19 AT18 AW20 AW19 AR20 AR19 AN16 AM19 AU19 AU20 AT33 AR34 Type O O O O O O OZ A A A A A A A A A A A A A A OZ OZ A OZ OZ A I I O O I I O O A A I I IOZ O Up Down Down IPD/IPU Description Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected GND Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected Reserved leave unconnected
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SPRS835DAugust 2013 Terminal Functions Power and Ground (Part 1 of 2)

Ball No. AF11 N20 N28 AH29 AG26 P11 M13 M15 M18 M20 Y28 AB28 AC28 AD28 AE28 Volts 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V Description C66x CorePac PLL supply DDR3A PLL supply ARM CorePac PLL supply DDR3B PLL supply Network Coprocessor PLL supply DDRA DLL supply DDRA DLL supply DDRA DLL supply DDRA DLL supply
Table 4-3
Supply AVDDA1 AVDDA2 AVDDA3 AVDDA4 AVDDA5 AVDDA6 AVDDA7 AVDDA8 AVDDA9 AVDDA10 AVDDA11 AVDDA12 AVDDA13 AVDDA14 AVDDA15 CVDD
DDRB DLL supply DDRB DLL supply DDRB DLL supply DDRB DLL supply DDRB DLL supply SmartReflex DSP core supply voltage. Must be tied to CVDDT rail
L6, M7, M9, M25, N6, N8, N10, N12, N14, N16, N18, N22, P7, AVS P9, P13, P15, P17, P19, P21, P27, R8, R10, R12, R14, R16, R18, R20, T9, T11, T15, T17, T19, T27, U8, U10, U12, U18, V9, V15, V19, V27, W8, W10, W12, W14, W18, W20, Y9, Y15, Y17, Y19, Y21, Y23, Y25, Y27, AA8, AA10, AA16, AA18, AA20, AA22, AA24, AA26, AB9, AB11, AB15, AB17, AB19, AB21, AB23, AB25, AB27, AC8, AC10, AC12, AC14, AC16, AC20, AC22, AC24, AC26, AD9, AD13, AD15, AD21, AD23, AD25, AD27, AE8, AE10, AE12, AE14, AE16, AE18, AE20, AE22, AE24, AE26, AF9, AF25, AF27, AG8, AG10, AG28, AH9, AH27, AJ8, AJ10, AJ28, AK7, AK9, AK29, AL6, AL8, AL30, AM5, AM31 T13, T21, U14, U16, U20, V13, V17, V21, W16, AC18, AD17, AD19 0.95 V
CVDD1 CVDDT CVDDT1
Core supply voltage for memory array SmartReflex Cortex-A15 processor core supply voltage. Must be tied to CVDD rail Cortex-A15 processor fixed core memory supply voltage 0.75-V DDR3A reference voltage 0.75-V DDR3B reference voltage 1.5-V DDR IO supply
H31, J30, K29, L28, M27, N24, N26, P23, P25, R24, R26, T23, AVS T25, U24, U26, V23, V25, W24, W26 R22, U22, W22 0.95 V 0.75 V 0.75 V
DDR3AVREFSSTL G14 DDR3BVREFSSTL AC31 DVDD15
H7, H9, H11, H13, H15, H17, H19, H21, H23, J6, J8, J10, J12, 1.5 V J14, J16, J18, J20, J22, K7, K9, K11, K13, K15, K17, K19, K21, K23, L8, L10, L12, L14, L16, L18, L20, L32, M11, M17, M19, M31, P29, P31, R28, R30, T29, T31, U28, U30, V29, V31, W28, W30, Y29, Y31, AA28, AA30, AB29, AB31, AC30, AD29, AD31, AE30, AF29, AF31, AG30, AH31, AJ30, AK31, AL32 H25, H27, J26, J28, J32, K25, K27, K31, L24, L26, L30, M29, 1.8 V N30, R6, T7, U6, V5, V7, W6, Y5, Y7, AA6, AB5, AB7, AC6, AD7, AE6, AF7, AG6, AJ26, AK27, AL26, AL28, AM27, AM29 AA14 AK11, AK13, AK15, AK17, AK19, AK21, AK23, AK25, AL10, AL12, AL14, AL16, AL18, AL20, AL22, AL24 AF13, AF15, AF17, AF19, AF21, AF23, AG12, AG14, AG16, AG18, AG20, AG22, AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25, AJ12, AJ14, AJ16, AJ18, AJ20, AJ22, AJ24 AB13 3.3 V 1.8 V 0.85 V
DVDD18
1.8-V IO supply
DVDD33 VDDAHV VDDALV
3.3-V USB supply SerDes IO supply SerDes low voltage
VDDUSB
0.85 V
SerDes digital IO supply
Terminals
59
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DDRA DLL supply

Supply VNWA1 VNWA2 VNWA3 VNWA4 VP VPH VPP VPTX VSS
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Terminal Functions Power and Ground (Part 2 of 2)

Ball No. AG24 AD11 M23 V11 AA12 Y13 L22, M21 Y11 0.85 V Volts 0.95 V 0.95 V 0.95 V 0.95 V 0.85 V 3.3 V Description Fixed Nwell supply Fixed Nwell supply Fixed Nwell supply Fixed Nwell supply Filtered 0.85 V USB supply Filtered 3.3 V USB supply Leave unconnected Filtered 0.85 V USB supply Ground
A2, A3, A37, A38, B1, B2, B38, B39, C1, C4, C6, C8, C10, C12, GND C14, C16, C18, C20, C22, C24, C26, C29, C32, C39, D34, D37, E3, E5, E7, E9, E11, E13, E15, E17, E19, E21, E28, G23, G25, G27, G29, G31, G35, H4, H6, H8, H12, H14, H18, H20, H24, H26, H28, H29, H30, H32, H37, J1, J2, J3, J4, J5, J7, J9, J11, J13, J15, J17, J19, J21, J23, J24, J25, J27, J29, J31, J33, K5, K6, K8, K10, K12, K14, K16, K18, K20, K22, K24, K26, K28, K30, K32, K35, L5, L7, L9, L11, L13, L15, L17, L19, L21, L23, L25, L27, L29, L31, L37, M6, M8, M10, M12, M14, M16, M22, M24, M26, M28, M30, M33, N5, N7, N9, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N31, N35, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, P26, P28, P30, P33, P37, R2, R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25, R27, R29, R31, R35, T6, T8, T10, T12, T14, T16, T18, T20, T22, T24, T26, T28, T30, T33, T37, U7, U9, U11, U13, U15, U17, U19, U21, U23, U25, U27, U29, U31, U35, V3, V6, V8, V10, V12, V14, V16, V18, V20, V22, V24, V26, V28, V30, V33, V37, W5, W7, W9, W11, W13, W15, W17, W19, W21, W23, W25, W27, W29, W31, W35, Y2, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, Y24, Y26, Y30, Y33, Y37, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21, AA23, AA25, AA27, AA29, AA35, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AB24, AB26, AB30, AB33, AB36, AB37, AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21, AC23, AC25, AC27, AC29, AC35, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AD20, AD22, AD24, AD26, AD30, AD33, AD37, AE3, AE7, AE9, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE25, AE27, AE29, AE31, AE35, AF6, AF8, AF10, AF12, AF14, AF16, AF18, AF20, AF22, AF24, AF26, AF28, AF30, AF33, AF37, AG4, AG7, AG9, AG11, AG13, AG15, AG17, AG19, AG21, AG23, AG25, AG27, AG29, AG31, AG35, AH6, AH7, AH8, AH10, AH12, AH14, AH16, AH18, AH20, AH22, AH24, AH26, AH28, AH30, AH33, AH37, AJ6, AJ7, AJ9, AJ11, AJ13, AJ15, AJ17, AJ19, AJ21, AJ23, AJ25, AJ27, AJ29, AJ31, AJ32, AJ35, AK2, AK6, AK8, AK10, AK12, AK14, AK16, AK18, AK20, AK22, AK24, AK26, AK28, AK30, AK33, AK37, AL5, AL7, AL9, AL11, AL13, AL15, AL17, AL19, AL21, AL23, AL25, AL27, AL29, AL31, AL35, AM3, AM8, AM10, AM12, AM13, AM17, AM18, AM20, AM22, AM32, AM33, AM37, AN2, AN5, AN6, AN7, AN8, AN9, AN11, AN12, AN13, AN14, AN15, AN17, AN18, AN20, AN21, AN22, AN23, AN24, AN25, AN26, AN27, AN28, AN29, AN31, AN35, AP4, AP7, AP10, AP13, AP16, AP19, AP20, AP21, AP24, AP27, AP28, AP29, AP30, AP37, AR3, AR6, AR9, AR12, AR15, AR18, AR21, AR22, AR25, AR28, AR31, AR33, AT2, AT5, AT8, AT11, AT14, AT17, AT20, AP27, AP28, AP29, AP30, AP37, AR3, AR6, AR9, AR12, AR15, AR18, AR21, AR22, AR25, AR28, AR31, AR33, AT2, AT5, AT8, AT11, AT14, AT17, AT20, AT23, AT26, AT29, AT32, AT36, AU1, AU2, AU3, AU6, AU9, AU12, AU15, AU18, AU21, AU24, AU27, AU30, AU33, AU39, AV1, AV2, AV5, AV8, AV11, AV14, AV17, AV20, AV23, AV26, AV29, AV32, AV35, AV38, AV39, AW2, AW3, AW6, AW9, AW12, AW15, AW18, AW21, AW24, AW27, AW30, AW33, AW37, AW38
PRODUCT PREVIEW
End of Table 4-3
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SPRS835DAugust 2013 Terminal Functions By Signal Name (Part 1 of 22)

Ball Number A1 A39 AW1 AW39 AM15 AM11 AW16 AW17 AU16 AU17 AV15 AV16 AW13 AW14 AU13 AV12 AU14 AV13 AP17 AP18 AR16 AR17 AT15 AT16 AP14 AP15 AR13 AR14 AT12 AT13 AL2 AM2 B31 B37 C37 G24 AF11 N20 N28 AH29 AG26 P11
Table 4-4
Table 4-4
Terminal Functions By Signal Name (Part 2 of 22)

Ball Number M13 M15 M18 M20 Y28 AB28 AC28 AD28 AE28 M2 M1 B30 D29 A35 B29 E29 D30 C30 A30 G30 F31 E30 F30 A31 F24 E24 D24 AF5 AL4 F24 E24 D24 G24 L6, M7, M9, M25, N6, N8, N10, N12, N14, N16, N18, N22, P7, P9, P13, P15, P17, P19, P21, P27, R8, R10, R12, R14, R16, R18, R20, T9, T11, T15, T17, T19, T27
Table 4-4

Ball Number U8, U10, U12, U18, V9, V15, V19, V27, W8, W10, W12, W14, W18, W20, Y9, Y15, Y17, Y19, Y21, Y23, Y25, Y27, AA8, AA10, AA16, AA18, AA20, AA22, AA24 AA26, AB9, AB11, AB15, AB17, AB19, AB21, AB23, AB25, AB27, AC8, AC10, AC12, AC14, AC16, AC20, AC22, AC24, AC26, AD9, AD13, AD15, AD21, AD23 AD25, AD27, AE8, AE10, AE12, AE14, AE16, AE18, AE20, AE22, AE24, AE26, AF9, AF25, AF27, AG8, AG10, AG28, AH9, AH27, AJ8, AJ10, AJ28, AK7 AK9, AK29, AL6, AL8, AL30, AM5, AM31 T13, T21, U14, U16, U20, V13, V17, V21, W16, AC18, AD17, AD19 H31, J30, K29, L28, M27, N24, N26, P23, P25, R24, R26, T23, T25, U24, U26, V23, V25, W24, W26 R22, U22, W22 A36 E8 G9 G8 G10 F9 F8 C9 D9 B9 D8 F10 A9 E10 A10 B10 D10
Signal Name (nopin) (nopin) (nopin) (nopin) AIFREFRES0 AIFREFRES1 AIFRXN0 AIFRXP0 AIFRXN1 AIFRXP1 AIFRXN2 AIFRXP2 AIFRXN3 AIFRXP3 AIFRXN4 AIFRXN5 AIFRXP4 AIFRXP5 AIFTXN0 AIFTXP0 AIFTXN1 AIFTXP1 AIFTXN2 AIFTXP2 AIFTXN3 AIFTXP3 AIFTXN4 AIFTXP4 AIFTXN5 AIFTXP5 ALTCORECLKN ALTCORECLKP ARM_LENDIAN ARMCLKN ARMCLKP ARMAVSSHARED AVDDA1 AVDDA2 AVDDA3 AVDDA4 AVDDA5 AVDDA6
Signal Name AVDDA7 AVDDA8 AVDDA9 AVDDA10 AVDDA11 AVDDA12 AVDDA13 AVDDA14 AVDDA15 AVSIFSEL0 AVSIFSEL1 BOOTMODE00 BOOTMODE01 BOOTMODE02 BOOTMODE03 BOOTMODE04 BOOTMODE05 BOOTMODE06 BOOTMODE07 BOOTMODE08 BOOTMODE09 BOOTMODE10 BOOTMODE11 BOOTMODE12 BOOTMODE13 BOOTMODE14 BOOTMODE15 BOOTCOMPLETE CORECLKSEL CORESEL0 CORESEL1 CORESEL2 CORESEL3 CVDD
Signal Name CVDD
CVDD
CVDD
CVDD CVDD1
CVDDT
CVDDT1 DDR3A_REMAP_EN DDR3AA00 DDR3AA01 DDR3AA02 DDR3AA03 DDR3AA04 DDR3AA05 DDR3AA06 DDR3AA07 DDR3AA08 DDR3AA09 DDR3AA10 DDR3AA11 DDR3AA12 DDR3AA13 DDR3AA14 DDR3AA15
Terminals
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PRODUCT PREVIEW

SPRS835DAugust 2013 Table 4-4 Terminal Functions By Signal Name (Part 4 of 22)
Ball Number B11 C11 G11 C13 A16 C15 B16 F15 D15 F14 D14 G15 D11 F11 G12 A11 A25 B12 B13 A12 A13 B25 G1 H2 F1 G2 H1 E2 F2 D2 E4 F4 G3 A4 B4 H3 D3 D4 G4 H5 D5 F5
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Table 4-4

Ball Number G5 D6 C5 B6 C7 F7 F6 A8 B8 G6 G7 D7 E16 G16 F16 G17 D16 D17 F17 E18 C19 D19 G18 F19 G19 B18 D18 F18 A20 B20 D20 G20 C21 E20 F20 G21 C23 G22 D23 F22 E22 B22
Table 4-4

Ball Number F21 D22 C2 F3 A6 E6 C17 A18 D21 A22 E14 D1 E1 C3 B3 B5 A5 A7 B7 B17 A17 A19 B19 B21 A21 B23 A23 A15 B15 E12 G13 A14 B14 H16 H10 H22 G14 F12 AA32 W33 W32 Y34
Signal Name DDR3ABA0 DDR3ABA1 DDR3ABA2 DDR3ACAS DDR3ACB00 DDR3ACB01 DDR3ACB02 DDR3ACB03
Signal Name DDR3AD20 DDR3AD21 DDR3AD22 DDR3AD23 DDR3AD24 DDR3AD25 DDR3AD26 DDR3AD27 DDR3AD28 DDR3AD29 DDR3AD30 DDR3AD31 DDR3AD32 DDR3AD33 DDR3AD34 DDR3AD35 DDR3AD36 DDR3AD37 DDR3AD38 DDR3AD39 DDR3AD40 DDR3AD41 DDR3AD42 DDR3AD43 DDR3AD44 DDR3AD45 DDR3AD46 DDR3AD47 DDR3AD48 DDR3AD49 DDR3AD50 DDR3AD51 DDR3AD52 DDR3AD53 DDR3AD54 DDR3AD55 DDR3AD56 DDR3AD57 DDR3AD58 DDR3AD59 DDR3AD60 DDR3AD61
Signal Name DDR3AD62 DDR3AD63 DDR3ADQM0 DDR3ADQM1 DDR3ADQM2 DDR3ADQM3 DDR3ADQM4 DDR3ADQM5 DDR3ADQM6 DDR3ADQM7 DDR3ADQM8 DDR3ADQS0N DDR3ADQS0P DDR3ADQS1N DDR3ADQS1P DDR3ADQS2N DDR3ADQS2P DDR3ADQS3N DDR3ADQS3P DDR3ADQS4N DDR3ADQS4P DDR3ADQS5N DDR3ADQS5P DDR3ADQS6N DDR3ADQS6P DDR3ADQS7N DDR3ADQS7P DDR3ADQS8N DDR3ADQS8P DDR3AODT0 DDR3AODT1 DDR3ARAS DDR3ARESET DDR3ARZQ0 DDR3ARZQ1 DDR3ARZQ2 DDR3AVREFSSTL DDR3AWE DDR3BA00 DDR3BA01 DDR3BA02 DDR3BA03
PRODUCT PREVIEW
DDR3ACB04 DDR3ACB05 DDR3ACB06 DDR3ACB07 DDR3ACE0 DDR3ACE1 DDR3ACKE0 DDR3ACKE1 DDR3ACLKN DDR3ACLKOUTN0 DDR3ACLKOUTN1 DDR3ACLKOUTP0 DDR3ACLKOUTP1 DDR3ACLKP DDR3AD00 DDR3AD01 DDR3AD02 DDR3AD03 DDR3AD04 DDR3AD05 DDR3AD06 DDR3AD07 DDR3AD08 DDR3AD09 DDR3AD10 DDR3AD11 DDR3AD12 DDR3AD13 DDR3AD14 DDR3AD15 DDR3AD16 DDR3AD17 DDR3AD18 DDR3AD19
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Ball Number W34 V34 W36 W37 AA33 Y32 Y38 AA39 Y35 Y39 AA38 Y36 AA37 AA34 AB35 AC36 AF32 AF34 AE32 AF35 AE33 AE36 AD36 AE34 AB34 AA36 AB39 AB38 AR39 AD39 AC38 AD38 AC39 AR38 L38 N34 M37 L39 N33 N37 N36 N38
Table 4-4
Table 4-4

Ball Number T32 R32 P35 R39 R38 N32 R33 P36 T34 R34 T35 R37 R36 U37 T36 U38 V35 U36 U34 W38 W39 U33 V32 V36 AG37 AF36 AG38 AG34 AG36 AH34 AH35 AG32 AH32 AJ33 AH36 AJ34 AJ36 AH39 AH38 AJ37 AK39 AK38
Table 4-4

Ball Number AK36 AK35 AL34 AL36 AL37 AL33 AN34 AN36 AN33 AM34 AM35 AM38 AM36 AN37 N39 P34 U39 U32 AG33 AG39 AK34 AM39 AE37 M39 M38 P38 P39 T38 T39 V38 V39 AF39 AF38 AJ38 AJ39 AL38 AL39 AN39 AN38 AE38 AE39 AC33
Signal Name DDR3BA04 DDR3BA05 DDR3BA06 DDR3BA07 DDR3BA08 DDR3BA09 DDR3BA10 DDR3BA11 DDR3BA12 DDR3BA13 DDR3BA14 DDR3BA15 DDR3BBA0 DDR3BBA1 DDR3BBA2 DDR3BCAS DDR3BCB00 DDR3BCB01 DDR3BCB02 DDR3BCB03 DDR3BCB04 DDR3BCB05 DDR3BCB06 DDR3BCB07 DDR3BCE0 DDR3BCE1 DDR3BCKE0 DDR3BCKE1 DDR3BCLKN DDR3BCLKOUTN0 DDR3BCLKOUTN1 DDR3BCLKOUTP0 DDR3BCLKOUTP1 DDR3BCLKP DDR3BD00 DDR3BD01 DDR3BD02 DDR3BD03 DDR3BD04 DDR3BD05 DDR3BD06 DDR3BD07
Signal Name DDR3BD08 DDR3BD09 DDR3BD10 DDR3BD11 DDR3BD12 DDR3BD13 DDR3BD14 DDR3BD15 DDR3BD16 DDR3BD17 DDR3BD18 DDR3BD19 DDR3BD20 DDR3BD21 DDR3BD22 DDR3BD23 DDR3BD24 DDR3BD25 DDR3BD26 DDR3BD27 DDR3BD28 DDR3BD29 DDR3BD30 DDR3BD31 DDR3BD32 DDR3BD33 DDR3BD34 DDR3BD35 DDR3BD36 DDR3BD37 DDR3BD38 DDR3BD39 DDR3BD40 DDR3BD41 DDR3BD42 DDR3BD43 DDR3BD44 DDR3BD45 DDR3BD46 DDR3BD47 DDR3BD48 DDR3BD49
Signal Name DDR3BD50 DDR3BD51 DDR3BD52 DDR3BD53 DDR3BD54 DDR3BD55 DDR3BD56 DDR3BD57 DDR3BD58 DDR3BD59 DDR3BD60 DDR3BD61 DDR3BD62 DDR3BD63 DDR3BDQM0 DDR3BDQM1 DDR3BDQM2 DDR3BDQM3 DDR3BDQM4 DDR3BDQM5 DDR3BDQM6 DDR3BDQM7 DDR3BDQM8 DDR3BDQS0N DDR3BDQS0P DDR3BDQS1N DDR3BDQS1P DDR3BDQS2N DDR3BDQS2P DDR3BDQS3N DDR3BDQS3P DDR3BDQS4N DDR3BDQS4P DDR3BDQS5N DDR3BDQS5P DDR3BDQS6N DDR3BDQS6P DDR3BDQS7N DDR3BDQS7P DDR3BDQS8N DDR3BDQS8P DDR3BODT0
Terminals
63
PRODUCT PREVIEW

Ball Number AD34 AD32 AC32 AA31 P32 AK32 AC31 AC37 H7, H9, H11, H13, H15, H17, H19, H21, H23, J6, J8, J10, J12, J14, J16, J18, J20, J22, K7, K9, K11, K13, K15, K17, K19, K21, K23, L8, L10, L12, L14, L16, L18, L20 L32, M11, M17, M19, M31, P29, P31, R28, R30, T29, T31, U28, U30, V29, V31, W28, W30, Y29, Y31, AA28, AA30, AB29, AB31, AC30, AD29, AD31, AE30, AF29 AF31, AG30, AH31, AJ30, AK31, AL32 H25, H27, J26, J28, J32, K25, K27, K31, L24, L26, L30, M29, N30, R6, T7, U6, V5, V7, W6, Y5, Y7, AA6, AB5, AB7, AC6, AD7, AE6, AF7, AG6, AJ26, AK27, AL26, AL28, AM27, AM29 AA14 F34 F37 G36 E39 E34 J34 H35 K33 C35 G37 F38 D35 H36 E35 G38
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Table 4-4

Ball Number F39 K34 F35 J35 G39 C36 J36 H38 D36 H34 H33 G33 G32 G34 E36 M32 J37 L33 L34 H39 J38 K37 J39 K39 K38 K36 L36 L35 M34 M36 M35 E37 F33 E38 D39 F36 AA2 AB2 Y3 Y4 W3 W4
Table 4-4

Ball Number V4 U4 U3 T3 AB4 AA3 U5 T4 AB3 R3 T5 R4 AA4 AC4 F29 B30 D29 A35 B29 E29 D30 C30 A30 G30 F31 E30 F30 A31 E32 B31 A36 A32 C31 B32 A33 D33 D31 B35 B33 E31 A34 D32
Signal Name DDR3BODT1 DDR3BRAS DDR3BRESET DDR3BRZQ0 DDR3BRZQ1 DDR3BRZQ2 DDR3BVREFSSTL DDR3BWE
Signal Name EMIFA15 EMIFA16 EMIFA17 EMIFA18 EMIFA19 EMIFA20 EMIFA21 EMIFA22 EMIFA23 EMIFBE0 EMIFBE1 EMIFCE0 EMIFCE1 EMIFCE2 EMIFCE3 EMIFD00 EMIFD01 EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD06 EMIFD07 EMIFD08 EMIFD09 EMIFD10 EMIFD11 EMIFD12 EMIFD13 EMIFD14 EMIFD15 EMIFOE EMIFRNW EMIFWAIT0 EMIFWAIT1 EMIFWE EMU00 EMU01 EMU02 EMU03 EMU04 EMU05
Signal Name EMU06 EMU07 EMU08 EMU09 EMU10 EMU11 EMU12 EMU13 EMU14 EMU15 EMU16 EMU17 EMU18 EXTFRAMEEVENT GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27
PRODUCT PREVIEW
DVDD15
DVDD15
DVDD15 DVDD18
DVDD33 EMIFA00 EMIFA01 EMIFA02 EMIFA03 EMIFA04 EMIFA05 EMIFA06 EMIFA07 EMIFA08 EMIFA09 EMIFA10 EMIFA11 EMIFA12 EMIFA13 EMIFA14
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Terminals

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Ball Number C33 C34 B36 B34 AE5 AT10 AT9 AM9 AJ5 AJ4 AW10 AU10 AV9 AW7 AW11 AU11 AV10 AW8 AJ2 AG3 AJ3 AG5 AP11 AR10 AP8 AR7 AP12 AR11 AP9 AR8 AH5 AJ1 AW5 AW4 AM6 AH4 AG2 AU7 AV6 AU4 AV3 AU8
Table 4-4
Table 4-4

Ball Number AV7 AU5 AV4 AF3 AF4 AH3 AH2 AT6 AP5 AR4 AT3 AT7 AP6 AR5 AT4 AH1 AF2 F29 AD4 AE4 E32 AP31 AR32 AD5 AN30 AV34 AV33 AW32 AW31 AM26 AU31 AV30 AU32 AV31 AT30 AR29 AT31 AR30 AP34 AK4 AD3 AC5
Table 4-4

Ball Number AD2 AM30 AM21 AV24 AU22 AW22 AV21 AV25 AU23 AW23 AV22 AT24 AR23 AP22 AT21 AT25 AR24 AP23 AT22 AR2 AP2 AR1 AT1 P2 P1 AN4 AM4 B24 A24 AP38 AP39 AU34 AT34 C38 D38 AK5 F23 E23 E33 F32 F26 G26
Signal Name GPIO28 GPIO29 GPIO30 GPIO31 HOUT HYP0CLKN HYP0CLKP HYP0REFRES HYP0RXFLCLK HYP0RXFLDAT HYP0RXN0 HYP0RXN1 HYP0RXN2 HYP0RXN3 HYP0RXP0 HYP0RXP1 HYP0RXP2 HYP0RXP3 HYP0RXPMCLK HYP0RXPMDAT HYP0TXFLCLK HYP0TXFLDAT HYP0TXN0 HYP0TXN1 HYP0TXN2 HYP0TXN3 HYP0TXP0 HYP0TXP1 HYP0TXP2 HYP0TXP3 HYP0TXPMCLK HYP0TXPMDAT HYP1CLKN HYP1CLKP HYP1REFRES HYP1RXFLCLK HYP1RXFLDAT HYP1RXN0 HYP1RXN1 HYP1RXN2 HYP1RXN3 HYP1RXP0
Signal Name HYP1RXP1 HYP1RXP2 HYP1RXP3 HYP1RXPMCLK HYP1RXPMDAT HYP1TXFLCLK HYP1TXFLDAT HYP1TXN0 HYP1TXN1 HYP1TXN2 HYP1TXN3 HYP1TXP0 HYP1TXP1 HYP1TXP2 HYP1TXP3 HYP1TXPMCLK HYP1TXPMDAT LENDIAN LRESETNMIEN LRESET MAINPLLODSEL MDCLK MDIO NMI PACLKSEL PASSCLKN PASSCLKP PCIECLKN PCIECLKP PCIEREFRES PCIERXN0 PCIERXN1 PCIERXP0 PCIERXP1 PCIETXN0 PCIETXN1 PCIETXP0 PCIETXP1 PHYSYNC POR RESETFULL RESETSTAT
Signal Name RESET RADSYNC RIOREFRES RIORXN0 RIORXN1 RIORXN2 RIORXN3 RIORXP0 RIORXP1 RIORXP2 RIORXP3 RIOTXN0 RIOTXN1 RIOTXN2 RIOTXN3 RIOTXP0 RIOTXP1 RIOTXP2 RIOTXP3 RP1CLKP RP1CLKN RP1FBP RP1FBN RSV000 RSV001 RSV002 RSV003 RSV004 RSV005 RSV006 RSV007 RSV008 RSV009 RSV010 RSV011 RSV012 RSV013 RSV014 RSV015 RSV016 RSV017 RSV018
Terminals
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PRODUCT PREVIEW

Ball Number AN10 AM7 AM23 AM28 AM25 AM16 AM14 AN19 D12 D13 F13 AD35 AC34 AB32 AV19 AV18 AT19 AT18 AW20 AW19 AR20 AR19 AN16 AM19 AU19 AU20 AT33 AR34 N1 N4 P4 P3 N2 N3 AW28 AW29 AU28 AU29 AV27 AV28 AT27 AT28
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Table 4-4

Ball Number AU25 AU26 AR26 AR27 AW25 AW26 AP25 AP26 AM24 B26 A26 A27 F25 C25 E26 D26 C28 F27 A28 B27 C27 D27 E27 D25 F28 G28 B28 D28 A29 E25 AW35 AW34 AK3 AK1 AL3 AE1 AG1 AF1 M2 M1 M3 M4
Table 4-4

Ball Number AE2 AD1 AB1 AC2 AC1 AL1 AM1 AP1 AN1 AP3 AN3 AC3 L1 L4 K4 K2 K1 M5 L2 K3 V2 W2 T2 U2 L3 R1 AA1 Y1 W1 V1 U1 T1 AP32 AN32 AP33 AP36 AT37 AT39 AU36 AR37 AV37 AR36
Signal Name RSV019 RSV020 RSV021 RSV022 RSV023 RSV024 RSV025 RSV026
Signal Name SGMII2RXN SGMII2RXP SGMII2TXN SGMII2TXP SGMII3RXN SGMII3RXP SGMII3TXN SGMII3TXP SGMIIREFRES SPI0CLK SPI0DIN SPI0DOUT SPI0SCS0 SPI0SCS1 SPI0SCS2 SPI0SCS3 SPI1CLK SPI1DIN SPI1DOUT SPI1SCS0 SPI1SCS1 SPI1SCS2 SPI1SCS3 SPI2CLK SPI2DIN SPI2DOUT SPI2SCS0 SPI2SCS1 SPI2SCS2 SPI2SCS3 SRIOSGMIICLKN SRIOSGMIICLKP SYSCLKN SYSCLKOUT SYSCLKP TCK TDI TDO TIMI0 TIMI1 TIMO0 TIMO1
Signal Name TMS TRST TSCOMPOUT TSPUSHEVT0 TSPUSHEVT1 TSREFCLKN TSREFCLKP TSRXCLKOUT0N TSRXCLKOUT0P TSRXCLKOUT1N TSRXCLKOUT1P TSSYNCEVT UART0CTS UART0RTS UART0RXD UART0TXD UART1CTS UART1RTS UART1RXD UART1TXD USBCLKM USBCLKP USBDM USBDP USBDRVVBUS USBID0 USBRESREF USBRX0M USBRX0P USBTX0M USBTX0P USBVBUS USIMRST USIMCLK USIMIO VCL VCLT VCNTL0 VCNTL0T VCNTL1 VCNTL1T VCNTL2
PRODUCT PREVIEW
RSV027 RSV028 RSV029 RSV030 RSV031 RSV032 RSV060 RSV061 RSV062 RSV063 RSV064 RSV065 RSV066 RSV067 RSV068 RSV069 RSV070 RSV071 RSV072 RSV073 SCL0 SCL1 SCL2 SDA0 SDA1 SDA2 SGMII0RXN SGMII0RXP SGMII0TXN SGMII0TXP SGMII1RXN SGMII1RXP SGMII1TXN SGMII1TXP
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Ball Number AU37 AT38 AV36 AU38 AU35 AR35 AW36 AP35 AK11, AK13, AK15, AK17, AK19, AK21, AK23, AK25, AL10, AL12, AL14, AL16, AL18, AL20, AL22, AL24 AF13, AF15, AF17, AF19, AF21, AF23, AG12, AG14, AG16, AG18, AG20, AG22, AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25, AJ12, AJ14, AJ16, AJ18, AJ20, AJ22, AJ24 AB13 AT35 AG24 AD11 M23 V11 AA12 Y13 L22, M21 Y11 A2, A3, A37, A38, B1, B2, B38, B39, C1, C4, C6, C8, C10, C12, C14, C16, C18, C20, C22, C24, C26, C29, C32, C39, D34, D37, E3, E5, E7, E9, E11, E13, E15, E17, E19 E21, E28, G23, G25, G27, G29, G31, G35, H4, H6, H8, H12, H14, H18, H20, H24, H26, H28, H29, H30, H32, H37, J1, J2, J3, J4, J5, J7, J9, J11, J13, J15, J17, J19 VSS VSS VSS
Table 4-4
Table 4-4

Ball Number J21, J23, J24, J25, J27, J29, J31, J33, K5, K6, K8, K10, K12, K14, K16, K18, K20, K22, K24, K26, K28, K30, K32, K35, L5, L7, L9, L11, L13, L15, L17, L19, L21, L23 L25, L27, L29, L31, L37, M6, M8, M10, M12, M14, M16, M22, M24, M26, M28, M30, M33, N5, N7, N9, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29 N31, N35, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, P26, P28, P30, P33, P37, R2, R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25, R27, R29, R31, R35 T6, T8, T10, T12, T14, T16, T18, T20, T22, T24, T26, T28, T30, T33, T37, U7, U9, U11, U13, U15, U17, U19, U21, U23, U25, U27, U29, U31, U35, V3, V6, V8, V10, V12 V14, V16, V18, V20, V22, V24, V26, V28, V30, V33, V37, W5, W7, W9, W11, W13, W15, W17, W19, W21, W23, W25, W27, W29, W31, W35, Y2, Y6, Y8, Y10 Y12, Y14, Y16, Y18, Y20, Y22, Y24, Y26, Y30, Y33, Y37, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21, AA23, AA25, AA27, AA29, AA35, AB6, AB8 AB10, AB12, AB14, AB16, AB18, AB20, AB22, AB24, AB26, AB30, AB33, AB36, AB37, AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21, AC23, AC25, AC27
Table 4-4

Ball Number AC29, AC35, AD6, AD8, AD10, AD12, AD14, AD16, AD18, AD20, AD22, AD24, AD26, AD30, AD33, AD37, AE3, AE7, AE9, AE11, AE13, AE15, AE17, AE19 AE21, AE23, AE25, AE27, AE29, AE31, AE35, AF6, AF8, AF10, AF12, AF14, AF16, AF18, AF20, AF22, AF24, AF26, AF28, AF30, AF33, AF37, AG4, AG7 AG9, AG11, AG13, AG15, AG17, AG19, AG21, AG23, AG25, AG27, AG29, AG31, AG35, AH6, AH7, AH8, AH10, AH12, AH14, AH16, AH18, AH20, AH22, AH24 AH26, AH28, AH30, AH33, AH37, AJ6, AJ7, AJ9, AJ11, AJ13, AJ15, AJ17, AJ19, AJ21, AJ23, AJ25, AJ27, AJ29, AJ31, AJ32, AJ35, AK2, AK6, AK8, AK10 AK12, AK14, AK16, AK18, AK20, AK22, AK24, AK26, AK28, AK30, AK33, AK37, AL5, AL7, AL9, AL11, AL13, AL15, AL17, AL19, AL21, AL23, AL25, AL27, AL29 AL31, AL35, AM3, AM8, AM10, AM12, AM13, AM17, AM18, AM20, AM22, AM32, AM33, AM37, AN2, AN5, AN6, AN7, AN8, AN9, AN11, AN12, AN13, AN14 AN15, AN17, AN18, AN20, AN21, AN22, AN23, AN24, AN25, AN26, AN27, AN28, AN29, AN31, AN35, AP4, AP7, AP10, AP13, AP16, AP19, AP20, AP21, AP24
Signal Name VCNTL2T VCNTL3 VCNTL3T VCNTL4 VCNTL4T VCNTL5 VCNTL5T VD VDDAHV
Signal Name VSS
Signal Name VSS
VSS
VSS
VSS
VDDALV
VSS
VSS
VDDUSB VDT VNWA1 VNWA2 VNWA3 VNWA4 VP VPH VPP VPTX VSS
VSS
VSS
VSS
VSS
VSS
Terminals
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PRODUCT PREVIEW

Ball Number AP27, AP28, AP29, AP30, AP37, AR3, AR6, AR9, AR12, AR15, AR18, AR21, AR22, AR25, AR28, AR31, AR33, AT2, AT5, AT8, AT11, AT14, AT17, AT20 AT23, AT26, AT29, AT32, AT36, AU1, AU2, AU3, AU6, AU9, AU12, AU15, AU18, AU21, AU24, AU27, AU30, AU33, AU39, AV1, AV2, AV5, AV8, AV11 AV14, AV17, AV20, AV23, AV26, AV29, AV32, AV35, AV38, AV39, AW2, AW3, AW6, AW9, AW12, AW15, AW18, AW21, AW24, AW27, AW30, AW33, AW37, AW38
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Signal Name VSS
VSS
PRODUCT PREVIEW
VSS
End of Table 4-4
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SPRS835DAugust 2013 Terminal Functions By Ball Number (Part 1 of 38)

Signal Name (nopin) VSS VSS DDR3AD11 DDR3ADQS2P DDR3ADQM2 DDR3ADQS3N DDR3AD27 DDR3AA11 DDR3AA13 DDR3ACKE1 DDR3ACLKOUTP0 DDR3ACLKOUTP1 DDR3ARAS DDR3ADQS8N DDR3ACB00 DDR3ADQS4P DDR3ADQM5 DDR3ADQS5N DDR3AD48 DDR3ADQS6P DDR3ADQM7 DDR3ADQS7P RSV005 DDR3ACLKN SPI0DIN SPI0DOUT SPI1DOUT SPI2SCS2 GPIO08 BOOTMODE07 GPIO13 BOOTMODE12 GPIO17 EMU19 GPIO20 EMU22 GPIO26 EMU28 GPIO03 BOOTMODE02 GPIO16
Table 4-5
Table 4-5
Terminal Functions By Ball Number (Part 2 of 38)

Signal Name DDR3A_REMAP_EN VSS VSS (nopin) VSS VSS DDR3ADQS1P DDR3AD12 DDR3ADQS2N DDR3AD23 DDR3ADQS3P DDR3AD28 DDR3AA08 DDR3AA14 DDR3ABA0 DDR3ACLKOUTN0 DDR3ACLKOUTN1 DDR3ARESET DDR3ADQS8P DDR3ACB02 DDR3ADQS4N DDR3AD45 DDR3ADQS5P DDR3AD49 DDR3ADQS6N DDR3AD61 DDR3ADQS7N RSV004 DDR3ACLKP SPI0CLK SPI1SCS0 SPI2SCS0 GPIO04 BOOTMODE03 GPIO01 BOOTMODE00 GPIO15 ARM_LENDIAN GPIO19 EMU21 GPIO24 EMU26
Table 4-5

Signal Name GPIO31 EMU33 GPIO23 EMU25 GPIO30 EMU32 ARMCLKN VSS VSS VSS DDR3ADQM0 DDR3ADQS1N VSS DDR3AD22 VSS DDR3AD24 VSS DDR3AA06 VSS DDR3ABA1 VSS DDR3ACAS VSS DDR3ACB01 VSS DDR3ADQM4 VSS DDR3AD40 VSS DDR3AD52 VSS DDR3AD56 VSS SPI0SCS1 VSS SPI1SCS1 SPI1CLK VSS GPIO07 BOOTMODE06 GPIO18 EMU20
Ball Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A30 A31 A31 A32 A32 A33 A33 A34 A34 A35 A35 A36
Ball Number A36 A37 A38 A39 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B29 B30 B30 B31 B31 B32 B32 B33 B33
Ball Number B34 B34 B35 B35 B36 B36 B37 B38 B39 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C30 C31 C31
Terminals
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PRODUCT PREVIEW

SPRS835DAugust 2013 Table 4-5 Terminal Functions By Ball Number (Part 4 of 38)
Signal Name VSS GPIO28 EMU30 GPIO29 EMU31 EMIFA08 EMIFA20 ARMCLKP RSV010 VSS DDR3ADQS0N DDR3AD07 DDR3AD14 DDR3AD15 DDR3AD18 DDR3AD21 DDR3AD31 DDR3AA09 DDR3AA07 DDR3AA15 DDR3ACE0 RSV027 RSV028 DDR3ACB06 DDR3ACB04 DDR3AD36 DDR3AD37 DDR3AD46 DDR3AD41 DDR3AD50 DDR3ADQM6 DDR3AD63 DDR3AD58 CORESEL2 SPI2CLK SPI0SCS3 SPI1SCS2 SPI2SCS1 GPIO02 BOOTMODE01 GPIO06 BOOTMODE05
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Table 4-5

Signal Name GPIO22 EMU24 GPIO27 EMU29 GPIO21 EMU23 VSS EMIFA11 EMIFA23 VSS RSV011 EMIFWAIT1 DDR3ADQS0P DDR3AD05 VSS DDR3AD08 VSS DDR3ADQM3 VSS DDR3AA00 VSS DDR3AA12 VSS DDR3AODT0 VSS DDR3ADQM8 VSS DDR3AD32 VSS DDR3AD39 VSS DDR3AD53 VSS DDR3AD60 RSV014 CORESEL1 SPI2SCS3 SPI0SCS2 SPI1SCS3 VSS GPIO05 BOOTMODE04
Table 4-5

Signal Name GPIO11 BOOTMODE10 GPIO25 EMU27 GPIO14 MAINPLLODSEL RSV015 EMIFA04 EMIFA13 EMIFCE3 EMIFOE EMIFWAIT0 EMIFA03 DDR3AD02 DDR3AD06 DDR3ADQM1 DDR3AD09 DDR3AD19 DDR3AD26 DDR3AD25 DDR3AA05 DDR3AA04 DDR3AA10 DDR3ACE1 DDR3AWE RSV029 DDR3ACB05 DDR3ACB03 DDR3AD34 DDR3AD38 DDR3AD47 DDR3AD43 DDR3AD54 DDR3AD62 DDR3AD59 RSV013 CORESEL0 SPI0SCS0 RSV017 SPI1DIN SPI2DIN GPIO00
Ball Number C32 C33 C33 C34 C34 C35 C36 C37
Ball Number D31 D31 D32 D32 D33 D33 D34 D35 D36 D37 D38 D39 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E29
Ball Number E30 E30 E31 E31 E32 E32 E33 E34 E35 E36 E37 E38 E39 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
PRODUCT PREVIEW
C38 C39 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D29 D30 D30
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Signal Name GPIO12 BOOTMODE11 GPIO10 BOOTMODE09 RSV016 EMIFRNW EMIFA00 EMIFA17 EMIFWE EMIFA01 EMIFA10 EMIFA15 DDR3AD00 DDR3AD03 DDR3AD10 DDR3AD16 DDR3AD20 DDR3AD29 DDR3AD30 DDR3AA02 DDR3AA01 DDR3AA03 DDR3ABA2 DDR3ACKE0 DDR3AODT1 DDR3AVREFSSTL DDR3ACB07 DDR3AD33 DDR3AD35 DDR3AD42 DDR3AD44 DDR3AD51 DDR3AD55 DDR3AD57 VSS CORESEL3 ARMAVSSHARED VSS RSV018 VSS SPI2DOUT VSS
Table 4-5
Table 4-5

Signal Name GPIO09 BOOTMODE08 VSS EMIFCE1 EMIFCE0 EMIFCE2 VSS EMIFA02 EMIFA09 EMIFA14 EMIFA19 DDR3AD04 DDR3AD01 DDR3AD13 VSS DDR3AD17 VSS DVDD15 VSS DVDD15 DDR3ARZQ1 DVDD15 VSS DVDD15 VSS DVDD15 DDR3ARZQ0 DVDD15 VSS DVDD15 VSS DVDD15 DDR3ARZQ2 DVDD15 VSS DVDD18 VSS DVDD18 VSS VSS VSS CVDDT
Table 4-5

Signal Name VSS EMIFBE1 EMIFBE0 EMIFA06 EMIFA12 VSS EMIFA22 EMIFD04 VSS VSS VSS VSS VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS VSS VSS DVDD18 VSS DVDD18 VSS CVDDT VSS DVDD18 VSS EMIFA05
Ball Number F30 F30 F31 F31 F32 F33 F34 F35 F36 F37 F38 F39 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G24 G25 G26 G27 G28 G29
Ball Number G30 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31
Ball Number H32 H33 H34 H35 H36 H37 H38 H39 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34
Terminals
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PRODUCT PREVIEW

Signal Name EMIFA18 EMIFA21 EMIFD01 EMIFD05 EMIFD07 UART1CTS UART0TXD UART1TXD UART0RXD VSS VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD18 VSS DVDD18 VSS CVDDT VSS DVDD18 VSS EMIFA07 EMIFA16 VSS EMIFD10 EMIFD06
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Table 4-5

Signal Name EMIFD09 EMIFD08 UART0CTS UART1RXD USBDRVVBUS UART0RTS VSS CVDD VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS VPP VSS DVDD18 VSS DVDD18 VSS CVDDT VSS DVDD18 VSS DVDD15 EMIFD02 EMIFD03 EMIFD12 EMIFD11 VSS DDR3BD00 DDR3BD03 TIMI1
Table 4-5

Signal Name AVSIFSEL1 TIMI0 AVSIFSEL0 TIMO0 TIMO1 UART1RTS VSS CVDD VSS CVDD VSS DVDD15 VSS AVDDA7 VSS AVDDA8 VSS DVDD15 AVDDA9 DVDD15 AVDDA10 VPP VSS VNWA3 VSS CVDD VSS CVDDT VSS DVDD18 VSS DVDD15 EMIFD00 VSS EMIFD13 EMIFD15 EMIFD14 DDR3BD02 DDR3BDQS0P DDR3BDQS0N SCL0 SDA1
Ball Number J35 J36 J37 J38 J39 K1 K2 K3
Ball Number K38 K39 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 L35 L36 L37 L38 L39 M1
Ball Number M1 M2 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 M36 M37 M38 M39 N1 N2
PRODUCT PREVIEW
K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37
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Signal Name SDA2 SCL1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS AVDDA2 VSS CVDD VSS CVDDT VSS CVDDT VSS AVDDA3 VSS DVDD18 VSS DDR3BD13 DDR3BD04 DDR3BD01 VSS DDR3BD06 DDR3BD05 DDR3BD07 DDR3BDQM0 RSV001 RSV000 SDA0 SCL2 VSS
Table 4-5
Table 4-5

Signal Name VSS CVDD VSS CVDD VSS AVDDA6 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDDT VSS CVDDT VSS CVDD VSS DVDD15 VSS DVDD15 DDR3BRZQ1 VSS DDR3BDQM1 DDR3BD10 DDR3BD15 VSS DDR3BDQS1N DDR3BDQS1P USBID0 VSS EMU15 EMU17 VSS DVDD18 VSS CVDD
Table 4-5

Signal Name VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDDT1 VSS CVDDT VSS CVDDT VSS DVDD15 VSS DVDD15 VSS DDR3BD09 DDR3BD14 DDR3BD17 VSS DDR3BD20 DDR3BD19 DDR3BD12 DDR3BD11 USBVBUS USBDM EMU09 EMU13 EMU16 VSS DVDD18 VSS CVDD VSS CVDD
Ball Number N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 N35 N36 N37 N38 N39 P1 P2 P3 P4 P5
Ball Number P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 R1 R2 R3 R4 R5 R6 R7 R8
Ball Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Terminals
73
PRODUCT PREVIEW

Signal Name VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDDT VSS CVDDT VSS CVDD VSS DVDD15 VSS DVDD15 DDR3BD08 VSS DDR3BD16 DDR3BD18 DDR3BD22 VSS DDR3BDQS2N DDR3BDQS2P USBTX0P USBDP EMU08 EMU07 EMU12 DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD1
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Table 4-5

Signal Name VSS CVDD1 VSS CVDD VSS CVDD1 VSS CVDDT1 VSS CVDDT VSS CVDDT VSS DVDD15 VSS DVDD15 VSS DDR3BDQM3 DDR3BD29 DDR3BD26 VSS DDR3BD25 DDR3BD21 DDR3BD23 DDR3BDQM2 USBTX0M USBCLKM VSS EMU06 DVDD18 VSS DVDD18 VSS CVDD VSS VNWA4 VSS CVDD1 VSS CVDD VSS CVDD1
Table 4-5

Signal Name VSS CVDD VSS CVDD1 VSS CVDDT VSS CVDDT VSS CVDD VSS DVDD15 VSS DVDD15 DDR3BD30 VSS DDR3BA05 DDR3BD24 DDR3BD31 VSS DDR3BDQS3N DDR3BDQS3P USBRX0P USBCLKP EMU04 EMU05 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD
Ball Number T12 T13 T14 T15 T16 T17 T18 T19
Ball Number U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U38 U39 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17
Ball Number V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 V39 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20
PRODUCT PREVIEW
T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14
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Terminals

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Signal Name VSS CVDDT1 VSS CVDDT VSS CVDDT VSS DVDD15 VSS DVDD15 VSS DDR3BA02 DDR3BA01 DDR3BA04 VSS DDR3BA06 DDR3BA07 DDR3BD27 DDR3BD28 USBRX0M VSS EMU02 EMU03 DVDD18 VSS DVDD18 VSS CVDD VSS VPTX VSS VPH VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD
Table 4-5
Table 4-5

Signal Name VSS CVDD VSS CVDD AVDDA11 DVDD15 VSS DVDD15 DDR3BA09 VSS DDR3BA03 DDR3BA12 DDR3BA15 VSS DDR3BA10 DDR3BA13 USBRESREF EMU00 EMU11 EMU18 VSS DVDD18 VSS CVDD VSS CVDD VSS VP VSS DVDD33 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD
Table 4-5

Signal Name VSS DVDD15 VSS DVDD15 DDR3BRZQ0 DDR3BA00 DDR3BA08 DDR3BBA1 VSS DDR3BCE1 DDR3BBA0 DDR3BA14 DDR3BA11 TSCOMPOUT EMU01 EMU14 EMU10 DVDD18 VSS DVDD18 VSS CVDD VSS CVDD VSS VDDUSB VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA12 DVDD15
Ball Number W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23
Ball Number Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26
Ball Number AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AA39 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29
Terminals
75
PRODUCT PREVIEW

Signal Name VSS DVDD15 RSV032 VSS DDR3BCE0 DDR3BBA2 VSS VSS DDR3BCKE1 DDR3BCKE0 TSPUSHEVT1 TSPUSHEVT0 TSSYNCEVT EXTFRAMEEVENT RESETSTAT DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS AVDDA13 VSS DVDD15 DDR3BVREFSSTL DDR3BRESET
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Table 4-5

Signal Name DDR3BODT0 RSV031 VSS DDR3BCAS DDR3BWE DDR3BCLKOUTN1 DDR3BCLKOUTP1 TRST RESET RESETFULL LRESETNMIEN NMI VSS DVDD18 VSS CVDD VSS VNWA2 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA14 DVDD15 VSS DVDD15 DDR3BRAS VSS DDR3BODT1 RSV030
Table 4-5

Signal Name DDR3BCB06 VSS DDR3BCLKOUTP0 DDR3BCLKOUTN0 TCK TMS VSS LRESET HOUT DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS AVDDA15 VSS DVDD15 VSS DDR3BCB02 DDR3BCB04 DDR3BCB07 VSS DDR3BCB05 DDR3BDQM8 DDR3BDQS8N
Ball Number AB30 AB31 AB32 AB33 AB34 AB35 AB36 AB37
Ball Number AC33 AC34 AC35 AC36 AC37 AC38 AC39 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AD35
Ball Number AD36 AD37 AD38 AD39 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AE35 AE36 AE37 AE38
PRODUCT PREVIEW
AB38 AB39 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32
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Terminals

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Signal Name DDR3BDQS8P TDO HYP1TXPMDAT HYP1RXPMCLK HYP1RXPMDAT BOOTCOMPLETE VSS DVDD18 VSS CVDD VSS AVDDA1 VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 DDR3BCB00 VSS DDR3BCB01 DDR3BCB03 DDR3BD33 VSS DDR3BDQS4P DDR3BDQS4N TDI HYP1RXFLDAT
Table 4-5
Table 4-5

Signal Name HYP0RXPMDAT VSS HYP0TXFLDAT DVDD18 VSS CVDD VSS CVDD VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VNWA1 VSS AVDDA5 VSS CVDD VSS DVDD15 VSS DDR3BD39 DDR3BDQM4 DDR3BD35 VSS DDR3BD36 DDR3BD32 DDR3BD34 DDR3BDQM5 HYP1TXPMCLK HYP1TXFLDAT HYP1TXFLCLK HYP1RXFLCLK HYP0TXPMCLK
Table 4-5

Signal Name VSS VSS VSS CVDD VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS CVDD VSS AVDDA4 VSS DVDD15 DDR3BD40 VSS DDR3BD37 DDR3BD38 DDR3BD42 VSS DDR3BD46 DDR3BD45 HYP0TXPMDAT HYP0RXPMCLK HYP0TXFLCLK HYP0RXFLDAT HYP0RXFLCLK VSS VSS CVDD
Ball Number AE39 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AF36 AF37 AF38 AF39 AG1 AG2
Ball Number AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AG35 AG36 AG37 AG38 AG39 AH1 AH2 AH3 AH4 AH5
Ball Number AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AH35 AH36 AH37 AH38 AH39 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8
Terminals
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PRODUCT PREVIEW

Signal Name VSS CVDD VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS DVDD18 VSS CVDD VSS DVDD15 VSS VSS DDR3BD41 DDR3BD43 VSS DDR3BD44 DDR3BD47 DDR3BDQS5N DDR3BDQS5P SYSCLKOUT VSS SYSCLKN POR RSV012 VSS CVDD VSS CVDD VSS VDDAHV
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Table 4-5

Signal Name VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS DVDD18 VSS CVDD VSS DVDD15 DDR3BRZQ2 VSS DDR3BDQM6 DDR3BD51 DDR3BD50 VSS DDR3BD49 DDR3BD48 TSREFCLKN ALTCORECLKN SYSCLKP CORECLKSEL VSS CVDD VSS CVDD VSS VDDAHV VSS VDDAHV VSS VDDAHV
Table 4-5

Signal Name VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS DVDD18 VSS DVDD18 VSS CVDD VSS DVDD15 DDR3BD55 DDR3BD52 VSS DDR3BD53 DDR3BD54 DDR3BDQS6N DDR3BDQS6P TSREFCLKP ALTCORECLKP VSS RSV003 CVDD HYP1REFRES RSV020 VSS HYP0REFRES VSS AIFREFRES1 VSS VSS RSV025 AIFREFRES0 RSV024 VSS
Ball Number AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16
Ball Number AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AK39 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14
Ball Number AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AL37 AL38 AL39 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17
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AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11
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Signal Name VSS RSV069 VSS RIOREFRES VSS RSV021 SGMIIREFRES RSV023 PCIEREFRES DVDD18 RSV022 DVDD18 RADSYNC CVDD VSS VSS DDR3BD59 DDR3BD60 DDR3BD62 VSS DDR3BD61 DDR3BDQM7 TSRXCLKOUT0P VSS TSRXCLKOUT1P RSV002 VSS VSS VSS VSS VSS RSV019 VSS VSS VSS VSS VSS RSV068 VSS VSS RSV026 VSS
Table 4-5
Table 4-5

Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS PACLKSEL VSS USIMCLK DDR3BD58 DDR3BD56 VSS DDR3BD57 DDR3BD63 DDR3BDQS7P DDR3BDQS7N TSRXCLKOUT0N RP1CLKN TSRXCLKOUT1N VSS HYP1TXN1 HYP1TXP1 VSS HYP0TXN2 HYP0TXP2 VSS HYP0TXN0 HYP0TXP0 VSS AIFTXN3 AIFTXP3 VSS AIFTXN0 AIFTXP0 VSS VSS VSS RIOTXN2 RIOTXP2
Table 4-5

Signal Name VSS SGMII3TXN SGMII3TXP VSS VSS VSS VSS MDCLK USIMRST USIMIO PHYSYNC VD VCL VSS RSV006 RSV007 RP1FBP RP1CLKP VSS HYP1TXN2 HYP1TXP2 VSS HYP0TXN3 HYP0TXP3 VSS HYP0TXN1 HYP0TXP1 VSS AIFTXN4 AIFTXP4 VSS AIFTXN1 AIFTXP1 VSS RSV067 RSV066 VSS VSS RIOTXN1 RIOTXP1 VSS SGMII2TXN
Ball Number AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20
Ball Number AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23
Ball Number AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26
Terminals
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Signal Name SGMII2TXP VSS PCIETXN1 PCIETXP1 VSS MDIO VSS RSV073 VCNTL5 VCNTL2 VCNTL1 DDR3BCLKP DDR3BCLKN RP1FBN VSS HYP1TXN3 HYP1TXP3 VSS HYP1TXN0 HYP1TXP0 VSS HYP0CLKP HYP0CLKN VSS AIFTXN5 AIFTXP5 VSS AIFTXN2 AIFTXP2 VSS RSV063 RSV062 VSS RIOTXN3 RIOTXP3 VSS RIOTXN0 RIOTXP0 VSS SGMII1TXN SGMII1TXP VSS
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Table 4-5

Signal Name PCIETXN0 PCIETXP0 VSS RSV072 RSV009 VDT VSS VCLT VCNTL3 VCNTL0 VSS VSS VSS HYP1RXN2 HYP1RXP2 VSS HYP1RXN0 HYP1RXP0 VSS HYP0RXN1 HYP0RXP1 VSS AIFRXN4 AIFRXP4 VSS AIFRXN1 AIFRXP1 VSS RSV070 RSV071 VSS RIORXN1 RIORXP1 VSS SGMII2RXN SGMII2RXP VSS SGMII0TXN SGMII0TXP VSS PCIERXN0 PCIERXP0
Table 4-5

Signal Name VSS RSV008 VCNTL4T VCNTL0T VCNTL2T VCNTL4 VSS VSS VSS HYP1RXN3 HYP1RXP3 VSS HYP1RXN1 HYP1RXP1 VSS HYP0RXN2 HYP0RXP2 VSS AIFRXN5 AIFRXP5 VSS AIFRXN2 AIFRXP2 VSS RSV061 RSV060 VSS RIORXN3 RIORXP3 VSS RIORXN0 RIORXP0 VSS SGMII1RXN SGMII1RXP VSS PCIERXN1 PCIERXP1 VSS PASSCLKP PASSCLKN VSS
Ball Number AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34
Ball Number AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AU1 AU2 AU3 AU4 AU5 AU6 AU7 AU8 AU9 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32
Ball Number AU33 AU34 AU35 AU36 AU37 AU38 AU39 AV1 AV2 AV3 AV4 AV5 AV6 AV7 AV8 AV9 AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35
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AR35 AR36 AR37 AR38 AR39 AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29
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Signal Name VCNTL3T VCNTL1T VSS VSS (nopin) VSS VSS HYP1CLKP HYP1CLKN VSS HYP0RXN3 HYP0RXP3 VSS HYP0RXN0 HYP0RXP0 VSS AIFRXN3 AIFRXP3 VSS AIFRXN0 AIFRXP0 VSS RSV065 RSV064 VSS RIORXN2 RIORXP2 VSS SGMII3RXN SGMII3RXP VSS SGMII0RXN SGMII0RXP VSS PCIECLKP PCIECLKN VSS SRIOSGMIICLKP SRIOSGMIICLKN VCNTL5T VSS
Table 4-5
Table 4-5

Signal Name VSS (nopin)
Ball Number AV36 AV37 AV38 AV39 AW1 AW2 AW3 AW4 AW5 AW6 AW7 AW8 AW9 AW10 AW11 AW12 AW13 AW14 AW15 AW16 AW17 AW18 AW19 AW20 AW21 AW22 AW23 AW24 AW25 AW26 AW27 AW28 AW29 AW30 AW31 AW32 AW33 AW34 AW35 AW36 AW37
Ball Number AW38 AW39 End of Table 4-5
Terminals
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4.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. An external pullup/pulldown resistor needs to be used in the following situations: Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state. Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. For the device configuration pins (listed in Table 7-29), if they are both routed out and are not driven (in Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. Tips for choosing an external pullup/pulldown resistor: Consider the total amount of current that may pass through the pullup or pulldown resistor. Be sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels. Select a pullup/pulldown resistor with the largest possible value that still ensures that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). Remember to include tolerances when selecting the resistor value. For pullup resistors, also remember to include tolerances on the DVDD rail. For most systems: A 1-k resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. A 20-k resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for the TCI6636K2H device, see Section 8.3 Electrical Characteristics on page 263. To determine which pins on the device include internal pullup/pulldown resistors, see Table 4-3 Terminal Functions Power and Ground on page 59.
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SPRS835DAugust 2013
5 Memory, Interrupts, and EDMA for TCI6636K2H

5.1 Memory Map Summary
The following table shows the memory map address ranges of the device.
Table 5-1
Start 00 0000 0000 00 0004 0000 00 0080 0000 00 0090 0000 00 00E0 0000 00 00E0 8000 00 00F0 0000 00 00F0 8000 00 0100 0000 00 0101 0000 00 0110 0000 00 0111 0000 00 01C0 0000 00 01D0 0000 00 01D0 0080 00 01D0 8000 00 01D0 8080 00 01D1 0000 00 01D1 0080 00 01D1 8000 00 01D1 8080 00 01D2 0000 00 01D2 0080 00 01D2 8000 00 01D2 8080 00 01D3 0000 00 01D3 0080 00 01D3 8000 00 01D3 8080 00 01D4 0000 00 01D4 0080 00 01D4 8000 00 01D4 8080 00 01D5 0000 00 01D5 0080 00 01D5 8000 00 01D5 8080 00 01D6 0000
Device Memory Map Summary for TCI6636K2H (Part 1 of 12)

End 00 0003 FFFF 00 007F FFFF 00 008F FFFF 00 00DF FFFF 00 00E0 7FFF 00 00EF FFFF 00 00F0 7FFF 00 00FF FFFF 00 0100 FFFF 00 010F FFFF 00 0110 FFFF 00 01BF FFFF 00 01CF FFFF 00 01D0 007F 00 01D0 7FFF 00 01D0 807F 00 01D0 FFFF 00 01D1 007F 00 01D1 7FFF 00 01D1 807F 00 01D1 FFFF 00 01D2 007F 00 01D2 7FFF 00 01D2 807F 00 01D2 FFFF 00 01D3 007F 00 01D3 7FFF 00 01D3 807F 00 01D3 FFFF 00 01D4 007F 00 01D4 7FFF 00 01D4 807F 00 01D4 FFFF 00 01D5 007F 00 01D5 7FFF 00 01D5 807F 00 01D5 FFFF 00 01D6 007F Bytes 256K 8M-256K 1M 5M 32K 1M-32K 32K 1M-32K 64K 1M-64K 64K 11M-64K 1M 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 ARM View ARM ROM Reserved Reserved Reserved Reserved Reserved Reserved Reserved ARM AXI2VBUSM Master Registers Reserved ARM STM Stimulus Ports Reserved Reserved Tracer CFG0 Reserved Tracer CFG1 Reserved Tracer CFG2 Reserved Tracer CFG3 Reserved Tracer CFG4 Reserved Tracer CFG5 Reserved Tracer CFG6 Reserved Tracer CFG7 Reserved Tracer CFG8 Reserved Tracer CFG9 Reserved Tracer CFG10 Reserved Tracer CFG11 Reserved Tracer CFG12 DSP View Reserved Reserved L2 SRAM Reserved L1P SRAM Reserved L1D SRAM Reserved C66x CorePac registers C66x CorePac registers C66x CorePac registers C66x CorePac registers Reserved Tracer CFG0 Reserved Tracer CFG1 Reserved Tracer CFG2 Reserved Tracer CFG3 Reserved Tracer CFG4 Reserved Tracer CFG5 Reserved Tracer CFG6 Reserved Tracer CFG7 Reserved Tracer CFG8 Reserved Tracer CFG9 Reserved Tracer CFG10 Reserved Tracer CFG11 Reserved Tracer CFG12 SOC View ARM ROM Reserved L2 SRAM Reserved
Physical 40 bit Address
Reserved L1D SRAM Reserved C66x CorePac registers C66x CorePac registers C66x CorePac registers C66x CorePac registers Reserved Tracer CFG0 Reserved Tracer CFG1 Reserved Tracer CFG2 Reserved Tracer CFG3 Reserved Tracer CFG4 Reserved Tracer CFG5 Reserved Tracer CFG6 Reserved Tracer CFG7 Reserved Tracer CFG8 Reserved Tracer CFG9 Reserved Tracer CFG10 Reserved Tracer CFG11 Reserved Tracer CFG12
Memory, Interrupts, and EDMA for TCI6636K2H
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L1P SRAM

Start 00 01D6 0080 00 01D6 8000 00 01D6 8080 00 01D7 0000 00 01D7 0080 00 01D7 8000 00 01D7 8080 00 01D8 0000 00 01D8 0080 00 01D8 8000 00 01D8 8080 00 01D9 0000 00 01D9 0080 00 01D9 8000 00 01D9 8080 00 01DA 0000 00 01DA 0080 00 01DA 8000 00 01DA 8080 00 01DB 0000 00 01DB 0080 00 01DB 8000 00 01DB 8080 00 01DC 0000 00 01DC 0080 00 01DC 8000 00 01DC 8080 00 01DD 0000 00 01DD 0080 00 01DD 8000 00 01DD 8080 00 01DE 0000 00 01DE 0080 00 01DE 0400 00 01DD 0480 00 01DE 0800 00 01DE 0880 00 01DE 8000 00 01DE 8080 00 01E0 0000 00 01E4 0000 00 01E4 4000
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End 00 01D6 7FFF 00 01D6 807F 00 01D6 FFFF 00 01D7 007F 00 01D7 7FFF 00 01D7 807F 00 01D7 FFFF 00 01D8 007F 00 01D8 7FFF 00 01D8 807F 00 01D8 8FFF 00 01D9 007F 00 01D9 7FFF 00 01D9 807F 00 01D9 FFFF 00 01DA 007F 00 01DA 7FFF 00 01DA 807F 00 01DA FFFF 00 01DB 007F 00 01DB 7FFF 00 01DB 807F 00 01DB 8FFF 00 01DC 007F 00 01DC 7FFF 00 01DC 807F 00 01DC FFFF 00 01DD 007F 00 01DD 7FFF 00 01DD 807F 00 01DD FFFF 00 01DE 007F 00 01DE 03FF 00 01DE 047F 00 01DD 07FF 00 01DE 087F 00 01DE 7FFF 00 01DE 807F 00 01DF FFFF 00 01E3 FFFF 00 01E4 3FFF 00 01E7 FFFF Bytes 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 32K-128 128 1K-128 128 1K-128 128 30K-128 128 64K-128 256K 16K 240k ARM View Reserved Tracer CFG13 Reserved Tracer CFG14 Reserved Tracer CFG15 Reserved Tracer CFG16 Reserved Tracer CFG17 Reserved Tracer CFG18 Reserved Tracer CFG19 Reserved Tracer CFG20 Reserved Tracer CFG21 Reserved Tracer CFG22 Reserved Tracer CFG23 Reserved Tracer CFG24 Reserved Tracer CFG25 Reserved Tracer CFG26 Reserved Tracer CFG27 Reserved Tracer CFG28 Reserved Tracer CFG29 Reserved Tracer CFG30 Reserved Tracer CFG31 Reserved Reserved Reserved Reserved DSP View Reserved Tracer CFG13 Reserved Tracer CFG14 Reserved Tracer CFG15 Reserved Tracer CFG16 Reserved Tracer CFG17 Reserved Tracer CFG18 Reserved Tracer CFG19 Reserved Tracer CFG20 Reserved Tracer CFG21 Reserved Tracer CFG22 Reserved Tracer CFG23 Reserved Tracer CFG24 Reserved Tracer CFG25 Reserved Tracer CFG26 Reserved Tracer CFG27 Reserved Tracer CFG28 Reserved Tracer CFG29 Reserved Tracer CFG30 Reserved Tracer CFG31 Reserved Reserved Reserved Reserved SOC View Reserved Tracer CFG13 Reserved Tracer CFG14 Reserved Tracer CFG15 Reserved Tracer CFG16 Reserved Tracer CFG17 Reserved Tracer CFG18 Reserved Tracer CFG19 Reserved Tracer CFG20 Reserved Tracer CFG21 Reserved Tracer CFG22 Reserved Tracer CFG23 Reserved Tracer CFG24 Reserved Tracer CFG25 Reserved Tracer CFG26 Reserved Tracer CFG27 Reserved Tracer CFG28 Reserved Tracer CFG29 Reserved Tracer CFG30 Reserved Tracer CFG31 Reserved Reserved Reserved Reserved
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SPRS835DAugust 2013 Device Memory Map Summary for TCI6636K2H (Part 3 of 12)
End 00 01E8 3FFF 00 01EB FFFF 00 01EF FFFF 00 01F7 FFFF 00 01F8 FFFF 00 01F9 FFFF 00 01FB FFFF 00 01FD FFFF 00 01FF FFFF 00 020F FFFF Bytes 16K 240k 256K 512K 64K 64K 128K 128K 128K 1M ARM View ARM CorePac VBUSP Memory Mapped Registers Reserved Reserved AIF2 control RAC_1 - FEI control RAC_1 - BEI control RAC_1 - GCCP 0 control RAC_1 - GCCP 1 control Reserved Network Coprocessor (Packet Accelerator, 1-gigabit Ethernet switch subsystem and Security Accelerator) RAC_0 - FEI control RAC_0 - BEI control RAC_0 - GCCP 0 control RAC_0 - GCCP 1 control Reserved Reserved Reserved Reserved Reserved Reserved TCP3d_0 Reserved Reserved Reserved Reserved Reserved TCP3d_1 Reserved VCP2_0 configuration Reserved VCP2_1 configuration Reserved VCP2_2 configuration Reserved VCP2_3 configuration Reserved USIM configuration Reserved Reserved FFTC_0 configuration DSP View ARM CorePac VBUSP Memory Mapped Registers Reserved Reserved AIF2 control RAC_1 - FEI control RAC_1 - BEI control RAC_1 - GCCP 0 control RAC_1 - GCCP 1 control Reserved Network Coprocessor (Packet Accelerator, 1-gigabit Ethernet switch subsystem and Security Accelerator) RAC_0 - FEI control RAC_0 - BEI control RAC_0 - GCCP 0 control RAC_0 - GCCP 1 control Reserved Reserved Reserved Reserved Reserved Reserved TCP3d_0 Reserved Reserved Reserved Reserved Reserved TCP3d_1 Reserved VCP2_0 configuration Reserved VCP2_1 configuration Reserved VCP2_2 configuration Reserved VCP2_3 configuration Reserved USIM configuration Reserved Reserved FFTC_0 configuration SOC View ARM CorePac VBUSP Memory Mapped Registers Reserved Reserved AIF2 control RAC_1 - FEI control RAC_1 - BEI control RAC_1 - GCCP 0 control RAC_1 - GCCP 1 control Reserved Network Coprocessor (Packet Accelerator, 1-gigabit Ethernet switch subsystem and Security Accelerator) RAC_0 - FEI control RAC_0 - BEI control RAC_0 - GCCP 0 control RAC_0 - GCCP 1 control Reserved Reserved Reserved Reserved Reserved Reserved TCP3d_0 Reserved Reserved Reserved Reserved Reserved TCP3d_1 Reserved VCP2_0 configuration Reserved VCP2_1 configuration Reserved VCP2_2 configuration Reserved VCP2_3 configuration Reserved USIM configuration Reserved Reserved FFTC_0 configuration
Table 5-1
Start 00 01E8 0000 00 01E8 4000 00 01EC 0000 00 01F0 0000 00 01F8 0000 00 01F9 0000 00 01FA 0000 00 01FC 0000 00 01FE 0000 00 0200 0000
00 0210 0000 00 0211 0000 00 0212 0000 00 0214 0000 00 0216 0000 00 0218 0000 00 0218 8000 00 0219 0000 00 021A 0000 00 021B 0000 00 021C 0000 00 021C 0400 00 021C 4000 00 021C 4400 00 021C 6000 00 021C 6400 00 021C 8000 00 021C 8400 00 021D 0000 00 021D 0100 00 021D 4000 00 021D 4100 00 021D 8000 00 021D 8100 00 021D C000 00 021D C100 00 021D F000 00 021D F080 00 021E 0000 00 021F 0000
00 0210 FFFF 00 0211 FFFF 00 0213 FFFF 00 0215 FFFF 00 0217 FFFF 00 0218 7FFF 00 0218 FFFF 00 0219 FFFF 00 021A FFFF 00 021B FFFF 00 021C 03FF 00 021C 3FFF 00 021C 43FF 00 021C 5FFF 00 021C 63FF 00 021C 7FFF 00 021C 83FF 00 021C FFFF 00 021D 00FF 00 021D 3FFF 00 021D 40FF 00 021D 7FFF 00 021D 80FF 00 021D BFFF 00 021D C0FF 00 021D EFFF 00 021D F07F 00 021D FFFF 00 021E FFFF 00 021F 07FF
64K 64K 128K 128K 128K 32k 32k 64k 64K 64K 1K 15K 1K 7K 1K 7K 1K 31K 256 16K 256 16K 256 16K 256 12K-256 128 4K-128 64K 2K
85
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Start 00 021F 0800 00 021F 1000 00 021F 1800 00 021F 4000 00 021F 4800 00 021F 8000 00 021F 8800 00 021F C000 00 021F C800 00 0220 0000 00 0220 0080 00 0221 0000 00 0221 0080 00 0222 0000 00 0222 0080 00 0223 0000 00 0223 0080 00 0224 0000 00 0224 0080 00 0225 0000 00 0225 0080 00 0226 0000 00 0226 0080 00 0227 0000 00 0227 0080 00 0228 0000 00 0228 0080 00 0229 0000 00 0229 0080 00 022A 0000 00 022A 0080 00 022B 0000 00 022B 0080 00 022C 0000 00 022C 0080 00 022D 0000 00 022D 0080 00 022E 0000 00 022E 0080 00 022F 0000 00 022F 0080 00 022F 0100 00 022F 0180
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End 00 021F 0FFF 00 021F 17FF 00 021F 3FFF 00 021F 47FF 00 021F 7FFF 00 021F 87FF 00 021F BFFF 00 021F C7FF 00 021F FFFF 00 0220 007F 00 0220 FFFF 00 0221 007F 00 0221 FFFF 00 0222 007F 00 0222 FFFF 00 0223 007F 00 0223 FFFF 00 0224 007F 00 0224 FFFF 00 0225 007F 00 0225 FFFF 00 0226 007F 00 0226 FFFF 00 0227 007F 00 0227 FFFF 00 0228 007F 00 0228 FFFF 00 0229 007F 00 0229 FFFF 00 022A 007F 00 022A FFFF 00 022B 007F 00 022B FFFF 00 022C 007F 00 022C FFFF 00 022D 007F 00 022D FFFF 00 022E 007F 00 022E FFFF 00 022F 007F 00 022F 00FF 00 022F 017F 00 022F 01FF Bytes 2K 2K 10K 2K 14K 2K 14K 2K 14K 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 64K-128 128 128 128 128 ARM View Reserved Reserved Reserved FFTC_1 configuration Reserved FFTC_2 configuration Reserved FFTC_3 configuration Reserved Timer0 Reserved Timer1 Reserved Timer2 Reserved Timer3 Reserved Timer4 Reserved Timer5 Reserved Timer6 Reserved Timer7 Reserved Timer 8 Reserved Timer 9 Reserved Timer 10 Reserved Timer 11 Reserved Timer 12 Reserved Timer 13 Reserved Timer 14 Reserved Timer 15 Timer 16 Timer 17 Timer 18 DSP View Reserved Reserved Reserved FFTC_1 configuration Reserved FFTC_2 configuration Reserved FFTC_3 configuration Reserved Timer0 Reserved Timer1 Reserved Timer2 Reserved Timer3 Reserved Timer4 Reserved Timer5 Reserved Timer6 Reserved Timer7 Reserved Timer 8 Reserved Timer 9 Reserved Timer 10 Reserved Timer 11 Reserved Timer 12 Reserved Timer 13 Reserved Timer 14 Reserved Timer 15 Timer 16 Timer 17 Timer 18 SOC View Reserved Reserved Reserved FFTC_1 configuration Reserved FFTC_2 configuration Reserved FFTC_3 configuration Reserved Timer0 Reserved Timer1 Reserved Timer2 Reserved Timer3 Reserved Timer4 Reserved Timer5 Reserved Timer6 Reserved Timer7 Reserved Timer 8 Reserved Timer 9 Reserved Timer 10 Reserved Timer 11 Reserved Timer 12 Reserved Timer 13 Reserved Timer 14 Reserved Timer 15 Timer 16 Timer 17 Timer 18
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86

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End 00 022F 027F 00 0230 FFFF 00 0231 01FF 00 0231 9FFF 00 0231 BFFF 00 0231 DFFF 00 0231 FFFF 00 0232 3FFF 00 0232 5FFF 00 0232 7FFF 00 0232 8FFF 00 0232 9FFF 00 0232 BFFF 00 0232 DFFF 00 0232 EFFF 00 0232 FFFF 00 0233 03FF 00 0233 07FF 00 0233 FFFF 00 0234 00FF 00 0234 3FFF 00 0234 40FF 00 0234 7FFF 00 0234 80FF 00 0234 BFFF 00 0234 C0FF 00 0234 FFFF 00 0235 0FFF 00 0235 FFFF 00 0236 03FF 00 0236 7FFF 00 0236 83FF 00 0236 FFFF 00 0237 03FF 00 0237 7FFF 00 0237 83FF 00 0237 FFFF 00 0238 03FF 00 0238 83FF Bytes 128 64K 512 40K-512 8K 8K 8K 16K 8K 8K 4K 4K 8K 8K 4K 4K 1K 1K 62K 256 16K 256 16K 256 16K 256 16K 4K 64K-4K 1K 31K 1K 31K 1K 31K 1K 31K 1K 1K ARM View Timer 19 Reserved PLL Controller Reserved HyperLink0 SerDes Config HyperLink1 SerDes Config Reserved PCIE SerDes Config AIF2 SerDes B4 Config AIF2 SerDes B8 Config DDRB PHY Config DDRA PHY Config SGMII SerDes Config SRIO SerDes Config Reserved Reserved SmartReflex0 SmartReflex1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power sleep controller (PSC) Reserved Memory protection unit (MPU) 0 Reserved Memory protection unit (MPU) 1 Reserved Memory protection unit (MPU) 2 Reserved Memory protection unit (MPU) 3 Reserved Memory protection unit (MPU) 4 Memory protection unit (MPU) 5 DSP View Timer 19 Reserved PLL Controller Reserved HyperLink0 SerDes Config HyperLink1 SerDes Config Reserved PCIE SerDes Config AIF2 SerDes B4 Config AIF2 SerDes B8 Config DDRB PHY Config DDRA PHY Config SGMII SerDes Config SRIO SerDes Config Reserved Reserved SmartReflex0 SmartReflex1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power sleep controller (PSC) Reserved Memory protection unit (MPU) 0 Reserved Memory protection unit (MPU) 1 Reserved Memory protection unit (MPU) 2 Reserved Memory protection unit (MPU) 3 Reserved Memory protection unit (MPU) 4 Memory protection unit (MPU) 5 SOC View Timer 19 Reserved PLL Controller Reserved HyperLink0 SerDes Config HyperLink1 SerDes Config Reserved PCIE SerDes Config
Table 5-1
Start 00 022F 0200 00 0230 0000 00 0231 0000 00 0231 0200 00 0231 A000 00 0231 C000 00 0231 E000 00 0232 0000 00 0232 4000 00 0232 6000 00 0232 8000 00 0232 9000 00 0232 A000 00 0232 C000 00 0232 E000 00 0232 F000 00 0233 0000 00 0233 0400 00 0233 0400 00 0234 0000 00 0234 0100 00 0234 4000 00 0234 4100 00 0234 8000 00 0234 8100 00 0234 C000 00 0234 C100 00 0235 0000 00 0235 1000 00 0236 0000 00 0236 0400 00 0236 8000 00 0236 8400 00 0237 0000 00 0237 0400 00 0237 8000 00 0237 8400 00 0238 0000 00 0238 8000
AIF2 SerDes B8 Config DDRB PHY Config DDRA PHY Config SGMII SerDes Config SRIO SerDes Config Reserved Reserved SmartReflex0 SmartReflex1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power sleep controller (PSC) Reserved Memory protection unit (MPU) 0 Reserved Memory protection unit (MPU) 1 Reserved Memory protection unit (MPU) 2 Reserved Memory protection unit (MPU) 3 Reserved Memory protection unit (MPU) 4 Memory protection unit (MPU) 5
87
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AIF2 SerDes B4 Config

Start 00 0238 8400 00 0238 8800 00 0238 8C00 00 0238 9000 00 0238 9400 00 0238 9800 00 0238 9C00 00 0238 A000 00 0238 A400 00 0238 A800 00 0240 0000 00 0244 0000 00 0244 4000 00 0245 0000 00 0245 4000 00 0246 0000 00 0246 4000 00 0247 0000 00 0247 4000 00 0248 0000 00 0248 4000 00 0249 0000 00 0249 4000 00 024A 0000 00 024A 4000 00 024B 0000 00 024B 4000 00 024C 0000 00 024C 0200 00 024C 0400 00 024C 0800 00 024D 0000 00 0250 0000 00 0250 0080 00 0250 8000 00 0251 0000 00 0252 0000
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End 00 0238 87FF 00 0238 8BFF 00 0238 8FFF 00 0238 93FF 00 0238 97FF 00 0238 9BFF 00 0238 9FFF 00 0238 A3FF 00 0238 A7FF 00 023F FFFF 00 0243 FFFF 00 0244 3FFF 00 0244 FFFF 00 0245 3FFF 00 0245 FFFF 00 0246 3FFF 00 0246 FFFF 00 0247 3FFF 00 0247 FFFF 00 0248 3FFF 00 0248 FFFF 00 0249 3FFF 00 0249 FFFF 00 024A 3FFF 00 024A FFFF 00 024B 3FFF 00 024B FFFF 00 024C 01FF 00 024C 03FF 00 024C 07FF 00 024C FFFF 00 024F FFFF 00 0250 007F 00 0250 7FFF 00 0250 FFFF 00 0251 FFFF 00 0252 03FF Bytes 1K 1K 1K 1K 1K 1K 1K 1K 1K 471K 256K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 512 1K-512 1K 62K 192K 128 32K-128 32K 64K 1K ARM View Memory protection unit (MPU) 6 Memory protection unit (MPU) 7 Memory protection unit (MPU) 8 Memory protection unit (MPU) 9 DSP View Memory protection unit (MPU) 6 Memory protection unit (MPU) 7 Memory protection unit (MPU) 8 Memory protection unit (MPU) 9 SOC View Memory protection unit (MPU) 6 Memory protection unit (MPU) 7 Memory protection unit (MPU) 8 Memory protection unit (MPU) 9 Memory protection unit (MPU) 10 Memory protection unit (MPU) 11 Memory protection unit (MPU) 12 Memory protection unit (MPU) 13 Memory protection unit (MPU) 14 Reserved Reserved DSP trace formatter 0 Reserved DSP trace formatter 1 Reserved DSP trace formatter 2 Reserved DSP trace formatter 3 Reserved DSP trace formatter 4 Reserved DSP trace formatter 5 Reserved DSP trace formatter 6 Reserved DSP trace formatter 7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Memory protection unit (MPU) 10 Memory protection unit (MPU) 10 Memory protection unit (MPU) 11 Memory protection unit (MPU) 11 Memory protection unit (MPU) 12 Memory protection unit (MPU) 12 Memory protection unit (MPU) 13 Memory protection unit (MPU) 13 Memory protection unit (MPU) 14 Memory protection unit (MPU) 14 Reserved Reserved DSP trace formatter 0 Reserved DSP trace formatter 1 Reserved DSP trace formatter 2 Reserved DSP trace formatter 3 Reserved DSP trace formatter 4 Reserved DSP trace formatter 5 Reserved DSP trace formatter 6 Reserved DSP trace formatter 7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DSP trace formatter 0 Reserved DSP trace formatter 1 Reserved DSP trace formatter 2 Reserved DSP trace formatter 3 Reserved DSP trace formatter 4 Reserved DSP trace formatter 5 Reserved DSP trace formatter 6 Reserved DSP trace formatter 7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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End 00 0252 FFFF 00 0253 007F 00 0253 03FF 00 0253 047F 00 0253 07FF 00 0253 087F 00 0253 0BFF 00 0253 0C3F 00 0253 FFFF 00 0253 103F 00 0253 FFFF 00 0255 FFFF 00 0257 FFFF 00 025F FFFF 00 0260 1FFF 00 0260 3FFF 00 0260 5FFF 00 0260 7FFF 00 0260 9FFF 00 0260 BEFF 00 0260 BFFF 00 0261 BFFF 00 0261 FFFF 00 0262 0FFF 00 0262 FFFF 00 0263 FFFF 00 0264 07FF 00 0264 FFFF 00 0267 FFFF 00 0268 FFFF 00 0270 7FFF 00 0270 FFFF 00 0271 FFFF 00 0272 7FFF 00 0272 FFFF 00 0273 FFFF 00 0274 7FFF Bytes 64K-1K 128 1K-128 128 1K-128 128 1K-128 64 1K-64 64 60K-64 128K 128K 512K 8K 8K 8K 8K 8K 8K-256 256 64K 16K 4K 60K 64K 2K 62K 192K 512K 32K 32K 64K 32K 32K 64K 32K ARM View Reserved I2C0 Reserved I C1 Reserved I C2 Reserved UART0 Reserved UART1 Reserved BCP ARM CorePac INTC (GIC400) Memory Mapped Registers TAC Secondary interrupt controller (INTC) 0 Reserved Secondary interrupt controller (INTC) 1 Reserved Secondary interrupt controller (INTC) 2 Reserved GPIO Config Reserved Reserved BOOTCFG chip-level registers Reserved USB PHY Config Semaphore Config Reserved Reserved USB MMR Config EDMA channel controller (TPCC) 0 EDMA channel controller (TPCC) 4 Reserved EDMA channel controller (TPCC) 1 EDMA channel controller (TPCC) 3 Reserved EDMA channel controller (TPCC) 2
2 2
Table 5-1
Start 00 0252 0400 00 0253 0000 00 0253 0080 00 0253 0400 00 0253 0480 00 0253 0800 00 0253 0880 00 0253 0C00 00 0253 0C40 00 0253 1000 00 0253 1040 00 0254 0000 00 0256 0000 00 0258 0000 00 0260 0000 00 0260 2000 00 0260 4000 00 0260 6000 00 0260 8000 00 0260 A000 00 0260 BF00 00 0260 C000 00 0261 C000 00 0262 0000 00 0262 1000 00 0263 0000 00 0264 0000 00 0264 0800 00 0265 0000 00 0268 0000 00 0270 0000 00 0270 8000 00 0271 0000 00 0272 0000 00 0272 8000 00 0273 0000 00 0274 0000
Physical 40 bit Address DSP View Reserved I2C0 Reserved I C1 Reserved I C2 Reserved UART0 Reserved UART1 Reserved BCP ARM CorePac INTC (GIC400) Memory Mapped Registers TAC Secondary interrupt controller (INTC) 0 Reserved Secondary interrupt controller (INTC) 1 Reserved Secondary interrupt controller (INTC) 2 Reserved GPIO Config Reserved Reserved BOOTCFG chip-level registers Reserved USB PHY Config Semaphore Config Reserved Reserved USB MMR Config
2 2
SOC View Reserved I2C0 Reserved I C1 Reserved I C2 Reserved UART0

2 2
UART1 Reserved BCP ARM CorePac INTC (GIC400) Memory Mapped Registers TAC Secondary interrupt controller (INTC) 0 Reserved Secondary interrupt controller (INTC) 1 Reserved Secondary interrupt controller (INTC) 2 Reserved GPIO Config Reserved Reserved BOOTCFG chip-level registers Reserved USB PHY Config Semaphore Config Reserved Reserved USB MMR Config
EDMA channel controller (TPCC) EDMA channel controller 0 (TPCC) 0 EDMA channel controller (TPCC) EDMA channel controller 4 (TPCC) 4 Reserved Reserved
EDMA channel controller (TPCC) EDMA channel controller 1 (TPCC) 1 EDMA channel controller (TPCC) EDMA channel controller 3 (TPCC) 3 Reserved Reserved
EDMA channel controller (TPCC) EDMA channel controller 2 (TPCC) 2
89
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Reserved

Start 00 0274 8000 00 0276 0000 00 0276 0400 00 0276 8000 00 0276 8400 00 0277 0000 00 0277 0400
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End 00 0275 FFFF 00 0276 03FF 00 0276 7FFF 00 0276 83FF 00 0276 FFFF 00 0277 03FF 00 0277 7FFF 00 0277 83FF 00 0277 FFFF 00 0278 03FF 00 0278 7FFF 00 0278 83FF 00 0278 FFFF 00 0279 03FF 00 0279 7FFF 00 0279 83FF 00 0279 FFFF 00 027A 03FF 00 027A 7FFF 00 027A 83FF 00 027A FFFF 00 027B 03FF 00 027B 7FFF 00 027B 83FF 00 027B 87FF 00 027B 8BFF 00 027B FFFF 00 027C 03FF 00 027C FFFF 00 027D 3FFF 00 027D 7FFF 00 027D FFFF Bytes 96K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 31K 1K 1K 1K 29K 1K 63K 16K 16K 32K ARM View Reserved EDMA TPCC0 transfer controller (TPTC) 0 Reserved EDMA TPCC0 transfer controller (TPTC) 1 Reserved EDMA TPCC1 transfer controller (TPTC) 0 Reserved EDMA TPCC1 transfer controller (TPTC) 1 Reserved EDMA TPCC1 transfer controller (TPTC) 2 Reserved EDMA TPCC1 transfer controller (TPTC) 3 Reserved EDMA TPCC2 transfer controller (TPTC) 0 Reserved EDMA TPCC2 transfer controller (TPTC) 1 Reserved EDMA TPCC2 transfer controller (TPTC) 2 Reserved EDMA TPCC2 transfer controller (TPTC) 3 Reserved EDMA TPCC3 transfer controller (TPTC) 0 Reserved EDMA TPCC3 transfer controller (TPTC) 1 EDMA TPCC4 transfer controller (TPTC) 0 EEDMA TPCC4 transfer controller (TPTC) 1 Reserved BCR config Reserved DSP View Reserved SOC View Reserved
EDMA TPCC0 transfer controller EDMA TPCC0 transfer controller (TPTC) 0 (TPTC) 0 Reserved Reserved
PRODUCT PREVIEW
00 0277 8000 00 0278 0400 00 0278 0000 00 0278 0400 00 0278 8000 00 0278 8400 00 0279 0000 00 0279 0400 00 0279 8000 00 0279 8400 00 027A 0000 00 027A 0400 00 027A 8000 00 027A 8400 00 027B 0000 00 027B 0400 00 027B 8000 00 027B 8400 00 027B 8800 00 027B 8C00 00 027C 0000 00 027C 0400 00 027D 0000 00 027D 4000 00 027D 8000
EDMA TPCC3 transfer controller EDMA TPCC3 transfer controller (TPTC) 1 (TPTC) 1 EDMA TPCC4 transfer controller EDMA TPCC4 transfer controller (TPTC) 0 (TPTC) 0 EEDMA TPCC4 transfer controller (TPTC) 1 Reserved BCR config Reserved EEDMA TPCC4 transfer controller (TPTC) 1 Reserved BCR config Reserved TI embedded trace buffer (TETB) - CorePac0
TI embedded trace buffer (TETB) - TI embedded trace buffer CorePac0 (TETB) - CorePac0 TBR ARM CorePac - Trace buffer ARM CorePac Reserved
TBR ARM CorePac - Trace buffer TBR ARM CorePac - Trace buffer - ARM CorePac - ARM CorePac Reserved Reserved
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End 00 027E 3FFF 00 027E FFFF 00 027F 3FFF 00 027F FFFF 00 0280 3FFF 00 0280 FFFF 00 0281 3FFF 00 0281 FFFF 00 0282 3FFF 00 0282 FFFF 00 0283 3FFF 00 0283 FFFF 00 0284 3FFF 00 0284 FFFF 00 0285 7FFF 00 0285 FFFF 00 028F FFFF 00 0293 FFFF 00 029F FFFF 00 02AF FFFF 00 02BF FFFF 00 02C0 FFFF 00 02C1 FFFF 00 02C3 FFFF 00 02C5 FFFF 00 02C7 FFFF 00 02C8 FFFF 00 02C9 FFFF 00 02CB FFFF 00 02CD FFFF 00 02EF FFFF 00 02FF FFFF 00 030F FFFF 00 07FF FFFF 00 0801 FFFF 00 0BBF FFFF 00 0BCF FFFF Bytes 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 16K 48K 32K 32K 640K 256K 768K 1M 1M 64K 64K 128K 128K 128K 64K 64K 128K 128K 15M-896K 1M 1M 79M 128K 60M-128K 1M ARM View DSP View SOC View TI embedded trace buffer (TETB) - CorePac1 Reserved TI embedded trace buffer (TETB) - CorePac2 Reserved TI embedded trace buffer (TETB) - CorePac3 Reserved
Table 5-1
Start 00 027E 0000 00 027E 4000 00 027F 0000 00 027F 4000 00 0280 0000 00 0280 4000 00 0281 0000 00 0281 4000 00 0282 0000 00 0282 4000 00 0283 0000 00 0283 4000 00 0284 0000 00 0284 4000 00 0285 0000 00 0285 8000 00 0286 0000 00 0290 0000 00 0294 0000 00 02A0 0000 00 02B0 0000 00 02C0 0000 00 02C1 0000 00 02C2 0000 00 02C4 0000 00 02C6 0000 00 02C8 0000 00 02C9 0000 00 02CA 0000 00 02CC 0000 00 02CE 0000 00 02F0 0000 00 0300 0000 00 0310 0000 00 0800 0000 00 0802 0000 00 0BC0 0000
TI embedded trace buffer (TETB) - TI embedded trace buffer CorePac1 (TETB) - CorePac1 Reserved Reserved
Reserved
Reserved
Reserved TI embedded trace buffer (TETB) - CorePac5 Reserved TI embedded trace buffer (TETB) - CorePac6 Reserved TI embedded trace buffer (TETB) - CorePac7 Reserved TBR_SYS-Trace Buffer -System Reserved Reserved Serial RapidIO configuration (SRIO) Reserved Navigator configuration Navigator linking RAM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Debug_SS Configuration Reserved Extended memory controller (XMC) configuration Reserved Multicore shared memory controller (MSMC) config
TI embedded trace buffer (TETB) - TI embedded trace buffer CorePac7 (TETB) - CorePac7 Reserved TBR_SYS-Trace Buffer -System Reserved Reserved Serial RapidIO configuration (SRIO) Reserved Navigator configuration Navigator linking RAM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Debug_SS Configuration Reserved Extended memory controller (XMC) configuration Reserved Multicore shared memory controller (MSMC) config Reserved TBR_SYS-Trace Buffer -System Reserved Reserved Serial RapidIO configuration (SRIO) Reserved Navigator configuration Navigator linking RAM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Debug_SS Configuration Reserved Extended memory controller (XMC) configuration Reserved Multicore shared memory controller (MSMC) config
91
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TI embedded trace buffer (TETB) - TI embedded trace buffer CorePac4 (TETB) - CorePac4
TI embedded trace buffer (TETB) - CorePac4

Start 00 0BD0 0000 00 0C00 0000 00 0C60 0000 00 1000 0000 00 1080 0000 00 1090 0000 00 10E0 0000 00 10E0 8000
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End 00 0BFF FFFF 00 0C5F FFFF 00 0FFF FFFF 00 107F FFFF 00 108F FFFF 00 10DF FFFF 00 10E0 7FFF 00 10EF FFFF 00 10F0 7FFF 00 117F FFFF 00 118F FFFF 00 11DF FFFF 00 11E0 7FFF 00 11EF FFFF 00 11F0 7FFF 00 127F FFFF 00 128F FFFF 00 12DF FFFF 00 12E0 7FFF 00 12EF FFFF 00 12F0 7FFF 00 137F FFFF 00 1388 FFFF 00 13DF FFFF 00 13E0 7FFF 00 13EF FFFF 00 13F0 7FFF 00 147F FFFF 00 148F FFFF 00 14DF FFFF 00 14E0 7FFF 00 14EF FFFF 00 14F0 7FFF 00 157F FFFF 00 158F FFFF 00 15DF FFFF 00 15E0 7FFF 00 15EF FFFF 00 15F0 7FFF 00 167F FFFF 00 168F FFFF 00 16DF FFFF Bytes 3M 6M 58M 8M 1M 5M 32K 1M-32K 32K 9M-32K 1M 5M 32K 1M-32K 32K 9M-32K 1M 5M 32K 1M-32K 32K 9M-32K 1M 5M 32K 1M-32K 32K 9M-32K 1M 5M 32K 1M-32K 32K 9M-32K 1M 5M 32K 1M-32K 32K 9M-32K 1M 5M ARM View Reserved Multicore shared memory (MSM) Reserved Reserved CorePac0 L2 SRAM Reserved CorePac0 L1P SRAM Reserved CorePac0 L1D SRAM Reserved CorePac1 L2 SRAM Reserved CorePac1 L1P SRAM Reserved CorePac1 L1D SRAM Reserved CorePac2 L2 SRAM Reserved CorePac2 L1P SRAM Reserved CorePac2 L1D SRAM Reserved CorePac3 L2 SRAM Reserved CorePac3 L1P SRAM Reserved CorePac3 L1D SRAM Reserved CorePac4 L2 SRAM Reserved CorePac4 L1P SRAM Reserved CorePac4 L1D SRAM Reserved CorePac5 L2 SRAM Reserved CorePac5 L1P SRAM Reserved CorePac5 L1D SRAM Reserved CorePac6 L2 SRAM Reserved DSP View Reserved Multicore shared memory (MSM) Reserved Reserved CorePac0 L2 SRAM Reserved CorePac0 L1P SRAM Reserved CorePac0 L1D SRAM Reserved CorePac1 L2 SRAM Reserved CorePac1 L1P SRAM Reserved CorePac1 L1D SRAM Reserved CorePac2 L2 SRAM Reserved CorePac2 L1P SRAM Reserved CorePac2 L1D SRAM Reserved CorePac3 L2 SRAM Reserved CorePac3 L1P SRAM Reserved CorePac3 L1D SRAM Reserved CorePac4 L2 SRAM Reserved CorePac4 L1P SRAM Reserved CorePac4 L1D SRAM Reserved CorePac5 L2 SRAM Reserved CorePac5 L1P SRAM Reserved CorePac5 L1D SRAM Reserved CorePac6 L2 SRAM Reserved SOC View Reserved Multicore shared memory (MSM) Reserved Reserved CorePac0 L2 SRAM Reserved CorePac0 L1P SRAM Reserved CorePac0 L1D SRAM Reserved CorePac1 L2 SRAM Reserved CorePac1 L1P SRAM Reserved CorePac1 L1D SRAM Reserved CorePac2 L2 SRAM Reserved CorePac2 L1P SRAM Reserved CorePac2 L1D SRAM Reserved CorePac3 L2 SRAM Reserved CorePac3 L1P SRAM Reserved CorePac3 L1D SRAM Reserved CorePac4 L2 SRAM Reserved CorePac4 L1P SRAM Reserved CorePac4 L1D SRAM Reserved CorePac5 L2 SRAM Reserved CorePac5 L1P SRAM Reserved CorePac5 L1D SRAM Reserved CorePac6 L2 SRAM Reserved
PRODUCT PREVIEW
00 10F0 0000 00 10F0 8000 00 1180 0000 00 1190 0000 00 11E0 0000 00 11E0 8000 00 11F0 0000 00 11F0 8000 00 1280 0000 00 1290 0000 00 12E0 0000 00 12E0 8000 00 12F0 0000 00 12F0 8000 00 1380 0000 00 1390 0000 00 13E0 0000 00 13E0 8000 00 13F0 0000 00 13F0 8000 00 1480 0000 00 1490 0000 00 14E0 0000 00 14E0 8000 00 14F0 0000 00 14F0 8000 00 1580 0000 00 1590 0000 00 15E0 0000 00 15E0 8000 00 15F0 0000 00 15F0 8000 00 1680 0000 00 1690 0000
92

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End 00 16E0 7FFF 00 16EF FFFF 00 16F0 7FFF 00 177F FFFF 00 178F FFFF 00 17DF FFFF 00 17E0 7FFF 00 17EF FFFF 00 17F0 7FFF 00 1FFF FFFF 00 200F FFFF 00 201F FFFF 00 205F FFFF 00 206F FFFF 00 207F FFFF 00 208F FFFF 00 209F FFFF 00 20A3 FFFF 00 20A4 FFFF 00 20AF FFFF 00 20B3 FFFF 00 20BE FFFF 00 20BF 01FF 00 20FF FFFF 00 2100 03FF 00 2100 05FF 00 2100 07FF 00 2100 09FF 00 2100 0AFF 00 2100 FFFF 00 2101 01FF 00 2101 07FF 00 2101 09FF 00 2101 0FFF 00 2101 FFFF 00 2103 FFFF 00 217F FFFF 00 2140 00FF 00 2140 01FF 00 217F FFFF 00 2180 7FFF 00 21BF FFFF Bytes 32K 1M-32K 32K 9M-32K 1M 5M 32K 1M-32K 32K 129M-32K 1M 1M 4M 1M 1M 1M 1M 256K 64K 704K 256K 704K 64K 4M 1K 512 512 512 256 62K-768 512 2K-512 512 2K-512 60K 128K 4M-256K 256 256 4M-512 32K 4M-32K ARM View CorePac6 L1P SRAM Reserved CorePac6 L1D SRAM Reserved CorePac7 L2 SRAM Reserved CorePac7 L1P SRAM Reserved CorePac7 L1D SRAM Reserved System trace manager (STM) configuration Reserved Reserved TCP3d_1 data Reserved TCP3d_0 data Reserved Reserved Reserved Reserved Boot ROM Reserved Reserved Reserved Reserved SPI0 SPI1 SPI2 EMIF Config Reserved DDR3A EMIF Config Reserved Reserved Reserved Reserved DDR3B EMIF configuration Reserved HyperLink0 config HyperLink1 config Reserved PCIe config Reserved DSP View CorePac6 L1P SRAM Reserved CorePac6 L1D SRAM Reserved CorePac7 L2 SRAM Reserved CorePac7 L1P SRAM Reserved CorePac7 L1D SRAM Reserved System trace manager (STM) configuration Reserved Reserved TCP3d_1 data Reserved TCP3d_0 data Reserved Reserved Reserved Reserved Boot ROM Reserved Reserved Reserved Reserved SPI0 SPI1 SPI2 EMIF Config Reserved Reserved Reserved Reserved Reserved Reserved DDR3B EMIF configuration Reserved HyperLink0 config HyperLink1 config Reserved PCIe config Reserved SOC View CorePac6 L1P SRAM Reserved CorePac6 L1D SRAM Reserved CorePac7 L2 SRAM Reserved CorePac7 L1P SRAM Reserved
Table 5-1
Start 00 16E0 0000 00 16E0 8000 00 16F0 0000 00 16F0 8000 00 1780 0000 00 1790 0000 00 17E0 0000 00 17E0 8000 00 17F0 0000 00 17F0 8000 00 2000 0000 00 2010 0000 00 2020 0000 00 2060 0000 00 2070 0000 00 2080 0000 00 2090 0000 00 20A0 0000 00 20A4 0000 00 20A5 0000 00 20B0 0000 00 20B4 0000 00 20BF 0000 00 20C0 0000 00 2100 0000 00 2100 0400 00 2100 0600 00 2100 0800 00 2100 0A00 00 2100 0B00 00 2101 0000 00 2101 0200 00 2101 0800 00 2101 0A00 00 2101 1000 00 2102 0000 00 2104 0000 00 2140 0000 00 2140 0100 00 2140 0400 00 2180 0000 00 2180 8000
Reserved System trace manager (STM) configuration Reserved Reserved TCP3d_1 data Reserved TCP3d_0 data Reserved Reserved Reserved Reserved Boot ROM Reserved Reserved Reserved Reserved SPI0 SPI1 SPI2 EMIF Config Reserved DDR3A EMIF Config Reserved Reserved Reserved Reserved DDR3B EMIF configuration Reserved HyperLink0 config HyperLink1 config Reserved PCIe config Reserved
93
PRODUCT PREVIEW
CorePac7 L1D SRAM

Start 00 21C0 0000 00 2200 0000 00 22A0 0000 00 22A1 0000 00 22B0 0000 00 22B1 0000 00 22C0 0000 00 22C1 0000 00 22D0 0000 00 22D1 0000 00 22E0 0000 00 22E1 0000 00 22F0 0000 00 22F1 0000 00 2300 0000 00 2301 0000 00 2310 0000 00 2311 0000 00 2320 0000 00 2325 0000 00 23A0 0000 00 23C0 0000 00 2400 0000 00 2800 0000 00 3000 0000 00 3400 0000 00 3800 0000 00 3C00 0000 00 4000 0000 00 5000 0000 00 6000 0000 00 8000 0000 01 0000 0000 01 2101 0000 01 2101 0200 08 0000 0000 0A 0000 0000 End of Table 5-1
1 2 3 4 No IO coherency supported for this region. (See ARM CorePac User Guide referenced in 1.10 Related Documentation from Texas Instruments on page 21) This region is mapped to DDR3B. It is aliased of 00 8000 0000 to 00 9FFF FFFF (the first 512MB of DDR3B) if the state of DDR3A_REMAP_EN pin at boot time is 0. This region is aliased of 00 8000 0000 to 00 9FFF FFFF (the first 512MB of DDR3B). This region is mapped to DDR3A or DDR3B depending on the state of DDR3A_REMAP_EN pin at boot time. If the pin is 1, this region is mapped to the first 2GB of DDR3A which is aliased of 08 0000 0000 to 08 7FFF FFFF. If the pin is 0, this region is mapped as 2GB of DDR3B. 5 MPAX from SES port extends the address to this region. 6 This region is aliased to 00 2101 0000-00 2101 01FF. 7 Access to 40-bit address requires XMC MPAX programmation.
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End 00 21FF FFFF 00 229F FFFF 00 22A0 FFFF 00 22AF FFFF 00 22B0 FFFF 00 22BF FFFF 00 22C0 FFFF 00 22CF FFFF 00 22D0 FFFF 00 22DF FFFF 00 22E0 FFFF 00 22EF FFFF 00 22F0 FFFF 00 22FF FFFF 00 2300 FFFF 00 230F FFFF 00 2310 FFFF 00 231F FFFF 00 2324 FFFF 00 239F FFFF 00 23BF FFFF 00 23FF FFFF 00 27FF FFFF 00 2FFF FFFF 00 33FF FFFF 00 37FF FFFF 00 3BFF FFFF 00 3FFF FFFF 00 4FFF FFFF 00 5FFF FFFF 00 7FFF FFFF 00 FFFF FFFF 01 2100 FFFF 01 2101 01FF 07 FFFF FFFF 09 FFFF FFFF FF FFFF FFFF Bytes 4M 10M 64K 1M-64K 64K 1M-64K 64K 1M-64K 64K 1M-64K 64K 1M-64K 64K 1M-64K 64K 1M-64K 64K 1M-64K 384K 8M-384K 2M 4M 64M 128M 64M 64M 64M 64M 256M 256M 512M 2G 528M+64K 512 32G-512 8G 984G ARM View Reserved Reserved VCP2_0 Data Reserved VCP2_1 Data Reserved VCP2_2 Data Reserved VCP2_3 Data Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TAC BEI Reserved Navigator BCR-RAC data Reserved HyperLink1 data EMIF16 CE0 EMIF16 CE1 EMIF16 CE2 EMIF16 CE3 HyperLink0 data PCIe data DDR3B data (1)
(2) (1) (4)
Physical 40 bit Address DSP View Reserved Reserved VCP2_0 Data Reserved VCP2_1 Data Reserved VCP2_2 Data Reserved VCP2_3 Data Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TAC BEI Reserved Navigator BCR-RAC data Reserved HyperLink1 data EMIF16 CE0 EMIF16 CE1 EMIF16 CE2 EMIF16 CE3 HyperLink0 data PCIe data DDR3B data DDR3B data Reserved DDR3A EMIF configuration (7) Reserved DDR3A data Reserved
(7) (3)
SOC View Reserved Reserved VCP2_0 Data Reserved VCP2_1 Data Reserved VCP2_2 Data Reserved VCP2_3 Data Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TAC BEI Reserved Navigator BCR-RAC data Reserved HyperLink1 data EMIF16 CE0 EMIF16 CE1 EMIF16 CE2 EMIF16 CE3 HyperLink0 data PCIe data DDR3B data DDR3A data Reserved DDR3A EMIF configuration (8) Reserved DDR3A data Reserved
(8) (5)
PRODUCT PREVIEW
DDR3A data/DDR3B data Reserved
DDR3A EMIF configuration (6) Reserved DDR3A data Reserved
94

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SPRS835DAugust 2013
8 Access to 40-bit address requires MSMC MPAX programmation. MPAX from SES port need to re-map the region of 00 2101 0000-00 2101 01FF to this region.
5.2 Memory Protection Unit (MPU)

CFG (configuration) space of all slave devices on the TeraNet is protected by the MPU. The TCI6636K2H contains fifteen MPUs: MPU0 is used for main TeraNet_3P_B (SCR_3P (B)) CFG. MPU1/2/5 are used for QM_SS (one for VBUSM port and one each for the two configuration VBUSP ports). MPU3/4/6 are used for RAC_0/RAC_1 and one for BCR. MPU7 is used for DDR3_B. MPU8 is used for EMIF16. MPU9 is used for interrupt controllers connected to TeraNet_3P (SCR_3P). MPU10 is used for semaphore. MPU11 is used to protect TeraNet_6P_B (SCR_6P (B)) CPU/6 CFG TeraNet MPU12/13/14 are used for SPI0/1/2 This section contains MPU register map and details of device-specific MPU registers only. For MPU features and details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 5-2 MPU0-MPU5 Default Configuration
MPU0 Main SCR_3P (B) Assume allowed 16 16 1KB granularity MPU1 (QM_SS DATA PORT) Assume allowed 16 16 1KB granularity MPU2 (QM_SS CFG1 PORT) Assume allowed 16 16 1KB granularity MPU3 BCR CFG Assume allowed 16 2 1KB granularity MPU4 RAC 0/1 Assume allowed 16 4 1KB granularity MPU5 (QM_SS CFG2 PORT) Assume allowed 16 16 1KB granularity
Setting Default permission Number of allowed IDs supported Number of programmable ranges supported Compare width End of Table 5-2
Table 5-3
Setting
MPU6-MPU11 Default Configuration

MPU6 Reserved MPU7 DDR3B Assume allowed 16 16 1KB granularity MPU8 EMIF16 Assume allowed 16 8 1KB granularity MPU9 INTC Assume allowed 16 4 1KB granularity MPU10 SM Assume allowed 16 2 1KB granularity MPU11 SCR_6P (B) Assume allowed 16 16 1KB granularity
Default permission Number of allowed IDs supported Number of programmable ranges supported Compare width End of Table 5-3
95
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Setting Default permission Number of allowed IDs supported
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MPU12-MPU14 Default Configuration

MPU12 SPI0 Assume allowed 16 MPU13 SPI1 Assume allowed 16 2 1KB granularity MPU14 SPI2 Assume allowed 16 2 1KB granularity
Number of programmable ranges supported 2 Compare width End of Table 5-4 1KB granularity
Table 5-5
MPU0 MPU1 MPU2 MPU3 MPU4 MPU5 MPU6 MPU7 MPU8 MPU9 MPU10 MPU11 MPU12 MPU13 MPU14 End of Table 5-5
MPU Memory Regions

Memory Protection Main CFG SCR QM_SS DATA PORT QM_SS CFG1 PORT BCR RAC 0/1 QM_SS CFG2 PORT Reserved DDR3B SPIROM/EMIF16 INTC/AINTC Semaphore SCR_6 and CPU/6 CFG SCR SPI0 SPI1 SPI2 Start Address 0x01D0_0000 0x23A0_0000 0x02A0_0000 0x027C_0000 0x0210_0000 0x02A0_4000 0x02C0_0000 0x2101_0000 0x20B0_0000 0x0264_0000 0x0260_0000 0x0220_0000 0x2100_0400 0x2100_0400 0x2100_0800 End Address 0x01E7_FFFF 0x23BF_FFFF 0x02AF_FFFF 0x027C_03FF 0x0215_FFFF 0x02BF_FFFF 0x02CD_FFFF 0xFFFF_FFFF 0x3FFF_FFFF 0x0264_07FF 0x0260_9FFF 0x03FF_FFFF 0x2100_07FF 0x2100_07FF 0x2100_0AFF
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Table 5-6 shows the unique Master ID assigned to each C66x CorePac and peripherals on the device.
Table 5-6
Master ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Master ID Settings (Part 1 of 4)

TCI6636K2H C66x CorePac0 Data C66x CorePac1 Data C66x CorePac2 Data C66x CorePac3 Data C66x CorePac4 Data C66x CorePac5 Data C66x CorePac6 Data C66x CorePac7 Data ARM CorePac 0 non-cache accesses and cache accesses for all ARM cores ARM CorePac 1 non-cache accesses ARM CorePac 2 non-cache accesses ARM CorePac 3 non-cache accesses Reserved Reserved Reserved
96

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SPRS835DAugust 2013 Master ID Settings (Part 2 of 4)

TCI6636K2H Reserved C66x CorePac0 CFG C66x CorePac1 CFG C66x CorePac2 CFG C66x CorePac3 CFG C66x CorePac4 CFG C66x CorePac5 CFG C66x CorePac6 CFG C66x CorePac7 CFG
Table 5-6
Master ID 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 to 55 56 57 58 59
EDMA0_TC0 read EDMA0_TC0 write EDMA0_TC1 read HyperLink0 HyperLink1 SRIO PCIE EDMA0_TC1 write EDMA1_TC0 read EDMA1_TC0 write EDMA1_TC1 read EDMA1_TC1write EDMA1_TC2 read EDMA1_TC2 write EDMA1_TC3 read EDMA1_TC3 write EDMA2_TC0 read EDMA2_TC0 write EDMA2_TC1 read EDMA2_TC1 write EDMA2_TC2 read EDMA2_TC2 write EDMA2_TC3 read EDMA2_TC3 write EDMA3_TC0 read EDMA3_TC0 write EDMA3_TC1 read Reserved EDMA3_TC1 write SRIO PKTDMA FFTC_0 FFTC_1 RAC_1_BE0 RAC_1_BE1
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Reserved

Master ID 60 61 62 63 64 65 66 67 68 to 71 72 to 79 80 81 82 83 84 to 87 88 to 91 92 to 95 96 to 99 100 to 101 102 103 104 105 106 107 108-139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157
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Master ID Settings (Part 3 of 4)

TCI6636K2H RAC_0_BE0 RAC_0_BE1 EDMA3CC0 EDMA3CC1 EDMA3CC2 FFTC_2 Reserved FFTC_3 Queue Manager AIF2 Reserved BCP_DIO0 BCP_DIO1 Reserved Reserved Reserved Packet Coprocessor MST2 Packet Coprocessor MST1 Reserved BCP TAC_FEI0 TAC_FEI1 Reserved Reserved DBG_DAP Reserved CPT_L2_0 CPT_L2_1 CPT_L2_2 CPT_L2_3 CPT_L2_4 CPT_L2_5 CPT_L2_6 CPT_L2_7 CPT_MSMC0 CPT_MSMC1 CPT_MSMC2 CPT_MSMC3 CPT_DDR3A CPT_SM CPT_QM_CFG1 CPT_QM_M CPT_CFG CPT_RAC_FEI
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SPRS835DAugust 2013 Master ID Settings (Part 4 of 4)

TCI6636K2H CPT_RAC_CFG1 CPT_TAC_BE CPT_QM_CFG2 CPT_DDR3B CPT_RAC_CFG2 CPT_BCR_CFG CPT_EDMA3CC0_4 CPT_EDMA3CC1_2_3 CPT_INTC
Table 5-6
Master ID 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180-183 184-255 End of Table 5-6
USB EDMA4_TC0 read EDMA4_TC0 write EDMA4_TC1 read EDMA4_TC1 write EDMA4_CC_TR CPT_MSMC0 CPT_MSMC1 CPT_MSMC2 CPT_MSMC3 Reserved TAC FEI2 NETCP Reserved
NoteThere are two master ID values assigned to the Queue Manager_second master port, one master ID
for external linking RAM and the other one for the PDSP/MCDM accesses. Table 5-7 shows the privilege ID of each C66x CorePac and every mastering peripheral. The table also shows the privilege level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.
Table 5-7
Privilege ID 0 1 2 3 4 5 6
Privilege ID Settings (Part 1 of 2)

Master C66x CorePac0 C66x CorePac1 C66x CorePac2 C66x CorePac3 C66x CorePac4 C66x CorePac5 C66x CorePac6 Privilege Level SW dependent, driven by MSMC SW dependent, driven by MSMC SW dependent, driven by MSMC SW dependent, driven by MSMC SW dependent, driven by MSMC SW dependent, driven by MSMC SW dependent, driven by MSMC Security Level Non-secure Non-secure Non-secure Non-secure Non-secure Non-secure Non-secure Access Type DMA DMA DMA DMA DMA DMA DMA
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CPT_SPI_ROM_EMIF16

Privilege ID 7 8 9
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Privilege ID Settings (Part 2 of 2)

Master C66x CorePac7 ARM CorePac SRIO_M and all Packet DMA masters (NetCP, Both QM_CDMA, FFTC, BCP_CDMA, AIF, SRIO_CDMA, USB Privilege Level SW dependent, driven by MSMC SW dependent Security Level Non-secure Non-secure Access Type DMA DMA DMA
Non-secure User/driven by SRIO block, user mode and supervisor mode is determined by per transaction basis. Only the transaction with source ID matching the value in SupervisorID register is granted supervisor mode. User Supervisor Driven by Emulation SW Supervisor Supervisor Non-secure Non-secure Driven by Emulation SW Non-secure Non-secure
10 11 12 13 14 15
QM_Second PCIe DAP
(1)
DMA DMA DMA DMA DMA
RAC_TAC/BCP_DIO HyperLink Reserved
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End of Table 5-7

1 QM_Second provides a path that PDSP uses to access the system memory.
5.2.1 MPU Registers This section includes the offsets for MPU registers and definitions for device-specific MPU registers. For Number of Programmable Ranges supported (PROGx_MPSA, PROGxMPEA) refer to the following tables.
5.2.1.1 MPU Register Map
Table 5-8
Offset 0h 4h 10h 14h 18h 1Ch 20h 200h 204h 208h 210h 214h 218h 220h 224h 228h 230h 234h 238h 240h 244h
MPU Registers (Part 1 of 2)

Name REVID CONFIG IRAWSTAT IENSTAT IENSET IENCLR EOI PROG0_MPSAR PROG0_MPEAR PROG0_MPPAR PROG1_MPSAR PROG1_MPEAR PROG1_MPPAR PROG2_MPSAR PROG2_MPEAR PROG2_MPPAR PROG3_MPSAR PROG3_MPEAR PROG3_MPPAR PROG4_MPSAR PROG4_MPEAR Description Revision ID Configuration Interrupt raw status/set Interrupt enable status/clear Interrupt enable Interrupt enable clear End of interrupt Programmable range 0, start address Programmable range 0, end address Programmable range 0, memory page protection attributes Programmable range 1, start address Programmable range 1, end address Programmable range 1, memory page protection attributes Programmable range 2, start address Programmable range 2, end address Programmable range 2, memory page protection attributes Programmable range 3, start address Programmable range 3, end address Programmable range 3, memory page protection attributes Programmable range 4, start address Programmable range 4, end address
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SPRS835DAugust 2013 MPU Registers (Part 2 of 2)

Name PROG4_MPPAR PROG5_MPSAR PROG5_MPEAR PROG5_MPPAR PROG6_MPSAR PROG6_MPEAR PROG6_MPPAR PROG7_MPSAR PROG7_MPEAR PROG7_MPPAR PROG8_MPSAR PROG8_MPEAR PROG8_MPPAR PROG9_MPSAR PROG9_MPEAR PROG9_MPPAR PROG10_MPSAR PROG10_MPEAR PROG10_MPPAR PROG11_MPSAR PROG11_MPEAR PROG11_MPPAR PROG12_MPSAR PROG12_MPEAR PROG12_MPPAR PROG13_MPSAR PROG13_MPEAR PROG13_MPPAR PROG14_MPSAR PROG14_MPEAR PROG14_MPPAR PROG15_MPSAR PROG15_MPEAR PROG15_MPPAR FLTADDRR FLTSTAT FLTCLR Description Programmable range 4, memory page protection attributes Programmable range 5, start address Programmable range 5, end address Programmable range 5, memory page protection attributes Programmable range 6, start address Programmable range 6, end address Programmable range 6, memory page protection attributes Programmable range 7, start address Programmable range 7, end address
Table 5-8
Offset 248h 250h 254h 258h 260h 264h 268h 270h 274h 278h 280h 284h 288h 290h 294h 298h 2A0h 2A4h 2A8h 2B0h 2B4h 2B8h 2C0h 2C4h 2C8h 2D0h 2D4h 2Dh 2E0h 2E4h 2E8h 2F0h 2F4h 2F8h 300h 304h 308h End of Table 5-8
Programmable range 8, start address Programmable range 8, end address Programmable range 8, memory page protection attributes Programmable range 9, start address Programmable range 9, end address Programmable range 9, memory page protection attributes Programmable range 10, start address Programmable range 10, end address Programmable range 10, memory page protection attributes Programmable range 11, start address Programmable range 11, end address Programmable range 11, memory page protection attributes Programmable range 12, start address Programmable range 12, end address Programmable range 12, memory page protection attributes Programmable range 13, start address Programmable range 13, end address Programmable range 13, memory page protection attributes Programmable range 14, start address Programmable range 14, end address Programmable range 14, memory page protection attributes Programmable range 15, start address Programmable range 15, end address Programmable range 15, memory page protection attributes Fault address Fault status Fault clear
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Programmable range 7, memory page protection attributes

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5.2.1.2 Device-Specific MPU Registers

5.2.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Figure 5-1 Configuration Register (CONFIG)
31 ADDR_WIDTH MPU0 MPU1 MPU2 MPU3 R-0 R-0 R-0 R-0 R-0 R-0 24 23 20 19 16 15 12 11 1 0 ASSUME_ALLOWED R-1 R-1 R-1 R-1 R-1 R-1
NUM_FIXED R-0 R-0 R-0 R-0 R-0 R-0
NUM_PROG R-16 R-16 R-16 R-2 R-4 R-16 Reserved
NUM_AIDS R-16 R-16 R-16 R-16 R-16 R-16
Reserved R-0 R-0 R-0 R-0 R-0 R-0
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MPU4 MPU5 MPU6 Reset Values MPU7 MPU8 MPU9 MPU10 MPU11 MPU12 MPU13 MPU14
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
R-16 R-8 R-4 R-2 R-16 R-2 R-2 R-2
R-16 R-16 R-16 R-16 R-16 R-16 R-16 R-16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1
Legend: R = Read only; -n = value after reset
Table 5-9
Bits 31 24 Field
Configuration Register Field Descriptions

Description Address alignment for range checking 0 = 1KB alignment 6 = 64KB alignment Number of fixed address ranges Number of programmable address ranges Number of supported AIDs Reserved. Always read as 0. Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not. 0 = Assume disallowed 1 = Assume allowed ADDR_WIDTH
23 20 19 16 15 12 11 1 0
NUM_FIXED NUM_PROG NUM_AIDS Reserved ASSUME_ALLOWED
End of Table 5-9
5.2.2 MPU Programmable Range Registers

5.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The Programmable Address Start Register holds the start address for the range. This register is writeable by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register, then the register is also writeable only by a secure entity.
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The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines the width of the address field in MPSAR and MPEAR.
Figure 5-2
31 START_ADDR R/W Legend: R = Read only; R/W = Read/Write
Programmable Range n Start Address Register (PROGn_MPSAR)

10 9 Reserved R 0
Table 5-10
Bit 31 10 90 Field
Programmable Range n Start Address Register Field Descriptions

Description Start address for range n Reserved. Always read as 0. START_ADDR Reserved
End of Table 5-10
Table 5-11
Register PROG0_MPSAR PROG1_MPSAR PROG2_MPSAR PROG3_MPSAR PROG4_MPSAR PROG5_MPSAR PROG6_MPSAR PROG7_MPSAR PROG8_MPSAR PROG9_MPSAR PROG10_MPSAR PROG11_MPSAR PROG12_MPSAR PROG13_MPSAR PROG14_MPSAR PROG15_MPSAR
MPU0-MPU5 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values

MPU0 0x01D0_0000 0x01F0_0000 0x02F0_0000 0x0200_0000 0x020C_0000 0x021C_0000 0x021D_0000 0x021F_0000 0x0234_0000 0x0254_0000 0x0258_0000 0x0000_0000 0x0290_0000 0x01E8_0000 0x01E8_0800 0x01E0_0000 MPU1 0x23A0_0000 0x23A0_2000 0x023A_6000 0x23A0_6800 0x23A0_7000 0x23A0_8000 0x23A0_C000 0x23A0_E000 0x23A0_F000 0x23A0_F800 0x23A1_0000 0x23A1_C000 0x23A4_0000 0x23A8_0000 0x23B0_0000 0x23B8_0000 MPU2 0x02A0_0000 0x02A0_2000 0x02A0_6000 0x02A0_6800 0x02A0_7000 0x02A0_8000 0x02A0_C000 0x02A0_E000 0x02A0_F000 0x02A0_F800 0x02A1_0000 0x02A2_0000 0x02A4_0000 0x02A8_0000 0x02AC_0000 0x02AE_0000 MPU3 0x027C_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU4 0x0210_0000 0x01F8_0000 Reserved Reserved N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU5 0x02A0_4000 0x02A0_5000 0x02A0_6400 0x02A0_7400 0x02A0_A000 0x02A0_D000 0x02A0_E000 0x02A0_F000 0x02A0_F800 0x02A1_2000 0x02A1_C000 0x02A2_8000 0x02A6_0000 0x02AA_0000 0x02B0_0000 0x02B8_0000
End of Table 5-11
Table 5-12
Register PROG0_MPSAR PROG1_MPSAR PROG2_MPSAR PROG3_MPSAR PROG4_MPSAR PROG5_MPSAR PROG6_MPSAR PROG7_MPSAR PROG8_MPSAR PROG9_MPSAR
MPU6-MPU11 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values (Part 1 of 2)
MPU6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MPU7 0x2101_0000 0x0000_0000 0x0800_0000 0x1000_0000 0x1800_0000 0x2000_0000 0x2800_0000 0x3000_0000 0x3800_0000 0x4000_0000 MPU8 0x3000_0000 0x3200_0000 0x3400_0000 0x3600_0000 0x3800_0000 0x3A00_0000 0x3C00_0000 0x2100_0800 N/A N/A MPU9 0x0260_0000 0x0260_4000 0x0260_8000 0x0256_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 MPU10 0x0264_0000 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A MPU11 0x0220_0000 0x0231_0000 0x0231_A000 0x0233_0000 0x0235_0000 0x0263_0000 0x0244_0000 0x024C_0000 0x0250_0000 0x0253_0000
103
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Register PROG10_MPSAR PROG11_MPSAR PROG12_MPSAR PROG13_MPSAR PROG14_MPSAR PROG15_MPSAR End of Table 5-12
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MPU6-MPU11 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values (Part 2 of 2)
MPU6 Reserved Reserved Reserved Reserved Reserved Reserved MPU7 0x4800_0000 0x5000_0000 0x5800_0000 0x6000_0000 0x6800_0000 0x7000_0000 MPU8 N/A N/A N/A N/A N/A N/A MPU9 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 MPU10 N/A N/A N/A N/A N/A N/A MPU11 0x0253_0C00 0x0260_B000 0x0262_0000 0x0300_0000 0x021E_0000 0x0268_0000
Table 5-13
MPU12-MPU14 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values

MPU12 0x2100_0400 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU13 0x2100_0400 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU14 0x2100_0800 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
PRODUCT PREVIEW
Register PROG0_MPSAR PROG1_MPSAR PROG2_MPSAR PROG3_MPSAR PROG4_MPSAR PROG5_MPSAR PROG6_MPSAR PROG7_MPSAR PROG8_MPSAR PROG9_MPSAR PROG10_MPSAR PROG11_MPSAR PROG12_MPSAR PROG13_MPSAR PROG14_MPSAR PROG15_MPSAR End of Table 5-13
5.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register then the register is also writeable only by a secure entity. The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field in MPSAR and MPEAR
Figure 5-3
31 END_ADDR R/W Legend: R = Read only; R/W = Read/Write
Programmable Range n End Address Register (PROGn_MPEAR)

10 9 Reserved R 0
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SPRS835DAugust 2013 Programmable Range n End Address Register Field Descriptions

Field END_ADDR Reserved Description End address for range n Reserved. Always read as 3FFh.
Table 5-14
Bit 31 10 90
End of Table 5-14
Table 5-15
Register PROG0_MPEAR PROG1_MPEAR PROG2_MPEAR PROG3_MPEAR PROG4_MPEAR PROG5_MPEAR PROG6_MPEAR PROG7_MPEAR PROG8_MPEAR PROG9_MPEAR PROG10_MPEAR PROG11_MPEAR PROG12_MPEAR PROG13_MPEAR PROG14_MPEAR PROG15_MPEAR
MPU0-MPU5 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values

MPU0 0x01DF_FFFF 0x01F7_FFFF 0x02FF_FFFF 0x020B_FFFF 0x020F_FFFF 0x021C_83FF 0x021D_C0FF 0x021F_C7FF 0x0234_C0FF 0x0255_FFFF 0x025F_FFFF 0x0000_0000 0x029F_FFFF 0x01E8_07FF 0x01E8_43FF 0x01E7_FFFF MPU1 0x23A0_1FFF 0x23A0_5FFF 0x23A0_67FF 0x23A0_6FFF 0x23A0_7FFF 0x23A0_BFFF 0x23A0_DFFF 0x23A0_EFFF 0x23A0_F7FF 0x23A0_FFFF 0x23A1_BFFF 0x23A3_FFFF 0x23A7_FFFF 0x23AF_FFFF 0x23B7_FFFF 0x23BF_FFFF MPU2 0x02A0_00FF 0x02A0_3FFF 0x02A0_63FF 0x02A0_6FFF 0x02A0_73FF 0x02A0_9FFF 0x02A0_CFFF 0x02A0_E7FF 0x02A0_F7FF 0x02A0_FFFF 0x02A1_1FFF 0x02A2_5FFF 0x02A5_FFFF 0x02A9_FFFF 0x02AD_FFFF 0x02AF_FFFF MPU3 0x027C_03FF 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU4 0x0215_FFFF 0x01FD_FFFF 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU5 0x02A0_4FFF 0x02A0_5FFF 0x02A0_67FF
0x02A0_BFFF 0x02A0_DFFF 0x02A0_E7FF 0x02A0_F7FF 0x02A0_FFFF 0x02A1_7FFF 0x02A1_FFFF 0x02A3_FFFF 0x02A7_FFFF 0x02AB_FFFF 0x02B7_FFFF 0x02BF_FFFF
End of Table 5-15
Table 5-16
Register PROG0_MPEAR PROG1_MPEAR PROG2_MPEAR PROG3_MPEAR PROG4_MPEAR PROG5_MPEAR PROG6_MPEAR PROG7_MPEAR PROG8_MPEAR PROG9_MPEAR PROG10_MPEAR PROG11_MPEAR PROG12_MPEAR PROG13_MPEAR PROG14_MPEAR PROG15_MPEAR

MPU6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MPU7 0x2103_FFFF 0x07FF_FFFF 0x0FFF_FFFF 0x17FF_FFFF 0x1FFF_FFFF 0x27FF_FFFF 0x2FFF_FFFF 0x37FF_FFFF 0x3FFF_FFFF 0x47FF_FFFF 0x4FFF_FFFF 0x57FF_FFFF 0x5FFF_FFFF 0x67FF_FFFF 0x6FFF_FFFF 0x7FFF_FFFF MPU8 0x31FF_FFFF 0x33FF_FFFF 0x35FF_FFFF 0x37FF_FFFF 0x39FF_FFFF 0x3BFF_FFFF 0x3FFF_FFFF 0x2100_0AFF N/A N/A N/A N/A N/A N/A N/A N/A MPU9 0x0260_1FFF 0x0260_5FFF 0x0260_9FFF 0x0257_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 MPU10 0x0264_07FF 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU11 0x022F_027F 0x0231_01FF 0x0232_FFFF 0x0233_07FF 0x0235_0FFF 0x0263_FFFF 0x024B_3FFF 0x024C_0BFF 0x0250_7FFF 0x0253_0BFF 0x0253_FFFF 0x0260_BFFF 0x0262_0FFF 0x03FF_FFFF 0x021E_1FFF 0x026F_FFFF
End of Table 5-16
105
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0x02A0_7FFF

Register PROG0_MPEAR PROG1_MPEAR PROG2_MPEAR PROG3_MPEAR PROG4_MPEAR PROG5_MPEAR PROG6_MPEAR PROG7_MPEAR PROG8_MPEAR PROG9_MPEAR PROG10_MPEAR PROG11_MPEAR PROG12_MPEAR PROG13_MPEAR PROG14_MPEAR PROG15_MPEAR End of Table 5-17
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MPU12 0x2100_07FF 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU13 0x2100_07FF 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU14 0x2100_0AFF 0x0000_0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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5.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
The programmable address memory protection page attribute register holds the permissions for the region. This register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also writeable only by a non-debug secure entity. The NS bit is writeable only by a non-debug secure entity. For debug accesses, the register is writeable only when NS = 1 or EMU = 1.
Figure 5-4
31 Reserved R 14 AID4 R/W 13 AID3 R/W 12 AID2 R/W 11 AID1 R/W 10 AID0 R/W
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)

26 25 AID15 R/W 9 AIDX R/W 24 AID14 R/W 8 Reserved R 23 AID13 R/W 22 AID12 R/W 7 NS R/W 21 AID11 R/W 6 EMU R/W 20 AID10 R/W 5 SR R/W 19 AID9 R/W 4 SW R/W 18 AID8 R/W 3 SX R/W 17 AID7 R/W 2 UR R/W 16 AID6 R/W 1 UW R/W 15 AID5 R/W 0 UX R/W
Legend: R = Read only; R/W = Read/Write
Table 5-18
Bits 31 26 25
Programmable Range n Memory Protection Page Attribute Register Field Descriptions (Part 1 of 3)
Name Reserved AID15 Description Reserved. Always read as 0. Controls access from ID = 15 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 14 0 = Access is not checked for permissions 1 = Access is checked for permissions
24
AID14
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SPRS835DAugust 2013 Programmable Range n Memory Protection Page Attribute Register Field Descriptions (Part 2 of 3)
Name AID13 Description Controls access from ID = 13 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 12 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 11 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 10 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 9 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 8 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 7 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 6 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 5 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 4 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 3 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 2 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 1 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID = 0 0 = Access is not checked for permissions 1 = Access is checked for permissions Controls access from ID > 15 0 = Access is not checked for permissions 1 = Access is checked for permissions Reserved. Always reads as 0. Non-secure access permission 0 = Only secure access allowed 1 = Non-secure access allowed Emulation (debug) access permission. This bit is ignored if NS = 1 0 = Debug access not allowed 1 = Debug access allowed
Table 5-18
Bits 23
22
AID12
21
AID11
20
AID10
19
AID9
18
AID8
17
AID7
16
AID6
15
AID5
14
AID4
13
AID3
12
AID2
11
AID1
10
AID0
AIDX
8 7
Reserved NS
EMU
107
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Bits 5 SR
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Programmable Range n Memory Protection Page Attribute Register Field Descriptions (Part 3 of 3)
Name Description Supervisor Read permission 0 = Access not allowed 1 = Access allowed Supervisor Write permission 0 = Access not allowed 1 = Access allowed Supervisor Execute permission 0 = Access not allowed 1 = Access allowed User Read permission 0 = Access not allowed 1 = Access allowed User Write permission 0 = Access not allowed 1 = Access allowed User Execute permission 0 = Access not allowed 1 = Access allowed
SW
SX
UR
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UW
UX
End of Table 5-181
Table 5-19
Register PROG0_MPPAR PROG1_MPPAR PROG2_MPPAR PROG3_MPPAR PROG4_MPPAR PROG5_MPPAR PROG6_MPPAR PROG7_MPPAR PROG8_MPPAR PROG9_MPPAR PROG10_MPPAR PROG11_MPPAR PROG12_MPPAR PROG13_MPPAR PROG14_MPPAR PROG15_MPPAR
MPU0-MPU5 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values
MPU0 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB6 0x03FF_FCB0 0x03FF_FCB6 MPU1 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCA4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCA4 0x03FF_FCB6 0x03FF_FCA4 0x03FF_FCA4 MPU2 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCA4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCA4 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 MPU3 0x03FF_FCB6 0x03FF_FCB6 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU4 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU5 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCA4 0x03FF_FCF4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCB4 0x03FF_FCF4 0x03FF_FCF4 0x03FF_FCA4 0x03FF_FCB6 0x03FF_FCA4 0x03FF_FCA4
End of Table 5-19
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SPRS835DAugust 2013 MPU6-MPU11 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values
MPU6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MPU7 0x03FF_FCB6 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF MPU8 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 N/A N/A N/A N/A N/A N/A N/A N/A MPU9 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 MPU10 0x03FF_FCB6 0x03FF_FCB6 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU11 0x03FF_FCB6 0x03FF_FCB0 0x03FF_FCB6 0x03FF_FCB0 0x03FF_FCB0 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB0
Table 5-20
0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB0 0x03FF_FCB6 0x03FF_FCB0 0x03FF_FCB6
End of Table 5-20
Table 5-21
MPU12-MPU14 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values
MPU12 0x03FF_FCB6 0x03FF_FCBF Reserved N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU13 0x03FF_FCB6 0x03FF_FCBF Reserved N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MPU14 0x03FF_FCB6 0x03FF_FCBF Reserved N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
End of Table 5-21
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0x03FF_FCB0

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5.3 Interrupts
This section discusses the interrupt sources, controller, and topology. Also provided are tables describing the interrupt events. 5.3.1 Interrupt Sources and Interrupt Controller The CPU interrupts on the TCI6636K2H device are configured through the C66x CorePac Interrupt Controller. The Interrupt Controller allows for up to 128 system events to be programmed to any of the 12 CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events. Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In addition, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through the CorePac Interrupt Controller blocks, CIC[2:0]. This is clocked using CPU/6. The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, ARM GIC (ARM Generic Interrupt Controller) plus the EDMA3CC. CIC0 has 104 event outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 0 through 3. Similarly, CIC1 has 104 event outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 4 through 7. CIC2 has 103 event outputs which provides 8, 20, 8, 8, 8, and 16 events to EDMA3CC0, EDMA3CC1, EDMA3C2, EDMA3CC3, EDMA3CC4, and HyperLinks respectively. The events that are routed to the C66x CorePacs for Advanced Event Triggering (AET) purposes from those EDMA3CC and FSYNC events that are not otherwise provided to each C66x CorePac. Modules such as FFTC, TCP3d, TAC, AIF, CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI handshaking interface. The EOI value is 0 for TCP3d_x, TAC, AIF, CP_MPU, BOOT_CFG, and CP_Tracer. For FFTC: the EOI value is 0 for FFTC_x_INTD_INTR0, the EOI value is 1 for FFTC_x_INTD_INTR1, the EOI value is 2 for FFTC_x_INTD_INTR2 the EOI value is 3 for FFTC_x_INTD_INTR3 (where FFTC_x can be FFTC_0, FFTC_1, FFTC_2 or FFTC_3)
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Figure 5-5 shows the TCI6636K2H interrupt topology.

Figure 5-5 Interrupt Topology
57 Shared Primary Events 8 Broadcast Events from AIF2 12 Reserved Events 19 Unique Primary Events 18 Secondary Events C66x CorePac0
26 QMSS q_pend Events
19 Unique Primary Events 18 Secondary Events C66x CorePac1
CIC0 19 Unique Primary Events 18 Secondary Events
32 QMSS lo Events 19 Unique Primary Events 18 Secondary Events 20 Broadcast Events from CIC0 19 Unique Primary Events 18 Secondary Events C66x CorePac4 C66x CorePac3
402 Common Events
402 Common Events
12 Reserved Events
19 Unique Primary Events 18 Secondary Events C66x CorePac5
CIC1 19 Unique Primary Events 18 Secondary Events C66x CorePac6
9 QMSS q_pend Events 19 Unique Primary Events 32 QMSS_lo Events 18 Secondary Events 20 Broadcast Events from CIC1 8 Shared Events 39 QMSS q_pend Events 24 2 Primary Events 8 2 Secondary Events 56 Primary Events 8 Secondary Events 44 Primary Events 20 Secondary Events
CIC2
C66x CorePac7
HyperLink EDMA3 CC0 EDMA3 CC1 EDMA3 CC2 EDMA3 CC3 EDMA3 CC4 ARM INTC
32 QMSS_1 hi Events
32 QMSS_2 hi Events
357 Common Events
56 Primary Events 8 Secondary Events 56 Primary Events 8 Secondary Events 56 Primary Events
19 Reserved Events
6636-38
8 Secondary Events
36
Peripherals
480 SPI Events
111
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C66x CorePac2

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Table 5-22 shows the mapping of system events.

Table 5-22
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
System Event Mapping C66x CorePac Primary Interrupts (Part 1 of 3)

Event Name EVT0 EVT1 EVT2 EVT3 TETB_HFULLINTN TETB_FULLINTN TETB_ACQINTN TETB_OVFLINTN TETB_UNFLINTN EMU_DTDMA MSMC_MPF_ERRORN EMU_RTDXRX EMU_RTDXTX IDMA0 IDMA1 SEM_ERRN SEM_INTN PCIE_INT4_PLUS_N Reserved RAC_0_INT SRIO_INTDST16_PLUS_N Reserved RAC_1_INT CIC_OUT35 CIC_2_OUT102 CIC_2_OUT94_PLUS_N CIC_OUT68_PLUS_10_MUL_N CIC_OUT69_PLUS_10_MUL_N CIC_OUT70_PLUS_10_MUL_N CIC_OUT71_PLUS_10_MUL_N CIC_OUT72_PLUS_10_MUL_N CIC_OUT73_PLUS_10_MUL_N CIC_OUT16 CIC_OUT17 CIC_OUT18 CIC_OUT19 CIC_OUT20 CIC_OUT21 CIC_OUT22 CIC_OUT23 CIC_OUT32 CIC_OUT33 CIC_OUT13_PLUS_16_MUL_N Description Event combiner 0 output Event combiner 1 output Event combiner 2 output Event combiner 3 output TETB is half full TETB is full TETB Acquisition complete interrupt TETB Overflow condition interrupt TETB Underflow condition interrupt Emulation interrupt for host scan, DTDMA transfer complete and AET Memory protection fault indicators for system master PrivID = 0 (C66x CorePac) Reserved Reserved IDMA channel 0 interrupt IDMA channel 1 interrupt Semaphore error interrupt Semaphore interrupt PCIE0 MSI interrupt Reserved RAC interrupt SRIO interrupt Reserved RAC interrupt CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
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SPRS835DAugust 2013 System Event Mapping C66x CorePac Primary Interrupts (Part 2 of 3)
Event Name CIC_OUT14_PLUS_16_MUL_N CIC_OUT15_PLUS_16_MUL_N CIC_OUT64_PLUS_10_MUL_N CIC_OUT65_PLUS_10_MUL_N CIC_OUT66_PLUS_10_MUL_N QMSS_INTD_1_HIGH_N QMSS_INTD_1_HIGH_8_PLUS_N QMSS_INTD_1_HIGH_16_PLUS_N QMSS_INTD_1_HIGH_24_PLUS_N QMSS_INTD_2_HIGH_N QMSS_INTD_2_HIGH_8_PLUS_N QMSS_INTD_2_HIGH_16_PLUS_N QMSS_INTD_2_HIGH_24_PLUS_N CIC_OUT0 CIC_OUT1 CIC_OUT2 CIC_OUT3 CIC_OUT4 CIC_OUT5 CIC_OUT6 CIC_OUT7 TIMER_N_INTL TIMER_N_INTH TIMER_8_INTL TIMER_8_INTH TIMER_9_INTL TIMER_9_INTH TIMER_10_INTL TIMER_10_INTH TIMER_11_INTL TIMER_11_INTH CIC_OUT8_PLUS_16_MUL_N CIC_OUT9_PLUS_16_MUL_N CIC_OUT10_PLUS_16_MUL_N CIC_OUT11_PLUS_16_MUL_N TIMER_14_INTL TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH GPIO_INT8 GPIO_INT9 GPIO_INT10 GPIO_INT11 GPIO_INT12 Description CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output
(1) (1) (1) (1) (1)
Table 5-22
Event No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Navigator 1 accumulated hi-priority interrupt 0 Navigator 1 accumulated hi-priority interrupt 8 Navigator 1 accumulated hi-priority interrupt 16 Navigator 1 accumulated hi-priority interrupt 24
Navigator 2 accumulated hi-priority interrupt 8 Navigator 2 accumulated hi-priority interrupt 16 Navigator 2 accumulated hi-priority interrupt 24 CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output Local timer interrupt low Local timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Local GPIO interrupt Local GPIO interrupt Local GPIO interrupt Local GPIO interrupt Local GPIO interrupt
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
113
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Navigator 2 accumulated hi-priority interrupt 0

Event No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
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System Event Mapping C66x CorePac Primary Interrupts (Part 3 of 3)

Event Name AIF_ATEVT0 AIF_ATEVT1 AIF_ATEVT2 AIF_ATEVT3 AIF_ATEVT4 AIF_ATEVT5 AIF_ATEVT6 AIF_ATEVT7 CIC_OUT67_PLUS_10_MUL_N INTERR EMC_IDMAERR Reserved CIC_2_SPECIAL_BROADCAST EFIINT0 EFIINT1 GPIO_INT13 GPIO_INT14 GPIO_INT15 IPC_GRN GPIO_INTN CIC_OUT12_PLUS_16_MUL_N CIC_OUT34 CIC_2_OUT13 MDMAERREVT Reserved EDMACC_0_4_TC_AET_INT PMC_ED EDMACC_1_2_TC_AET_INT EDMACC_1_3_TC_AET_INT UMC_ED1 UMC_ED2 PDC_INT SYS_CMPA PMC_CMPA PMC_DMPA DMC_CMPA DMC_DMPA UMC_CMPA UMC_DMPA EMC_CMPA EMC_BUSERR Description AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event CIC Interrupt Controller output
(1)
Dropped C66x CorePac interrupt event Invalid IDMA parameters Reserved CIC Interrupt Controller output EFI interrupt from Side A EFI interrupt from Side B Local GPIO interrupt Local GPIO interrupt Local GPIO interrupt Boot CFG GPIO interrupt CIC Interrupt Controller output CIC Interrupt Controller output CIC Interrupt Controller output DMA internal bus error event Reserved EDMA3CC0_4 AET event Single bit error detected during DMA read EDMA3CC1_2 AET event EDMA3CC3_4 AET event Corrected bit error detected Uncorrected bit error detected Power down sleep interrupt SYS CPU MP fault event CPU memory protection fault DMA memory protection fault CPU memory protection fault DMA memory protection fault CPU memory protection fault DMA memory protection fault CPU memory protection fault Bus error interrupt
(1) (1) (1)
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End of Table 5-22

1 For C66x CorePac[0-3], this generic primary interrupt comes from CIC0 and for C66x CorePac[4-7], this generic primary interrupt comes from CIC1.
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Table 5-24 list the ARM CorePac interrupt inputs.

NoteEvent No. 0 is identical to ARM GIC interrupt ID 0. Table 5-23
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
System Event Mapping ARM CorePac Interrupts (Part 1 of 12)

Event Name RSTMUX_INT8 RSTMUX_INT9 RSTMUX_INT10 RSTMUX_INT11 IPC_GR8 IPC_GR9 IPC_GR10 IPC_GR11 SEM_INT8 SEM_INT9 SEM_INT10 SEM_INT11 SEM_ERR8 SEM_ERR9 SEM_ERR10 SEM_ERR11 MSMC_MPF_ERROR8 MSMC_MPF_ERROR9 MSMC_MPF_ERROR10 MSMC_MPF_ERROR11 ARM_NPMUIRQ0 ARM_NPMUIRQ1 ARM_NPMUIRQ2 ARM_NPMUIRQ3 ARM_NINTERRIRQ ARM_NAXIERRIRQ PCIE_INT0 PCIE_INT1 PCIE_INT2 PCIE_INT3 PCIE_INT4 PCIE_INT5 PCIE_INT6 PCIE_INT7 PCIE_INT8 PCIE_INT9 PCIE_INT10 PCIE_INT11 PCIE_INT12 PCIE_INT13 Description Boot config watchdog timer expiration (timer 16) event for ARM Core 0 Boot config watchdog timer expiration (timer 17) event for ARM Core 1 Boot config watchdog timer expiration (timer 18) event for ARM Core 2 Boot config watchdog timer expiration (timer 19) event for ARM Core 3 Boot config IPCG
Boot config IPCG Boot config IPCG Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Memory protection fault indicators for system master PrivID = 8 Memory protection fault indicators for system master PrivID = 9 Memory protection fault indicators for system master PrivID = 10 Memory protection fault indicators for system master PrivID = 11 ARM performance monitoring unit interrupt request ARM performance monitoring unit interrupt request ARM performance monitoring unit interrupt request ARM performance monitoring unit interrupt request ARM internal memory ECC error interrupt request ARM bus error interrupt request PCIE legacy INTA interrupt PCIE legacy INTB interrupt PCIE legacy INTC interrupt PCIE legacy INTD interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE error interrupt PCIE power management interrupt
115
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Boot config IPCG

Event No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
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Event Name QMSS_QUE_PEND_658 QMSS_QUE_PEND_659 QMSS_QUE_PEND_660 QMSS_QUE_PEND_661 QMSS_QUE_PEND_662 QMSS_QUE_PEND_663 QMSS_QUE_PEND_664 QMSS_QUE_PEND_665 QMSS_QUE_PEND_8704 QMSS_QUE_PEND_8705 QMSS_QUE_PEND_8706 QMSS_QUE_PEND_8707 QMSS_QUE_PEND_8708 QMSS_QUE_PEND_8709 QMSS_QUE_PEND_8710 QMSS_QUE_PEND_8711 QMSS_QUE_PEND_8712 QMSS_QUE_PEND_8713 QMSS_QUE_PEND_8714 QMSS_QUE_PEND_8715 QMSS_QUE_PEND_8716 QMSS_QUE_PEND_8717 QMSS_QUE_PEND_8718 QMSS_QUE_PEND_8719 QMSS_QUE_PEND_8720 QMSS_QUE_PEND_8721 QMSS_QUE_PEND_8722 QMSS_QUE_PEND_8723 QMSS_QUE_PEND_8724 QMSS_QUE_PEND_8725 QMSS_QUE_PEND_8726 QMSS_QUE_PEND_8727 QMSS_QUE_PEND_8728 QMSS_QUE_PEND_8729 QMSS_QUE_PEND_8730 QMSS_QUE_PEND_8731 QMSS_QUE_PEND_8732 QMSS_QUE_PEND_8733 QMSS_QUE_PEND_8734 QMSS_QUE_PEND_8735 TIMER_0_INTL TIMER_0_INTH TIMER_1_INTL TIMER_1_INTH Description Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high
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SPRS835DAugust 2013 System Event Mapping ARM CorePac Interrupts (Part 3 of 12)
Event Name TIMER_2_INTL TIMER_2_INTH TIMER_3_INTL TIMER_3_INTH TIMER_4_INTL TIMER_4_INTH TIMER_5_INTL TIMER_5_INTH TIMER_6_INTL TIMER_6_INTH TIMER_7_INTL TIMER_7_INTH TIMER_8_INTL TIMER_8_INTH TIMER_9_INTL TIMER_9_INTH TIMER_10_INTL TIMER_10_INTH TIMER_11_INTL TIMER_11_INTH TIMER_12_INTL TIMER_12_INTH TIMER_13_INTL TIMER_13_INTH TIMER_14_INTL TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH TIMER_16_INTL TIMER_16_INTH TIMER_17_INTL TIMER_17_INTH TIMER_18_INTL TIMER_18_INTH TIMER_19_INTL TIMER_19_INTH GPIO_INT0 GPIO_INT1 GPIO_INT2 GPIO_INT3 GPIO_INT4 GPIO_INT5 GPIO_INT6 GPIO_INT7 Description Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low
Table 5-23
Event No. 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt
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Timer interrupt high

Event No. 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171
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Event Name GPIO_INT8 GPIO_INT9 GPIO_INT10 GPIO_INT11 GPIO_INT12 GPIO_INT13 GPIO_INT14 GPIO_INT15 GPIO_INT16 GPIO_INT17 GPIO_INT18 GPIO_INT19 GPIO_INT20 GPIO_INT21 GPIO_INT22 GPIO_INT23 GPIO_INT24 GPIO_INT25 GPIO_INT26 GPIO_INT27 GPIO_INT28 GPIO_INT29 GPIO_INT30 GPIO_INT31 SRIO_INT00 SRIO_INT01 SRIO_INT02 SRIO_INT03 SRIO_INT04 SRIO_INT05 SRIO_INT06 SRIO_INT07 SRIO_INT08 SRIO_INT09 SRIO_INT10 SRIO_INT11 SRIO_INT12 SRIO_INT13 SRIO_INT14 SRIO_INT15 SRIO_INT16 SRIO_INT17 SRIO_INT18 SRIO_INT19 Description GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt
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118

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Event Name SRIO_INT20 SRIO_INT21 SRIO_INT22 SRIO_INT23 SRIO_INT_PKTDMA_0 QMSS_INTD_1_PKTDMA_0 QMSS_INTD_1_PKTDMA_1 QMSS_INTD_1_HIGH_0 QMSS_INTD_1_HIGH_1 QMSS_INTD_1_HIGH_2 QMSS_INTD_1_HIGH_3 QMSS_INTD_1_HIGH_4 QMSS_INTD_1_HIGH_5 QMSS_INTD_1_HIGH_6 QMSS_INTD_1_HIGH_7 QMSS_INTD_1_HIGH_8 QMSS_INTD_1_HIGH_9 QMSS_INTD_1_HIGH_10 QMSS_INTD_1_HIGH_11 QMSS_INTD_1_HIGH_12 QMSS_INTD_1_HIGH_13 QMSS_INTD_1_HIGH_14 QMSS_INTD_1_HIGH_15 QMSS_INTD_1_HIGH_16 QMSS_INTD_1_HIGH_17 QMSS_INTD_1_HIGH_18 QMSS_INTD_1_HIGH_19 QMSS_INTD_1_HIGH_20 QMSS_INTD_1_HIGH_21 QMSS_INTD_1_HIGH_22 QMSS_INTD_1_HIGH_23 QMSS_INTD_1_HIGH_24 QMSS_INTD_1_HIGH_25 QMSS_INTD_1_HIGH_26 QMSS_INTD_1_HIGH_27 QMSS_INTD_1_HIGH_28 QMSS_INTD_1_HIGH_29 QMSS_INTD_1_HIGH_30 QMSS_INTD_1_HIGH_31 QMSS_INTD_1_LOW_0 QMSS_INTD_1_LOW_1 QMSS_INTD_1_LOW_2 QMSS_INTD_1_LOW_3 QMSS_INTD_1_LOW_4 Description SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt for Packet DMA starvation Navigator interrupt for Packet DMA starvation Navigator interrupt for Packet DMA starvation Navigator hi interrupt Navigator hi interrupt
Table 5-23
Event No. 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215
Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt
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Navigator hi interrupt

Event No. 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259
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Event Name QMSS_INTD_1_LOW_5 QMSS_INTD_1_LOW_6 QMSS_INTD_1_LOW_7 QMSS_INTD_1_LOW_8 QMSS_INTD_1_LOW_9 QMSS_INTD_1_LOW_10 QMSS_INTD_1_LOW_11 QMSS_INTD_1_LOW_12 QMSS_INTD_1_LOW_13 QMSS_INTD_1_LOW_14 QMSS_INTD_1_LOW_15 QMSS_INTD_2_PKTDMA_0 QMSS_INTD_2_PKTDMA_1 QMSS_INTD_2_HIGH_0 QMSS_INTD_2_HIGH_1 QMSS_INTD_2_HIGH_2 QMSS_INTD_2_HIGH_3 QMSS_INTD_2_HIGH_4 QMSS_INTD_2_HIGH_5 QMSS_INTD_2_HIGH_6 QMSS_INTD_2_HIGH_7 QMSS_INTD_2_HIGH_8 QMSS_INTD_2_HIGH_9 QMSS_INTD_2_HIGH_10 QMSS_INTD_2_HIGH_11 QMSS_INTD_2_HIGH_12 QMSS_INTD_2_HIGH_13 QMSS_INTD_2_HIGH_14 QMSS_INTD_2_HIGH_15 QMSS_INTD_2_HIGH_16 QMSS_INTD_2_HIGH_17 QMSS_INTD_2_HIGH_18 QMSS_INTD_2_HIGH_19 QMSS_INTD_2_HIGH_20 QMSS_INTD_2_HIGH_21 QMSS_INTD_2_HIGH_22 QMSS_INTD_2_HIGH_23 QMSS_INTD_2_HIGH_24 QMSS_INTD_2_HIGH_25 QMSS_INTD_2_HIGH_26 QMSS_INTD_2_HIGH_27 QMSS_INTD_2_HIGH_28 QMSS_INTD_2_HIGH_29 QMSS_INTD_2_HIGH_30 Description Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt Navigator interrupt for Packet DMA starvation Navigator interrupt for Packet DMA starvation Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt
PRODUCT PREVIEW
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Event Name QMSS_INTD_2_HIGH_31 QMSS_INTD_2_LOW_0 QMSS_INTD_2_LOW_1 QMSS_INTD_2_LOW_2 QMSS_INTD_2_LOW_3 QMSS_INTD_2_LOW_4 QMSS_INTD_2_LOW_5 QMSS_INTD_2_LOW_6 QMSS_INTD_2_LOW_7 QMSS_INTD_2_LOW_8 QMSS_INTD_2_LOW_9 QMSS_INTD_2_LOW_10 QMSS_INTD_2_LOW_11 QMSS_INTD_2_LOW_12 QMSS_INTD_2_LOW_13 QMSS_INTD_2_LOW_14 QMSS_INTD_2_LOW_15 UART_0_UARTINT UART_0_URXEVT UART_0_UTXEVT UART_1_UARTINT UART_1_URXEVT UART_1_UTXEVT I2C_0_INT I2C_0_REVT I2C_0_XEVT I2C_1_INT I2C_1_REVT I2C_1_XEVT I2C_2_INT I2C_2_REVT I2C_2_XEVT SPI_0_INT0 SPI_0_INT1 SPI_0_XEVT SPI_0_REVT SPI_1_INT0 SPI_1_INT1 SPI_1_XEVT SPI_1_REVT SPI_2_INT0 SPI_2_INT1 SPI_2_XEVT SPI_2_REVT Description Navigator second hi interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt
Table 5-23
Event No. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt Navigator second interrupt UART0 interrupt UART0 receive event UART0 transmit event UART1 interrupt UART1 receive event UART1 transmit event I2C interrupt I2C receive event I2C transmit event I2C interrupt I2C receive event I2C transmit event I2C interrupt I2C receive event I2C transmit event SPI interrupt SPI interrupt SPI DMA TX event SPI DMA RX event SPI interrupt SPI interrupt SPI DMA TX event SPI DMA RX event SPI interrupt SPI interrupt SPI DMA TX event SPI DMA RX event
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PRODUCT PREVIEW
Navigator second interrupt

Event No. 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347
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Event Name DBGTBR_DMAINT DBGTBR_ACQCOMP ARM_TBR_DMA ARM_TBR_ACQ NETCP_MDIO_LINK_INT0 NETCP_MDIO_LINK_INT1 NETCP_MDIO_USER_INT0 NETCP_MDIO_USER_INT1 NETCP_MISC_INT NETCP_PKTDMA_INT0 EDMACC_0_GINT EDMACC_0_TC_0_INT EDMACC_0_TC_1_INT EDMACC_0_TC_2_INT EDMACC_0_TC_3_INT EDMACC_0_TC_4_INT EDMACC_0_TC_5_INT EDMACC_0_TC_6_INT EDMACC_0_TC_7_INT EDMACC_1_GINT EDMACC_1_TC_0_INT EDMACC_1_TC_1_INT EDMACC_1_TC_2_INT EDMACC_1_TC_3_INT EDMACC_1_TC_4_INT EDMACC_1_TC_5_INT EDMACC_1_TC_6_INT EDMACC_1_TC_7_INT EDMACC_2_GINT EDMACC_2_TC_0_INT EDMACC_2_TC_1_INT EDMACC_2_TC_2_INT EDMACC_2_TC_3_INT EDMACC_2_TC_4_INT EDMACC_2_TC_5_INT EDMACC_2_TC_6_INT EDMACC_2_TC_7_INT EDMACC_3_GINT EDMACC_3_TC_0_INT EDMACC_3_TC_1_INT EDMACC_3_TC_2_INT EDMACC_3_TC_3_INT EDMACC_3_TC_4_INT EDMACC_3_TC_5_INT Description Debug trace buffer (TBR) DMA event Debug trace buffer (TBR) Acquisition has been completed ARM trace buffer (TBR) DMA event ARM trace buffer (TBR) Acquisition has been completed Packet Accelerator subsystem MDIO interrupt Packet Accelerator subsystem MDIO interrupt Packet Accelerator subsystem MDIO interrupt Packet Accelerator subsystem MDIO interrupt Packet Accelerator subsystem MDIO interrupt Packet Accelerator Packet DMA starvation interrupt EDMA3CC0 global completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC1 global completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC2 global completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC3 global completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt
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Event Name EDMACC_3_TC_6_INT EDMACC_3_TC_7_INT EDMACC_4_GINT EDMACC_4_TC_0_INT EDMACC_4_TC_1_INT EDMACC_4_TC_2_INT EDMACC_4_TC_3_INT EDMACC_4_TC_4_INT EDMACC_4_TC_5_INT EDMACC_4_TC_6_INT EDMACC_4_TC_7_INT SR_0_PO_VCON_SMPSERR_INT SR_0_SMARTREFLEX_INTREQ0 SR_0_SMARTREFLEX_INTREQ1 SR_0_SMARTREFLEX_INTREQ2 SR_0_SMARTREFLEX_INTREQ3 SR_0_VPNOSMPSACK SR_0_VPEQVALUE SR_0_VPMAXVDD SR_0_VPMINVDD SR_0_VPINIDLE SR_0_VPOPPCHANGEDONE SR_0_VPSMPSACK SR_0_SR_TEMPSENSOR SR_0_SR_TIMERINT SR_1_PO_VCON_SMPSERR_INT SR_1_SMARTREFLEX_INTREQ0 SR_1_SMARTREFLEX_INTREQ1 SR_1_SMARTREFLEX_INTREQ2 SR_1_SMARTREFLEX_INTREQ3 SR_1_VPNOSMPSACK SR_1_VPEQVALUE SR_1_VPMAXVDD SR_1_VPMINVDD SR_1_VPINIDLE SR_1_VPOPPCHANGEDONE SR_1_VPSMPSACK SR_1_SR_TEMPSENSOR SR_1_SR_TIMERINT HyperLink_0_INT HyperLink_1_INT Description EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC4 global completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt
Table 5-23
Event No. 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388
EDMA3CC4 individual completion interrupt SmartReflex SMPS Error interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage SmartReflex The new voltage required is equal to or greater than MaxVdd SmartReflex The new voltage required is equal to or less than MinVdd SmartReflex. Indicating that the FSM of voltage processor is in idle SmartReflex Indicating that the average frequency error is within the desired limit SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval SmartReflex temperature threshold crossing interrupt Smart Reflex internal timer expiration interrupt SmartReflex SMPS Error interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage SmartReflex The new voltage required is equal to or greater than MaxVdd SmartReflex The new voltage required is equal to or less than MinVdd SmartReflex. Indicating that the FSM of voltage processor is in idle SmartReflex Indicating that the average frequency error is within the desired limit SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval SmartReflex temperature threshold crossing interrupt Smart Reflex internal timer expiration interrupt HyperLink 0 interrupt HyperLink 1 interrupt
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PRODUCT PREVIEW
EDMA3CC4 individual completion interrupt

Event No. 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432
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Event Name ARM_NCTIIRQ0 ARM_NCTIIRQ1 ARM_NCTIIRQ2 ARM_NCTIIRQ3 USB_INT00 USB_INT01 USB_INT02 USB_INT03 USB_INT04 USB_OABSINT USB_MISCINT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF_ATEVT0 AIF_ATEVT1 AIF_ATEVT2 AIF_ATEVT3 AIF_ATEVT4 AIF_ATEVT5 AIF_ATEVT6 AIF_ATEVT7 AIF_ATEVT16 AIF_ATEVT17 AIF_ATEVT18 AIF_ATEVT19 AIF_ATEVT20 AIF_ATEVT21 AIF_ATEVT22 AIF_ATEVT23 USIM_PONIRQ USIM_RREQ USIM_WREQ RAC_0_INT RAC_1_INT Reserved Reserved TAC_INT Reserved Description ARM cross trigger (CTI) IRQ interrupt ARM cross trigger (CTI) IRQ interrupt ARM cross trigger (CTI) IRQ interrupt ARM cross trigger (CTI) IRQ interrupt USB event ring 0 interrupt USB event ring 1 interrupt USB event ring 2 interrupt USB event ring 3 interrupt USB event ring 4 interrupt USB OABS interrupt USB miscellaneous interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event AIF Timer event USIM interrupt USIM read DMA event USIM write DMA event RAC interrupt RAC interrupt Reserved Reserved TAC interrupt Reserved
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Event Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CIC_2_OUT29 CIC_2_OUT30 CIC_2_OUT31 CIC_2_OUT32 CIC_2_OUT33 CIC_2_OUT34 CIC_2_OUT35 CIC_2_OUT36 CIC_2_OUT37 CIC_2_OUT38 CIC_2_OUT39 CIC_2_OUT40 CIC_2_OUT41 CIC_2_OUT42 CIC_2_OUT43 CIC_2_OUT44 CIC_2_OUT45 CIC_2_OUT46 CIC_2_OUT47 CIC_2_OUT18 CIC_2_OUT19 CIC_2_OUT22 CIC_2_OUT23 CIC_2_OUT50 CIC_2_OUT51 CIC_2_OUT66 CIC_2_OUT67 CIC_2_OUT88 CIC_2_OUT89 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 5-23
Event No. 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476
Reserved Reserved Reserved Reserved Reserved CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt CIC2 interrupt
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Reserved

Event No. 477 478 479
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Event Name CIC_2_OUT90 CIC_2_OUT91 CIC_2_OUT92 Description CIC2 interrupt CIC2 interrupt CIC2 interrupt
End of Table 5-23
Table 5-24, Table 5-25 and Table 5-26 list the C66x CorePac Secondary interrupt inputs
Table 5-24
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
CIC0 Event Inputs C66x CorePac Secondary Interrupts (Part 1 of 12)

Event Name EDMACC_1_ERRINT EDMACC_1_MPINT EDMACC_1_TC_0_ERRINT EDMACC_1_TC_1_ERRINT EDMACC_1_TC_2_ERRINT EDMACC_1_TC_3_ERRINT EDMACC_1_GINT Reserved EDMACC_1_TC_0_INT EDMACC_1_TC_1_INT EDMACC_1_TC_2_INT EDMACC_1_TC_3_INT EDMACC_1_TC_4_INT EDMACC_1_TC_5_INT EDMACC_1_TC_6_INT EDMACC_1_TC_7_INT EDMACC_2_ERRINT EDMACC_2_MPINT EDMACC_2_TC_0_ERRINT EDMACC_2_TC_1_ERRINT EDMACC_2_TC_2_ERRINT EDMACC_2_TC_3_ERRINT EDMACC_2_GINT Reserved EDMACC_2_TC_0_INT EDMACC_2_TC_1_INT EDMACC_2_TC_2_INT EDMACC_2_TC_3_INT EDMACC_2_TC_4_INT EDMACC_2_TC_5_INT EDMACC_2_TC_6_INT EDMACC_2_TC_7_INT EDMACC_0_ERRINT EDMACC_0_MPINT EDMACC_0_TC_0_ERRINT Description EDMA3CC1 error interrupt EDMA3CC1 memory protection interrupt EDMA3CC1 TPTC0 error interrupt EDMA3CC1 TPTC1 error interrupt EDMA3CC1 TPTC2 error interrupt EDMA3CC1 TPTC3 error interrupt EDMA3CC1 GINT Reserved EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC2 error interrupt EDMA3CC2 memory protection interrupt EDMA3CC2 TPTC0 error interrupt EDMA3CC2 TPTC1 error interrupt EDMA3CC2 TPTC2 error interrupt EDMA3CC2 TPTC3 error interrupt EDMA3CC2 GINT Reserved EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC0 error interrupt EDMA3CC0 memory protection interrupt EDMA3CC0 TPTC0 error interrupt
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SPRS835DAugust 2013 CIC0 Event Inputs C66x CorePac Secondary Interrupts (Part 2 of 12)
Event Name EDMACC_0_TC_1_ERRINT EDMACC_0_GINT Reserved EDMACC_0_TC_0_INT EDMACC_0_TC_1_INT EDMACC_0_TC_2_INT EDMACC_0_TC_3_INT EDMACC_0_TC_4_INT EDMACC_0_TC_5_INT EDMACC_0_TC_6_INT EDMACC_0_TC_7_INT Reserved QMSS_QUE_PEND_652 PCIE_INT12 PCIE_INT13 PCIE_INT0 PCIE_INT1 PCIE_INT2 PCIE_INT3 SPI_0_INT0 SPI_0_INT1 SPI_0_XEVT SPI_0_REVT I2C_0_INT I2C_0_REVT I2C_0_XEVT Reserved Reserved DBGTBR_DMAINT MPU_12_INT DBGTBR_ACQCOMP MPU_13_INT MPU_14_INT NETCP_MDIO_LINK_INT0 NETCP_MDIO_LINK_INT1 NETCP_MDIO_USER_INT0 NETCP_MDIO_USER_INT1 NETCP_MISC_INT TRACER_CORE_0_INT TRACER_CORE_1_INT TRACER_CORE_2_INT TRACER_CORE_3_INT TRACER_DDR_INT TRACER_MSMC_0_INT Description EDMA3CC0 TPTC1 error interrupt EDMA3CC0 global completion interrupt Reserved EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt
Table 5-24
Event No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
EDMA3CC0 individual completion interrupt Reserved Navigator transmit queue pending event for indicated queue PCIE protocol error interrupt PCIE power management interrupt PCIE legacy INTA interrupt PCIE legacy INTB interrupt PCIE legacy INTC interrupt PCIE legacy INTD interrupt SPI0 interrupt0 SPI0 interrupt1 SPI0 transmit event SPI0 receive event I2C0 interrupt I2C0 receive event I2C0 transmit event Reserved Reserved Debug trace buffer (TBR) DMA event MPU12 addressing violation interrupt and protection violation interrupt Debug trace buffer (TBR) acquisition has been completed MPU13 addressing violation interrupt and protection violation interrupt MPU14 addressing violation interrupt and protection violation interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem misc interrupt Tracer sliding time window interrupt for DSP0 L2 Tracer sliding time window interrupt for DSP1 L2 Tracer sliding time window interrupt for DSP2 L2 Tracer sliding time window interrupt for DSP3 L2 Tracer sliding time window interrupt for MSMC-DDR3A Tracer sliding time window interrupt for MSMC SRAM bank0
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Event No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122
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Event Name TRACER_MSMC_1_INT TRACER_MSMC_2_INT TRACER_MSMC_3_INT TRACER_CFG_INT TRACER_QMSS_QM_CFG1_INT TRACER_QMSS_DMA_INT TRACER_SEM_INT PSC_ALLINT MSMC_SCRUB_CERROR BOOTCFG_INT SR_0_PO_VCON_SMPSERR_INT MPU_0_INT QMSS_QUE_PEND_653 MPU_1_INT QMSS_QUE_PEND_654 MPU_2_INT QMSS_QUE_PEND_655 MPU_3_INT QMSS_QUE_PEND_656 MSMC_DEDC_CERROR MSMC_DEDC_NC_ERROR MSMC_SCRUB_NC_ERROR MSMC_MPF_ERROR0 MSMC_MPF_ERROR8 MSMC_MPF_ERROR9 MSMC_MPF_ERROR10 MSMC_MPF_ERROR11 MSMC_MPF_ERROR12 MSMC_MPF_ERROR13 MSMC_MPF_ERROR14 MSMC_MPF_ERROR15 DDR3_0_ERR HyperLink_0_INT SRIO_INTDST0 SRIO_INTDST1 SRIO_INTDST2 SRIO_INTDST3 SRIO_INTDST4 SRIO_INTDST5 SRIO_INTDST6 SRIO_INTDST7 SRIO_INTDST8 SRIO_INTDST9 SRIO_INTDST10 Description Tracer sliding time window interrupt for MSMC SRAM bank1 Tracer sliding time window interrupt for MSMC SRAM bank2 Tracer sliding time window interrupt for MSMC SRAM bank3 Tracer sliding time window interrupt for CFG0 TeraNet Tracer sliding time window interrupt for Navigator CFG1 slave port Tracer sliding time window interrupt for Navigator DMA internal bus slave port Tracer sliding time window interrupt for Semaphore Power & Sleep Controller interrupt Correctable (1-bit) soft error detected during scrub cycle Chip-level MMR Error Register SmartReflex SMPS error interrupt MPU0 addressing violation interrupt and protection violation interrupt Navigator transmit queue pending event for indicated queue MPU1 addressing violation interrupt and protection violation interrupt. Navigator transmit queue pending event for indicated queue MPU2 addressing violation interrupt and protection violation interrupt. Navigator transmit queue pending event for indicated queue MPU3 addressing violation interrupt and protection violation interrupt. Navigator transmit queue pending event for indicated queue Correctable (1-bit) soft error detected on SRAM read Non-correctable (2-bit) soft error detected on SRAM read Non-correctable (2-bit) soft error detected during scrub cycle Memory protection fault indicators for system master PrivID = 0 Memory protection fault indicators for system master PrivID = 8 Memory protection fault indicators for system master PrivID = 9 Memory protection fault indicators for system master PrivID = 10 Memory protection fault indicators for system master PrivID = 11 Memory protection fault indicators for system master PrivID = 12 Memory protection fault indicators for system master PrivID = 13 Memory protection fault indicators for system master PrivID = 14 Memory protection fault indicators for system master PrivID = 15 DDR3A_EMIF error interrupt HyperLink 0 interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt
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Event Name SRIO_INTDST11 SRIO_INTDST12 SRIO_INTDST13 SRIO_INTDST14 SRIO_INTDST15 AEMIF_EASYNCERR TRACER_CORE_4_INT TRACER_CORE_5_INT TRACER_CORE_6_INT TRACER_CORE_7_INT QMSS_INTD_1_PKTDMA_0 QMSS_INTD_1_PKTDMA_1 SRIO_INT_PKTDMA_0 NETCP_PKTDMA_INT0 SR_0_SMARTREFLEX_INTREQ0 SR_0_SMARTREFLEX_INTREQ1 SR_0_SMARTREFLEX_INTREQ2 SR_0_SMARTREFLEX_INTREQ3 SR_0_VPNOSMPSACK SR_0_VPEQVALUE SR_0_VPMAXVDD SR_0_VPMINVDD SR_0_VPINIDLE SR_0_VPOPPCHANGEDONE Reserved UART_0_UARTINT UART_0_URXEVT UART_0_UTXEVT QMSS_QUE_PEND_657 QMSS_QUE_PEND_658 QMSS_QUE_PEND_659 QMSS_QUE_PEND_660 QMSS_QUE_PEND_661 QMSS_QUE_PEND_662 QMSS_QUE_PEND_663 QMSS_QUE_PEND_664 QMSS_QUE_PEND_665 SR_0_VPSMPSACK ARM_TBR_DMA ARM_TBR_ACQ ARM_NINTERRIRQ ARM_NAXIERRIRQ SR_0_SR_TEMPSENSOR Description SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt Asynchronous EMIF16 error interrupt Tracer sliding time window interrupt for DSP4 L2 Tracer sliding time window interrupt for DSP5 L2 Tracer sliding time window interrupt for DSP6 L2
Table 5-24
Event No. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
Navigator interrupt for Packet DMA starvation Navigator interrupt for Packet DMA starvation IPC interrupt generation Packet Accelerator0 Packet DMA starvation interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage SmartReflex. The new voltage required is equal to or greater than MaxVdd SmartReflex. The new voltage required is equal to or less than MinVdd SmartReflex indicating that the FSM of voltage processor is in idle SmartReflex indicating that the average frequency error is within the desired limit Reserved UART0 interrupt UART0 receive event UART0 transmit event Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval ARM trace buffer (TBR) DMA event ARM trace buffer (TBR) acquisition has been completed ARM internal memory ECC error interrupt request ARM bus error interrupt request SmartReflex temperature threshold crossing interrupt
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Tracer sliding time window interrupt for DSP7 L2

Event No. 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209
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Event Name SR_0_SR_TIMERINT AIF_ATEVT8 AIF_ATEVT9 AIF_ATEVT10 AIF_ATEVT11 AIF_ATEVT12 AIF_ATEVT13 AIF_ATEVT14 AIF_ATEVT15 TIMER_7_INTL TIMER_7_INTH TIMER_6_INTL TIMER_6_INTH TIMER_5_INTL TIMER_5_INTH TIMER_4_INTL TIMER_4_INTH TIMER_3_INTL TIMER_3_INTH TIMER_2_INTL TIMER_2_INTH TIMER_1_INTL TIMER_1_INTH TIMER_0_INTL TIMER_0_INTH TCP3D_0_INT TCP3D_1_INT Reserved Reserved TCP3D_0_REVT0 TCP3D_0_REVT1 TCP3D_1_REVT0 TCP3D_1_REVT1 Reserved Reserved Reserved Reserved TAC_INT TAC_DEVT0 TAC_DEVT1 AIF_INT EDMACC_4_ERRINT EDMACC_4_MPINT EDMACC_4_TC_0_ERRINT Description SmartReflex internal timer expiration interrupt AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high TCP3d interrupt TCP3d interrupt Reserved Reserved TCP3d event TCP3d event TCP3d event TCP3d event Reserved Reserved Reserved Reserved TAC interrupt TAC debug event TAC debug event AIF interrupt EDMA3CC4 error interrupt EDMA3CC4 memory protection interrupt EDMA3CC4 TPTC0 error interrupt
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Event Name EDMACC_4_TC_1_ERRINT EDMACC_4_GINT EDMACC_4_TC_0_INT EDMACC_4_TC_1_INT EDMACC_4_TC_2_INT EDMACC_4_TC_3_INT EDMACC_4_TC_4_INT EDMACC_4_TC_5_INT EDMACC_4_TC_6_INT EDMACC_4_TC_7_INT EDMACC_3_ERRINT EDMACC_3_MPINT EDMACC_3_TC_0_ERRINT EDMACC_3_TC_1_ERRINT EDMACC_3_GINT EDMACC_3_TC_0_INT EDMACC_3_TC_1_INT EDMACC_3_TC_2_INT EDMACC_3_TC_3_INT EDMACC_3_TC_4_INT EDMACC_3_TC_5_INT EDMACC_3_TC_6_INT EDMACC_3_TC_7_INT UART_1_UARTINT UART_1_URXEVT UART_1_UTXEVT I2C_1_INT I2C_1_REVT I2C_1_XEVT SPI_1_INT0 SPI_1_INT1 SPI_1_XEVT SPI_1_REVT MPU_5_INT MPU_8_INT MPU_9_INT MPU_11_INT MPU_4_INT MPU_6_INT MPU_7_INT MPU_10_INT SPI_2_INT0 SPI_2_INT1 SPI_2_XEVT Description EDMA3CC4 TPTC1 error interrupt EDMA3CC4 GINT EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt
Table 5-24
Event No. 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253
EDMA3CC3 error interrupt EDMA3CC3 memory protection interrupt EDMA3CC3 TPTC0 error interrupt EDMA3CC3 TPTC1 error interrupt EDMA3CC3 GINT EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt UART1 interrupt UART1 receive event UART1 transmit event I2C1 interrupt I2C1 receive event I2C1 transmit event SPI1 interrupt0 SPI1 interrupt1 SPI1 transmit event SPI1 receive event MPU5 addressing violation interrupt and protection violation interrupt MPU8 addressing violation interrupt and protection violation interrupt MPU9 addressing violation interrupt and protection violation interrupt MPU11 addressing violation interrupt and protection violation interrupt MPU4 addressing violation interrupt and protection violation interrupt MPU6 addressing violation interrupt and protection violation interrupt MPU7 addressing violation interrupt and protection violation interrupt MPU10 addressing violation interrupt and protection violation interrupt SPI2 interrupt0 SPI2 interrupt1 SPI2 transmit event
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PRODUCT PREVIEW

Event No. 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297
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Event Name SPI_2_REVT I2C_2_INT I2C_2_REVT I2C_2_XEVT Reserved Reserved Reserved Reserved Reserved Reserved USIM_PONIRQ USIM_RREQ USIM_WREQ BCP_INT0 BCP_INT1 BCP_INT2 BCP_INT3 RAC_0_TRACE_GCCP0 RAC_0_TRACE_GCCP1 RAC_1_TRACE_GCCP0 RAC_1_TRACE_GCCP1 Reserved Reserved Reserved Reserved TAC_DEVT2 TAC_DEVT3 TAC_DEVT4 TAC_DEVT5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved TRACER_RAC_1_INT TRACER_RAC_FE_INT QMSS_QUE_PEND_666 QMSS_QUE_PEND_667 QMSS_QUE_PEND_668 QMSS_QUE_PEND_669 QMSS_QUE_PEND_670 QMSS_QUE_PEND_671 Description SPI2 receive event I2C2 interrupt I2C2 receive event I2C2 transmit event Reserved Reserved Reserved Reserved Reserved Reserved USIM interrupt USIM read DMA event USIM write DMA event BCP interrupt BCP interrupt BCP interrupt BCP interrupt RAC trace RAC trace RAC trace RAC trace Reserved Reserved Reserved Reserved TAC debug TAC debug TAC debug TAC debug Reserved Reserved Reserved Reserved Reserved Reserved Reserved Tracer RAC interrupt Tracer RAC interrupt Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue
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132

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Event Name QMSS_QUE_PEND_8844 QMSS_QUE_PEND_8845 QMSS_QUE_PEND_8846 QMSS_QUE_PEND_8847 QMSS_QUE_PEND_8848 QMSS_QUE_PEND_8849 QMSS_QUE_PEND_8850 QMSS_QUE_PEND_8851 QMSS_QUE_PEND_8852 QMSS_QUE_PEND_8853 QMSS_QUE_PEND_8854 QMSS_QUE_PEND_8855 QMSS_QUE_PEND_8856 QMSS_QUE_PEND_8857 QMSS_QUE_PEND_8858 QMSS_QUE_PEND_8859 QMSS_QUE_PEND_8860 QMSS_QUE_PEND_8861 QMSS_QUE_PEND_8862 QMSS_QUE_PEND_8863 QMSS_INTD_2_PKTDMA_0 QMSS_INTD_2_PKTDMA_1 QMSS_INTD_1_LOW_0 QMSS_INTD_1_LOW_1 QMSS_INTD_1_LOW_2 QMSS_INTD_1_LOW_3 QMSS_INTD_1_LOW_4 QMSS_INTD_1_LOW_5 QMSS_INTD_1_LOW_6 QMSS_INTD_1_LOW_7 QMSS_INTD_1_LOW_8 QMSS_INTD_1_LOW_9 QMSS_INTD_1_LOW_10 QMSS_INTD_1_LOW_11 QMSS_INTD_1_LOW_12 QMSS_INTD_1_LOW_13 QMSS_INTD_1_LOW_14 QMSS_INTD_1_LOW_15 QMSS_INTD_2_LOW_0 QMSS_INTD_2_LOW_1 QMSS_INTD_2_LOW_2 QMSS_INTD_2_LOW_3 QMSS_INTD_2_LOW_4 QMSS_INTD_2_LOW_5 Description Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue
Table 5-24
Event No. 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341
Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator ECC error interrupt Navigator ECC error interrupt Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low
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PRODUCT PREVIEW
Navigator transmit queue pending event for indicated queue

Event No. 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385
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Event Name QMSS_INTD_2_LOW_6 QMSS_INTD_2_LOW_7 QMSS_INTD_2_LOW_8 QMSS_INTD_2_LOW_9 QMSS_INTD_2_LOW_10 QMSS_INTD_2_LOW_11 QMSS_INTD_2_LOW_12 QMSS_INTD_2_LOW_13 QMSS_INTD_2_LOW_14 QMSS_INTD_2_LOW_15 TRACER_EDMACC_0 TRACER_EDMACC_123_INT TRACER_CIC_INT TRACER_MSMC_4_INT TRACER_MSMC_5_INT TRACER_MSMC_6_INT TRACER_MSMC_7_INT TRACER_SPI_ROM_EMIF_INT TRACER_QMSS_QM_CFG2_INT TRACER_TAC_BE_INT Reserved TRACER_DDR_1_INT TRACER_BCR_INT HYPERLINK_1_INT VCP2_0_INT0 VCP2_0_INT1 VCP2_0_INT2 VCP2_0_INT3 VCP2_1_INT0 VCP2_1_INT1 VCP2_1_INT2 VCP2_1_INT3 VCP2_0_REVT0 VCP2_0_XEVT0 VCP2_0_REVT1 VCP2_0_XEVT1 VCP2_0_REVT2 VCP2_0_XEVT2 VCP2_0_REVT3 VCP2_0_XEVT3 VCP2_1_REVT0 VCP2_1_XEVT0 VCP2_1_REVT1 VCP2_1_XEVT1 Description Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Tracer sliding time window interrupt for EDMA3CC0 Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3 Tracer sliding time window interrupt for interrupt controllers (CIC) Tracer sliding time window interrupt for MSMC SRAM bank4 Tracer sliding time window interrupt for MSMC SRAM bank5 Tracer sliding time window interrupt for MSMC SRAM bank6 Tracer sliding time window interrupt for MSMC SRAM bank7 Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules Tracer sliding time window interrupt for QM2 Tracer TAC interrupt Reserved Tracer sliding time window interrupt for DDR3B Tracer sliding time window interrupt for BCR HyperLink 1 interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event
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134

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Event Name VCP2_1_REVT2 VCP2_1_XEVT2 VCP2_1_REVT3 VCP2_1_XEVT3 FFTC_0_INT0 FFTC_0_INT1 FFTC_0_INT2 FFTC_0_INT3 FFTC_1_INT0 FFTC_1_INT1 FFTC_1_INT2 FFTC_1_INT3 FFTC_2_INT0 FFTC_2_INT1 FFTC_2_INT2 FFTC_2_INT3 FFTC_3_INT0 FFTC_3_INT1 FFTC_3_INT2 FFTC_3_INT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF_ATEVT16 AIF_ATEVT17 AIF_ATEVT18 AIF_ATEVT19 AIF_ATEVT20 AIF_ATEVT21 AIF_ATEVT22 AIF_ATEVT23 USB_INT00 USB_INT04 USB_INT05 USB_INT06 USB_INT07 USB_INT08 USB_INT09 USB_INT10 Description VCP event VCP event VCP event VCP event FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt
Table 5-24
Event No. 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429
FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt
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FFTC interrupt

Event No. 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471
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Event Name USB_INT11 USB_MISCINT USB_OABSINT TIMER_12_INTL TIMER_12_INTH TIMER_13_INTL TIMER_13_INTH TIMER_14_INTL TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH TIMER_16_INTL TIMER_17_INTL TIMER_18_INTL TIMER_19_INTL DDR3_1_ERR GPIO_INT16 GPIO_INT17 GPIO_INT18 GPIO_INT19 GPIO_INT20 GPIO_INT21 GPIO_INT22 GPIO_INT23 GPIO_INT24 GPIO_INT25 GPIO_INT26 GPIO_INT27 GPIO_INT28 GPIO_INT29 GPIO_INT30 GPIO_INT31 SRIO_INTDST16 SRIO_INTDST17 SRIO_INTDST18 SRIO_INTDST19 PCIE_INT4 PCIE_INT5 PCIE_INT6 PCIE_INT7 SEM_INT12 SEM_INT13 Description USB interrupt USB miscellaneous interrupt USB OABS interrupt Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high DDR3B_EMIF error interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt SRIOI interrupt SRIOI interrupt SRIOI interrupt SRIOI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt Semaphore interrupt Semaphore interrupt
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136

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Event Name SEM_ERR12 SEM_ERR13 Description Semaphore error interrupt Semaphore error interrupt
Table 5-24
Event No. 472 473
End of Table 5-24
Table 5-25
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Event Name EDMACC_1_ERRINT EDMACC_1_MPINT EDMACC_1_TC_0_ERRINT EDMACC_1_TC_1_ERRINT EDMACC_1_TC_2_ERRINT EDMACC_1_TC_3_ERRINT EDMACC_1_GINT Reserved EDMACC_1_TC_0_INT EDMACC_1_TC_1_INT EDMACC_1_TC_2_INT EDMACC_1_TC_3_INT EDMACC_1_TC_4_INT EDMACC_1_TC_5_INT EDMACC_1_TC_6_INT EDMACC_1_TC_7_INT EDMACC_2_ERRINT EDMACC_2_MPINT EDMACC_2_TC_0_ERRINT EDMACC_2_TC_1_ERRINT EDMACC_2_TC_2_ERRINT EDMACC_2_TC_3_ERRINT EDMACC_2_GINT Reserved EDMACC_2_TC_0_INT EDMACC_2_TC_1_INT EDMACC_2_TC_2_INT EDMACC_2_TC_3_INT EDMACC_2_TC_4_INT EDMACC_2_TC_5_INT EDMACC_2_TC_6_INT EDMACC_2_TC_7_INT EDMACC_0_ERRINT EDMACC_0_MPINT EDMACC_0_TC_0_ERRINT EDMACC_0_TC_1_ERRINT EDMACC_0_GINT Reserved Description EDMA3CC1 error interrupt EDMA3CC1 memory protection interrupt EDMA3CC1 TPTC0 error interrupt
EDMA3CC1 TPTC2 error interrupt EDMA3CC1 TPTC3 error interrupt EDMA3CC1 GINT Reserved EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC1 individual completion interrupt EDMA3CC2 error interrupt EDMA3CC2 memory protection interrupt EDMA3CC2 TPTC0 error interrupt EDMA3CC2 TPTC1 error interrupt EDMA3CC2 TPTC2 error interrupt EDMA3CC2 TPTC3 error interrupt EDMA3CC2 GINT Reserved EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC2 individual completion interrupt EDMA3CC0 error interrupt EDMA3CC0 memory protection interrupt EDMA3CC0 TPTC0 error interrupt EDMA3CC0 TPTC1 error interrupt EDMA3CC0 GINT Reserved
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PRODUCT PREVIEW
EDMA3CC1 TPTC1 error interrupt

Event No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
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Event Name EDMACC_0_TC_0_INT EDMACC_0_TC_1_INT EDMACC_0_TC_2_INT EDMACC_0_TC_3_INT EDMACC_0_TC_4_INT EDMACC_0_TC_5_INT EDMACC_0_TC_6_INT EDMACC_0_TC_7_INT Reserved QMSS_QUE_PEND_658 PCIE_INT12 PCIE_INT13 PCIE_INT0 PCIE_INT1 PCIE_INT2 PCIE_INT3 SPI_0_INT0 SPI_0_INT1 SPI_0_XEVT SPI_0_REVT I2C_0_INT I2C_0_REVT I2C_0_XEVT Reserved Reserved DBGTBR_DMAINT MPU_12_INT DBGTBR_ACQCOMP MPU_13_INT MPU_14_INT NETCP_MDIO_LINK_INT0 NETCP_MDIO_LINK_INT1 NETCP_MDIO_USER_INT0 NETCP_MDIO_USER_INT1 NETCP_MISC_INT TRACER_CORE_0_INT TRACER_CORE_1_INT TRACER_CORE_2_INT TRACER_CORE_3_INT TRACER_DDR_INT TRACER_MSMC_0_INT TRACER_MSMC_1_INT TRACER_MSMC_2_INT TRACER_MSMC_3_INT Description EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt EDMA3CC0 individual completion interrupt Reserved Navigator transmit queue pending event for indicated queue PCIE interrupt PCIE interrupt PCIE interrupt PCIE interrupt PCIE interrupt PCIE interrupt SPI0 interrupt SPI0 interrupt SPI0 transmit event SPI0 receive event I2C0 interrupt I2C0 receive event I2C0 transmit event Reserved Reserved Debug trace buffer (TBR) DMA event MPU12 interrupt Debug trace buffer (TBR) acquisition has been completed MPU13 interrupt MPU14 interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem misc interrupt Tracer sliding time window interrupt for DSP0 L2 Tracer sliding time window interrupt for DSP1 L2 Tracer sliding time window interrupt for DSP2 L2 Tracer sliding time window interrupt for DSP3 L2 Tracer sliding time window interrupt for MSMC-DDR3A Tracer sliding time window interrupt for MSMC SRAM bank0 Tracer sliding time window interrupt for MSMC SRAM bank1 Tracer sliding time window interrupt for MSMC SRAM bank2 Tracer sliding time window interrupt for MSMC SRAM bank3
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138

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Event Name TRACER_CFG_INT TRACER_QMSS_QM_CFG1_INT TRACER_QMSS_DMA_INT TRACER_SEM_INT PSC_ALLINT MSMC_SCRUB_CERROR BOOTCFG_INT SR_0_PO_VCON_SMPSERR_INT MPU_0_INT QMSS_QUE_PEND_659 MPU_1_INT QMSS_QUE_PEND_660 MPU_2_INT QMSS_QUE_PEND_661 MPU_3_INT QMSS_QUE_PEND_662 MSMC_DEDC_CERROR MSMC_DEDC_NC_ERROR MSMC_SCRUB_NC_ERROR Reserved MSMC_MPF_ERROR8 MSMC_MPF_ERROR9 MSMC_MPF_ERROR10 MSMC_MPF_ERROR11 MSMC_MPF_ERROR12 MSMC_MPF_ERROR13 MSMC_MPF_ERROR14 MSMC_MPF_ERROR15 DDR3_0_ERR HyperLink_0_INT SRIO_INTDST0 SRIO_INTDST1 SRIO_INTDST2 SRIO_INTDST3 SRIO_INTDST4 SRIO_INTDST5 SRIO_INTDST6 SRIO_INTDST7 SRIO_INTDST8 SRIO_INTDST9 SRIO_INTDST10 SRIO_INTDST11 SRIO_INTDST12 SRIO_INTDST13 Description Tracer sliding time window interrupt for CFG0 TeraNet Tracer sliding time window interrupt for Navigator CFG1 slave port Tracer sliding time window interrupt for Navigator DMA internal bus slave port Tracer sliding time window interrupt for Semaphore Power & Sleep Controller interrupt Correctable (1-bit) soft error detected during scrub cycle Chip-level MMR Error Register SmartReflex SMPS error interrupt MPU0 addressing violation interrupt and protection violation interrupt.
Table 5-25
Event No. 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
MPU1 addressing violation interrupt and protection violation interrupt. Navigator transmit queue pending event for indicated queue MPU2 addressing violation interrupt and protection violation interrupt. Navigator transmit queue pending event for indicated queue MPU3 addressing violation interrupt and protection violation interrupt. Navigator transmit queue pending event for indicated queue Correctable (1-bit) soft error detected on SRAM read Non-correctable (2-bit) soft error detected on SRAM read Non-correctable (2-bit) soft error detected during scrub cycle Reserved Memory protection fault indicators for system master PrivID = 8 Memory protection fault indicators for system master PrivID = 9 Memory protection fault indicators for system master PrivID = 10 Memory protection fault indicators for system master PrivID = 11 Memory protection fault indicators for system master PrivID = 12 Memory protection fault indicators for system master PrivID = 13 Memory protection fault indicators for system master PrivID = 14 Memory protection fault indicators for system master PrivID = 15 DDR3A_EMIF Error interrupt HyperLink 0 interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt
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PRODUCT PREVIEW
Navigator transmit queue pending event for indicated queue

Event No. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
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Event Name SRIO_INTDST14 SRIO_INTDST15 AEMIF_EASYNCERR TRACER_CORE_4_INT TRACER_CORE_5_INT TRACER_CORE_6_INT TRACER_CORE_7_INT QMSS_INTD_1_PKTDMA_0 QMSS_INTD_1_PKTDMA_1 SRIO_INT_PKTDMA_0 NETCP_PKTDMA_INT0 SR_0_SMARTREFLEX_INTREQ0 SR_0_SMARTREFLEX_INTREQ1 SR_0_SMARTREFLEX_INTREQ2 SR_0_SMARTREFLEX_INTREQ3 SR_0_VPNOSMPSACK SR_0_VPEQVALUE SR_0_VPMAXVDD SR_0_VPMINVDD SR_0_VPINIDLE SR_0_VPOPPCHANGEDONE Reserved UART_0_UARTINT UART_0_URXEVT UART_0_UTXEVT QMSS_QUE_PEND_663 QMSS_QUE_PEND_664 QMSS_QUE_PEND_665 QMSS_QUE_PEND_666 QMSS_QUE_PEND_667 QMSS_QUE_PEND_668 QMSS_QUE_PEND_669 QMSS_QUE_PEND_670 QMSS_QUE_PEND_671 SR_0_VPSMPSACK ARM_TBR_DMA ARM_TBR_ACQ ARM_NINTERRIRQ ARM_NAXIERRIRQ SR_0_SR_TEMPSENSOR SR_0_SR_TIMERINT AIF_ATEVT8 AIF_ATEVT9 Description SRIO interrupt SRIO interrupt Asynchronous EMIF16 error interrupt Tracer sliding time window interrupt for DSP4 L2 Tracer sliding time window interrupt for DSP5 L2 Tracer sliding time window interrupt for DSP6 L2 Tracer sliding time window interrupt for DSP7 L2 Navigator interrupt for Packet DMA starvation Navigator interrupt for Packet DMA starvation IPC interrupt generation Packet Accelerator0 Packet DMA starvation interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex controller interrupt SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage SmartReflex. The new voltage required is equal to or greater than MaxVdd SmartReflex. The new voltage required is equal to or less than MinVdd SmartReflex indicating that the FSM of voltage processor is in idle SmartReflex indicating that the average frequency error is within the desired limit Reserved UART0 interrupt UART0 receive event UART0 transmit event Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval ARM trace buffer (TBR) DMA event ARM trace buffer (TBR) Acquisition has been completed ARM internal memory ECC error interrupt request ARM bus error interrupt request SmartReflex temperature threshold crossing interrupt SmartReflex internal timer expiration interrupt AIF timer event AIF timer event
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140

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Event Name AIF_ATEVT10 AIF_ATEVT11 AIF_ATEVT12 AIF_ATEVT13 AIF_ATEVT14 AIF_ATEVT15 TIMER_7_INTL TIMER_7_INTH TIMER_6_INTL TIMER_6_INTH TIMER_5_INTL TIMER_5_INTH TIMER_4_INTL TIMER_4_INTH TIMER_3_INTL TIMER_3_INTH TIMER_2_INTL TIMER_2_INTH TIMER_1_INTL TIMER_1_INTH TIMER_0_INTL TIMER_0_INTH TCP3D_0_INT TCP3D_1_INT Reserved Reserved TCP3D_0_REVT0 TCP3D_0_REVT1 TCP3D_1_REVT0 TCP3D_1_REVT1 Reserved Reserved Reserved Reserved TAC_INT TAC_DEVT0 TAC_DEVT1 AIF_INT EDMACC_4_ERRINT EDMACC_4_MPINT EDMACC_4_TC_0_ERRINT EDMACC_4_TC_1_ERRINT EDMACC_4_GINT EDMACC_4_TC_0_INT Description AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event Timer interrupt low Timer interrupt high Timer interrupt low
Table 5-25
Event No. 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212
Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high TCP3d interrupt TCP3d interrupt Reserved Reserved TCP3d event TCP3d event TCP3d event TCP3d event Reserved Reserved Reserved Reserved TAC interrupt TAC debug event TAC debug event AIF interrupt EDMA3CC4 error interrupt EDMA3CC4 memory protection interrupt EDMA3CC4 TPTC0 error interrupt EDMA3CC4 TPTC1 error interrupt EDMA3CC4 GINT EDMA3CC4 individual completion interrupt
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Event No. 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256
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Event Name EDMACC_4_TC_1_INT EDMACC_4_TC_2_INT EDMACC_4_TC_3_INT EDMACC_4_TC_4_INT EDMACC_4_TC_5_INT EDMACC_4_TC_6_INT EDMACC_4_TC_7_INT EDMACC_3_ERRINT EDMACC_3_MPINT EDMACC_3_TC_0_ERRINT EDMACC_3_TC_1_ERRINT EDMACC_3_GINT EDMACC_3_TC_0_INT EDMACC_3_TC_1_INT EDMACC_3_TC_2_INT EDMACC_3_TC_3_INT EDMACC_3_TC_4_INT EDMACC_3_TC_5_INT EDMACC_3_TC_6_INT EDMACC_3_TC_7_INT UART_1_UARTINT UART_1_URXEVT UART_1_UTXEVT I2C_1_INT I2C_1_REVT I2C_1_XEVT SPI_1_INT0 SPI_1_INT1 SPI_1_XEVT SPI_1_REVT MPU_5_INT MPU_8_INT MPU_9_INT MPU_11_INT MPU_4_INT MPU_6_INT MPU_7_INT MPU_10_INT SPI_2_INT0 SPI_2_INT1 SPI_2_XEVT SPI_2_REVT I2C_2_INT I2C_2_REVT Description EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC4 individual completion interrupt EDMA3CC3 error interrupt EDMA3CC3 memory protection interrupt EDMA3CC3 TPTC0 error interrupt EDMA3CC3 TPTC1 error interrupt EDMA3CC3 GINT EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt EDMA3CC3 individual completion interrupt UART1 interrupt UART1 receive event UART1 transmit event I2C1 interrupt I2C1 receive event I2C1 transmit event SPI1 interrupt0 SPI1 interrupt1 SPI1 transmit event SPI1 receive event MPU5 addressing violation interrupt and protection violation interrupt MPU8 addressing violation interrupt and protection violation interrupt MPU9 addressing violation interrupt and protection violation interrupt MPU11 addressing violation interrupt and protection violation interrupt MPU4 addressing violation interrupt and protection violation interrupt MPU6 addressing violation interrupt and protection violation interrupt MPU7 addressing violation interrupt and protection violation interrupt MPU10 addressing violation interrupt and protection violation interrupt SPI2 interrupt0 SPI2 interrupt1 SPI2 transmit event SPI2 receive event I2C2 interrupt I2C2 receive event
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Event Name I2C_2_XEVT Reserved Reserved Reserved Reserved Reserved Reserved USIM_PONIRQ USIM_RREQ USIM_WREQ BCP_INT0 BCP_INT1 BCP_INT2 BCP_INT3 RAC_0_TRACE_GCCP0 RAC_0_TRACE_GCCP1 RAC_1_TRACE_GCCP0 RAC_1_TRACE_GCCP1 Reserved Reserved Reserved Reserved TAC_DEVT2 TAC_DEVT3 TAC_DEVT4 TAC_DEVT5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved TRACER_RAC_1_INT TRACER_RAC_FE_INT QMSS_QUE_PEND_652 QMSS_QUE_PEND_653 QMSS_QUE_PEND_654 QMSS_QUE_PEND_655 QMSS_QUE_PEND_656 QMSS_QUE_PEND_657 QMSS_QUE_PEND_8844 QMSS_QUE_PEND_8845 QMSS_QUE_PEND_8846 Description I2C2 transmit event Reserved Reserved Reserved Reserved Reserved Reserved USIM interrupt USIM read DMA event
Table 5-25
Event No. 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
BCP interrupt BCP interrupt BCP interrupt BCP interrupt RAC trace RAC trace RAC trace RAC trace Reserved Reserved Reserved Reserved TAC debug TAC debug TAC debug TAC debug Reserved Reserved Reserved Reserved Reserved Reserved Reserved Tracer RAC interrupt Tracer RAC interrupt Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue
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PRODUCT PREVIEW
USIM write DMA event

Event No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344
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Event Name QMSS_QUE_PEND_8847 QMSS_QUE_PEND_8848 QMSS_QUE_PEND_8849 QMSS_QUE_PEND_8850 QMSS_QUE_PEND_8851 QMSS_QUE_PEND_8852 QMSS_QUE_PEND_8853 QMSS_QUE_PEND_8854 QMSS_QUE_PEND_8855 QMSS_QUE_PEND_8856 QMSS_QUE_PEND_8857 QMSS_QUE_PEND_8858 QMSS_QUE_PEND_8859 QMSS_QUE_PEND_8860 QMSS_QUE_PEND_8861 QMSS_QUE_PEND_8862 QMSS_QUE_PEND_8863 QMSS_INTD_2_PKTDMA_0 QMSS_INTD_2_PKTDMA_1 QMSS_INTD_1_LOW_0 QMSS_INTD_1_LOW_1 QMSS_INTD_1_LOW_2 QMSS_INTD_1_LOW_3 QMSS_INTD_1_LOW_4 QMSS_INTD_1_LOW_5 QMSS_INTD_1_LOW_6 QMSS_INTD_1_LOW_7 QMSS_INTD_1_LOW_8 QMSS_INTD_1_LOW_9 QMSS_INTD_1_LOW_10 QMSS_INTD_1_LOW_11 QMSS_INTD_1_LOW_12 QMSS_INTD_1_LOW_13 QMSS_INTD_1_LOW_14 QMSS_INTD_1_LOW_15 QMSS_INTD_2_LOW_0 QMSS_INTD_2_LOW_1 QMSS_INTD_2_LOW_2 QMSS_INTD_2_LOW_3 QMSS_INTD_2_LOW_4 QMSS_INTD_2_LOW_5 QMSS_INTD_2_LOW_6 QMSS_INTD_2_LOW_7 QMSS_INTD_2_LOW_8 Description Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator ECC error interrupt Navigator ECC error interrupt Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low
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Event Name QMSS_INTD_2_LOW_9 QMSS_INTD_2_LOW_10 QMSS_INTD_2_LOW_11 QMSS_INTD_2_LOW_12 QMSS_INTD_2_LOW_13 QMSS_INTD_2_LOW_14 QMSS_INTD_2_LOW_15 TRACER_EDMACC_0 TRACER_EDMACC_123_INT TRACER_CIC_INT TRACER_MSMC_4_INT TRACER_MSMC_5_INT TRACER_MSMC_6_INT TRACER_MSMC_7_INT TRACER_SPI_ROM_EMIF_INT TRACER_QMSS_QM_CFG2_INT TRACER_TAC_BE_INT Reserved TRACER_DDR_1_INT TRACER_BCR_INT HyperLink_1_INT VCP2_0_INT0 VCP2_0_INT1 VCP2_0_INT2 VCP2_0_INT3 VCP2_1_INT0 VCP2_1_INT1 VCP2_1_INT2 VCP2_1_INT3 VCP2_0_REVT0 VCP2_0_XEVT0 VCP2_0_REVT1 VCP2_0_XEVT1 VCP2_0_REVT2 VCP2_0_XEVT2 VCP2_0_REVT3 VCP2_0_XEVT3 VCP2_1_REVT0 VCP2_1_XEVT0 VCP2_1_REVT1 VCP2_1_XEVT1 VCP2_1_REVT2 VCP2_1_XEVT2 VCP2_1_REVT3 Description Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Navigator second interrupt low Tracer sliding time window interrupt for EDMA3CC0 Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
Table 5-25
Event No. 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388
Tracer sliding time window interrupt for MSMC SRAM bank4 Tracer sliding time window interrupt for MSMC SRAM bank5 Tracer sliding time window interrupt for MSMC SRAM bank6 Tracer sliding time window interrupt for MSMC SRAM bank7 Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules Tracer sliding time window interrupt for QM2 Tracer TAC interrupt Reserved Tracer sliding time window interrupt for DDR3B Tracer sliding time window interrupt for BCR HyperLink 1 interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event
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Tracer sliding time window interrupt for interrupt controllers (CIC)

Event No. 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432
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Event Name VCP2_1_XEVT3 FFTC_0_INT0 FFTC_0_INT1 FFTC_0_INT2 FFTC_0_INT3 FFTC_1_INT0 FFTC_1_INT1 FFTC_1_INT2 FFTC_1_INT3 FFTC_2_INT0 FFTC_2_INT1 FFTC_2_INT2 FFTC_2_INT3 FFTC_3_INT0 FFTC_3_INT1 FFTC_3_INT2 FFTC_3_INT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF_ATEVT16 AIF_ATEVT17 AIF_ATEVT18 AIF_ATEVT19 AIF_ATEVT20 AIF_ATEVT21 AIF_ATEVT22 AIF_ATEVT23 USB_INT00 USB_INT04 USB_INT05 USB_INT06 USB_INT07 USB_INT08 USB_INT09 USB_INT10 USB_INT11 USB_MISCINT USB_OABSINT Description VCP event FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB miscellaneous interrupt USB OABS interrupt
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Event Name TIMER_12_INTL TIMER_12_INTH TIMER_13_INTL TIMER_13_INTH TIMER_14_INTL TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH TIMER_16_INTL TIMER_17_INTL TIMER_18_INTL TIMER_19_INTL DDR3_1_ERR GPIO_INT16 GPIO_INT17 GPIO_INT18 GPIO_INT19 GPIO_INT20 GPIO_INT21 GPIO_INT22 GPIO_INT23 GPIO_INT24 GPIO_INT25 GPIO_INT26 GPIO_INT27 GPIO_INT28 GPIO_INT29 GPIO_INT30 GPIO_INT31 SRIO_INTDST20 SRIO_INTDST21 SRIO_INTDST22 SRIO_INTDST23 PCIE_INT8 PCIE_INT9 PCIE_INT10 PCIE_INT11 SEM_INT12 SEM_INT13 SEM_ERR12 SEM_ERR13 Reserved Description Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low
Table 5-25
Event No. 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474
Timer interrupt low Timer interrupt high DDR3B_EMIF error interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt SRIOI interrupt SRIOI interrupt SRIOI interrupt SRIOI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt PCIE MSI interrupt Semaphore interrupt Semaphore interrupt Semaphore error interrupt Semaphore error interrupt Reserved
End of Table 5-25
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Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
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CIC2 Event Inputs (Secondary Events for EDMA3CC0 and HyperLinks) (Part 1 of 11)
Event Name GPIO_INT8 GPIO_INT9 GPIO_INT10 GPIO_INT11 GPIO_INT12 GPIO_INT13 GPIO_INT14 GPIO_INT15 DBGTBR_DMAINT Reserved Reserved TETB_FULLINT0 TETB_HFULLINT0 TETB_ACQINT0 TETB_FULLINT1 TETB_HFULLINT1 TETB_ACQINT1 TETB_FULLINT2 TETB_HFULLINT2 TETB_ACQINT2 TETB_FULLINT3 TETB_HFULLINT3 TETB_ACQINT3 Reserved QMSS_INTD_1_HIGH_16 QMSS_INTD_1_HIGH_17 QMSS_INTD_1_HIGH_18 QMSS_INTD_1_HIGH_19 QMSS_INTD_1_HIGH_20 QMSS_INTD_1_HIGH_21 QMSS_INTD_1_HIGH_22 QMSS_INTD_1_HIGH_23 QMSS_INTD_1_HIGH_24 QMSS_INTD_1_HIGH_25 QMSS_INTD_1_HIGH_26 QMSS_INTD_1_HIGH_27 QMSS_INTD_1_HIGH_28 QMSS_INTD_1_HIGH_29 QMSS_INTD_1_HIGH_30 QMSS_INTD_1_HIGH_31 NETCP_MDIO_LINK_INT0 NETCP_MDIO_LINK_INT1 NETCP_MDIO_USER_INT0 NETCP_MDIO_USER_INT1 Description GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt Debug trace buffer (TBR) DMA event Reserved Reserved TETB0 is full TETB0 is half full TETB0 acquisition has been completed TETB1 is full TETB1 is half full TETB1 acquisition has been completed TETB2 is full TETB2 is half full TETB2 acquisition has been completed TETB3 is full TETB3 is half full TETB3 acquisition has been completed Reserved Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt Packet Accelerator 0 subsystem MDIO interrupt
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SPRS835DAugust 2013 CIC2 Event Inputs (Secondary Events for EDMA3CC0 and HyperLinks) (Part 2 of 11)
Event Name NETCP_MISC_INT TRACER_CORE_0_INT TRACER_CORE_1_INT TRACER_CORE_2_INT TRACER_CORE_3_INT TRACER_DDR_INT TRACER_MSMC_0_INT TRACER_MSMC_1_INT TRACER_MSMC_2_INT TRACER_MSMC_3_INT TRACER_CFG_INT TRACER_QMSS_QM_CFG1_INT TRACER_QMSS_DMA_INT TRACER_SEM_INT SEM_ERR0 SEM_ERR1 SEM_ERR2 SEM_ERR3 BOOTCFG_INT NETCP_PKTDMA_INT0 MPU_0_INT MSMC_SCRUB_CERROR MPU_1_INT SRIO_INT_PKTDMA_0 MPU_2_INT QMSS_INTD_1_PKTDMA_0 MPU_3_INT QMSS_INTD_1_PKTDMA_1 MSMC_DEDC_CERROR MSMC_DEDC_NC_ERROR MSMC_SCRUB_NC_ERROR Reserved MSMC_MPF_ERROR0 MSMC_MPF_ERROR1 MSMC_MPF_ERROR2 MSMC_MPF_ERROR3 MSMC_MPF_ERROR4 MSMC_MPF_ERROR5 MSMC_MPF_ERROR6 MSMC_MPF_ERROR7 MSMC_MPF_ERROR8 MSMC_MPF_ERROR9 MSMC_MPF_ERROR10 MSMC_MPF_ERROR11 Description Packet Accelerator 0 subsystem MDIO interrupt Tracer sliding time window interrupt for DSP0 L2 Tracer sliding time window interrupt for DSP1 L2 Tracer sliding time window interrupt for DSP2 L2 Tracer sliding time window interrupt for DSP3 L2 Tracer sliding time window interrupt for MSMC-DDR3A Tracer sliding time window interrupt for MSMC SRAM bank0 Tracer sliding time window interrupt for MSMC SRAM bank1 Tracer sliding time window interrupt for MSMC SRAM bank2
Table 5-26
Event No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
Tracer sliding time window interrupt for TeraNet CFG Tracer sliding time window interrupt for Navigator CFG1 slave port Tracer sliding time window interrupt for Navigator DMA internal bus slave port Tracer sliding time window interrupt for Semaphore interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt BOOTCFG error interrupt Packet Accelerator0 Packet DMA starvation interrupt MPU0 interrupt MSMC error interrupt MPU1 interrupt Packet Accelerator0 Packet DMA interrupt MPU2 interrupt Navigator Packet DMA interrupt MPU3 interrupt Navigator Packet DMA interrupt MSMC error interrupt MSMC error interrupt MSMC error interrupt Reserved Memory protection fault indicators for system master PrivID = 0 Memory protection fault indicators for system master PrivID = 1 Memory protection fault indicators for system master PrivID = 2 Memory protection fault indicators for system master PrivID = 3 Memory protection fault indicators for system master PrivID = 4 Memory protection fault indicators for system master PrivID = 5 Memory protection fault indicators for system master PrivID = 6 Memory protection fault indicators for system master PrivID = 7 Memory protection fault indicators for system master PrivID = 8 Memory protection fault indicators for system master PrivID = 9 Memory protection fault indicators for system master PrivID = 10 Memory protection fault indicators for system master PrivID = 11
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Tracer sliding time window interrupt for MSMC SRAM bank3

Event No. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
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Event Name MSMC_MPF_ERROR12 MSMC_MPF_ERROR13 MSMC_MPF_ERROR14 MSMC_MPF_ERROR15 Reserved SRIO_INTDST0 SRIO_INTDST1 SRIO_INTDST2 SRIO_INTDST3 SRIO_INTDST4 SRIO_INTDST5 SRIO_INTDST6 SRIO_INTDST7 SRIO_INTDST8 SRIO_INTDST9 SRIO_INTDST10 SRIO_INTDST11 SRIO_INTDST12 SRIO_INTDST13 SRIO_INTDST14 SRIO_INTDST15 SRIO_INTDST16 SRIO_INTDST17 SRIO_INTDST18 SRIO_INTDST19 SRIO_INTDST20 SRIO_INTDST21 SRIO_INTDST22 SRIO_INTDST23 AEMIF_EASYNCERR TETB_FULLINT4 TETB_HFULLINT4 TETB_ACQINT4 TETB_FULLINT5 TETB_HFULLINT5 TETB_ACQINT5 TETB_FULLINT6 TETB_HFULLINT6 TETB_ACQINT6 TETB_FULLINT7 TETB_HFULLINT7 TETB_ACQINT7 TRACER_CORE_4_INT TRACER_CORE_5_INT Description Memory protection fault indicators for system master PrivID = 12 Memory protection fault indicators for system master PrivID = 13 Memory protection fault indicators for system master PrivID = 14 Memory protection fault indicators for system master PrivID = 15 Reserved SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt Asynchronous EMIF16 error interrupt TETB4 is full TETB4 is half full TETB4 acquisition has been completed TETB5 is full TETB5 is half full TETB5 acquisition has been completed TETB6 is full TETB6 is half full TETB6 acquisition has been completed TETB7 is full TETB7 is half full TETB7 acquisition has been completed Tracer sliding time window interrupt for DSP4 L2 Tracer sliding time window interrupt for DSP5 L2
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Event Name TRACER_CORE_6_INT TRACER_CORE_7_INT SEM_ERR4 SEM_ERR5 SEM_ERR6 SEM_ERR7 QMSS_INTD_1_HIGH_0 QMSS_INTD_1_HIGH_1 QMSS_INTD_1_HIGH_2 QMSS_INTD_1_HIGH_3 QMSS_INTD_1_HIGH_4 QMSS_INTD_1_HIGH_5 QMSS_INTD_1_HIGH_6 QMSS_INTD_1_HIGH_7 QMSS_INTD_1_HIGH_8 QMSS_INTD_1_HIGH_9 QMSS_INTD_1_HIGH_10 QMSS_INTD_1_HIGH_11 QMSS_INTD_1_HIGH_12 QMSS_INTD_1_HIGH_13 QMSS_INTD_1_HIGH_14 QMSS_INTD_1_HIGH_15 QMSS_INTD_2_HIGH_0 QMSS_INTD_2_HIGH_1 QMSS_INTD_2_HIGH_2 QMSS_INTD_2_HIGH_3 QMSS_INTD_2_HIGH_4 QMSS_INTD_2_HIGH_5 QMSS_INTD_2_HIGH_6 QMSS_INTD_2_HIGH_7 QMSS_INTD_2_HIGH_8 QMSS_INTD_2_HIGH_9 QMSS_INTD_2_HIGH_10 QMSS_INTD_2_HIGH_11 QMSS_INTD_2_HIGH_12 QMSS_INTD_2_HIGH_13 QMSS_INTD_2_HIGH_14 QMSS_INTD_2_HIGH_15 QMSS_INTD_2_HIGH_16 QMSS_INTD_2_HIGH_17 QMSS_INTD_2_HIGH_18 QMSS_INTD_2_HIGH_19 QMSS_INTD_2_HIGH_20 QMSS_INTD_2_HIGH_21 Description Tracer sliding time window interrupt for DSP6 L2 Tracer sliding time window interrupt for DSP7 L2 Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt
Table 5-26
Event No. 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt
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Navigator hi interrupt

Event No. 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219
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Event Name QMSS_INTD_2_HIGH_22 QMSS_INTD_2_HIGH_23 QMSS_INTD_2_HIGH_24 QMSS_INTD_2_HIGH_25 QMSS_INTD_2_HIGH_26 QMSS_INTD_2_HIGH_27 QMSS_INTD_2_HIGH_28 QMSS_INTD_2_HIGH_29 QMSS_INTD_2_HIGH_30 QMSS_INTD_2_HIGH_31 MPU_12_INT MPU_13_INT MPU_14_INT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TRACER_QMSS_QM_CFG2_INT TRACER_EDMACC_0 TRACER_EDMACC_123_INT TRACER_CIC_INT MPU_4_INT MPU_5_INT MPU_6_INT MPU_7_INT MPU_8_INT QMSS_INTD_2_PKTDMA_0 QMSS_INTD_2_PKTDMA_1 SR_0_VPSMPSACK DDR3_0_ERR HyperLink_0_INT EDMACC_0_ERRINT EDMACC_0_MPINT EDMACC_0_TC_0_ERRINT EDMACC_0_TC_1_ERRINT EDMACC_1_ERRINT EDMACC_1_MPINT EDMACC_1_TC_0_ERRINT Description Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt Navigator second hi interrupt MPU12 addressing violation interrupt and protection violation interrupt MPU13 addressing violation interrupt and protection violation interrupt MPU14 addressing violation interrupt and protection violation interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Tracer sliding time window interrupt for Navigator CFG2 slave port Tracer sliding time window interrupt foR EDMA3CC0 Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3 Tracer sliding time window interrupt for interrupt controllers (CIC) MPU4 addressing violation interrupt and protection violation interrupt MPU5 addressing violation interrupt and protection violation interrupt MPU6 addressing violation interrupt and protection violation interrupt MPU7 addressing violation interrupt and protection violation interrupt MPU8 addressing violation interrupt and protection violation interrupt Navigator ECC error interrupt Navigator ECC error interrupt SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval DDR3A error interrupt HyperLink 0 interrupt EDMA3CC0 error interrupt EDMA3CC0 memory protection interrupt EDMA3CC0 TPTC0 error interrupt EDMA3CC0 TPTC1 error interrupt EDMA3CC1 error interrupt EDMA3CC1 memory protection interrupt EDMA3CC1 TPTC0 error interrupt
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Event Name EDMACC_1_TC_1_ERRINT EDMACC_1_TC_2_ERRINT EDMACC_1_TC_3_ERRINT EDMACC_2_ERRINT EDMACC_2_MPINT EDMACC_2_TC_0_ERRINT EDMACC_2_TC_1_ERRINT EDMACC_2_TC_2_ERRINT EDMACC_2_TC_3_ERRINT EDMACC_3_ERRINT EDMACC_3_MPINT EDMACC_3_TC_0_ERRINT EDMACC_3_TC_1_ERRINT EDMACC_4_ERRINT EDMACC_4_MPINT EDMACC_4_TC_0_ERRINT EDMACC_4_TC_1_ERRINT QMSS_QUE_PEND_652 QMSS_QUE_PEND_653 QMSS_QUE_PEND_654 QMSS_QUE_PEND_655 QMSS_QUE_PEND_656 QMSS_QUE_PEND_657 QMSS_QUE_PEND_658 QMSS_QUE_PEND_659 QMSS_QUE_PEND_660 QMSS_QUE_PEND_661 QMSS_QUE_PEND_662 QMSS_QUE_PEND_663 QMSS_QUE_PEND_664 QMSS_QUE_PEND_665 QMSS_QUE_PEND_666 QMSS_QUE_PEND_667 QMSS_QUE_PEND_668 QMSS_QUE_PEND_669 QMSS_QUE_PEND_670 QMSS_QUE_PEND_671 QMSS_QUE_PEND_8844 QMSS_QUE_PEND_8845 QMSS_QUE_PEND_8846 QMSS_QUE_PEND_8847 QMSS_QUE_PEND_8848 QMSS_QUE_PEND_8849 QMSS_QUE_PEND_8850 Description EDMA3CC1 TPTC1 error interrupt EDMA3CC1 TPTC2 error interrupt EDMA3CC1 TPTC3 error interrupt EDMA3CC2 error interrupt EDMA3CC2 memory protection interrupt EDMA3CC2 TPTC0 error interrupt EDMA3CC2 TPTC1 error interrupt EDMA3CC2 TPTC2 error interrupt EDMA3CC2 TPTC3 error interrupt
Table 5-26
Event No. 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263
EDMA3CC3 memory protection interrupt EDMA3CC3 TPTC0 error interrupt EDMA3CC3 TPTC1 error interrupt EDMA3CC4 error interrupt EDMA3CC4 memory protection interrupt EDMA3CC4 TPTC0 error interrupt EDMA3CC4 TPTC1 error interrupt Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue
153
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EDMA3CC3 error interrupt

Event No. 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307
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Event Name QMSS_QUE_PEND_8851 QMSS_QUE_PEND_8852 QMSS_QUE_PEND_8853 QMSS_QUE_PEND_8854 QMSS_QUE_PEND_8855 QMSS_QUE_PEND_8856 QMSS_QUE_PEND_8857 QMSS_QUE_PEND_8858 QMSS_QUE_PEND_8859 QMSS_QUE_PEND_8860 QMSS_QUE_PEND_8861 QMSS_QUE_PEND_8862 QMSS_QUE_PEND_8863 Reserved Reserved Reserved Reserved Reserved Reserved SEM_INT0 SEM_INT1 SEM_INT2 SEM_INT3 SEM_INT4 SEM_INT5 SEM_INT6 SEM_INT7 SEM_INT8 SEM_INT9 SEM_INT10 SEM_INT11 SEM_INT12 SEM_INT13 SEM_INT14 SEM_INT15 SEM_ERR8 SEM_ERR9 SEM_ERR10 SEM_ERR11 SEM_ERR12 SEM_ERR13 SEM_ERR14 SEM_ERR15 DDR3_1_ERR Description Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Reserved Reserved Reserved Reserved Reserved Reserved Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt Semaphore error interrupt DDR3B error interrupt
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Event Name HyperLink_1_INT FFTC_0_INT0 FFTC_0_INT1 FFTC_0_INT2 FFTC_0_INT3 FFTC_1_INT0 FFTC_1_INT1 FFTC_1_INT2 FFTC_1_INT3 FFTC_2_INT0 FFTC_2_INT1 FFTC_2_INT2 FFTC_2_INT3 FFTC_3_INT0 FFTC_3_INT1 FFTC_3_INT2 FFTC_3_INT3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF_INT AIF_ATEVT0 AIF_ATEVT1 AIF_ATEVT2 AIF_ATEVT3 AIF_ATEVT4 AIF_ATEVT5 AIF_ATEVT6 AIF_ATEVT7 AIF_ATEVT8 AIF_ATEVT9 AIF_ATEVT10 AIF_ATEVT11 AIF_ATEVT12 AIF_ATEVT13 AIF_ATEVT14 AIF_ATEVT15 Reserved Reserved Description HyperLink 1 interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt
Table 5-26
Event No. 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351
FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt FFTC interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIF interrupt AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event AIF timer event Reserved Reserved
155
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FFTC interrupt

Event No. 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395
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Event Name Reserved Reserved TCP3D_0_INT TCP3D_1_INT Reserved Reserved BCP_INT0 BCP_INT1 BCP_INT2 BCP_INT3 PSC_ALLINT Reserved RAC_0_TRACE_GCCP0 RAC_0_TRACE_GCCP1 RAC_1_TRACE_GCCP0 RAC_1_TRACE_GCCP1 Reserved Reserved Reserved Reserved MPU_9_INT MPU_10_INT MPU_11_INT TRACER_MSMC_4_INT TRACER_MSMC_5_INT TRACER_MSMC_6_INT TRACER_MSMC_7_INT TRACER_DDR_1_INT TRACER_BCR_INT TRACER_RAC_1_INT Reserved TRACER_RAC_FE_INT TRACER_SPI_ROM_EMIF_INT TRACER_TAC_BE_INT Reserved TIMER_8_INTL TIMER_8_INTH TIMER_9_INTL TIMER_9_INTH TIMER_10_INTL TIMER_10_INTH TIMER_11_INTL TIMER_11_INTH TIMER_14_INTL Description Reserved Reserved TCP3d interrupt TCP3d interrupt Reserved Reserved BCP interrupt BCP interrupt BCP interrupt BCP interrupt PSC interrupt Reserved RAC trace RAC trace RAC trace RAC trace Reserved Reserved Reserved Reserved MPU9 addressing violation interrupt and protection violation interrupt MPU10 addressing violation interrupt and protection violation interrupt MPU11 addressing violation interrupt and protection violation interrupt Tracer sliding time window interrupt for MSMC SRAM Bank 4 Tracer sliding time window interrupt for MSMC SRAM Bank 4 Tracer sliding time window interrupt for MSMC SRAM Bank 4 Tracer sliding time window interrupt for MSMC SRAM Bank 4 Tracer sliding time window interrupt for DDR3B Tracer sliding time window interrupt for BCR Tracer sliding time window interrupt for RAC Reserved Tracer sliding time window interrupt for RAC Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules Tracer sliding time window interrupt for TAC Reserved Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low
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Event Name TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH USB_INT00 USB_INT04 USB_INT05 USB_INT06 USB_INT07 USB_INT08 USB_INT09 USB_INT10 USB_INT11 USB_MISCINT USB_OABSINT TCP3D_0_REVT0 TCP3D_0_REVT1 TCP3D_1_REVT0 TCP3D_1_REVT1 Reserved Reserved Reserved Reserved VCP2_0_INT0 VCP2_0_INT1 VCP2_0_INT2 VCP2_0_INT3 VCP2_1_INT0 VCP2_1_INT1 VCP2_1_INT2 VCP2_1_INT3 VCP2_0_REVT0 VCP2_0_XEVT0 VCP2_0_REVT1 VCP2_0_XEVT1 VCP2_0_REVT2 VCP2_0_XEVT2 VCP2_0_REVT3 VCP2_0_XEVT3 VCP2_1_REVT0 VCP2_1_XEVT0 VCP2_1_REVT1 VCP2_1_XEVT1 VCP2_1_REVT2 VCP2_1_XEVT2 Description Timer interrupt high Timer interrupt low Timer interrupt high USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt USB interrupt
Table 5-26
Event No. 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439
USB interrupt USB interrupt USB miscellaneous interrupt USB OABS interrupt TCP3d interrupt TCP3d interrupt TCP3d interrupt TCP3d interrupt Reserved Reserved Reserved Reserved VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt VCP interrupt
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USB interrupt

Event No. 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478
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Event Name VCP2_1_REVT3 VCP2_1_XEVT3 TETB_OVFLINT0 TETB_UNFLINT0 TETB_OVFLINT1 TETB_UNFLINT1 TETB_OVFLINT2 TETB_UNFLINT2 TETB_OVFLINT3 TETB_UNFLINT3 TETB_OVFLINT4 TETB_UNFLINT4 TETB_OVFLINT5 TETB_UNFLINT5 TETB_OVFLINT6 TETB_UNFLINT6 TETB_OVFLINT7 TETB_UNFLINT7 ARM_TBR_DMA RAC_0_INT RAC_1_INT Reserved Reserved GPIO_INT0 GPIO_INT1 GPIO_INT2 GPIO_INT3 GPIO_INT4 GPIO_INT5 GPIO_INT6 GPIO_INT7 IPC_GR0 IPC_GR1 IPC_GR2 IPC_GR3 IPC_GR4 IPC_GR5 IPC_GR6 IPC_GR7 Description VCP interrupt VCP interrupt ETB0 overflow (emulation trace buffer) ETB0 underflow ETB1 overflow (emulation trace buffer) ETB1 underflow ETB2 overflow (emulation trace buffer) ETB2 underflow ETB3 overflow (emulation trace buffer) ETB3 underflow ETB4 overflow (emulation trace buffer) ETB4 underflow ETB5 overflow (emulation trace buffer) ETB5 underflow ETB6 overflow (emulation trace buffer) ETB6 underflow ETB7 overflow (emulation trace buffer) ETB7 underflow ARM trace buffer RAC interrupt RAC interrupt Reserved Reserved GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt IPC interrupt generation IPC interrupt generation IPC interrupt generation IPC interrupt generation IPC interrupt generation IPC interrupt generation IPC interrupt generation IPC interrupt generation
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End of Table 5-26
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SPRS835DAugust 2013
5.3.2 CIC Registers This section includes the CIC memory map information and registers.
5.3.2.1 CIC0 Register Map
Table 5-27
Address Offset 0x0 0x4 0xc 0x10 0x20 0x24 0x28 0x2C 0x34 0x38 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0
CIC0 Registers (Part 1 of 7)

Register Mnemonic REVISION_REG CONTROL_REG HOST_CONTROL_REG GLOBAL_ENABLE_HINT_REG STATUS_SET_INDEX_REG STATUS_CLR_INDEX_REG ENABLE_SET_INDEX_REG ENABLE_CLR_INDEX_REG HINT_ENABLE_SET_INDEX_REG HINT_ENABLE_CLR_INDEX_REG RAW_STATUS_REG0 RAW_STATUS_REG1 RAW_STATUS_REG2 RAW_STATUS_REG3 RAW_STATUS_REG4 RAW_STATUS_REG5 RAW_STATUS_REG6 RAW_STATUS_REG7 RAW_STATUS_REG8 RAW_STATUS_REG9 RAW_STATUS_REG10 RAW_STATUS_REG11 RAW_STATUS_REG12 RAW_STATUS_REG13 RAW_STATUS_REG14 RAW_STATUS_REG15 ENA_STATUS_REG0 ENA_STATUS_REG1 ENA_STATUS_REG2 ENA_STATUS_REG3 ENA_STATUS_REG4 ENA_STATUS_REG5 ENA_STATUS_REG6 ENA_STATUS_REG7 ENA_STATUS_REG8 ENA_STATUS_REG9 ENA_STATUS_REG10 ENA_STATUS_REG11 ENA_STATUS_REG12 Register Name Revision Register Control Register Host Control Register Global Host Interrupt Enable Register Status Set Index Register Status Clear Index Register Enable Set Index Register Enable Clear Index Register Host Interrupt Enable Set Index Register Host Interrupt Enable Clear Index Register Raw Status Register 0 Raw Status Register 1 Raw Status Register 2 Raw Status Register 3 Raw Status Register 4 Raw Status Register 5 Raw Status Register 6 Raw Status Register 7 Raw Status Register 8 Raw Status Register 9 Raw Status Register 10 Raw Status Register 11 Raw Status Register 12 Raw Status Register 13 Raw Status Register 14 Raw Status Register 15 Enabled Status Register 0 Enabled Status Register 1 Enabled Status Register 2 Enabled Status Register 3 Enabled Status Register 4 Enabled Status Register 5 Enabled Status Register 6 Enabled Status Register 7 Enabled Status Register 8 Enabled Status Register 9 Enabled Status Register10 Enabled Status Register 11 Enabled Status Register 12
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Address Offset 0x2B4 0x2B8 0x2BC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x38C 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420
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Register Mnemonic ENA_STATUS_REG13 ENA_STATUS_REG14 ENA_STATUS_REG15 ENABLE_REG0 ENABLE_REG1 ENABLE_REG2 ENABLE_REG3 ENABLE_REG4 ENABLE_REG5 ENABLE_REG6 ENABLE_REG7 ENABLE_REG8 ENABLE_REG9 ENABLE_REG10 ENABLE_REG11 ENABLE_REG12 ENABLE_REG13 ENABLE_REG14 ENABLE_REG15 ENABLE_CLR_REG0 ENABLE_CLR_REG1 ENABLE_CLR_REG2 ENABLE_CLR_REG3 ENABLE_CLR_REG4 ENABLE_CLR_REG5 ENABLE_CLR_REG6 ENABLE_CLR_REG7 ENABLE_CLR_REG8 ENABLE_CLR_REG9 ENABLE_CLR_REG10 ENABLE_CLR_REG11 ENABLE_CLR_REG12 ENABLE_CLR_REG13 ENABLE_CLR_REG14 ENABLE_CLR_REG15 CH_MAP_REG0 CH_MAP_REG1 CH_MAP_REG2 CH_MAP_REG3 CH_MAP_REG4 CH_MAP_REG5 CH_MAP_REG6 CH_MAP_REG7 CH_MAP_REG8 Register Name Enabled Status Register 13 Enabled Status Register 14 Enabled Status Register 15 Enable Register 0 Enable Register 1 Enable Register 2 Enable Register 3 Enable Register 4 Enable Register 5 Enable Register 6 Enable Register 7 Enable Register 8 Enable Register 9 Enable Register 10 Enable Register 11 Enable Register 12 Enable Register 13 Enable Register 14 Enable Register 15 Enable Clear Register 0 Enable Clear Register 1 Enable Clear Register 2 Enable Clear Register 3 Enable Clear Register 4 Enable Clear Register 5 Enable Clear Register 6 Enable Clear Register 7 Enable Clear Register 8 Enable Clear Register 9 Enable Clear Register 10 Enable Clear Register 11 Enable Clear Register 12 Enable Clear Register 13 Enable Clear Register 14 Enable Clear Register 15 Interrupt Channel Map Register for 0 to 0+3 Interrupt Channel Map Register for 4 to 4+3 Interrupt Channel Map Register for 8 to 8+3 Interrupt Channel Map Register for 12 to 12+3 Interrupt Channel Map Register for 16 to 16+3 Interrupt Channel Map Register for 20 to 20+3 Interrupt Channel Map Register for 24 to 24+3 Interrupt Channel Map Register for 28 to 28+3 Interrupt Channel Map Register for 32 to 32+3
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SPRS835DAugust 2013 CIC0 Registers (Part 3 of 7)

Register Mnemonic CH_MAP_REG9 CH_MAP_REG10 CH_MAP_REG11 CH_MAP_REG12 CH_MAP_REG13 CH_MAP_REG14 CH_MAP_REG15 CH_MAP_REG16 CH_MAP_REG17 CH_MAP_REG18 CH_MAP_REG19 CH_MAP_REG20 CH_MAP_REG21 CH_MAP_REG22 CH_MAP_REG23 CH_MAP_REG24 CH_MAP_REG25 CH_MAP_REG26 CH_MAP_REG27 CH_MAP_REG28 CH_MAP_REG29 CH_MAP_REG30 CH_MAP_REG31 CH_MAP_REG32 CH_MAP_REG33 CH_MAP_REG34 CH_MAP_REG35 CH_MAP_REG36 CH_MAP_REG37 CH_MAP_REG38 CH_MAP_REG39 CH_MAP_REG40 CH_MAP_REG41 CH_MAP_REG42 CH_MAP_REG43 CH_MAP_REG44 CH_MAP_REG45 CH_MAP_REG46 CH_MAP_REG47 CH_MAP_REG48 CH_MAP_REG49 CH_MAP_REG50 CH_MAP_REG51 CH_MAP_REG52 Register Name Interrupt Channel Map Register for 36 to 36+3 Interrupt Channel Map Register for 40 to 40+3 Interrupt Channel Map Register for 44 to 44+3 Interrupt Channel Map Register for 48 to 48+3 Interrupt Channel Map Register for 52 to 52+3 Interrupt Channel Map Register for 56 to 56+3 Interrupt Channel Map Register for 60 to 60+3 Interrupt Channel Map Register for 64 to 64+3 Interrupt Channel Map Register for 68 to 68+3
Table 5-27
Address Offset 0x424 0x428 0x42C 0x430 0x434 0x438 0x43C 0x440 0x444 0x448 0x44C 0x450 0x454 0x458 0x45C 0x460 0x464 0x468 0x46C 0x470 0x474 0x478 0x47C 0x480 0x484 0x488 0x48C 0x490 0x494 0x498 0x49C 0x4A0 0x4A4 0x4A8 0x4AC 0x4B0 0x4B4 0x4B8 0x4BC 0x4C0 0x4C4 0x4C8 0x4CC 0X4D0
Interrupt Channel Map Register for 76 to 76+3 Interrupt Channel Map Register for 80 to 80+3 Interrupt Channel Map Register for 84 to 84+3 Interrupt Channel Map Register for 88 to 88+3 Interrupt Channel Map Register for 92 to 92+3 Interrupt Channel Map Register for 96 to 96+3 Interrupt Channel Map Register for 100 to 100+3 Interrupt Channel Map Register for 104 to 104+3 Interrupt Channel Map Register for 108 to 108+3 Interrupt Channel Map Register for 112 to 112+3 Interrupt Channel Map Register for 116 to 116+3 Interrupt Channel Map Register for 120 to 120+3 Interrupt Channel Map Register for 124 to 124+3 Interrupt Channel Map Register for 128 to 128+3 Interrupt Channel Map Register for 132 to 132+3 Interrupt Channel Map Register for 136 to 136+3 Interrupt Channel Map Register for 140 to 140+3 Interrupt Channel Map Register for 144 to 144+3 Interrupt Channel Map Register for 148 to 148+3 Interrupt Channel Map Register for 152 to 152+3 Interrupt Channel Map Register for 156 to 156+3 Interrupt Channel Map Register for 160 to 160+3 Interrupt Channel Map Register for 164 to 164+3 Interrupt Channel Map Register for 168 to 168+3 Interrupt Channel Map Register for 172 to 172+3 Interrupt Channel Map Register for 176 to 176+3 Interrupt Channel Map Register for 180 to 180+3 Interrupt Channel Map Register for 184 to 184+3 Interrupt Channel Map Register for 188 to 188+3 Interrupt Channel Map Register for 192 to 192+3 Interrupt Channel Map Register for 196 to 196+3 Interrupt Channel Map Register for 200 to 200+3 Interrupt Channel Map Register for 204 to 204+3 Interrupt Channel Map Register for 208 to 208+3
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Interrupt Channel Map Register for 72 to 72+3

Address Offset 0X4D4 0X4D8 0X4DC 0X4E0 0X4E4 0X4E8 0X4FC 0X4F0 0X4F4 0X4F8 0X4FC 0X500 0X504 0X508 0X50C 0X510 0X514 0X518 0X51C 0X520 0X524 0X528 0X52C 0X520 0X524 0X528 0x52C 0x530 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x554 0x558 0x55C 0x560 0x564 0x568 0x56C 0x570
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Register Mnemonic CH_MAP_REG53 CH_MAP_REG54 CH_MAP_REG55 CH_MAP_REG56 CH_MAP_REG57 CH_MAP_REG58 CH_MAP_REG59 CH_MAP_REG60 CH_MAP_REG61 CH_MAP_REG62 CH_MAP_REG63 CH_MAP_REG64 CH_MAP_REG65 CH_MAP_REG66 CH_MAP_REG67 CH_MAP_REG68 CH_MAP_REG69 CH_MAP_REG70 CH_MAP_REG71 CH_MAP_REG72 CH_MAP_REG73 CH_MAP_REG74 CH_MAP_REG75 CH_MAP_REG76 CH_MAP_REG77 CH_MAP_REG78 CH_MAP_REG79 CH_MAP_REG80 CH_MAP_REG81 CH_MAP_REG82 CH_MAP_REG83 CH_MAP_REG84 CH_MAP_REG85 CH_MAP_REG86 CH_MAP_REG87 CH_MAP_REG88 CH_MAP_REG89 CH_MAP_REG90 CH_MAP_REG91 CH_MAP_REG92 CH_MAP_REG93 CH_MAP_REG94 CH_MAP_REG95 CH_MAP_REG96 Register Name Interrupt Channel Map Register for 212 to 212+3 Interrupt Channel Map Register for 216 to 216+3 Interrupt Channel Map Register for 220 to 220+3 Interrupt Channel Map Register for 224 to 224+3 Interrupt Channel Map Register for 228 to 228+3 Interrupt Channel Map Register for 232 to 232+3 Interrupt Channel Map Register for 236 to 236+3 Interrupt Channel Map Register for 240 to 240+3 Interrupt Channel Map Register for 244 to 244+3 Interrupt Channel Map Register for 248 to 248+3 Interrupt Channel Map Register for 252 to 252+3 Interrupt Channel Map Register for 256 to 256+3 Interrupt Channel Map Register for 260 to 260+3 Interrupt Channel Map Register for 264 to 264+3 Interrupt Channel Map Register for 268 to 268+3 Interrupt Channel Map Register for 272 to 272+3 Interrupt Channel Map Register for 276 to 276+3 Interrupt Channel Map Register for 280 to 280+3 Interrupt Channel Map Register for 284 to 284+3 Interrupt Channel Map Register for 288 to 288+3 Interrupt Channel Map Register for 292 to 292+3 Interrupt Channel Map Register for 296 to 296+3 Interrupt Channel Map Register for 300 to 300+3 Interrupt Channel Map Register for 304 to 304+3 Interrupt Channel Map Register for 308 to 308+3 Interrupt Channel Map Register for 312 to 312+3 Interrupt Channel Map Register for 316 to 316+3 Interrupt Channel Map Register for 320 to 320+3 Interrupt Channel Map Register for 324 to 324+3 Interrupt Channel Map Register for 328 to 328+3 Interrupt Channel Map Register for 332 to332+3 Interrupt Channel Map Register for336 to 336+3 Interrupt Channel Map Register for 340 to 340+3 Interrupt Channel Map Register for 344 to 344+3 Interrupt Channel Map Register for 348 to 348+3 Interrupt Channel Map Register for 352 to 352+3 Interrupt Channel Map Register for 356 to 356+3 Interrupt Channel Map Register for 360 to 360+3 Interrupt Channel Map Register for 364 to 364+3 Interrupt Channel Map Register for 368 to 368+3 Interrupt Channel Map Register for372 to 372+3 Interrupt Channel Map Register for 376 to 376+3 Interrupt Channel Map Register for 380 to 380+3 Interrupt Channel Map Register for 384 to 384+3
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Register Mnemonic CH_MAP_REG97 CH_MAP_REG98 CH_MAP_REG99 CH_MAP_REG100 CH_MAP_REG101 CH_MAP_REG102 CH_MAP_REG103 CH_MAP_REG104 CH_MAP_REG105 CH_MAP_REG106 CH_MAP_REG107 CH_MAP_REG108 CH_MAP_REG109 CH_MAP_REG110 CH_MAP_REG111 CH_MAP_REG112 CH_MAP_REG113 CH_MAP_REG114 CH_MAP_REG115 CH_MAP_REG116 CH_MAP_REG117 CH_MAP_REG118 CH_MAP_REG119 CH_MAP_REG120 CH_MAP_REG121 CH_MAP_REG122 CH_MAP_REG123 CH_MAP_REG124 CH_MAP_REG125 CH_MAP_REG126 CH_MAP_REG127 CH_MAP_REG128 CH_MAP_REG129 CH_MAP_REG130 CH_MAP_REG131 CH_MAP_REG132 CH_MAP_REG133 CH_MAP_REG134 CH_MAP_REG135 CH_MAP_REG136 CH_MAP_REG137 CH_MAP_REG138 CH_MAP_REG139 CH_MAP_REG140 Register Name Interrupt Channel Map Register for 388 to 388+3 Interrupt Channel Map Register for 392 to 392+3 Interrupt Channel Map Register for 396 to 396+3 Interrupt Channel Map Register for 400 to 400+3 Interrupt Channel Map Register for 404 to 404+3 Interrupt Channel Map Register for 408 to 408+3 Interrupt Channel Map Register for 412 to412+3 Interrupt Channel Map Register for 416 to 416+3 Interrupt Channel Map Register for 420 to 420+3
Table 5-27
Address Offset 0x574 0x578 0x57C 0x580 0x584 0x588 0x58C 0x590 0x594 0x598 0x59C 0x5A0 0x5A4 0x5A8 0x5AC 0x5B0 0x5B4 0x5B8 0x5BC 0x5C0 0x5C4 0x5C8 0x5CC 0x5D0 0x5D4 0x5D8 0x5DC 0x5E0 0x5E4 0x5E8 0x5EC 0x5F0 0x5F4 0x5F8 0x5FC 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620
163
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Address Offset 0x624 0x628 0x62C 0x630 0x634 0x638 0x63C 0x640 0x644 0x648 0x64C 0x650 0x654 0x658 0x65C 0x660 0x664 0x668 0x66C 0x670 0x674 0x678 0x67C 0x680 0x684 0x688 0x68C 0x690 0x694 0x698 0x69C 0x800 0x804 0x808 0x80c 0x810 0x814 0x818 0x81c 0x820 0x824 0x828 0x82c 0x830
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Register Mnemonic CH_MAP_REG141 CH_MAP_REG142 CH_MAP_REG143 CH_MAP_REG144 CH_MAP_REG145 CH_MAP_REG146 CH_MAP_REG147 CH_MAP_REG148 CH_MAP_REG149 CH_MAP_REG150 CH_MAP_REG151 CH_MAP_REG152 CH_MAP_REG153 CH_MAP_REG154 CH_MAP_REG155 CH_MAP_REG156 CH_MAP_REG157 CH_MAP_REG158 CH_MAP_REG159 CH_MAP_REG160 CH_MAP_REG161 CH_MAP_REG162 CH_MAP_REG163 CH_MAP_REG164 CH_MAP_REG165 CH_MAP_REG166 CH_MAP_REG167 CH_MAP_REG168 CH_MAP_REG169 CH_MAP_REG170 CH_MAP_REG171 HINT_MAP_REG0 HINT_MAP_REG1 HINT_MAP_REG2 HINT_MAP_REG3 HINT_MAP_REG4 HINT_MAP_REG5 HINT_MAP_REG6 HINT_MAP_REG7 HINT_MAP_REG8 HINT_MAP_REG9 HINT_MAP_REG10 HINT_MAP_REG11 HINT_MAP_REG12 Register Name Interrupt Channel Map Register for 564 to 564+3 Interrupt Channel Map Register for 568 to 568+3 Interrupt Channel Map Register for 572 to 572+3 Interrupt Channel Map Register for 576 to 576+3 Interrupt Channel Map Register for 580 to 580+3 Interrupt Channel Map Register for 584 to 584+3 Interrupt Channel Map Register for 588 to 588+3 Interrupt Channel Map Register for 592 to 592+3 Interrupt Channel Map Register for 596 to 596+3 Interrupt Channel Map Register for 600 to 600+3 Interrupt Channel Map Register for 604 to 604+3 Interrupt Channel Map Register for 608 to 608+3 Interrupt Channel Map Register for 612 to 612+3 Interrupt Channel Map Register for 616 to 616+3 Interrupt Channel Map Register for 620 to 620+3 Interrupt Channel Map Register for 624 to 624+3 Interrupt Channel Map Register for 628 to 628+3 Interrupt Channel Map Register for 632 to 632+3 Interrupt Channel Map Register for 636 to 636+3 Interrupt Channel Map Register for 640 to 640+3 Interrupt Channel Map Register for 644 to 644+3 Interrupt Channel Map Register for 648 to 648+3 Interrupt Channel Map Register for 652 to 652+3 Interrupt Channel Map Register for 656 to 656+3 Interrupt Channel Map Register for 660 to 660+3 Interrupt Channel Map Register for 664 to 664+3 Interrupt Channel Map Register for 668 to 668+3 Interrupt Channel Map Register for 672 to 672+3 Interrupt Channel Map Register for 676 to 676+3 Interrupt Channel Map Register for 680 to 680+3 Interrupt Channel Map Register for 684 to 684+3 Host Interrupt Map Register for 0 to 0+3 Host Interrupt Map Register for 4 to 4+3 Host Interrupt Map Register for 8 to 8+3 Host Interrupt Map Register for 12 to 12+3 Host Interrupt Map Register for 16 to 16+3 Host Interrupt Map Register for 20 to 20+3 Host Interrupt Map Register for 24 to 24+3 Host Interrupt Map Register for 28 to 28+3 Host Interrupt Map Register for 32 to 32+3 Host Interrupt Map Register for 36 to 36+3 Host Interrupt Map Register for 40 to 40+3 Host Interrupt Map Register for 44 to 44+3 Host Interrupt Map Register for 48 to 48+3
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Register Mnemonic HINT_MAP_REG13 HINT_MAP_REG14 HINT_MAP_REG15 HINT_MAP_REG16 HINT_MAP_REG17 HINT_MAP_REG18 HINT_MAP_REG19 ENABLE_HINT_REG0 ENABLE_HINT_REG1 ENABLE_HINT_REG2 Register Name Host Interrupt Map Register for 52 to 52+3 Host Interrupt Map Register for 56 to 56+3 Host Interrupt Map Register for 60 to 60+3 Host Interrupt Map Register for 64 to 64+3 Host Interrupt Map Register for 68 to 68+3 Host Interrupt Map Register for 72 to 72+3 Host Interrupt Map Register for 76 to 76+3 Host Interrupt Enable Register 0 Host Interrupt Enable Register 1
Table 5-27
Address Offset 0x834 0x838 0x83c 0x840 0x844 0x848 0x84c 0x1500 0x1504 0x1508
End of Table 5-27

Table 5-28
Address Offset 0x0 0x10 0x20 0x24 0x28 0x2c 0x34 0x38 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x280 0x284 0x288 0x28C

Register Mnemonic REVISION_REG GLOBAL_ENABLE_HINT_REG STATUS_SET_INDEX_REG STATUS_CLR_INDEX_REG ENABLE_SET_INDEX_REG ENABLE_CLR_INDEX_REG HINT_ENABLE_SET_INDEX_REG HINT_ENABLE_CLR_INDEX_REG RAW_STATUS_REG0 RAW_STATUS_REG1 RAW_STATUS_REG2 RAW_STATUS_REG3 RAW_STATUS_REG4 RAW_STATUS_REG5 RAW_STATUS_REG6 RAW_STATUS_REG7 RAW_STATUS_REG8 RAW_STATUS_REG9 RAW_STATUS_REG10 RAW_STATUS_REG11 RAW_STATUS_REG12 RAW_STATUS_REG13 RAW_STATUS_REG14 RAW_STATUS_REG15 ENA_STATUS_REG0 ENA_STATUS_REG1 ENA_STATUS_REG2 ENA_STATUS_REG3 Register Name Revision Register Global Host Interrupt Enable Register Status Set Index Register Status Clear Index Register Enable Set Index Register Enable Clear Index Register Host Interrupt Enable Set Index Register Host Interrupt Enable Clear Index Register Raw Status Register 0 Raw Status Register 1 Raw Status Register 2 Raw Status Register 3 Raw Status Register 4 Raw Status Register 5 Raw Status Register 6 Raw Status Register 7 Raw Status Register 8 Raw Status Register 9 Raw Status Register 10 Raw Status Register 11 Raw Status Register 12 Raw Status Register 13 Raw Status Register 14 Raw Status Register 15 Enabled Status Register 0 Enabled Status Register 1 Enabled Status Register 2 Enabled Status Register 3
165
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Host Interrupt Enable Register 2

Address Offset 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x38C
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Register Mnemonic ENA_STATUS_REG4 ENA_STATUS_REG5 ENA_STATUS_REG6 ENA_STATUS_REG7 ENA_STATUS_REG8 ENA_STATUS_REG9 ENA_STATUS_REG10 ENA_STATUS_REG11 ENA_STATUS_REG12 ENA_STATUS_REG13 ENA_STATUS_REG14 ENA_STATUS_REG15 ENABLE_REG0 ENABLE_REG1 ENABLE_REG2 ENABLE_REG3 ENABLE_REG4 ENABLE_REG5 ENABLE_REG6 ENABLE_REG7 ENABLE_REG8 ENABLE_REG9 ENABLE_REG10 ENABLE_REG11 ENABLE_REG12 ENABLE_REG13 ENABLE_REG14 ENABLE_REG15 ENABLE_CLR_REG0 ENABLE_CLR_REG1 ENABLE_CLR_REG2 ENABLE_CLR_REG3 ENABLE_CLR_REG4 ENABLE_CLR_REG5 ENABLE_CLR_REG6 ENABLE_CLR_REG7 ENABLE_CLR_REG8 ENABLE_CLR_REG9 ENABLE_CLR_REG10 ENABLE_CLR_REG11 ENABLE_CLR_REG12 ENABLE_CLR_REG13 ENABLE_CLR_REG14 ENABLE_CLR_REG15 Register Name Enabled Status Register 4 Enabled Status Register 5 Enabled Status Register 6 Enabled Status Register 7 Enabled Status Register 8 Enabled Status Register 9 Enabled Status Register10 Enabled Status Register 11 Enabled Status Register 12 Enabled Status Register 13 Enabled Status Register 14 Enabled Status Register 15 Enable Register 0 Enable Register 1 Enable Register 2 Enable Register 3 Enable Register 4 Enable Register 5 Enable Register 6 Enable Register 7 Enable Register 8 Enable Register 9 Enable Register 10 Enable Register 11 Enable Register 12 Enable Register 13 Enable Register 14 Enable Register 15 Enable Clear Register 0 Enable Clear Register 1 Enable Clear Register 2 Enable Clear Register 3 Enable Clear Register 4 Enable Clear Register 5 Enable Clear Register 6 Enable Clear Register 7 Enable Clear Register 8 Enable Clear Register 9 Enable Clear Register 10 Enable Clear Register 11 Enable Clear Register 12 Enable Clear Register 13 Enable Clear Register 14 Enable Clear Register 15
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Register Mnemonic CH_MAP_REG0 CH_MAP_REG1 CH_MAP_REG2 CH_MAP_REG3 CH_MAP_REG4 CH_MAP_REG5 CH_MAP_REG6 CH_MAP_REG7 CH_MAP_REG8 CH_MAP_REG9 CH_MAP_REG10 CH_MAP_REG11 CH_MAP_REG12 CH_MAP_REG13 CH_MAP_REG14 CH_MAP_REG15 CH_MAP_REG16 CH_MAP_REG17 CH_MAP_REG18 CH_MAP_REG19 CH_MAP_REG20 CH_MAP_REG21 CH_MAP_REG22 CH_MAP_REG23 CH_MAP_REG24 CH_MAP_REG25 CH_MAP_REG26 CH_MAP_REG27 CH_MAP_REG28 CH_MAP_REG29 CH_MAP_REG30 CH_MAP_REG31 CH_MAP_REG32 CH_MAP_REG33 CH_MAP_REG34 CH_MAP_REG35 CH_MAP_REG36 CH_MAP_REG37 CH_MAP_REG38 CH_MAP_REG39 CH_MAP_REG40 CH_MAP_REG41 CH_MAP_REG42 CH_MAP_REG43 Register Name Interrupt Channel Map Register for 0 to 0+3 Interrupt Channel Map Register for 4 to 4+3 Interrupt Channel Map Register for 8 to 8+3 Interrupt Channel Map Register for 12 to 12+3 Interrupt Channel Map Register for 16 to 16+3 Interrupt Channel Map Register for 20 to 20+3 Interrupt Channel Map Register for 24 to 24+3 Interrupt Channel Map Register for 28 to 28+3 Interrupt Channel Map Register for 32 to 32+3
Table 5-28
Address Offset 0x400 0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420 0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464 0x468 0x46c 0x470 0x474 0x478 0x47c 0x480 0x484 0x488 0x48c 0x490 0x494 0x498 0x49c 0x4A0 0x4A4 0x4A8 0x4AC
167
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Address Offset 0x4B0 0x4B4 0x4B8 0x4BC 0x4C0 0x4C4 0x4C8 0x4CC 0X4D0 0X4D4 0X4D8 0X4DC 0X4E0 0X4E4 0X4E8 0X4FC 0X4F0 0X4F4 0X4F8 0X4FC 0X500 0X504 0X508 0X50C 0X510 0X514 0X518 0X51C 0X520 0X524 0X528 0X52C 0X520 0X524 0X528 0x52C 0x530 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C
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Register Mnemonic CH_MAP_REG44 CH_MAP_REG45 CH_MAP_REG46 CH_MAP_REG47 CH_MAP_REG48 CH_MAP_REG49 CH_MAP_REG50 CH_MAP_REG51 CH_MAP_REG52 CH_MAP_REG53 CH_MAP_REG54 CH_MAP_REG55 CH_MAP_REG56 CH_MAP_REG57 CH_MAP_REG58 CH_MAP_REG59 CH_MAP_REG60 CH_MAP_REG61 CH_MAP_REG62 CH_MAP_REG63 CH_MAP_REG64 CH_MAP_REG65 CH_MAP_REG66 CH_MAP_REG67 CH_MAP_REG68 CH_MAP_REG69 CH_MAP_REG70 CH_MAP_REG71 CH_MAP_REG72 CH_MAP_REG73 CH_MAP_REG74 CH_MAP_REG75 CH_MAP_REG76 CH_MAP_REG77 CH_MAP_REG78 CH_MAP_REG79 CH_MAP_REG80 CH_MAP_REG81 CH_MAP_REG82 CH_MAP_REG83 CH_MAP_REG84 CH_MAP_REG85 CH_MAP_REG86 CH_MAP_REG87 Register Name Interrupt Channel Map Register for 176 to 176+3 Interrupt Channel Map Register for 180 to 180+3 Interrupt Channel Map Register for 184 to 184+3 Interrupt Channel Map Register for 188 to 188+3 Interrupt Channel Map Register for 192 to 192+3 Interrupt Channel Map Register for 196 to 196+3 Interrupt Channel Map Register for 200 to 200+3 Interrupt Channel Map Register for 204 to 204+3 Interrupt Channel Map Register for 208 to 208+3 Interrupt Channel Map Register for 212 to 212+3 Interrupt Channel Map Register for 216 to 216+3 Interrupt Channel Map Register for 220 to 220+3 Interrupt Channel Map Register for 224 to 224+3 Interrupt Channel Map Register for 228 to 228+3 Interrupt Channel Map Register for 232 to 232+3 Interrupt Channel Map Register for 236 to 236+3 Interrupt Channel Map Register for 240 to 240+3 Interrupt Channel Map Register for 244 to 244+3 Interrupt Channel Map Register for 248 to 248+3 Interrupt Channel Map Register for 252 to 252+3 Interrupt Channel Map Register for 256 to 256+3 Interrupt Channel Map Register for 260 to 260+3 Interrupt Channel Map Register for 264 to 264+3 Interrupt Channel Map Register for 268 to 268+3 Interrupt Channel Map Register for 272 to 272+3 Interrupt Channel Map Register for 276 to 276+3 Interrupt Channel Map Register for 280 to 280+3 Interrupt Channel Map Register for 284 to 284+3 Interrupt Channel Map Register for 288 to 288+3 Interrupt Channel Map Register for 292 to 292+3 Interrupt Channel Map Register for 296 to 296+3 Interrupt Channel Map Register for 300 to 300+3 Interrupt Channel Map Register for 304 to 304+3 Interrupt Channel Map Register for 308 to 308+3 Interrupt Channel Map Register for 312 to 312+3 Interrupt Channel Map Register for 316 to 316+3 Interrupt Channel Map Register for 320 to 320+3 Interrupt Channel Map Register for 324 to 324+3 Interrupt Channel Map Register for 328 to 328+3 Interrupt Channel Map Register for 332 to332+3 Interrupt Channel Map Register for336 to 336+3 Interrupt Channel Map Register for 340 to 340+3 Interrupt Channel Map Register for 344 to 344+3 Interrupt Channel Map Register for 348 to 348+3
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Register Mnemonic CH_MAP_REG88 CH_MAP_REG89 CH_MAP_REG90 CH_MAP_REG91 CH_MAP_REG92 CH_MAP_REG93 CH_MAP_REG94 CH_MAP_REG95 CH_MAP_REG96 CH_MAP_REG97 CH_MAP_REG98 CH_MAP_REG99 CH_MAP_REG100 CH_MAP_REG101 CH_MAP_REG102 CH_MAP_REG103 CH_MAP_REG104 CH_MAP_REG105 CH_MAP_REG106 CH_MAP_REG107 CH_MAP_REG108 CH_MAP_REG109 CH_MAP_REG110 CH_MAP_REG111 CH_MAP_REG112 CH_MAP_REG113 CH_MAP_REG114 CH_MAP_REG115 CH_MAP_REG116 CH_MAP_REG117 CH_MAP_REG118 CH_MAP_REG119 CH_MAP_REG120 CH_MAP_REG121 CH_MAP_REG122 CH_MAP_REG123 CH_MAP_REG124 CH_MAP_REG125 CH_MAP_REG126 CH_MAP_REG127 CH_MAP_REG128 CH_MAP_REG129 CH_MAP_REG130 CH_MAP_REG131 Register Name Interrupt Channel Map Register for 352 to 352+3 Interrupt Channel Map Register for 356 to 356+3 Interrupt Channel Map Register for 360 to 360+3 Interrupt Channel Map Register for 364 to 364+3 Interrupt Channel Map Register for 368 to 368+3 Interrupt Channel Map Register for372 to 372+3 Interrupt Channel Map Register for 376 to 376+3 Interrupt Channel Map Register for 380 to 380+3 Interrupt Channel Map Register for 384 to 384+3
Table 5-28
Address Offset 0x550 0x554 0x558 0x55C 0x560 0x564 0x568 0x56C 0x570 0x574 0x578 0x57C 0x580 0x584 0x588 0x58C 0x590 0x594 0x598 0x59C 0x5A0 0x5A4 0x5A8 0x5AC 0x5B0 0x5B4 0x5B8 0x5BC 0x5C0 0x5C4 0x5C8 0x5CC 0x5D0 0x5D4 0x5D8 0x5DC 0x5E0 0x5E4 0x5E8 0x5EC 0x5F0 0x5F4 0x5F8 0x5FC
Interrupt Channel Map Register for 392 to 392+3 Interrupt Channel Map Register for 396 to 396+3 Interrupt Channel Map Register for 400 to 400+3 Interrupt Channel Map Register for 404 to 404+3 Interrupt Channel Map Register for 408 to 408+3 Interrupt Channel Map Register for 412 to412+3 Interrupt Channel Map Register for 416 to 416+3 Interrupt Channel Map Register for 420 to 420+3 Interrupt Channel Map Register for 424 to 424+3 Interrupt Channel Map Register for 428 to 428+3 Interrupt Channel Map Register for 432 to 432+3 Interrupt Channel Map Register for 436 to 436+3 Interrupt Channel Map Register for 440 to 440+3 Interrupt Channel Map Register for 444 to 444+3 Interrupt Channel Map Register for 448 to 448+3 Interrupt Channel Map Register for 452 to 452+3 Interrupt Channel Map Register for 456 to 456+3 Interrupt Channel Map Register for 460 to 460+3 Interrupt Channel Map Register for 464 to 464+3 Interrupt Channel Map Register for 468 to 468+3 Interrupt Channel Map Register for 472 to 472+3 Interrupt Channel Map Register for 476 to 476+3 Interrupt Channel Map Register for 480 to 480+3 Interrupt Channel Map Register for 484 to 484+3 Interrupt Channel Map Register for 488 to 488+3 Interrupt Channel Map Register for 482 to 492+3 Interrupt Channel Map Register for 496 to 496+3 Interrupt Channel Map Register for 500 to 500+3 Interrupt Channel Map Register for 504 to 504+3 Interrupt Channel Map Register for 508 to 508+3 Interrupt Channel Map Register for 512 to 512+3 Interrupt Channel Map Register for 516 to 516+3 Interrupt Channel Map Register for 520 to 520+3 Interrupt Channel Map Register for 524 to 524+3
169
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Address Offset 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620 0x624 0x628 0x62C 0x630 0x634 0x638 0x63C 0x640 0x644 0x648 0x64C 0x650 0x654 0x658 0x65C 0x660 0x664 0x668 0x66C 0x670 0x674 0x678 0x67C 0x680 0x684 0x688 0x68C 0x690 0x694 0x698 0x69C 0x800 0x804 0x808 0x80c
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Register Mnemonic CH_MAP_REG132 CH_MAP_REG133 CH_MAP_REG134 CH_MAP_REG135 CH_MAP_REG136 CH_MAP_REG137 CH_MAP_REG138 CH_MAP_REG139 CH_MAP_REG140 CH_MAP_REG141 CH_MAP_REG142 CH_MAP_REG143 CH_MAP_REG144 CH_MAP_REG145 CH_MAP_REG146 CH_MAP_REG147 CH_MAP_REG148 CH_MAP_REG149 CH_MAP_REG150 CH_MAP_REG151 CH_MAP_REG152 CH_MAP_REG153 CH_MAP_REG154 CH_MAP_REG155 CH_MAP_REG156 CH_MAP_REG157 CH_MAP_REG158 CH_MAP_REG159 CH_MAP_REG160 CH_MAP_REG161 CH_MAP_REG162 CH_MAP_REG163 CH_MAP_REG164 CH_MAP_REG165 CH_MAP_REG166 CH_MAP_REG167 CH_MAP_REG168 CH_MAP_REG169 CH_MAP_REG170 CH_MAP_REG171 HINT_MAP_REG0 HINT_MAP_REG1 HINT_MAP_REG2 HINT_MAP_REG3 Register Name Interrupt Channel Map Register for 528 to 528+3 Interrupt Channel Map Register for 532 to 532+3 Interrupt Channel Map Register for 536 to 536+3 Interrupt Channel Map Register for 540 to 540+3 Interrupt Channel Map Register for 544 to 544+3 Interrupt Channel Map Register for 548 to 548+3 Interrupt Channel Map Register for 552 to 552+3 Interrupt Channel Map Register for 556 to 556+3 Interrupt Channel Map Register for 560 to 560+3 Interrupt Channel Map Register for 564 to 564+3 Interrupt Channel Map Register for 568 to 568+3 Interrupt Channel Map Register for 572 to 572+3 Interrupt Channel Map Register for 576 to 576+3 Interrupt Channel Map Register for 580 to 580+3 Interrupt Channel Map Register for 584 to 584+3 Interrupt Channel Map Register for 588 to 588+3 Interrupt Channel Map Register for 592 to 592+3 Interrupt Channel Map Register for 596 to 596+3 Interrupt Channel Map Register for 600 to 600+3 Interrupt Channel Map Register for 604 to 604+3 Interrupt Channel Map Register for 608 to 608+3 Interrupt Channel Map Register for 612 to 612+3 Interrupt Channel Map Register for 616 to 616+3 Interrupt Channel Map Register for 620 to 620+3 Interrupt Channel Map Register for 624 to 624+3 Interrupt Channel Map Register for 628 to 628+3 Interrupt Channel Map Register for 632 to 632+3 Interrupt Channel Map Register for 636 to 636+3 Interrupt Channel Map Register for 640 to 640+3 Interrupt Channel Map Register for 644 to 644+3 Interrupt Channel Map Register for 648 to 648+3 Interrupt Channel Map Register for 652 to 652+3 Interrupt Channel Map Register for 656 to 656+3 Interrupt Channel Map Register for 660 to 660+3 Interrupt Channel Map Register for 664 to 664+3 Interrupt Channel Map Register for 668 to 668+3 Interrupt Channel Map Register for 672 to 672+3 Interrupt Channel Map Register for 676 to 676+3 Interrupt Channel Map Register for 680 to 680+3 Interrupt Channel Map Register for 684 to 684+3 Host Interrupt Map Register for 0 to 0+3 Host Interrupt Map Register for 4 to 4+3 Host Interrupt Map Register for 8 to 8+3 Host Interrupt Map Register for 12 to 12+3
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Register Mnemonic HINT_MAP_REG4 HINT_MAP_REG5 HINT_MAP_REG6 HINT_MAP_REG7 HINT_MAP_REG8 HINT_MAP_REG9 HINT_MAP_REG10 HINT_MAP_REG11 HINT_MAP_REG12 HINT_MAP_REG13 ENABLE_HINT_REG0 ENABLE_HINT_REG1 Register Name Host Interrupt Map Register for 16 to 16+3 Host Interrupt Map Register for 20 to 20+3 Host Interrupt Map Register for 24 to 24+3 Host Interrupt Map Register for 28 to 28+3 Host Interrupt Map Register for 32 to 32+3 Host Interrupt Map Register for 36 to 36+3 Host Interrupt Map Register for 40 to 40+3 Host Interrupt Map Register for 44 to 44+3 Host Interrupt Map Register for 48 to 48+3
Table 5-28
Address Offset 0x810 0x814 0x818 0x81c 0x820 0x824 0x828 0x82c 0x830 0x834 0x1500 0x1504
Host Interrupt Enable Register 0 Host Interrupt Enable Register 1
End of Table 5-28

Table 5-29
Address Offset 0x0 0x10 0x20 0x24 0x28 0x2c 0x34 0x38 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x280 0x284

Register Mnemonic REVISION_REG GLOBAL_ENABLE_HINT_REG STATUS_SET_INDEX_REG STATUS_CLR_INDEX_REG ENABLE_SET_INDEX_REG ENABLE_CLR_INDEX_REG HINT_ENABLE_SET_INDEX_REG HINT_ENABLE_CLR_INDEX_REG RAW_STATUS_REG0 RAW_STATUS_REG1 RAW_STATUS_REG2 RAW_STATUS_REG3 RAW_STATUS_REG4 RAW_STATUS_REG5 RAW_STATUS_REG6 RAW_STATUS_REG7 RAW_STATUS_REG8 RAW_STATUS_REG9 RAW_STATUS_REG10 RAW_STATUS_REG11 RAW_STATUS_REG12 RAW_STATUS_REG13 RAW_STATUS_REG14 RAW_STATUS_REG15 ENA_STATUS_REG0 ENA_STATUS_REG1 Register Name Revision Register Global Host Interrupt Enable Register Status Set Index Register Status Clear Index Register Enable Set Index Register Enable Clear Index Register Host Interrupt Enable Set Index Register Host Interrupt Enable Clear Index Register Raw Status Register 0 Raw Status Register 1 Raw Status Register 2 Raw Status Register 3 Raw Status Register 4 Raw Status Register 5 Raw Status Register 6 Raw Status Register 7 Raw Status Register 8 Raw Status Register 9 Raw Status Register 10 Raw Status Register 11 Raw Status Register 12 Raw Status Register 13 Raw Status Register 14 Raw Status Register 15 Enabled Status Register 0 Enabled Status Register 1
171
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Host Interrupt Map Register for 52 to 52+3

Address Offset 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4
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Register Mnemonic ENA_STATUS_REG2 ENA_STATUS_REG3 ENA_STATUS_REG4 ENA_STATUS_REG5 ENA_STATUS_REG6 ENA_STATUS_REG7 ENA_STATUS_REG8 ENA_STATUS_REG9 ENA_STATUS_REG10 ENA_STATUS_REG11 ENA_STATUS_REG12 ENA_STATUS_REG13 ENA_STATUS_REG14 ENA_STATUS_REG15 ENABLE_REG0 ENABLE_REG1 ENABLE_REG2 ENABLE_REG3 ENABLE_REG4 ENABLE_REG5 ENABLE_REG6 ENABLE_REG7 ENABLE_REG8 ENABLE_REG9 ENABLE_REG10 ENABLE_REG11 ENABLE_REG12 ENABLE_REG13 ENABLE_REG14 ENABLE_REG15 ENABLE_CLR_REG0 ENABLE_CLR_REG1 ENABLE_CLR_REG2 ENABLE_CLR_REG3 ENABLE_CLR_REG4 ENABLE_CLR_REG5 ENABLE_CLR_REG6 ENABLE_CLR_REG7 ENABLE_CLR_REG8 ENABLE_CLR_REG9 ENABLE_CLR_REG10 ENABLE_CLR_REG11 ENABLE_CLR_REG12 ENABLE_CLR_REG13 Register Name Enabled Status Register 2 Enabled Status Register 3 Enabled Status Register 4 Enabled Status Register 5 Enabled Status Register 6 Enabled Status Register 7 Enabled Status Register 8 Enabled Status Register 9 Enabled Status Register10 Enabled Status Register 11 Enabled Status Register 12 Enabled Status Register 13 Enabled Status Register 14 Enabled Status Register 15 Enable Register 0 Enable Register 1 Enable Register 2 Enable Register 3 Enable Register 4 Enable Register 5 Enable Register 6 Enable Register 7 Enable Register 8 Enable Register 9 Enable Register 10 Enable Register 11 Enable Register 12 Enable Register 13 Enable Register 14 Enable Register 15 Enable Clear Register 0 Enable Clear Register 1 Enable Clear Register 2 Enable Clear Register 3 Enable Clear Register 4 Enable Clear Register 5 Enable Clear Register 6 Enable Clear Register 7 Enable Clear Register 8 Enable Clear Register 9 Enable Clear Register 10 Enable Clear Register 11 Enable Clear Register 12 Enable Clear Register 13
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Register Mnemonic ENABLE_CLR_REG14 ENABLE_CLR_REG15 CH_MAP_REG0 CH_MAP_REG1 CH_MAP_REG2 CH_MAP_REG3 CH_MAP_REG4 CH_MAP_REG5 CH_MAP_REG6 CH_MAP_REG7 CH_MAP_REG8 CH_MAP_REG9 CH_MAP_REG10 CH_MAP_REG11 CH_MAP_REG12 CH_MAP_REG13 CH_MAP_REG14 CH_MAP_REG15 CH_MAP_REG116 CH_MAP_REG117 CH_MAP_REG118 CH_MAP_REG119 CH_MAP_REG120 CH_MAP_REG121 CH_MAP_REG122 CH_MAP_REG123 CH_MAP_REG124 CH_MAP_REG125 CH_MAP_REG126 CH_MAP_REG127 CH_MAP_REG128 CH_MAP_REG129 CH_MAP_REG130 CH_MAP_REG131 CH_MAP_REG132 CH_MAP_REG133 CH_MAP_REG134 CH_MAP_REG135 CH_MAP_REG136 CH_MAP_REG137 CH_MAP_REG138 CH_MAP_REG139 CH_MAP_REG140 CH_MAP_REG141 Register Name Enable Clear Register 14 Enable Clear Register 15 Interrupt Channel Map Register for 0 to 0+3 Interrupt Channel Map Register for 4 to 4+3 Interrupt Channel Map Register for 8 to 8+3 Interrupt Channel Map Register for 12 to 12+3 Interrupt Channel Map Register for 16 to 16+3 Interrupt Channel Map Register for 20 to 20+3 Interrupt Channel Map Register for 24 to 24+3
Table 5-29
Address Offset 0x3B8 0x38C 0x400 0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420 0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x5C0 0x5C4 0x5C8 0x5CC 0x5D0 0x5D4 0x5D8 0x5DC 0x5E0 0x5E4 0x5E8 0x5EC 0x5F0 0x5F4 0x5F8 0x5FC 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620 0x624
173
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Address Offset 0x628 0x62C 0x630 0x634 0x638 0x63C 0x640 0x644 0x648 0x64C 0x650 0x654 0x658 0x65C 0x660 0x664 0x668 0x66C 0x670 0x674 0x678 0x67C 0x680 0x684 0x688 0x68C 0x690 0x694 0x698 0x69C 0x800 0x804 0x808 0x80c 0x810 0x814 0x818 0x81c 0x820 0x824 0x828 0x1500 0x1504 End of Table 5-29
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Register Mnemonic CH_MAP_REG142 CH_MAP_REG143 CH_MAP_REG144 CH_MAP_REG145 CH_MAP_REG146 CH_MAP_REG147 CH_MAP_REG148 CH_MAP_REG149 CH_MAP_REG150 CH_MAP_REG151 CH_MAP_REG152 CH_MAP_REG153 CH_MAP_REG154 CH_MAP_REG155 CH_MAP_REG156 CH_MAP_REG157 CH_MAP_REG158 CH_MAP_REG159 CH_MAP_REG160 CH_MAP_REG161 CH_MAP_REG162 CH_MAP_REG163 CH_MAP_REG164 CH_MAP_REG165 CH_MAP_REG166 CH_MAP_REG167 CH_MAP_REG168 CH_MAP_REG169 CH_MAP_REG170 CH_MAP_REG171 HINT_MAP_REG0 HINT_MAP_REG1 HINT_MAP_REG2 HINT_MAP_REG3 HINT_MAP_REG4 HINT_MAP_REG5 HINT_MAP_REG6 HINT_MAP_REG7 HINT_MAP_REG8 HINT_MAP_REG9 HINT_MAP_REG10 ENABLE_HINT_REG0 ENABLE_HINT_REG1 Register Name Interrupt Channel Map Register for 568 to 568+3 Interrupt Channel Map Register for 572 to 572+3 Interrupt Channel Map Register for 576 to 576+3 Interrupt Channel Map Register for 580 to 580+3 Interrupt Channel Map Register for 584 to 584+3 Interrupt Channel Map Register for 588 to 588+3 Interrupt Channel Map Register for 592 to 592+3 Interrupt Channel Map Register for 596 to 596+3 Interrupt Channel Map Register for 600 to 600+3 Interrupt Channel Map Register for 604 to 604+3 Interrupt Channel Map Register for 608 to 608+3 Interrupt Channel Map Register for 612 to 612+3 Interrupt Channel Map Register for 616 to 616+3 Interrupt Channel Map Register for 620 to 620+3 Interrupt Channel Map Register for 624 to 624+3 Interrupt Channel Map Register for 628 to 628+3 Interrupt Channel Map Register for 632 to 632+3 Interrupt Channel Map Register for 636 to 636+3 Interrupt Channel Map Register for 640 to 640+3 Interrupt Channel Map Register for 644 to 644+3 Interrupt Channel Map Register for 648 to 648+3 Interrupt Channel Map Register for 652 to 652+3 Interrupt Channel Map Register for 656 to 656+3 Interrupt Channel Map Register for 660 to 660+3 Interrupt Channel Map Register for 664 to 664+3 Interrupt Channel Map Register for 668 to 668+3 Interrupt Channel Map Register for 672 to 672+3 Interrupt Channel Map Register for 676 to 676+3 Interrupt Channel Map Register for 680 to 680+3 Interrupt Channel Map Register for 684 to 684+3 Host Interrupt Map Register for 0 to 0+3 Host Interrupt Map Register for 4 to 4+3 Host Interrupt Map Register for 8 to 8+3 Host Interrupt Map Register for 12 to 12+3 Host Interrupt Map Register for 16 to 16+3 Host Interrupt Map Register for 20 to 20+3 Host Interrupt Map Register for 24 to 24+3 Host Interrupt Map Register for 28 to 28+3 Host Interrupt Map Register for 32 to 32+3 Host Interrupt Map Register for 36 to 36+3 Host Interrupt Map Register for 40 to 40+3 Host Interrupt Enable Register 0 Host Interrupt Enable Register 1
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SPRS835DAugust 2013
5.3.3 Inter-Processor Register Map

Table 5-30
Address Start 0x02620200 0x02620204 0x02620208 0x0262020C 0x02620210 0x02620214 0x02620218 0x0262021C 0x02620220 0x02620240 0x02620244 0x02620248 0x0262024C 0x02620250 0x02620254 0x02620258 0x0262025C 0x02620260 0x02620264 0x02620268 0x0262026C 0x02620270 0x0262027C 0x02620280 0x02620284 0x02620288 0x0262028C 0x02620290 0x02620294 0x02620298 0x0262029C 0x026202A0 0x026202A4 0x026202A8 0x026202AC 0x026202B0 0x026202A0 0x026202BC End of Table 5-30
IPC Generation Registers (IPCGRx)

Address End 0x02620203 0x02620207 0x0262020B 0x0262020F 0x02620213 0x02620217 0x0262021B 0x0262021F 0x0262023F 0x02620243 0x02620247 0x0262024B 0x0262024F 0x02620253 0x02620257 0x0262025B 0x0262025F 0x02620263 0x02620267 0x0262026B 0x0262026F 0x0262027B 0x0262027F 0x02620283 0x02620287 0x0262028B 0x0262028F 0x02620293 0x02620297 0x0262029B 0x0262029F 0x026202A3 0x026202A7 0x026202AB 0x026202AF 0x026202BB 0x026202BB 0x026202BF Size 4B 4B 4B 4B 4B 4B 4B 4B 32B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 12B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 12B 28B 4B Register Name NMIGR0 NMIGR1 NMIGR2 NMIGR3 NMIGR4 NMIGR5 NMIGR6 NMIGR7 Reserved IPCGR0 IPCGR1 IPCGR2 IPCGR3 IPCGR4 IPCGR5 IPCGR6 IPCGR7 IPCGR8 IPCGR9 IPCGR10 IPCGR11 Reserved IPCGRH IPCAR0 IPCAR1 IPCAR2 IPCAR3 IPCAR4 IPCAR5 IPCAR6 IPCAR7 IPCAR8 IPCAR9 IPCAR10 IPCAR11 Reserved Reserved IPCARH Description NMI Event Generation Register for C66x CorePac0 NMI Event Generation Register for C66x CorePac1 NMI Event Generation Register for C66x CorePac2 NMI Event Generation Register for C66x CorePac3 NMI Event Generation Register for C66x CorePac4 NMI Event Generation Register for C66x CorePac5 NMI Event Generation Register for C66x CorePac6
Reserved IPC Generation Register for C66x CorePac0 IPC Generation Register for C66x CorePac1 IPC Generation Register for C66x CorePac2 IPC Generation Register for C66x CorePac3 IPC Generation Register for C66x CorePac4 IPC Generation Register for C66x CorePac5 IPC Generation Register for C66x CorePac6 IPC Generation Register for C66x CorePac7 IPC Generation Register for ARM CorePac0 IPC Generation Register for ARM CorePac1 IPC Generation Register for ARM CorePac2 IPC Generation Register for ARM CorePac3 Reserved IPC Generation Register for Host IPC Acknowledgement Register for C66x CorePac0 IPC Acknowledgement Register for C66x CorePac1 IPC Acknowledgement Register for C66x CorePac2 IPC Acknowledgement Register for C66x CorePac3 IPC Acknowledgement Register for C66x CorePac4 IPC Acknowledgement Register for C66x CorePac5 IPC Acknowledgement Register for C66x CorePac6 IPC Acknowledgement Register for C66x CorePac7 IPC Acknowledgement Register for ARM CorePac0 IPC Acknowledgement Register for ARM CorePac1 IPC Acknowledgement Register for ARM CorePac2 IPC Acknowledgement Register for ARM CorePac3 Reserved Reserved IPC Acknowledgement Register for host
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NMI Event Generation Register for C66x CorePac7

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5.3.4 NMI and LRESET The Non-Maskable Interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One NMI pin and one LRESET pin are shared by all eight C66x CorePacs on the device. The CORESEL[3:0] pins can be configured to select between the eight C66x CorePacs available as shown in Table 5-31.
Table 5-31
XXXX 0000 0001 0010 0011 0100 0101 0110 0111 1XXX 0000 0001 0010 0011 0100 0101 0110 0111 1XXX 0000 0001 0010 0011 0100 0101 0110 0111 1XXX End of Table 5-31
LRESET and NMI Decoding

LRESETNMIEN Pin Input 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Mux Block Output No local reset or NMI assertion Assert local reset to C66x CorePac0 Assert local reset to C66x CorePac1 Assert local reset to C66x CorePac2 Assert local reset to C66x CorePac3 Assert local reset to C66x CorePac4 Assert local reset to C66x CorePac5 Assert local reset to C66x CorePac6 Assert local reset to C66x CorePac7 Assert local reset to all C66x CorePacs De-assert local reset & NMI to C66x CorePac0 De-assert local reset & NMI to C66x CorePac1 De-assert local reset & NMI to C66x CorePac2 De-assert local reset & NMI to C66x CorePac3 De-assert local reset & NMI to C66x CorePac4 De-assert local reset & NMI to C66x CorePac5 De-assert local reset & NMI to C66x CorePac6 De-assert local reset & NMI to C66x CorePac7 De-assert local reset & NMI to all C66x CorePacs Assert NMI to C66x CorePac0 Assert NMI to C66x CorePac1 Assert NMI to C66x CorePac2 Assert NMI to C66x CorePac3 Assert NMI to C66x CorePac4 Assert NMI to C66x CorePac5 Assert NMI to C66x CorePac6 Assert NMI to C66x CorePac7 Assert NMI to all C66x CorePacs X 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input
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5.4 Enhanced Direct Memory Access (EDMA3) Controller for TCI6636K2H

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device C66x DSP CorePac or the ARM CorePac.. There are five EDMA channel controllers on the device: EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1. EDMA3CC1 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3.
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EDMA3CC2 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3. EDMA3CC3 has two transfer controllers: TPTC0 and TPTC1. EDMA3CC4 has two transfer controllers: TPTC0 and TPTC1.
In the context of this document, TPTCx is associated with EDMA3CCy, and is referred to as EDMA3CCy TPTCx. Each of the transfer controllers has a direct connection to the switch fabric. Section 6.2 Switch Fabric Connections Matrix - Data Space on page 189 lists the peripherals that can be accessed by the transfer controllers. EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR3A/DDR3B subsytems. The others are used for the remaining traffic. Each EDMA3 channel controller includes the following features: Fully orthogonal transfer description 3 transfer dimensions: Array (multiple bytes) Frame (multiple arrays) Block (multiple frames) Single event can trigger transfer of array, frame, or entire block Independent indexes on source and destination Flexible transfer definition: Increment or FIFO transfer addressing modes Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention Chaining allows multiple transfers to execute with one event 512 PaRAM entries for all EDMA3CC Used to define transfer context for channels Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry 64 DMA channels for all EDMA3CC Manually triggered (CPU writes to channel controller register) External event triggered Chain triggered (completion of one transfer triggers another) 8 Quick DMA (QDMA) channels per EDMA3CCx Used for software-driven transfers Triggered upon writing to a single PaRAM set entry Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0, EDMA3CC3, and EDMA3CC4 Four transfer controllers and four event queues with programmable system-level priority each for DMA3CC1 and EDMA3CC2 Interrupt generation for transfer completion and error conditions Debug visibility Queue watermarking/threshold allows detection of maximum usage of event queues Error and status recording to facilitate debug
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5.4.1 EDMA3 Device-Specific Information The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases. For most applications, increment mode can be used. On the TCI6636K2H SoC, the EDMA can use constant addressing mode only with the enhanced Viterbi decoder coprocessor (VCP) and the enhanced turbo decoder coprocessor (TCP). Constant addressing mode is not supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers and EDMA3 transfer controller (TPTC) control registers see Section 5.1 Memory Map Summary on page 83. For memory offsets and other details on EDMA3CC and TPTC Control Register entries, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 5.4.2 EDMA3 Channel Controller Configuration Table 5-32 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 5-32
Description Number of DMA channels in channel controller Number of QDMA channels Number of interrupt channels Number of PaRAM set entries Number of event queues Number of transfer controllers Memory protection existence Number of memory protection and shadow regions End of Table 5-32
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EDMA3 Channel Controller Configuration

EDMA3 CC0 64 8 64 512 2 2 Yes 8 EDMA3 CC1 64 8 64 512 4 4 Yes 8 EDMA3 CC2 64 8 64 512 4 4 Yes 8 EDMA3 CC3 64 8 64 512 2 2 Yes 8 EDMA3 CC4 64 8 64 512 2 2 Yes 8
5.4.3 EDMA3 Transfer Controller Configuration Each transfer controller on the device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the transfer controller configurations are: FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data. The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller. BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface. Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a transfer controller. DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of destination FIFO register sets for a transfer controller determines the maximum number of outstanding transfer requests. All four parameters listed above are fixed by the design of the device.
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Table 5-33 shows the configuration of each of the EDMA3 transfer controllers present on the device.
Table 5-33
Parameter FIFOSIZE BUSWIDTH DSTREGDEPTH DBS
EDMA3 Transfer Controller Configuration

EDMA3 CC0/CC4 TC0 1024 bytes 32 bytes 4 entries 128 bytes TC1 1024 bytes 32 bytes TC0 1024 bytes 16 bytes TC1 1024 bytes 16 bytes EDMA3 CC1 TC2 1024 bytes 16 bytes 4 entries 128 bytes TC3 1024 bytes 16 bytes 4 entries 128 bytes TC0 1024 bytes 16 bytes 4 entries 128 bytes EDMA3 CC2 TC1 1024 bytes 16 bytes TC2 1024 bytes 16 bytes TC3 1024 bytes 16 bytes 4 entries 128 bytes EDMA3CC3 TC0 1024 bytes 16 bytes 4 entries 128 bytes TC1 1024 bytes 16 bytes 4 entries 128 bytes
4 entries 4 entries 4 entries 128 bytes 128 bytes 128 bytes
4 entries 4 entries 128 bytes 128 bytes
End of Table 5-33
5.4.4 EDMA3 Channel Synchronization Events The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables list the source of the synchronization event associated with each of the EDMA EDMA3CC DMA channels. On the TCI6636K2H, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed. For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
Table 5-34
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
EDMA3CC0 Events for TCI6636K2H (Part 1 of 2)

Event Name TIMER_8_INTL TIMER_8_INTH TIMER_9_INTL TIMER_9_INTH TIMER_10_INTL TIMER_10_INTH TIMER_11_INTL TIMER_11_INTH CIC_2_OUT66 CIC_2_OUT67 CIC_2_OUT68 CIC_2_OUT69 CIC_2_OUT70 CIC_2_OUT71 CIC_2_OUT72 CIC_2_OUT73 GPIO_INT8 GPIO_INT9 GPIO_INT10 GPIO_INT11 GPIO_INT12 GPIO_INT13 GPIO_INT14 Description Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt
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Event No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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Event Name GPIO_INT15 TIMER_4_INTL TIMER_4_INTH TIMER_5_INTL TIMER_5_INTH TIMER_6_INTL TIMER_6_INTH TIMER_7_INTL TIMER_7_INTH GPIO_INT0 GPIO_INT1 GPIO_INT2 GPIO_INT3 GPIO_INT4 GPIO_INT5 GPIO_INT6 GPIO_INT7 TIMER_0_INTL TIMER_0_INTH TIMER_1_INTL TIMER_1_INTH TIMER_2_INTL TIMER_2_INTH TIMER_3_INTL TIMER_3_INTH SRIO_INTDST0 SRIO_INTDST1 SRIO_INTDST2 SRIO_INTDST3 SRIO_INTDST4 SRIO_INTDST5 SRIO_INTDST6 SRIO_INTDST7 AIF_ATEVT0 AIF_ATEVT1 AIF_ATEVT2 AIF_ATEVT3 AIF_ATEVT4 AIF_ATEVT5 AIF_ATEVT6 AIF_ATEVT7 Description GPIO interrupt Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer
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End of Table 5-34
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SPRS835DAugust 2013 EDMA3CC1 Events for TCI6636K2H (Part 1 of 2)

Event Name SPI_0_INT0 SPI_0_INT1 SPI_0_XEVT SPI_0_REVT SEM_INT8 SEM_INT9 GPIO_INT0 GPIO_INT1 GPIO_INT2 GPIO_INT3 AIF_ATEVT0 AIF_ATEVT1 AIF_ATEVT2 AIF_ATEVT3 SEM_INT0 SEM_INT1 SEM_INT2 SEM_INT3 SEM_INT4 SEM_INT5 SEM_INT6 SEM_INT7 TIMER_8_INTL TIMER_8_INTH TIMER_9_INTL TIMER_9_INTH TIMER_10_INTL TIMER_10_INTH TIMER_11_INTL TIMER_11_INTH TIMER_12_INTL TIMER_12_INTH TIMER_13_INTL TIMER_13_INTH TIMER_14_INTL TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH SEM_INT10 SEM_INT11 SEM_INT12 SEM_INT13 CIC_2_OUT0 CIC_2_OUT1 Description SPI0 interrupt SPI0 interrupt SPI0 transmit event SPI0 receive event Semaphore interrupt Semaphore interrupt GPIO interrupt GPIO interrupt GPIO interrupt
Table 5-35
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AIF Timer event AIF Timer event AIF Timer event AIF Timer event Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Semaphore interrupt Semaphore interrupt Semaphore interrupt Semaphore interrupt CIC2 Interrupt Controller output CIC2 Interrupt Controller output
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GPIO interrupt

Event No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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Event Name CIC_2_OUT2 CIC_2_OUT3 CIC_2_OUT4 CIC_2_OUT5 CIC_2_OUT6 CIC_2_OUT7 CIC_2_OUT8 AIF_ATEVT4 AIF_ATEVT5 I2C_0_REVT I2C_0_XEVT CIC_2_OUT13 CIC_2_OUT14 CIC_2_OUT15 CIC_2_OUT16 CIC_2_OUT17 CIC_2_OUT18 CIC_2_OUT19 USIM_RREQ USIM_WREQ Description CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output AIF Timer event AIF Timer event I2C0 receive I2C0 transmit CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output USIM read DMA event USIM write DMA event
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End of Table 5-35
Table 5-36
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Event Name TAC_DEVT2 TAC_DEVT3 TAC_DEVT4 TAC_DEVT5 AIF_ATEVT4 AIF_ATEVT5 TETB_FULLINT4 TETB_HFULLINT4 TETB_FULLINT5 TETB_HFULLINT5 TETB_FULLINT6 TETB_HFULLINT6 TETB_FULLINT7 TETB_HFULLINT7 SRIO_INTDST0 SRIO_INTDST1 SRIO_INTDST2 SRIO_INTDST3 SRIO_INTDST4 SRIO_INTDST5 Description TAC debug TAC debug TAC debug TAC debug AIF timer AIF timer TETB4 is full TETB4 is half full TETB5 is full TETB5 is half full TETB6 is full TETB6 is half full TETB7 is full TETB7 is half full SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt
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Event Name SRIO_INTDST6 SRIO_INTDST7 AIF_ATEVT6 AIF_ATEVT7 TAC_DEVT0 TAC_DEVT1 GPIO_INT0 GPIO_INT1 GPIO_INT2 GPIO_INT3 GPIO_INT4 GPIO_INT5 GPIO_INT6 GPIO_INT7 TCP3D_0_REVT0 TCP3D_0_REVT1 TCP3D_1_REVT0 TCP3D_1_REVT1 CIC_2_OUT48 TAC_INT UART_0_URXEVT UART_0_UTXEVT CIC_2_OUT22 CIC_2_OUT23 CIC_2_OUT24 CIC_2_OUT25 CIC_2_OUT26 CIC_2_OUT27 CIC_2_OUT28 SPI_0_XEVT SPI_0_REVT VCP2_0_REVT0 VCP2_0_XEVT0 VCP2_0_REVT1 VCP2_0_XEVT1 VCP2_0_REVT2 VCP2_0_XEVT2 VCP2_0_REVT3 VCP2_0_XEVT3 RAC_0_INT RAC_1_INT Reserved Description SRIO interrupt SRIO interrupt AIF timer AIF timer TAC debug TAC debug GPIO interrupt GPIO interrupt GPIO interrupt
Table 5-36
Event No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt TCP3d event TCP3d event TCP3d event TCP3d event CIC2 Interrupt Controller output TAC interrupt UART0 receive event UART0 transmit event CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output SPI0 transmit event SPI0 receive event VCP receive event VCP transmit event VCP receive event VCP transmit event VCP receive event VCP transmit event VCP receive event VCP transmit event RAC interrupt RAC interrupt Reserved
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GPIO interrupt

Event No. 62 63
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Event Name Reserved BCP_INT0 Description Reserved BCP interrupt
End of Table 5-36
Table 5-37
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Event Name SPI_2_INT0 SPI_2_INT1 SPI_2_XEVT SPI_2_REVT I2C_2_REVT I2C_2_XEVT UART_1_URXEVT UART_1_UTXEVT SPI_1_INT0 SPI_1_INT1 SPI_1_XEVT SPI_1_REVT I2C_0_REVT I2C_0_XEVT I2C_1_REVT I2C_1_XEVT SRIO_INTDST0 SRIO_INTDST1 SRIO_INTDST2 SRIO_INTDST3 SRIO_INTDST4 SRIO_INTDST5 SRIO_INTDST6 SRIO_INTDST7 TCP3D_0_REVT0 TCP3D_0_REVT1 TCP3D_1_REVT0 TCP3D_1_REVT1 Reserved Reserved Reserved Reserved TETB_FULLINT0 TETB_HFULLINT0 TETB_FULLINT1 TETB_HFULLINT1 TETB_FULLINT2 TETB_HFULLINT2 Description SPI2 interrupt SPI2 interrupt SPI2 transmit event SPI2 receive event I2C2 receive I2C2 transmit UART1 receive event UART1 transmit event SPI1 interrupt SPI1 interrupt SPI1 transmit event SPI1 receive event I2C0 receive I2C0 transmit I2C1 receive I2C1 transmit SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt SRIO interrupt TCP3d event TCP3d event TCP3d event TCP3d event Reserved Reserved Reserved Reserved TETB0 is full TETB0 is half full TETB1 is full TETB1 is half full TETB2 is full TETB2 is half full
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Event Name TETB_FULLINT3 TETB_HFULLINT3 VCP2_0_REVT0 VCP2_0_XEVT0 VCP2_0_REVT1 VCP2_0_XEVT1 VCP2_0_REVT2 VCP2_0_XEVT2 VCP2_0_REVT3 VCP2_0_XEVT3 VCP2_1_REVT0 VCP2_1_XEVT0 VCP2_1_REVT1 VCP2_1_XEVT1 VCP2_1_REVT2 VCP2_1_XEVT2 VCP2_1_REVT3 VCP2_1_XEVT3 CIC_2_OUT57 CIC_2_OUT50 CIC_2_OUT51 CIC_2_OUT52 CIC_2_OUT53 CIC_2_OUT54 CIC_2_OUT55 CIC_2_OUT56 Description TETB3 is full TETB3 is half full VCP event VCP event VCP event VCP event VCP event VCP event VCP event
Table 5-37
Event No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
VCP event VCP event VCP event VCP event VCP event VCP event VCP event VCP event CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output
End of Table 5-37
Table 5-38
Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13

Event Name GPIO_INT16 GPIO_INT17 GPIO_INT18 GPIO_INT19 GPIO_INT20 GPIO_INT21 GPIO_INT22 GPIO_INT23 AIF_ATEVT0 AIF_ATEVT1 AIF_ATEVT2 AIF_ATEVT3 AIF_ATEVT4 AIF_ATEVT5 Description GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer
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VCP event

Event No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
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Event Name AIF_ATEVT6 AIF_ATEVT7 AIF_ATEVT16 AIF_ATEVT17 AIF_ATEVT18 AIF_ATEVT19 AIF_ATEVT20 AIF_ATEVT21 AIF_ATEVT22 AIF_ATEVT23 TIMER_8_INTL TIMER_8_INTH TIMER_14_INTL TIMER_14_INTH TIMER_15_INTL TIMER_15_INTH DBGTBR_DMAINT ARM_TBR_DMA QMSS_QUE_PEND_658 QMSS_QUE_PEND_659 QMSS_QUE_PEND_660 QMSS_QUE_PEND_661 QMSS_QUE_PEND_662 QMSS_QUE_PEND_663 QMSS_QUE_PEND_664 QMSS_QUE_PEND_665 QMSS_QUE_PEND_8736 QMSS_QUE_PEND_8737 QMSS_QUE_PEND_8738 QMSS_QUE_PEND_8739 QMSS_QUE_PEND_8740 QMSS_QUE_PEND_8741 QMSS_QUE_PEND_8742 QMSS_QUE_PEND_8743 ARM_NCNTVIRQ3 ARM_NCNTVIRQ2 ARM_NCNTVIRQ1 ARM_NCNTVIRQ0 ARM_NCNTPNSIRQ3 ARM_NCNTPNSIRQ2 ARM_NCNTPNSIRQ1 ARM_NCNTPNSIRQ0 CIC_2_OUT82 CIC_2_OUT83 Description AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer AIF timer Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Timer interrupt low Timer interrupt high Debug trace buffer (TBR) DMA event ARM trace buffer (TBR) DMA event Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue Navigator transmit queue pending event for indicated queue ARM virtual timer interrupt for core 3 ARM virtual timer interrupt for core 2 ARM virtual timer interrupt for core 1 ARM virtual timer interrupt for core 0 ARM non secure timer interrupt for core 3 ARM non secure timer interrupt for core 2 ARM non secure timer interrupt for core 1 ARM non secure timer interrupt for core 0 CIC2 Interrupt Controller output CIC2 Interrupt Controller output
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Event Name CIC_2_OUT84 CIC_2_OUT85 CIC_2_OUT86 CIC_2_OUT87 CIC_2_OUT88 CIC_2_OUT89 Description CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output CIC2 Interrupt Controller output
Table 5-38
Event No. 58 59 60 61 62 63
End of Table 5-38
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6 System Interconnect
On the KeyStone II devices, the C66x CorePac, the EDMA3 transfer controllers, and the system peripherals are interconnected through the TeraNets, which are non-blocking switch fabrics enabling fast and contention-free internal data movement. The TeraNets provide low-latency, concurrent data transfers between master peripherals and slave peripherals. The TeraNets also allow for seamless arbitration between the system masters when accessing system slaves. The ARM CorePac is connected to the MSMC and the debug subsystem directly, and to other masters via the TeraNets. Through the MSMC, the ARM CorePacs can be interconnected to DDR3A and TeraNet 3_A, which allows the ARM CorePacs to access to the peripheral buses: TeraNet 3P_A for peripheral configuration TeraNet 6P_A for ARM Boot ROM TeraNet 3_C for DDR3B
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6.1 Internal Buses and Switch Fabrics

The C66x CorePacs, the ARM CorePacs, the EDMA3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves on the other hand rely on the masters to perform transfers to and from them.
Examples of masters include the EDMA3 traffic controllers, SRIO, and network coprocessor packet DMA. Examples of slaves include the SPI, UART, and I C. The masters and slaves in the device communicate through the TeraNet (switch fabric). The device contains two types of switch fabric: Data TeraNet is a high-throughput interconnect mainly used to move data across the system Configuration TeraNet is mainly used to access peripheral registers
2
Some peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral. Note that the data TeraNet also connects to the configuration TeraNet.
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6.2 Switch Fabric Connections Matrix - Data Space

The figures below show the connections between masters and slaves through various sections of the TeraNet.
Figure 6-1
Bridge_1 Bridge_2 From TeraNet_3_C Bridge_3 MPU_8 MPU_12
TeraNet 3_A-1
Bridge_11 Tracer_SPI_ ROM_EMIF16
6636
S S S S S S
EMIF16 SPI_0
CPU/3
SRIO Packet DMA QM Packet DMA QM_2 Packet DMA FFTC_0 Packet DMA FFTC_1 Packet DMA FFTC_2 Packet DMA FFTC_3 Packet DMA Debug_SS BCP_DIO0 TAC_FE2 TAC_FE3 TAC_FE BCP_DIO1 USB_MST
M M M M M M M M M M M M M M
TNet_3_G CPU/3 TNet_3_F CPU/3 TNet_3_D CPU/3
TNet_6P_A CPU/6
MPU_14
SPI_2 Boot_ROM Boot_ROM ARM VCP2_0 VCP2_1 VCP2_2 VCP2_3 Bridge_5 Bridge_6 Bridge_7
TeraNet 3_A-1
S
TNet_3_H CPU/3
S S S
To TeraNet_3_C Bridge_8 Bridge_9 Bridge_10 Bridge_12 To TeraNet_3P_A Bridge_13 Bridge_14
System Interconnect
189
PRODUCT PREVIEW
BCP Packet DMA
MPU_13
SPI_1

6636 www.ti.com
TeraNet 3_A-2
Tracer_TAC_BE MPU_1 Tracer_QM_M
S S
TAC_BE1 QM_SS
Tracer_SPI_ ROM_EMIF16
CPU/3
S S S S S
PCIe TCP3d_0 TCP3d_1 RAC_0_FE RAC_1_FE
XGE NETCP
M M M M M M M M M M M M M M M M M
TNet_3_L CPU/3
TeraNet 3_A-2
PRODUCT PREVIEW
190
AIF/DMA RAC_0_BE1_HP RAC_1_BE1_HP TC_0 EDMA CC1 TC_1 TC_2 TC_3 TC_0 EDMA CC2 TC_1 TC_2 TC_3 EDMA CC3 TC_0 TC_1 SRIO_M PCIe
L2 Cache_0_A L2 Cache_0_B L2 Cache_1_A L2 Cache_1_B L2 Cache_2_A L2 Cache_2_B L2 Cache_3_A L2 Cache_3_B To TeraNet C66x SDMA L2 Cache_4_A L2 Cache_4_B L2 Cache_5_A L2 Cache_5_B L2 Cache_6_A L2 Cache_6_B L2 Cache_7_A L2 Cache_7_B
System Interconnect

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SPRS835DAugust 2013 TeraNet 3_C
Figure 6-3
XMC
6636
ARM CorePac
TeraNet 3_B CPU/3
HyperLink 0 HyperLink 1
M M
S S S S
SES SMS
HyperLink 0 HyperLink 1
S
MSMC
Tracer_ MSMC0-8
M
BR_SES_0 Bridge_5 Bridge_6 Bridge_7 From TeraNet_3_A Bridge_8 Bridge_9 Bridge_10
DDR3A
CPU/3
BR_SES_1 BR_SES_2 BR_SMS_0 BR_SMS_1 BR_SMS_2
TNet_SES CPU/1
TNet_SMS CPU/1
TeraNet 3_C
TNet_msmc_sys CPU/1
To TeraNet_3_A To TeraNet_3P_A
QM_Second EDMA CC0 EDMA CC4 TC_0 TC_1 TC_0 TC_1
M M M M M M M
TNet_3_J CPU/3
CPU Port Sys Port
TNet_3_U CPU/3
MPU_7 Tracer_DDRB
DDR3B
Bridge_1 To TeraNet_3_A Bridge_2 Bridge_3
RAC_0_BE1_LP RAC_1_BE1_LP
System Interconnect
191
PRODUCT PREVIEW

SPRS835DAugust 2013 Figure 6-4 TeraNet C66x to SDMA
6636 www.ti.com
L2 Cache_0_A L2 Cache_0_B L2 Cache_1_A L2 Cache_1_B L2 Cache_2_A L2 Cache_2_B L2 Cache_3_A
TNet_3_M CPU/3 TNet_3_N CPU/3 TNet_3_O CPU/3 TNet_3_P CPU/3

From TeraNet 3_A-2
Tracer_L2_0
CorePac_0
Tracer_L2_1
CorePac_1
Tracer_L2_2
CorePac_2
L2 Cache_3_B L2 Cache_4_A L2 Cache_4_B L2 Cache_5_A L2 Cache_5_B L2 Cache_6_A L2 Cache_6_B L2 Cache_7_A L2 Cache_7_B
Tracer_L2_3
CorePac_3
PRODUCT PREVIEW
192
TNet_3_Q CPU/3 TNet_3_R CPU/3 TNet_3_S CPU/3 TNet_3_T CPU/3
Tracer_L2_4
CorePac_4
Tracer_L2_5
CorePac_5
Tracer_L2_6
CorePac_6
Tracer_L2_7
CorePac_7
System Interconnect

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SPRS835DAugust 2013
The following tables list the master and slave end point connections. Intersecting cells may contain one of the following: Y There is a connection between this master and that slave. - There is NO connection between this master and that slave. n A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 6-1 Data Space Interconnect -Section 1 (Part 1 of 3)
Slaves BCR_RAC_(0-1)_FEI CorePac0_SDMA CorePac1_SDMA CorePac2_SDMA CorePac3_SDMA CorePac4_SDMA CorePac5_SDMA CorePac6_SDMA CorePac7_SDMA BootROM_C66x BootROM_ARM
DBG_STM
AEMIF16
Masters 10GbE AIF2 BCP BCP_DIO(0) BCP_DIO(1) CorePac0_CFG CorePac1_CFG CorePac2_CFG CorePac3_CFG CorePac4_CFG CorePac5_CFG CorePac6_CFG CorePac7_CFG CPT_BCR_CFG CPT_CFG CPT_DDR3A CPT_DDR3B CPT_INTC CPT_L2_(0-7) CPT_MSMC(0-7) CPT_QM_CFG1 CPT_QM_CFG2 CPT_QM_M CPT_RAC_CFG1 CPT_RAC_CFG2 CPT_RAC_FEI CPT_SM CPT_SPI_ROM_EMIF16 CPT_TAC_BE CPT_TPCC(0_4)T CPT_TPCC(1_2_3)T DBG_DAP
11 Y
42 42 Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
System Interconnect
193
PRODUCT PREVIEW

SPRS835DAugust 2013 Table 6-1 Data Space Interconnect -Section 1 (Part 2 of 3)
Slaves BCR_RAC_(0-1)_FEI CorePac0_SDMA CorePac1_SDMA CorePac2_SDMA CorePac3_SDMA CorePac4_SDMA CorePac5_SDMA CorePac6_SDMA CorePac7_SDMA Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y BootROM_C66x BootROM_ARM
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Masters EDMA0_CC_TR EDMA0_TC0_RD EDMA0_TC0_WR EDMA0_TC1_RD EDMA0_TC1_WR EDMA1_CC_TR EDMA1_TC0_RD EDMA1_TC0_WR EDMA1_TC1_RD EDMA1_TC1_WR EDMA1_TC2_RD EDMA1_TC2_WR EDMA1_TC3_RD EDMA1_TC3_WR EDMA2_CC_TR EDMA2_TC0_RD EDMA2_TC0_WR EDMA2_TC1_RD EDMA2_TC1_WR EDMA2_TC2_RD EDMA2_TC2_WR EDMA2_TC3_RD EDMA2_TC3_WR EDMA3_CC_TR EDMA3_TC0_RD EDMA3_TC0_WR EDMA3_TC1_RD EDMA3_TC1_WR EDMA4_CC_TR EDMA4_TC0_RD EDMA4_TC0_WR EDMA4_TC1_RD EDMA4_TC1_WR FFTC_0 FFTC_1 FFTC_2 FFTC_3 HyperLink0_Master HyperLink1_Master
2,11 2,11 3,11 3,11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 2,11 2,11 3,11 3,11 11 11 11 11 11 11
42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42
2,11 3,11 11 Y Y Y Y Y Y Y Y Y 2,11 3,11 1,11 1,11
2,11 3,11 11 Y Y Y Y Y Y Y Y Y 2,11 3,11 1,11 1,11
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
194
System Interconnect
DBG_STM Y Y Y Y Y Y Y Y Y -
AEMIF16
PRODUCT PREVIEW

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SPRS835DAugust 2013 Data Space Interconnect -Section 1 (Part 3 of 3)

Slaves BCR_RAC_(0-1)_FEI CorePac0_SDMA CorePac1_SDMA CorePac2_SDMA CorePac3_SDMA CorePac4_SDMA CorePac5_SDMA CorePac6_SDMA CorePac7_SDMA Y Y Y Y Y Y Y Y Y Y Y Y Y Y BootROM_C66x BootROM_ARM
Table 6-1
Masters MSMC_SYS NETCP PCIE QM_Master1 QM_Master2 QM_SEC RAC_0_BE0 RAC_0_BE1 RAC_1_BE0 RAC_1_BE1 SRIO SRIO Packet DMA TAC_FEI(0-2) USB End of Table 6-1
11 11 11 11 -
42 42 42 -
11 -
11 -
Y Y Y Y Y Y Y Y Y Y Y Y Y Y
DBG_STM Y Y Y Y Y
AEMIF16
Table 6-2
Data Space Interconnect - Section 2 (Part 1 of 3)

Slaves TCP3D_(0-1)_DATA VCP2_(0-3)_DATA
MSMC_SMS
HyperLink0
HyperLink1
MSMC_SES
Masters 10GbE AIF2 BCP BCP_DIO(0) BCP_DIO(1) CorePac0_CFG CorePac1_CFG CorePac2_CFG CorePac3_CFG CorePac4_CFG CorePac5_CFG CorePac6_CFG CorePac7_CFG CPT_BCR_CFG
10 9 6 5 9 -
Y Y Y Y -
Y Y Y Y -
SES_2 SES_2 SES_0 SES_0 SES_2 -
SMS_2 SMS_2 SMS_0 SMS_0 SMS_2 -
Y -
Y Y Y Y Y -
11 -
TAC_BEI
SPI(0-2)
DDR3B
PCIE
QM
Y Y -
Y -
Y -
System Interconnect
195
PRODUCT PREVIEW

SPRS835DAugust 2013 Table 6-2 Data Space Interconnect - Section 2 (Part 2 of 3)
Slaves TCP3D_(0-1)_DATA VCP2_(0-3)_DATA Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
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MSMC_SMS
HyperLink0
HyperLink1
MSMC_SES
Masters CPT_CFG CPT_DDR3A CPT_DDR3B CPT_INTC CPT_L2_(0-7) CPT_MSMC(0-7) CPT_QM_CFG1 CPT_QM_CFG2 CPT_QM_M CPT_RAC_CFG1 CPT_RAC_CFG2 CPT_RAC_FEI CPT_SM CPT_SPI_ROM_EMIF16 CPT_TAC_BE CPT_TPCC(0_4)T CPT_TPCC(1_2_3)T DBG_DAP EDMA0_CC_TR EDMA0_TC0_RD EDMA0_TC0_WR EDMA0_TC1_RD EDMA0_TC1_WR EDMA1_CC_TR EDMA1_TC0_RD EDMA1_TC0_WR EDMA1_TC1_RD EDMA1_TC1_WR EDMA1_TC2_RD EDMA1_TC2_WR EDMA1_TC3_RD EDMA1_TC3_WR EDMA2_CC_TR EDMA2_TC0_RD EDMA2_TC0_WR EDMA2_TC1_RD EDMA2_TC1_WR EDMA2_TC2_RD EDMA2_TC2_WR
Y Y Y Y Y 5 5 6 6 7 7 8 8 9 9 10 10 5 5
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Y SES_0 SES_0 SES_1 SES_1 SES_0 SES_0 SES_1 SES_1 SES_1 SES_1 SES_1 SES_1 SES_2 SES_2 SES_2 SES_2 SES_0 SES_0
Y SMS_0 SMS_0 SMS_1 SMS_1 SMS_0 SMS_0 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_2 SMS_2 SMS_2 SMS_2 SMS_0 SMS_0
Y Y Y Y Y Y Y Y Y Y Y -
Y 2,11 2,11 3,11 3,11 11 11 11 11 11 11 11 11 11 11 11 11 11 11
TAC_BEI Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
SPI(0-2)
DDR3B
PCIE
QM
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
PRODUCT PREVIEW
196
System Interconnect

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SPRS835DAugust 2013 Data Space Interconnect - Section 2 (Part 3 of 3)

Slaves TCP3D_(0-1)_DATA VCP2_(0-3)_DATA Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
Table 6-2
MSMC_SMS
HyperLink0
HyperLink1
MSMC_SES
Masters EDMA2_TC3_RD EDMA2_TC3_WR EDMA3_CC_TR EDMA3_TC0_RD EDMA3_TC0_WR EDMA3_TC1_RD EDMA3_TC1_WR EDMA4_CC_TR EDMA4_TC0_RD EDMA4_TC0_WR EDMA4_TC1_RD EDMA4_TC1_WR FFTC_0 FFTC_1 FFTC_2 FFTC_3 HyperLink0_Master HyperLink1_Master MSMC_SYS NETCP PCIE QM_Master1 QM_Master2 QM_SEC RAC_0_BE0 RAC_0_BE1 RAC_1_BE0 RAC_1_BE1 SRIO SRIO Packet DMA TAC_FEI(0-2) USB End of Table 6-2
6 6 7 7 8 8 Y Y Y Y 7 8 9 5 Y Y Y 7 10 5 8 Y Y Y Y Y 9 9 10 5
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 10 Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 10 Y Y Y Y Y Y Y Y Y Y
SES_0 SES_0 SES_1 SES_1 SES_1 SES_1 SES_1 SES_1 SES_1 SES_1 SES_1 SES_1 SES_2 SES_2 Y Y SES_1 SES_2 SES_0 SES_1 SES_2 SES_2 SES_0 SES_2 SES_2 SES_2 SES_2 SES_0
SMS_0 SMS_0 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_1 SMS_2 SMS_2 Y Y SMS_1 SMS_2 SMS_0 SMS_1 SMS_2 SMS_2 SMS_0 SMS_2 SMS_2 SMS_2 SMS_2 SMS_0
Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 3 3 Y Y Y
11 11 11 11 11 11 2,11 2,11 3,11 3,11 11 11 11 11 Y Y 11 11 11 -
TAC_BEI Y Y Y Y Y Y 11 11 11 11 Y Y Y Y Y -
SPI(0-2)
DDR3B
PCIE
QM
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
System Interconnect
197
PRODUCT PREVIEW

SPRS835DAugust 2013
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6.3 Switch Fabric Connections Matrix - Configuration Space

The figures below show the connections between masters and slaves through various sections of the TeraNet.
Figure 6-5
Bridge_12 Bridge_13 Bridge_14 Tracer_QM_CFG1 From TeraNet_3_C Tracer_QM_CFG2 MPU_10 MPU_6 From TeraNet_3_A Tracer_BCR_CFG MPU_2 MPU_3
TeraNet 3P_A
S S M M S S S S S S S S S
Tracer _EDMA CC1 - CC3 TNet_3P_C CPU/3
MPU ( 15) BCR CFG QM_SS_ CFG1 QM_SS_ CFG2 Semaphore RAC_0_CFG RAC_1_CFG
CorePac_4 CorePac_5 CorePac_6 CorePac_7
M M M M
TeraNet 3P_A
PRODUCT PREVIEW
6636
Tracer_SM
CPU/3
MPU_4 Tracer_ RAC_CFG_1
TNet_3P_H CPU/3
CorePac_0 CorePac_1 CorePac_2 CorePac_3
M M M M
Tracer _EDMA CC0 & CC4
TNet_3P_M CPU/3
CC0 TC ( 2) CC4 TC ( 2)
CC1 TC ( 4) CC2 TC ( 4) CC3 TC ( 2)
S S S S
MPU_9 Tracer_INTC
TNet_3P_L CPU/3
S S
ARM INTC CP_INTC0-2
TETB CorePac ( 8) DBG_TBR_SYS (Debug_SS) TBR_SYS_ ARM_CorePac MPU_0 Tracer_CFG To TeraNet_3P_Tracer To TeraNet_3P_B
198
System Interconnect

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SPRS835DAugust 2013 TeraNet 3P_B

TNet_3P_N CPU/3 TNet_3P_D CPU/3
Figure 6-6
From TeraNet_3P_A
S S S S S S S S S S S S S S S S S S
CP_T0-T8 (MSMC) CP_T ( 23) SRIO TAC BCP CFG NetCP
CPU/3
XGE CFG TCP3d_0 TCP3d_1 VCP2_0 VCP2_1 VCP2_2 VCP2_3 FFTC_0 FFTC_1 FFTC_2 FFTC_3 Bridge 20
TeraNet 3P_B
TNet_3P_F CPU/3
TNet_3P_E CPU/3
TNet_3P_G CPU/3
MPU_11
6636
To TeraNet_6P_B
System Interconnect
199
PRODUCT PREVIEW
AIF2

SPRS835DAugust 2013 Figure 6-7 TeraNet 6P_B
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Bridge 20 From TeraNet_3P_B
S S S S S
Timer ( 20) USIM OTP Debug SS PLL_CTL GPSC BOOT_CFG UART ( 2) I C ( 3)

2
CPU/6
S S S S S S S S S S S S S S S S S S
TeraNet 6P_B
PRODUCT PREVIEW
6636
GPIO
AIF2 B4 SerDes CFG AIF2 B8 SerDes CFG USB PHY CFG PCIe SerDes CFG HyperLink SerDes CFG SRIO SerDes CFG XGE SerDes CFG NetCP SerDes CFG DDR3B PHY CFG DDR3A PHY CFG USB MMR CFG SmartReflex0 SmartReflex1
200
System Interconnect

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SPRS835DAugust 2013 TeraNet 3P_Tracer
Figure 6-8
Tracer_MSMC_1 Tracer_MSMC_2 Tracer_MSMC_3 Tracer_MSMC_4 Tracer_MSMC_5 Tracer_MSMC_6 Tracer_MSMC_7 Tracer_MSMC_8
M M M M M M M M
TeraNet 3P_P CPU/3
Tracer_MSMC_0
6636
Tracer_SM Tracer_CIC Tracer_DDRB Tracer_QM_CFG1 Tracer_QM_CFG2 Tracer_QM_M Tracer_L2_0-7 ( 8) Tracer_BCR_CFG Tracer_TAC Tracer_CFG Tracer_RAC
M M M M M M M M M M M M M M M
TeraNet 3P_Tracer CPU/3
From TeraNet_3P_A
Debug_SS STM
Tracer_RAC_CFG_1 Tracer_RAC_CFG_2 Tracer_EDMA3CC0_4 Tracer_EDMA3CC1_2_3 Tracer_SPI_ ROM_EMIF16
System Interconnect
201
PRODUCT PREVIEW

SPRS835DAugust 2013
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The following tables list the master and slave end point connections. Intersecting cells may contain one of the following: Y There is a connection between this master and that slave. - There is NO connection between this master and that slave. n A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 6-3 Configuration Space Interconnect - Section 1 (Part 1 of 2)
Slaves CPT_SPI_ROM_EMIF16_CFG
AIF2_SERDES_B4_CFG
AIF2_SERDES_B8_CFG
Masters 10GbE AIF2 BCP Packet DMA BCP_DIO(0-1) CorePac0_CFG CorePac1_CFG CorePac2_CFG CorePac3_CFG CorePac4_CFG CorePac5_CFG CorePac6_CFG CorePac7_CFG DBG_DAP EDMA0_CC_TR EDMA0_TC0_RD EDMA0_TC0_WR EDMA0_TC1_RD EDMA0_TC1_WR EDMA1_CC_TR EDMA1_TC0_RD EDMA1_TC0_WR EDMA1_TC1_RD EDMA1_TC1_WR EDMA1_TC2_RD EDMA1_TC2_WR EDMA1_TC3_RD EDMA1_TC3_WR EDMA2_CC_TR EDMA2_TC0_RD EDMA2_TC0_WR
12 12 12 12 12 12 12 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
202
System Interconnect
CPT_TPCC1_2_3_CFG
CPT_MSMC(0-7)_CFG
CPT_RAC_CFG1_CFG
CPT_RAC_CFG2_CFG
10GbE_SERDES_CFG
CPT_QM_CFG1_CFG
CPT_QM_CFG2_CFG
CPT_INTC(0-2)_CFG
CPT_BCR_CFG_CFG
CPT_TPCC0_4_CFG
CPT_RAC_FEI_CFG
CPT_L2_(0-7)_CFG
CPT_TAC_BE_CFG
CPT_DDR3A_CFG
CPT_DDR3B_CFG
CPT_QM_M_CFG
ADTF(0-7)_CFG
BOOTCFG_CFG
PRODUCT PREVIEW
CPT_CFG_CFG
CP_INTC_CFG
CPT_SM_CFG
10GbE_CFG
ARM_CFG
AIF2_CFG
BCR_CFG
BCP_CFG

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SPRS835DAugust 2013 Configuration Space Interconnect - Section 1 (Part 2 of 2)

Slaves CPT_SPI_ROM_EMIF16_CFG
Table 6-3
AIF2_SERDES_B4_CFG
AIF2_SERDES_B8_CFG
Masters EDMA2_TC1_RD EDMA2_TC1_WR EDMA2_TC2_RD EDMA2_TC2_WR EDMA2_TC3_RD EDMA2_TC3_WR EDMA3_CC_TR EDMA3_TC0_RD EDMA3_TC0_WR EDMA3_TC1_RD EDMA3_TC1_WR EDMA4_CC_TR EDMA4_TC0_RD EDMA4_TC0_WR EDMA4_TC1_RD EDMA4_TC1_WR FFTC_0 FFTC_1 FFTC_2 FFTC_3
CPT_TPCC1_2_3_CFG Y -
CPT_MSMC(0-7)_CFG
CPT_RAC_CFG1_CFG
CPT_RAC_CFG2_CFG
10GbE_SERDES_CFG
CPT_QM_CFG1_CFG
CPT_QM_CFG2_CFG
CPT_INTC(0-2)_CFG
CPT_BCR_CFG_CFG
CPT_TPCC0_4_CFG
CPT_RAC_FEI_CFG
CPT_L2_(0-7)_CFG
CPT_TAC_BE_CFG
CPT_DDR3A_CFG
CPT_DDR3B_CFG
CPT_QM_M_CFG
ADTF(0-7)_CFG
BOOTCFG_CFG
CPT_CFG_CFG
CP_INTC_CFG
CPT_SM_CFG
10GbE_CFG
ARM_CFG
AIF2_CFG
BCR_CFG
BCP_CFG
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 -
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
HyperLink0_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 HyperLink1_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 MSMC_SYS NETCP PCIE QM_Master1 QM_Master2 QM_SEC RAC_(0-1)_BE0 RAC_(0-1)_BE1 SRIO SRIO Packet DMA TAC_FEI_(0-2) USB End of Table 6-3 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 -
12 -
12 -
14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 -
System Interconnect
203
PRODUCT PREVIEW

SPRS835DAugust 2013 Table 6-4 Configuration Space Interconnect -Section 2 (Part 1 of 2)
Slaves HYPERLINK0_SERDES_CFG HYPERLINK1_SERDES_CFG
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EDMA0_TC(0-1)_CFG
EDMA1_TC(0-3)_CFG
EDMA2_TC(0-3)_CFG
EDMA3_TC(0-1)_CFG
EDMA4_TC(0-1)_CFG
NETCP_SERDES_CFG
PCIE_SERDES_CFG
DDR3A_PHY_CFG
DDR3B_PHY_CFG
EDMA0_CC_CFG
EDMA1_CC_CFG
EDMA2_CC_CFG
EDMA3_CC_CFG
EDMA4_CC_CFG
FFTC_(0-3)_CFG
MPU(0-14)_CFG
DBG_TBR_SYS
PLL_CTL_CFG
I2C(0-2)_CFG
NETCP_CFG
GPIO_CFG
Masters 10GbE AIF2
BCP Packet DMA BCP_DIO(0-1) CorePac0_CFG CorePac1_CFG CorePac2_CFG CorePac3_CFG CorePac4_CFG CorePac5_CFG CorePac6_CFG CorePac7_CFG DBG_DAP EDMA0_CC_TR EDMA0_TC0_RD EDMA0_TC0_WR EDMA0_TC1_RD EDMA0_TC1_WR EDMA1_CC_TR EDMA1_TC0_RD EDMA1_TC0_WR EDMA1_TC1_RD EDMA1_TC1_WR EDMA1_TC2_RD EDMA1_TC2_WR EDMA1_TC3_RD EDMA1_TC3_WR EDMA2_CC_TR EDMA2_TC0_RD EDMA2_TC0_WR EDMA2_TC1_RD EDMA2_TC1_WR EDMA2_TC2_RD EDMA2_TC2_WR EDMA2_TC3_RD EDMA2_TC3_WR
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
12 12 12 12 12 12 12 12 12 12 12 12 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -
12 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y -
12 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 -
204
System Interconnect
QM_CFG1
DBG_CFG
OTP_CFG
PSC_CFG
GIC_CFG
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SPRS835DAugust 2013 Configuration Space Interconnect -Section 2 (Part 2 of 2)

Slaves HYPERLINK0_SERDES_CFG HYPERLINK1_SERDES_CFG
Table 6-4
EDMA0_TC(0-1)_CFG
EDMA1_TC(0-3)_CFG
EDMA2_TC(0-3)_CFG
EDMA3_TC(0-1)_CFG
EDMA4_TC(0-1)_CFG
NETCP_SERDES_CFG
PCIE_SERDES_CFG
DDR3A_PHY_CFG
DDR3B_PHY_CFG
EDMA0_CC_CFG
EDMA1_CC_CFG
EDMA2_CC_CFG
EDMA3_CC_CFG
EDMA4_CC_CFG
FFTC_(0-3)_CFG
MPU(0-14)_CFG
DBG_TBR_SYS
PLL_CTL_CFG
I2C(0-2)_CFG
NETCP_CFG
GPIO_CFG
Masters EDMA3_CC_TR EDMA3_TC0_RD EDMA3_TC0_WR EDMA3_TC1_RD EDMA3_TC1_WR EDMA4_CC_TR EDMA4_TC0_RD EDMA4_TC0_WR EDMA4_TC1_RD EDMA4_TC1_WR FFTC_0 FFTC_1 FFTC_2 FFTC_3 HyperLink0_Master HyperLink1_Master MSMC_SYS NETCP PCIE QM_Master1 QM_Master2 QM_SEC RAC_(0-1)_BE0 RAC_(0-1)_BE1 SRIO SRIO Packet DMA TAC_FEI_(0-2) USB End of Table 6-4
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
14 -
14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 -
12 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 -
12 -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y Y 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y Y Y Y Y Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Y Y Y Y Y Y Y Y Y Y Y Y -
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 -
12 12 12 12 12 12 12 12 12 12 12 12 -
12 -
14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 -
14 14 14 14 14 14 14 14 14 14 14 14 -
12 -
System Interconnect
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PRODUCT PREVIEW
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
QM_CFG1
DBG_CFG
OTP_CFG
PSC_CFG
GIC_CFG

SPRS835DAugust 2013 Table 6-5 Configuration Space Interconnect - Section 3 (Part 1 of 2)
Slaves SRIO_SERDES_CFG TCP3D_(0-1)_CFG TIMER(0-19)_CFG VCP2_(0-3)_CFG 12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13 USB_MMR_CFG UART(0-1)_CFG RAC_(0-1)_CFG SEC_MGR_CFG TBR_SYS_ARM USB_PHY_CFG 12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
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SR_CFG(0-1)
TETB0_CFG
TETB1_CFG
TETB2_CFG
TETB3_CFG
TETB4_CFG
TETB5_CFG
TETB6_CFG
TETB7_CFG
Masters 10GbE AIF2 BCP Packet DMA BCP_DIO(0-1)
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y -
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 13 13 13
12 Y Y Y Y Y Y Y Y Y 13 13 13
12 Y Y Y Y Y Y Y Y Y 14 14 13
12 Y Y Y Y Y Y Y Y Y 14 14 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 Y 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 Y 12 13
12 Y Y Y Y Y Y Y Y Y 13 13 13
12 Y Y Y Y Y Y Y Y Y 14 14 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
12 Y Y Y Y Y Y Y Y Y 12 12 12 12 12 12 12 12 13
CorePac0_CFG CorePac1_CFG CorePac2_CFG CorePac3_CFG CorePac4_CFG CorePac5_CFG CorePac6_CFG CorePac7_CFG DBG_DAP EDMA0_CC_TR EDMA0_TC0_RD EDMA0_TC0_WR EDMA0_TC1_RD EDMA0_TC1_WR EDMA1_CC_TR EDMA1_TC0_RD EDMA1_TC0_WR EDMA1_TC1_RD EDMA1_TC1_WR EDMA1_TC2_RD EDMA1_TC2_WR EDMA1_TC3_RD EDMA1_TC3_WR EDMA2_CC_TR EDMA2_TC0_RD EDMA2_TC0_WR EDMA2_TC1_RD EDMA2_TC1_WR EDMA2_TC2_RD EDMA2_TC2_WR EDMA2_TC3_RD EDMA2_TC3_WR EDMA3_CC_TR EDMA3_TC0_RD
206
System Interconnect
USIM_CFG
SRIO_CFG
QM_CFG2
TAC_CFG
SM_CFG
PRODUCT PREVIEW

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SPRS835DAugust 2013 Configuration Space Interconnect - Section 3 (Part 2 of 2)

Slaves SRIO_SERDES_CFG TCP3D_(0-1)_CFG TIMER(0-19)_CFG VCP2_(0-3)_CFG 13 12 12 12 12 12 12 Y 12 14 USB_MMR_CFG UART(0-1)_CFG RAC_(0-1)_CFG SEC_MGR_CFG TBR_SYS_ARM USB_PHY_CFG 13 12 12 12 12 12 12 Y 12 14 -
Table 6-5
SR_CFG(0-1)
TETB0_CFG
TETB1_CFG
TETB2_CFG
TETB3_CFG
TETB4_CFG
TETB5_CFG
TETB6_CFG
TETB7_CFG
Masters EDMA3_TC0_WR EDMA3_TC1_RD EDMA3_TC1_WR EDMA4_CC_TR EDMA4_TC0_RD EDMA4_TC0_WR EDMA4_TC1_RD EDMA4_TC1_WR FFTC_0 FFTC_1 FFTC_2 FFTC_3 HyperLink0_Master HyperLink1_Master MSMC_SYS NETCP PCIE QM_Master1 QM_Master2 QM_SEC RAC_(0-1)_BE0 RAC_(0-1)_BE1 SRIO SRIO Packet DMA TAC_FEI_(0-2) USB End of Table 6-5
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 12 12 12 12 Y 12 12 14 12
13 12 12 12 12 12 12 Y 12 14 -
14 12 12 12 12 Y 12 14 12
14 12 12 12 12 Y 12 14 12
14 12 12 12 12 Y 12 14 12
14 12 12 12 12 Y 12 14 12
14 12 12 12 12 12 12 Y 12 14 12
14 12 12 12 12 12 12 Y 12 14 12
14 12 12 12 12 Y 12 14 12
14 12 12 12 12 Y 12 14 12
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
13 12 12 12 12 12 12 Y 12 12 14 -
13 12 12 12 12 12 12 Y 12 14 -
USIM_CFG
SRIO_CFG
QM_CFG2
TAC_CFG
SM_CFG
System Interconnect
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6.4 Bus Priorities

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User-programmable priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means higher priority PRI = 000b = urgent, PRI = 111b = low. All other masters provide their priority directly and do not need a default priority setting. Examples include the C66x CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA-based peripherals also have internal registers to define the priority level of their initiated transactions. The Packet DMA secondary port is one master port that does not have priority allocation register inside the Multicore Navigator. The priority level for transactiosn from this master port is described by the PKTDMA_PRI_ALLOC register shown in Figure 6-9 and Table 6-6.
Figure 6-9
31 Reserved R/W-00000000000000000000001000011 Legend: R= Read only; R/W = Read/Write; -n = value after reset
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)

3 2 0
PRODUCT PREVIEW
PKTDMA_PRI RW-000
Table 6-6
Bit 31-3 2-0 Field
Packed DMA Priority Allocation Register Field Descriptions

Description Reserved. Controls the priority level for the transactions from the packet DMA master port, which accesses the external linking RAM.
Reserved PKDTDMA_PRI
End of Table 6-6
For all other modules, see the respective User Guides in 1.10 Related Documentation from Texas Instruments on page 21 for programmable priority registers.
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System Interconnect

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SPRS835DAugust 2013
7 Device Boot and Configuration

7.1 Device Boot
7.1.1 Boot Sequence The boot sequence is a process by which the internal memory is loaded with program and data sections. The boot sequence is started automatically after each power-on reset or warm reset. The TCI6636K2H supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[15:0] device configuration inputs to determine the software configuration that must be completed. For more details on boot sequence see the Bootloader User Guide in 1.10 Related Documentation from Texas Instruments on page 21. For TCI6636K2H nonsecure devices, there are two types of booting: the C66x CorePac as the boot master and the ARM CorePac as the boot master. For secure devices, the C66x CorePac is always the secure master and the C66x CorePac0 or ARM CorePac Core0 can be the boot master. The ARM CorePac does not support no-boot mode. Both the C66x CorePacs and the ARM CorePac need to read the bootmode register to determine how to proceed with the boot. Table 7-1 shows memory space reserved for boot by the C66x CorePac.
Table 7-1 C66x DSP Boot RAM Memory Map
Size 0x1_0000 0x80 0x7f00 4 4 0x410 0x4000 0x90 0x20 0xf0 0x13fc 0x404 0x180 0x60 0x80 0x4 0x4 Description Reserved GEM ROM version string Boot Master Table overlayed with scratch Boot Master Table Valid Length Field Host Data Address (boot magic address for secure boot through master peripherals) Secure host Data structure Boot Stack Boot Log Data Boot Status Stack Boot Stats Boot Data Boot Trace Info DDR Config Boot RAM call table Boot Parameter table Secure Signal Magic address Boot Magic address 0x80_0000 0x8e_7f80 0x8e_8000 0x8e_767c 0x8e_fff0 0x8f_7800 0x8f_a290 0x8f_e290 0x8f_e320 0x8f_e410 0x8f_e520 0x8f_f91c 0x8f_fd20 0x8f_fea0 0x8f_ff00 0x8f_fff8 0x8f_fffc End of Table 7-1 Start Address
Table 7-2 shows addresses reserved for boot by the ARM CorePac.
Table 7-2 ARM Boot RAM Memory Map (Part 1 of 3)
Size 0xc00 0x80 0x5000 Context RAM not scrubbed on secure boot Global level 0 non-secure translation table Global non-secure page table for memory covering ROM Description Start Address 0xc57_e000 0xc58_6f80 0xc58_7000
Device Boot and Configuration
209
PRODUCT PREVIEW

SPRS835DAugust 2013 Table 7-2 ARM Boot RAM Memory Map (Part 2 of 3)
Size 0x1000 0x1000 0x1000 0x1000 0x7f00 4 0x200 0x3000 0x3000 4 4 4 4 0x400 0x400 0x400 0x400 0x400 0x400 0x400 0x400 0x180 0x80 0x100 0x100 0x100 0x100 0x19e0 0x1010 0x180 0x80 0x100 0x100 0x100 0x100 0x19e0 0x1010 0x180 0x80 0x100 0x100 0x100 0x100 0x19e0 Core 0 non-secure level 1 translation table Core 1 non-secure level 1 translation table Core 2 non-secure level 1 translation table Core 3 non-secure level 1 translation table Packet memory buffer Host Data Address (boot magic address for secure boot through master peripherals) DDR3a configuration structure Boot Data Supervisor stack, each core gets 0xc00 bytes Arm boot magic address, core 0 Arm boot magic address, core 1 Arm boot magic address, core 2 Arm boot magic address, core 3 Abort stack, core 0 Abort stack, core 1 Abort stack, core 2 Abort stack, core 3 Unknown mode stack, core 0 Unknown mode stack, core 1 Unknown mode stack, core 2 Unknown mode stack, core 3 Boot Version string, core 0 Boot status stack, core 0 Boot stats, core 0 Boot log, core 0 Boot RAM call table, core 0 Boot parameter tables, core 0 Boot Data, core 0 Boot Trace, core 0 Boot Version string, core 1 Boot status stack, core 1 Boot stats, core 1 Boot log, core 1 Boot RAM call table, core 1 Boot parameter tables, core 1 Boot Data, core 1 Boot Trace, core 1 Boot Version string, core 2 Boot status stack, core 2 Boot stats, core 2 Boot log, core 2 Boot RAM call table, core 2 Boot parameter tables, core 2 Boot Data, core 2 Description
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Start Address 0xc58_c000 0xc58_d000 0xc58_e000 0xc58_f000 0xc59_0000 0xc59_7f00 0xc5a_6e00 0xc5a_7000 0xc5a_a000 0xc5a_d000 0xc5a_d004 0xc5a_d008 0xc5a_d00c 0xc5a_e000 0xc5a_e400 0xc5a_e800 0xc5a_ec00 0xc5a_f000 0xc5a_f400 0xc5a_f800 0xc5a_fc00 0xc5b_0000 0xc5b_0180 0xc5b_0200 0xc5b_0300 0x5b_0400 0xc5b_0500 0xc5b_0600 0xc5b_1fe0 0xc5b_4000 0xc5b_4180 0xc5b_4200 0xc5b_4300 0x5b_4400 0xc5b_4500 0xc5b_4600 0xc5b_5fe0 0xc5b_8000 0xc5b_8180 0xc5b_8200 0xc5b_8300 0x5b_8400 0xc5b_8500 0xc5b_8600
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SPRS835DAugust 2013 ARM Boot RAM Memory Map (Part 3 of 3)

Size 0x1010 0x180 0x80 0x100 0x100 0x100 0x100 0x19e0 0x1010 0x4_0000 Boot Trace, core 2 Boot Version string, core 3 Boot status stack, core 3 Boot stats, core 3 Boot log, core 3 Boot RAM call table, core 3 Boot parameter tables, core 3 Boot Data, core 3 Boot Trace, core 3 Description
Table 7-2
Start Address 0xc5b_9fe0 0xc5b_c000 0xc5b_c180 0xc5b_c200 0xc5b_c300 0x5b_c400 0xc5b_c500 0xc5b_c600 0xc5b_dfe0 0xc5c_0000 End of Table 7-2
7.1.2 Boot Modes Supported The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are four possible boot modes: Public ROM Boot when the C6xx CorePac0 is the boot master The C66x CorePac is released from reset and begins executing from the L3 ROM base address. The ARM CorePac is also released from reset at the same time as the C66xCorePac. Both the C66x CorePac and the ARM CorePac read the bootmode register inside the bootCFG module to determine which is the boot master. After the Boot ROM for the Cortex-A15 processor reads the bootmode to determine that the C66x CorePac is the boot master, all Cortex-A15 processors stay idle by executing WFI instruction and waiting for the C66x CorePacs interrupt. The chip Boot ROM reads the bootmode register to determine that the C66x CorePac0 is the boot master, then the C66x CorePac0 performs the boot process and the other C66x CorePacs execute an IDLE instruction. After the boot process is completed, the C66x CorePac0 begins to execute the code downloaded during the boot process. If the downloaded code included code for the other C66x cores and/or the Cortex-A15 processor cores, the downloaded code may contain logic to write the code execution addresses to the boot address register for the core that is to execute it. The C66x CorePac0 can then generate an interrupt to the core causing it to execute the code. When they receive the IPC interrupt, the rest of the C66x CorePacs and the ARM CorePac complete boot management operations and begin executing from the predefined location in memory. Public ROM Boot when the ARM CorePac Core0 is the boot master The only difference between this boot mode and and when the C66x CorePac is the boot master, is that the ARM CorePac performs the boot process while the C66x CorePacs execute idle instructions. When the ARM CorePac Core0 finishes the boot process, it may send interrupts to the C66x CorePacs and Cortex-A15 processor cores through IPC registers. The C66x CorePacs complete the boot management operations and begin executing from the predefined locations. Secure ROM Boot when the C66x CorePac0 is the boot master The C66x CorePac0 and the ARM CorePac Core0 are released from reset simultaneously and the C66x CorePac0 begins executing from secure ROM. The C66x CorePac0 performs the boot process includingany authentication and decryption required on the bootloaded image for the C66x CorePacs and for the ARM CorePac prior to beginning execution. Secure ROM Boot when the ARM CorePac0 is the boot master The C66x CorePac0 and the ARM CorePac Core0 are released from reset simultaneously and begin executing from secure ROM. The ARM CorePac Core0 initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the bootloaded image for the C66x CorePacs and ARM CorePac prior to beginning execution.
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The boot process performed by the C66x CorePac0 and the ARM CorePac Core0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[15:0] value in the DEVSTAT register. The C66x CorePac0 and the ARM CorePac Core0 read this value, and then execute the associated boot process in software. Bit 8 determines whether the boot is C66x CorePac boot or ARM CorePac boot. The figure below shows the bits associated with BOOTMODE[15:0] (DEVSTAT[16:1]) when the C66x CorePac or ARM CorePac is the boot master. Note that Figure 7-1 does not include bit 0 of the DEVSTAT contents. Bit 0 is used to select overall system endianess that is independent of the boot mode. The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error occurs. The PLL settings are shown at the end of this section, and the PLL set-up details can be found in Section 9.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers on page 286.
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NoteIt is important to keep in mind that BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits of the
DEVSTAT register.
Figure 7-1
16 X 15 X
DEVSTAT Boot Mode Pins ROM Mapping

DEVSTAT Boot Mode Pins ROM Mapping 14 0 1 X Csel 13 ARMEN Port Bus Addr Mode Wait Width 12 SYSEN 11 10 9 8 7 6 5 4 3 0 Min Port 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 1 0
2
Mode SLEEP I C SLAVE I2C MASTER SPI EMIF (ARM Master) EMIF (DSP Master) NAND (ARM Master) NAND (DSP Master)
SlaveAddr X Width 0 X
ARM PLL CONFIG
SYS PLL CONFIG X Npin
Param ldx ARM PLL CONFIG X Chip Sel
Base Addr
1 Lane X PA clk
First Block
Clear
ARM PLL CONFIG X Chip Sel Boot Master Min
Ref Clock
Data Rate
ARM PLL CONFIG Lane Setup ARM PLL CONFIG Rsvd Lane Setup
SRIO (ARM Master) SRIO (DSP Master) Ethernet (ARM Master) Ethernet (DSP Master) PCIe (ARM Master) PCIe (DSP Master) HyperLink (ARM Master) HyperLink (DSP Master) UART (ARM Master) UART (DSP Master)
Ref clk
Ext Con
SYS PLL CONFIG
Ref clk
Bar Config
ARM PLL CONFIG SerDes Cfg ARM PLL CONFIG SerDes Cfg ARM PLL CONFIG X X X
Port X X
Ref clk X X X X
Data Rate X X
Port
Min
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7.1.2.1 Boot Device Field
The Boot Device field BOOTMODE[16-14-4-3-2-1] and the Boot Device field BOOTMODE[8] define the boot device and the boot master that is chosen. The following table shows the supported boot modes.
Table 7-3
Bit 16, 14, 4, 3, 2, 1
Boot Mode Pins: Boot Device Values

Field Boot Device Description Device boot mode ARM is a boot master when BOOTMODE[8]=0 Sleep = X0[Min]000b 2 I C Slave = [Slave Addr1]1[Min]000b 2 I C Master = X1[Min]001b SPI = [Width][Csel0][Min]010b EMIF = 0[BaseAddr0][Min]011b NAND = 1[BaseAddr0][Min]011b Serial Rapid I/O = [Lane][Ref Clock0][Min]100b Ethernet (SGMII) = [Pa clk][Ref Clk0][Min]101b PCI = [Ref clk][Bar Config2]0110b HyperLink = [Port][Ref Clk0]1110b UART = XX[Min]111b C66x is a boot master when BOOTMODE[8]=1 Sleep = X0[Min]000b 2 I C Slave = [Slave Addr1]1[Min]000b 2 I C Master = X1[Min]001b SPI = [Width][Csel0][Min]010b EMIF = 0[BaseAddr0][Min]011b NAND = 1[BaseAddr0][Min]011b Serial Rapid I/O = [Lane][Ref Clock0][Min]100b Ethernet (SGMII) = [Pa clk][Ref Clk0][Min]101b PCI = [Ref clk][Bar Config2]0110b HyperLink = [Port][Ref Clk0]1110b UART = XX[Min]111b
End of Table 7-3
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7.1.2.2 Device Configuration Field
The device configuration fieldsDEVSTAT[16:1] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode.
7.1.2.2.1 Sleep Boot Mode Configuration Figure 7-2
16 X 15 X
Sleep Boot Mode Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 0 13 12 11 10 ARM PLL Cfg 9 8 Boot Master 7 6 Sys PLL Config 5 4 Min 3 2 000 1 0 Lendian
ARMen SYSEN
Table 7-4
Sleep Boot Configuration Field Descriptions

Description Reserved Boot Device- used in conjunction with Boot Devices [Used in conjunction with bits 3-1] 0 = Sleep (default) Others = Other boot modes Enable the ARM PLL 0 = PLL disabled 1 = PLL enabled Enable the System PLL 0 = PLL disabled (default) 1 = PLL enabled
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Bit 16-15 14
Field Reserved Boot Devices
13
ARMen
12
SYSEN
11-9 8
ARM PLL Setting The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Boot Master Boot Master select 0 = ARM is boot master 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
7-5 4
SYS PLL Setting Min
3-1
Boot Devices
Boot Devices[3:1] used in conjunction with Boot Device [14] 000 = Sleep Others = Other boot modes Endianess (device) 0 = Big endian 1 = Little endian
Lendian
End of Table 7-4
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2
7.1.2.2.2 I C Boot Device Configuration I2C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
Figure 7-3
16 15
I2C Passive Mode Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 1 13 Port 12 11 10 ARM PLL Cfg 9 8 Boot Master 7 6 Sys PLL Config 5 4 Min 3 2 000 1 0 Lendian
Slave Addr
Table 7-5
Bit 16-15 Field
I2C Passive Mode Device Configuration Field Descriptions

Description I2C Slave boot bus address 2 0 = I C slave boot bus address is 0x00 1 = I2C slave boot bus address is 0x10 (default) 2 2 = I C slave boot bus address is 0x20 2 3 = I C slave boot bus address is 0x30 Boot Device[14] used in conjunction with Boot Devices [Use din conjunction with bits 3-1] 0 = Other boot modes 1= I2C Slave boot mode I C port number 2 0 = I C0 2 1 = I C1 2 = I2C2 3 = Reserved
2
Slave Addr
14
Boot Devices
13-12
Port
11-9 8
ARM PLL Setting The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Boot Master Boot Master select 0 = ARM is boot master 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
7-5 4
SYS PLL Setting Min
3-1
Boot Devices
Boot Devices[3:1] used in conjunction with Boot Device [14] 000 = I2C Slave Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-5
215
PRODUCT PREVIEW

SPRS835DAugust 2013
2 I C Master Mode
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In master mode, the I C device configuration uses ten bits of device configuration instead of seven as used in other 2 boot modes. In this mode, the device makes the initial read of the I C EEPROM while the PLL is in bypass mode. The initial read contains the desired clock multiplier, which must be set up prior to any subsequent reads.
Figure 7-4
16 15 Reserved 14
2 I C Master Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping 13 12 11 10 9 8 Boot Master 7 Reserved 6 5 4 Min 3 2 001 1 0 Lendian
Bus Addr
Param ldx/Offset
Port
Table 7-6
Bit 16-14 Field
I2C Master Mode Device Configuration Field Descriptions

Description Reserved I C bus address slave device 2 0 = I C slave boot bus address is 0x50 (default) 2 1 = I C slave boot bus address is 0x51 2 = I2C slave boot bus address is 0x52 2 3 = I C slave boot bus address is 0x53 This value specifies the parameter table index when the C66x is the boot master This value specifies the start read address at 8K times this value when the ARM is the boot master
2
Reserved Bus Addr
PRODUCT PREVIEW
13-12
11-9
Param Idx/Offset Parameter Table Index: 0-7
Boot Master
Boot Master select 0 = ARM is boot master 1 = C66x is boot master Reserved I C port number 0 = I2C0 (default) 2 1 = I C1 2 2 = I C2 3 = Reserved Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
2
7 6-5
Reserved Port
Min
3-1
Boot Devices
Boot Devices[3:1] 2 001 = I C Master Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-6
7.1.2.2.3 SPI Boot Device Configuration Figure 7-5

16 Width 15 Csel
SPI Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 13 12 11 10 9 8 Boot Master 7 Npin 6 5 4 Min 3 2 010 1 0 Lendian
Mode
Param ldx/Offset
Port
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SPRS835DAugust 2013 SPI Device Configuration Field Descriptions

Field Width Description SPI address width configuration 0 = 16-bit address values are used 1 = 24-bit address values are used (default) The chip select field value 0-3(default = 0) Clk Polarity/ Phase 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge. 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK. 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge (default). 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK. This value specifies the parameter table index when the C66x is the boot master This value specifies the start read address at 8K times this value when the ARM is the boot master
Table 7-7
Bit 16
15-14 13-12
Csel Mode
Boot Master
Boot Master select 0 = ARM is boot master (default) 1 = C66x is boot master Selected Chip Select driven 0 = CS0 to the selected chip select is driven 1 = CS0-CS4 to the selected chip select are driven (default) Specify SPI port 0 = SPI0 used (default) 1 = SPI1 used 2 = SPI2 used 3 = Reserved Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
Npin
6-5
Port
Min
3-1
Boot Devices
Boot Devices[3:1] 010 = SPI boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-7
7.1.2.2.4 EMIF Boot Device Configuration Figure 7-6

16 0 0 15
EMIF Boot Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 13 Wait Wait 12 Width Width 11 X 10 9 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Cfg Sys PLL Cfg 5 4 0 0 3 2 011 011 1 0 Lendian Lendian
Base Addr Base Addr
Chip Sel ARM PLL Cfg
217
PRODUCT PREVIEW
11-9
Param Idx/Offset
Parameter Table Index: 0-7

Bit 16 Field Boot Devices
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EMIF Boot Device Configuration Field Descriptions

Description Boot Devices[16] used conjunction with Boot Devices[4] and Boot Devices [Used in conjunction with bits 3-1] 0 = EMIF boot mode 1 = Other boot modes Base address (0-3) used to calculate the branch address. Branch address is the chip select plus Base Address *16MB Extended Wait 0 = Extended Wait disabled 1 = Extended Wait enabled EMIF Width 0 = 8-bit EMIF Width 1 = 16-bit EMIF Width When Boot Master = 0 (ARM is Boot Master), Pin[11:9] used as ARM PLL Setting and the chip select region CS2 is used. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), Pin[10:9] used as Chip Sel that specifies the chip select region, CS2-CS5. 00 = CS2 01 = CS3 10 = CS4 11 = CS5
15-14 13
Base Addr Wait
12
Width
PRODUCT PREVIEW
11-9
Chip Sel/ARM PLL Setting
Boot Master
Boot Master select 0 = ARM is boot master 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Boot Devices[4] used conjunction with Boot Devices[16] and Boot Devices [Use din conjunction with bits 3-1] 0 = EMIF boot mode 1 = Other boot modes Boot Devices[3:1] used in conjunction with Boot Device [4] 011 = EMIF boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
7-5 4
SYS PLL Setting Boot Devices
3-1
Boot Devices
Lendian
End of Table 7-8
7.1.2.2.5 NAND Boot Device Configuration Figure 7-7

16 1 1 15
NAND Boot Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 First Block First Block 13 12 Clear Clear 11 X 10 Chip Sel ARM PLL Cfg 9 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Cfg Sys PLL Cfg 5 4 Min Min 3 2 011 011 1 0 Lendian Lendian
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Table 7-9
Bit 16 Field
NAND Boot Device Configuration Field Descriptions

Description Boot Devices[16] used conjunction with Boot Devices [3-1] 0 = Other boot modes 1 = NAND boot mode First Block. This value is used to calculate the first block read. The first block read is the first block value *16. ClearNAND 0 = Device is not a ClearNAND (default) 1 = Device is a ClearNAND When Boot Master = 0 (ARM is Boot Master), Pin[11:9] used as ARM PLL Setting and the chip select region CS2 is used. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Boot Devices
15-13 12
First Block Clear
11-9
Chip Sel/ARM PLL Setting
Boot Master
Boot Master select 0 = ARM is boot master (default) 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that would normally be set by the other BOOTMODE pins when Min is 0. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. Boot Devices 011 = NAND boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
7-5 4
SYS PLL Setting Min
3-1
Boot Devices
Lendian
End of Table 7-9
7.1.2.2.6 Serial Rapid I/O Boot Device Configuration
The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
Figure 7-8
16 X Lane 15
Serial Rapid I/O Boot Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 13 12 11 10 Lane Setup ARM PLL Cfg 9 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Cfg Sys PLL Cfg 5 4 Min Min 3 2 100 100 1 0 Lendian Lendian
Ref Clock Ref Clock
Data Rate Data Rate
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PRODUCT PREVIEW
When Boot Master =1 (C66x is Boot Master), Pin[10:9] used as Chip Sel that specifies the chip select region, CS2-CS5. 00 = CS2 01 = CS3 10 = CS4 11 = CS5

Bit 16 Field Lane
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Serial Rapid I/O Boot Device Configuration Field Descriptions

Description When Boot Master =0 (ARM is Boot Master), Pin[16] is used as Lane. 0 = 4 ports, each 1 lane wide (default) 1 = 2 ports, each 2lanes wide When Boot Master =1 (C66x is Boot Master), Pin[16] is reserved. SRIO Reference clock frequency 0 = 125MHz 1 = 156.25MHz (default) 2 = Reserved 3 = Reserved SRIO Data Rate 0 = 1.25 GBs 1 = 2.5 GBs 2 = 3.125 GBs 3 = 5 GBs (default) When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting with all lanes enabled. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. The default value is 156.26 Mhz. Table 7-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [11:9] are used as Lane Set up. 0 = 4 ports, each 1 lane wide (default) 1 = 3 ports, lanes 0, 1 form a 2 lane port, lane 2,3 are single ports 2 = 3 ports, lanes 0, 1 are single lane ports, lanes 2,3 form a 2 lane port 3 = 2 ports, lane 0, 1 are one port, lane 2, 3 are a second port 4 = 1 port, 4 lanes wide 5 - 7 = 4 ports, each 1 lane wide
15-14
Ref Clock
13-12
Data Rate
PRODUCT PREVIEW
11-9
Lane Setup/ARM PLL Setting
Boot Master
Boot Master select 0 = ARM is boot master (default) 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 7-27 shows settings for various input clock frequencies. (default = 4) Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
7-5
SYS PLL Setting
Min
3-1
Boot Devices
Boot Devices 100 = SRIO boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-10
In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.
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7.1.2.3 Ethernet (SGMII) Boot Device Configuration

Figure 7-9
16 Pa clk Pa clk 15
Ethernet (SGMII) Boot Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 13 12 11 10 Lane Setup ARM PLL Cfg 9 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Cfg Sys PLL Cfg 5 4 Min Min 3 2 101 101 1 0 Lendian Lendian
Ref Clock Ref Clock
Ext Con Ext Con
Table 7-11
Bit 16 Field Pa clk
Ethernet (SGMII) Boot Device Configuration Field Descriptions

Description PA clock reference 0 = PA clocked at the same reference as the core reference 1 = PA clocked at the same reference as the SerDes reference (default) SRIO Reference clock frequency 0 = 125MHz 1 = 156.25MHz (default) 2 = Reserved 3 = Reserved External connection mode 0 = MAC to MAC connection, master with auto negotiation 1 = MAC to MAC connection, slave with auto negotiation (default) 2 = MAC to MAC, forced link, maximum speed 3 = MAC to fiber connection When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [10:9] are used as Lane Set up. 0 = All SGMII ports enabled (default) 1 = Only SGMII port 0 enabled 2 = SGMII port 0 and 1 enabled 3 = SGMII port 0, 1 and 2 enabled 4-7 = Reserved
15-14
Ref Clock
13-12
Ext Con
11-9
Lane Setup/ARM PLL Setting
Boot Master
Boot Master select 0 = ARM is boot master (default) 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 7-27 shows settings for various input clock frequencies. (default = 4) Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
7-5
SYS PLL Setting
Min
3-1
Boot Devices
Boot Devices 101 = Ethernet boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-11
221
PRODUCT PREVIEW

SPRS835DAugust 2013 7.1.2.3.1 PCIe Boot Device Configuration Figure 7-10
16 Ref clk Ref clk 15
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PCIe Boot Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 13 12 11 10 Reserved ARM PLL Cfg 9 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Cfg Sys PLL Cfg 5 4 3 2 1 0 Lendian Lendian
Bar Config Bar Config
0110 0110
Table 7-12
Bit 16 Field Ref clk
PCIe Boot Device Configuration Field Descriptions

Description PCIe Reference clock frequency 0 = 100MHz 1 = Reserved PCIe BAR registers configuration This value can range from 0 to 0xf. See Table 7-13. When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [10:9] are reserved. Boot Master select 0 = ARM is boot master (default) 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits.This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 7-27 shows settings for various input clock frequencies. Boot Devices[4:1] 0110 = PCIe boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
PRODUCT PREVIEW
15-12 11-9
Bar Config Reserved/ARM PLL Setting
Boot Master
7-5
SYS PLL Setting
4-1
Boot Devices
Lendian
End of Table 7-12
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SPRS835DAugust 2013 BAR Config / PCIe Window Sizes

32-Bit Address Translation 64-Bit Address Translation BAR5 Clone of BAR4 BAR2/3 BAR4/5 BAR0 PCIe MMRs BAR1 32 16 16 32 16 16 32 32 64 4 4 4 BAR2 32 16 32 32 16 32 32 32 64 128 128 128 BAR3 32 32 32 32 64 64 64 64 128 128 128 256 BAR4 32 64 64 64 64 64 64 128
Table 7-13
BAR cfg 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111
128 256 256 256 512 1024 2048 256 512 1024 2048
7.1.2.3.2 HyperLink Boot Device Configuration Figure 7-11

16 Port Port 15
HyperLink Boot Device Configuration Fields

DEVSTAT Boot Mode Pins ROM Mapping 14 13 12 11 10 Reserved ARM PLL Cfg 9 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Cfg Sys PLL Cfg 5 4 3 2 1 0 Lendian Lendian
RefClk RefClk
Data Rate Data Rate
1110 1110
Table 7-14
Bit 16 Field Port
HyperLink Boot Device Configuration Field Descriptions (Part 1 of 2)

Description HyperLink port 0 = HyperLink0 1 = HyperLink1 HyperLink reference clock configuration 0 = 125 MHz 1 = 156.25 MHz 2-3 = Reserved HyperLink data rate configuration 0 = 1.25 GBs 1 = 3.125 GBs 2 = 6.25 GBs 3 = 12.5GBs
15-14
Ref Clocks
13-12
Data Rate
11-9
Reserved/ARM When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are determined by the PLL Setting [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. When Boot Master =1 (C66x is Boot Master), pin [10:9] are reserved. Boot Master Boot Master select 0 = ARM is boot master (default) 1 = C66x is boot master
223
PRODUCT PREVIEW
256

Bit 7-5 4-1 Field SYS PLL Setting Boot Devices
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HyperLink Boot Device Configuration Field Descriptions (Part 2 of 2)

Description The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Default system reference clock is 156.25 MHz. Table 7-27 shows settings for various input clock frequencies. Boot Devices[4:1] 1110 = HyperLink boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-14
7.1.2.3.3 UART Boot Device Configuration
PRODUCT PREVIEW
Figure 7-12
16 X X 15 X X
UART Boot Mode Configuration Field Description

DEVSTAT Boot Mode Pins ROM Mapping 14 X X 13 X X 12 Port Port 11 X 10 X ARM PLL Cfg 9 X 8 Boot Master=1 Boot Master=0 7 6 Sys PLL Config Sys PLL Config 5 4 Min Min 3 2 111 111 1 0 Lendian Lendian
Table 7-15
Bit 16-13 12 Field
UART Boot Configuration Field Descriptions

Description Not Used UART Port number 0 = UART0 1 = UART1
Reserved Port
11-9 8
ARM PLL Setting The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. Boot Master Boot Master select 0 = ARM is boot master 1 = C66x is boot master The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device. Table 7-27 shows settings for various input clock frequencies. (default = 4) Minimum boot configuration select bit. 0 = Minimum boot pin select disabled 1 = Minimum boot pin select enabled. When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for configuration bits with a "(default)" tag added in the description column). When Min = 0, all fields must be independently configured.
7-5 4
SYS PLL Setting Min
3-1
Boot Devices
Boot Devices[3:1] 111 = UART boot mode Others = Other boot modes Endianess 0 = Big endian 1 = Little endian
Lendian
End of Table 7-15
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7.1.2.4 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the most common format the RBL employs to determine the boot flow. These boot parameter tables have certain parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The common entries in the boot parameter table are shown in table Table 7-16.
Table 7-16
Byte Offset 0 2 4 6 8 10 12 14 16 18 20 Name Length Checksum Boot Mode Port Num SW PLL, MSW SW PLL, LSW Sec PLL Config, MSW Sec PLL Config, LSW System Freq Core Freq Boot Master
Boot Parameter Table Common Parameters

Description The length of the table, including the length field, in bytes. The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum verification of the table by the boot ROM. Internal values used by RBL for different boot modes. Identifies the device port number to boot from, if applicable PLL configuration, MSW PLL configuration, LSW ARM PLL configuration, MSW ARM PLL configuration, LSW The Frequency of the system clock in MHz The frequency of the core clock in MHz Set to TRUE if C66x is the master core.
End of Table 7-16
7.1.2.4.1 EMIF16 Boot Parameter Table Table 7-17

Byte Offset 22 Name Options
EMIF16 Boot Parameter Table

Description Async Config Parameters are used. 0 = Value in the async config paramters are not used to program async config registers. 1 = Value in the async config paramters are used to program async config registers. Set to 0 for EMIF16 (NOR) boot Most significant bit for Branch address (depends on chip select) Least significant bit for Branch address (depends on chip select) Chip Select for the NOR flash Memory width of the Emif16 bus (16 bits) Extended wait mode enabled 0 = Wait enable is disabled 1 = Wait enable is enabled Async Config Register MSW Async Config Register LSW Configured Through Boot Configuration Pins NO
24 26 28 30 32 34
Type Branch Address MSW Branch Address LSW Chip Select Memory Width Wait Enable
NO YES YES YES YES YES
36 38
Async Config MSW Async Config LSW
NO NO
End of Table 7-17
225
PRODUCT PREVIEW

SPRS835DAugust 2013 7.1.2.4.2 SRIO Boot Parameter Table Table 7-18 SRIO Boot Parameter Table
Description Bit 0 Tx enable 0 = SRIO Transmit disable 1 = SRIO Transmit Enable Bit 1 Mailbox Enable 0 = Mailbox mode disabled. (SRIO boot is in DirectIO mode). 1 = Mailbox mode enabled. (SRIO boot is in Messaging mode). Bit 2 Bypass Configuration 0 = Configure the SRIO 1 = Bypass SRIO configuration Bit 3 Bypass QM Configuration 0 = Configure the QM and CPDMA 1 = Bypass the QM and CPDMA configuration Bit 4 PLL setup 0 = SERDES Configuration registers are taken without modification. 1 = SERDES Configuration are modified based on the reference clock and link rate. Bit 5-15 = Reserved 24 Lane Setup 0b0000 = SRIO configured as four 1x ports 0b0001 = SRIO configured as 3 ports (2x, 1x, 1x) 0b0010 = SRIO configured as 3 ports (1x, 1x, 2x) 0b0011 =SRIO configured as 2 ports (2x, 2x) 0b0100 = SRIO configured as 1 4x port 0b 0101 - 0bffff = Reserved Reserved The node ID value to set for this device The SerDes reference clock frequency, in 1/100 MHZ Link rate, MHz Packet forward address range, low value Packet Forward address range, high value The bit is set for each lane/port that is configured as promiscuous Number of seconds before timeout. The value 0 disables the timeout SERDES Auxillary Register Configuration, MSW SERDES Auxillary Register Configuration, LSW YES (but not all lane setup are possible through the boot configuration pins) Configured Through Boot Configuration Pins NO
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Byte Offset Name 22 Options
PRODUCT PREVIEW
26 28 30 32 34 36 38 40 44 48 52 56 60 64 68 72 76 80
Reserved Node ID SerDes ref clk Link Rate PF Low PF High Promiscuous Mask Timeout Sec SERDES Aux, MSW SERDES Aux, LSW
NA NO YES YES NO NO NO NO NO NO NO NO NO NO NO NO NO NO
SERDES Rx Lane0 MSW SERDES Rx Configuration, Lane0, MSW SERDES Rx Lane0 LSW SERDES Rx Configuration, Lane0, LSW
End of Table 7-18
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7.1.2.4.3 Ethernet Boot Parameter Table Table 7-19

Byte Offset 22
Ethernet Boot Parameter Table (Part 1 of 2)

Name Options Description Bits 02 - 00 Interface 000 - 100 = Reserved 101 = SGMII 110 = Reserved 111 = Reserved Bits 03 HD 0 = Half Duplex 1 = Full Duplex Configured Through Boot Configuration Pins NO
Bits 06 - 05 Initialize Config 00 = Switch, SerDes, SGMII and PASS are configured 01 = Initialization is not done for the peripherals that are already enabled and running. 10 = Reserved 11 = None of the Ethernet system is configured. Bits 15 - 07 Reserved 24 26 28 30 32 34 36 38 40 42 44 46 48 50 MAC High MAC Med MAC Low Multi MAC High Multi MAC Med Multi MAC Low Source Port Dest Port Device ID 12 Device ID 34 Dest MAC High Dest MAC Med Dest MAC Low Lane Enable The 16 MSBs of the MAC address to receive during boot The 16 middle bits of the MAC address to receive during boot The 16 LSBs of the MAC address to receive during boot The 16 MSBs of the multi-cast MAC address to receive during boot The 16 middle bits of the multi-cast MAC address to receive during boot The 16 LSBs of the multi-cast MAC address to receive during boot The source UDP port to accept boot packets from. A value of 0 will accept packets from any UDP port The destination port to accept boot packets on. The first two bytes of the device ID. This is typically a string value, and is sent in the Ethernet ready frame The 2nd two bytes of the device ID. The 16 MSBs of the MAC destination address used for the Ethernet ready frame. Default is broadcast. The 16 middle bits of the MAC destination address The 16 LSBs of the MAC destination address One bit per lane. 0 - Lane disabled 1 - Lane enabled Bits 0-3 are the config index, bit 4 set if direct config used, bit 5 set if no configuration done The SGMII control register value The SGMII ADV Ability register value The 16 MSBs of the SGMII Tx config register The 16 LSBs of the SGMII Tx config register The 16 MSBs of the SGMII Rx config register The 16 LSBs of the SGMII Rx config register The 16 MSBs of the SGMII Aux config register The 16 LSBs of the SGMII Aux config register NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO
52 54 56 58 60 62 64 66 68
SGMII Config SGMII Control SGMII Adv Ability SGMII TX Cfg High SGMII TX Cfg Low SGMII RX Cfg High SGMII RX Cfg Low SGMII Aux Cfg High SGMII Aux Cfg Low
227
PRODUCT PREVIEW
Bit 4 Skip TX 0 = Send Ethernet Ready Frame every 3 seconds 1 = Don't send Ethernet Ready Frame

Byte Offset 70 72
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Ethernet Boot Parameter Table (Part 2 of 2)

Name PKT PLL Cfg MSW PKT PLL CFG LSW Description The packet subsystem PLL configuration, MSW The packet subsystem PLL configuration, LSW Configured Through Boot Configuration Pins NO NO
End of Table 7-19
7.1.2.4.4 PCIe Boot Parameter Table Table 7-20

Byte Offset 22
PCIe Boot Parameter Table

Name Options Description Bits 00 Mode 0 = Host Mode (Direct boot mode) 1 = Boot Table Boot Mode Bits 01 Configuration of PCIe 0 = PCIe is configured by RBL 1 = PCIe is not configured by RBL Bit 03-02 Reserved Bits 04 Multiplier 0 = SERDES PLL configuration is done based on SERDES register values 1 = SERDES PLL configuration based on the reference clock values Bits 05 - 15 = Reserved Configured Through Boot Configuration Pins NO
PRODUCT PREVIEW
24 26 28
Address Width Link Rate Reference clock
PCI address width, can be 32 or 64 SerDes frequency, in Mbps. Can be 2500 or 5000
YES with in conjunction with BAR sizes NO
NO Reference clock frequency, in units of 10 kHz. Value values are 10000 (100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz) and 31250 (312.5 MHz). A value of 0 means that value is already in the SerDes cfg parameters and will not be computed by the boot ROM. Window 1size. Window 2 size. Window 3 size. Valid only if address width is 32. Window 4 Size. Valid only if the address width is 32. Vendor ID Device ID Class code revision ID MSW Class code revision ID LSW PCIe SerDes config word, MSW PCIe SerDes config word, LSW SerDes lane config word, msw lane 0 SerDes lane config word, lsw, lane 0 SerDes lane config word, msw, lane 1 SerDes lane config word, lsw, lane 1 The timeout period. Values 0 disables the time out YES YES YES YES NO NO NO NO NO NO NO NO NO NO
30 32 34 36 38 40 42 44 46 48 50 52 54 56 58
Window 1 Size Window 2 Size Window 3 Size Window 4 Size Vendor ID Device ID Class code Rev ID MSW Class code Rev ID LSW SerDes cfg msw SerDes cfg lsw SerDes lane 0 cfg msw SerDes lane 0 cfg lsw SerDes lane 1 cfg msw SerDes lane 1 cfg lsw Timeout period (Secs)
End of Table 7-20
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2
7.1.2.4.5 I C Boot Parameter Table

I
Table 7-21
Offset Field 22 Option
I2C Boot Parameter Table

Value Bits 02 - 00 Mode 000 = Boot Parameter Table Mode 001 = Boot Table Mode 010 = Boot Config Mode 011 = Load GP header format data 100 = Slave Receive Boot Config Bits 15 - 03= Reserved The I C device address to boot from Extended boot device address I C address used to send data in the I C master broadcast mode. The I C address of this device The desired I C data rate (kHz) The next device address to boot (Used only if boot config option is selected) The extended next device address to boot (Used only if boot config option is selected) The number of CPU cycles to delay between writing the address to an I C EEPROM and reading data.
2 2 2 2 2 2
Configured Through Boot Configuration Pins NO
24 26 28 30 34 36 38 40
Boot Dev Addr Boot Dev Addr Ext Broadcast Addr Local Address Bus Frequency Next Dev Addr Next Dev Addr Ext Address Delay
YES YES NO NO NO NO NO NO
End of Table 7-21
7.1.2.4.6 SPI Boot Parameter Table Table 7-22

Byte Offset 22
SPI Boot Parameter Table

Name Options Description Bits 01 & 00 Modes 00 = Load a boot parameter table from the SPI (Default mode) 01 = Load boot records from the SPI (boot tables) 10 = Load boot config records from the SPI (boot config tables) 11 = Load GP header blob Bits 15- 02= Reserved The number of bytes in the SPI device address. Can be 16 or 24 bit The operational mode, 4 or 5 pin The chip select used (valid in 4 pin mode only). Can be 0-3. Standard SPI mode (0-3) Setup time between chip assert and transaction The SPI bus frequency in kHz. The first address to read from, MSW (valid for 24 bit address width only) The first address to read from, LSW Next Chip Select to be used (Used only in boot Config mode) The Next read address (used in boot config mode only) The Next read address (used in boot config mode only) Configured Through Boot Configuration Pins NO
24 26 28 30 32 34 36 38 40 42 44
Address Width NPin Chipsel Mode C2Delay Bus Freq, 100kHz Read Addr MSW Read Addr LSW Next Chip Select Next Read Addr MSW Next Read Addr LSW
YES YES YES YES NO NO YES YES NO NO NO
End of Table 7-22
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SPRS835DAugust 2013 7.1.2.4.7 HyperLink Boot Parameter Table Table 7-23
Byte Offset 12
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HyperLink Boot Parameter Table

Name Options Description Bits 00 Reserved Bits 01 Configuration of Hyperlink 0 = HyperLink is configured by RBL 1 = HyperLink is not configured by RBL Bits 15- 02 = Reserved Configured Through Boot Configuration Pins NO
14 16 18
Number of Lanes SerDes cfg msw SerDes cfg lsw SerDes CFG RX lane 0 cfg msw SerDes CFG RXlane 0 cfg lsw SerDes CFG TX lane 0 cfg msw SerDes CFG TXlane 0 cfg lsw SerDes CFG RX lane 1 cfg msw SerDes CFG RXlane 1 cfg lsw SerDes CFG TX lane 1 cfg msw SerDes CFG TXlane 1 cfg lsw SerDes CFG RX lane 2 cfg msw SerDes CFG RXlane 2 cfg lsw SerDes CFG TX lane 2 cfg msw SerDes CFG TXlane 2 cfg lsw SerDes CFG RX lane 3 cfg msw SerDes CFG RXlane 3 cfg lsw SerDes CFG TX lane 3 cfg msw SerDes CFG TXlane 3 cfg lsw
Number of Lanes to be configured PCIe SerDes config word, MSW PCIe SerDes config word, LSW SerDes RX lane config word, msw lane 0 SerDes RX lane config word, lsw, lane 0 SerDes TX lane config word, msw lane 0 SerDes TX lane config word, lsw, lane 0 SerDes RX lane config word, msw lane 1 SerDes RX lane config word, lsw, lane 1 SerDes TX lane config word, msw lane 1 SerDes TX lane config word, lsw, lane 1 SerDes RX lane config word, msw lane 2 SerDes RX lane config word, lsw, lane 2 SerDes TX lane config word, msw lane 2 SerDes TX lane config word, lsw, lane 2 SerDes RX lane config word, msw lane 3 SerDes RX lane config word, lsw, lane 3 SerDes TX lane config word, msw lane 3 SerDes TX lane config word, lsw, lane 3
NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO
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20 22 24 26 28 30 32 34 36 38 40 42 44 46
End of Table 7-23
7.1.2.4.8 UART Boot Parameter Table Table 7-24

Byte Offset 22 24
UART Boot Parameter Table (Part 1 of 2)

Name Reserved Data Format Description None Bits 00 Data Format 0 = Data Format is BLOB 1 = Data Format is Boot Table Bits 15 - 01 Reserved Bits 00 Protocol 0 = Xmodem Protocol 1 = Reserved Bits 15 - 01 Reserved Number of NACK pings to be sent before giving up Maximum number of consecutive receive errors acceptable. Time (msecs) waiting for NACK/ACK. Time Period between characters Number of bits supported for data. Only 8 bits is supported. Configured Through Boot Configuration Pins NA NO
26
Protocol
NO
28 30 32 34 36
Initial NACK Count Max Err Count NACK Timeout Character Timeout nDatabits
NO NO NO NO NO
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SPRS835DAugust 2013 UART Boot Parameter Table (Part 2 of 2)

Name Parity Description Bits 01 - 00 Parity 00 = No Parity 01 = Odd parity 10 = Even Parity Bits 15 - 02 Reserved Number of stop bits times two. Valid values are 2 (stop bits = 1), 3 (Stop Bits = 1.5), 4 (Stop Bits = 2) The over sample factor. Only 13 and 16 are valid. Bits 00 Flow Control 0 = No Flow Control 1 = RTS_CTS flow control Bits 15 - 01 Reserved Baud Rate, MSW Baud Rate, LSW Configured Through Boot Configuration Pins NO
Table 7-24
Byte Offset 38
40 42 44
nStopBitsx2 Over sample factor Flow Control
NO NO NO
46 48
Data Rate MSW Data Rate LSW
NO NO
End of Table 7-24
7.1.2.4.9 NAND Boot Parameter Table Table 7-25

Byte Offset 22
NAND Boot Parameter Table

Name Options Description Bits 00 Geometry 0 = Geometry is taken from this table 1 = Geometry is queried from NAND device. Bits 01 Clear NAND 0 = NAND Device is a non clear NAND and requires ECC 1 = NAND is a clear NAND and doesn.t need ECC. Bits 15 - 02 Reserved Configured Through Boot Configuration Pins NO
24 26 28 30 32 34 36 38 40
numColumnAddrBytes numRowAddrBytes numofDataBytesperPage_msw numofDataBytesperPage_lsw numPagesperBlock busWidth numSpareBytesperPage csel First Block
Number of bytes used to specify column address Number of bytes used to specify row address. Number of data bytes in each page, MSW Number of data bytes in each page, LSW Number of Pages per Block EMIF bus width. Only 8 or 16 bits is supported. Number of spare bytes allocated per page. Chip Select number (valid chip selects are 2-5) First block for RBL to try to read.
NO NO NO NO NO NO NO YES (If ARM is the boot master only chip select 2 is supported) YES
End of Table 7-25
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The RBL also provides an option to configure the DDR table before loading the image into the external memory. More information on how to configure the DDR3, refer to the Bootloader User Guide. The configuration table for DDR3 is shown in Table 7-26
Table 7-26
Byte Offset 0 4 8
DDR3 Boot Parameter Table

Name configselect msw configselect slsw configselect lsw pllprediv pllMult pllPostDiv sdRamConfig sdRamConfig2 sdRamRefreshctl sdRamTiming1 sdRamTiming2 sdRamTiming3 IpDfrNvmTiming powerMngCtl iODFTTestLogic performcountCfg performCountMstRegSel readIdleCtl sysVbusmIntEnSet sdRamOutImpdedCalcfg tempAlertCfg ddrPhyCtl1 ddrPhyCtl2 proClassSvceMap mstId2ClsSvce1Map mstId2ClsSvce2Map eccCtl eccRange1 eccRange2 rdWrtExcThresh Chip Config Description Selecting the configuration register below that to be set. Each filed below is represented by one bit each. Selecting the configuration register below that to be set. Each filed below is represented by one bit each. Selecting the configuration register below that to be set. Each filed below is represented by one bit each. PLL pre divider value (Should be the exact value not value -1) PLL Multiplier value (Should be the exact value not value -1) PLL post divider value (Should be the exact value not value -1) SDRAM config register SDRAM Config register SDRAM Refresh Control Register SDRAM Timing 1 Register SDRAM Timing 2 Register SDRAM Timing 3 Register LP DDR2 NVM Timing Register Power management Control Register IODFT Test Logic Global Control Register Performance Counter Config Register Performance Counter Master Region Select Register Read IDLE counter Register System Interrupt Enable Set Register SDRAM Output Impedence Calibration Config Register Temperature Alert Configuration Register DDR PHY Control Register 1 DDR PHY Control Register 1 Priority to Class of Service mapping Register Master ID to Class of Service Mapping 1 Register Master ID to Class of Service Mapping 2Register ECC Control Register ECC Address Range1 Register ECC Address Range2 Register Read Write Execution Threshold Register Chip Specific PHY configuration Configured Through Boot Configuration Pins NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO
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12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 - 376
End of Table 7-26
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7.1.2.5 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for: Any level of customization to current boot methods Definition of a completely customized boot 7.1.3 SoC Security The TI SoC contains security architecture that allows the C66x CorePacs and ARM CorePac to perform secure accesses within the device. For more information, contact a TI sales office for additional information available with the purchase of a secure device. 7.1.4 System PLL Settings
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See Table 7-11 for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip divider to reduce the frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip divider (/3), applies 350 MHz to the NETCP. The Main PLL is controlled using a PLL controller and a chip-level MMR. The ARM CorePac PLL, DDR3A PLL, DDR3B PLL and PASS PLL are controlled by chip level MMRs. For details on how to set up the PLL see Section 9.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers on page 286.For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
Table 7-27
BOOTMODE [7:5] 0b000 0b001 0b010 0b011 0b100 0b101 0b110 0b111
System PLL Configuration

Input Clock Freq (MHz) 50.00 66.67 80.00 100.00 156.25 250.00 312.50 122.88 800 MHz Device PLLD 0 0 0 0 3 4 7 0 PLLM 31 23 19 15 40 31 40 12 DSP 800 800.04 800 800 800.78 800 800.78 798.72 1000 MHz Device PLLD 0 0 0 0 4 0 4 3 PLLM 39 29 24 19 63 7 31 64 DSP 1000 1000.05 1000 1000 1000 1000 1000 999.989 1200 MHz Device PLLD 0 0 0 0 2 4 2 0 PLLM 47 35 29 23 45 47 22 19 DSP 1200 1200.06 1200 1200 1197.92 1200 1197.92 1228.80 PLLD 0 1 3 0 24 4 24 11 PA = 350 MHz (1) PLLM 41 62 104 20 335 41 167 204 DSP 1050 1050.053 1050 1050 1050 1050 1050 1049.6
(2)
End of Table 7-27

1 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator. 2 represents frequency in MHz.
7.1.4.1 ARM CorePac System PLL Settings
The PLL default settings are determined by the BOOTMODE[11:9] bits. Table 7-28 shows settings for various input clock frequencies. This will set the PLL to the maximum clock setting for the device. CLK = CLKIN (PLLM+1) (2 (PLLD+1))
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The PLL default settings are determined by the BOOTMODE[7:5] bits. Table 7-27 shows the settings for various input clock frequencies. This will set the PLL to the maximum clock setting for the device. CLK = CLKIN (PLLM+1) (2 (PLLD+1))

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The ARM CorePac PLL is controlled using a PLL controller and a chip-level MMR. For details on how to set up the PLL see Section 9.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers on page 286. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
Table 7-28
BOOTMODE [11:9] 0b000 0b001 0b010 0b011 0b100
ARM PLL Configuration

Input Clock Freq (MHz) 50.00 66.67 80.00 100.00 156.25 250.00 312.50 122.88 800 MHz Device PLLD 0 0 0 0 0 4 7 0 PLLM 31 23 19 15 40 31 40 12 DSP 800 800.04 800 800 800.78 800 800.78 798.72 1000 MHz Device PLLD 0 0 0 0 4 0 4 3 PLLM 39 29 24 19 63 7 31 64 DSP 1000 1000.05 1000 1000 1000 1000 1000 999.40 1200 MHz Device PLLD 0 0 0 0 24 4 2 0 PLLM 47 35 29 23 45 47 22 19 DSP 1200 1200.06 1200 1200 1197.92 1200 1197.92 1200.80 PLLD 0 0 0 0 0 4 0 0 1400 MHz Device PLLM 55 41 34 27 17 55 8 22 DSP 1400 1400.07 1400 1400 1406.25 1400 1406.25 1413.12
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0b101 0b110 0b111
End of Table 7-28
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7.2 Device Configuration

Certain device configurations like boot mode and endianess are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used. 7.2.1 Device Configuration at Device Reset The logic level present on each device configuration pin is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP. Table 7-29 describes the device configuration pins.
NoteIf a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see the Pullup/PullDown Resistors section of the Terminals chapter. Table 7-29
(1) (2)
Device Configuration Pins

Pin No. F29 IPD/IPU IPU
(1)
Configuration Pin LENDIAN
Functional Description Device endian mode (LENDIAN) 0 = Device operates in big endian mode 1 = Device operates in little endian mode Method of boot See Boot Modes Supported on page 211 for more details. See the Bootloader for the C66x DSP User Guide in 1.10 Related Documentation from Texas Instruments on page 21for detailed information on boot configuration. AVS interface selection 00 - AVS 4pin 6bit Dual-Phase VCNTL[5:2] (Default) 01 - AVS 4pin 4bit Single-Phase VCNTL[5:2] 10 - AVS 6pin 6bit Single-Phase VCNTL[5:0] 2 11 - I C Main PLL Output divider select 0 = Main PLL output divider needs to be set to 2 by BOOTROM 1 = Reserved ARM AVS Shared with the rest of SOC AVS 0 = ARM Core voltage and rest of SoC core voltage independent. 1= ARM Core voltage and rest of SoC core voltage shared bootstrap_reserved. Pulldown resistor required on pin. Control ARM remapping of DDR3A address space in the lower 4GB (32b space) Mode select 0 = DDR3A memory is accessible from ARM at 0x08 0000 0000 - 0x09 FFFF FFFF. 1 = DDR3A memory is accessible from ARM at 0x00 8000 0000 - 0x00 FFFF FFFF with 0x00 8000 0000 - 0x00 FFFF FFFF aliased at 0x08 0000 0000 - 0x08 FFFF FFFF.
BOOTMODE[15:0]
(1) (2)
IPD B31, E32, A31, F30, E30, F31, G30, A30, C30, D30, E29, B29, A35, D29, B30, F29 M1, M2 IPD
AVSIFSEL[1:0]
(1) (2)
MAINPLLODSEL
(1) (2)
E32
IPD
ARMAVSSHARED(1)
G24
IPU
ARM_LENDIAN
(1) (1)
B31 A36
IPD IPD
DDR3A_MAP_EN
End of Table 7-29

1 Internal 100-A pulldown or pullup is provided for this terminal. In most systems, a 1-k resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see the Pullup/Pulldown Resistors section of the Terminals chapter. 2 These signal names are the secondary functions of these pins.
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7.2.2 Peripheral Selection After Device Reset Several of the peripherals on the TCI6636K2H are controlled by the Power Sleep Controller (PSC). By default, the PCIe, SRIO, HyperLink, RAC, TAC, FFTC, AIF2, TCP3d, TCP3e, and VCP are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used. If one of the above modules is used in the selected ROM boot mode, the ROM code automatically enables the module. All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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7.2.3 Device State Control Registers The TCI6636K2H device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 7-30.
Table 7-30
Address Start 0x02620000 0x02620008 0x02620018 0x0262001C 0x02620020 0x02620024 0x02620038 0x0262003C 0x02620040 0x02620044 0x02620048 0x0262004C 0x02620050 0x02620054 0x02620058 0x0262005C 0x02620060 0x026200E0 0x02620110 0x02620118 0x02620130 0x02620134 0x02620138 0x0262013C 0x02620140 0x02620144 0x02620148 0x0262014C
Device State Control Registers (Part 1 of 4)

Address End 0x02620007 0x02620017 0x0262001B 0x0262001F 0x02620023 0x02620037 0x0262003B 0x0262003F 0x02620043 0x02620047 0x0262004B 0x0262004F 0x02620053 0x02620057 0x0262005B 0x0262005F 0x026200DF 0x0262010F 0x02620117 0x0262012F 0x02620133 0x02620137 0x0262013B 0x0262013F 0x02620143 0x02620147 0x0262014B 0x0262014F Size 8B 16B 4B 4B 4B 20B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 128B 48B 8B 24B 4B 4B 4B 4B 4B 4B 4B 4B Acronym Reserved Reserved JTAGID Reserved DEVSTAT Reserved KICK0 KICK1 DSP_BOOT_ADDR0 DSP_BOOT_ADDR1 DSP_BOOT_ADDR2 DSP_BOOT_ADDR3 DSP_BOOT_ADDR4 DSP_BOOT_ADDR5 DSP_BOOT_ADDR6 DSP_BOOT_ADDR7 Reserved Reserved MACID Reserved LRSTNMIPINSTAT_CLR RESET_STAT_CLR Reserved BOOTCOMPLETE Reserved RESET_STAT LRSTNMIPINSTAT DEVCFG See section 7.2.3.7 See section 7.2.3.5 See section 7.2.3.2 See section 7.2.3.9 See section 7.2.3.6 See section 7.2.3.8 See section 9.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem on page 320 See section 7.2.3.4 The boot address for C66x CorePac0 The boot address for C66x CorePac1 The boot address for C66x CorePac2 The boot address for C66x CorePac3 The boot address for C66x CorePac4 The boot address for C66x CorePac5 The boot address for C66x CorePac6 The boot address for C66x CorePac7 See section 7.2.3.1 See section 7.2.3.3 Description
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SPRS835DAugust 2013 Device State Control Registers (Part 2 of 4)

Address End 0x02620153 0x02620157 0x0262015B 0x0262015F 0x02620160 0x02620167 0x0262016B 0x0262017F 0x02620183 0x0262018F 0x02620193 0x02620197 0x0262019B 0x0262019F 0x026201A3 0x026201A7 0x026201AB 0x026201AF 0x026201B3 0x026201B7 0x026201BB 0x026201BF 0x026201C3 0x026201C7 0x026201CB 0x026201CF 0x026201FF 0x02620203 0x02620207 0x0262020B 0x0262020F 0x02620213 0x02620217 0x0262021B 0x0262021F 0x0262023F Size 4B 4B 4B 4B 4B 4B 4B 20B 4B 12B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 48B 4B 4B 4B 4B 4B 4B 4B 4B 32B Acronym PWRSTATECTL Reserved Reserved Reserved Reserved Reserved Reserved Reserved SmartReflex Class0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved NMIGR0 NMIGR1 NMIGR2 NMIGR3 NMIGR4 NMIGR5 NMIGR6 NMIGR7 Reserved See section 7.2.3.11 See section 9.2.4 Description See section 7.2.3.10
Table 7-30
Address Start 0x02620150 0x02620154 0x02620158 0x0262015C 0x02620160 0x02620164 0x02620168 0x0262016C 0x02620180 0x02620184 0x02620190 0x02620194 0x02620198 0x0262019C 0x026201A0 0x026201A4 0x026201A8 0x026201AC 0x026201B0 0x026201B4 0x026201B8 0x026201BC 0x026201C0 0x026201C4 0x026201C8 0x026201CC 0x026201D0 0x02620200 0x02620204 0x02620208 0x0262020C 0x02620210 0x02620214 0x02620218 0x0262021C 0x02620220
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Address Start 0x02620240 0x02620244 0x02620248 0x0262024C 0x02620250 0x02620254 0x02620258 0x0262025C 0x02620260 0x02620264 0x02620268 0x0262026C 0x02620270 0x0262027C 0x02620280 0x02620284 0x02620288 0x0262028C 0x02620290 0x02620294 0x02620298 0x0262029C 0x026202A0 0x026202A4 0x026202A8 0x026202AC 0x026202B0 0x026202BC 0x026202C0 0x02620300 0x02620304 0x02620308 0x0262030C 0x02620310 0x02620314 0x02620318 0x0262031C 0x02620320 0x02620324 0x02620328 0x0262032C 0x02620330 0x02620334 0x02620338
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Device State Control Registers (Part 3 of 4)

Address End 0x02620243 0x02620247 0x0262024B 0x0262024F 0x02620253 0x02620257 0x0262025B 0x0262025F 0x02620263 0x02620267 0x0262026B 0x0262026F 0x0262027B 0x0262027F 0x02620283 0x02620287 0x0262028B 0x0262028F 0x02620293 0x02620297 0x0262029B 0x0262029F 0x026202A3 0x026202A7 0x026202AB 0x026202AF 0x026202BB 0x026202BF 0x026202FF 0x02620303 0x02620307 0x0262030B 0x0262030F 0x02620313 0x02620317 0x0262031B 0x0262031F 0x02620323 0x02620327 0x0262032B 0x0262032F 0x02620333 0x02620337 0x0262034F Size 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 12B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 12B 4B 64B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B Acronym IPCGR0 IPCGR1 IPCGR2 IPCGR3 IPCGR4 IPCGR5 IPCGR6 IPCGR7 IPCGR8 IPCGR9 IPCGR10 IPCGR11 Reserved IPCGRH IPCAR0 IPCAR1 IPCAR2 IPCAR3 IPCAR4 IPCAR5 IPCAR6 IPCAR7 IPCAR8 IPCAR9 IPCAR10 IPCAR11 Reserved IPCARH Reserved TINPSEL TOUTPSEL RSTMUX0 RSTMUX1 RSTMUX2 RSTMUX3 RSTMUX4 RSTMUX5 RSTMUX6 RSTMUX7 RSTMUX8 RSTMUX9 RSTMUX10 RSTMUX11 Reserved See section 7.2.3.16 See section 7.2.3.17 See section 7.2.3.18 See section 7.2.3.15 See section 7.2.3.14 See section 7.2.3.13 Description See section 7.2.3.12
PRODUCT PREVIEW
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SPRS835DAugust 2013 Device State Control Registers (Part 4 of 4)

Address End 0x02620353 0x02620357 0x0262035B 0x0262035F 0x02620363 0x02620367 0x0262036B 0x0262036F 0x02620373 0x02620377 0x0262039B 0x0262039F 0x02620403 0x02620407 0x0262040B 0x026205FF 0x026206FF 0x02620703 0x0262070F 0x02620713 0x02620717 0x0262071B 0x0262071F 0x0262072F 0x02620733 0x02620737 0x0262074F 0x026207FF 0x02620C7B 0x02620C7F 0x02620C97 0x02620C9B 0x02620FFF Size 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 132B 4B 4B 4B 4B 62B 256B 4B 12B 4B 4B 4B 4B 16B 4B 4B 24B 176B Acronym MAINPLLCTL0 MAINPLLCTL1 PASSPLLCTL0 PASSPLLCTL1 DDR3APLLCTL0 DDR3APLLCTL1 DDR3BPLLCTL0 DDR3BPLLCTL1 ARMPLLCTL0 ARMPLLCTL1 Reserved Reserved ARMENDIAN_CFG0_0 ARMENDIAN_CFG0_1 ARMENDIAN_CFG0_2 Reserved Reserved CHIP_MISC_CTL0 Reserved SYSENDSTAT Reserved Reserved Reserved Reserved SYNCECLK_PINCTL Reserved USB_PHY_CTL Reserved See section USB PHY Control (USB_PHY_CTLx) Registers on page 260 See section SYNECLK_PINCTL Register on page 260 See section System Endian Status Register (SYSENDSTAT) on page 259 See section Chip Miscellaneous Control (CHIP_MISC_CTL0) Register on page 258 See section ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7 on page 257 See section ARM CorePac System PLL Settings on page 233 See section 9.6 DDR3A PLL and DDR3B PLL on page 302 See section 9.6 DDR3A PLL and DDR3B PLL on page 302 Description See section 9.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers on page 286 See section 9.7 PASS PLL on page 304
Table 7-30
Address Start 0x02620350 0x02620354 0x02620358 0x0262035C 0x02620360 0x02620364 0x02620368 0x0262036C 0x02620370 0x02620374 0x02620378 0x0262039C 0x02620400 0x02620404 0x02620408 0x0262040C 0x02620600 0x02620700 0x02620704 0x02620710 0x02620714 0x02620718 0x0262071C 0x02620720 0x02620730 0x02620734 0x02620738 0x02620750 0x02620800 0x02620C7C 0x02620C80 0x02620C98 0x02620C9C
1148B Reserved 4B 24B 4B 868B CHIP_MISC_CTL1 Reserved DEVSPEED Reserved See section Device Speed (DEVSPEED) Register on page 256 See section Chip Miscellaneous Control (CHIP_MISC_CTL1) Register on page 259
End of Table 7-30
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7.2.3.1 Device Status (DEVSTAT) Register
The Device Status Register depicts device configuration selected upon a power-on reset by the POR or RESETFULL pin. Once set, these bits remain set until a power-on reset. The Device Status Register is shown in the figure below.
Figure 7-13
31 Reserved R-0000 0000 0000 00
Device Status Register

26 25 DDR3A_MAP_EN R-x
spacer
24 Reserved R-x
22
21 ARMAVSSHARED R/W-x
20 Reserved
19 MAINPLLODSEL R/W-x
18 AVSIFSEL R/W-xx
17
16 BOOTMODE R/W-x xxxx xxxx xxxx xxx
0 LENDIAN R-x
(1)
PRODUCT PREVIEW
R-x
Legend: R = Read only; RW = Read/Write; -n = value after reset

1 x indicates the bootstrap value latched via the external pin
Table 7-31
Bit 31-26 25 Field
Device Status Register Field Descriptions

Description Reserved. Read only, writes have no effect. DDR3A mapping enable 0 = DDR3A memory is accessible from ARM at 0x8:0000_0000 - 0x9:FFFF_FFFF. 1 = DDR3A memory is accessible in 32b space from ARM, i.e., at 0x0:8000_0000 - 0x0:FFFF_FFFF. DDR3A is also accessible at 0x8:0000_0000 - 0x9:FFFF_FFFF, with the space 0x0:8000_0000 - 0x0:FFFF_FFFF address aliased at 0x8:0000_0000 - 0x8:7FFF_FFFF. Reserved ARM AVS Shared with the rest of SOC AVS 0 = ARM Core voltage and rest of SoC core voltage independent. 1= ARM Core voltage and rest of SoC core voltage share Reserved Main PLL Output divider select 0 = Main PLL output divider needs to be set to 2 by BOOTROM 1 = Reserved AVS interface selection 00 = AVS 4-bit Dual Phase VCNTL[5:2] and I2C 2 01 = AVS 4-bit Single Phase VCNTL[5:2] and I C 1x = AVS 6-bit Single Phase VCNTL[5:0] Determines the bootmode configured for the device. For more information on bootmode, see Section 7.1.2 Boot Modes Supported on page 211 and see the Bootloader for the C66x DSP User Guide in1.10 Related Documentation from Texas Instruments on page 21. Device endian mode (LENDIAN) shows the status of whether the system is operating in big endian mode or little endian mode (default). 0 = System is operating in big endian mode 1 = System is operating in little endian mode (default)
Reserved DDR3A_MAP_EN
24-22 21
Reserved ARMAVSSHARED
20 19
Reserved MAINPLLODSEL
18-17
AVSIFSEL
16-1
BOOTMODE
LENDIAN
End of Table 7-31
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7.2.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in Figure 7-14 and described in Table 7-32.
Figure 7-14
31 Reserved R-0 Legend: R = Read only; RW = Read/Write; -n = value after reset
Device Configuration Register (DEVCFG)

3 2 PCIESSMODE R/W-00 1 0 SYSCLKOUTEN R/W-1
Bit 31-3 2-1
Field Reserved PCIESSMODE
Description Reserved. Read only, writes have no effect. Device Type Input of PCIeSS 00 = Endpoint 01 = Legacy Endpoint 10 = Rootcomplex 11 = Reserved) SYSCLKOUT enable 0 = No clock output 1 = Clock output enabled (default)
SYSCLKOUTEN
End of Table 7-32
7.2.3.3 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x02620018. The JTAG ID Register is shown below.
Figure 7-15
31 VARIANT R-xxxx
JTAG ID (JTAGID) Register

28 27 PART NUMBER R-1011 1001 1000 0001 12 11 MANUFACTURER R-0000 0010 111 1 0 LSB R-1
Legend: RW = Read/Write; R = Read only; -n = value after reset
Table 7-33
Bit 31-28 27-12 11-1 0 Field
JTAG ID Register Field Descriptions

Value xxxx 1011 1001 1000 0001 0000 0010 111 1 Description Variant value Part Number for boundary scan Manufacturer This bit is read as a 1 for TCI6636K2H
VARIANT PART NUMBER MANUFACTURER LSB
End of Table 7-33
NoteThe value of the VARIANT and PART NUMBER fields depends on the silicon revision being used.
See the Silicon Errata for details.
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Table 7-32
Device Configuration Register Field Descriptions

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7.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent spurious writes from changing any of the Bootcfg MMR (memory mapped registers) values. When the kicker is locked (which it is initially after power on reset), none of the Bootcfg MMRs are writable (they are only readable). This mechanism requires an MMR write to each of the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is unlocked. See Table 7-30 Device State Control Registers on page 236 for the address location. Once released, all the Bootcfg MMRs having write permissions are writable (the read only MMRs are still read only). The KICK0 data is 0x83e70b13. The KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs locks the kicker mechanism and blocks writes to Bootcfg MMRs. To ensure protection to all Bootcfg MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.
7.2.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register latches the status of LRESET and NMI based on the setting of CORESEL[2:0]. The LRESETNMI PIN Status Register is shown in the figure and table below.
Figure 7-16
31 Reserved R-0
PRODUCT PREVIEW
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

16 15 NMI7 R-0 14 NMI6 R-0 13 NMI5 R-0 12 NMI4 R-0 11 NMI3 R-0 10 9 8 7 LR7 R-0 6 LR6 R-0 5 LR5 R-0 4 LR4 R-0 3 LR3 R-0 2 LR2 R-0 1 LR1 R-0 0 LR0 R-0
NMI2 NMI1 NMI0 R-0 R-0 R-0
Table 7-34
Bit 31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field
LRESETNMI PIN Status Register Field Descriptions

Description Reserved C66x CorePac7 in NMI C66x CorePac6 in NMI C66x CorePac5 in NMI C66x CorePac4 in NMI C66x CorePac3 in NMI C66x CorePac2 in NMI C66x CorePac1 in NMI C66x CorePac0 in NMI C66x CorePac7 in Local Reset C66x CorePac6 in Local Reset C66x CorePac5 in Local Reset C66x CorePac4 in Local Reset C66x CorePac3 in Local Reset C66x CorePac2 in Local Reset C66x CorePac1 in Local Reset C66x CorePac0 in Local Reset
Reserved NMI7 NMI6 NMI5 NM4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
End of Table 7-34
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7.2.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register clears the status of LRESET and NMI based on CORESEL[2:0]. The LRESETNMI PIN Status Clear Register is shown in the figure and table below.
Figure 7-17
31 Reserved R-0
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

16 15 NMI7 WC, +0 14 NMI6 WC, +0 13 NMI5 WC, +0 12 NMI4 WC, +0 11 NMI3 WC, +0 10 NMI2 WC, +0 9 8 7 LR7 WC, +0 6 LR6 WC, +0 5 LR5 WC, +0 4 LR4 WC, +0 3 LR3 WC, +0 2 LR2 WC, +0 1 LR1 WC, +0 0 LR0 WC, +0
NMI1 NMI0 WC, +0 WC, +0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Bit 31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field Reserved NMI7 NM6 NMI5 NMI4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
Description Reserved C66x CorePac7 in NMI Clear C66x CorePac6 in NMI Clear C66x CorePac5 in NMI Clear C66x CorePac4 in NMI Clear C66x CorePac3 in NMI Clear C66x CorePac2 in NMI Clear C66x CorePac1 in NMI Clear C66x CorePac0 in NMI Clear C66x CorePac7 in Local Reset Clear C66x CorePac6 in Local Reset Clear C66x CorePac5 in Local Reset Clear C66x CorePac4 in Local Reset Clear C66x CorePac3 in Local Reset Clear C66x CorePac2 in Local Reset Clear C66x CorePac1 in Local Reset Clear C66x CorePac0 in Local Reset Clear
End of Table 7-35
7.2.3.7 Reset Status (RESET_STAT) Register
The Reset Status Register (RESET_STAT) captures the status of local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps. In case of local reset: The LRx bits are written as 1 and the GR bit is written as 0 only when the C66x CorePac receives a local reset without receiving a global reset. In case of global reset: The LRx bits are written as 0 and the GR bit is written as 1 only when a global reset is asserted.
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Table 7-35
LRESETNMI PIN Status Clear Register Field Descriptions

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The Reset Status Register is shown in the figure and table below.
Figure 7-18
31 GR R, +1 30 Reserved R, + 000 0000 0000 0000 0000 0000
Reset Status Register (RESET_STAT)

8 7 LR7 R,+0 6 LR6 R,+0 5 LR5 R,+0 4 LR4 R,+0 3 LR3 R,+0 2 LR2 R,+0 1 LR1 R,+0 0 LR0 R,+0
Table 7-36
Bit 31 GR
Reset Status Register Field Descriptions

Field Description Global reset status 0 = Device has not received a global reset. 1 = Device received a global reset. Reserved. C66x CorePac7 reset status 0 = C66x CorePac7 has not received a local reset. 1 = C66x CorePac7 received a local reset. C66x CorePac6 reset status 0 = C66x CorePac6 has not received a local reset. 1 = C66x CorePac6 received a local reset. C66x CorePac5 reset status 0 = C66x CorePac5 has not received a local reset. 1 = C66x CorePac5 received a local reset. C66x CorePac4 reset status 0 = C66x CorePac4 has not received a local reset. 1 = C66x CorePac4received a local reset. C66x CorePac3 reset status 0 = C66x CorePac3 has not received a local reset. 1 = C66x CorePac3 received a local reset. C66x CorePac2 reset status 0 = C66x CorePac2 has not received a local reset. 1 = C66x CorePac2 received a local reset. C66x CorePac1 reset status 0 = C66x CorePac1 has not received a local reset. 1 = C66x CorePac1 received a local reset. C66x CorePac0 reset status 0 = C66x CorePac0 has not received a local reset. 1 = C66x CorePac0 received a local reset.
PRODUCT PREVIEW
30-8 7
Reserved LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
End of Table 7-36
7.2.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear Register is shown in the figure and table below.
Figure 7-19
31 GR RW, +0 30 Reserved R, + 000 0000 0000 0000 0000 0000
Reset Status Clear Register (RESET_STAT_CLR)

8 7 LR7 RW,+0 6 LR6 RW,+0 5 LR5 RW,+0 4 LR4 RW,+0 3 LR3 RW,+0 2 LR2 RW,+0 1 LR1 RW,+0 0 LR0 RW,+0
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SPRS835DAugust 2013 Reset Status Clear Register Field Descriptions

Description Global reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register. Reserved. C66x CorePac7 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR7 bit clears the corresponding bit in the RESET_STAT register. C66x CorePac6 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR6 bit clears the corresponding bit in the RESET_STAT register.
Table 7-37
Bit 31 Field GR
30-8 7
Reserved LR7
LR6
LR5
LR4
C66x CorePac4 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR4 bit clears the corresponding bit in the RESET_STAT register. C66x CorePac3 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register. C66x CorePac2 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register. C66x CorePac1 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register. C66x CorePac0 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
LR3
LR2
LR1
LR0
End of Table 7-37
7.2.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status to indicate the completion of the ROM booting process. The Boot Complete Register is shown in the figure and table below.
Figure 7-20
31 12
Boot Complete Register (BOOTCOMPLETE)

11 BC11 RW,+0 10 BC10 RW,+0 9 BC9 RW,+0 8 BC8 RW,+0 7 BC7 RW,+0 6 BC6 RW,+0 5 BC5 RW,+0 4 BC4 RW,+0 3 BC3 RW,+0 2 BC RW,+0 1 BC1 RW,+0 0 BC0 RW,+0
Reserved R, + 0000 0000 0000 0000 0000
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C66x CorePac5 reset clear bit 0 = Writing a 0 has no effect. 1 = Writing a 1 to the LR5 bit clears the corresponding bit in the RESET_STAT register.

Bit 31-12 11 Field Reserved BC11
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Boot Complete Register Field Descriptions

Description Reserved. ARM CorePac 3 boot status 0 = ARM CorePac 3 boot NOT complete 1 = ARM CorePac 3 boot complete ARM CorePac 2 boot status 0 = ARM CorePac 2 boot NOT complete 1 = ARM CorePac 2 boot complete ARM CorePac 1 boot status 0 = ARM CorePac 1 boot NOT complete 1 = ARM CorePac 1 boot complete ARM CorePac 0 boot status 0 = ARM CorePac 0 boot NOT complete 1 = ARM CorePac 0 boot complete C66x CorePac7 boot status 0 = C66x CorePac 7 boot NOT complete 1 = C66x CorePac 7 boot complete C66x CorePac6 boot status 0 = C66x CorePac 6 boot NOT complete 1 = C66x CorePac 6 boot complete C66x CorePac5 boot status 0 = C66x CorePac 5 boot NOT complete 1 = C66x CorePac 5 boot complete C66x CorePac4 boot status 0 = C66x CorePac 4 boot NOT complete 1 = C66x CorePac 4 boot complete C66x CorePac 3 boot status 0 = C66x CorePac 3 boot NOT complete 1 = C66x CorePac 3 boot complete C66x CorePac2 boot status 0 = C66x CorePac 2 boot NOT complete 1 = C66x CorePac 2 boot complete C66x CorePac1 boot status 0 = C66x CorePac 1 boot NOT complete 1 = C66x CorePac 1 boot complete C66x CorePac0 boot status 0 = C66x CorePac 0 boot NOT complete 1 = C66x CorePac 0 boot complete
10
BC10
BC9
BC8
PRODUCT PREVIEW
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
End of Table 7-38
The BCx bit indicates the boot complete status of the corresponding C66x CorePac. All BCx bits are sticky bits that is, they can be set only once by the software after device reset and they will be cleared to 0 on all device resets (warm reset and power-on reset). Boot ROM code is implemented such that each C66x CorePac sets its corresponding BCx bit immediately before branching to the predefined location in memory.
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7.2.3.10 Power State Control (PWRSTATECTL) Register
The Power State Control Register (PWRSTATECTL) is controlled by the software to indicate the power-saving mode. Under ROM code, the C66x CorePac reads this register to differentiate between the various power saving modes. This register is cleared only by POR and is not changed by any other device reset. See the Hardware Design Guide for KeyStone Devices in 1.10 Related Documentation from Texas Instruments on page 21 for more information. The PWRSTATECTL Register is shown in Figure 7-21 and described in Table 7-39.
Figure 7-21
31
Power State Control Register (PWRSTATECTL)

10 9 Width RW+0 8 Wait RW+0 7 6 5 4 3 2 1 Hibernation RW+0 0 Reserved R+0
Hibernation Recovery Branch Address RW+0000 0000 0000 0000 00
Recovery Master Local Reset Action RW+0 RW+0
Stored Hibernation Mode SR Index RW+0 RW+0
Table 7-39
Bit 31-10 9 Field
Power State Control Register Field Descriptions

Description Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User Guide in1.10 Related Documentation from Texas Instruments on page 21. EMIF 16 Width (if the recovery address is in EMIF16 space). 0 = 8-bit 1 = 16-bit Extended Wait (if the recovery address is in EMIF16 space) 0 = Extended Wait disabled 1 = Extended Wait enabled Master performs hibernation recovery 0 = C66x CorePacs perform hibernation recovery 1 = ARM CorePac performs hibernation recovery Action of Local Reset 00 = Idle on Local Reset 01 = Branch to the base of MSMC on Local Reset 10 = Branch to the base of DDR3 on Local Reset 11 = Branch to the base of L2 on Local Reset (C66x CorePac) 0-3 value latched in the SR bits of the DEVSTAT register Indicates whether the device is in hibernation mode 1 or mode 2. 0 = Hibernation mode 1 1 = Hibernation mode 2 Indicates whether the device is in hibernation mode or not. 0 = Not in hibernation mode 1 = Hibernation mode Reserved
Hibernation Recovery Branch Address Width
Wait
Recovery Master
6-5
Local Reset Action
4-3 2
Stored Index Hibernation Mode
Hibernation
Reserved
End of Table 7-39
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Legend: R = Read Only, RW = Read/Write; -n = value after reset

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7.2.3.11 NMI Event Generation to C66x CorePac (NMIGRx) Register
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The TCI6636K2H has eight NMIGRx registers (NMIGR0 through NMIGR7). The NMIGR0 register generates an NMI event to C66x CorePac0, the NMIGR1 register generates an NMI event to C66x CorePac1, and so on. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI event generation to the C66x CorePac is shown in Figure 7-22 and described in Table 7-40.
Figure 7-22
31 Reserved R, +0000 0000 0000 0000 0000 0000 0000 000 Legend: RW = Read/Write; -n = value after reset
NMI Generation Register (NMIGRx)

1 0 NMIG RW,+0
PRODUCT PREVIEW
Table 7-40
Bit 31-1 0 Field
NMI Generation Register Field Descriptions

Description Reserved Reads return 0 Writes: 0 = No effect 1 = Creates NMI pulse to the corresponding C66x CorePac C66x CorePac0 for NMIGR0, etc.
Reserved NMIG
End of Table 7-40
7.2.3.12 IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts. The TCI6636K2H has twelve IPCGRx registers (IPCGR0 through IPCGR11 ). These registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the IPCGRx register generates an interrupt pulse to the C66x CorePacx (0 <= x <= 7) or ARM CorePac core (x-8) (8<=x<=11). These registers also provide a Source ID facility identifying up to 28 different sources of interrupts. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. There can be numerous sources for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation Register is shown in Figure 7-23 and described in Table 7-41.
Figure 7-23
31 SRCS27 RW +0 30 SRCS26 RW +0
IPC Generation Registers (IPCGRx)

29 SRCS25 RW +0 28 SRCS24 RW +0 27 SRCS23 SRCS4 RW +0 (per bit field) 8 7 SRCS3 RW +0 6 SRCS2 RW +0 5 SRCS1 RW +0 4 SRCS0 RW +0 3 Reserved R, +000 1 0 IPCG RW +0
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SPRS835DAugust 2013 IPC Generation Registers Field Descriptions

Description Reads return current value of internal register bit. Writes: 0 = No effect 1 = Sets both SRCSx and the corresponding SRCCx.
Table 7-41
Bit 31-4 Field SRCSx
3-1 0
Reserved IPCG
Reserved Reads return 0. Writes: 0 = No effect 1 = Creates an inter-DSP/ARM interrupt.
End of Table 7-41
7.2.3.13 IPC Acknowledgement (IPCARx) Registers
The IPCARx registers facilitate inter-CorePac interrupt acknowledgement. The TCI6636K2H has twelve IPCARx (IPCAR0 through IPCAR11) registers. These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in the following figure and table.
Figure 7-24
31 SRCC27 RW +0 30 SRCC26 RW +0
IPC Acknowledgement Registers (IPCARx)

29 SRCC25 RW +0 28 SRCC24 RW +0 27 SRCC23 SRCC4 RW +0 (per bit field) 8 7 SRCC3 RW +0 6 SRCC2 RW +0 5 SRCC1 RW +0 4 SRCC0 RW +0 3 Reserved R, +0000 0
Table 7-42
Bit 31-4 Field SRCCx
IPC Acknowledgement Registers Field Descriptions

Description Reads return current value of internal register bit. Writes: 0 = No effect 1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 7-42
7.2.3.14 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin HOUT.
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The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6) followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight SYSCLK1/6 cycle window the pulse blocking window. To generate back-to-back pulses, the back-to-back writes to the IPCGRH register must be written after the eight SYSCLK1/6 cycle pulse-blocking window has elapsed. The IPC Generation Host Register is shown in Figure 7-25 and described in Table 7-43.
Figure 7-25
31 SRCS27 RW +0 30 SRCS26 RW +0
IPC Generation Registers (IPCGRH)

29 SRCS25 RW +0 28 SRCS24 RW +0 27 SRCS23 SRCS4 RW +0 (per bit field) 8 7 SRCS3 RW +0 6 SRCS2 RW +0 5 SRCS1 RW +0 4 SRCS0 RW +0 3 Reserved R, +000 1 0 IPCG RW +0
PRODUCT PREVIEW
Table 7-43
Bit 31-4 Field SRCSx
IPC Generation Registers Field Descriptions

Description Reads return current value of internal register bit. Writes: 0 = No effect 1 = Sets both SRCSx and the corresponding SRCCx.
3-1 0
Reserved IPCG
Reserved Reads return 0. Writes: 0 = No effect 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 7-43
7.2.3.15 IPC Acknowledgement Host (IPCARH) Register
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the same as for other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 7-26 and described in Table 7-44.
Figure 7-26
31 SRCC27 RW +0 30 SRCC26 RW +0
IPC Acknowledgement Register (IPCARH)

29 SRCC25 RW +0 28 SRCC24 RW +0 27 SRCC23 SRCC4 RW +0 (per bit field) 8 7 SRCC3 RW +0 6 SRCC2 RW +0 5 SRCC1 RW +0 4 SRCC0 RW +0 3 Reserved R, +0000 0
Table 7-44
Bit 31-4 Field SRCCx
IPC Acknowledgement Register Field Descriptions

Description Reads the return current value of the internal register bit. Writes: 0 = No effect 1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 7-44
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7.2.3.16 Timer Input Selection Register (TINPSEL)
The Timer Input Selection Register selects timer inputs and is shown in Figure 7-27 and described in Table 7-45.
Figure 7-27
31 TINPHSEL15 RW, +0 23 TINPHSEL11 RW, +0 15 TINPHSEL7 RW, +0 7 TINPHSEL3 RW, +0
Timer Input Selection Register (TINPSEL)

30 TINPLSEL15 RW, +0 22 TINPLSEL11 RW, +0 14 TINPLSEL7 RW, +0 6 TINPLSEL3 RW, +0 29 TINPHSEL14 RW, +0 21 TINPHSEL10 RW, +0 13 TINPHSEL6 RW, +0 5 TINPHSEL2 RW, +0 28 TINPLSEL14 RW, +0 20 TINPLSEL10 RW, +0 12 TINPLSEL6 RW, +0 4 TINPLSEL2 RW, +0 27 TINPHSEL13 RW, +0 19 TINPHSEL9 RW, +0 11 TINPHSEL5 RW, +0 3 TINPHSEL1 RW, +0 26 TINPLSEL13 RW, +0 18 TINPLSEL9 RW, +0 10 TINPLSEL5 RW, +0 2 TINPLSEL1 RW, +0 25 TINPHSEL12 RW, +0 17 TINPHSEL8 RW, +0 9 TINPHSEL4 RW, +0 1 TINPHSEL0 RW, +0 24 TINPLSEL12 RW, +0 16 TINPLSEL8 RW, +0 8 TINPLSEL4 RW, +0 0 TINPLSEL0 RW, +0
Table 7-45
Bit 31 Field
Timer Input Selection Field Description (Part 1 of 3)

Description Input select for TIMER15 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER15 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER14 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER14 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER13 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER13 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER12 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER12low. 0 = TIMI0 1 = TIMI1 Input select for TIMER11 high. 0 = TIMI0 1 = TIMI1
TINPHSEL15
30
TINPLSEL15
29
TINPHSEL14
28
TINPLSE14
27
TINPHSEL13
26
TINPLSEL13
25
TINPHSEL12
24
TINPLSEL12
23
TINPHSEL11
251
PRODUCT PREVIEW

Bit 22 Field TINPLSEL11
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Timer Input Selection Field Description (Part 2 of 3)

Description Input select for TIMER11 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER10 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER10 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER9 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER9 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER8 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER8 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER7 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER7 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER6 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER6 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER5 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER5 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER4 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER4 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER3 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER3 low. 0 = TIMI0 1 = TIMI1
21
TINPHSEL10
20
TINPLSEL10
19
TINPHSEL9
PRODUCT PREVIEW
18
TINPLSEL9
17
TINPHSEL8
16
TINPLSEL8
15
TINPHSEL7
14
TINPLSEL7
13
TINPHSEL6
12
TINPLSEL6
11
TINPHSEL5
10
TINPLSEL5
TINPHSEL4
TINPLSEL4
TINPHSEL3
TINPLSEL3
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SPRS835DAugust 2013 Timer Input Selection Field Description (Part 3 of 3)

Description Input select for TIMER2 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER2 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER1 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER1 low. 0 = TIMI0 1 = TIMI1 Input select for TIMER0 high. 0 = TIMI0 1 = TIMI1 Input select for TIMER0 low. 0 = TIMI0 1 = TIMI1
Table 7-45
Bit 5 Field
TINPHSEL2
TINPLSEL2
TINPHSEL1
TINPLSEL1
TINPHSEL0
TINPLSEL0
End of Table 7-45
7.2.3.17 Timer Output Selection Register (TOUTPSEL)
The control register TOUTSEL handles the timer output selection and is shown in Figure 7-28 and described in Table 7-46.
Figure 7-28
31 Reserved R,+0000000000000000000000 Legend: R = Read only; RW = Read/Write; -n = value after reset
Timer Output Selection Register (TOUTPSEL)

10 9 TOUTPSEL1 RW,+00001 5 4 TOUTPSEL0 RW,+00000 0
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Bit 31-10 9-5 Field Reserved TOUTPSEL1
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Timer Output Selection Field Description

Description Reserved Output select for TIMO1 00000: TOUTL0 00001: TOUTH0 00010: TOUTL1 00011: TOUTH1 00100: TOUTL2 00101: TOUTH2 00110: TOUTL3 00111: TOUTH3 01000: TOUTL4 01001: TOUTH4 01010: TOUTL5 01011: TOUTH5 01100: TOUTL6 01101: TOUTH6 01110: TOUTL7 01111: TOUTH7 Output select for TIMO0 00000: TOUTL0 00001: TOUTH0 00010: TOUTL1 00011: TOUTH1 00100: TOUTL2 00101: TOUTH2 00110: TOUTL3 00111: TOUTH3 01000: TOUTL4 01001: TOUTH4 01010: TOUTL5 01011: TOUTH5 01100: TOUTL6 01101: TOUTH6 01110: TOUTL7 01111: TOUTH7 10000: TOUTL8 10001: TOUTH8 10010: TOUTL9 10011: TOUTH9 10100: TOUTL10 10101: TOUTH10 10110: TOUTL11 10111: TOUTH11 11000: TOUTL12 11001: TOUTH12 11010: TOUTL13 11011: TOUTH13 11100: TOUTL14 11101: TOUTH14 11110: TOUTL15 11111: TOUTH15 10000: TOUTL8 10001: TOUTH8 10010: TOUTL9 10011: TOUTH9 10100: TOUTL10 10101: TOUTH10 10110: TOUTL11 10111: TOUTH11 11000: TOUTL12 11001: TOUTH12 11010: TOUTL13 11011: TOUTH13 11100: TOUTL14 11101: TOUTH14 11110: TOUTL15 11111: TOUTH15
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4-0
TOUTPSEL0
End of Table 7-46
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7.2.3.18 Reset Mux (RSTMUXx) Register
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX11 for each of the C66x CorePacs and ARM CorePac on the device. These registers are located in Bootcfg memory space. The Reset Mux Register is shown in the figure and table below.
Figure 7-29
31 Reserved R, +0000 0000 0000 0000 0000 00
Reset Mux Register

10 9 EVTSTATCLR RC, +0 8 Reserved R, +0 7 DELAY RW, +100 5 4 EVTSTAT R, +0 3 OMODE RW, +000 1 0 LOCK RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
Table 7-47
Bit 31-10 9 Field
Reset Mux Register Field Descriptions

Description Reserved Clear event status 0 = Writing 0 has no effect 1 = Writing 1 to this bit clears the EVTSTAT bit Reserved Delay cycles between NMI & local reset 000b = 256 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b 001b = 512 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b 010b = 1024 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b 011b = 2048 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b 100b = 4096 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b (default) 101b = 8192 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b 110b = 16384 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b 111b = 32768 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b Event status 0 = No event received (Default) 1 = WD timer event received by Reset Mux block Timer event operation mode 000b = WD timer event input to the Reset Mux block does not cause any output event (default) 001b = Reserved 010b = WD Timer Event input to the Reset Mux block causes local reset input to C66x CorePac. Note that for Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to generate reset to PLL Controller. 011b = WD Timer Event input to the Reset Mux block causes NMI input to C66x CorePac. Note that for Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to generate reset to PLL Controller. 100b = WD Timer Event input to the Reset Mux block causes NMI input followed by local reset input to C66x CorePac. Delay between NMI and local reset is set in DELAY bit field. Note that for Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to generate reset to PLL Controller. 101b = WD timer event input to the Reset Mux block causes device reset to TCI6636K2H. Note that for Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to the Device Reset generation to generate reset to PLL Controller. 110b = Reserved 111b = Reserved Lock register fields 0 = Register fields are not locked (default) 1 = Register fields are locked until the next timer reset
Reserved EVTSTATCLR
8 7-5
Reserved DELAY
EVTSTAT
3-1
OMODE
LOCK
End of Table 7-47
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7.2.3.19 Device Speed (DEVSPEED) Register
The Device Speed Register shows the device speed grade and is shown below.
Figure 7-30
31 Reserved R-n Legend: R = Read only; -n = value after reset
Device Speed Register (DEVSPEED)

28 27 DEVSPEED 16 15 Reserved R-n 12 11 ARMSPEED 0
Table 7-1
Bit Field
Device Speed Register Field Descriptions

Description Reserved. Read only Indicates the speed of the device (read only) 0b0000 0000 0000 = 800 MHz 0b0000 0000 0001 = 1000 MHz 0b0000 0000 001x = 1200 MHz 0b0000 0000 01xx = Reserved 0b0000 0000 1xxx = Reserved 0b0000 0001 xxxx = Reserved 0b0000 001x xxxx = Reserved 0b0000 01xx xxxx = Reserved 0b0000 1xxx xxxx = 1200 MHz 0b0001 xxxx xxxx= 1000 MHz 0b001x xxxx xxxx = 800 MHz Reserved. Read only Indicates the speed of the ARM (read only) 0b0000 0000 0000 = 800 MHz 0b0000 0000 0001 = 1000 MHz 0b0000 0000 001x = 1200 MHz (1) 0b0000 0000 01xx = 1350 MHz (1) 0b0000 0000 1xxx = 1400 MHz 0b0000 0001 xxxx = Reserved (1) 0b0000 001x xxxx = 1400 MHz (1) 0b0000 01xx xxxx = 1350.8 MHz 0b0000 1xxx xxxx = 1200 MHz 0b0001 xxxx xxxx= 1000 MHz 0b001x xxxx xxxx = 800 MHz
PRODUCT PREVIEW
31-28 27-16
Reserved DEVSPEED
15-12 11-0
Reserved ARMSPEED
End of Table 7-0

1 Possible future support
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7.2.3.20 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
The registers defined in ARM Configuration Register 0 (ARMENDIAN_CFGr_0) and ARM Configuration Register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is shown.)
Figure 7-1
31 BASEADDR RW, +0000 0000 0000 0000 0000 0000 Legend: RW = Read/Write; -n = value after reset
ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7

8 7 Reserved R,+0000 0000 0
Table 7-1
Bit 31-8 Field
ARM Endian Configuration Register 0 Field Descriptions

Description 24-bit Base Address of Configuration Region R This base address defines the start of a contiguous block of Memory Mapped Register space for which a word swap is done by the ARM CorePac bridge.
BASEADDR
7-0
Reserved
Reserved
End of Table 7-1

Figure 7-2
31 Reserved R, +0000 0000 0000 0000 0000 0000 0000 Legend: RW = Read/Write; -n = value after reset

4 3 SIZE RW,+0000 0
Table 7-2
Bit 31-4 3-0 Field

Description Reserved 4-bit encoded size of Configuration Region R The value in the SIZE field defines the size of the contiguous block of Memory Mapped Register space for which a word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR). 0000 : 64KB 0001 : 128KB 0010 : 256KB 0011 : 512KB 0100 : 1MB 0101 : 2MB 0110 : 4MB 0111 : 8MB 1000 : 16MB 1001 : 32MB 1010 : 64MB 1011 : 128MB Others : Reserved
Reserved SIZE
End of Table 7-2
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The registers defined in ARM Configuration Register 2 (ARMENDIAN_CFGr_2) enable the word swapping of a region.
Figure 7-3

1 0 DIS RW,+0
Table 7-3

Description Reserved Disabling the word swap of a region 0 : Enable word swap for region 1 : Disable word swap for region
PRODUCT PREVIEW
Bit 31-1 0
Field Reserved DIS
End of Table 7-3
7.2.3.23 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register

Figure 7-4
31 19
Chip Miscellaneous Control Register (CHIP_MISC_CTL0)

18 17 16 AET_MUXSEL0 RW,+0 15 Reserved RW,+0 14 RAC23_DIS RW,+0 13 RAC01_DIS RW,+0 12 MSMC_BLOCK_PARITY _RST RW,+0 11 3 2 0
Reserved R, + 0000 0000 0000
USB_PM AETMUX E_EN SEL1 RW,+0 RW,+0
Reserved RW,+0
QM_PRIORITY RW,+0
Table 7-4
Bit 31-19 18 Field
Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions (Part 1 of 2)

Description Reserved. Enables wakeup event generation from USB 0 = Disable PME event generation 1 = Enable PME event generation Controls the mux that selects whether an AET event from EDMA CC2 or EDMA CC3 is connected to the C66x Interrupt Controller 0 = EDMA CC2 (default) 1 = EDMA CC3 Controls the mux that selects whether an AET event from EDMA CC2 or EDMA CC4 is connected to the C66x Interrupt Controller 0 = EDMA CC2 (default) 1 = EDMA CC4
Reserved USB_PME_EN
17
AETMUXSEL1
16
AETMUXSEL0
15-14 13
Reserved RAC01_DIS Controls RAC broadcaster indicates presence/absence of RAC 0/1 1 = RAC is Disabled 0 = RAC is Enabled Controls MSMC parity RAM reset. When set to 1 means the MSMC parity RAM will not be reset.
12
MSMC_BLOCK_PARITY_RST
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SPRS835DAugust 2013 Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions (Part 2 of 2)
Description Reserved Control the priority level for the transactions from QM_Master port, which access the external linking RAM.
Table 7-4
Bit 11-3 2-0 Field
Reserved QM_PRIORITY
End of Table 7-4
7.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register

Figure 7-5
31 Reserved R, + 0000 0000 00000000
Chip Miscellaneous Control Register (CHIP_MISC_CTL1)

15 14 IO_TRACE_SEL RW,+0 13 ARM_PLL_EN RW,+0 12 Reserved 0
Table 7-5
Bit 31-15 14 Field
Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions

Description Reserved. This bit controls the pin muxing of GPIO[31:17] and EMU[33:19] pin 0 = GPIO[31:17] is selected 1 = EMU[33:19] pins is selected This bit controls the glitchfree clock mux between bypass clock and ARM PLL output clock 0 = Bypass clock (default) 1 = PLL output clock
Reserved IO_TRACE_SEL
13
ARM_PLL_EN
12-0
Reserved
End of Table 7-5
7.2.3.25 System Endian Status Register (SYSENDSTAT)
This register provides a way for reading the system endianness in an endian-neutral way. A zero value indicates big endian and a non-zero value indicates little endian. The SYSENDSTAT register captures the LENDIAN bootmode pin and is used by the BOOTROM to guide the bootflow. The value is latched on the rising edge of POR or RESETFULL.
Figure 7-6
System Endian Status Register

1 0 SYSENDSTAT R,+0
Table 7-6
Bit 31-1 0 Field
System Endian Status Register Descriptions

Description Reserved Reflects the same value as the LENDIAN bit in the DEVSTAT register. 0 - C66x/System is in Big Endian 1 - C66x/System is in Little Endian
Reserved SYSENDSTAT
End of Table 7-6
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RW,+0000000000000

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7.2.3.26 SYNECLK_PINCTL Register
This register controls the routing of recovered clock signals from any Ethernet port (SGMII of the multiport switches) to the two clock outputs TSRXCLKOUT0/TSRXCLKOUT1.
Figure 7-7
31 Reserved R, +0000 0000 0000 0000 0000 0000 0 Legend: RW = Read/Write; -n = value after reset
SYNECLK_PINCTL Register
7 6 TSRXCLKOUT1SEL RW,+0 4 3 Reserved 2 TSRXCLKOUT0SEL RW,+0 0
Table 7-7
Bit 31-7 6-4 Field
SYNECLK_PINCTL Register Descriptions

Description
PRODUCT PREVIEW
Reserved TSRXCLKOUT1SEL 000 = SGMII Lane 0 rxbclk 001 = SGMII Lane 1 rxbclk 010 = SGMII Lane 2 rxbclk 011 = SGMII Lane 3 rxbclk 100 = Reserved. Do not write. 101 = Reserved. Do not write. 110 = Reserved. Do not write. 111 = Reserved. Do not write.
3 2-0
Reserved TSRXCLKOUT0SEL 000 = SGMII Lane 0 rxbclk 001 = SGMII Lane 1 rxbclk 010 = SGMII Lane 2 rxbclk 011 = SGMII Lane 3 rxbclk 100 = Reserved. Do not write. 101 = Reserved. Do not write. 110 = Reserved. Do not write. 111 = Reserved. Do not write.
End of Table 7-7
7.2.3.27 USB PHY Control (USB_PHY_CTLx) Registers
These registers control the USB PHY. See the USB3 for KeyStone II Devices User Guide for more details.
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8 Device Operating Conditions

8.1 Absolute Maximum Ratings
Table 8-1 Absolute Maximum Ratings (1)
CVDD CVDDT CVDD1 CVDDT1 DVDD15 DVDD18 DVDD33 DDR3VREFSSTL Supply voltage range (2): VDDAHV VDDALV VDDUSB AVDDA1, AVDDA2, AVDDA3,AVDDA4, AVDDA5 AVDDA6, AVDDA7 AVDDA8, AVDDA9, AVDDA10 AVDDA11, AVDDA12, AVDDA13 AVDDA14, AVDDA15 VSS Ground LVCMOS (1.8 V) DDR3A, DDR3B IC Input voltage (VI) range: LVDS LJCB SerDes USB LVCMOS (1.8 V) DDR3A, DDR3B Output voltage (VO) range: IC SerDes USB Operating case temperature range, TC: ESD stress voltage, VESD
(3) 2 2
Over Operating Case Temperature Range (Unless Otherwise Noted) -0.3 V to 1.3 V -0.3 V to 1.3 V -0.3 V to 1.3 V -0.3 V to 1.3 V -0.3 V to 2.45 V -0.3 V to 2.45 V
0.49 DVDD15 to 0.51 DVDD15 -0.3 V to 2.45 V -0.3 V to 1.3 V -0.3V to 0.89 V -0.3 V to 2.45 V -0.3 V to 2.45 V
0V -0.3 V to DVDD18+0.3 V -0.3 V to 2.45 V -0.3 V to 2.45 V -0.3 V to DVDD18+0.3 V -0.3 V to 1.3 V -0.3 V to VDDAHV1+0.3 V 3.3 V -0.3 V to DVDD18+0.3 V -0.3 V to 2.45 V -0.3 V to 2.45 V -0.3 V to VDDAHV+0.3 V 3.3 V 0C to 85C -40C to 100C 1000 V
(5)
Commercial Extended HBM (human body model) (4) CDM (charged device model) LVCMOS (1.8 V)
250 V 20% overshoot/undershoot for 20% of signal duty cycle -65C to 150C
Overshoot/undershoot (6)
DDR3A, DDR3B IC
2
Storage temperature range, Tstg: End of Table 8-1
1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 All voltage values are with respect to VSS.
Device Operating Conditions
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3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. 4 Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance. 5 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance. 6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is DVDD18 + 0.20 DVDD18 and maximum undershoot value would be VSS - 0.20 DVDD18
8.2 Recommended Operating Conditions

Table 8-2 Recommended Operating Conditions (1)
(2)
Min Initial CVDD SR DSP core supply 1000MHz Device 1200MHz Device Initial CVDDT SR Cortex-A15 processor core supply 1000MHz Device 1200MHz Device CVDD1 CVDDT1 DVDD18 DVDD15 DSP Core supply Cortex-A15 processor Core supply 1.8-V supply I/O voltage 1.5-V supply I/O voltage 0.95 SRVnom*0.95 (3) SRVnom*0.95
(3)
Nom 1.0 0.8-1.1 0.8-1.1 1.0 0.8-1.1 0.8-1.1 0.95 0.95 1.8 1.5 0.5 DVDD15 1.8 1.8 0.85 3.3 0.85
Max Unit 1.05 SRVnom*1.05 SRVnom*1.05 1.05 SRVnom*1.05 SRVnom*1.05 0.997 0.997 1.89 1.575 0.51 DVDD15 1.89 1.89 0.892 3.465 V V V V V V V V V V V V V V V V 0 V V V
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0.95 SRVnom*0.95 (3) SRVnom*0.95

(3)
0.902 0.902 1.71 1.425 0.49 DVDD15 1.71 1.71 0.807 3.135
DDR3VREFSSTL DDR3A, DDR3B reference voltage VDDAHV AVDDx VDDALH DVDD33 VDDUSB VSS VIH SerDes regulator supply PLL analog, DDR DLL supply SerDes termination supply USB USB Ground LVCMOS (1.8 V) High-level input voltage IC USB DDR3A, DDR3B EMIF LVCMOS (1.8 V) VIL Low-level input voltage DDR3A, DDR3B EMIF USB IC TC End of Table 8-2 Operating case temperature Commercial Extended
2 2
0 0.65 DVDD18 0.7 DVDD18
3.3 VREFSSTL + 0.1 0.35 DVDD18 -0.3 3.3 0.3 DVDD18 0 -40 100 100 VREFSSTL - 0.1
V V V V V V C C
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002. 2 All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002. 3 SRVnom refers to the unique SmartReflex core supply voltage between 0.8 V and 1.1 V set from the factory for each individual device.
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8.3 Electrical Characteristics

Table 8-3 Electrical Characteristics
Parameter LVCMOS (1.8 V) VOH High-level output voltage DDR3A, DDR3B USB IC
2 (2)
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) Test Conditions IO = IOH
(1)
Min DVDD18 - 0.45 DVDD15 - 0.4
Typ
Max Unit
3.3
LVCMOS (1.8 V) VOL Low-level output voltage DDR3A, DDR3B USB I2 C
IO = IOL
0.45 0.4 TBD V
No IPD/IPU LVCMOS (1.8 V) II

(3)
-10 50 -170 TBD 100 -100 TBD
10 170 -50 TBD 10 -6 -8 mA A A
Internal pullup Internal pulldown
Input current [DC] USB I2 C LVCMOS (1.8 V)
0.1 DVDD18 V < VI < 0.9 DVDD18 V
-10
IOH
High-level output current [DC] DDR3A, DDR3B IC

2 (4)
LVCMOS (1.8 V) IOL Low-level output current [DC] DDR3A, DDR3B IC LVCMOS (1.8 V) IOZ
(5) 2
6 8 3 -10 -10 -10 10 10 10 A mA
Off-state output current [DC]
DDR3A, DDR3B IC
2
End of Table 8-3

1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. 2 2 I C uses open collector IOs and does not have a VOH Minimum. 3 II applies to input-only pins and bidirectional pins. For input-only pins, II indicates the input leakage current. For bidirectional pins, II includes input leakage current and off-state (Hi-Z) output leakage current. 4 I2C uses open collector IOs and does not have a IOH Maximum. 5 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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IO = 3 mA, pulled up to 1.8 V
0.4

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8.4 Power Supply to Peripheral I/O Mapping

Table 8-4 Power Supply to Peripheral I/O Mapping
Power Supply
(1) (2)
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) I/O Buffer Type Associated Peripheral SYSCLK(P|N) PLL input buffer ALTCORECLK(P|N) PLL input buffer SRIOSGMIICLK(P|N) SerDes PLL input buffer CVDD Supply core voltage LJCB DDR3ACLK(P|N) PLL input buffer DDR3BCLK(P|N) PLL input buffer PASSCLK(P|N) PLL input buffer ARMCLK(P|N) PLL input buffer
PRODUCT PREVIEW
VDDALV
LJCB
SERDES low voltage PCIECLK(P|N) SerDes Clock Reference HYP0CLK(P|N) SerDes Clock Reference
VDDAHV
SerDes IO voltage
SerDes/CML
HYP1CLK(P|N) SerDes USBCLK(P|N) SerDes XFICLK(P|N) SerDes
DVDD15
1.5-V supply I/O voltage
DDR3A, DDR3B (1.5 V) All DDR3A, DDR3B memory controller peripheral I/O buffer All GPIO peripheral I/O buffer All JTAG and EMU peripheral I/O buffer All TIMER peripheral I/O buffer All SPI peripheral I/O buffer
DVDD18
1.8-V supply I/O voltage
LVCMOS (1.8 V)
All RESETs, NMI, control peripheral I/O buffer All SmartReflex peripheral I/O buffer All Hyperlink sideband peripheral I/O buffer All MDIO peripheral I/O buffer All UART peripheral I/O buffer
2
Open-drain (1.8 V) End of Table 8-4
All I C peripheral I/O buffer
1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers. 2 Please see the Hardware Design Guide for KeyStone Devices in 1.10 Related Documentation from Texas Instruments on page 21 for more information about individual peripheral I/O.
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9 TCI6636K2H Peripheral Information and Electrical Specifications

This chapter covers the various peripherals on the TCI6636K2H device. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.
9.1 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9.2 Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the TCI6636K2H. The various power supply rails and their primary functions are listed in Table 9-1.
Name AVDDAx CVDD CVDD1 CVDDT1 CVDDT DVDD15 DVDD18 DVDD33 VDDA18 VDDAHV VDDALV VDDUSB VP, VPTX VSS End of Table 9-1 Primary Function Core PLL, DDR3 DLL supply voltage SmartReflex DSP core supply voltage DSP core fixed supply voltage ARM core fixed supply voltage SmartReflex ARM core supply voltage DDR3A, DDR3B I/O power supply voltage 1.8-V I/O power supply voltage USB 3.3-V IO supply PLL supply voltage SerDes I/O power supply voltage SerDes analog power supply voltage USB LV PHY power supply voltage Filtered 0.85-V supply voltage Ground Voltage 1.8 V 0.8 - 1.1 V 0.95 V 0.95 V 0.8 - 1.1 V 1.5 V 1.8 V 3.3 V 1.8 V 1.8 V 0.85 V 0.85 V 0.85 V GND Notes Core PLL, DDR3 DLL supply DSP variable core supply DSP Core fixed supply ARM core fixed supply ARM variable core supply DDR3A, DDR3B I/O power supply 1.8-V I/O power supply USB high voltage supply PLL supplies SerDes I/O power supply SerDes analog supply USB LV PHY supply Filtered 0.85-V USB supply Ground
TCI6636K2H Peripheral Information and Electrical Specifications
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Table 9-1
Power Supply Rails on the TCI6636K2H

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9.2.1 Power-Up Sequencing This section defines the requirements for a power-up sequencing from a power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below. 1. CVDD/CVDDT 2. CVDD1, CVDDT1, VDDAHV, AVDDAx, DVDD18 3. DVDD15 4. VDDALV, VDDUSB 5. DVDD33 The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below. 1. VDDAHV, AVDDAx, DVDD18 2. CVDD/CVDDT 3. CVDD1, CVDDT1 4. DVDD15 5. VDDALV, VDDUSB 6. DVDD33 The clock input buffers for SYSCLK, ARMCLK, ALTCORECLK, DDR3ACLK, DDR3BCLK, PASSCLK, and SRIOSGMIICLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD/CVDDT are at a valid voltage level. Driving these clock inputs high before CVDD/CVDDT are valid could cause damage to the device. Once CVDD/CVDDT are valid, it is acceptable that the P and N legs of these clocks may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDD/CVDDT are present. If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled to ground through a 1-k resistor. The P leg should be tied to CVDD/CVDDT to ensure it will not have any voltage present until CVDD/CVDDT areactive. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device. The device initialization is divided into two phases. The first phase consists of the time period from the activation of the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire power stabilization phase. This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL triggers the end of the initialization phase, but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock that is used by the C66x CorePacs. See Figure 9-7 for more details.
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9.2.1.1 Core-Before-IO Power Sequencing
The details of the Core-before-IO power sequencing are defined in Table 9-2. Figure 9-1 shows power sequencing and reset control of the TCI6636K2H. POR may be removed after the power has been stable for the required 100 sec. RESETFULL must be held low for a period (see item 9 in Figure 9-1) after the rising edge of POR, but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed.
NoteTI recommends a maximum of 80 ms between one power rail being valid and the next power rail in
the sequence starting to ramp.
Item 1
System State Begin Power Stabilization Phase CVDD/ CVDDT (core AVS) ramp up. POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous reset (created from POR ) is put into the reset state. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. CVDD1 and CVDDT1 (core constant) ramp at the same time or within 80 ms of CVDD. Although ramping CVDD1 and CVDDT1 simultaneously with CVDD/CVDDT is permitted, the voltage for CVDD1 and CVDDT1 must never exceed CVDD until after CVDD has reached a valid voltage. The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 and CVDDT1 should trail CVDD as this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 and CVDDT1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1 and CVDDT1. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. The timing for CVDD1 and CVDDT1 is based on CVDD/CVDDT valid. CVDD1 and CVDDT1 and DVDD18/ADDAVH/AVDDAx may be enabled at the same time but do not need to ramp simultaneously. CVDD1 and CVDDT1 may be valid before or after DVDD18/ADDAVH/AVDDAx is valid, as long as the timing above is met. VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD/CVDDT. DVDD18 must be enabled within 80 ms of CVDD/CVDDT valid and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100 ms from the time when CVDD/CVDDT are valid to the time when DVDD18 is valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD/CVDDT valid. DVDD18/ADDAVH/AVDDAx and CVDD1 and CVDDT1 may be enabled at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after CVDD1 and CVDDT1 are valid, as long as the timing above is met. Once CVDD/CVDDT are valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low. The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD/CVDDT are at a valid level and the setup time before POR goes high specified by item 7. DVDD15 can ramp up within 80ms of when DVDD18 is valid. RESETSTAT is driven low once the DVDD18 supply is available. All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high. VDDALV, VDDUSB, VP and VPTX ramp up within 80ms of when DVDD15 is valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. DVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSB, VP and VPTX are valid. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. POR must continue to remain low for at least 100 s after all power rails have stabilized. End power stabilization phase Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 s is required before a rising edge of POR. The clock must be active during the entire 16 s.
2a
2b
2c 2d 3
3a 4 5 6 7
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Table 9-2
Core Before IO Power Sequencing (Part 1 of 2)

Item 8 9
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Core Before IO Power Sequencing (Part 2 of 2)

System State RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level. The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin. Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles. End device initialization phase GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL. GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
10 11
End of Table 9-2
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Power Stabilization Phase Device Initialization Phase
Figure 9-1
POR 8 RESETFULL 9 Configuration Inputs
RESET 1 2d
CVDD CVDDT 2a CVDD1 CVDDT1
2
VDDAHV AVDDAx DVDD18
2b 3a 3
DVDD15 4
VDDALV VDDUSB 5
DVDD33 7 SYSCLK1 2c
DDRCLKOUT
RESETSTAT
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9.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 9-2 and defined in Table 9-3.
NoteTI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp.

Table 9-3
Time 1
IO-Before-Core Power Sequencing

System State Begin Power Stabilization Phase Because POR is low, all the core logic having asynchronous reset (created from POR) are put into the reset state once the core supply ramps up. POR must remain low through the power stabilization phase. The VDDAHV, AVDDAx, and DVDD18 can ramp simultaneously. RESETSTAT is driven low once the DVDD18 supply is available. All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is stable could cause damage to the device. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. DVDD15 (1.5 V) supply is ramped up following DVDD18. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. RESET may be driven high any time after DVDD18 is at a valid level. CVDD/CVDDT (core AVS) supply ramp up following DVDD15. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. The DDR3ACLK, DDR3BCLK and SYSCLK1 may begin to toggle anytime between when CVDD/CVDDT are at a valid level and the setup time before POR goes high specified by t6. CVDD1 and CVDDT1 (core constant) ramp at the same time or following CVDD/CVDDT. Although ramping CVDD1 and CVDDT1 and CVDD/CVDDT simultaneously is permitted, the voltage for CVDD1 and CVDDT1 must never exceed CVDD/CVDDT until after CVDD/CVDDT have reached a valid voltage. The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 and CVDDT1 should trail CVDD/CVDDT as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 and CVDDT1 (core constant) ramp up before CVDD/CVDDT (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1 and CVDDT1. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. Once CVDD/CVDDT are valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should be driven either with a valid clock or held in a static state with one leg high and one leg low. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. VDDALV and VDDUSB are ramping following CVDD1 and CVDDT1. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. DVDD33 supply is ramping up following VDDALV and VDDUSB. Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less. POR must continue to remain low for at least 100 s after all power rails have stabilized. End power stabilization phase Begin Device Initialization Device initialization requires 500 SYSCLK1 periods after the power stabilization phase. The maximum clock period is 33.33 nsec so a delay of an additional 16 s is required before a rising edge of POR. The clock must be active during the entire 16 s. POR must remain low. RESETFULL is held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level. The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin. Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay is 10000 to 50000 clock cycles. End device initialization phase GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL. GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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2 2a 3 3a 4
4a
5 6 7 8
9 10
11 12
End of Table 9-3
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Power Stabilization Phase POR 9 Device Initialization Phase
Figure 9-2
RESETFULL 10 Configuration Inputs 2a RESET 1
VDDAHV AVDDAx DVDD18 2
3b
CVDD CVDDT 3
CVDD1 CVDDT1 4
DVDD15 5
VDDALV VDDUSB 7 6
DVDD33 8 3a SYSCLK1
DDRCLKOUT
RESETSTAT
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9.2.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time may affect the long-term reliability of the part (due to an elevated voltage condition that can stress the part). The device should not be held in a reset for times exceeding one hour at a time and no more than 5% of the total lifetime for which the device is powered-up. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the device to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.
9.2.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the clocks is contingent on the state of the boot configuration pins. Table 9-4 describes the clock sequencing and the conditions that affect clock operation. Note that all clock drivers should be in a high-impedance state until CVDD is at a valid level and that all clock inputs be either active or in a static state with one leg pulled to ground and the other connected to CVDD.
Table 9-4
Clock DDR3ACLK DDR3BCLK SYSCLK
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Clock Sequencing
Condition None None CORECLKSEL = 0 CORECLKSEL = 1 CORECLKSEL = 0 CORECLKSEL = 1 PASSCLKSEL = 0 Sequencing Must be present 16 sec before POR transitions high. Must be present 16 sec before POR transitions high. SYSCLK is used to clock the core PLL. It must be present 16 sec before POR transitions high. SYSCLK is used only for AIF2. Clock must be present before the reset to the AIF2 is removed. Reserved. ALTCORECLK is not used and should be tied to a static state. ALTCORECLK is used to clock the core PLL. It must be present 16 sec before POR transitions high. PASSCLK is not used and should be tied to a static state. PASSCLK is used as a source for the PASS PLL. It must be present before the PASS PLL is removed from reset and programmed. SRIOSGMIICLK must be present 16 sec before POR transitions high.
ALTCORECLK
PASSCLK
PASSCLKSEL = 1 An SGMII port will be used.
SGMII will not be used. SRIO SRIOSGMIICLK must be present 16 sec before POR transitions high. will be used as a boot device. SRIOSGMIICLK SGMII will not be used. SRIO will be used after boot. SGMII will not be used. SRIO will not be used. PCIE will be used as a boot device. PCIECLK PCIE will be used after boot. PCIE will not be used. HyperLink will be used as a boot device. HYPCLK HyperLink will be used after boot. HyperLink will not be used. End of Table 9-4 SRIOSGMIICLK is used as a source to the SRIO SerDes PLL. It must be present before the SRIO is removed from reset and programmed. SRIOSGMIICLK is not used and should be tied to a static state. PCIECLK must be present 16 sec before POR transitions high. PCIECLK is used as a source to the PCIE SerDes PLL. It must be present before the PCIe is removed from reset and programmed. PCIECLK is not used and should be tied to a static state. HYPCLK must be present 16 sec before POR transitions high. HYPCLK is used as a source to the HyperLink SerDes PLL. It must be present before the HyperLink is removed from reset and programmed. HYPCLK is not used and should be tied to a static state.
9.2.2 Power-Down Sequence The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent an excessive amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

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A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can affect long term reliability. 9.2.3 Power Supply Decoupling and Bulk Capacitors To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of power supply decoupling and bulk capacitors see the Hardware Design Guide for KeyStone II Devices (currently in development). 9.2.4 SmartReflex
Texas Instruments SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the TCI6636K2H device is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each TCI6636K2H device. To help maximize performance and minimize power consumption of the device, SmartReflex is required to be implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins (depending on power supply device being used), which are used to select the output voltage of the core voltage regulator. For information on implementation of SmartReflex see the DSP Power Consumption Summary for KeyStone Devices Application Report and the Hardware Design Guide for KeyStone II Devices (in development).
Table 9-5
(see Figure 9-3) No. 1 2 3 4 td(VCNTL[2:0]-VCNTL[3]) Parameter Delay time - VCNTL[2:0] valid after VCNTL[3] low 0.07 Min Max 300.00 172020C
(1)
SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics

Unit ns ms ns ms
toh(VCNTL[3]-VCNTL[2:0]) Output hold time - VCNTL[2:0] valid after VCNTL[3] td(VCNTL[2:0]-VCNTL[3]) toh(VCNTL[3]-VCNTL[2:0) Delay time - VCNTL[2:0] valid after VCNTL[3] high Output hold time - VCNTL[2:0] valid after VCNTL[3] high
300.00 0.07 172020C
End of Table 9-5

1 C = 1/SYSCLK1 frequency (See Figure 9-9)in ms
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Increasing the device complexity increases its power consumption. With higher clock rates and increased performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in any powered circuit, independent of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, which is the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.

SPRS835DAugust 2013 Figure 9-3 SmartReflex 4-Pin 6-bit VID Interface Timing
4 VCNTL[3] 1 VCNTL[2:0] 2 LSB VID[2:0] 3 MSB VID[5:3]
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9.3 Power Sleep Controller (PSC)

The Power Sleep Controller (PSC) includes a Global Power Sleep Controller (GPSC) and a number of Local Power Sleep Controllers (LPSC) that control overall device power by turning off unused power domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several important power and clock operations. For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 9.3.1 Power Domains The device has several power domains that can be turned on for operation or off to minimize power dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various power domains. The following table shows the TCI6636K2H power domains.
Table 9-6
Domain 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Power Domains (Part 1 of 2)

Block(s) Most peripheral logic (BOOTCFG, 2 EMIF16, I C, INTC, GPIO, USB, USIM) Per-core TETB and system TETB Network Coprocessor PCIe SRIO HyperLink0 Reserved MSMC RAM C66x Core 0, L1/L2 RAMs C66x Core 1, L1/L2 RAMs C66x Core 2, L1/L2 RAMs C66x Core 3, L1/L2 RAMs C66x Core 4, L1/L2 RAMs C66x Core 5, L1/L2 RAMs C66x Core 6, L1/L2 RAMs C66x Core 7, L1/L2 RAMs EMIF(DDR3A, DDR3B) RAC_0, RAC_1, and TAC Reserved FFTC_0 and FFTC_1 FFTC_2, FFTC_3 AIF2 TCP3d_0, TCP3d_1 Reserved VCP2_0, VCP2_1, VCP2_2, and VCP2_3 Reserved BCP Reserved HyperLink1 Reserved Note Cannot be disabled RAMs can be powered down Logic can be powered down Logic can be powered down Logic can be powered down Logic can be powered down Reserved MSMC RAM can be powered down L2 RAMs can sleep L2 RAMs can sleep L2 RAMs can sleep L2 RAMs can sleep L2 RAMs can sleep L2 RAMs can sleep L2 RAMs can sleep L2 RAMs can sleep Logic can be powered down Logic can be powered down Reserved Logic can be powered down Logic can be powered down RAMs can be powered down RAMs can be powered down Reserved RAMs can be powered down Reserved Logic can be powered down Reserved Logic can be powered down Reserved Software control Software control Reserved Software control Software control Software control Software control Reserved Software control Reserved Software control Reserved Software control Reserved Software control via C66x CorePac. For details, see the C66x CorePac Reference Guide. Power Connection Always on Software control Software control Software control Software control Software control Reserved Software control
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Domain 30 31
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Power Domains (Part 2 of 2)

Block(s) ARM Smart Reflex ARM CorePac Note Logic can be powered down Logic can be powered down Power Connection Software control Software control
End of Table 9-6
9.3.2 Clock Domains Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls the clock gating logic for each module.
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Table 9-7 shows the TCI6636K2H clock domains.

Table 9-7
LPSC Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Clock Domains (Part 1 of 2)

Module(s) Shared LPSC for all peripherals other than those listed in this table Reserved USB EMIF16 Reserved Debug subsystem and tracers Reserved Packet Accelerator Ethernet SGMIIs Security Accelerator PCIe SRIO HyperLink0 SmartReflex MSMC RAM C66x CorePac0 C66x CorePac1 C66x CorePac2 C66x CorePac3 C66x CorePac4 C66x CorePac5 C66x CorePac6 C66x CorePac7 DDR3A EMIF DDR3B EMIF TAC RAC_0 and RAC_1 Reserved FFTC_0 FFTC_1 Notes Always on Reserved Software control Software control Reserved Software control Always on Software control Software control Software control Software control Software control Software control Always on Software control Software control Software control Software control Software control Software control Software control Software control Software control Software control Software control Software control Software control Reserved Software control Software control
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SPRS835DAugust 2013 Clock Domains (Part 2 of 2)

Module(s) FFTC_2 FFTC_3 Reserved Reserved AIF2 TCP3d_0 TCP3d_1 Reserved Reserved VCP2_0 VCP2_1 VCP2_2 VCP2_3 Reserved Reserved Reserved Reserved BCP Reserved HyperLink1 Reserved ARM Smart Reflex ARM CorePac Bootcfg, PSC, and PLL Controller Notes Software control Software control Reserved Reserved Software control Software control Software control Reserved Reserved
Table 9-7
LPSC Number 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 No LPSC End of Table 9-7
Software control Software control Software control Reserved Reserved Reserved Reserved Software control Reserved Software control Reserved Software control Software control These modules do not use LPSC
9.3.3 PSC Register Memory Map Table 9-8 shows the PSC Register memory map.
Table 9-8
Offset 0x000 0x004 - 0x010 0x014 0x018 - 0x11C 0x120 0x124 0x128 0x12C - 0x1FC 0x200 0x204 0x208 0x20C 0x210
PSC Register Memory Map (Part 1 of 5)

Register PID Reserved VCNTLID Reserved PTCMD Reserved PTSTAT Reserved PDSTAT0 PDSTAT1 PDSTAT2 PDSTAT3 PDSTAT4 Description Peripheral Identification Register Reserved Voltage Control Identification Register Reserved Power Domain Transition Command Register Reserved Power Domain Transition Status Register Reserved Power Domain Status Register 0 Power Domain Status Register 1 Power Domain Status Register 2 Power Domain Status Register 3 Power Domain Status Register 4
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Software control

Offset 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C 0x27C - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C
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Register PDSTAT5 PDSTAT6 PDSTAT7 PDSTAT8 PDSTAT9 PDSTAT10 PDSTAT11 PDSTAT12 PDSTAT13 PDSTAT14 PDSTAT15 PDSTAT16 PDSTAT17 PDSTAT18 PDSTAT19 PDSTAT20 PDSTAT21 PDSTAT22 PDSTAT23 PDSTAT24 PDSTAT25 PDSTAT26 PDSTAT27 PDSTAT28 PDSTAT29 PDSTAT30 PDSTAT31 Reserved PDCTL0 PDCTL1 PDCTL2 PDCTL3 PDCTL4 PDCTL5 PDCTL6 PDCTL7 PDCTL8 PDCTL9 PDCTL10 PDCTL11 PDCTL12 PDCTL13 PDCTL14 PDCTL15 Description Power Domain Status Register 5 Power Domain Status Register 6 Power Domain Status Register 7 Power Domain Status Register 8 Power Domain Status Register 9 Power Domain Status Register 10 Power Domain Status Register 11 Power Domain Status Register 12 Power Domain Status Register 13 Power Domain Status Register 14 Power Domain Status Register 15 Power Domain Status Register 16 Power Domain Status Register 17 Power Domain Status Register 18 Power Domain Status Register 19 Power Domain Status Register 20 Power Domain Status Register 21 Power Domain Status Register 22 Power Domain Status Register 23 Power Domain Status Register 24 Power Domain Status Register 25 Power Domain Status Register 26 Power Domain Status Register 27 Power Domain Status Register 28 Power Domain Status Register 29 Power Domain Status Register 30 Power Domain Status Register 31 Reserved Power Domain Control Register 0 Power Domain Control Register 1 Power Domain Control Register 2 Power Domain Control Register 3 Power Domain Control Register 4 Power Domain Control Register 5 Power Domain Control Register 6 Power Domain Control Register 7 Power Domain Control Register 8 Power Domain Control Register 9 Power Domain Control Register 10 Power Domain Control Register 11 Power Domain Control Register 12 Power Domain Control Register 13 Power Domain Control Register 14 Power Domain Control Register 15
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SPRS835DAugust 2013 PSC Register Memory Map (Part 3 of 5)

Register PDCTL16 PDCTL17 PDCTL18 PDCTL19 PDCTL20 PDCTL21 PDCTL22 PDCTL23 PDCTL24 PDCTL25 PDCTL26 PDCTL27 PDCTL28 PDCTL29 PDCTL30 PDCTL31 Reserved MDSTAT0 MDSTAT1 MDSTAT2 MDSTAT3 MDSTAT4 MDSTAT5 MDSTAT6 MDSTAT7 MDSTAT8 MDSTAT9 MDSTAT10 MDSTAT11 MDSTAT12 MDSTAT13 MDSTAT14 MDSTAT15 MDSTAT16 MDSTAT17 MDSTAT18 MDSTAT19 MDSTAT20 MDSTAT21 MDSTAT22 MDSTAT23 MDSTAT24 MDSTAT25 MDSTAT26 Description Power Domain Control Register 16 Power Domain Control Register 17 Power Domain Control Register 18 Power Domain Control Register 19 Power Domain Control Register 20 Power Domain Control Register 21 Power Domain Control Register 22 Power Domain Control Register 23 Power Domain Control Register 24
Table 9-8
Offset 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35c 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C 0x380 - 0x7FC 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 0x81C 0x820 0x824 0x828 0x82C 0x830 0x834 0x838 0x83C 0x840 0x844 0x848 0x84C 0x850 0x854 0x858 0x85C 0x860 0x864 0x868
Power Domain Control Register 26 Power Domain Control Register 27 Power Domain Control Register 28 Power Domain Control Register 29 Power Domain Control Register 30 Power Domain Control Register 31 Reserved Module Status Register 0 (never gated) Module Status Register 1 Module Status Register 2 Module Status Register 3 Module Status Register 4 Module Status Register 5 Module Status Register 6 Module Status Register 7 Module Status Register 8 Module Status Register 9 Module Status Register 10 Module Status Register 11 Module Status Register 12 Module Status Register 13 Module Status Register 14 Module Status Register 15 Module Status Register 16 Module Status Register 17 Module Status Register 18 Module Status Register 19 Module Status Register 20 Module Status Register 21 Module Status Register 22 Module Status Register 23 Module Status Register 24 Module Status Register 25 Module Status Register 26
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Power Domain Control Register 25

Offset 0x86C 0x870 0x874 0x878 0x87C 0x880 0x884 0x888 0x88C 0x890 0x894 0x898 0x89C 0x8A0 0x8A4 0x8A8 0x8AC 0x8B0 0x8B4 0x8B8 0x8BC 0x8C0 0x8C4 0x8C8 0x8CC 0x8D0 0x8D4 - 0x9FC 0xA00 0xA04 0xA08 0xA0C 0xA10 0xA14 0xA18 0xA1C 0xA20 0xA24 0xA28 0xA2C 0xA30 0xA34 0xA38 0xA3C 0xA40
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Register MDSTAT27 MDSTAT28 MDSTAT29 MDSTAT30 MDSTAT31 MDSTAT32 MDSTAT33 MDSTAT34 MDSTAT35 MDSTAT36 MDSTAT37 MDSTAT38 MDSTAT39 MDSTAT40 MDSTAT41 MDSTAT42 MDSTAT43 MDSTAT44 MDSTAT45 MDSTAT46 MDSTAT47 MDSTAT48 MDSTAT49 MDSTAT50 MDSTAT51 MDSTAT52 Reserved MDCTL0 MDCTL1 MDCTL2 MDCTL3 MDCTL4 MDCTL5 MDCTL6 MDCTL7 MDCTL8 MDCTL9 MDCTL10 MDCTL11 MDCTL12 MDCTL13 MDCTL14 MDCTL15 MDCTL16 Description Module Status Register 27 Module Status Register 28 Module Status Register 29 Module Status Register 30 Module Status Register31 Module Status Register 32 Module Status Register 33 Module Status Register 34 Module Status Register 35 Module Status Register 36 Module Status Register 37 Module Status Register 38 Module Status Register 39 Module Status Register 40 Module Status Register 41 Module Status Register 42 Module Status Register 43 Module Status Register 44 Module Status Register 45 Module Status Register 46 Module Status Register 47 Module Status Register 48 Module Status Register 49 Module Status Register 50 Module Status Register 51 Module Status Register 52 Reserved Module Control Register 0 (never gated) Module Control Register 1 Module Control Register 2 Module Control Register 3 Module Control Register 4 Module Control Register 5 Module Control Register 6 Module Control Register 7 Module Control Register 8 Module Control Register 9 Module Control Register 10 Module Control Register 11 Module Control Register 12 Module Control Register 13 Module Control Register 14 Module Control Register 15 Module Control Register 16
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SPRS835DAugust 2013 PSC Register Memory Map (Part 5 of 5)

Register MDCTL17 MDCTL18 MDCTL19 MDCTL20 MDCTL21 MDCTL22 MDCTL23 MDCTL24 MDCTL25 MDCTL26 MDCTL27 MDCTL28 MDCTL29 MDCTL30 MDCTL31 MDCTL32 MDCTL33 MDCTL34 MDCTL35 MDCTL36 MDCTL37 MDCTL38 MDCTL39 MDCTL40 MDCTL41 MDCTL42 MDCTL43 MDCTL44 MDCTL45 MDCTL46 MDCTL47 MDCTL48 MDCTL49 MDCTL50 MDCTL51 MDCTL52 Reserved Description Module Control Register 17 Module Control Register 18 Module Control Register 19 Module Control Register 20 Module Control Register 21 Module Control Register 22 Module Control Register 23 Module Control Register 24 Module Control Register 25
Table 9-8
Offset 0xA44 0xA48 0xA4C 0xA50 0xA54 0xA58 0xA5C 0xA60 0xA64 0xA68 0xA6C 0xA70 0xA74 0xA78 0xA7C 0xA80 0xA84 0xA88 0xA8C 0xA90 0xA94 0xA98 0xA9C 0xAA0 0xAA4 0xAA8 0xAAC 0xAB0 0xAB4 0xAB8 0xABC 0xAC0 0xAC4 0xAC8 0xACC 0xAD0 0xAD4 - 0xFFC End of Table 9-8
Module Control Register 27 Module Control Register 28 Module Control Register 29 Module Control Register 30 Module Control Register31 Module Control Register 32 Module Control Register 33 Module Control Register 34 Module Control Register 35 Module Control Register 36 Module Control Register 37 Module Control Register 38 Module Control Register 39 Module Control Register 40 Module Control Register 41 Module Control Register 42 Module Control Register 43 Module Control Register 44 Module Control Register 45 Module Control Register 46 Module Control Register 47 Module Control Register 48 Module Control Register 49 Module Control Register 50 Module Control Register 51 Module Control Register 52 Reserved
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Module Control Register 26

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9.4 Reset Controller

The reset controller detects the different type of resets supported on the TCI6636K2H device and manages the distribution of those resets throughout the device. The device has the following types of resets: Power-on reset Hard reset Soft reset Local reset Table 9-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more information on the effects of each reset on the PLL controllers and their clocks, see Section 9.4.8 Reset Electrical Data/Timing on page 285.
Table 9-9
Type Power-on reset
Reset Types
Initiator POR pin RESETFULL pin RESET pin Effect(s) Resets the entire chip including the test and emulation logic. The device configuration pins are latched only during power-on reset. Hard reset resets everything except for test, emulation logic, and reset isolation modules. This reset is different from power-on reset in that the PLL Controller assumes power and clocks are stable when a hard reset is asserted. The device configurations pins are not relatched. Emulation-initiated reset is always a hard reset. By default, these initiators are configured as hard reset, but can be configured (except emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in self-refresh mode. Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and DDR3 EMIF MMRs contents are retained. By default, these initiators are configured as hard reset, but can be configured as soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained during a soft reset if the SDRAM is placed in self-refresh mode. Resets the C66x CorePac, without disturbing clock alignment or memory contents. The device configuration pins are not relatched.
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Hard reset
PLLCTL
(1)
Register (RSCTRL)
Watchdog timers Emulation
RESET pin Soft reset PLLCTL Register (RSCTRL) Watchdog timers Local reset LRESET pin Watchdog timer timeout LPSC MMRs End of Table 9-9
1 All masters in the device have access to the PLL Control Registers.
9.4.1 Power-on Reset Power-on reset is used to reset the entire device, including the test and emulation logic. Power-on reset is initiated by the following: 1. POR pin 2. RESETFULL pin During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device, including the reset-isolated logic, when the device is already powered up. For this reason, the RESETFULL pin, unlike POR, should be driven by the on-board host control other than the power good circuitry. For power-on reset, the Main PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.
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NoteTo most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The RESET pin should not be tied to the POR pin.
9.4.2 Hard Reset A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-isolated modules. POR should also remain de-asserted during this time. Hard reset is initiated by the following: RESET pin RSCTRL Register in the PLL Controller Watchdog timer Emulation By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft resets. The following sequence must be followed during a hard reset: 1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time the RESET signal propagates to all modules (except those specifically mentioned above). To prevent off-chip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET. 2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset. 3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device. 4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
NoteThe POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied to the POR pin.
Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback TCI6636K2H Peripheral Information and Electrical Specifications 283
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The following sequence must be followed during a power-on reset: 1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and remain in their reset state until otherwise configured by their respective peripheral. All peripherals that are power-managed are disabled after a power-on reset and must be enabled through the Device State Control Registers (for more details, see 7.2.3 Device State Control Registers on page 236). 2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in reset. 3. POR must be held active until all supplies on the board are stable, and then for at least an additional period of time (as specified in Section 9.2.1 Power-Up Sequencing on page 266) for the chip-level PLLs to lock. 4. The POR pin can now be de-asserted. Reset-sampled pin values are latched at this point. Then, all chip-level PLLs are taken out of reset, locking sequences begin, and all power-on device initialization processes begin. 5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, the DDR3A PLL and DDR3B PLL have already completed their locking sequences and are supplying a valid clock. The system clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide-by settings. 6. The device is now out of reset and code execution begins as dictated by the selected boot mode.

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9.4.3 Soft Reset A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3A EMIF MMRs, DDR3B EMIF MMRs, PCIe MMRs sticky bits, and external memory content are retained. POR should also remain de-asserted during this time. Soft reset is initiated by the following: RESET pin RSCTRL Register in the PLL Controller Watchdog timer In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected, and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3A and DDR3B memory controller registers are not reset. If the user places the DDR3A and DDR3B SDRAM in self-refresh mode before invoking the soft reset, the DDR3A and DDR3B SDRAM memory content is retained. During a soft reset, the following occurs: 1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates through the system. Internal system clocks are not affected. PLLs remain locked. 2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL Controller pauses system clocks for approximately 8 cycles. At this point: The peripherals remain in the state they were in before the soft reset. The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT Register. The DDR3A and DDR3B MMRs and PCIe MMRs retain their previous values. Only the DDR3A and DDR3B memory controller and PCIe state machines are reset by the soft reset. The PLL Controller remains in the mode it was in prior to the soft reset. System clocks are unaffected. The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration pins are not latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used to select the boot mode. 9.4.4 Local Reset The local reset can be used to reset a particular C66x CorePac without resetting any other device components. Local reset is initiated by the following: LRESET pin Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG registers in the PLL Controller. (See Reset Configuration Register (RSTCFG) on page 296 and 5.3.2 CIC Registers on page 160.) Local reset NMI NMI followed by a time delay and then a local reset for the C66x CorePac selected Hard reset by requesting reset via the PLL Controller LPSC MMRs (memory-mapped registers) For more details see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21)
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9.4.5 ARM CorePac Reset The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such as the Cortex-A15 processor, memory subsystem, debug logic, etc. The ARM CorePac incorporates the PSC to generate resets for its internal modules. Details of reset generation and distribution inside the ARM CorePac can be found in the KeyStone II ARM CorePac Users Guide listed in Related Documentation from Texas Instruments on page 21. 9.4.6 Reset Priority If any of the above reset sources occur simultaneously, the PLL Controller processes only the highest priority reset request. The reset request priorities are as follows (high to low): Power-on reset Hard/soft reset 9.4.7 Reset Controller Register The reset controller registers are part of the PLL Controller MMRs. All TCI6636K2H device-specific MMRs are covered in Section 9.5.2 PLL Controller Memory Map on page 291. For more details on these registers and how to program them, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 9.4.8 Reset Electrical Data/Timing
Table 9-10
No. RESETFULL Pin Reset 1 tw(RESETFULL) Pulse width - pulse width RESETFULL low Soft/Hard-Reset 2 tw(RESET) Pulse width - pulse width RESET low 500C ns End of Table 9-10
1 C = 1/SYSCLK1 clock frequency in ns
Reset Timing Requirements (1)

Min Max Unit
(see Figure 9-4 and Figure 9-5)
500C
ns
Table 9-11
No.
Reset Switching Characteristics (1)

Parameter RESETFULL Pin Reset Min Max Unit
3 4
td(RESETFULLH-RESETSTATH) td(RESETH-RESETSTATH)
Delay time - RESETSTAT high after RESETFULL high Soft/Hard Reset Delay time - RESETSTAT high after RESET high
50000C ns 50000C ns
End of Table 9-11

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SPRS835DAugust 2013 Figure 9-4 RESETFULL Reset Timing
POR 1 RESETFULL
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RESET 3 RESETSTAT
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Figure 9-5
Soft/Hard Reset Timing
POR
RESETFULL 2 RESET 4 RESETSTAT
Table 9-12
See Figure 9-6) No. 1 2
Boot Configuration Timing Requirements
(1)
Min tsu(GPIOn-RESETFULL) th(RESETFULL-GPIOn) Setup time - GPIO valid before RESETFULL asserted Hold time - GPIO valid after RESETFULL asserted 12C 12C
Max
Unit ns ns
End of Table 9-12

1 C = 1/SYSCLK1 clock frequency in ns.
Figure 9-6
Boot Configuration Timing

POR 1 RESETFULL
GPIO[15:0] 2
9.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
This section provides a description of the Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL, and the PLL Controller. For details on the operation of the PLL Controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.

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The Main PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios, alignment, and gating for the system clocks to the device. By default, the device powers up with the main PLL bypassed. Figure 9-7 shows a block diagram of the Main PLL and the PLL Controller. The ARM PLL,DDR3A PLL, DDR3B PLL, and PASS PLL are used to provide dedicated clock to the ARM CorePac,DDR3A, DDR3B, and PASS respectively. These chip level PLLs support a wide range of multiplier and divider values, which can be programmed through the chip level registers located in the Device Control Register block. The Boot ROM will program the multiplier values for main PLL, ARM PLLand PASS PLL based on boot mode. (See Device Boot and Configuration on page 209 for more details.) The DDR3A PLL and DDR3B PLL are used to supply clocks to DDR3A and DDR3B EMIF logic. These PLLs can also be used without programming the PLL Controller. Instead, they can be controlled using the chip-level registers (DDR3APLLCTL0, DDR3APLLCTL1,DDR3BPLLCTL0, DDR3BPLLCTL1) located in the Device Control Register block. To write to these registers, software must go through an unlocking sequence using the KICK0/KICK1 registers. The multiplier values for all chip-level PLLs can be reprogrammed later based on the input parameter table. This feature provides flexibility in that these PLLs may be able to reuse other clock sources instead of having its own clock source.
Figure 9-7 Main PLL and PLL Controller
PLLM
PLL
SYSCLK(N|P) ALTCORECLK(N|P) CORECLKSEL

PLLD
VCO
PLLOUT
CLKOD
1
BYPASS
PLL Controller
POSTDIV /1 PLLDIV1 /1 PLLDIV2 /x PLLDIV3 /z PLLDIV4
SYSCLK1 SYSCLK1 SYSCLK2
C66x CorePacs To Peripherals, HyperLink, etc.
SYSCLK3
To Switch Fabric, Accelerators, SRIO, SmartReflex, etc.
SYSCLK4
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Note that the Main PLL Controller registers can be accessed by any master in the device. The PLLM[5:0] bits of the multiplier are controlled by the PLLM Register inside the PLL Controller and the PLLM[12:6] bits are controlled by the chip-level MAINPLLCTL0 Register. The output divide and bypass logic of the PLL are controlled by fields in the SECCTL Register in the PLL Controller. Only PLLDIV3, and PLLDIV4 are programmable on the device. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in section 1.10 Related Documentation from Texas Instruments on page 21for more details on how to program the PLL controller. The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the Main PLL Controller. The Main PLL Controller also controls reset propagation through the chip, clock alignment, and test points. The Main PLL Controller monitors the PLL status and provides an output signal indicating when the PLL is locked. Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in section 1.10 Related Documentation from Texas Instruments on page 21 for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter). The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see Section 9.5.5 Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing. It should be assumed that any registers not included in these sections are not supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits. The PLL Controller module as described in the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21 includes a superset of features, some of which are not supported on the TCI6636K2H device. The following sections describe the registers that are supported. 9.5.1 Main PLL Controller Device-Specific Information
9.5.1.1 Internal Clocks and Maximum Operating Frequencies
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The Main PLL, used to drive theC66x CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3, and the PASS modules) requires a PLL Controller to manage the various clock divisions, gating, and synchronization. Unlike other PLL, CLKOD functionality of Main PLL is replaced by PLL controller Post-Divider register (POSTDIV). The POSTDIV.RATIO[3:0] and POSTDIV.POSTDEN bits control the post divider ratio and divider enable respectively. PLLM[5:0] input of the Main PLL is controlled by the PLL controller PLLM register. The Main PLL Controller has four SYSCLK outputs that are listed below, along with the clock descriptions. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below. SYSCLK1: Full-rate clock for all C66x CorePacs. Using local dividers, SYSCLK1 is used to derive clocks required for the majority of peripherals that do not need reset isolation. The system peripherals and modules driven by SYSCLK1 are as follows; however, not all peripherals are supported in every part. See the Features chapter for the complete list of peripherals supported in your part. AIF2, BCP, FFTC, RAC, TAC, TCP3d, VCP2, EMIF16, USB 3.0, USIM, HyperLink, PCIe, SGMII, SRIO, GPIO, Timer64, I2C, SPI, TeraNet, UART, ROM, CIC, Security Manager, BootCFG, PSC, Queue Manager, Semaphore, MPUs, EDMA, MSMC, DDR3, EMIF.
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SYSCLK2: Full-rate, reset-isolated clock used to generate various other clocks required by peripherals that need reset isolation: e.g., SmartReflex and SRIO. SYSCLK3: 1/x-rate clock used to clock the C66x CorePac emulation. The default rate for this clock is 1/3. This clock is programmable from /1 to /32, where this clock does not violate the maximum of 350 MHz. SYSCLK3 can be turned off by software. SYSCLK4: 1/z-rate clock for the system trace module only. The default rate for this clock is 1/5. This clock is configurable: the maximum configurable clock is 210 MHz and the minimum configuration clock is 32 MHz. SYSCLK4 can be turned off by software.
Only SYSCLK3 and SYSCLK4 are programmable.

9.5.1.2 Local Clock Dividers
Table 9-13
Clock
Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers (Part 1 of 2)
Module Internal Clock Divider(s) SYSCLK1 Internal Clock Dividers Antenna Interface Subsystem 2 (AIF2) ARM CorePac Bit Rate Coprocessor (BCP) C66x DSP CorePacs Chip Interrupt Controllers (CICx) DDR3 Memory Controller A (also receives clocks from the DDR3A_PLL) DDR3 Memory Controller B (also receives clocks from the DDR3B_PLL) EMIF16 Enhanced Viterbi-Decoder Coprocessor (VCP) Fast Fourier Transform Coprocessor (FFTC) /3, /6 /1, /3, /3, /6, /6 /3 /1, /2, /3, /4 /6 /2 /3 /6 /3 /3 /2, /3, /6 /3 /1 /2, /3, /4, /6 /3, /4 /6 /2, /3, /6, /8 /3 /2, /3 /6 /3, /6 SYSCLK1 Shared Local Clock Dividers Power/Sleep Controller (PSC) EDMA -/12, /24 ---------------------Shared Local Clock Divider
SYSCLK1
HyperLink Multicore Navigator Queue Manager MultiCore Shared Memory Controller (MSMC) PCI express (PCIe) Receive Accelerator Coprocessor (RAC) ROM Serial Gigabit Media Independent Interface (SGMII) Transmit Accelerator Coprocessor (TAC) Turbo Decoder Coprocessor (TCP3d) Universal Asynchronous Receiver/Transmitter (UART) Universal Serial Bus 3.0 (USB 3.0)
SYSCLK1
Memory Protection Units (MPUx) Semaphore TeraNet (SYSCLK1/3 domain)
--
/3
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The clock signals from the Main PLL Controller are routed to various modules and peripherals on the device. Some modules and peripherals have one or more internal clock dividers. Other modules and peripherals have no internal clock dividers, but are grouped together and receive clock signals from a shared local clock divider. Internal and shared local clock dividers have fixed division ratios. See table Table 9-13.

Clock
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Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers (Part 2 of 2)
Module Boot Config General-Purpose Input/Output (GPIO) I2C Internal Clock Divider(s) Shared Local Clock Divider
SYSCLK1
Security Manager Serial Peripheral Interconnect (SPI) TeraNet (CPU /6 domain) Timers Universal Subscriber Identity Module (USIM)
--
/6
SYSCLK2 Internal Clock Dividers Serial RapidIO (SRIO) SYSCLK2 SmartReflex C66x CorePacs SmartReflex ARM CorePac End of Table 9-13 /3, /4, /6 /12, /128 /12, /128, /128 ----
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9.5.1.3 Module Clock Input
Table 9-7 lists various clock domains in the device and their distribution in each peripheral. The table also shows the distributed clock division in modules and their mapping with source clocks of the device PLLs.
9.5.1.4 Main PLL Controller Operating Modes
The Main PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the BYPASS bit of the PLL Secondary Control Register (SECCTL). In bypass mode, PLL input is fed directly out as SYSCLK1. In PLL mode, SYSCLK1 is generated from the PLL output using the values set in the PLLM and PLLD fields in the MAINPLLCTL0 Register. External hosts must avoid access attempts to the DSP while the frequency of its internal clocks is changing. User software must implement a mechanism that causes the DSP to notify the host when the PLL configuration has completed.
9.5.1.5 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device power-up. The device should not be taken out of reset until this stabilization time has elapsed. The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value, see Table 9-14. The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the PLL Controller can be switched to PLL mode. The Main PLL lock time is given in Table 9-14.
Table 9-14 Main PLL Stabilization, Lock, and Reset Times
Parameter PLL stabilization time PLL lock time PLL reset time End of Table 9-14
1 C = SYSCLK1(N|P) cycle time in ns.
Min 100
Typ
Max
(1)
Unit s
2000 C 1000
ns
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9.5.2 PLL Controller Memory Map The memory map of the Main PLL Controller is shown in Table 9-15. TCI6636K2H-specific Main PLL Controller Register definitions can be found in the sections following Table 9-15. For other registers in the table, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. It is recommended to use read-modify-write sequence to make any changes to the valid bits in the Main PLL Controller registers. Note that only registers documented here are accessible on the TCI6636K2H. Other addresses in the Main PLL Controller memory map including the Reserved registers must not be modified. Furthermore, only the bits within the registers described here are supported.
Table 9-15 PLL Controller Registers (Including Reset Controller) (Part 1 of 2)
Acronym RSTYPE RSTCTRL RSTCFG RSISO PLLCTL SECCTL PLLM PLLDIV1 PLLDIV2 PLLDIV3 POSTDIV PLLCMD PLLSTAT ALNCTL DCHANGE CKEN CKSTAT SYSTAT PLLDIV4 PLLDIV5 PLLDIV6 PLLDIV7 PLLDIV8 Register Name Reserved Reset Type Status Register (Reset Main PLL Controller) Software Reset Control Register (Reset Main PLL Controller) Reset Configuration Register (Reset Main PLL Controller) Reset Isolation Register (Reset Main PLL Controller) Reserved PLL Control Register Reserved PLL Secondary Control Register Reserved PLL Multiplier Control Register Reserved PLL Controller Divider 1Register PLL Controller Divider 2 Register PLL Controller Divider 3Register Reserved PLL Controller Post-Divide Register Reserved PLL Controller Command Register PLL Controller Status Register PLL Controller Clock Align Control Register PLLDIV Ratio Change Status Register Reserved Reserved SYSCLK Status Register Reserved PLL Controller Divider 4Register Reserved Reserved Reserved Reserved
Hex Address Range 00 0231 0000 - 00 0231 00E3 00 0231 00E4 00 0231 00E8 00 0231 00EC 00 0231 00F0 00 0231 00F0 - 00 0231 00FF 00 0231 0100 00 0231 0104 00 0231 0108 00 0231 010C 00 0231 0110 00 0231 0114 00 0231 0118 00 0231 011C 00 0231 0120 00 0231 0124 00 0231 0128 00 0231 012C - 00 0231 0134 00 0231 0138 00 0231 013C 00 0231 0140 00 0231 0144 00 0231 0148 00 0231 014C 00 0231 0150 00 0231 0154 - 00 0231 015C 00 0231 0160 00 0231 0164 00 0231 0168 00 0231 016C 00 0231 0170
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SPRS835DAugust 2013 Table 9-15 PLL Controller Registers (Including Reset Controller) (Part 2 of 2)
Acronym PLLDIV9 - PLLDIV16 Register Name Reserved Reserved
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Hex Address Range 00 0231 0174 - 00 0231 0193 00 0231 0194 - 00 0231 01FF End of Table 9-15
9.5.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 9-8 and described in Table 9-16.
Figure 9-8
31
PLL Secondary Control Register (SECCTL)

24 Reserved R-0000 0000 23 BYPASS RW-1 22 OUTPUT DIVIDE RW-0001 19 18 Reserved RW-001 0000 0000 0000 0000 0
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Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-16
Bit 31-24 23 Field
PLL Secondary Control Register Field Descriptions

Description Reserved Main PLL bypass enable 0 = Main PLL bypass disabled 1 = Main PLL bypass enabled Output divider ratio bits 0h = 1. Divide frequency by 1 1h = 2. Divide frequency by 2 2h = 3. Divide frequency by 3 3h = 4. Divide frequency by 4 4h - Fh = 5 to 16. Divide frequency range: divide frequency by 5 to divide frequency by 80. Reserved
Reserved BYPASS
22-19
OUTPUT DIVIDE
18-0
Reserved
End of Table 9-16
9.5.2.2 PLL Controller Divider Register (PLLDIV3, and PLLDIV4)
The PLL Controller Divider Registers (PLLDIV3 and PLLDIV4) are shown in Figure 9-9 and described in Table 9-17. The default values of the RATIO field on a reset for PLLDIV3, and PLLDIV4 are different as mentioned in the footnote of Figure 9-9.
Figure 9-9
31 Reserved R-0
PLL Controller Divider Register (PLLDIVn)

16 Dn 15
(1)
14 EN Reserved R-0
7 RATIO R/W-n
(2)
R/W-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset

1 D3EN for PLLDIV3; D4EN for PLLDIV4 2 n=02h for PLLDIV3; n=03h for PLLDIV4
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SPRS835DAugust 2013 PLL Controller Divider Register Field Descriptions

Description Reserved Divider Dn enable bit (See footnote of Figure 9-9) 0 = Divider n is disabled 1 = No clock output. Divider n is enabled. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Divider ratio bits (See footnote of Figure 9-9) 0h = 1. Divide frequency by 1 1h = 2. Divide frequency by 2 2h = 3. Divide frequency by 3 3h = 4. Divide frequency by 4 4h - 4Fh = 5 to 80. Divide frequency range: divide frequency by 5 to divide frequency by 80.
Table 9-17
Bit 31-16 15 Field
Reserved DnEN
14-8 7-0
Reserved RATIO
End of Table 9-17
9.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller Clock Align Control Register (ALNCTL) is shown in Figure 9-10 and described in Table 9-18.
Figure 9-10
31 Reserved R-0 Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
PLL Controller Clock Align Control Register (ALNCTL)

5 4 ALN4 R/W-1 3 ALN3 R/W-1 2 Reserved R-0 0
Table 9-18
Bit 31-5 2-0 4 3 Field
PLL Controller Clock Align Control Register Field Descriptions

Description Reserved. This location is always read as 0. A value written to this field has no effect. SYSCLKn alignment. Do not change the default values of these fields. 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set. 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
Reserved ALN4 ALN3
End of Table 9-18
9.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLL CTL flags the change in the DCHANGE Status Register. During the GO operation, the PLL controller changes only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also needs to be aligned to other clocks. The PLLDIV Divider Ratio Change Status Register is shown in Figure 9-11 and described in Table 9-19.
Figure 9-11
31 Reserved R-0 Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
PLLDIV Divider Ratio Change Status Register (DCHANGE)

5 4 SYS4 R/W-1 3 SYS3 R/W-1 2 Reserved R-0 0
293
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Bit 31-5 2-0 4 3 Field Reserved SYS4 SYS3
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PLLDIV Divider Ratio Change Status Register Field Descriptions

Description Reserved. This bit location is always read as 0. A value written to this field has no effect. Identifies when the SYSCLKn divide ratio has been modified. 0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected. 1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
End of Table 9-19
9.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[4:1]. SYSTAT is shown in Figure 9-12 and described in Table 9-20.
Figure 9-12
31 Reserved R-n Legend: R/W = Read/Write; R = Read only; -n = value after reset
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SYSCLK Status Register (SYSTAT)

4 3 SYS4ON R-1 2 SYS3ON R-1 1 SYS2ON R-1 0 SYS1ON R-1
Table 9-20
Bit 31-4 3-0 Field
SYSCLK Status Register Field Descriptions

Description Reserved. This location is always read as 0. A value written to this field has no effect. SYSCLK[N] on status 0 = SYSCLK[N] is gated 1 = SYSCLK[N] is on
(1)
Reserved SYS[N ]ON
End of Table 9-20

1 Where N = 1, 2, 3, or 4
9.5.2.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in Figure 9-13 and described in Table 9-21.
Figure 9-13
31 29
Reset Type Status Register (RSTYPE)

28 EMU-RST R-0 27 Reserved R-0 12 11 WDRST[N] R-0 8 7 Reserved R-0 3 2 PLLCTRLRST R-0 1 RESET R-0 0 POR R-0
Reserved R-0
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SPRS835DAugust 2013 Reset Type Status Register Field Descriptions

Description Reserved. Always reads as 0. Writes have no effect. Reset initiated by emulation 0 = Not the last reset to occur 1 = The last reset to occur Reserved. Always reads as 0. Writes have no effect. Reset initiated by Watchdog Timer[N] 0 = Not the last reset to occur 1 = The last reset to occur
Table 9-21
Bit 31-29 28 Field
Reserved EMU-RST
27-12 11 10 9 8 7-3 2
Reserved WDRST3 WDRST2 WDRST1 WDRST0 Reserved PLLCTLRST
Reserved. Always reads as 0. Writes have no effect. Reset initiated by PLLCTL 0 = Not the last reset to occur 1 = The last reset to occur RESET reset 0 = RESET was not the last reset to occur 1 = RESET was the last reset to occur Power-on reset 0 = Power-on reset was not the last reset to occur 1 = Power-on reset was the last reset to occur
RESET
POR
End of Table 9-21
9.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value is 0x5A69. A valid key will be stored as 0x000C. Any other key value is invalid. When the RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register (RSTCTRL) is shown in Figure 9-14 and described in Table 9-22.
Figure 9-14
31 Reserved R-0x0000 Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
Reset Control Register (RSTCTRL)

17 16 SWRST R/W-0x
(1)
15 KEY R/W-0x0003
Table 9-22
Bit 31-17 16 Field
Reset Control Register Field Descriptions

Description Reserved Software reset 0 = Reset 1 = Not reset Key used to enable writes to RSTCTRL and RSTCFG.
Reserved SWRST
15-0
KEY
End of Table 9-22
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9.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset (a hard reset or a soft reset) initiated by RESET, the watchdog timer, and the Main PLL Controllers RSTCTRL Register. By default, these resets are hard resets. The Reset Configuration Register (RSTCFG) is shown in Figure 9-15 and described in Table 9-23.
Figure 9-15
31 Reserved R-0x000000
Reset Configuration Register (RSTCFG)

14 13 PLLCTLRSTTYPE R/W-0
(2)
12 RESETTYPE R/W-0
2
11 Reserved R-0x0
3 WDTYPE[N R/W-0x00
(1) 2
0 ]

1 Where N = 1, 2, 3,....N (Not all these outputs may be used on a specific device.) 2 Writes are conditional based on valid key. For details, see Section 9.5.2.7 Reset Control Register (RSTCTRL).
PRODUCT PREVIEW
Table 9-23
Bit 31-14 13 Field
Reset Configuration Register Field Descriptions

Description Reserved PLL controller initiates a software-driven reset of type: 0 = Hard reset (default) 1 = Soft reset RESET initiates a reset of type: 0 = Hard reset (default) 1 = Soft reset Reserved Watchdog timer [N] initiates a reset of type: 0 = Hard reset (default) 1 = Soft reset
Reserved PLLCTLRSTTYPE
12
RESETTYPE
11-4 3 2 1 0
Reserved WDTYPE3 WDTYPE2 WDTYPE1 WDTYPE0
End of Table 9-23
9.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non-power-on reset. Setting any of these bits effectively blocks reset to all Main PLL Control Registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the module-specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-isolate a particular module. For more information on the MDCTLx Register, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. The Reset Isolation Register (RSISO) is shown in Figure 9-16 and described in Table 9-24.
Figure 9-16
31 Reserved R-0x0000
Reset Isolation Register (RSISO)

16 15 Reserved R-0x00 10 9 SRIOISO R/W-0 8 SRISO R/W-0 7 4 3 AIF2ISO R/W-0 2 0
Reserved R-0x0
Reserved R-000
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SPRS835DAugust 2013 Reset Isolation Register Field Descriptions

Description Reserved. Isolate SRIO module control 0 = Not reset isolated 1 = Reset isolated Isolate SmartReflex control 0 = Not reset isolated 1 = Reset isolated Reserved Isolate AIF2 module control 0 = Not reset isolated 1 = Reset isolated Reserved
Table 9-24
Bit 31-10 9 Field
Reserved SRIOISO
SRISO
7-4 3
Reserved AIF2ISO
2-0
Reserved
End of Table 9-24
9.5.3 Main PLL Control Registers The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the Main PLL Controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset. For valid configurable values of the MAINPLLCTL registers, see Section 7.1.4 System PLL Settings on page 233. See Section 7.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register on page 242 for the address location of the KICK registers and their locking and unlocking sequences. See Figure 9-17 and Table 9-25 for MAINPLLCTL0 details and Figure 9-18 and Table 9-26 for MAINPLLCTL1 details.
Figure 9-17
31 BWADJ[7:0] RW,+0000 0101 Legend: RW = Read/Write; -n = value after reset
Main PLL Control Register 0 (MAINPLLCTL0)

24 23 Reserved RW - 0000 0 19 18 PLLM[12:6] RW,+0000000 12 11 6 5 PLLD RW,+000000 0
Reserved RW, +000000
Table 9-25
Bit 31-24 Field
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions (Part 1 of 2)

Description BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7. Reserved 7-bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor minus 1. The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the PLLM[12:6] bits are controlled by the above chip-level register. MAINPLLCTL0 register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL Controller. See the PLL Secondary Control Register (SECCTL) on page 292 for more details.
BWADJ[7:0]
23-19 18-12
Reserved PLLM[12:6]
297
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Bit 11-6 5-0 Field Reserved PLLD
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Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions (Part 2 of 2)

Description Reserved A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
End of Table 9-25
Figure 9-18
31
Main PLL Control Register 1 (MAINPLLCTL1)

7 Reserved RW - 0000000000000000000000000 6 ENSAT RW-0 5 4 3 BWADJ[11:8] RW- 0000 0
Reserved R-00
Legend: RW = Read/Write; -n = value after reset
PRODUCT PREVIEW
Table 9-26
Bit 31-7 6 5-4 3-0 Field
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions

Description Reserved Needs to be set to 1 for proper PLL operation Reserved BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7
Reserved ENSAT Reserved BWADJ[11:8]
End of Table 9-26
9.5.4 ARM PLL Control Registers The ARM PLL uses two chip-level registers (ARMPLLCTL0 and ARMPLLCTL1) without using the Main PLL Controller like other PLLs for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an un-locking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset. For valid configurable values of the ARMPLLCTL registers, see Section 7.1.4.1 ARM CorePac System PLL Settings on page 233. See Section 7.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register on page 242 for the address location of the KICK registers and their locking and unlocking sequences. See Figure 9-19 and Table 9-27 for ARMPLLCTL0 details and Figure 9-20 and Table 9-28 for ARMPLLCTL1 details.
.
Figure 9-19
31
ARM PLL Control Register 0 (ARMPLLCTL0) (1)

24 23 BYPASS RW,+0 22 19 18 PLLM RW,+0000000010011 6 5 PLLD RW,+000000 0
BWADJ[7:0] RW,+0000 1001
CLKOD RW,+0001

1 This register is Reset on POR only. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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SPRS835DAugust 2013 ARM PLL Control Register 0 Field Descriptions

Description BWADJ[11:8] and BWADJ[7:0] are located inARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7 Enable bypass mode 0 = Bypass disabled 1 = Bypass enabled A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1 A 13-bit field that selects the values for the multiplication factor A 6-bit field that selects the values for the reference divider
Table 9-27
Bit 31-24 Field
BWADJ[7:0]
23
BYPASS
22-19 18-6 5-0
CLKOD PLLM PLLD
End of Table 9-27
Figure 9-20
31
ARM PLL Control Register 1 (ARMPLLCTL1)

15 Reserved RW - 00000000000000000 14 PLLRST RW-0 13 Reserved RW-0000000 7 6 ENSAT RW-0 5 4 3 BWADJ[11:8] RW- 0000 0
Reserved R-00
Table 9-28
Bit 31-15 14 Field
ARM PLL Control Register 1Field Descriptions

Description Reserved PLL Reset bit 0 = PLL Reset is released 1 = PLL Reset is asserted Reserved Needs to be set to 1 for proper PLL operation Reserved BWADJ[11:8] and BWADJ[7:0] are located in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7
Reserved PLLRST
13-7 6 5-4 3-0
End of Table 9-28
See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21 for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the ARM PLL is also controlled by the SECCTL register in the PLL Controller. See the PLL Secondary Control Register (SECCTL) on page 292 for more details. 9.5.5 Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
Table 9-29
No. SYSCLK[P:N] 1 1 3 2 tc(SYSCLKN) tc(SYSCLKP) tw(SYSCLKN) tw(SYSCLKN) Cycle time SYSCLKN cycle time Cycle time SYSCLKP cycle time Pulse width SYSCLKN high Pulse width SYSCLKN low 3.25 or 6.51 or 8.138 (2) 3.25 or 6.51 or 8.138 0.45*tc 0.45*tc 0.55*tc 0.55*tc ns ns ns ns
Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 1 of 3)

Min Max Unit
299
PRODUCT PREVIEW

No. 2 3 4 4 5 5 tw(SYSCLKP) tw(SYSCLKP) tr(SYSCLK_250 mV) tf(SYSCLK_250 mV) tj(SYSCLKN) tj(SYSCLKP) Pulse width SYSCLKP high Pulse width SYSCLKP low Transition time SYSCLK differential rise time (250 mV) Transition time SYSCLK differential fall time (250 mV) Jitter, peak_to_peak _ periodic SYSCLKN Jitter, peak_to_peak _ periodic SYSCLKP ARMCLK[P:N] 1 1 3 2 2 3 4 4 5 5 tc(ARMCLKN) tc(ARMCLKP) tw(ARMCLKN) tw(ARMCLKN) tw(ARMCLKP) tw(ARMCLKP) tr(ARMCLK_250 mV) tf(ARMCLK_250 mV) tj(ARMCLKN) tj(ARMCLKP) Cycle time ARMCLKN cycle time Cycle time ARMCLKP cycle time Pulse width ARMCLKN high Pulse width ARMCLKN low Pulse width ARMCLKP high Pulse width ARMCLKP low Transition time ARMCLK differential rise time (250 mV) Transition time ARMCLK differential fall time (250 mV) Jitter, peak_to_peak _ periodic ARMCLKN Jitter, peak_to_peak _ periodic ARMCLKP ALTCORECLK[P:N] 1 1 3 2 2 3 4 4 5 5 tc(ALTCORCLKN) tc(ALTCORECLKP) tw(ALTCORECLKN) tw(ALTCORECLKN) tw(ALTCORECLKP) tw(ALTCORECLKP) tr(ALTCORECLK_250 mV) tf(ALTCORECLK_250 mV) tj(ALTCORECLKN) tj(ALTCORECLKP) Cycle time ALTCORECLKN cycle time Cycle time ALTCORECLKP cycle time Pulse width ALTCORECLKN high Pulse width ALTCORECLKN low Pulse width ALTCORECLKP high Pulse width ALTCORECLKP low Transition time ALTCORECLK differential rise time (250 mV) Transition time ALTCORECLK differential fall time (250 mV) Jitter, peak_to_peak _ periodic ALTCORECLKN Jitter, peak_to_peak _ periodic ALTCORECLKP SRIOSGMIICLK[P:N] 1 1 3 2 2 3 4 4 5 tc(SRIOSGMIICLKN) tc(SRIOSGMIICLKP) tw(SRIOSGMIICLKN) tw(SRIOSGMIICLKN) tw(SRIOSGMIICLKP) tw(SRIOSGMIICLKP) tr(SRIOSGMIICLK_250mV) tf(SRIOSGMIICLK_250mV) tj(SRIOSGMIICLKN) Cycle time SRIOSGMIICLKN cycle time Cycle time SRIOSGMIICLKP cycle time Pulse width SRIOSGMIICLKN high Pulse width SRIOSGMIICLKN low Pulse width SRIOSGMIICLKP high Pulse width SRIOSGMIICLKP low Transition time SRIOSGMIICLK differential rise time (250 mV) Transition time SRIOSGMIICLK differential fall time (250 mV) Jitter, RMS SRIOSGMIICLKN 3.2 or 6.4 3.2 or 6.4 0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN) 0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN) 0.45*tc(SRIOSGMIICLKP) 0.45*tc(SRIOSGMIICLKP) 50 50 0.55*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP) 350 350 ns ns ns ns ns ns ps ps 3.2 3.2 0.45*tc(ALTCORECLKN) 0.45*tc(ALTCORECLKN) 0.45*tc(ALTCORECLKP) 0.45*tc(ALTCORECLKP) 50 50 25 25 0.55*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP) 350 350 100 100 ns ns ns ns ns ns ps ps ps ps 3.2 3.2 0.45*tc(ARMCLKN) 0.45*tc(ARMCLKN) 0.45*tc(ARMCLKP) 0.45*tc(ARMCLKP) 50 50 25 25 0.55*tc(ARMCLKN) 0.55*tc(ARMCLKN) 0.55*tc(ARMCLKP) 0.55*tc(ARMCLKP) 350 350 100 100 ns ns ns ns ns ns ps ps ps ps
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Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 2 of 3)

Min 0.45*tc 0.45*tc 50 50 Max 0.55*tc 0.55*tc 350 350 0.2*tc(SYSCLKN)
(3)
(see Figure 9-21 and Figure 9-22) Unit ns ns ps ps ps ps
0.2*tc(SYSCLKP)
PRODUCT PREVIEW
2 ps, RMS
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SPRS835DAugust 2013 Main PLL Controller/ARM/SRIO/HyperLink/PCIe Clock Input Timing Requirements

Min
(1)
Table 9-29
No. 5 5 5
(Part 3 of 3)
Max Unit
tj(SRIOSGMIICLKP) tj(SRIOSGMIICLKN) tj(SRIOSGMIICLKP)
Jitter, RMS SRIOSGMIICLKP Jitter, RMS SRIOSGMIICLKN (SRIO not used) Jitter, RMS SRIOSGMIICLKP (SRIO not used) HyperLink CLK[P:N]
2 ps, RMS 4 ps, RMS 4 ps, RMS
1 1 3 2 2 3 4 4 5 5
tc(HYPCLKN) tc(HYPCLKP) tw(HYPCLKN) tw(HYPCLKN) tw(HYPCLKP) tw(HYPCLKP) tr(HYPCLK_250mV) tf(HYPCLK_250mV) tj(HYPCLKN) tj(HYPCLKP)
Cycle time HYPCLKN cycle time Cycle time HYPCLKP cycle time Pulse width HYPCLKN high Pulse width HYPCLKN low Pulse width HYPCLKP high Pulse width HYPCLKP low Transition time HYPCLK differential rise time (250 mV) Transition time HYPCLK differential fall time (250 mV) Jitter, RMS HYPCLKN Jitter, RMS HYPCLKP PCIECLK[P:N]
3.2 or 4 or 6.4 3.2 or 4 or 6.4 0.45*tc(HYPCLKN) 0.45*tc(HYPCLKN) 0.45*tc(HYPCLKP) 0.45*tc(HYPCLKP) 50 50 0.55*tc(HYPCLKN) 0.55*tc(HYPCLKN) 0.55*tc(HYPCLKP) 0.55*tc(HYPCLKP) 350 350
ns ns ns ns ns ns ps ps
4 ps, RMS 4 ps, RMS
1 1 3 2 2 3 4 4 5 5
tc(PCIECLKN) tc(PCIECLKP) tw(PCIECLKN) tw(PCIECLKN) tw(PCIECLKP) tw(PCIECLKP) tr(PCIECLK_250mV) tf(PCIECLK_250mV) tj(PCIECLKN) tj(PCIECLKP)
Cycle time PCIECLKN cycle time Cycle time PCIECLKP cycle time Pulse width PCIECLKN high Pulse width PCIECLKN low Pulse width PCIECLKP high Pulse width PCIECLKP low Transition time PCIECLK differential rise time (250 mV) Transition time PCIECLK differential fall time (250 mV) Jitter, RMS PCIECLKN Jitter, RMS PCIECLKP
3.2 or 4 or 6.4 or 10 3.2 or 4 or 6.4 or 10 0.45*tc(PCIECLKN) 0.45*tc(PCIECLKN) 0.45*tc(PCIECLKP) 0.45*tc(PCIECLKP) 50 50 0.55*tc(PCIECLKN) 0.55*tc(PCIECLKN) 0.55*tc(PCIECLKP) 0.55*tc(PCIECLKP) 350 350
ns ns ns ns ns ns ps ps
4 ps, RMS 4 ps, RMS
End of Table 9-29

1 See the Hardware Design Guide for KeyStone Devices in 1.10 Related Documentation from Texas Instruments on page 21for detailed recommendations. 2 If AIF2 is being used then SYSCLK(N|P) can be programmed only to fixed values, if AIF2 is not being used then any value in the range between the min and max values can be used. 3 If AIF2 is used then the Max allowed jitter on SYSCLK(N|P) is 4ps RMS
Figure 9-21
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing

1 2 <CLK_NAME>CLKN <CLK_NAME>CLKP 4 5 3
301
PRODUCT PREVIEW

SPRS835DAugust 2013 Figure 9-22 Main PLL Transition Time
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peak-to-peak differential input voltage (250 mV to 2 V)
250 mV peak-to-peak
TR = 50 ps min to 350 ps max (10% to 90 %) for the 250 mV peak-to-peak centered at zero crossing
9.6 DDR3A PLL and DDR3B PLL
PRODUCT PREVIEW
The DDR3A PLL and DDR3B PLL generate interface clocks for the DDR3A and DDR3B memory controllers. When coming out of power-on reset, DDR3A PLL and DDR3B PLL are programmed to a valid frequency during the boot configuration process before being enabled and used. DDR3A PLL and DDR3B PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in 1.10 Related Documentation from Texas Instruments on page 21for detailed recommendations.
Figure 9-23 DDR3A PLL and DDR3B PLL Block Diagram
PLLM
DDR3 PLL
DDRCLK(N|P)
PLLD
VCO
PLLOUT
CLKOD
1
DDR3 PHY
DDR
BYPASS
9.6.1 DDR3A PLL and DDR3B PLL Control Registers The DDR3A PLL and DDR3B PLL, which are used to drive the DDR3A PHY and DDR3B PHY for the EMIF, do not use a PLL controller. DDR3A PLL and DDR3B PLL can be controlled using the DDR3APLLCTL0/DDR3BPLLCTL0 and DDR3APLLCTL1/DDR3BPLLCTL1 registers located in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configurable values, see 7.1.4 System PLL Settings on page 233. See 7.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register on page 242 for the address location of the registers and locking and unlocking sequences for accessing the registers. These registers are reset on POR only.
.
Figure 9-24
31
DDR3A PLL and DDR3B PLL Control Register 0 (DDR3APLLCTL0/DDR3BPLLCTL0)

BWADJ[7:0] RW,+0000 1001
CLKOD RW,+0001
302

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SPRS835DAugust 2013 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
Description BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7 Enable bypass mode 0 = Bypass disabled 1 = Bypass enabled A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1 A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply factor minus 1 A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide value minus 1
Table 9-30
Bit 31-24 Field
BWADJ[7:0]
23
BYPASS
22-19 18-6 5-0
CLKOD PLLM PLLD
End of Table 9-30
Figure 9-25
31
DDR3A PLL and DDR3B PLL Control Register 1 (DDR3APLLCTL0/DDR3BPLLCTL1)

15 Reserved RW - 00000000000000000 14 PLLRST RW-0 13 Reserved RW-0000000 7 6 ENSAT RW-0 5 4 3 BWADJ[11:8] RW- 0000 0
Reserved R-00
Table 9-31
Bit 31-15 14 Field
DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions

Description Reserved PLL Reset bit 0 = PLL Reset is released 1 = PLL Reset is asserted Reserved Needs to be set to 1 for proper PLL operation Reserved BWADJ[11:8] and BWADJ[7:0] are located in DDRPLLCTL0 and DDRPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7
Reserved PLLRST
13-7 6 5-4 3-0
End of Table 9-31
9.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information As shown in Figure 9-23, the output of DDR3A PLL and DDR3B PLL (PLLOUT) is divided by 2 and directly fed to the DDR3A and DDR3B memory controller. During power-on resets, the internal clocks of the DDR3 PLL are affected as described in Section 9.4 Reset Controller on page 282. The DDR3 PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
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9.6.3 DDR3 PLL Input Clock Electrical Data/Timing Table 9-32 applies to both DDR3A and DDR3B memory interfaces.
Table 9-32
No. DDRCLK[P:N] 1 1 3 2 2 3 4 4 5 5 tc(DDRCLKN) tc(DDRCLKP) tw(DDRCLKN) tw(DDRCLKN) tw(DDRCLKP) tw(DDRCLKP) tr(DDRCLK_250 mV) tf(DDRCLK_250 mV) tj(DDRCLKN) tj(DDRCLKP) Cycle time _ DDRCLKN cycle time Cycle time _ DDRCLKP cycle time Pulse width _ DDRCLKN high Pulse width _ DDRCLKN low Pulse width _ DDRCLKP high Pulse width _ DDRCLKP low Transition time _ DDRCLK differential rise time (250 mV) Transition time _ DDRCLK differential fall time (250 mV) Jitter, peak_to_peak _ periodic DDRCLKN Jitter, peak_to_peak _ periodic DDRCLKP 3.2 3.2 0.45*tc(DDRCLKN) 0.45*tc(DDRCLKN) 0.45*tc(DDRCLKP) 0.45*tc(DDRCLKP) 50 50 25 25 0.55*tc(DDRCLKN) 0.55*tc(DDRCLKN) 0.55*tc(DDRCLKP) 0.55*tc(DDRCLKP) 350 350 0.02*tc(DDRCLKN) 0.02*tc(DDRCLKP) ns ns ns ns ns ns ps ps ps ps
DDR3 PLL DDRCLK(N|P) Timing Requirements

Min Max Unit
PRODUCT PREVIEW
End of Table 9-32
Figure 9-26
DDR3 PLL DDRCLK Timing

1 2 DDRCLKN DDRCLKP 4 5 3
9.7 PASS PLL

The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select the input source of the PASS PLL as either the output of the Main PLL mux or the PASSCLK clock reference source. When coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be programmed to a valid frequency before being enabled and used. PASS PLL power is supplied via the PASS PLL power-supply pin (AVDDA3). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in 1.10 Related Documentation from Texas Instruments on page 21 for detailed recommendations.
Figure 9-27 PASS PLL Block Diagram
SYSCLK(P|N) ALTCORECLK(P|N) CORECLKSEL PLL
PLLOUT
PLL Controller
SYSCLKn
C66x CorePac
PLLM
PASS PLL
/3 PLLOUT Network Coprocessor
VCO
PASSCLK(P|N) PACLKSEL
PLLD
CLKOD
1
BYPASS
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9.7.1 PASS PLL Local Clock Dividers The clock signal from the PASS PLL Controller is routed to the Network Coprocessor. The Net CP module has two internal dividers with fixed division ratios. See table Table 9-34.
Table 9-33
Clock PLLOUT
PASS PLL Clock Domain Module Internal Clock Dividers

Module Network Coprocessor Internal Clock Divider(s) /13, /16
End of Table 9-33
9.7.2 PASS PLL Control Registers
Figure 9-28
31
PASS PLL Control Register 0 (PASSPLLCTL0)

BWADJ[7:0] RW,+0000 1001
CLKOD RW,+0001
Table 9-34
Bit 31-24 Field
PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)

Description BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7 Enable bypass mode 0 = Bypass disabled 1 = Bypass enabled A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16. CLKOD field is loaded with output divide value minus 1 A 13-bit field that selects the values for the multiplication factor (see note below). PLLM field is loaded with the multiply factor minus 1. A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1.
BWADJ[7:0]
23
BYPASS
22-19 18-6 5-0
CLKOD PLLM PLLD
End of Table 9-34
Figure 9-29
31
PASS PLL Control Register 1 (PASSPLLCTL1)

15 Reserved RW - 00000000000000000 14 PLLRST RW-0 13 PAPLL RW-0 12 7 6 ENSAT RW-0 5 4 3 BWADJ[11:8] RW- 0000 0
Reserved RW-000000
Reserved R-00
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The PASS PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. PASS PLL can be controlled using the PAPLLCTL0 and PAPLLCTL1 registers located in the Bootcfg module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configuration values, see 7.1.4 System PLL Settings on page 233. See 7.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register on page 242 for the address location of the registers and locking and unlocking sequences for accessing these registers. These registers are reset on POR only.

Bit 31-15 14 Field Reserved PLLRST
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PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)

Description Reserved PLL Reset bit 0 = PLL Reset is released 1 = PLL Reset is asserted 0 = Not supported 1 = PAPLL Reserved Needs to be set to 1 for proper PLL operation Reserved BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. BWADJ[11:0] should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7
13 12-7 6 5-4 3-0
PAPLL Reserved ENSAT Reserved BWADJ[11:8]
PRODUCT PREVIEW
End of Table 9-35
9.7.3 PASS PLL Device-Specific Information As shown in Figure 9-27, the output of PASS PLL (PLLOUT) is divided by 3 and directly fed to the Network Coprocessor. During power-on resets, the internal clocks of the PASS PLL are affected as described in Section 9.4 Reset Controller on page 282. The PASS PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any other resets. 9.7.4 PASS PLL Input Clock Electrical Data/Timing
Table 9-36
No. PASSCLK[P:N] 1 1 3 2 2 3 4 4 5 5 tc(PASSCLKN) tc(PASSCLKP) tw(PASSCLKN) tw(PASSCLKN) tw(PASSCLKP) tw(PASSCLKP) tr(PASSCLK_250mV) tf(PASSCLK_250mV) tj(PASSCLKN) tj(PASSCLKP) Cycle time _ PASSCLKN cycle time Cycle time _ PASSCLKP cycle time Pulse width _ PASSCLKN high Pulse width _ PASSCLKN low Pulse width _ PASSCLKP high Pulse width _ PASSCLKP low Transition time _ PASSCLK differential rise time (250 mV) Transition time _ PASSCLK differential fall time (250 mV) Jitter, peak_to_peak _ periodic PASSCLKN Jitter, peak_to_peak _ periodic PASSCLKP 3.2 3.2 0.45*tc(PASSCLKN) 0.45*tc(PASSCLKN) 0.45*tc(PASSCLKP) 0.45*tc(PASSCLKP) 50 50 6.4 6.4 0.55*tc(PASSCLKN) 0.55*tc(PASSCLKN) 0.55*tc(PASSCLKP) 0.55*tc(PASSCLKP) 350 350 100 100 ns ns ns ns ns ns ps ps ps, pk-pk ps, pk-pk
PASS PLL Timing Requirements

Min Max Unit
(See Figure 9-30 and Figure 9-22)
End of Table 9-36
Figure 9-30
PASS PLL Timing

1 2 PASSCLKN PASSCLKP 4 5 3
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9.8 External Interrupts

9.8.1 External Interrupts Electrical Data/Timing
Table 9-37
(see Figure 9-31) No. 1 1 1 2 2 2 3 tsu(LRESET-LRESETNMIENL) tsu(NMI-LRESETNMIENL) tsu(CORESELn-LRESETNMIENL) th(LRESETNMIENL-LRESET) th(LRESETNMIENL-NMI) th(LRESETNMIENL-CORESELn) tw(LRESETNMIEN) Setup time - LRESET valid before LRESETNMIEN low Setup time - NMI valid before LRESETNMIEN low Setup time - CORESEL[3:0] valid before LRESETNMIEN low Hold time - LRESET valid after LRESETNMIEN high Hold time - NMI valid after LRESETNMIEN high Hold time - CORESEL[3:0] valid after LRESETNMIEN high Pulsewidth - LRESETNMIEN low width Min 12*P 12*P 12*P 12*P 12*P 12*P 12*P Max Unit ns ns ns ns ns ns ns
(1)
NMI and LRESET Timing Requirements
End of Table 9-37

1 P = 1/SYSCLK1 clock frequency in ns.
Figure 9-31
NMI and LRESET Timing

1 2
CORESEL[3:0]/ LRESET/ NMI 3 LRESETNMIEN
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9.9 DDR3A and DDR3B Memory Controllers

The 72-bit DDR3 Memory Controller bus of the TCI6636K2H is used to interface to JEDEC standard-compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and does not share the bus with any other type of peripheral. 9.9.1 DDR3 Memory Controller Device-Specific Information The TCI6636K2H includes one 64-bit wide, 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS. Due to the complicated nature of the interface, a limited number of topologies are supported to provide a 16-bit, 32-bit, or 64-bit interface. The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank topologies to be supported by the interface: 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC) 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC) 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC) 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC) 64-bit: Four 16-bit SDRAMs 64-bit: Eight 8-bit SDRAMs 32-bit: Two 16-bit SDRAMs 32-bit: Four 8-bit SDRAMs 16-bit: One 16-bit SDRAM 16-bit: Two 8-bit SDRAMs The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes before signaling to master B that the message is ready, when master B attempts to read the software message, the master B read may bypass the master A write. Thus, master B may read stale data and receive an incorrect message. Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering in the software. If master A does not wait for an indication that a write is complete, it must perform the following workaround: 1. Perform the required write to DDR3 memory space. 2. Perform a dummy write to the DDR3 memory controller module ID and revision register. 3. Perform a dummy read to the DDR3 memory controller module ID and revision register. 4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.
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9.9.2 DDR3 Slew Rate Control The DDR3 slew rate is controlled by use of the PHY registers. See the KeyStone II DDR3 UserGuide in 1.10 Related Documentation from Texas Instruments on page 21 for details. 9.9.3 DDR3 Memory Controller Electrical Data/Timing The DDR3 Implementation Guidelines Application Report in 1.10 Related Documentation from Texas Instruments on page 21 specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met. Therefore, no electrical data/timing information is supplied here for this interface.
NoteTI supports only designs that follow the board design guidelines outlined in the application report.
9.10 I2C Peripheral

The Inter-Integrated Circuit (I2C) module provides an interface between DSP and other devices compliant with Philips Semiconductors (now NXP Semiconductors) Inter-Integrated Circuit bus specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the device through the I2C module. 9.10.1 I C Device-Specific Information The device includes multiple I C peripheral modules.
NoteWhen using the I
2 2 2 2
C module, ensure there are external pullup resistors on the SDA and SCL pins.
The I C modules on the TCI6636K2H may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.), communicate with other controllers in a system, or to implement a user interface. The I C port supports: 2 Compatibility with Philips I C specification revision 2.1 (January 2000) Fast mode up to 400 kbps (no fail-safe I/O buffers) Noise filter to remove noise of 50 ns or less 7-bit and 10-bit device addressing modes Multi-master (transmit/receive) and slave (transmit/receive) functionality Events: DMA, interrupt, or polling Slew-rate limited open-drain output buffers
2
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Figure 9-32 shows a block diagram of the I C module.

Figure 9-32 I2C Module Block Diagram
I C Module Clock Prescale I CPSC Control Bit Clock Generator Noise Filter I CCLKH I2CCLKL I2CMDR I CCNT Transmit Shift Transmit Buffer Interrupt/DMA Noise Filter Receive I2CDRR Receive Buffer Receive Shift I CIMR I CSTR I CIVR
2 2 2 2 2 2 2
Peripheral Clock (CPU/6)
SCL I C Clock
2
I COAR I2CSAR
Own Address Slave Address Mode Data Count Extended Mode
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2
Transmit I2CXSR
I2CEMDR
I CDXR SDA I2C Data
Interrupt Mask/Status Interrupt Status Interrupt Vector
I CRSR
Shading denotes control/status registers.
9.10.2 I C Peripheral Register Description

Table 9-38
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030
I2C Registers (Part 1 of 2)

Acronym ICOAR ICIMR ICSTR ICCLKL ICCLKH ICCNT ICDRR ICSAR ICDXR ICMDR ICIVR ICEMDR ICPSC Register Name I C Own Address Register I C Interrupt Mask/status Register I2C Interrupt Status Register I C Clock Low-time Divider Register I C Clock High-time Divider Register I2C Data Count Register I C Data Receive Register I C Slave Address Register I2C Data Transmit Register I C Mode Register I C Interrupt Vector Register I2C Extended Mode Register I C Prescaler Register
2 2 2 2 2 2 2 2 2
Hex Address Offsets
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SPRS835DAugust 2013 I C Registers (Part 2 of 2)

Acronym ICPID1 ICPID2 Register Name I C Peripheral Identification Register 1 [value: 0x0000 0105] I C Peripheral Identification Register 2 [value: 0x0000 0005] Reserved
2 2
Table 9-38
0x0034 0x0038 0x003C -0x007F
Hex Address Offsets
End of Table 9-38
9.10.3 I C Electrical Data/Timing

9.10.3.1 Inter-Integrated Circuits (I C) Timing
Table 9-39
(see Figure 9-33) Standard Mode No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tc(SCL) tsu(SCLH-SDAL) th(SDAL-SCLL) tw(SCLL) tw(SCLH) tsu(SDAV-SCLH) th(SCLL-SDAV) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(SCLH-SDAH) tw(SP) Cb
2
I2C Timing Requirements
(1)
Fast Mode Min 2.5 0.6 0.6 1.3 0.6 100 (2)
(3) (4)
Min Cycle time, SCL Setup time, SCL high before SDA low (for a repeated START condition) Hold time, SCL low after SDA low (for a START and a repeated START condition) Pulse duration, SCL low Pulse duration, SCL high Setup time, SDA valid before SCL high Hold time, SDA valid after SCL low (for I C bus devices) Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Setup time, SCL high before SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line 4
2
Max
Max Units s s s s s ns 0.9 s s 300 300 300 300 ns ns ns ns s 50 400 ns pF
10 4.7 4 4.7 4 250 0

(3)
3.45
4.7 1000 1000 300 300
1.3 20 + 0.1Cb (5) 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb

(5) (5) (5)
0.6 0 400
(5)
End of Table 9-39

1 The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. 2 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the 2 SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I C-Bus Specification) before the SCL line is released. 3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 4 The maximum th(SDA-SCLL) has to be met only if the device does not stretch the low period [tw(SCLL)] of the SCL signal. 5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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2 I C Receive Timings
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11 SDA 8 4 10 SCL 1 7 3 Stop Start Repeated Start 12 2 3 5 6 14 13
Stop
PRODUCT PREVIEW
Table 9-40
(see Figure 9-34)
I2C Switching Characteristics (1)

Standard Mode Fast Mode Min 2.5 0.6 0.6 1.3 0.6 100 0 1.3 1000 1000 300 300 4 10 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb
(1) (1) (1) (1)
No. 16 17 18 19 20 21 22 23 24 25 26 27 28 tc(SCL) tsu(SCLH-SDAL) th(SDAL-SCLL) tw(SCLL) tw(SCLH) td(SDAV-SDLH) tv(SDLL-SDAV) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) td(SCLH-SDAH) Cp End of Table 9-40 Cycle time, SCL
Parameter
Min 10 4.7 4 4.7 4 250

2
Max
Max Unit ms ms ms ms ms ns 0.9 ms ms 300 300 300 300 ns ns ns ns ms 10 pF
Setup time, SCL high to SDA low (for a repeated START condition) Hold time, SDA low after SCL low (for a START and a repeated START condition) Pulse duration, SCL low Pulse duration, SCL high Delay time, SDA valid to SCL high Valid time, SDA valid after SCL low (for I C bus devices) Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Delay time, SCL high to SDA high (for STOP condition) Capacitance for each I2C pin
0 4.7
0.6
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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SPRS835DAugust 2013 I C Transmit Timings

26 24
2
Figure 9-34
SDA 23 19 25 SCL 16 22 18 Stop Start Repeated Start 27 18 17 20 21 28
9.11 SPI Peripheral

The Serial Peripheral Interconnect (SPI) module provides an interface between the DSP and other SPI-compliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot. The SPI module on TCI6636K2H is supported only in master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander. 9.11.1 SPI Electrical Data/Timing
Table 9-41
See Figure 9-35) No. Master Mode Timing Diagrams Base Timings for 3 Pin Mode 7 7 7 7 8 8 8 8 tsu(SPIDIN-SPC) tsu(SPIDIN-SPC) tsu(SPIDIN-SPC) tsu(SPIDIN-SPC) th(SPC-SPIDIN) th(SPC-SPIDIN) th(SPC-SPIDIN) th(SPC-SPIDIN) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0 Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1 Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0 Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1 Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0 Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1 Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0 Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1 2 2 2 2 5 5 5 5 ns ns ns ns ns ns ns ns Min Max Unit
SPI Timing Requirements
End of Table 9-41
Table 9-42
No.
SPI Switching Characteristics (Part 1 of 2)

Parameter Master Mode Timing Diagrams Base Timings for 3 Pin Mode Min
(1)
(See Figure 9-35 and Figure 9-36) Max Unit
1 2 3 4 4 4
tc(SPC) tw(SPCH) tw(SPCL) td(SPIDOUT-SPC) td(SPIDOUT-SPC) td(SPIDOUT-SPC)
Cycle time, SPICLK, all master modes Pulse width high, SPICLK, all master modes Pulse width low, SPICLK, all master modes Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK. Polarity = 0, Phase = 0. Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK. Polarity = 0, Phase = 1. Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK Polarity = 1, Phase = 0
3*P2
ns ns ns 5 5 5 ns ns ns
0.5*(3*P2) - 1 0.5*(3*P2) - 1
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Stop

No. 4 5 5 5 5 6 td(SPIDOUT-SPC) td(SPC-SPIDOUT) td(SPC-SPIDOUT) td(SPC-SPIDOUT) td(SPC-SPIDOUT)
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SPI Switching Characteristics (Part 2 of 2)

Parameter Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK Polarity = 1, Phase = 1 Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK. Polarity = 0 Phase = 0 Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 0 Phase = 1 Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 1 Phase = 0 Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK Polarity = 1 Phase = 1 0.5*tc - 2 0.5*tc - 2 0.5*tc - 2 0.5*tc - 2 Min Max 5 2 2 2 2 Unit ns ns ns ns ns ns ns ns ns
(See Figure 9-35 and Figure 9-36)
toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 0 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 1 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 0 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 1 Additional SPI Master Timings 4 Pin Mode with Chip Select Option
PRODUCT PREVIEW
6 6 6
19 19 19 19 20 20 20 20
td(SCS-SPC) td(SCS-SPC) td(SCS-SPC) td(SCS-SPC) td(SPC-SCS) td(SPC-SCS) td(SPC-SCS) td(SPC-SCS) tw(SCSH)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0 Phase = 0 Delay from SPISCSx\ active to first SPICLK. Polarity = 0 Phase = 1 Delay from SPISCSx\ active to first SPICLK. Polarity = 1 Phase = 0 Delay from SPISCSx\ active to first SPICLK. Polarity = 1 Phase = 1 Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 0 Phase = 0 Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 0 Phase = 1 Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 1 Phase = 0 Delay from final SPICLK edge to master deasserting SPISCSx\. Polarity = 1 Phase = 1 Minimum inactive time on SPISCSx\ pin between two transfers when SPISCSx\ is not held using the CSHOLD feature.
2*P2 - 5
2*P2 + 5 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns 2*P2 - 5 2*P2 + 5 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns 1*P2 - 5 1*P2 + 5 ns ns ns ns ns
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 1*P2 - 5 1*P2 + 5
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 2*P2 - 5
End of Table 9-42

1 P2=1/(SYSCLK1/6)
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SPRS835DAugust 2013 SPI Master Mode Timing Diagrams Base Timings for 3-Pin Mode
1 2 SPICLK 4 SPIDOUT MO(0) 7 SPIDIN MI(0) 8 MI(1) MI(n-1) MI(n) 5 MO(1) 6 MO(n-1) MO(n) 3 MASTER MODE POLARITY = 0 PHASE = 0
Figure 9-35
4 SPICLK 5 SPIDOUT MO(0) 7 SPIDIN MI(0) 8 MI(1) MI(n-1) MO(1) 6 MO(n-1)
MO(n)
MI(n)
MASTER MODE POLARITY = 1 PHASE = 0
SPICLK 5 SPIDOUT MO(0) 7 SPIDIN MI(0) 8 MI(1) MI(n-1) MI(n) MO(1) 6 MO(n-1) MO(n)
MASTER MODE POLARITY = 1 PHASE = 1 SPICLK 4 SPIDOUT MO(0) 7 SPIDIN MI(0) 8 MI(1) MI(n-1) MI(n) 5 MO(1) 6 MO(n-1) MO(n)
Figure 9-36
SPI Additional Timings for 4-Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT 19 SPICLK 20
SPIDOUT SPIDIN SPISCSx
MO(0) MI(0)
MO(1) MI(1)
MO(n-1) MI(n-1)
MO(n) MI(n)
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MASTER MODE POLARITY = 0 PHASE = 1

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9.12 HyperLink Peripheral

The TCI6636K2H includes HyperLinks for companion device interfaces. This is a four-lane SerDes interface designed to operate at up to 10 Gbps per lane from pin-to-pin. The interface is used to connect with external accelerators that are manufactured using TI libraries. The HyperLink lines must be connected with DC coupling. The interface includes the serial station management interfaces used to send power management and flow messages between devices. Each HyperLink interface consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire input buses and two 2-wire output buses. Each 2-wire bus includes a data signal and a clock signal.
Table 9-43
No. FL Interface
HyperLink Peripheral Timing Requirements

Min Max Unit
(see Figure 9-37, Figure 9-38 and Figure 9-39)
PRODUCT PREVIEW
1 2 3 6 7 6 7
tc(HYPTXFLCLK) tw(HYPTXFLCLKH) tw(HYPTXFLCLKL) tsu(HYPTXFLDAT-HYPTXFLCLKH) th(HYPTXFLCLKH-HYPTXFLDAT) tsu(HYPTXFLDAT-HYPTXFLCLKL) th(HYPTXFLCLKL-HYPTXFLDAT)
Clock period - HYPTXFLCLK (C1) High pulse width - HYPTXFLCLK Low pulse width - HYPTXFLCLK Setup time - HYPTXFLDAT valid before HYPTXFLCLK high Hold time - HYPTXFLDAT valid after HYPTXFLCLK high Setup time - HYPTXFLDAT valid before HYPTXFLCLK low Hold time - HYPTXFLDAT valid after HYPTXFLCLK low PM Interface
5.75 0.4*C1 0.6*C1 0.4*C1 0.6*C1 1 1 1 1
ns ns ns ns ns ns ns
1 2 3 6 7 6 7
tc(HYPRXPMCLK) tw(HYPRXPMCLK) tw(HYPRXPMCLK) tsu(HYPRXPMDAT-HYPRXPMCLKH) th(HYPRXPMCLKH-HYPRXPMDAT) tsu(HYPRXPMDAT-HYPRXPMCLKL) th(HYPRXPMCLKL-HYPRXPMDAT)
Clock period - HYPRXPMCLK (C3) High pulse width - HYPRXPMCLK Low pulse width - HYPRXPMCLK Setup time - HYPRXPMDAT valid before HYPRXPMCLK high Hold time - HYPRXPMDAT valid after HYPRXPMCLK high Setup time - HYPRXPMDAT valid before HYPRXPMCLK low Hold time - HYPRXPMDAT valid after HYPRXPMCLK low
5.75 0.4*C3 0.6*C3 0.4*C3 0.6*C3 1 1 1 1
End of Table 9-43
Table 9-44
No.
HyperLink Peripheral Switching Characteristics (Part 1 of 2)

Parameter FL Interface Min Max Unit
1 2 3 4 5 4 5
tc(HYPRXFLCLK) tw(HYPRXFLCLKH) tw(HYPRXFLCLKL) tosu(HYPRXFLDAT-HYPRXFLCLKH) toh(HYPRXFLCLKH-HYPRXFLDAT) tosu(HYPRXFLDAT-HYPRXFLCLKL) toh(HYPRXFLCLKL-HYPRXFLDAT)
Clock period - HYPRXFLCLK (C2) High pulse width - HYPRXFLCLK Low pulse width - HYPRXFLCLK Setup time - HYPRXFLDAT valid before HYPRXFLCLK high Hold time - HYPRXFLDAT valid after HYPRXFLCLK high Setup time - HYPRXFLDAT valid before HYPRXFLCLK low Hold time - HYPRXFLDAT valid after HYPRXFLCLK low PM Interface
6.4 0.4*C2 0.4*C2 0.25*C2-0.4 0.25*C2-0.4 0.25*C2-0.4 0.25*C2-0.4 0.6*C2 0.6*C2
1 2 3 4 5
tc(HYPTXPMCLK) tw(HYPTXPMCLK) tw(HYPTXPMCLK) tosu(HYPTXPMDAT-HYPTXPMCLKH) toh(HYPTXPMCLKH-HYPTXPMDAT)
Clock period - HYPTXPMCLK (C4) High pulse width - HYPTXPMCLK Low pulse width - HYPTXPMCLK Setup time - HYPTXPMDAT valid before HYPTXPMCLK high Hold time - HYPTXPMDAT valid after HYPTXPMCLK high
6.4 0.4*C4 0.4*C4 0.25*C2-0.4 0.25*C2-0.4 0.6*C4 0.6*C4
ns ns ns ns ns
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Parameter Min 0.25*C2-0.4 0.25*C2-0.4 Max Unit ns ns
Table 9-44
No. 4 5
tosu(HYPTXPMDAT-HYPTXPMCLKL) toh(HYPTXPMCLKL-HYPTXPMDAT)
Setup time - HYPTXPMDAT valid before HYPTXPMCLK low Hold time - HYPTXPMDAT valid after HYPTXPMCLK low
End of Table 9-44
Figure 9-37
HyperLink Station Management Clock Timing
1 2 3
Figure 9-38
HyperLink Station Management Transmit Timing

4 HYPTX<xx>CLK 5 4 5
HYPTX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 9-39
HyperLink Station Management Receive Timing

6 HYPRX<xx>CLK 7 6 7
HYPRX<xx>DAT
<xx> represents the interface that is being used: PM or FL
317
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9.13 UART Peripheral

The universal asynchronous receiver/transmitter (UART) module provides an interface between the device and a UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550 asynchronous communications element which, in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the C66x of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the C66x CorePac to be sent to the peripheral device. The C66x CorePac can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
Table 9-45
No. Receive Timing 4 5 5 6 6 6 tw(RXSTART) tw(RXH) tw(RXL) tw(RXSTOP1) tw(RXSTOP15) tw(RXSTOP2) Pulse width, receive start bit Pulse width, receive data/parity bit high Pulse width, receive data/parity bit low Pulse width, receive stop bit 1 Pulse width, receive stop bit 1.5 Pulse width, receive stop bit 2 Autoflow Timing Requirements 8 td(CTSL-TX) Delay time, CTS asserted to START bit transmit P (2) 5P ns End of Table 9-45
1 U = UART baud time = 1/programmed baud rate 2 P = 1/(SYSCLK1/6)
PRODUCT PREVIEW
UART Timing Requirements

Min
(1)
(see Figure 9-40 and Figure 9-41) Max Unit
0.96U
1.05U 1.05U 1.05U 1.05U 1.05U 1.05U
ns ns ns ns ns ns
0.96U 0.96U 0.96U 0.96U 0.96U
Figure 9-40
UART Receive Timing Waveform

4 5 Bit 0 Bit 1 Bit N-1 Bit N 5 Parity 6 Stop Idle Start
RXD
Stop/Idle
Start
Figure 9-41
UART CTS (Clear-to-Send Input) Autoflow Timing Waveform

8 TXD Bit N-1 Bit N Stop Start Bit 0
CTS
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Parameter Transmit Timing Min
(1)
Table 9-46
No.
(See Figure 9-42 and Figure 9-43) Max Unit
1 2 2 3 3 3
tw(TXSTART) tw(TXH) tw(TXL) tw(TXSTOP1) tw(TXSTOP15) tw(TXSTOP2)
Pulse width, transmit start bit Pulse width, transmit data/parity bit high Pulse width, transmit data/parity bit low Pulse width, transmit stop bit 1 Pulse width, transmit stop bit 1.5 Pulse width, transmit stop bit 2 Autoflow Timing Requirements
-2
U+2 U+2 U+2 U+2 1.5 * ('U + 2) 2 * ('U + 2)
ns ns ns ns ns ns
U-2 U-2 U-2 1.5 * (U - 2) 2 * (U - 2)

(2)
End of Table 9-46

1 U = UART baud time = 1/programmed baud rate 2 P = 1/(SYSCLK1/6)
Figure 9-42
UART Transmit Timing Waveform

1 2 Bit 0 Bit 1 Bit N-1 Bit N 2 Parity 3 Stop Idle Start
TXD
Stop/Idle
Start
Figure 9-43
UART RTS (Request-to-Send Output) Autoflow Timing Waveform

7 RXD Bit N-1 Bit N Stop Start
CTS
9.14 PCIe Peripheral

The two-lane PCI express (PCIe) module on TCI6636K2H provides an interface between the device and other PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed data transfer at rates up to 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide in .
9.15 Packet Accelerator

The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It maintains 8k multiple-in, multiple-out hardware queues and also provides checksum capability as well as some QoS capabilities. The PA enables a single IP address to be used for a multicore device and can process up to 1.5 Mpps. The Packet Accelerator is coupled with the Network Coprocessor. For more information, see the Packet Accelerator (PA) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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PRODUCT PREVIEW
td(RX-RTSH)
Delay time, STOP bit received to RTS deasserted
5P
ns

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9.16 Security Accelerator

The Security Accelerator (SA) provides wire-speed processing on 1 Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air interface security protocols. It functions on the packet level with the packet and the associated security context being one of the above three types. The Security Accelerator is coupled with the Network Coprocessor, and receives the packet descriptor containing the security context in the buffer descriptor and the data to be encrypted/decrypted in the linked buffer descriptor. For more information, see the Security Accelerator (SA) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
9.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem

The gigabit Ethernet (GbE) switch subsystem provides an efficient interface between the device and the networked community. The Ethernet Media Access Controller (EMAC) supports 10Base-T (10 Mbits/second), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with the Network Coprocessor. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. An address range is assigned to the TCI6636K2H. Each individual device has a 48-bit MAC address and consumes only one unique MAC address out of the range. There are two registers to hold these values, MACID1[31:0] (32 bits) and MACID2[15:0] (16 bits) . The bits of these registers are defined as follows:
Figure 9-44
31 MACID R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Legend: R = Read only; -x, value is indeterminate
PRODUCT PREVIEW
MACID1 Register (MMR Address 0x02620110)

0
Table 9-47
Bit 31-0 Field
MACID1 Register Field Descriptions

Description MAC ID. Lower 32 bits.
MAC ID
Figure 9-45
31
MACID2 Register (MMR Address 0x02620114)

24 CRC R+,cccc cccc 23 Reserved R,+rr rrrr 18 17 FLOW R,+z 16 BCAST R,+y 15 MACID R,+xxxx xxxx xxxx xxxx 0
Legend: R = Read only; -x, value is indeterminate
Table 9-48
Bit 31-24 23-18 17 Field
MACID2 Register Field Descriptions (Part 1 of 2)

Description Variable 000000 MAC Flow Control 0 = Off 1 = On
Reserved Reserved FLOW
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SPRS835DAugust 2013 MACID2 Register Field Descriptions (Part 2 of 2)

Description Default m/b-cast reception 0 = Broadcast 1 = Disabled MAC ID. Upper 16 bits.
Table 9-48
Bit 16 Field BCAST
15-0
MAC ID
End of Table 9-48
Figure 9-46
31
RFTCLK Select Register (CPTS_RFTCLK_SEL)

4 Reserved R-0 3 CPTS_RFTCLK_SEL RW - 0 0
Legend: R = Read only; -x, value is indeterminate
Table 9-49
Bit 31-4 3-0 Field
RFTCLK Select Register Field Descriptions

Description Reserved. Read as 0. Reference clock select. This signal is used to control an external multiplexer that selects one of 8 clocks for time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the TS_CTL register. 0000 = SYSCLK2 0001 = SYSCLK3 0010 = TIMI0 0011 = TIMI1 1000 = TSREFCLK Others = Reserved
Reserved CPTS_RFTCLK_SEL
End of Table 9-49
321
PRODUCT PREVIEW
There is a central processor time synchronization (CPTS) submodule in the Ethernet switch module that can be used for time synchronization. Programming this register selects the clock source for the CPTS_RCLK. See the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21for the register address and other details about the time synchronization submodule. The register CPTS_RFTCLK_SEL for reference clock selection of the time synchronization submodule is shown in Figure 9-46.

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9.18 SGMII Management Data Input/Output (MDIO)

The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the gigabit Ethernet (GbE) switch subsystem for correct operation. The module allows almost transparent operation of the MDIO interface, with very little attention from the C66x CorePac. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
Table 9-50
(see Figure 9-47) No. 1 tc(MDCLK) tw(MDCLKH) tw(MDCLKL) tsu(MDIO-MDCLKH) th(MDCLKH-MDIO) tt(MDCLK) End of Table 9-50 Cycle time, MDCLK Pulse duration, MDCLK high Pulse duration, MDCLK low Setup time, MDIO data input valid before MDCLK high Hold time, MDIO data input valid after MDCLK high Transition time, MDCLK Min 400 180 180 10 10 5 Max Unit ns ns ns ns ns ns
MDIO Timing Requirements
PRODUCT PREVIEW
2 3 4 5
Figure 9-47
MDIO Input Timing

1 MDCLK 2 MDIO (Input) 3 4 5
Table 9-51
(see Figure 9-48) No. 6
MDIO Switching Characteristics

Parameter Min Max 100 Unit ns
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
End of Table 9-51
Figure 9-48
MDIO Output Timing

1 MDCLK 6 MDIO (Ouput)
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9.19 Timers
The timers can be used to time events, count events, generate pulses, interrupt the CorePacs, and send synchronization events to the EDMA3 channel controller. 9.19.1 Timers Device-Specific Information The TCI6636K2H device has up to twenty 64-bit timers in total, of which Timer0 through Timer7 are dedicated to each of the up to eight C66x CorePacs as watchdog timers and can also be used as general-purpose timers. Timer16 through Timer19 are dedicated to each of the Cortex-A15 processor cores as a watchdog timer and can also be used as general-purpose timers.The remaining timers can be configured as general-purpose timers only, with each timer programmed as a 64-bit timer or as two separate 32-bit timers. When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses (rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable period. When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter. When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again. If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming Reset Type Status Register (RSTYPE) on page 294 and the type of reset initiated can set by programming Reset Configuration Register (RSTCFG) on page 296. For more information, see the 64-bit Timer (Timer 64) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 9.19.2 Timers Electrical Timing The tables and figures below describe the timing requirements and switching characteristics of the timers.
Table 9-52
(see Figure 9-49) No. 1 2 tw(TINPH) tw(TINPL) Pulse duration, high Pulse duration, low Min 12C 12C Max Unit ns ns
Timer Input Timing Requirements (1)
End of Table 9-52

1 C = 1/(SYSCLK1/6) clock frequency in ns
Table 9-53
(see Figure 9-49) No. 3 4 tw(TOUTH) tw(TOUTL)
Timer Output Switching Characteristics (1)

Parameter Pulse duration, high Pulse duration, low Min 12C - 3 12C - 3 Max Unit ns ns
End of Table 9-53

1 C = 1/(SYSCLK1/6) clock frequency in ns.
Figure 9-49
Timer Timing
1 2
TIMIx 3 TIMOx 4
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9.20 Rake Search Accelerator (RSA)

There are sixteen Rake Search Accelerators (RSAs) on the device. Each C66x CorePac has one set of directly-connected RSA pairs. The RSA is an extension of the C66x CorePac. The C66x CorePac performs send/receive to the RSAs via the .L and .S functional units.
9.21 Enhanced Viterbi-Decoder Coprocessor (VCP2)

The device has four high-performance embedded Viterbi Decoder Coprocessors (VCP2) that improve channel-decoding operations on-chip. Operating at SYSCLK1 clock divided by 3, each VCP2 can decode more than 762 12.2-Kbps 3G adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels when running at 333 MHz. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP2 and the C66x CorePac are carried out through the EDMA3 controller. The VCP2 supports: Unlimited frame sizes Code rates 3/4, 1/2, 1/3, 1/4, and 1/5 Constraint lengths 5, 6, 7, 8, and 9 Programmable encoder polynomials Programmable reliability and convergence lengths Hard and soft decoded decisions Tail and convergent modes Yamamoto logic Tail biting logic Various input and output FIFO lengths For more information, see the Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
PRODUCT PREVIEW
9.22 Turbo Decoder Coprocessor (TCP3d)

The TCI6636K2H has two high-performance embedded Turbo-Decoder Coprocessors (TCP3d) that speed up channel-decoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and WiMAX. Operating at SYSCLK1 divided by 2 or 3, the TCP3d processes data channels at a throughput of > 100 Mbps. For more information, see the Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
9.23 Turbo Encoder Coprocessor (TCP3e)

The TCI6636K2H has a high-performance Turbo-Encoder Coprocessor (TCP3e) (embedded in the BCP) that speeds up channel-encoding operations on-chip for WCDMA, HSPA, HSPA+, TD-SCDMA, LTE, and WiMAX. Operating at SYSCLK1 divided by 3, the TCP3e is capable of processing data channels at a throughput of > 200 Mbps. For more information, see the Turbo Encoder Coprocessor 3 (TCP3e) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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9.24 Bit Rate Coprocessor (BCP)

The BCP is a hardware accelerator for wireless infrastructure and performs most of the uplink and downlink layer 1 bit processing for 3G and 4G wireless standards. BCP supports LTE, LTE-A, FDD WCDMA, TD-SCDMA, and WiMAX 802.16-2009 standards. It supports various downlink processing blocks like CRC attachment, turbo encoding, rate matching, code block concatenation, scrambling, and modulation. BCP supports various uplink processing blocks like soft slicer, de-scrambler, de-concatenation, rate de-matching, and LLR combining. For more information, see the Bit Coprocessor (BCP) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
9.25 Serial RapidIO (SRIO) Port

The SRIO port on the device is a high-performance, low pin-count SerDes interconnect. SRIO interconnects in a baseband board design provide connectivity and control among the components. The device supports four 1 Serial RapidIO links or one 4 Serial RapidIO link. The SRIO interface is designed to operate at a data rate of up to 5 Gbps per differential pair. This equals 20 raw GBaud/s for the 4 SRIO port, or approximately 15 Gbps data throughput rate. The PHY part of the SRIO consists of the physical layer and includes the input and output buffers (each serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the parallel-to-serial/serial-to-parallel converters. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 9.25.1 Serial RapidIO Device-Specific Information The approach to specifying interface timing for the SRIO Port is different from other interfaces. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. The Serial RapidIO peripheral is a master peripheral in the device. It conforms to the RapidIO Interconnect Specification, Part VI: Physical Layer 1/4 LP-Serial Specification, Revision 1.3. For the SRIO port, Texas Instruments provides a PCB solution showing two TI SRIO-enabled DSPs connected together via a 4 SRIO link. TI has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met.
NoteTI supports only designs that follow the board design guidelines outlined in the application report.
9.26 General-Purpose Input/Output (GPIO)

9.26.1 GPIO Device-Specific Information The GPIO peripheral pins are used for general purpose input/output for the device. These pins are also used to configure the device at boot time. For more detailed information on device/peripheral configuration and the TCI6636K2H device pin muxing, see Device Configuration on page 235. These GPIO pins can also used to generate individual core interrupts (no support of bank interrupt) and EDMA events.
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9.26.2 GPIO Peripheral Register Description

Table 9-54
0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024
GPIO Registers
Acronym BINTEN DIR OUT_DATA SET_DATA CLR_DATA IN_DATA SET_RIS_TRIG CLR_RIS_TRIG SET_FAL_TRIG CLR_FAL_TRIG Register Name GPIO interrupt per bank enable register Reserved GPIO Direction Register GPIO Output Data Register GPIO Set Data Register GPIO Clear Data Register GPIO Input Data Register GPIO Set Rising Edge Interrupt Register GPIO Clear Rising Edge Interrupt Register GPIO Set Falling Edge Interrupt Register GPIO Clear Falling Edge Interrupt Register Reserved Reserved
Hex Address Offsets
PRODUCT PREVIEW
0x0028 0x002C 0x0030 0x008C 0x0090 - 0x03FF End of Table 9-54
9.26.3 GPIO Electrical Data/Timing

Table 9-55
(see Figure 9-50) No. 1 2 tw(GPOH) tw(GPOL) Pulse duration, GPOx high Pulse duration, GPOx low Min 12C 12C Max Unit ns ns
GPIO Input Timing Requirements
(1)
End of Table 9-55

Table 9-56
(see Figure 9-50) No. 3 4 tw(GPOH) tw(GPOL)
GPIO Output Switching Characteristics

Parameter Pulse duration, GPOx high Pulse duration, GPOx low
(1)
Min 36C - 8 36C - 8
Max
Unit ns ns
End of Table 9-56

1 C = 1/(SYSCLK1/6) clock frequency in ns
Figure 9-50
GPIO Timing
1 2
GPIx 3 GPOx 4
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9.27 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the C66x CorePacs. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is not broken. The Semaphore module has unique interrupts to each of the C66x CorePacs to identify when that CorePac has acquired the resource. Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated. The Semaphore module supports three masters and contains 32 semaphores that can be shared within the system. There are two methods of accessing a semaphore resource: Direct Access: A C66x CorePac directly accesses a semaphore resource. If free, the semaphore is granted. If not free, the semaphore is not granted. Indirect Access: A C66x CorePac indirectly accesses a semaphore resource by writing to it. Once the resource is free, an interrupt notifies the C66x CorePac that the resource is available.
9.28 Antenna Interface Subsystem 2 (AIF2)

The AIF2 transfers data between the external RF units and the C66x CorePacs, RAC, TAC, and the FFTC modules via the TeraNet. The external AIF2 interface connects the AIF2 with either RF units and/or other baseband OBSAI/CPRI devices. The AIF2 has 11 timer synchronization events from the AIF2 Timer (AT) module: Timer synchronization events 0-3 are routed as primary events to the EDMA3CC1 and also as secondary events to the C66x CorePacs via CIC2. Timer synchronization events 3-7 are routed as primary events to the EDMA3CC2. Timer synchronization events 8, 9, and 10 are hard-wired to TAC, RAC_0, and RAC_1 respectively.
Table 9-57
No. RP1 Clock and Frameburst 1 1 2 3 3 2 4 4 4 4 5 5 6 6 7 7 7 7 tc(RP1CLKN) tc(RP1CLKP) tw(RP1CLKNL) tw(RP1CLKNH) tw(RP1CLKPL) tw(RP1CLKPH) tr(RP1CLKN) tf(RP1CLKN) tr(RP1CLKP) tf(RP1CLKP) tj(RP1CLKN) tj(RP1CLKP) tw(RP1FBN) tw(RP1FBP) tr(RP1CLKN) tf(RP1CLKN) tr(RP1CLKP) tf(RP1CLKP) Cycle time, RP1CLK(N) Cycle time, RP1CLK(P) Pulse duration, RP1CLK(N) low Pulse duration, RP1CLK(N) high Pulse duration, RP1CLK(P) low Pulse duration, RP1CLK(P) high Rise time - RP1CLKN 10% to 90% Fall time - RP1CLKN 90% to 10% Rise time - RP1CLKP 10% to 90% Fall time - RP1CLKP 90% to 10% Period jitter (peak-to-peak), RP1CLK(N) Period jitter (peak-to-peak), RP1CLK(P) Bit period, RP1FB(N) Bit period, RP1FB(P) Rise time - RP1FBN 10% to 90% Fall time - RP1FBN 90% to 10% Rise time - RP1FBP 10% to 90% Fall time - RP1FBP 90% to 10% 8 * C1 8 * C1 32.55 32.55 0.4 * C1
(1)
AIF2 Timer Module Timing Requirements (Part 1 of 2)

Min Max Unit
See Figure 9-49, Figure 9-52, Figure 9-53, and Figure 9-54
32.55 32.55 0.6 * C1 0.6 * C1 0.6 * C1 0.6 * C1 350.00 350.00 350.00 350.00 600 600 8 * C1 8 * C1 350.00 350.00 350.00 350.00
ns ns ns ns ns ns ps ps ps ps ps ps ns ns ps ps ps ps
0.4 * C1 0.4 * C1 0.4 * C1
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No. 8 8 8 8 9 9 9 9 tsu(RP1FBN-RP1CLKP) tsu(RP1FBN-RP1CLKN) tsu(RP1FBN-RP1CLKP) tsu(RP1FBN-RP1CLKN) th(RP1FBN-RP1CLKP) th(RP1FBN-RP1CLKN) th(RP1FBN-RP1CLKP) th(RP1FBN-RP1CLKN) Setup time - RP1FBN valid before RP1CLKP high Setup time - RP1FBN valid before RP1CLKN low Setup time - RP1FBP valid before RP1CLKP high Setup time - RP1FBP valid before RP1CLKN low Hold time - RP1FBN valid after RP1CLKP high Hold time - RP1FBN valid after RP1CLKN low Hold time - RP1FBP valid after RP1CLKP high Hold time - RP1FBP valid after RP1CLKN low PHY Sync and Radio Sync Pulses
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AIF2 Timer Module Timing Requirements (Part 2 of 2)

Min 2 2 2 2 2 2 2 2 Max Unit ns ns ns ns ns ns ns ns
See Figure 9-49, Figure 9-52, Figure 9-53, and Figure 9-54
PRODUCT PREVIEW
10 11 12 13
tw(PHYSYNCH) tc(PHYSYNC) tw(RADSYNCH) tc(RADSYNC)
Pulse duration, PHYSYNC high Cycle time, PHYSYNC pulse to PHYSYNC pulse Pulse duration, RADSYNC high Cycle time, RADSYNC pulse to RADSYNC pulse
6.50 10.00 6.50 1.00
ns ms ns ms
End of Table 9-57

1 C1 = tc(RP1CLKN/P)
Figure 9-51
AIF2 RP1 Frame Synchronization Clock Timing

1 2 RP1CLKN RP1CLKP 4 5 3
Figure 9-52
RP1CLKN RP1CLKP
AIF2 RP1 Frame Synchronization Burst Timing

6
RP1FBP/N 7
RP1 Frame Burst BIT 0 8 9
RP1 Frame Burst BIT 2
RP1 Frame Burst BIT N
Figure 9-53
AIF2 Physical Layer Synchronization Pulse Timing

11 10
PHYSYNC
Figure 9-54
AIF2 Radio Synchronization Pulse Timing

13 12
RADSYNC
328

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SPRS835DAugust 2013 AIF2 Timer Module Switching Characteristics

Parameter External Frame Event Min
(1)
Table 9-58
(see Figure 9-55) No.
Max
Unit
14 15
tw(EXTFRAMEEVENTH) tw(EXTFRAMEEVENTL)
Pulse width, EXTFRAMEEVENT output high Pulse width, EXTFRAMEEVENT output low
4 * C1 4 * C1
ns ns
End of Table 9-58

1 C1 = tc(RP1CLKN/P)
Figure 9-55
AIF2 Timer External Frame Event Timing

14 15
9.29 Receive Accelerator Coprocessor (RAC)

The TCI6636K2H has two Receive Accelerator Coprocessor (RAC) subsystems. Each RAC subsystem is a receive chip-rate accelerator based on a generic correlator coprocessor (GCCP). It supports Universal Mobile Telecommunications System (UMTS) operations and assists in transferring data received from the antenna to the receive core and performs receive functions that target the WCDMA macro bits. The RAC subsystem consists of several components: Two GCCP accelerators for finger despread (FD), path monitor (PM), preamble detection (PD), and stream power estimator (SPE) Back-end interface (BEI) for management of the RAC configuration and the data output. Front-end interface (FEI) for reception of the antenna data for processing and access to all MMRs (memory-mapped registers) and memories in the RAC components The RAC has a total of three ports connected to the switch fabric: BEI includes two master connections to the switch fabric for output data to device memory. One is 128-bit and the other is 64-bit. Both are clocked at a SYSCLK1 divided by 3 or 4 rate. The FEI has a 64-bit slave connection to the switch fabric for input data as well as direct memory access (to facilitate debug)
9.30 Transmit Accelerator Coprocessor (TAC)

The Transmit Accelerator Coprocessor (TAC) subsystem is a transmit chip-rate accelerator for support of UMTS (Universal Mobile Telecommunications System) applications.
9.31 Fast Fourier Transform Coprocessor (FFTC)

There are four Fast Fourier Transform Coprocessors (FFTC) used to accelerate FFT, IFFT, DFT, and IDFT operations. For more information, see the Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
329
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EXT FRAME EVENT

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9.32 Universal Serial Bus 3.0 (USB 3.0)

The device includes a USB 3.0 controller providing the following capabilities: Support of USB 3.0 peripheral (or device) mode at the following speeds: Super Speed (SS) (5 Gbps) High Speed (HS) (480 Mbps) Full Speed (FS) (12 Mbps) Support of USB 3.0 host mode at the following speeds: Super Speed (SS) (5 Gbps) High Speed (HS) (480 Mbps) Full Speed (FS) (12 Mbps) Low Speed (LS) (1.5 Mbps) Integrated DMA controller with extensible Host Controller Interface (xHCI) support Support for 14 transmit and 14 receive endpoints plus control EP0 For more information, see the Universal Serial Bus (USB) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21.
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9.33 Universal Subscriber Identity Module (USIM)

The TCI6636K2H is equipped with a Universal Subscriber Identity Module (USIM) for user authentication. The USIM is compatible with ISO, ETSI/GSM, and 3GPP standards. The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details.
9.34 EMIF16 Peripheral

The EMIF16 module provides an interface between the device and external memories such as NAND and NOR flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide in 1.10 Related Documentation from Texas Instruments on page 21. 9.34.1 EMIF16 Electrical Data/Timing
Table 9-59
No. General Timing 2 28 14 tw(WAIT) td(WAIT-WEH) td(WAIT-OEH) Pulse duration, WAIT assertion and deassertion minimum time Setup time, WAIT asserted before WE high Setup time, WAIT asserted before OE high 2E 4E + 3 4E + 3 ns ns ns
EMIF16 Asynchronous Memory Timing Requirements (1) (Part 1 of 2)

Min Max Unit
(see Figure 9-56 through Figure 9-59)
330

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SPRS835DAugust 2013 EMIF16 Asynchronous Memory Timing Requirements

(1)
Table 9-59
No.
(Part 2 of 2)
Min Max Unit
(see Figure 9-56 through Figure 9-59)
Read Timing 3 3 4 5 4 5 6 7 8 9 10 10 11 12 13 tC(CEL) tC(CEL) tosu(CEL-OEL) toh(OEH-CEH) tosu(CEL-OEL) toh(OEH-CEH) tosu(BAV-OEL) toh(OEH-BAIV) tosu(AV-OEL) toh(OEH-AIV) tw(OEL) tw(OEL) td(WAITH-OEH) tsu(D-OEH) th(OEH-D) EMIF read cycle time when ew = 0, meaning not in extended wait mode EMIF read cycle time when ew =1, meaning extended wait mode enabled Output setup time from CE low to OE low. SS = 0, not in select strobe mode Output hold time from OE high to CE high. SS = 0, not in select strobe mode Output setup time from CE low to OE low in select strobe mode, SS = 1 Output hold time from OE high to CE high in select strobe mode, SS = 1 Output setup time from BA valid to OE low Output hold time from OE high to BA invalid Output setup time from A valid to OE low Output hold time from OE high to A invalid OE active time low, when ew = 0. Extended wait mode is disabled. OE active time low, when ew = 1. Extended wait mode is enabled. Delay time from WAIT deasserted to OE# high Input setup time from D valid to OE high Input hold time from OE high to D invalid Write Timing 15 15 16 17 16 17 18 19 20 21 22 23 24 24 26 27 25 tc(CEL) tc(CEL) tosuCEL-WEL) toh(WEH-CEH) tosuCEL-WEL) toh(WEH-CEH) tosu(RNW-WEL) toh(WEH-RNW) tosu(BAV-WEL) toh(WEH-BAIV) tosu(AV-WEL) toh(WEH-AIV) tw(WEL) tw(WEL) tosu(DV-WEL) toh(WEH-DIV) td(WAITH-WEH) EMIF write cycle time when ew = 0, meaning not in extended wait mode (WS+WST+WH+ (WS+WST+WH+ TA+4)*E-3 TA+4)*E+3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4E + 3 ns 3 0.5 (RS+RST+RH+3) *E-3 (RS+RST+RH+3) *E-3 (RS+1) * E - 3 (RH+1) * E - 3 (RS+1) * E - 3 (RH+1) * E - 3 (RS+1) * E - 3 (RH+1) * E - 3 (RS+1) * E - 3 (RH+1) * E - 3 (RST+1) * E - 3 (RST+1) * E - 3 (RS+RST+RH+3) *E+3 (RS+RST+RH+3) *E+3 (RS+1) * E + 3 (RH+1) * E + 3 (RS+1) * E + 3 (RH+1) * E + 3 (RS+1) * E + 3 (RH+1) * E + 3 (RS+1) * E + 3 (RH+1) * E + 3 (RST+1) * E + 3 (RST+1) * E + 3 4E + 3 ns ns ns ns ns ns
ns ns ns ns ns ns ns ns
EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WH+ (WS+WST+WH+ TA+4)*E-3 TA+4)*E+3 Output setup time from CE low to WE low. SS = 0, not in select strobe mode Output hold time from WE high to CE high. SS = 0, not in select strobe mode Output setup time from CE low to WE low in select strobe mode, SS = 1 Output hold time from WE high to CE high in select strobe mode, SS = 1 Output setup time from RNW valid to WE low Output hold time from WE high to RNW invalid Output setup time from BA valid to WE low Output hold time from WE high to BA invalid Output setup time from A valid to WE low Output hold time from WE high to A invalid WE active time low, when ew = 0. Extended wait mode is disabled. WE active time low, when ew = 1. Extended wait mode is enabled. Output setup time from D valid to WE low Output hold time from WE high to D invalid Delay time from WAIT deasserted to WE# high (WS+1) * E - 3 (WH+1) * E - 3 (WS+1) * E - 3 (WH+1) * E - 3 (WS+1) * E - 3 (WH+1) * E - 3 (WS+1) * E - 3 (WH+1) * E - 3 (WS+1) * E - 3 (WH+1) * E - 3 (WST+1) * E - 3 (WST+1) * E - 3 (WS+1) * E - 3 (WH+1) * E - 3
End of Table 9-59

1 E = 1/(SYSCLK1/6)
331
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ns

SPRS835DAugust 2013 Figure 9-56 EMIF16 Asynchronous Memory Read Timing Diagram
3 EM_CE[3:0]
EM_R/W
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EM_BA[1:0] EM_A[21:0] 4 6 8 10 EM_OE 5 7 9
PRODUCT PREVIEW
12 EM_D[15:0] EM_WE
13
Figure 9-57
EMIF16 Asynchronous Memory Write Timing Diagram

15
EM_CE[3:0] EM_R/W EM_BA[1:0] EM_A[21:0] 16 18 20 22 24 EM_WE 26 27 EM_D[15:0] EM_OE 17 19 21 23
332

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SPRS835DAugust 2013 EMIF16 EM_WAIT Read Timing Diagram

Setup EM_CE[3:0] EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_OE 14 11 2 EM_WAIT Asserted 2 Strobe Extended Due to EM_WAIT Strobe Hold
Figure 9-58
Figure 9-59
EMIF16 EM_WAIT Write Timing Diagram

Setup Strobe Extended Due to EM_WAIT Strobe Hold
EM_CE[3:0] EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_WE 28 25 2 EM_WAIT Asserted 2 Deasserted
333
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Deasserted

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9.35 Emulation Features and Capability

The debug capabilities of KeyStoneII devices include the Debug subsystem module (DEBUGSS). The DEBUGSS module contains the ICEPick module which handles the external JTAG Test Access Port (TAP) and multiple secondary TAPs for the various processing cores of the device. It also provides Debug Access Port (DAP) for system wide memory access from debugger, Cross triggering, System trace, Peripheral suspend generation, Debug port (EMUx) pin management etc. The DEBUGSS module works in conjunction with the debug capability integrated in the processing cores (ARM and DSP subsystems) to provide a comprehensive hardware platform for a rich debug and development experience. 9.35.1 Chip Level Features Support for 1149.1(JTAG and Boundary scan) and 1149.6 (Boundary scan extensions). Trace sources to DEBUG SubSystem System Trace Module (DEBUGSS STM) Provides a way for hardware instrumentation and software messaging to supplement the processor core trace mechanisms. Hardware instrumentation support of CPTracers to support logging of bus transactions for critical endpoints Software messaging/instrumentation support for DSP and QMSS PDSP cores through DEBUGSS STM. Trace Sinks Support for trace export (from all processor cores and DEBUGSS STM) through emulation pins. Concurrent trace of DSP and STM traces or ARM and STM traces via EMU pins is possible. Concurrent trace export of DSP and ARM is not possible via EMU pins. Support for 32KB DEBUGSS TBR (Trace Buffer and Router) to hold system trace. The data can be drained using EDMA to on-chip or DDR memory buffers. These intermediate buffers can subsequently be drained through the device high speed interfaces. The DEBUGSS TBR is dedicated to the DEBUGSS STM module.The trace draining interface used in KeyStone II for DEBUGSS and ARMSS are based on the new CT-TBR. Cross triggering: Provides a way to propagate debug (trigger) events from one processor/subsystem/module to another Cross triggering between multiple devices via EMU0/EMU1 pins Cross triggering between multiple processing cores within the device like ARM/DSP Cores and non-processor entities like ARM STM (input only), CPTracers, CT-TBRs and DEBUGSS STM (input only) Synchronized starting and stopping of processing cores Global start of all ARM cores Global start of all DSP cores Global stopping of all ARM and DSP cores Emulation mode aware peripherals (suspend features and debug access features) Support system memory access via the DAP port (natively support 32-bit address, and it can support 36-bit address through configuration of MPAX inside MSMC). Debug access to any invalid memory location (reserved/clock-gated/power-down) shall not cause system hang. Scan access to secondary TAPs of DEBUGSS shall be disabled in Secure devices by default. Security override sequence shall be supported (requires software override sequence) to enable debug in secure devices. In addition, Debug features of the ARM cores are blockable through the ARM debug authentication interface in secure devices. Support WIR (wait-in-reset) debug boot mode for Non-secure devices. Debug functionality shall survive all pin resets except power-on resets (POR/RESETFULL) and test reset (TRST). PDSP Debug features like access/control through DAP, Halt mode debug and software instrumentation.
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334

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9.35.1.1 ARM Subsystem Features
9.35.1.2 DSP Features
Support for Halt-mode debug Support for Real-time debug Support for Monitor mode debug Advanced Event Triggering (AET) for data/PC watch-points, event monitoring and visibility into external events Support for PC/Timing/Data/Event trace. TETB (TI Embedded Trace Buffer) of 4KB to store PC/Timing/Data/Event trace. The trace data is copied by EDMA to external memory for draining by device high speed serial interfaces or it can be drained through EMUx pins Support for Cross triggering source/sink to other C66x CorePacs and device subsystems. Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems application report For more information on the AET, see the following documents in 1.10 Related Documentation from Texas Instruments on page 21: 9.35.2 ICEPick Module The debugger is connected to the device through its external JTAG interface. The first level of debug interface seen by the debugger is connected to the ICEPick module embedded in the DEBUGSS. ICEPick is the chip-level TAP, responsible for providing access to the IEEE 1149.1 and IEEE1149.6 boundary scan capabilities of the device. The device has multiple processors, some with secondary JTAG TAPs (C66x CorePacs) and others with an APB memory mapped interface (ARM CorePac and Coresight components). ICEPick manages the TAPs as well as the power/reset/clock controls for the logic associated with the TAPs as well as the logic associated with the APB ports. ICEPick provides the following debug capabilities: Debug connect logic for enabling or disabling most ICEPick instructions
335
PRODUCT PREVIEW
Support for invasive debug like halt mode debugging (breakpoint, watchpoints) and monitor mode debugging Support for non-invasive debugging (program trace, performance monitoring) Support for A15 Performance Monitoring Unit (cycle counters) Support for per core CoreSight Program Trace Module (CS-PTM) with timing Support for an integrated CoreSight System Trace Module (CS-STM) for hardware event and software instrumentation A shared timestamp counter for all ARM cores and STM is integrated in ARMSS for trace data correlation Support for a 16KB Trace Buffer and Router (TBR) to hold PTM/STM trace. The trace data is copied by EDMA to external memory for draining by device high speed serial interfaces. Support for simultaneous draining of trace stream through EMUn pins and TBR (to achieve higher aggregate trace throughput) Support for debug authentication interface to disable debug accesses in secure devices Support for cross triggering between MPU cores, CS-STM and CT-TBR Support for debug through warm reset

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Dynamic TAP insertion Serially linking up to 32 TAP controllers Individually selecting one or more of the TAPS for scan without disrupting the instruction register (IR) state of other TAPs Power, reset and clock management Provides the power and clock status of the domain to the debugger Provides debugger control of the power domain of a processor. Force the domain power and clocks on Prohibit the domain from being clock-gated or powered down Applies system reset Provides wait-in-reset (WIR) boot mode Provides global and local WIR release Provides global and local reset block
PRODUCT PREVIEW
The ICEPick module implements a connect register, which must be configured with a predefined key to enable the full set of JTAG instructions. Once the debug connect key has been properly programmed, ICEPick signals and subsystems emulation logic should be turned on.
9.35.2.1 ICEPick Dynamic Tap Insertion
To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP router to program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively choose which subsystem TAPs are accessible through the device-level debug interface. Each secondary TAP can be dynamically included in or excluded from the scan path. From external JTAG interface point of view, secondary TAPS that are not selected appear not to exist. There are two types of components connected through ICEPick to external debug interface: Legacy JTAG Components C66x implements a JTAG-compatible port and are directly interfaced with ICEPick and individually attached to an ICEPick secondary TAP. CoreSight Components The CoreSight components are interfaced with ICEPick through the CS_DAP module. The CS_DAP is attached to the ICEPick secondary TAP and translates JTAG transactions into APBv3 transactions. Table 9-60 shows the ICEPick secondary taps in the system. For more details on the test related P1500 TAPs, please refer to the DFTSS specification.
Table 9-60
Tap # 0 1 2 3 4 5 6 7 8 9..13 Type n/a JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG
ICEPick Debug Secondary TAPs (Part 1 of 2)

Name n/a C66x CorePac0 C66x CorePac1 C66x CorePac2 C66x CorePac3 C66x CorePac4 C66x CorePac5 C66x CorePac6 C66x CorePac7 Reserved IR Scan Length n/a 38 38 38 38 38 38 38 38 NA Access in Secure Device Description No No No No No No No No No No RESERVED (This is an internal TAP and not exposed at the DEBUGSS boundary) C66x CorePac0 C66x CorePac1 C66x CorePac2 C66x CorePac3 C66x CorePac4 C66x CorePac5 C66x CorePac6 C66x CorePac7 Spare ports for future expansion
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SPRS835DAugust 2013 ICEPick Debug Secondary TAPs (Part 2 of 2)

Name IR Scan Length Access in Secure Device Description No ARM A15 Cores (This is an internal TAP and not exposed at the DEBUGSS boundary) PDSP Cores (This is an internal TAP and not exposed at the DEBUGSS boundary)
Table 9-60
Tap # 14 Type CS
CS_DAP (APB-AP) 4 CS_DAP (AHB-AP)
End of Table 9-60
For more information on ICEPick, see the Debug and Trace for KeyStoneII Devices in 1.10 Related Documentation from Texas Instruments on page 21.
9.36 Debug Port (EMUx)
NoteNote that if EMU[1:0] signals are shared for cross-triggering purposes in the board level, they
SHOULD NOT be used for trace purposes.

Table 9-61 Emulation Interface with Different Debug Port Configurations (Part 1 of 2)
ARM Trace TRCDTa[29] TRCDTb[31] TRCDTa[28] TRCDTb[30] TRCDTa[27] TRCDTb[29] TRCDTa[26] TRCDTb[28] TRCDTa[25] TRCDTb[27] TRCDTa[24] TRCDTb[26] TRCDTa[23] TRCDTb[25] TRCDTa[22] TRCDTb[24] TRCDTa[21] TRCDTb[23] TRCDTa[20] TRCDTb[22] TRCDTa[19] TRCDTb[21] TRCDTa[19] TRCDTa[18] TRCDTb[20] TRCDTa[18] DSP Trace STM TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state Debug Boot Mode
Cross EMU Pins Triggering EMU33 EMU32 EMU31 EMU30 EMU29 EMU28 EMU27 EMU26 EMU25 EMU24 EMU23 EMU22 EMU21 EMU20 EMU19
TRCDTa[17] TRCDTb[19] TRCDTa[17] TRCDTb[19] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[16] TRCDTb[18] TRCDTa[16] TRCDTb[18] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[15] TRCDTb[17] TRCDTa[15] TRCDTb[17] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state
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The device also supports 34 emulation pins EMU[33:0], which includes 19 dedicated EMU pins and 15 pins multiplexed with GPIO. These pins are shared by A15/DSP/STM trace, cross triggering, and debug bootmodes as shown in Table 9-64. The 34-pin dedicated emulation interface is also defined in the following table.

SPRS835DAugust 2013 Table 9-61 Emulation Interface with Different Debug Port Configurations (Part 2 of 2)
ARM Trace DSP Trace STM Debug Boot Mode
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Cross EMU Pins Triggering EMU18 EMU17 EMU16 EMU15 EMU14 EMU13 EMU12 EMU11 EMU10 EMU9 EMU8 EMU7 EMU6 EMU5 EMU4 EMU3 EMU2 EMU1 EMU0 Trigger1 Trigger0
TRCDTa[14] TRCDTb[16] TRCDTa[14] TRCDTb[16] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[13] TRCDTb[15] TRCDTa[13] TRCDTb[15] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[12] TRCDTb[14] TRCDTa[12] TRCDTb[14] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[11] TRCDTb[13] TRCDTa[11] TRCDTb[13] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[10] TRCDTb[12] TRCDTa[10] TRCDTb[12] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTa[9] TRCDTa[8] TRCDTa[7] TRCDTa[6] TRCDTa[5] TRCDTa[4] TRCDTa[3] TRCDTa[2] TRCDTa[1] TRCDTa[0] TRCCTRL TRCCLK TRCDTb[11] TRCDTa[9] TRCDTb[10] TRCDTa[8] TRCDTb[9] TRCDTb[8] TRCDTb[7] TRCDTb[6] TRCDTb[5] TRCDTb[4] TRCDTb[3] TRCDTb[2] TRCCTRL TRCCLK TRCDTb[1] TRCDTb[0] TRCDTa[7] TRCDTa[6] TRCDTa[5] TRCDTa[4] TRCDTa[3] TRCDTa[2] TRCDTa[1] TRCDTa[0] TRCCLKB TRCCLKA TRCDTb[11] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTb[10] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDTb[9] TRCDTb[8] TRCDTb[7] TRCDTb[6] TRCDTb[5] TRCDTb[4] TRCDTb[3] TRCDTb[2] TRCCLKB TRCCLKA TRCDTb[1] TRCDTb[0] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or TRCCLK, or Tri-state dbgbootmode[1] dbgbootmode[0]
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End of Table 9-61
9.36.1 Concurrent Use of Debug Port Following combinations are possible concurrently: Trigger 0/1 Trigger 0/1 and STM Trace (upto 4 datapins) Trigger 0/1 and STM Trace (upto 4 datapins) and C66x Trace (upto 20 datapins) Trigger 0/1 and STM Trace (1-4 datapins) and ARM Trace (27-24 datapins) STM Trace (1-4 datapins) and ARM Trace (29-26 data pins) Trigger 0/1 and ARM Trace (upto 29 data pins) ARM Trace (upto 32 datapins)

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ARM and DSP simultaneous trace is not supported. 9.36.2 Master ID for HW and SW Messages Table 9-62 describes the master ID for the various hardware and software masters of the STM.
Table 9-62
CPTracer Name CPT_MSMCx_MST, where x = 0..3 CPT_MSMC4_MST CPT_MSMCx_MST, where x = 5..7 CPT_DDR3A_MST CPT_L2_x_MST, where x = 0..7 CPT_TPCC0_4_MST CPT_TPCC1_2_3_MST CPT_INTC_MST CPT_SM_MST CPT_QM_CFG1_MST CPT_QM_CFG2_MST CPT_QM_M_MST CPT_SPI_ROM_EMIF16 _MST CPT_CFG_MST CPT_RAC_FEI_MST CPT_RAC_CFG1_MST CPT_TAC_BE_MST CPT_BCR_CFG_MST CPT_RAC_CFG2_MST CPT_DDR3B_MST End of Table 9-62
MSTID mapping for Hardware Instrumentation (CPTRACERS)

MSTID [7:0] 0x94-0x97 0xB1 0xAE - 0xB0 0x98 0x8C - 0x93 0xA4 0xA5 0xA6 0x99 0x9A 0xA0 0x9B 0xA7 0x9C 0x9D 0x9E 0x9F 0xA3 0xA2 0xA1 Clock domain SYSCLK1/1 SYSCLK1/1 SYSCLK1/1 SYSCLK1/1 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SYSCLK1/3 SID[4:0] 0x0..3 0x4 0x5..7 0x8 0x9..0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Description MSMC SRAM Bank 0 to MSMC SRAM Bank 3 monitors MSMC SRAM Bank 4 MSMC SRAM Bank 5to MSMC SRAM Bank 7 monitors MSMC DDR3A port monitor DSP 0 to 7 SDMA port monitors EDMA 0 and EDMA 4 CFG port monitor EDMA 1, EDMA2 and EDMA3 CFG port monitor INTC port monitor (for INTC 0/1/2 and GIC400) Semaphore CFG port monitors QMSS CFG1 port monitor QMSS CFG2 port monitor QM_M CFG/DMA port monitor SPI ROM EMIF16 CFG port monitor SCR_3P_B and SCR_6P_B CFG peripheral port monitors RAC_FE port monitor RAC A/B CFG port monitor TAC_BE port monitor BCR (RAC Broadcaster) CFG port monitor RAC C/D CFG port monitor DDR 3B port monitor (on SCR 3C)
Table 9-63
Core Name C66x CorePac0 C66x CorePac1 C66x CorePac2 C66x CorePac3 C66x CorePac4 C66x CorePac5 C66x CorePac6 C66x CorePac7 A15 Core0 A15 Core1 A15 Core2
MSTID Mapping for Software Messages (Part 1 of 2)

MSTID [7:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID C66x CorePac MDMA Master ID ARM Master IDs ARM Master ID ARM Master ID
339
PRODUCT PREVIEW

Core Name A15 Core3 QMSS PDSPs End of Table 9-63
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MSTID Mapping for Software Messages (Part 2 of 2)

MSTID [7:0] 0xB 0x46 Description ARM Master ID All QMSS PDSPs share the same master ID. Differentiating between the 8 PDSPs is done through the channel number used
9.36.3 SoC Cross-Triggering Connection The cross-trigger lines are shared by all the subsystems implementing cross-triggering. An MPU subsystem trigger event can therefore be propagated to any application subsystem or system trace component. The remote subsystem or system trace component can be programmed to be sensitive to the global SOC trigger lines to either: Generate a processor debug request Generate an interrupt request Start/Stop processor trace Start/Stop CBA transaction tracing through CPTracers Start external logic analyzer trace Stop external logic analyzer trace
Table 9-64
Name
PRODUCT PREVIEW
Cross-Triggering Connection
Source Triggers Sink Triggers Comments
Inside DEBUGSS Device-to-device trigger via EMU0/1 pins MIPI-STM CT-TBR CS-TPIU YES NO YES NO YES YES YES YES Outside DEBUGSS DSPSS CP_Tracers ARM End of Table 9-64 YES YES YES YES YES YES ARM Cores, ARM CS-STM and ARM CT-TBR This is fixed (not affected by configuration) Trigger input only for MIPI-STM in DebugSS DEBUGSS CT-TBR DEBUGSS CS-TPIU
The following table describes the crosstrigger connection between various cross trigger sources and TI XTRIG module.
Table 9-65
Name C66x CorePac0-7
TI XTRIG Assignment
Assigned XTRIG Channel Number XTRIG 0-7
CPTracer 0..31 (The CPTracer number refers to the SID[4:0] as shown in Table 9-62 XTRIG 8 .. 39
9.36.4 Peripherals-Related Debug Requirement Table 9-66 lists all the peripherals on this device, and the status of whether or not it supports emulation suspend or emulation request events.
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The DEBUGSS supports upto 32 debug suspend sources (processor cores) and 64 debug suspend sinks (peripherals). The assignment of processor cores is shown in and the assignment of peripherals is shown in Table 9-66. By default the logical AND of all the processor cores is routed to the peripherals. It is possible to select an individual core to be routed to the peripheral (For example: used in tightly coupled peripherals like timers), a logical AND of all cores (Global peripherals) or a logical OR of all cores by programming the DEBUGSS.DRM module. The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral function is required or if the peripheral suspend should occur only after a particular completion point is reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the emulation suspend functionality.
Table 9-66 Peripherals Emulation Support (Part 1 of 2)
Emulation Suspend Support Peripheral Stop-Mode Real-Time Mode FREE Bit STOP Bit Emulation Request Support (cemudbg/emudbg) Debug Peripheral Assignment
Infrastructure Peripherals EDMA_x, where X=0/1/2/3/4 QM_SS CP_Tracers_X, where X = 0..32 MPU_X, where X = 0..11 CP_INTC BOOT_CFG SEC_MGR PSC PLL TIMERx, x=0, 1..7, 8..19 Semaphore GPIO N Y (CPDMA only) N N N N N N N Y N N N Y (CPDMA only) N N N N N N N N N N N N Y Y N Y Y Y Y N N N Y N NA 20 NA NA NA NA NA NA NA 0, 1..7, 8..19 NA NA
Y (CPDMA only) Y (CPDMA only) N N N N N N N Y N N N N N N N N N Y N N
Memory Controller Peripherals DDR3A/B MSMC EMIF16

2
N N N
N N N Serial Interfaces
N N N
N N N
Y Y Y
NA NA NA
I C_X, where X = 0/1/2 SPI_X, where X = 0/1/2 UART_X, where X = 0/1 USIM
Y N Y Y
N N N N
Y N Y Y
Y N Y N
Y Y Y N
21/22/23 NA 24/25 28
High Speed Serial Interfaces Hyperlink_0/1 PCIeSS 0 SRIO / NetCP_1 NetCP (ethernet switch) USBSS N N Y Y N N N Y Y N Accelarators RAC_0 RAC_1 TAC_2 Y Y N N N N N N N N N N Y Y N 30 31 NA N N Y Y N N N Y (Soft Only) Y N Y N Y N N 26 27 NA
341
PRODUCT PREVIEW

SPRS835DAugust 2013 Table 9-66 Peripherals Emulation Support (Part 2 of 2)
Emulation Suspend Support Peripheral VCP_0/1/2/3 TCP3d_0/1 BCP FFTC_0/1/2/3 AIF End of Table 9-66 Stop-Mode Y Y Y Y Y Real-Time Mode N Y Y Y Y FREE Bit Y Y N Y Y STOP Bit N Y N Y N Emulation Request Support (cemudbg/emudbg) N N N N N Debug Peripheral Assignment
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34/35/36/37 42/43 46 47/48/49/50 53
Based on the above table the number of suspend interfaces in Keystone II devices is listed below.
Table 9-67
Interfaces EMUSUSP Interfaces EMUSUSP Realtime Interfaces
PRODUCT PREVIEW
EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS)

NUM_SUSPEND_PERIPHERALS 54 15
Table 9-68 summarizes the DEBUG core assignment. Emulation suspend output of all the cores are synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.
Table 9-68
Core # 0..7 8..11 12..29 30 31 End of Table 9-68
EMUSUSP Core Summary (for EMUSUSP handshake to DEBUGSS)

Assignment C66x CorePac0..7 ARM CorePac 8..11 Reserved Logical OR of Core# 0..11 Logical AND of Core #0..11
9.36.5 Advance Event Triggering (AET) The device supports advanced event triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities: Hardware program breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture. Data watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture. Counters: count the occurrence of an event or cycles for performance monitoring. State sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences. For more information on the AET, see the following documents in 1.10 Related Documentation from Texas Instruments on page 21. Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems application report
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9.36.6 Trace The device supports trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system. For more information on board design guidelines for trace advanced emulation, see the Emulation and Trace Headers Technical Reference in 1.10 Related Documentation from Texas Instruments on page 21.
9.36.6.1 Trace Electrical Data/Timing
Table 9-69
(see Figure 9-60) No. 1 1 2 2 3 tw(DPnH) tw(DPnL) tw(DPnL)10% tsko(DPn) tskp(DPn) tsldp_o(DPn) End of Table 9-69 Pulse duration, DPn/EMUn high Parameter Min 2.4 1.5 2.4 1.5 -1 1 600 3.3 Max Unit ns ns ns ns ns ps V/ns
Trace Switching Characteristics
tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh Pulse duration, DPn/EMUn low Pulse duration, DPn/EMUn low detected at 10% Voh Output skew time, time delay difference between DPn/EMUn pins configured as trace Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays. Output slew rate DPn/EMUn
Figure 9-60
Trace Timing
A TPLH Buffer Inputs Buffers DP[n] / EMU[n] Pins B 1 B 3 C C TPHL 2
9.36.7 IEEE 1149.1 JTAG The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous test reset (TRST) and only the five baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6). It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
9.36.7.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the TCI6636K2H device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the devices internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high, but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.
Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback TCI6636K2H Peripheral Information and Electrical Specifications 343
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SPRS835DAugust 2013
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9.36.7.2 JTAG Electrical Data/Timing

Table 9-70
(see Figure 9-61) No. 1 1a 1b 3 3 4 4 tc(TCK) tw(TCKH) tw(TCKL) tsu(TDI-TCK) tsu(TMS-TCK) th(TCK-TDI) th(TCK-TMS) Cycle time, TCK Pulse duration, TCK high (40% of tc) Pulse duration, TCK low(40% of tc) Input setup time, TDI valid to TCK high Input setup time, TMS valid to TCK high Input hold time, TDI valid from TCK high Input hold time, TMS valid from TCK high Min 34 13.6 13.6 3.4 3.4 17 17 Max Unit ns ns ns ns ns ns ns
JTAG Test Port Timing Requirements
End of Table 9-70
PRODUCT PREVIEW
Table 9-71
(see Figure 9-61) No. 2
JTAG Test Port Switching Characteristics

Parameter Min Max 13.6 Unit ns
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
End of Table 9-71
Figure 9-61
JTAG Test-Port Timing

1 1a TCK 2 TDO 3 TDI / TMS 4 1b
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A Revision History
Revision D Added SRIOSGMIICLK clocking info to the table. (Page 305) Corrected USBVBUS terminal designation. It is not reserved. (Page 58) Added the bridge numbers to the Interconnect tables in the System Interconnect chapter (Page 194) Added the TeraNet drawings to the System Interconnect chapter (Page 190) Updated the Power-Up Sequence information in the Peripheral Information and Electrical Specifications chapter (Page 271) Corrected Event (48-80) Names (Page 116) Changed SerDes field to Reserved as it is not implemented (Page 224) Corrected Buffer Type (Page 268) Added DEVSPEED address (Page 241) Removed PLLLOCK LOCK, STAT and EVAL registers (Page 241)
PRODUCT PREVIEW
Removed PLLLOCK STAT and EVAL registers (Page 241) Changed the power up order of power rails (Page 271) Changed CPTS_RFTCLK_SEL from three bits to four bits (Page 326) Updated L3 memory data (Page 28) Updated L2 memory (Page 27) Updated memory data for L2 and MSM (Page 25) Updated MSM SRAM data (Page 28) Updated the C66x CorePac Block Diagram (Page 24) Revision C Added a footnote to the System Event Mapping table (Page 113) Added CHIP_MISC_CTL1 register (Page 231) Added Initial Voltage for SR core supply (Page 258) Added the Boot Parameter Table section (Page 217) Updated the PWRSTATECTL register (Page 239) Updated the register bit fields (Page 239) Updated the L1 and L2 specs. Changed 4-way to 2-way, and changed 8-way to 16-way. (Page 32) Added ARM PLL Configuration info for 1400 MHz device (Page 226) Added bit 13 as PAPLL in the PASSPLLCTL1 register (Page 301) Added Note "Each supply must ramp monotonically and must reach a stable valid level in 20ms or less" (Page 267) Added Note "Each supply must ramp monotonically and must reach a stable valid level in 20ms or less" (Page 265) Changed PLLD at 156.25 from 24 to 2 for 1200 MHz device (Page 225) Updated PLLD at 156.25 from 0 to 3 for 800 MHz devices (Page 225) Updated the CVDD and its associated peripheral (Page 259) Added tying CVDD and CVDDT together (Page 60) Updated with CVDDS (Page 267) Updated with CVDDS (Page 265) Corrected rise and fall time of all differential clock pairs (Page 296) Corrected rise and fall time of differential clock pairs (Page 297) Added additional information to Emulation Features and Capability section (Page 329) Changed 5000 to 6000 (Page 88) Corrected the ARM_LENDIAN configuration pin description (Page 227) Added ARMCLK specification (Page 296) Added ARMCLK specification (Page 296) Changed EMIF16 CS(x) to EMIF16 CE(x-2) (Page 84) Changed 1200.80 to 1228.80 (Page 225) Updated with miscellaneous information (Page 272)
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Revision History

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SPRS835DAugust 2013
Updated with miscellaneous information (Page 271) Updated the ALNCTL Register in the Peripheral Information and Electrical Specifications chapter. (Page 289) Updated the DCHANGE Register in the Peripheral Information and Electrical Specifications chapter. (Page 289) Changed to not support external charge pump for 5V (Page 325) Changed bit to pin (Page 227) Updated BOOTMODE pins and MIN information (Page 202) Updated the Clocking info. (Page 35) Revision B Added Terminal functions and pin list tables. (Page 42) Reorganized memory content. (Page 85) Added device pin map. (Page 37) Revision A Added Device Boot and Configuration chapter. (Page 195) Added Device Operating Conditions chapter. (Page 239) Added Peripheral Information and Electrical Specifications chapter. (Page 243) Added System Interconnect chapter. (Page 182) In the SPI Switching Characteristics table: Changed the incorrect SPIx_Clk signal name to SPICLK. (Page 288) In the SPI Switching Characteristics table: Changed the incorrect SPIx_SCS signal name to SPISCSx. (Page 289) In the SPI Switching Characteristics table: Corrected signal name from SPIx_SIMO to SPIDOUT. (Page 288) In the SPI Timing Requirements table: Changed the incorrect SPIx_Clk signal name to SPICLK. (Page 288) In the SPI Timing Requirements table: Corrected signal name SPIx_SOMI to SPIDIN. (Page 288) Added Security section (Page 208) Added thermal values into the Thermal Resistance Characteristics table. (Page 312)
Revision History
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SPRS835DAugust 2013
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B Mechanical Data
B.1 Thermal Data
Table B-1 shows the thermal resistance characteristics for the PBGA - AAW mechanical package.
Table B-1
No. 1 2 RJC RJB Junction-to-case Junction-to-board
Thermal Resistance Characteristics (PBGA Package) AAW

C/W 0.11 1.65
End of Table B-1
B.2 Packaging Information

The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document.
PRODUCT PREVIEW
346
Mechanical Data
IMPORTANT NOTICE
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TCI6636K2H

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Literature Number: SPRS835D August 2013

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

ARM CorePac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Memory, Interrupts, and EDMA for TCI6636K2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Device Boot and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

TCI6636K2H Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

1 TCI6636K2H Features and Description

Copyright 2013 Texas Instruments Incorporated

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

1.2 KeyStone Architecture

1.3 Device Description

TCI6636K2H Features and Description

Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

1.4 Enhancements in KeyStone II

Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback

TCI6636K2H Features and Description

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

1.5 Functional Block Diagram

6MB MSM SRAM

Boot ROM Semaphore Power Management

ARM A15 ARM A15

ARM A15 ARM A15

32KB L1 32KB L1 32KB L1 32KB L1 P-Cache D-Cache P-Cache D-Cache

8 C66x DSP Cores @ up to 1.2 GHz 4 ARM Cores @ up to 1.4 GHz

TCI6636K2H Features and Description

Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

1.6 Device Characteristics

Copyright 2013 Texas Instruments Incorporated Submit Documentation Feedback

TCI6636K2H Features and Description

TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Voltage BGA Package Process Technology Product Status

End of Table 1-1