Rabbit® 5000 Microprocessor: User's Manual

Rabbit 5000 Microprocessor
Users Manual
019-0168_C
Rabbit 5000 Microprocessor Users Manual

Part Number 019-0168 Printed in the U.S.A. Digi International Inc. 20082010 All rights reserved.
Digi International Inc. reserves the right to make changes and improvements to its products without providing notice.
Trademarks
Rabbit and Dynamic C are registered trademarks of Digi International Inc. Windows is a registered trademark of Microsoft Corporation.
The latest revision of this manual is available at www.rabbit.com.
TABLE OF CONTENTS
Chapter 1. The Rabbit 5000 Processor

1.1 1.2 1.3 1.4 1.5
13
Introduction.........................................................................................................................................13 Features ...............................................................................................................................................14 Block Diagram ....................................................................................................................................16 Basic Specifications ............................................................................................................................17 Comparing Rabbit Microprocessors ...................................................................................................18
Chapter 2. Clocks
21
2.1 Overview.............................................................................................................................................21 2.1.1 Block Diagram ...........................................................................................................................22 2.1.2 Registers .....................................................................................................................................22 2.2 Dependencies ......................................................................................................................................23 2.2.1 I/O Pins ......................................................................................................................................23 2.2.2 Other Registers ...........................................................................................................................23 2.3 Operation ............................................................................................................................................24 2.3.1 Main Clock .................................................................................................................................24 2.3.2 Spectrum Spreader .....................................................................................................................25 2.3.3 Clock Doubler ............................................................................................................................27 2.3.4 32 kHz Clock .............................................................................................................................30 2.4 Register Descriptions ..........................................................................................................................32
Chapter 3. Reset and Bootstrap
37
3.1 Overview.............................................................................................................................................37 3.1.1 Block Diagram ...........................................................................................................................38 3.1.2 Registers .....................................................................................................................................38 3.2 Dependencies ......................................................................................................................................39 3.2.1 I/O Pins ......................................................................................................................................39 3.2.2 Clocks .........................................................................................................................................39 3.2.3 Other Registers ...........................................................................................................................39 3.2.4 Interrupts ....................................................................................................................................39 3.3 Operation ............................................................................................................................................40 3.3.1 Asynchronous Serial Bootstrap ..................................................................................................42 3.3.2 Serial Flash Bootstrap ................................................................................................................42 3.3.3 Parallel Bootstrap .......................................................................................................................43 3.4 Register Descriptions ..........................................................................................................................44
Chapter 4. System Management
45
4.1 Overview.............................................................................................................................................45 4.1.1 Block Diagram ...........................................................................................................................46 4.1.2 Registers .....................................................................................................................................47 4.2 Dependencies ......................................................................................................................................48 4.2.1 I/O Pins ......................................................................................................................................48 4.2.2 Clocks .........................................................................................................................................48 4.2.3 Interrupts ....................................................................................................................................48
Table of Contents
4.3 Operation ............................................................................................................................................ 49 4.3.1 Periodic Interrupt ....................................................................................................................... 49 4.3.2 Real-Time Clock ....................................................................................................................... 49 4.3.3 Watchdog Timer ........................................................................................................................ 50 4.3.4 Secondary Watchdog Timer ...................................................................................................... 50 4.4 Register Descriptions ......................................................................................................................... 51
Chapter 5. Memory Management
57
5.1 Overview ............................................................................................................................................ 57 5.1.1 Block Diagram ........................................................................................................................... 60 5.1.2 Registers .................................................................................................................................... 61 5.2 Dependencies ..................................................................................................................................... 62 5.2.1 I/O Pins ...................................................................................................................................... 62 5.2.2 Clocks ........................................................................................................................................ 62 5.2.3 Other Registers .......................................................................................................................... 62 5.2.4 Interrupts .................................................................................................................................... 62 5.3 Operation ............................................................................................................................................ 63 5.3.1 Memory Management Unit (MMU) .......................................................................................... 63 5.3.2 Memory Bank Operation ........................................................................................................... 64 5.3.3 Memory Modes ......................................................................................................................... 66 5.3.4 Separate Instruction and Data Space ......................................................................................... 68 5.3.5 Memory Protection .................................................................................................................... 68 5.3.6 Stack Protection ......................................................................................................................... 69 5.4 Register Descriptions ......................................................................................................................... 70
Chapter 6. Interrupts
81
6.1 Overview ............................................................................................................................................ 81 6.2 Operation ............................................................................................................................................ 82 6.3 Interrupt Tables .................................................................................................................................. 82
Chapter 7. External Interrupts
85
7.1 Overview ............................................................................................................................................ 85 7.2 Block Diagram ................................................................................................................................... 85 7.2.1 Registers .................................................................................................................................... 86 7.3 Dependencies ..................................................................................................................................... 86 7.3.1 I/O Pins ...................................................................................................................................... 86 7.3.2 Clocks ........................................................................................................................................ 86 7.3.3 Interrupts .................................................................................................................................... 86 7.4 Operation ............................................................................................................................................ 86 7.4.1 Example ISR .............................................................................................................................. 87 7.5 Register Descriptions ......................................................................................................................... 88
Chapter 8. Parallel Port A
89
8.1 Overview ............................................................................................................................................ 89 8.1.1 Block Diagram ........................................................................................................................... 89 8.1.2 Registers .................................................................................................................................... 89 8.2 Dependencies ..................................................................................................................................... 90 8.2.1 I/O Pins ...................................................................................................................................... 90 8.2.2 Clocks ........................................................................................................................................ 90 8.2.3 Other Registers .......................................................................................................................... 90 8.2.4 Interrupts .................................................................................................................................... 90 8.3 Operation ............................................................................................................................................ 90 8.4 Register Descriptions ......................................................................................................................... 91
Chapter 9. Parallel Port B
93
9.1 Overview.............................................................................................................................................93 9.1.1 Block Diagram ...........................................................................................................................94 9.1.2 Registers .....................................................................................................................................94 9.2 Dependencies ......................................................................................................................................94 9.2.1 I/O Pins ......................................................................................................................................94 9.2.2 Clocks .........................................................................................................................................94 9.2.3 Other Registers ...........................................................................................................................94 9.2.4 Interrupts ....................................................................................................................................95 9.3 Operation ............................................................................................................................................95 9.4 Register Descriptions ..........................................................................................................................95
Chapter 10. Parallel Port C
97
10.1 Overview...........................................................................................................................................97 10.1.1 Block Diagram .........................................................................................................................98 10.1.2 Registers ...................................................................................................................................98 10.2 Dependencies ....................................................................................................................................99 10.2.1 I/O Pins ....................................................................................................................................99 10.2.2 Clocks .......................................................................................................................................99 10.2.3 Other Registers .........................................................................................................................99 10.2.4 Interrupts ..................................................................................................................................99 10.3 Operation ..........................................................................................................................................99 10.4 Register Descriptions ......................................................................................................................100
Chapter 11. Parallel Port D
105
11.1 Overview.........................................................................................................................................105 11.1.1 Block Diagram .......................................................................................................................107 11.1.2 Registers .................................................................................................................................108 11.2 Dependencies ..................................................................................................................................109 11.2.1 I/O Pins ..................................................................................................................................109 11.2.2 Clocks .....................................................................................................................................109 11.2.3 Other Registers .......................................................................................................................109 11.2.4 Interrupts ................................................................................................................................109 11.3 Operation ........................................................................................................................................110 11.4 Register Descriptions ......................................................................................................................111
Chapter 12. Parallel Port E
123
12.1 Overview.........................................................................................................................................123 12.1.1 Block Diagram .......................................................................................................................125 12.1.2 Registers .................................................................................................................................126 12.2 Dependencies ..................................................................................................................................126 12.2.1 I/O Pins ..................................................................................................................................126 12.2.2 Clocks .....................................................................................................................................126 12.2.3 Other Registers .......................................................................................................................127 12.2.4 Interrupts ................................................................................................................................127 12.3 Operation ........................................................................................................................................127 12.4 Register Descriptions ......................................................................................................................128
Chapter 13. Parallel Port H
143
13.1 Overview.........................................................................................................................................143 13.1.1 Block Diagram .......................................................................................................................144 13.1.2 Registers .................................................................................................................................144 13.2 Dependencies ..................................................................................................................................145 13.2.1 I/O Pins ..................................................................................................................................145 13.2.2 Clocks .....................................................................................................................................145 13.2.3 Other Registers .......................................................................................................................145 13.2.4 Interrupts ................................................................................................................................145 13.3 Operation ........................................................................................................................................145
Table of Contents
13.4 Register Descriptions ..................................................................................................................... 146
Chapter 14. Timer A
149
14.1 Overview ........................................................................................................................................ 149 14.1.1 Block Diagram ....................................................................................................................... 151 14.1.2 Registers ................................................................................................................................ 152 14.2 Dependencies ................................................................................................................................. 152 14.2.1 I/O Pins .................................................................................................................................. 152 14.2.2 Clocks .................................................................................................................................... 152 14.2.3 Other Registers ...................................................................................................................... 152 14.2.4 Interrupts ................................................................................................................................ 153 14.3 Operation ........................................................................................................................................ 153 14.3.1 Handling Interrupts ................................................................................................................ 153 14.3.2 Example ISR .......................................................................................................................... 153 14.4 Register Descriptions ..................................................................................................................... 154
Chapter 15. Timer B
157
Chapter 16. Timer C
163
Chapter 17. Serial Ports A D
171
17.1 Overview ........................................................................................................................................ 171 17.1.1 Block Diagram ....................................................................................................................... 173 17.1.2 Registers ................................................................................................................................ 174 17.2 Dependencies ................................................................................................................................. 175 17.2.1 I/O Pins .................................................................................................................................. 175 17.2.2 Clocks .................................................................................................................................... 175 17.2.3 Other Registers ...................................................................................................................... 176 17.2.4 Interrupts ................................................................................................................................ 176 17.3 Operation ........................................................................................................................................ 177 17.3.1 Asynchronous Mode .............................................................................................................. 177 17.3.2 Clocked Serial Mode ............................................................................................................. 178
17.4 Register Descriptions ......................................................................................................................180
Chapter 18. Serial Ports E F
187
18.1 Overview.........................................................................................................................................187 18.1.1 Block Diagram .......................................................................................................................188 18.1.2 Registers .................................................................................................................................189 18.2 Dependencies ..................................................................................................................................190 18.2.1 I/O Pins ..................................................................................................................................190 18.2.2 Clocks .....................................................................................................................................190 18.2.3 Other Registers .......................................................................................................................190 18.2.4 Interrupts ................................................................................................................................191 18.3 Operation ........................................................................................................................................192 18.3.1 Asynchronous Mode ..............................................................................................................192 18.3.2 HDLC Mode ..........................................................................................................................192 18.3.3 More on Clock Synchronization and Data Encoding .............................................................193 18.4 Register Descriptions ......................................................................................................................197
Chapter 19. Slave Port
203
19.1 Overview.........................................................................................................................................203 19.1.1 Block Diagram .......................................................................................................................204 19.1.2 Registers .................................................................................................................................204 19.2 Dependencies ..................................................................................................................................205 19.2.1 I/O Pins ..................................................................................................................................205 19.2.2 Clocks .....................................................................................................................................205 19.2.3 Interrupts ................................................................................................................................205 19.3 Operation ........................................................................................................................................206 19.3.1 Master Setup ..........................................................................................................................207 19.3.2 Slave Setup .............................................................................................................................207 19.3.3 Master/Slave Communication ................................................................................................208 19.3.4 Slave/Master Communication ................................................................................................208 19.3.5 Handling Interrupts ................................................................................................................208 19.3.6 Example ISR ..........................................................................................................................208 19.3.7 Other Configurations ..............................................................................................................209 19.3.8 Timing Diagrams ...................................................................................................................210 19.4 Register Descriptions ......................................................................................................................212
Chapter 20. Analog Components
215
20.1 Overview.........................................................................................................................................215 20.2 Block Diagram ................................................................................................................................218 20.2.1 Registers .................................................................................................................................219 20.3 Dependencies ..................................................................................................................................219 20.3.1 I/O Pins ..................................................................................................................................219 20.3.2 Clocks .....................................................................................................................................219 20.4 Operation ........................................................................................................................................220 20.4.1 Fast A/D Converter ................................................................................................................220 20.4.2 Fast D/A Converter ................................................................................................................220 20.4.3 Slow A/D Converter ...............................................................................................................220 20.5 Sample Circuits...............................................................................................................................221 20.6 Register Descriptions ......................................................................................................................223
Chapter 21. DMA Channels
229
21.1 Overview.........................................................................................................................................229 21.1.1 Block Diagram .......................................................................................................................232 21.1.2 Registers .................................................................................................................................233 21.2 Dependencies ..................................................................................................................................234 21.2.1 I/O Pins ..................................................................................................................................234 21.2.2 Clocks .....................................................................................................................................234 21.2.3 Interrupts ................................................................................................................................234 21.3 Operation ........................................................................................................................................235
Table of Contents
21.3.1 Handling Interrupts ................................................................................................................ 236 21.3.2 Example ISR .......................................................................................................................... 236 21.3.3 DMA Priority with the Processor .......................................................................................... 236 21.3.4 DMA Channel Priority .......................................................................................................... 238 21.3.5 Buffer Descriptor Modes ....................................................................................................... 238 21.3.5.1 Single Buffer .................................................................................................................. 239 21.3.5.2 Buffer Array ................................................................................................................... 239 21.3.5.3 Linked List ..................................................................................................................... 240 21.3.5.4 Circular Queue ............................................................................................................... 241 21.3.5.5 Linked Array .................................................................................................................. 241 21.3.6 DMA with Peripherals ........................................................................................................... 242 21.3.6.1 DMA with HDLC Serial Ports ...................................................................................... 242 21.3.6.2 DMA with Ethernet ....................................................................................................... 242 21.3.6.3 DMA with Wi-Fi ........................................................................................................... 242 21.3.6.4 DMA with PWM and Timer C ...................................................................................... 242 21.4 Register Descriptions ..................................................................................................................... 243
Chapter 22. 10/100Base-T Ethernet
257
22.1 Overview ........................................................................................................................................ 257 22.1.1 Block Diagram ....................................................................................................................... 259 22.1.2 Registers ................................................................................................................................ 260 22.2 Dependencies ................................................................................................................................. 262 22.2.1 I/O Pins .................................................................................................................................. 262 22.2.2 Clocks .................................................................................................................................... 262 22.2.3 Other Registers ...................................................................................................................... 262 22.2.4 Interrupts ................................................................................................................................ 263 22.3 Operation ........................................................................................................................................ 263 22.3.1 Setup ...................................................................................................................................... 264 22.3.2 Transmit ................................................................................................................................. 264 22.3.3 Receive .................................................................................................................................. 264 22.3.4 Handling Interrupts ................................................................................................................ 265 22.3.5 Multicast Addressing ............................................................................................................. 266 22.4 Register Descriptions ..................................................................................................................... 267
Chapter 23. 802.11b/g Wireless
281
23.1 Overview ........................................................................................................................................ 281 23.1.1 Block Diagram ....................................................................................................................... 282 23.1.2 Registers ................................................................................................................................ 283 23.2 Dependencies ................................................................................................................................. 285 23.2.1 I/O Pins .................................................................................................................................. 285 23.3 Clocks............................................................................................................................................. 286 23.3.1 Other Registers ...................................................................................................................... 286 23.3.2 Interrupts ................................................................................................................................ 286 23.4 Operation ........................................................................................................................................ 286
Chapter 24. Input Capture
287
24.1 Overview ........................................................................................................................................ 287 24.1.1 Block Diagram ....................................................................................................................... 288 24.1.2 Registers ................................................................................................................................ 289 24.2 Dependencies ................................................................................................................................. 290 24.2.1 I/O Pins .................................................................................................................................. 290 24.2.2 Clocks .................................................................................................................................... 290 24.2.3 Other Registers ...................................................................................................................... 290 24.2.4 Interrupts ................................................................................................................................ 290 24.3 Operation ........................................................................................................................................ 291 24.3.1 Input-Capture Channel .......................................................................................................... 291 24.3.2 Handling Interrupts ................................................................................................................ 291 24.3.3 Example ISR .......................................................................................................................... 291 24.3.4 Capture Mode ........................................................................................................................ 292
24.3.5 Count Mode ............................................................................................................................292 24.4 Register Descriptions ......................................................................................................................293
Chapter 25. Quadrature Decoder
299
25.1 Overview.........................................................................................................................................299 25.1.1 Block Diagram .......................................................................................................................301 25.1.2 Registers .................................................................................................................................301 25.2 Dependencies ..................................................................................................................................302 25.2.1 I/O Pins ..................................................................................................................................302 25.2.2 Clocks .....................................................................................................................................302 25.2.3 Other Registers .......................................................................................................................302 25.2.4 Interrupts ................................................................................................................................302 25.3 Operation ........................................................................................................................................303 25.3.1 Handling Interrupts ................................................................................................................303 25.3.2 Example ISR ..........................................................................................................................303 25.4 Register Descriptions ......................................................................................................................304
Chapter 26. Pulse Width Modulator
307
26.1 Overview.........................................................................................................................................307 26.1.1 Block Diagram .......................................................................................................................309 26.1.2 Registers .................................................................................................................................309 26.2 Dependencies ..................................................................................................................................310 26.2.1 I/O Pins ..................................................................................................................................310 26.2.2 Clocks .....................................................................................................................................310 26.2.3 Other Registers .......................................................................................................................310 26.2.4 Interrupts ................................................................................................................................310 26.3 Operation ........................................................................................................................................311 26.3.1 Handling Interrupts ................................................................................................................311 26.3.2 Example ISR ..........................................................................................................................311 26.4 Register Descriptions ......................................................................................................................312
Chapter 27. External I/O Control
315
27.1 Overview.........................................................................................................................................315 27.1.1 External I/O Bus .....................................................................................................................315 27.1.2 I/O Strobes .............................................................................................................................316 27.1.3 I/O Handshake ........................................................................................................................317 27.1.4 Block Diagram .......................................................................................................................318 27.1.5 Registers .................................................................................................................................318 27.2 Dependencies ..................................................................................................................................319 27.2.1 I/O Pins ..................................................................................................................................319 27.2.2 Clocks .....................................................................................................................................319 27.2.3 Other Registers .......................................................................................................................319 27.2.4 Interrupts ................................................................................................................................319 27.3 Operation ........................................................................................................................................320 27.3.1 External I/O Bus .....................................................................................................................320 27.3.2 I/O Strobes .............................................................................................................................320 27.3.3 I/O Handshake ........................................................................................................................320 27.4 Register Descriptions ......................................................................................................................321
Chapter 28. Breakpoints
331
28.1 Overview.........................................................................................................................................331 28.1.1 Block Diagram .......................................................................................................................332 28.1.2 Registers .................................................................................................................................333 28.2 Dependencies ..................................................................................................................................334 28.2.1 I/O Pins ..................................................................................................................................334 28.2.2 Clocks .....................................................................................................................................334 28.2.3 Other Registers .......................................................................................................................334 28.2.4 Interrupts ................................................................................................................................334 28.3 Operation ........................................................................................................................................334
Table of Contents
28.3.1 Handling Interrupts ................................................................................................................ 334 28.3.2 Example ISR .......................................................................................................................... 335 28.4 Register Descriptions ..................................................................................................................... 336
Chapter 29. Low-Power Operation
339
29.1 Overview ........................................................................................................................................ 339 29.1.1 Registers ................................................................................................................................ 340 29.2 Operation ........................................................................................................................................ 341 29.2.1 Unused Pins ........................................................................................................................... 341 29.2.2 Clock Rates ............................................................................................................................ 341 29.2.3 Short Chip Selects ................................................................................................................. 342 29.2.4 Self-Timed Chip Selects ........................................................................................................ 347 29.3 Register Descriptions ..................................................................................................................... 348
Chapter 30. System/User Mode
351
30.1 Overview ........................................................................................................................................ 351 30.1.1 Registers ................................................................................................................................ 352 30.2 Dependencies ................................................................................................................................. 353 30.2.1 I/O Pins .................................................................................................................................. 353 30.2.2 Clocks .................................................................................................................................... 353 30.2.3 Other Registers ...................................................................................................................... 353 30.2.4 Interrupts ................................................................................................................................ 354 30.3 Operation ........................................................................................................................................ 355 30.3.1 Memory Protection Only ....................................................................................................... 355 30.3.2 Mixed System/User Mode Operation .................................................................................... 356 30.3.3 Complete Operating System .................................................................................................. 356 30.3.4 Enabling the System/User Mode ........................................................................................... 357 30.3.5 System/User Mode Instructions ............................................................................................ 358 30.3.6 System Mode Violation Interrupt .......................................................................................... 359 30.3.7 Handling Interrupts in the System/User Mode ...................................................................... 360 30.4 Register Descriptions ..................................................................................................................... 362
Chapter 31. Specifications
369
31.1 DC Characteristics.......................................................................................................................... 369 31.2 AC Characteristics.......................................................................................................................... 371 31.3 Memory Access Times................................................................................................................... 372 31.3.1 Memory Reads ....................................................................................................................... 372 31.3.2 Memory Writes ...................................................................................................................... 372 31.3.3 External I/O Reads ................................................................................................................ 375 31.3.4 External I/O Writes ................................................................................................................ 375 31.3.5 Memory Access Times .......................................................................................................... 378 31.4 Clock Speeds .................................................................................................................................. 381 31.4.1 Recommended Clock/Memory Configurations ..................................................................... 381 31.5 Power and Current Consumption ................................................................................................... 385 31.5.1 Sleepy Mode Current Consumption ...................................................................................... 386 31.5.2 Battery-Backed Clock Current Consumption ........................................................................ 387
Chapter 32. Package Specifications and Pinout
389
32.1 Ball Grid Array Packages............................................................................................................... 389 32.1.1 Pinout 17 17 Ethernet Option ............................................................................................. 389 32.1.2 Pinout 17 17 Wi-Fi Option ................................................................................................. 390 32.1.3 Mechanical Dimensions and Land Pattern ............................................................................ 391 32.2 Rabbit Pin Descriptions.................................................................................................................. 393
Appendix A. Parallel Port Pins with Alternate Functions
397
A.1 Alternate Parallel Port Pin Outputs ................................................................................................. 397 A.2 Alternate Parallel Port Pin Inputs.................................................................................................... 399
Appendix B. Rabbit 5000 Errata
401
B.1 Errata ................................................................................................................................................401
Index
405
Table of Contents
1. THE RABBIT 5000 PROCESSOR

1.1 Introduction
Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small- and medium-scale single-board computers. The first microprocessors were the Rabbit 2000, Rabbit 3000, and the Rabbit 4000. The latest microprocessor is the Rabbit 5000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small single-board computers. The Rabbit microprocessors share a similar architecture and a high degree of compatibility with these microprocessors, but represent a vast improvement. The Rabbit 5000 is a high-performance microprocessor with low electromagnetic interference (EMI), and is designed specifically for embedded control, communications, and network connectivity. Extensive integrated features and glueless architecture facilitate rapid hardware design, while a C-friendly instruction set promotes efficient development of even the most complex applications. The Rabbit 5000 is the first Rabbit microprocessor to have a full 16-bit internal bus architecture, providing significant performance improvements when used with external 16-bit memory devices. It also has the ability to support both 8-bit and 16-bit external memory devices. The Rabbit 5000 is also the fastest microprocessor from Rabbit, now a Digi International brand, running at up to 100 MHz, with compact code and support for up to 16 MB of memory. Operating with a 1.8 V core and 3.3 V I/O, the Rabbit 5000 boasts eight channels of DMA, six serial ports with IrDA, 48+ digital I/O, quadrature decoder, PWM outputs, and pulse capture and measurement capabilities. It also features a battery-backable realtime clock, glueless memory and I/O interfacing, and ultra-low power modes. Four levels of interrupt priority allow fast response to real-time events. Its compact instruction set and high clock speeds give the Rabbit 5000 exceptionally fast math, logic, and I/O performance. The Rabbit 5000 contains 128 KB of internal high-speed 16-bit SRAM, which can be used for code and/or data. It is capable of booting off of a standard serial flash, so a microcontroller application with no external parallel memory is possible. The Rabbit 5000 provides two options for network connectivity a full 10/100Base-T Ethernet MAC with a standard MII PHY interface, and a wireless 802.11b/g MAC compatible with several standard Wi-Fi transceivers. The two network interfaces share both internal resources and I/O pins, and so only one can be enabled at a time.
Chapter 1 The Rabbit 5000 Processor 13
1.2 Features
The Rabbit 5000 has several powerful design features that practically eliminate EMI problems, which is essential for OEMs who need to pass CE and regulatory radio-frequency emissions tests. The amplitude of any electromagnetic radiation is reduced by the internal spectrum spreader, by gated clocks (which prevent unnecessary clocking of unused registers), and by separate power planes for the processor core and I/O pins (which reduce noise crosstalk). An external I/O bus can be used by designers to enable separate buses for I/O and memory, or to limit loading the memory bus to reduce EMI and ground bounce problems when interfacing external peripherals to the processor. The external I/O bus accomplishes this by duplicating the Rabbit's data bus on Parallel Port A, and uses Parallel Port B to provide the processor's six or eight least significant address lines for interfacing with external peripherals. The high-performance instruction set offers both greater efficiency and execution speed of compiler-generated C code. Instructions include numerous single-byte opcodes that execute in two clock cycles, 16-bit and 32-bit loads and stores, 16-bit and 32-bit logical and arithmetic operations, 16 16 multiply (executes in 12 clocks), long jumps and returns for accessing a full 16 MB of memory, and one-byte prefixes to turn memory-access instructions into internal and external I/O instructions. Hardware-supported breakpoints ease debugging by trapping on code execution or data reads and writes. The Rabbit 5000 requires no external memory driver or interface-logic. Its 24-bit address bus, 8-bit or 16-bit data bus, three chip-select lines, two output-enable lines, and two write-enable lines can be interfaced directly with up to six memory devices. Up to 1 MB of memory can be accessed directly via the Dynamic C development software, and up to 16 MB can be interfaced with additional software development. The Rabbit 5000 also contains 128 KB of internal high-speed 16-bit SRAM, which can be used in addition to any external memory devices. A built-in slave port allows the Rabbit 5000 to be used as master or slave in multi-processor systems, permitting separate tasks to be assigned to dedicated processors. An 8-line data port and five control signals simplify the exchange of data between devices. A remote cold boot enables startup and programming via a serial port, a slave port, or from a standard external serial flash device. The Rabbit 5000 features six 8-bit parallel ports, yielding a total of 48 digital I/O. Six CMOS-compatible serial ports are available. All six are configurable as asynchronous (including output pulses in IrDA format), while four are configurable as clocked serial (SPI) and two are configurable as SDLC/HDLC. The various internal peripherals share the parallel ports I/O pins. The Rabbit 5000 also offers many specialized peripherals. Two input-capture channels each have a 16-bit counter, clocked by the output of an internal timer, that can be used to capture and measure pulses. These measurements can be extended to a variety of functions such as measuring pulse widths or for baud-rate autodetection. Two Quadrature Decoder channels each have two inputs, as well as an 8- or 10-bit up/down counter. Each quadrature
14 Rabbit 5000 Microprocessor Users Manual
decoder channel provides a direct interface to optical encoder units. Four independent pulsewidth modulator (PWM) outputs, each based on a 1024-pulse frame, are driven by the output of a programmable internal timer. The PWM outputs can be filtered to create a 10-bit D/A converter or they can be used directly to drive devices such as motors or solenoids. Two external interrupt vectors can multiplex inputs from up to six external pins. The Rabbit 5000 has three timer systems. Timer A consists of ten 8-bit counters, each of which has a programmed time constant. Six of them can be cascaded from the primary Timer A counter. Timer B contains a 10-bit counter, two match registers, and two step registers. An interrupt can be generated or the output pin can be updated when the counter reaches a match value, and the match value can then be incremented automatically by the step value. Timer C is a 16-bit counter that counts up to a programmable limit. It contains eight match registers so that up to four PWM (both synchronous and variable-phase) or quadrature decoder signals can be created. The Rabbit 5000 also provides support for protected operating systems. Support for two levels of operation, known as system and user modes, allow application-critical code to operate in safety while user code is prevented from inadvertently disturbing the setup of the processor. Memory blocks as small as 4 KB can be write-protected against accidental writes by user code, and stack over/underflows can be trapped by high-priority interrupts. Security features are also available in the Rabbit 5000. Portions of the new instruction set were introduced to increase encryption algorithm speeds dramatically, and 32 bytes of battery-backed RAM can store an encryption key away from prying eyes. The Rabbit 5000 supports eight channels of DMA access to internal or external memory, internal I/O addresses, and the external I/O bus. Directing a DMA channel to or from an internal peripheral such as a serial port or the Ethernet port automatically connects DMA enable signals. Burst size, priority, and guaranteed cycles for the processor are all under program control. The Rabbit 5000 contains an 802.11b/g wireless MAC peripheral, also designed to operate with the DMA peripheral. It includes support for all standard Wi-Fi features, including infrastructure and ad-hoc modes. The high-speed internal A/D converter and D/A converter and clocked-serial control port provide a generic interface to several common Wi-Fi transceivers. A low-speed A/D converter is also available to monitor the transmit signal strength if desired. The two A/D converters and single D/A converter are available for customer use when the Wi-Fi peripheral is disabled. The Rabbit 5000 also contains a full-featured 10/100Base-T Ethernet MAC peripheral. Designed to operate with the DMA peripheral, the Ethernet peripheral is fully compliant with the 802.3 Ethernet standard, including support for auto-negotiation, link detection, multicast filtering, and broadcast addresses. An industry-standard MII interface is used to connect to an external PHY device.
Chapter 1 The Rabbit 5000 Processor
15
1.3 Block Diagram

SMODE0 /BUFEN /IORD /WDTOUT SMODE1 RESOUT /RESET /IOWR STATUS CLK
D[7:0] (8-bit mode) or D[15:0] (16-bit mode)
Data Buffer
External Interface
SYSTEM/USER
CPU
A[23:0]
ADDRESS BUS
Address Buffer Spectrum Spreader
Memory Management/ Control Clock Doubler
Memory Chip Interface 128K SRAM Parallel Ports Port A Port B Port C Port D Port E
/CS2, /CS1, /CS0 /OE1, /OE0 /WE1, /WE0
CLKI CLKIEN
Fast Clock
Global Power Save & Clock Distribution
(15 bits)
PA [7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PH[7:0]
TIMER C[3:0]
Timer C Timer A VBAT RAM

(32 bytes) batterybackable
Port H Serial Port A

Asynch Synch Serial Serial Asynch Synch Bootstrap Bootstrap Asynch Serial IrDA IrDA Bootstrap
TXA, RXA, CLKA, ATXA, ARXA
Timer B
CLK32K
32.768 kHz Clock Input
Real-Time Clock
(16 bits)
Serial Ports B,C,D
TXB, RXB, CLKB, ATXB, ARXB TXC, RXC, CLKC TXD, RXD, CLKD
Watchdog Timer Secondary Watchdog Periodic Interrupt

WAIT ID[7:0] IA[7:0] I[7:0] INT0A, INT1A INT0B, INT1B DREQ0[B:A] DREQ1[B:A]
DATA BUS
Asynch Serial
Synch Serial
Asynch Serial IrDA
Serial Ports E, F
Asynch Serial HDLC SDLC Asynch Serial IrDA HDLC/SDLC IrDA
TXE, RXE TCLKE, RCLKE TXF, RXF TCLKF, RCLKF
External I/O Chip Interface External Interrupts DMA (8 channels)
Pulse Width Modulation Quadrature Decoder Input Capture Slave Port
PWM[3:0] QD1A, QD1B QD2A, QD2B AQD1A, AQD1B AQD2A, AQD2B PC[7,5,3,1] PD[7,5,3,1] PE[7,5,3,1] SD[7:0] SA[1:0], /SCS, /SRD, /SWR, /SLAVEATTN
25 MHz
25 shared I/O
10/100Base-T Ethernet
802.11a/b/g Wi-Fi 10-bit High-Speed DAC 10-bit High-Speed ADC 10-bit slow ADC
20 MHz
Slave Interface Bootstrap Interface
16
1.4 Basic Specifications

Two versions of the Rabbit 5000 are availablethe standard 289-ball BGA and a compact 196-ball BGA for specialty Wi-Fi applications. The larger package is intended for most Rabbit applications; the smaller package has specific features and limitations, and is not presently offered for sale. If you need further information, please contact your Rabbit sales representative.
Table 1-1. Rabbit 5000 Specifications and Features
Package Package Size Operating Voltage Operating Current Operating Temp. Maximum Clock Speed Digital I/O Network Interfaces Serial Ports Baud Rate Address Bus Data Bus Timers Real-Time Clock RTC Oscillator Circuitry Watchdog Timer/Supervisor Clock Modes Power-Down Modes External I/O Bus A/D Converters D/A Converters 48+ (arranged in six 8-bit ports) 10/100Base-T 802.11b/g Wi-Fi 6 CMOS-compatible 289-ball BGA 196-ball BGA
15 mm 15 mm 1.4 mm 12 mm 12 mm 1.2 mm 1.8 V DC core, 3.3 V DC I/O ring 0.57 mA/MHz @ 1.8 V/3.3 V (Wi-Fi and Ethernet diabled) -40C to +85C 100 MHz 19 802.11b/g Wi-Fi 2 CMOS-compatible
Clock speed/8 max. asynchronous 20/24-bit 8/16-bit 8-bit 8/16-bit
Ten 8-bit, one 10-bit with 2 match registers, and one 16-bit with 8 match registers Yes, battery-backable External Yes 1, 2, /2, /3, /4, /6, /8 Sleepy (32 kHz) Ultra-Sleepy (16, 8, 2 kHz) 8 data, 8 address lines No
10-bit, 2 synchronous channels, up to 40 megasamples/s 10-bit, single channel, up to 300 ksamples/s 10-bit, 2 synchronous channels, up to 40 megasamples/s
17
1.5 Comparing Rabbit Microprocessors

The Rabbit 2000, Rabbit 3000, Rabbit 4000, and Rabbit 5000 features are compared below.
Feature Maximum Clock Speed, industrial Maximum Clock Speed, commercial Maximum Crystal Frequency Main Oscillator (may be doubled internally up to maximum clock speed) 32.768 kHz Crystal Oscillator Operating Voltage, core Operation Voltage, I/O Maximum I/O Input Voltage Rabbit 5000 100 MHz 100 MHz Rabbit 4000 60 MHz 60 MHz Rabbit 3000 55.5 MHz 58.8 MHz Rabbit 2000 30 MHz 30 MHz
100 MHz
60 MHz
30 MHz
30 MHz
External 1.8 V 10% 3.3 V 10% 3.6 V 0.57 mA/MHz @ 1.8 V/3.3 V (Wi-Fi and Ethernet disabled) 289/196 N/A 15 15 1.4 12 12 1.2 0.8 mm Yes Yes 1, 2, /2, /3, /4, /6, /8 32 kHz 16, 8, 4, 2 kHz Short and Self-Timed Chip Selects Yes 6
External 1.8 V 10% 3.3 V 10% 3.6 V
External 3.3 V 10% 5.5 V
Internal 5.0 V 10% 5.5 V
Current Consumption
0.35 mA/MHz @ 3.3 V
2 mA/MHz @ 3.3 V
4 mA/MHz @5V
Number of Package Pins Size of Package, LQFP/PQFP Spacing Between Package Pins Size of Package, BGA (mm) Spacing Between Package Pins Separate Power and Ground for I/O Buffers (EMI reduction) Clock Spectrum Spreader Clock Modes Powerdown Modes, sleepy Powerdown Modes, ultra sleepy Low-Power Memory Control Extended Memory Timing for High-Frequency Operation Number of 8-bit I/O Ports
128
128
100
16 16 1.5 mm 16 16 1.5 mm 24 18 3 mm 0.4 mm (16 mils) 0.4 mm (16 mils) 0.65 mm (26 mils) 10 10 1.2 0.8 mm Yes Yes 1, 2, /2, /3, /4, /6, /8 32 kHz 16, 8, 4, 2 kHz Short and Self-Timed Chip Selects Yes 5 10 10 1.2 Not available 0.8 mm Yes Yes 1x, 2x, /2, /3 /4, /6, /8 32 kHz 16, 8, 4, 2 kHz Short and Self-Timed Chip Selects Yes 7 No Rabbit 2000B/C 1x, 2x, /4, /8 32 kHz
None
No 5
18
Feature Auxiliary I/O Data/Address Bus Number of Serial Ports Serial Ports Capable of SPI/ Clocked Serial Serial Ports Capable of SDLC/ HDLC Asynch Serial Ports With Support for IrDA Communication Serial Ports with Support for SDLC/HDLC IrDA Communication Maximum Asynchronous Baud Rate Ethernet Port Wi-Fi PWM Outputs Variable-Phase PWM Outputs (PPM) Input Capture Units Quadrature Decoders
Rabbit 5000 Yes 6 4 (A, B, C, D) 2 (E, F) 6
Rabbit 2000 None 4 2 (A, B) None None
None
Clock Speed/8 10/100Base-T Yes 4 4 2 2 channels
Clock Speed/8 10Base-T No 4 4 2 2 channels
Clock Speed/8 None No 4 None 2 2 channels
Clock Speed/32 None No None None None None
19
20
2. CLOCKS
2.1 Overview
The Rabbit 5000 supports up to three separate clocks at oncethe main clock, the 32 kHz clock, and the 20 MHz Wi-Fi clock. The main clock is used to drive the processor clock and the peripheral clock inside the processor. The 32 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers. The Rabbit 5000 has a spectrum spreader on the main clock that shortens and lengthens clock cycles. This has the net effect of reducing the peak energy of clock harmonics by spreading the spectral energy into nearby frequencies, which reduces EMI and facilitates government-mandated EMI testing. Gated clocks are used whenever possible to avoid clocking unused portions of the processor, and separate power-supply pins for the core and I/O ring further reduce EMI from the Rabbit 5000. The main clock can be doubled or divided by 2, 4, 6, or 8 to reduce EMI and power consumption. The 32 kHz clock (which can be divided by 2, 4, 8, or 16) can be used instead of the main clock to generate processor and peripheral clocks as low as 2 kHz for significant power savings. Note that dividing the 32 kHz clock only affects the processor and peripheral clocks; the full 32 kHz signal is still provided to the real-time clock and watchdog timer peripherals that use it directly. The periodic interrupt is disabled automatically since there is not enough time to process it when running off the 32 kHz clock. There is also a 25 MHz Ethernet clock that is provided to the external PHY chip if you are using the Ethernet option, but this Ethernet clock is not applied directly to the Rabbit 5000. The Ethernet clock can be driven by the processor clock, the processor clock divided by 2, or by the input on PE6. The Ethernet clock needs to be 25 MHz to conform to the 10/100Base-T specification. See Chapter 22 for more details on the Ethernet clock.
Chapter 2 Clocks
21
2.1.1 Block Diagram
CLK_IN
PLL
Wi-Fi Clock
CLKIEN
Clock Disable GCSR Spectrum Spreader GCMxR
MAIN CLOCK
CLKI
Clock Doubler GCDR
Divide by 2, 4, 6, 8 GCSR
GCSR
CPU Clock
Peripheral Clock CLK32K Divide by 2, 4, 8, 16 GPSCR GOCR
CLK Pin Divide by 2
Real-Time Clock Periodic Interrupt Asynch. Serial Bootstrap Watchdog Timer
2.1.2 Registers
Register Name Global Control/Status Register Global Clock Modulator 0 Register Global Clock Modulation 1 Register Global Clock Double Register Mnemonic GCSR GCM0R GCM1R GCDR I/O Address 0x0000 0x000A 0x000B 0x000F R/W R/W W W R/W Reset 11000000 00000000 00000000 00000000
22
2.2 Dependencies
2.2.1 I/O Pins The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to mitigate any noise problems associated with slowly transitioning signals. The main clock disable output is on the CLKIEN pin. Its state is changed by one of the bit combinations of bits 4:2 in GCSR. The CLKIEN pin will output low to disable an external main oscillator when the 32 kHz mode with main oscillator disabled is selected, and will output high for all other clock modes The 32 kHz clock input is on the CLK32K pin. There is an internal Schmitt trigger on this pin as well. The peripheral clock or peripheral clock divided by 2 may be optionally output on the CLK pin by enabling it via bits 7:6 in GOCR. The 20 MHz Wi-Fi clock input is located on the CLK_IN pin; a PLL multiplies clocks up to the 80 MHz required for the Wi-Fi peripheral. 2.2.2 Other Registers
Register GOCR Function Used to set up the CLK output pin.
Chapter 2 Clocks
23
2.3 Operation
2.3.1 Main Clock The main clock is input on the CLKI pin, and is optionally sent through the spectrum spreader and then the clock doubler. Both of these are described in greater detail below. Different main clock modes may be selected via the GCSR, as shown in Table 2-1. Note that one GCSR setting slows the processor clock while the peripheral clock operates at full speed; this allows some power reduction while keeping settings like serial baud rates and the PWM at their desired values.
Table 2-1. Clock Modes
GCSR Setting xxx010xx xxx011xx xxx110xx xxx111xx xxx000xx xxx001xx xxx100xx Processor Clock Main clock Main clock / 2 Main clock / 4 Main clock / 6 Main clock / 8 Main clock / 8 32 kHz clock (possibly divided) 32 kHz clock (possibly divided); main clock disabled via CLKIEN output signal Peripheral Clock Main clock Main clock / 2 Main clock / 4 Main clock / 6 Main clock / 8 (default on startup) Main clock 32 kHz clock (possibly divided via GPSCR) 32 kHz clock (possibly divided via GPSCR)
xxx101xx
When the 32 kHz clock is enabled in GCSR, it can be further divided by 2, 4, 6, or 8 to generate even lower frequencies by enabling those modes in bits 02 of GPSCR. See Table 2-4 for more details.
24
2.3.2 Spectrum Spreader When enabled, the spectrum spreader stretches and compresses the main clock in a complex pattern that spreads the energy of the clock harmonics over a wider range of frequencies.
Spectrum Spreader Disabled -10
AMPLITUDE (dB)
Spectrum Spreader Enabled (normal setting)
-20
-30
-40
-50 400
405
410
415
420
425
430
435
FREQUENCY (MHz)
Figure 2-1. Effects of Spectrum Spreader
There are three settings that correspond to normal and strong spreading in the 050 MHz and >50 MHz main clock range. Each setting will affect the clock cycle differently; the maximum cycle shortening (at 1.8 V and 25C) is shown in Table 2-2 below.
Table 2-2. Spectrum Spreader Settings
050 MHz > 50 MHz Normal GCM0R Value 0x40 Description Normal spreading of frequencies over 50 MHz Normal spreading of frequencies up to 50 MHz; strong spreading of frequencies over 50 MHz Strong spreading of frequencies up to 50 MHz; normal spreading of frequencies over 50 MHz Max. Cycle Shortening 2.3 ns
Normal
Strong
0x00
3 ns
Strong
0x80
4.5 ns
Chapter 2 Clocks
25
The spectrum spreader either stretches or shrinks the low plateau of the clock by a maximum of 3 ns for the normal spreading and up to 4.5 ns for the strong spreading. If the clock doubler is used, this will cause an additional asymmetry between alternate clock cycles. Both normal and strong modes reduce clock harmonics by approximately 15 dB for frequencies above 100 MHz; for lower frequencies the strong setting has a greater effect in reducing the peak spectral strength as shown in Figure 2-2.
15 Strong Spreading 10 Normal Spreading 5
Harmonics (dB)
50
100
150
200
250
300
350
Frequency (MHz)
Figure 2-2. Peak Spectral Amplitude Reduction by Spectrum Spreader
Two registers control the clock spectrum spreader. These registers must be loaded in a specific manner with proper time delays. GCM0R is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by storing 0x080 in GCM1R. If GCM1R is cleared (when disabling the spectrum spreader), there is up to a 500-clock delay before the spectrum spreader is actually disabled. The proper procedure is to clear GCM1R, wait for 500 clocks, set GCM0R, and then enable the spreader by storing 0x080 in GCM1R. The spectrum spreader is applied to the main clock before the clock doubler, so if both are enabled there will be additional asymmetry between alternate clock cycles.If the clock doubler is used, the spectrum spreader affects every other cycle and reduces the clock high time. If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced.
26
2.3.3 Clock Doubler The clock doubler allows a lower frequency crystal to be used for the main oscillator and to provide an added range over which the clock frequency can be adjusted. The clock doubler is controlled via the Global Clock Double Register (GCDR). The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock. Table 2-3 lists the recommended delays in GCDR for various oscillator or crystal frequencies.
Table 2-3. Recommended Delays Set In GCDR for Clock Doubler
Recommended GCDR Value 0x0F 0x0B 0x09 0x06 0x03 0x01 0x00 Frequency Range 7.3728 MHz 7.372811.0592 MHz 11.059216.5888 MHz 16.588820.2752 MHz 20.275252.8384 MHz 52.838477.4144 MHz >77.4144 MHz
Chapter 2 Clocks
27
When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 2-3.
P
Oscillator Oscillator delayed and inverted Doubled clock

Delay time
48%
52%
0.48P
0.52P
0.48P
0.52P
Example Write Cycle
Address / CS Data out
Write pulse Early write pulse option Address / CS
Example Read Cycle
Data out from mem Output enb Early output enb option
Figure 2-3. Effect of Clock Doubler
The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The times given above are for a core supply voltage of 1.8 V and a temperature of 25C. The values increase or decrease by 1% for each 5C increase or decrease in temperature. The doubled clock is created by xoring the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle of the built-in oscillator can be as asymmetric as 52%/48%, the clock generated by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. The memory access time is not affected because the memory bus cycle is 2 clocks long and includes both a long and a short
clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly The maximum allowed clock speed must be reduced slightly if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses, and the early option memory output enable. See Chapter 5 for more information on the early output enable and write enable options. The power consumption is proportional to the clock frequency, and for this reason power can be reduced by slowing the clock when less computing activity is taking place. The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme.
Chapter 2 Clocks
29
2.3.4 32 kHz Clock The 32.768 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers. If these features are not used in a design, the use of the 32 kHz clock is optional. A simplified version of the recommended oscillator circuit for the Rabbit 5000 is shown below. The values of resistors and capacitors may need to be adjusted for various frequencies and crystal load capacitances. Technical Note TN235, External 32.768 kHz Oscillator Circuits, is available on the Rabbit Web site and goes into this circuit in detail.
VBAT R1
R1 and R2 control the power consumed by the unbuffered inverter.
Cin
R2
SN74AHC1GU04
U1A
NC7SP14
U2A
Rp Rs CL = 5-12 pF 32.768 kHz C1 C2
C1 values may vary or C1 may be eliminated
Figure 2-4. Basic 32.768 kHz Oscillator Circuit
The 32.768 kHz circuit consumes microampere-level currents and has a very high impedance, making it susceptible to noise, moisture, and environmental contaminants. It is strongly recommended to conformally coat this circuit to limit the effects of humidity and dust on the oscillation frequency. Details about this requirement are available in Technical Note TN303, Conformal Coating, from the Rabbit Web site. The 32.768 kHz oscillator is slow to start oscillating after power-on. The startup delay may be as much as 5 seconds. For this reason, a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure. If the clock is battery-backed, there will be no startup delay since the oscillator is already oscillating. Crystals with low series resistance (R < 35 k) will start faster.
30
The 32 kHz oscillator can be used to drive the processor and the peripheral clock to provide significant power savings in ultra-sleepy modes. The 32 kHz oscillator can be divided by 2, 4, 8, or 16 to provide clock speeds as low as 2.048 kHz. Special self-timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra-sleepy mode is enabled; see Chapter 29 for more details on reducing power consumption.
Table 2-4. Ultra-Sleepy Clock Modes
GPSCR Setting xxxxx000 xxxxx100 xxxxx101 xxxxx110 xxxxx111 Processor and Peripheral Clock 32.768 kHz 16.384 kHz 8.192 kHz 4.096 kHz 2.048 kHz
When the 32 kHz clock is enabled, the periodic interrupt is disabled automatically. The real-time clock and watchdog timers keep running, and use the full 32 kHz clock speed even when the processor and peripheral clocks use a divider on the 32 kHz clock.
Chapter 2 Clocks
31
2.4 Register Descriptions

Global Control/Status Register Bit(s) 7:6 (rd-only) Value 00 01 10 11 5 0 1 4:2 000 (GCSR) Description No reset or watchdog timer timeout since the last read. The watchdog timer timed out. These bits are cleared by a read of this register. This bit combination is not possible. Reset occurred. These bits are cleared by a read of this register. No effect on the periodic interrupt. This bit will always be read as zero. Force a periodic interrupt to be pending. Processor clock from the main clock, divided by 8. Peripheral clock from the main clock, divided by 8. Processor clock from the main clock, divided by 8. Peripheral clock from the main clock. Processor clock from the main clock. Peripheral clock from the main clock. Processor clock from the main clock, divided by 2. Peripheral clock from the main clock, divided by 2. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The main clock is disabled. Processor clock from the main clock, divided by 4. Peripheral clock from the main clock, divided by 4. Processor clock from the main clock, divided by 6. Peripheral clock from the main clock, divided by 6. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. (Address = 0x0000)
001
010
011
100
101
110
111 1:0 00 01 10 11
32
Global Clock Modulator 0 Register Bit(s) 7:6 Value 00 01 10 11 5:0
(GCM0R) Description
(Address = 0x000A)
Clock dither in 1 ns steps, from 0 ns to 26 ns. Do not modify while the dither function is enabled. Clock dither in 0.5 ns steps, from 0 ns to 13 ns. Clock dither in 2 ns steps, from 0 ns to 52 ns. This bit combination is reserved and must not be used. These bits are reserved and should be written with zeros.
Global Clock Modulator 1 Register Bit(s) 7 Value 0 1 6:0
(GCM1R) Description
(Address = 0x000B)
Disable the clock dither function. The disable does not take effect until the dither pattern has returned to the 0 ns base delay value. Enable the clock dither function. These bits are reserved and should be written with zeros.
Chapter 2 Clocks
33
Global Clock Double Register Bit(s) 7:5 4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10001 10010 10011 other Value
(GCDR) Description
(Address = 0x000F)
These bits are reserved and should be written with zeros. The clock doubler circuit is disabled. 6 ns nominal low time. 7 ns nominal low time. 8 ns nominal low time. 9 ns nominal low time. 10 ns nominal low time. 11 ns nominal low time. 12 ns nominal low time. 13 ns nominal low time. 14 ns nominal low time. 15 ns nominal low time. 16 ns nominal low time. 17 ns nominal low time. 18 ns nominal low time. 19 ns nominal low time. 20 ns nominal low time. 3 ns nominal low time. 4 ns nominal low time. 5 ns nominal low time. Any bit combination not listed is reserved and must not be used.
34
Global Output Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(GOCR) Description
(Address = 0x000E)
CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. CLK pin is low. CLK pin is high. STATUS pin is active (low) during a first opcode byte fetch. STATUS pin is active (low) during an interrupt acknowledge. STATUS pin is low. STATUS pin is high. /WDTOUT pin functions normally. Enable /WDTOUT for test mode. Rserved for internal use only. /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz). This bit combination is reserved and should not be used. /BUFEN pin is active (low) during external I/O cycles. /BUFEN pin is active (low) during data memory accesses. /BUFEN pin is low. /BUFEN pin is high.
Chapter 2 Clocks
35
36
3. RESET AND BOOTSTRAP

3.1 Overview
The Rabbit 5000s /RESET pin initializes everything in the processor except for the realtime clock registers and the contents of the battery-backed onchip-encryption RAM. If a write cycle is in progress, it waits until the write cycle is completed to avoid potential memory corruption. After reset, the Rabbit 5000 checks the state of the SMODE and SYSCFG pins. Depending on the state of the SMODE pins, it either begins normal operation by fetching instruction bytes from memory bank zero, which is mapped to either /CS0 or /CS3 depending on the state of the SYSCFG0 pin, or it enters a special bootstrap mode where it fetches bytes from either Serial Port A or the slave port. In this mode, bytes can be written to internal registers to set up the Rabbit 5000 for a particular configuration, or to memory to load a program. The processor can begin normal operation once the bootstrap operation is completed.
Chapter 3 Reset and Bootstrap
37
3.1.1 Block Diagram

Reset
/RESET
Reset Delay CPU Clock
Master Reset
Rabbit 5000
Bootstrap SPCR Asynch Serial Bootstrap SMODE0 SMODE1 Bootstrap Selection Serial Flash Bootstrap Slave Port Bootstrap Normal Operation
Internal SRAM is on /CS0 SYSCFG0 SRAM Chip Select Internal SRAM is on /CS3
3.1.2 Registers
Register Name Slave Port Control Register Mnemonic SPCR I/O Address 0x0024 R/W R/W Reset 0xx00000
38
3.2 Dependencies
3.2.1 I/O Pins SMODE0, SMODE1 When the Rabbit 5000 is first powered up or when it is reset, the state of the SMODE0 and SMODE1 pins controls its operation. SYSCFG0 When the Rabbit 5000 is first powered up or when it is reset, the state of this pin controls whether memory bank zero is mapped to /CS0 or the internal SRAM (/CS3). SYSCFG1 This pin should always be tied to ground. /RESET Pulling the /RESET pin low will initialize everything in the Rabbit 5000 except for the real-time clock registers and the onchip-encryption RAM. /CS1 During reset the impedance of the /CS1 pin is high, and all other memory and I/O control signals are held high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the VBATIO pin (which powers /CS1). In this case, a pullup resistor is required on /CS1 to keep the RAM deselected during powerdown. RESOUT The RESOUT pin, which is powered by the backup battery, is high during reset and powerdown as long as VBAT and VBATIO are present, but low at all other times, and can be used to control an external power switch to disconnect VDDIO from VBATIO when the main power source is removed. 3.2.2 Clocks The processor requires a 32 kHz clock input to generate the 2400 bps internal clock required for asynchronous serial bootstrap, which is used when booting via Dynamic C and the Rabbit Field Utility. No 32 kHz clock is required for either clocked serial or slave port bootstrap. When the processor comes out of reset, the CPU clock and peripheral clocks are both in divide-by-8 mode. 3.2.3 Other Registers
Register SPCR Function Enable/disable processor monitoring of SMODE pins; read current state of SMODE pins.
3.2.4 Interrupts There are no interrupts associated with reset or bootstrap.
39
3.3 Operation
Pulling the /RESET pin low will initialize everything in the Rabbit 5000 except for the real-time clock registers and the onchip-encryption RAM. The reset of the Rabbit 5000 is delayed until any write cycles in progress are completed; the reset takes effect as soon as no write cycles are occurring. The reset sequence requires a minimum of 128 cycles of the main clock to complete in either case. During reset, the impedance of the /CS1 pin is high and all other memory and I/O control signals are held high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the VBATIO pin (which powers /CS1). In this case, a pullup resistor is required on /CS1 to keep the RAM deselected during powerdown. The RESOUT pin, which is powered by the backup battery, is high during reset and powerdown as long as VBAT and VBATIO are present, but low at all other times, and can be used to control an external power switch to disconnect VDDIO from VBATIO when the main power source is removed. Table 3-1 lists the condition of the processor after reset takes place. The state of all registers after reset is provided in the chapter describing the specific peripheral.
Table 3-1. Rabbit 5000 Condition After Reset
Function CPU Clock, Peripheral Clock Clock Doubler, Clock Dither Memory Bank 0 Control Register Memory Advanced Control Register CPU Registers: PC, SP, IIR, EIR, SU, HTR Interrupt Priority (IP Register) Watchdog Timer Secondary Watchdog Timer Operation After Reset Divide-by-8 mode Disabled /CS0, /OE0, write-protected, 4 wait states 8-bit interface
0x0000
0xFF (Priority 3) Enabled (2 seconds) Disabled
40
The processor checks the SMODE and SYSCFG0 pins after the /RESET signal is inactive. Table 3-2 summarizes what happens.
Table 3-2. SMODE Pin Settings
SMODE Pins [1,0] 00 SYSCFG0 0 Operation No bootstrap; code is fetched from address 0x0000 on /CS0, /OE0. No bootstrap; code is fetched from address 0x0000 on /CS3, /OE0. The internal SRAM is enabled as a 16-bit memory device. Bootstrap from the slave port. Bootstrap from Serial Port A, serial flash mode. Bootstrap from Serial Port A, asynchronous mode.
00 01 10 11
1 x x x
If both SMODE pins are zero, the Rabbit 5000 begins fetching instructions from the memory device mapped into memory bank 0. When SYSCFG0 is low, memory bank 0 is set to /CS0 and /OE0. If SYSCFG0 is high, memory bank 0 is set to /CS3 and /OE0, and the internal SRAM is selected in 16-bit mode. If a 16-bit memory is used in memory bank 0, the first section of code must immediately select the 16-bit bus mode. Chapter 5 provides a short sample program to do this. If either of the SMODE pins is high, the processor will enter the bootstrap mode and accept triplets from Serial Port A, the serial flash bootstrap port, or the slave port, depending on the SMODE pin selection. It is good practice to place pulldown resistors on the SMODE pins to ensure the proper operation of your design. In the bootstrap mode, the processor inhibits the normal memory fetch, and instead fetches instructions from a small internal boot ROM. This program reads triplets of three bytes from the selected peripheral. The first byte is the most-significant byte of a 16-bit address, the second byte is the least-significant byte of the address, and the third byte is the data to be written. If the uppermost bit of the address is 1, then the address is assumed to be an internal register address instead of a memory address, and the data are written to the appropriate register instead. For example, a triplet of (0x04, 0x34, 0x5A) will write 0x5A to logical memory address 0x0434, while a triplet of (0x80, 0x34, 0x5A) will write 0x5A to processor register 0x34. Processor registers with addresses above 0xFF are not accessible in the bootstrap mode. The boot ROM program waits for data to be available; each byte received automatically resets the watchdog timer with a 2-second timeout. Bytes must be received quickly enough to prevent timeout (or the watchdog must be disabled). The device checks the state of the SMODE pins each time it jumps back to the start of the ROM program and responds according to the current state. In addition, by setting bit 7 of
41
the Slave Port Control Register (SPCR) high, the processor can be told to ignore the state of the SMODE pins and continue normal operation. Note that the processor can be told to re-enter bootstrap mode at any time by setting bit 7 of SPCR low; once this occurs and the least significant four bits of the current PC address are zero, the processor will sample the state of the SMODE pins and respond accordingly. This feature allows in-line downloading from the selected bootstrap port; once the download is complete, bit 7 of SPCR can be set high and the processor will continue operating from where it left off. As a security feature, any attempt to enter the bootstrap mode from either the SMODE pins or by writing to bit 7 of the SPCR will erase the data stored in the onchip-encryption RAM. This prevents loading a small program in memory to read out the data. 3.3.1 Asynchronous Serial Bootstrap When the asynchronous serial bootstrap mode is selected by the SMODE pins, the Rabbit 5000 will being accepting triplets at 2400 bps on Serial Port A. The baud rate is generated from the 32 kHz clock input, so a 32 kHz clock is required for this mode. 3.3.2 Serial Flash Bootstrap When the serial flash bootstrap mode is selected by the SMODE pins, the Rabbit 5000 will enable the SPI serial flash bootstrap port on pins PD4, PD5, PD6, and PB0; the pins functionality is listed in Table 3-3 below. Note that these pins can be used for Serial Port B in normal operation, so the serial flash may use the serial port as a regular serial port if desired.
Table 3-3. Serial Flash Bootstrap Pin Functions
Pin PD4 PD5 PD6 PB0 SPI Signal MOSI MISO CS SCK Operation Rabbit data transmit (to serial flash) Rabbit data receive (from serial flash) Chip select (to serial flash) Serial clock (output to serial flash)
The Rabbit 5000 divides the main clock by 64 to provide the SPI clock for the serial flash bootstrap. Once this mode is entered, the Rabbit 5000 will send the byte sequence "0x03 0x00 0x00 0x00", which is an industry-standard command that enables continuous read mode starting at serial flash address 0x0. Figure 3-1 provides a sample timing diagram. The Rabbit 5000 will then read triplets out of the serial flash until the bootstrap mode is exited.
42
CE# SCK MODE 0 SI

MSB MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
O3
ADD MSB HIGH IMPEDANCE
ADD
ADD N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT
SO
Figure 3-1. SPI Timing Diagram for Serial Flash Bootstrap Mode
3.3.3 Parallel Bootstrap When the parallel bootstrap mode is selected by the SMODE pins, the Rabbit 5000 will enable the parallel slave port interface on Parallel Ports A and B, and will wait for triplets to be sent to that interface. See Chapter 19 for more details on the operation of the slave port.
43

Slave Port Control Register Bit(s) 7 Value 0 1 6:5 Read Write 4:2 000 001 010 011 100 101 110 111 1:0 00 01 10 11 (SPCR) Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. These bits are ignored and should be written with zero. Disable the slave port. Parallel Port A is a byte-wide input port. Disable the slave port. Parallel Port A is a byte-wide output port. Enable the slave port, with /SCS from Parallel Port E bit 7. Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:2] is used for the address bus. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. Enable the slave port, with /SCS from Parallel Port B bit 6. Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3. (Address = 0x0024)
44
4. SYSTEM MANAGEMENT
4.1 Overview
There are a number of basic system peripherals in the Rabbit 5000 processor, some of which are covered in later chapters. The peripherals covered in this chapter are the periodic interrupt, the real-time clock, the watchdog timers, the battery-backed onchip-encryption RAM, and some of the miscellaneous output pins and their control and processor registers that provide the processor ID and revision numbers. The periodic interrupt, when enabled, is generated every 16 clocks of the 32 kHz clock (every 488 s, or 2.048 kHz). This interrupt can be used to perform periodic tasks. The real-time clock (RTC) consists of a 48-bit counter that is clocked by the 32 kHz clock. It is powered by the VBAT pin, and so can be battery-backed. The value in the counter is not affected by reset, and can only be set to zero by writing to the RTC control register. The 48-bit width provides a 272-year span before rollover occurs. There are two watchdog timers in the Rabbit 5000, both clocked by the 32 kHz clock. The main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the processor if not reloaded within that time. Its purpose is to restart the processor when it detects that a program gets stuck or disabled. The secondary watchdog timer can time out from 30.5 s up to 7.8 ms, and generates a Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt if the secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the periodic interrupt stops occurring. In addition, it can be used as a periodic interrupt on its own. The battery-backed onchip-encryption RAM consists of 32 bytes of memory that are powered by the VBAT pin. Their values are not affected by reset, but are erased if the state of the SMODE pins changes. These 32 bytes are intended for storing sensitive data (such as an encryption key) somewhere other than an external memory device. The tamperprotection erase feature prevents loading a program into the onchip-encryption RAM via the programming port and reading out the bytes. The following other registers are also described in this chapter. Global Output Control Register (GOCR), which controls the behavior of the CLK, STATUS, /WDT, and /BUFEN pins Global CPU Register (GCPU), which holds the identification number of the processor. Global Revision Register (GREV), which hold the revision number of the processor.
Chapter 4 System Management 45
4.1.1 Block Diagram

Basic System Peripherals
32 kHz Clock
Periodic Interrupt (488 s) GCSR
Interrupt Generation
Interrupt Request
Real-Time Clock RTCxR RTCCR Watchdog Timer WDTCR WDTTR Secondary Watchdog Timer WDTCR SWDTR Interrupt Generation Interrupt Request Master Reset /WDTOUT Pin
46
4.1.2 Registers
Register Name Global Control/Status Register Real-Time Clock Control Register Real-Time Clock Byte 0 Register Real-Time Clock Byte 1 Register Real-Time Clock Byte 2 Register Real-Time Clock Byte 3 Register Real-Time Clock Byte 4 Register Real-Time Clock Byte 5 Register Watchdog Timer Control Register Watchdog Timer Test Register Secondary Watchdog Timer Register Global Output Control Register Global ROM Configuration Register Global RAM Configuration Register Global CPU Configuration Register Global Revision Register Battery-Backed Onchip-Encryption RAM Byte 001F Mnemonic GCSR RTCCR RTC0R RTC1R RTC2R RTC3R RTC4R RTC5R WDTCR WDTTR SWDTR GOCR GROM GRAM GCPU GREV VRAM00 VRAM1F I/O Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000C 0x000E 0x002C 0x002D 0x002E 0x002F 0x06000x061F R/W R/W W R/W R R R R R W W W R/W R R R R R/W Reset 11000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 11111111 00000000 0xx00000 0xx00000 0xx00010 0xx00000 xxxxxxxx
Chapter 4 System Management
47
4.2 Dependencies
4.2.1 I/O Pins The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of these pins can be used as general-purpose outputs by driving them high or low. The CLK pin can output the peripheral clock, the peripheral clock divided by two, or be driven high or low. The STATUS pin can be active low during the first byte of each opcode fetch, active low during an interrupt acknowledge, or driven high or low. The /WDTOUT pin can be active low whenever the watchdog timer resets the device or driven low. The /BUFEN pin can be active low during external I/O cycles, active low during data memory cycles, or driven high or low. The values in the battery-backed onchip-encryption RAM bytes are cleared if the signal on the SMODE pins changes state. 4.2.2 Clocks The periodic interrupt, real-time clock, watchdog timer, and secondary watchdog timer require the 32 kHz clock. 4.2.3 Interrupts The periodic interrupt is enabled in GCSR, and will occur every 488 s. It is cleared by reading GCSR. It can operate at Priority 1, 2, or 3. The secondary watchdog interrupt will occur whenever the secondary watchdog is enabled and allowed to count down to zero. It is cleared by restarting the secondary watchdog by writing to WDTCR. The secondary watchdog interrupt always occurs at Priority 3.
48
4.3 Operation
4.3.1 Periodic Interrupt The following steps explain how a periodic interrupt is used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Enable the periodic interrupt by writing to GCSR. 3. The interrupt request is cleared by reading from GCSR. A sample interrupt handler is shown below.
periodic_isr:: push af ioi ld a, (GCSR)
; clear the interrupt request and get status
; handle any periodic tasks here pop af ipres ret
4.3.2 Real-Time Clock The real-time clock consists of six 8-bit registers that together comprise a 48-bit value. The real-time clock is not synchronized to the read operation, so the least-significant bit should be read twice and checked for matching values; if the two reads do not match, then the real-time clock may have been updating during the read and should be read again. Writing to RTC0R latches the current real-time clock value into the RTCxR holding registers, so the following sequence should be used to read the real-time clock. 1. Write any value to RTC0R and then read back a value from RTC0R. 2. Write a value to RTC0R again, and again read back a value from RTC0R. 3. If the two values do not match, repeat Step 2 until the last two readings are identical. 4. At this point, registers RTC1R through RTC6R can also be read and used. Note that the periodic interrupt and the real-time clock are clocked by the same edge of the 32 kHz clock; if read from the periodic interrupt, the count is guaranteed to be stable and only needs to be read once (assuming it occurs within one clock of the 32 kHz clock). The real-time clock can be reset by writing the sequence 0x40 0x80 to RTCCR. It can be reset and left in the byte increment mode by writing 0x40 0xC0 to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time clock. The byte increment mode is disabled by writing 0x00 to RTCCR.
49
4.3.3 Watchdog Timer The watchdog timer is enabled on reset with a 2-second timeout. Unless specific data are written to WDTCR before that time expires, the processor will be reset. The watchdog timer can be disabled by writing a sequence of two bytes to WDTTR as described in the register description.
Table 4-1. Watchdog Timer Settings
WDTCR Value 0x5A 0x57 0x59 0x53 0x5F Effect Restart watchdog timer with 2-second timeout. Restart watchdog timer with 1-second timeout. Restart watchdog timer with 500-millisecond timeout. Restart watchdog timer with 250-millisecond timeout. Restart the secondary watchdog timer.
The watchdog timer also contains a special test mode that speeds up the timeout period by clocking it with the peripheral clock instead of the 32 kHz clock. This mode can be enabled by writing to WDTTR. 4.3.4 Secondary Watchdog Timer The secondary watchdog timer is disabled on reset. The following steps explain how to use the secondary watchdog timer. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Write the desired timeout period to SWDTR. This also enables the secondary watchdog timer. 3. Restart the secondary watchdog timer by either writing the timeout period to SWDTR or writing 0x5F to WDTCR. If the secondary watchdog timer counts down to zero, a Priority 3 secondary watchdog interrupt will occur. This interrupt request is cleared by writing a new timeout value to SWDTR. A sample interrupt handler is shown below.
secwd_isr:: push af ; determine why the interrupt occurred and take appropriate action ld a, 0x40 ioi ld (SWDTR), a pop af ipres ret ; timeout period of 0x40/32kHz = 1.95ms ; clear the interrupt request
50

Global Control/Status Register Bit(s) 7:6 (Readonly) Value 00 01 10 11 5 0 1 4:2 000 001 010 011 100 (GCSR) Description No reset or watchdog timer timeout since the last read. The watchdog timer timed out. These bits are cleared by a read of this register. This bit combination is not possible. Reset occurred. These bits are cleared by a read of this register. No effect on the periodic interrupt. This bit will always be read as zero. Force a periodic interrupt to be pending. Processor clock from the main clock, divided by eight. Peripheral clock from the main clock, divided by eight. Processor clock from the main clock, divided by eight. Peripheral clock from the main clock. Processor clock from the main clock. Peripheral clock from the main clock. Processor clock from the main clock, divided by two. Peripheral clock from the main clock, divided by two. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The main clock is disabled. Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. (Address = 0x0000)
101
110 111 1:0 00 01 10 11
51
Real-Time Clock Control Register Bit(s) 7:0 Value 0x00
(RTCCR) Description
(Address = 0x0001)
No effect on the real-time clock counter, or disable the byte increment function, or cancel the real-time clock reset command. Arm the real-time clock for reset or byte increment. This command must be written prior to either the real-time clock reset command or the first byte increment write. Reset all six bytes of the real-time clock counter to 0x00. The reset must be preceded by writing 0x40 to arm the reset function. Reset all six bytes of the real-time clock counter to 0x00, and remain in byteincrement mode in preparation for setting the time. This bit combination must be used with every byte-increment write. No effect on the real-time clock counter. Increment the corresponding byte of the real-time clock counter.
0x40
0x80 0xC0 7:6 5:0 01 0 1
Real-Time Clock x Register
(RTC0R) (RTC1R) (RTC2R) (RTC3R) (RTC4R) (RTC5R) Description
(Address = 0x0002) (Address = 0x0003) (Address = 0x0004) (Address = 0x0005) (Address = 0x0006) (Address = 0x0007
Bit(s) 7:0
Value Read Write
The current value of the 48-bit real-time clock counter is returned. Writing to RTC0R transfers the current count of the real-time clock to a holding register while the real-time clock continues counting.
Watchdog Timer Control Register Bit(s) 7:0 Value 0x5A 0x57 0x59 0x53 0x5F other
(WDTCR) Description
(Address = 0x0008)
Restart the watchdog timer with a 2-second timeout period. Restart the watchdog timer with a 1-second timeout period. Restart the watchdog timer with a 500 ms timeout period. Restart the watchdog timer with a 250 ms timeout period. Restart the secondary watchdog timer. No effect on watchdog timer or secondary watchdog timer.
52
Watchdog Timer Test Register Bit(s) 7:0 Value 0x51 0x52 0x53
(WDTTR) Description
(Address = 0x0009)
Clock the least significant byte of the watchdog timer from the peripheral clock. Clock the most significant byte of the watchdog timer from the peripheral clock. Clock both bytes of the watchdog timer, in parallel, from the peripheral clock. Disable the watchdog timer. This value, by itself, does not disable the watchdog timer. Only a sequence of two writes, where the first write is 0x51, 0x52, or 0x53, followed by a write of 0x54, actually disables the watchdog timer. The watchdog timer will be re-enabled by any other write to this register. Normal clocking (32 kHz clock) for the watchdog timer.
0x54
other
Secondary Watchdog Timer Register Bit(s) Value
(SWDTR) Description
(Address = 0x000C)
7:0
The time constant for the secondary watchdog timer is stored. This time constant will take effect the next time that the secondary watchdog counter counts down to zero. The timer counts modulo n + 1, where n is the programmed time constant. The secondary watchdog timer can be disabled by writing the sequence 0x5A 0x52 0x44 to this register.
Global ROM Configuration Register Bit(s) 7 (Readonly) 6:5 4:0 Value 0 1 Read 00000
(GROM) Description
(Address = 0x002C)
Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. ROM identifier for this version of the chip.
Global RAM Configuration Register Bit(s) 7 (Readonly) 6:5 4:0 Value 0 1 Read 00001
(GRAM) Description
(Address = 0x002D)
Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. RAM identifier for this version of the chip.
53
Global Output Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(GOCR) Description
(Address = 0x000E)
CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. CLK pin is low. CLK pin is high. STATUS pin is active (low) during a first opcode byte fetch. STATUS pin is active (low) during an interrupt acknowledge. STATUS pin is low. STATUS pin is high. /WDTOUT pin functions normally. Enable /WDTOUT for test mode. Reserved for internal use only. /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz). This bit combination is reserved and should not be used. /BUFEN pin is active (low) during external I/O cycles. /BUFEN pin is active (low) during data memory accesses. /BUFEN pin is low. /BUFEN pin is high.
Global CPU Register Bit(s) 7 (Readonly) 6:5 4:0 Value 0 1 Read 00011
(GCPU) Description
(Address = 0x002E)
Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. CPU identifier for this version of the chip.
Global Revision Register Bit(s) 7 (Readonly) 6:5 4:0 Value 0 1 Read 00011
(GREV) Description
(Address = 0x002F)
Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. CPU identifier for this version of the chip.
54
Battery-Backed Onchip-Encryption RAM
(VRAM00) through (VRAM31) Description
(Address = 0x0600) through (Address = 0x061F)
Bit(s) 7:0
Value
General-purpose RAM locations. Cleared by Intrusion Detect conditions.
55
56
5. MEMORY MANAGEMENT
5.1 Overview
The Rabbit 5000 supports both 8-bit and 16-bit external flash and SRAM devices; three chip selects and two read/write-enable strobes allow up to six external devices to be attached at once. The 8-bit mode allows 0, 1, 2, or 4 wait states to be specified for each device, and the 16-bit mode allows 0 to 7 wait states depending on the settings. Both 8-bit and 16-bit page-mode devices are also supported. In addition, the Rabbit 5000 contains 128 KB of internal SRAM that resides on its own chip select signal. It can be enabled in either 8- or 16-bit mode. The Rabbit 5000s physical memory space contains four consecutive banks, each of which can be mapped to an individual chip-select/enable strobe pair. The banks can be set for equal sizes ranging from 128 KB up to 4 MB, providing a total physical memory range from 512 KB up to 16 MB. Figure 5-1 shows a sample configuration.
Chapter 5 Memory Management
57
0xFFFFF Memory Bank 3 MB3CR = 0x86 0xC0000 0xBFFFF Memory Bank 2 MB2CR = 0xC5 0x80000 0x7FFFF Memory Bank 1 MB1CR = 0xC0 0x40000 0x3FFFF Memory Bank 0 MB0CR = 0xC0 0x00000 0 wait states /CS0 /OE0 /WE0 512KB Flash 0 wait states /CS1 /OE1 /WE1 256KB SRAM 1 wait state /CS2 /OE1 /WE1 256KB SRAM
1MB
Figure 5-1. Mapping Rabbit 5000 Physical Memory Space
Either one or both of the two most significant address bits (which are used to select the quadrant) can be inverted, providing the ability to bank-switch other pages from a larger memory device into the same memory bank. Code is executed in the 64 KB logical memory space, which is divided into four segments: root, data, stack, and XMEM. The root segment is mapped directly to physical address 0x000000, while the data and stack segments can be mapped to 4 KB boundaries anywhere in the physical space. The boundaries between the root and data segments and the data and stack segments can be adjusted in 4 KB blocks as well. The XMEM segment is a fixed 8 KB, and points to a physical memory address block specified in the XPC register. It is possible to run code in the XMEM window, providing an easy means of storing and executing code beyond the 64 KB logical memory space. Special call and return instructions to physical addresses are provided that automatically update the XPC register as necessary.
58
FFFFFF
16 MB
FFFF E000 y000
64 KB XPC STACK SEGMENT DATA SEGMENT
SEGSIZE x REGISTER y 43 0 (0x13) R/W 7

x000
ROOT
0000
000000
LOGICAL ADDRESS MAP
PHYSICAL ADDRESS MAP
Figure 5-2. Logical and Physical Memory Mapping
59
The Rabbit 2000 and 3000 had numerous instructions for reading and writing data to logical addresses, but only had limited support for reading and writing data to a physical memory address. In the Rabbit 4000, a wide range of instructions was provided to read and write to physical addresses. The same instructions can be used to write to logical addresses. All of these instructions are available in the Rabbit 5000. The 64 KB logical memory space limitation can also be expanded by using the separate instruction and data space mode. When this mode is enabled, address bit A16 is inverted for all data accesses in the root and/or data segments, and address bit A19 is inverted for all data accesses in the root and/or data segments before bank selection (physical device) occurs. These two features allow both code and data to access separate 64 KB logical spaces instead of sharing a single space. It is possible to protect memory in the Rabbit 5000 at three different levelseach of the memory banks can be made read-only, physical memory can be write-protected in 64 KB blocks, and two of those 64 KB blocks can be protected with a granularity of 4 KB. A Priority 3 interrupt will occur if a write is attempted in one of the protected 64 KB or 4 KB blocks. In addition, it is possible to place limits around the code execution stack and generate an interrupt if a stack-related write occurs within 16 bytes of those limits. 5.1.1 Block Diagram
Interrupt Handler
Interrupt Request
Logical or Physical Access
MMU MMIDR MECR RAMSR STKSEG* DATSEG* SEGSIZE
Physical Address
Memory Protection WPCR WPxR WPSyR WPSyLR WPSyHR STKCR STKzLR
Memory Bank Control MBxCR MTCR MACR ACSxCR
/CSx /WEx /OEx D[15:0] A[23:0]
60
5.1.2 Registers
Register Name MMU Instruction/Data Register Stack Segment Register Stack Segment LSB Register Stack Segment MSB Register Data Segment Register Data Segment LSB Register Data Segment MSB Register Segment Size Register Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register Memory Timing Control Register Memory Alternate Control Register Advanced /CS0 Control Register Advanced /CS1 Control Register Advanced /CS2 Control Register RAM Segment Register Write-Protect Control Register Write-Protect x Register Write-Protect Segment A Register Write-Protect Segment A Low Register Write-Protect Segment A High Register Write-Protect Segment B Register Write-Protect Segment B Low Register Write-Protect Segment B High Register Stack Limit Control Register Stack Low Limit Register Stack High Limit Register Mnemonic MMIDR STACKSEG STACKSEGL STACKSEGH DATSEG DATSEGL DATSEGH SEGSIZE MB0CR MB1CR MB2CR MB3CR MECR MTCR MACR ACS0CR ACS1CR ACS2CR RAMSR WPCR WPxR WPSAR WPSALR WPSAHR WPSBR WPSBLR WPSBHR STKCR STKLLR STKHLR I/O Address 0x0010 0x0011 0x001A 0x001B 0x0012 0x001E 0x001F 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001D 0x0410 0x0411 0x0412 0x0448 0x0440 0x460+x 0x0480 0x0481 0x0482 0x0484 0x0485 0x0486 0x0444 0x0445 0x0446 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W R/W W W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 00001000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx
61
5.2 Dependencies
5.2.1 I/O Pins There are three chip select pins, /CS0, /CS1, and /CS2; two read strobes, /OE0 and /OE1; and two write strobes, /WE0 and /WE1. /CS3 is available to the internal SRAM only and does not come out to a pin. There are eight dedicated data bus pins, D0 through D7. If the 16-bit mode is enabled, then PH0PH7 automatically act as the upper byte of the data bus, D8 through D15. There are 20 dedicated address pins, A0 through A19. Up to four more address pins can be enabled on PE0PE3, representing A20 through A23. Pin PE4 can be enabled as /A0 to allow byte reads and writes in 16-bit SRAM devices. 5.2.2 Clocks All memory operations are clocked by the processor clock. 5.2.3 Other Registers
Register Function
PEFR, PEALR, PEAHR Enable A20-A23 and /A0.
5.2.4 Interrupts When a write is attempted to a write-protected 64 KB or 4 KB block, a write-protection violation interrupt is generated. The interrupt request is cleared when it is handled. The write-protection violation interrupt vector is in the IIR at offset 0x090. It is always set to Priority 3. When a stack-related write is attempted to a region outside that set by the stack limit registers, a stack limit violation occurs. The interrupt request is cleared when it is handled. The stack limit violation interrupt vector is in the IIR at offset 0x1B0. It is always set to Priority 3.
62
5.3 Operation
5.3.1 Memory Management Unit (MMU) Code execution takes place in the 64 KB logical memory space, which is divided into four segments: root, data, stack, and extended (XMEM). The root segment is always mapped starting at physical address 0x000000, but the other segments can be remapped to start at any physical 4 KB block boundary. The data and stack segment mappings are set by writing to the appropriate register, as shown in Table 5-1. The DATASEG and STACKSEG registers provide backwards compatibility to the Rabbit 2000 and 3000 processors; these registers map directly to DATASEGL and STACKSEGL, but the contents of DATASEGH and STACKSEGH are set to zero.
Table 5-1. Memory Management Registers
Register DATASEG DATASEGL DATASEGH STACKSEG STACKSEGL STACKSEGH XPC LXPC Segment Data Data Data Stack Stack Stack XMEM XMEM Size 8 bits 8 bits 4 bits 8 bits 8 bits 4 bits 8 bits 12 bits Comments Maps to DATASEGL; DATASEGH set to 0x00 Maps to STACKSEGL; STACKSEGH set to 0x00 Loaded via instructions LD XPC,A and LD A,XPC Loaded via instructions: LD LXPC,HL and LD HL,LXPC
Each of these registers provides a 4 KB offset that is added to the logical address to provide a physical address as shown in Figure 5-3.
63
DATASEGH
DATASEG
DATASEGL
+
0
16-bit logical address
20-bit physical address STKSEGH
24-bit physical address
STKSEG
STKSEGL
+
0 0
XPC
LXPC 16-bit logical address
+
0
Figure 5-3. MMU Operation
5.3.2 Memory Bank Operation On startup the Rabbit 5000 checks the status of the SYSCFG pins. To provide support for external memory, both SYSCFG pins should be set low and Memory Bank 0 enabled to use /CS0, /OE0, and /WE0 in 8-bit mode with four wait states and write protection enabled. It is expected that an external flash device containing startup code is attached to those strobes. The other memory banks come up undefined and their controls should be set via the appropriate MBxCR register to a valid setting before use. If SYSCFG0 is high and SYSCFG1 is low, Memory Bank 0 is enabled to use /CS3, /OE0, and /WE0 in 16-bit mode. This allows the processor to start operation directly out of the internal SRAM. The size of the memory banks is defined in the MECR register. The default size is 256 KB (the bank selection looks at the two most significant address bits), but this value can be adjusted down to 128 KB or up to 4 MB per bank.
64
The two address bits used to select the bank can be inverted in MBxCR, which enables mapping different sections of a memory device larger than the current memory bank into memory. Figure 5-4 shows an example of this feature.
0xFFFFF 0xC0000 0xBFFFF 1MB Memory Device 0x80000 0x7FFFF 0x40000 0x3FFFF A18, A19 normal 0x00000
. . .
Memory Bank 1 0x40000 0x3FFFF Memory Bank 0 0x00000
0xFFFFF 0xC0000 0xBFFFF 1MB Memory Device 0x80000 0x7FFFF 0x40000 0x3FFFF 0x00000
. . .
A18 normal, A19 inverted Memory Bank 1 0x40000 0x3FFFF Memory Bank 0 0x00000
Figure 5-4. Mapping Different Sections of a Memory Device Larger Than the Current Memory Bank
It is possible to extend the timing of the /OE and/or /WE strobes by one half of a clock. This provides slightly longer strobes for slower memories; see the timing diagrams in Chapter 31. These options are available in MTCR. It is possible to force /CS1 to be always active in MMIDR; enabling this will cause conflicts only if a device shares a /OE or /WE strobe with another device. This option allows faster access to particular memory devices.
Chapter 5 Memory Management 65
5.3.3 Memory Modes The Rabbit 5000 supports both 8-bit and 16-bit memories on all chip selects, including the internal SRAM. It also provides support for page-mode devices. The mode for each chip select is set in MACR; 8-bit mode is the default for all chip selects. When in basic 8-bit mode, the wait states are selected in the memory bank registers, MBxCR; the options are 0, 1, 2, or 4 wait states. Note that this may put an upper bound on the processor clock speed, depending on the access time of your 8-bit memory device. When in 16-bit or page-mode (either 8- or 16-bit), the wait states are selected by both the MBxCR and the advanced chip select registers, ACSxCR. When the 16-bit mode is enabled, Parallel Port H is used for the high byte of the data, and is configured automatically for this operation, overriding any other Parallel Port H function.
Table 5-2. Memory Modes
Mode 8-bit 16-bit 8-bit Page Mode 16-bit Page Mode Byte Writes? Yes Selectable Yes Selectable Word Reads? No Yes No Yes Word Writes? No Yes No Yes Wait State Register MBxCR MBxCR ACSxCR MBxCR ACSxCR MBxCR ACSxCR Wait State Options 0, 1, 2, 4 011 011 first access, 07 page accesses 011 first access, 07 page accesses
A 16-bit memory device may or may not support byte writes, so there is an option to select between these two cases in ACSxCR. With the default option any byte writes or unaligned word writes to a 16-bit memory will be suppressed (i.e., the /WE will not be asserted). Any aligned word reads or writes are recognized internally and are combined into just one write transaction on the external bus. The other option for the 16-bit bus does not inhibit byte writes or unaligned word writes, and replicates the byte data on both halves of the data bus in these cases. In this mode the A0 and /A0 signals must be used by the memory to enable the individual bytes.
Table 5-3. A0 and /A0 Signals for Various Transaction Types
Transaction Type Word Read (prefetch only) Word Write Byte Read or Write Even Address Byte Read or Write Odd Address A0 Low Low Low High /A0 Low Low High Low
66
All of the power-saving modes in Chapter 29 can be used with the 16-bit mode. The second advanced bus mode is the Page Mode. This mode also can be enabled for any external chip select, and can be used with either 8-bit or 16-bit memories connected to these chip selects. Page-Mode memories provide for a faster access time if the requested data are in the same page as the previous data. In the Rabbit 5000 (and most memory devices) a page can be selected as either 8 or 16 bytes. Thus, if an address is identical to the previous address except in the lower four bits, the access time is assumed to be faster. These wait-state options are also controlled in the ACSxCR. In Page Mode the chip select and /OE remain active from one page access to the next, and only the three or four least-significant bits of the address change to request the new data. This obviously interferes with a number of the power-saving modes and will take precedence over them for chip select accesses, as appropriate. The power-saving modes will still apply to the other chip select and output-enable signals. The logic recognizes which /OE is being used with each chip select in the Page Mode. As mentioned previously, the ACSxCR registers each contain three fields to control the generation of wait states in the advanced bus modes. These settings are in addition to the wait-state setting in MBxCR when an advanced bus mode is enabled. When the 16-bit bus is enabled, one to seven automatic wait states for memory read bus cycles can be enabled in addition to the zero to four wait states in MBxCR. This setting is also used for the first access when the Page Mode is enabled; a second setting selects the number of wait states for all subsequent reads in the Page Mode, allowing from zero to three automatic wait states for the same-page accesses in the Page Mode. The choices available for the advanced bus wait states are sufficient to allow interfacing to a variety of standard memories for any Rabbit 5000 speed grade. When a 16-bit memory is connected to /CS0, the first few instructions must program the device to operate in 16-bit mode. This code is shown below. This code should be the first thing executed by your device. Because the processor is fetching bytes from a 16-bit memory device that is not connected to A0, only one-byte instructions can be used, and they must occur in pairs.
ORG XOR XOR LD LD SCF SCF RLA RLA LD LD SCF SCF ADC ADC ADD 0000h A A H, A H, A ; a <= 00000000 ; h <= 00000000
B, A B, A
; a <= 00000001 ; a <= 00000010 ; b <= 00000010
A, B A, B A, A
; a <= 00000101 ; a <= 00000111 ; a <= 00001110 67
ADD SCF SCF ADC ADC LD LD IOI IOI LD LD NOP NOP
A, A
; a <= 00011100
A, A, L, L,
H H A A
; a <= 00011101 ; l <= 00011101 ; two IOIs same as one
(HL), B (HL), B
; ; ; ;
MACR <= 00000010 dummy memory write (no /WE) required delay to start up the 16-bit bus
5.3.4 Separate Instruction and Data Space To make better use of the 64 KB of logical space, an option is provided to map code and data accesses in the same address space to separate devices. This is accomplished by enabling the inversion of A16 and the most-significant bit of the bank select bits for accesses in the root and data segments. Careful use of these features allows both code and data to separately use up to 64 KB of logical memory. The RAM segment register (RAMSR) provides a shortcut for updating code by accessing it as data. It provides a window that uses the instruction address decoding when read or written as data. This mapping will only occur when the RAMSR is within the root or data segments; the RAMSR will be ignored if it is mapped to the stack segment or XPC window. The Rabbit 5000 Designers Handbook provides further details on the use of the separate instruction and data space feature. 5.3.5 Memory Protection Memory blocks may be protected at three separate granularities, as shown in Table 5-4. Writes can be prevented to any memory bank by writing to MBxCR. Writes can be prevented and trapped at a resolution of 64 KB by enabling protection for that block in the appropriate WPxR register. For further control, two of those 64 KB blocks can be further subdivided into 4 KB blocks by selecting them as the write protect segments A or B. When a write is attempted to a block protected in WPxR, WPSxLR, or WPSxHR, a Priority 3 write-protect interrupt occurs. This feature is automatically enabled by writing to the block protection registers; to disable it, set all the write-protect block registers to zero.
Table 5-4. Memory Protection Options
Method Memory Bank Write-Protect Blocks Write Protect Segment A/B Block Size Registers Used
128 KB 4 MB MBxCR, MECR 64 KB 4 KB WPCR, WPxR WPSxR, WPSxLR, WPSxHR
68
5.3.6 Stack Protection The Rabbit 5000 provides stack overflow and underflow protection. Low and high logical address limits can be set in STKLLR and STKHLR; a Priority 3 stack-violation interrupt occurs when a stack-based write occurs within the 16 bytes below the upper limit or within the 16 bytes above the lower limit. Note that the writes will still occur even if they are within the 16 bytes surrounding the limits, but the interrupt can serve as a warning to the application that the stack is in danger of being over or underrun. The stack checking can be enabled or disabled by writing to STKCR.
69

MMU Instruction/Data Register Bit(s) 7 Value 0 (MMIDR) Description Internal I/O addresses are decoded using only the lower eight bits of the internal I/O address bus. This restricts internal I/O addresses to the range 0x0000 0x00FF. Internal I/O addresses are decoded using all 15 bits of the address internal I/O address bus. This option must be selected to access internal I/O addresses of 0x0100 and higher. This bit is reserved an must be written with zero. 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 Enable A16 and bank select address MSB inversion independent of instruction/data. Enable A16 and bank select address MSB inversion for data accesses only. This enables the instruction/data split. Normal /CS1 operation. Force /CS1 always active. This will not cause any conflicts as long as the memory using /CS1 does not also share an output enable or write enable with another memory. Normal operation. For a data segment access, invert bank select address MSB before MBxCR decision. Normal operation. For a data segment access, invert A16 Normal operation. For a root segment access, invert bank select address MSB before MBxCR decision. Normal operation. For a root segment access, invert A16 (Address = 0x0010)
1 6 5
Stack Segment Register Bit(s) 7:0 Value Read Write
(STACKSEG) Description
(Address = 0x0011)
The current contents of this register are reported. Eight LSBs (MSBs are set to zero by write) of physical address offset to use if SEGSIZ[7:4] Addr[15:12] < 0xE
70
Stack Segment Low Register Bit(s) 7:0 Value Read Write
(STACKSEGL) Description
(Address = 0x001A)
The current contents of this register are reported. Eight LSBs of physical address offset to use if SEGSIZ[7:4] Addr[15:12] < 0xE
Stack Segment High Register Bit(s) 7:4 3:0 Read Write Value
(STACKSEGH) Description
(Address = 0x001B)
These bits are reserved and should always be written as zero. These bits always return zeros when read. The current contents of this register are reported. Four MSBs of physical address offset to use if SEGSIZ[7:4] Addr[15:12] < 0xE
Data Segment Register Bit(s) 7:0 Value Read Write
(DATSEG) Description
(Address = 0x0012)
The current contents of this register are reported. Eight LSBs (MSBs are set to zero by write) of physical address offset to use if: SEGSIZ[3:0] Addr[15:12] < SEGSIZ[7:4]
Data Segment Low Register Bit(s) 7:0 Value
(DATSEGL) Description
(Address = 0x001E)
Eight LSBs of physical address offset to use if SEGSIZ[3:0] Addr[15:12] < SEGSIZ[7:4]
Data Segment High Register Bit(s) 7:4 3:0 Value
(DATSEGH) Description
(Address = 0x001F)
These bits are reserved and should always be written as zero. These bits always return zeros when read. Four MSBs of physical address offset to use if SEGSIZ[3:0] Addr[15:12] < SEGSIZ[7:4]
71
Segment Size Register Bit(s) 7:0 7:4 3:0 Value Read Write Write
(SEGSIZ) Description
(Address = 0x0013)
The current contents of this register are reported. Boundary value for switching from DATSEG to STACKSEG for translation. Boundary value for switching from none to DATSEG for translation.
Memory Bank x Control Register
(MB0CR) (MB1CR) (MB2CR) (MB3CR) Description
(Address = 0x0014) (Address = 0x0015) (Address = 0x0016) (Address = 0x0017)
Bit(s) 7:6
Value 00 01 10 11
Four (five for writes) wait states for accesses in this bank. Two (three for writes) wait states for accesses in this bank. One (two for writes) wait states for accesses in this bank. Zero (one for writes) wait states for accesses in this bank. Pass bank select address MSB for accesses in this bank. Invert bank select address MSB for accesses in this bank. Pass bank select address LSB for accesses in this bank. Invert bank select address LSB for accesses in this bank. /OE0 and /WE0 are active for accesses in this bank. /OE1 and /WE1 are active for accesses in this bank. /OE0 only is active for accesses in this bank (i.e., read-only). Transactions are normal in every other way. /OE1 only is active for accesses in this bank (i.e., read-only). Transactions are normal in every other way. /CS0 is active for accesses in this bank. /CS1 is active for accesses in this bank. /CS2 is active for accesses in this bank. /CS3 (internal memory) is active for accesses in this bank. When standalone operation is selected (by strapping a pin), this bit combination is forced for MB0CR only.
0 1
0 1
3:2
00 01 10 11
1:0
00 01 10 11
72
MMU Expanded Code Register Bit(s) 7:5 Value 000 001 010 011 100 101 110 111 4:3 2:0 000 001 010 011 100 101 110 111
(MECR) Description
(Address = 0x0018)
Bank select address is A[19:18]. Bank select address is A[20:19]. Bank select address is A[21:20]. Bank select address is A[22:21]. Bank select address is A[23:22]. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. Bank select address is A[18:17]. These bits are reserved and should be written with zeros. Read returns zeros. Normal operation. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. For an XPC access, use MB0CR independent of bank select address. For an XPC access, use MB1CR independent of bank select address. For an XPC access, use MB2CR independent of bank select address. For an XPC access, use MB3CR independent of bank select address.
Memory Timing Control Register Bit(s) 7:4 3 0 1 2 0 1 1 0 1 0 0 1 Value
(MTCR) Description
(Address = 0x0019)
These bits are reserved and should be written with zeros. Normal timing for /OE1 (rising edge to rising edge, one clock minimum). Extended timing for /OE1 (one-half clock earlier than normal). Normal timing for /OE0 (rising edge to rising edge, one clock minimum). Extended timing for /OE0 (one-half clock earlier than normal). Normal timing for /WE1 (rising edge to falling edge, one and one-half clocks minimum). Extended timing for /WE1 (falling edge to falling edge, two clocks minimum). Normal timing for /WE0 (rising edge to falling edge, one and one-half clocks minimum). Extended timing for /WE0 (falling edge to falling edge, two clocks minimum).
73
Memory Alternate Control Register Bit(s) 7 Value 0 1 6 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(MACR) Description
(Address = 0x001D)
Normal 8-bit operation for /CS3. Use MBxCR for wait states. This bit is used only when external memory is present. Normal 16-bit operation for /CS3. Use MBxCR for wait states. When standalone operation is selected (by strapping a pin), this bit is forced high. This bit is reserved and must not be used. Normal 8-bit operation for /CS2. Page-Mode 8-bit operation for /CS2. Normal 16-bit operation for /CS2. Page-Mode 16-bit operation for /CS2. Normal 8-bit operation for /CS1. Page-Mode 8-bit operation for /CS1. Normal 16-bit operation for /CS1. Page-Mode 16-bit operation for /CS1. Normal 8-bit operation for /CS0. Page-Mode 8-bit operation for /CS0. Normal 16-bit operation for /CS0. Page-Mode 16-bit operation for /CS0.
74
Advanced Chip Select x Control Register
(ACS0CR) (ACS1CR) (ACS2CR) Description
(Address = 0x0410) (Address = 0x0411) (Address = 0x0412)
Bit(s) 7:5
Value 000 001 010 011 100 101 110 111
Zero extra wait states for reads, writes, or first Page-Mode access. One extra wait state for reads, writes, or first Page-Mode read access. Two extra wait states for reads, writes, or first Page-Mode access. Three extra wait states for reads, writes, or first Page-Mode read access. Four extra wait states for reads, writes, or first Page-Mode read access. Five extra wait states for reads, writes, or first Page-Mode read access. Six extra wait state for reads, writes, or first Page-Mode read access. Seven extra wait state for reads, writes, or first Page-Mode read access. Zero extra wait states for subsequent Page-Mode accesses. One extra wait state for subsequent Page-Mode accesses. Two extra wait states for subsequent Page-Mode accesses. Three extra wait states for subsequent Page-Mode accesses. This bit is reserved and should not be used.
4:3
00 01 10 11
2 1 0 1 0 0 1
Page size 16 bytes. Page size 8 bytes. Disable byte writes on 16-bit bus. Enable byte writes on 16-bit bus.
RAM Segment Register Bit(s) 7:2 1:0 00 01 10 11 Value
(RAMSR) Description
(Address = 0x0448)
Compare value for RAM segment limit checking. Disable RAM segment limit checking. Select data-type MMU translation if PC[15:10] is equal to RAMSR[7:2]. Select data-type MMU translation if PC[15:11] is equal to RAMSR[7:3]. Select data-type MMU translation if PC[15:12] is equal to RAMSR[7:4].
75
Write Protection Control Register Bit(s) 7:1 0 0 1 Value
(WPCR) Description
(Address = 0x0440)
These bits are reserved and should be written with zeros. Write protection in User Mode only. Write protection in System and User modes.
76
Write-Protect x Register
(WP0R) (WP1R) (WP2R) (WP3R) (WP4R) (WP5R) (WP6R) (WP7R) (WP8R) (WP9R) (WP10R) (WP11R) (WP12R) (WP13R) (WP14R) (WP15R) (WP16R) (WP17R) (WP18R) (WP19R) (WP20R) (WP21R) (WP22R) (WP23R) (WP24R) (WP25R) (WP26R) (WP27R) (WP28R) (WP29R) (WP30R) (WP31R)
(Address = 0x0460) (Address = 0x0461) (Address = 0x0462) (Address = 0x0463) (Address = 0x0464) (Address = 0x0465) (Address = 0x0466) (Address = 0x0467) (Address = 0x0468) (Address = 0x0469) (Address = 0x046A) (Address = 0x046B) (Address = 0x046C) (Address = 0x046D) (Address = 0x046E) (Address = 0x046F) (Address = 0x0470) (Address = 0x0471) (Address = 0x0472) (Address = 0x0473) (Address = 0x0474) (Address = 0x0475) (Address = 0x0476) (Address = 0x0477) (Address = 0x0478) (Address = 0x0479) (Address = 0x047A) (Address = 0x047B) (Address = 0x047C) (Address = 0x047D) (Address = 0x047E) (Address = 0x047F)
Bit(s) 7:0
Value 0
Description Disable write protection for the corresponding 64 KB segment. Enable write protection for the corresponding 64 KB segment. The eight-bit address of the segment to be write-protected is formed using bits [4:0] of the WPxR register address concatenated with the bit address of the corresponding bit in the register.
77
Write-Protect Segment x Register Bit(s) 7:0 Value
(WPSAR) (WPSBR) Description
(Address = 0x0480) (Address = 0x0484)
When these eight bits [23:16] match bits of the physical address, write-protect that 64 KB range in 4 KB increments using WPSxLR and WPSxHR.
Write-Protect Segment x Low Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(WPSALR) (WPSBLR) Description
Disable 4 KB write protect for relative address 0x70000x7FFF in WP Segment x. Enable 4 KB write protect for relative address 0x70000x7FFF in WP Segment x. Disable 4 KB write protect for relative address 0x60000x6FFF in WP Segment x. Enable 4 KB write protect for relative address 0x60000x6FFF in WP Segment x. Disable 4 KB write protect for relative address 0x50000x5FFF in WP Segment x. Enable 4 KB write protect for relative address 0x50000x5FFF in WP Segment x. Disable 4 KB write protect for relative address 0x40000x4FFF in WP Segment x. Enable 4 KB write protect for relative address 0x40000x4FFF in WP Segment x. Disable 4 KB write protect for relative address 0x30000x3FFF in WP Segment x. Enable 4 KB write protect for relative address 0x30000x3FFF in WP Segment x. Disable 4 KB write protect for relative address 0x20000x2FFF in WP Segment x. Enable 4 KB write protect for relative address 0x20000x2FFF in WP Segment x. Disable 4 KB write protect for relative address 0x10000x1FFF in WP Segment x. Enable 4 KB write protect for relative address 0x10000x1FFF in WP Segment x. Disable 4 KB write protect for relative address 0x00000x0FFF in WP Segment x. Enable 4 KB write protect for relative address 0x00000x0FFF in WP Segment x.
78
Write-Protect Segment x High Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(WPSAHR) (WPSBHR) Description
Disable 4 KB write protect for relative address 0xF0000xFFFF in WP Segment x. Enable 4 KB write protect for relative address 0xF0000xFFFF in WP Segment x. Disable 4 KB write protect for relative address 0xE0000xEFFF in WP Segment x. Enable 4 KB write protect for relative address 0xE0000xEFFF in WP Segment x. Disable 4 KB write protect for relative address 0xD0000xDFFF in WP Segment x. Enable 4 KB write protect for relative address 0xD0000xDFFF in WP Segment x. Disable 4 KB write protect for relative address 0xC0000xCFFF in WP Segment x. Enable 4 KB write protect for relative address 0xC0000xCFFF in WP Segment x. Disable 4 KB write protect for relative address 0xB0000xBFFF in WP Segment x. Enable 4 KB write protect for relative address 0xB0000xBFFF in WP Segment x. Disable 4 KB write protect for relative address 0xA0000xAFFF in WP Segment x. Enable 4 KB write protect for relative address 0xA0000xAFFF in WP Segment x. Disable 4 KB write protect for relative address 0x90000x9FFF in WP Segment x. Enable 4 KB write protect for relative address 0x90000x9FFF in WP Segment x. Disable 4 KB write protect for relative address 0x80000x8FFF in WP Segment x. Enable 4 KB write protect for relative address 0x80000x8FFF in WP Segment x.
Stack Limit Control Register Bit(s) 7:1 0 0 1 Value
(STKCR) Description
(Address = 0x0444)
These bits are reserved and should be written with zeros. Disable stack-limit checking. Enable stack-limit checking.
Stack Low Limit Register Bit(s) 7:0 Value
(STKLLR) Description
(Address = 0x0445)
Lower limit for stack-limit checking. If a stack operation or stack-relative memory access is attempted at an address less than {STKLLR, 0x10}, a stacklimit violation interrupt is generated.
79
Stack High Limit Register Bit(s) 7:0 Value
(STKHLR) Description
(Address = 0x0446)
Upper limit for stack-limit checking. If a stack operation or stack-relative memory access is attempted at an address greater than {STKHLR, 0xEF}, a stack-limit violation interrupt is generated.
80
6. INTERRUPTS
6.1 Overview
The Rabbit 5000 can operate at one of four priority levels, 03, with Priority 0 being the expected standard operating level. The current priority and up to three previous priority levels are kept in the processors 8-bit IP register, where bits 01 contain the current priority. Every time an interrupt is handled or an IPSET instruction occurs, the value in the register is shifted left by two bits, and the new priority placed in bits 01. When an IPRES or IRET instruction occurs, the value in IP is shifted right by two bits (bits 01 are shifted into bits 67). On reset, the processor starts at Priority 3. Most interrupts can be set to be Priority 13. A pending interrupt will be handled only if its interrupt priority is greater than the current processor priority. This means that even a Priority 3 interrupt can be blocked if the processor is currently at Priority 3. The System Mode Violation, Stack Limit Violation, Write Protection Violation, secondary watchdog, and breakpoint interrupts are always enabled at Priority 3. In addition, when the System/ User Mode is enabled and the processor is in the User Mode, the processor will not actually enter Priority 3; any attempt to enter Priority 3 will actually be requested as Priority 2. When an interrupt is handled, a call is executed to a fixed location in the interrupt vector tables. This operation requires 11 clocks, the minimum interrupt latency for the Rabbit 5000. There are two vector tables, the internal and the external interrupt vector tables, that can be located anywhere in logical memory by setting the processors IIR and EIR registers. The IIR and EIR registers hold the upper byte of each tables address. For example, if IIR is loaded with 0xC4, then the internal interrupt vector table will start at the logical memory address 0xC400. The internal interrupt vector table occupies 512 bytes, and the external interrupt vector table is 256 bytes in size. Since the RST and SYSCALL vectors use all eight bits of the IIR for addressing, the lowermost bit of IIR should always be set to zero so to keep some vectors from inadvertently overlapping. Each interrupts vector begins on a 16-byte boundary inside the vector tables. It may be possible to fit a small routine into that space, but it is typical to place a call to a separate routine in that location. Some Rabbit 5000 instructions are chained atomic, which means that an interrupt cannot occur between that instruction and the following instruction. These instructions are useful for doing things like exiting interrupt handlers properly or updating semaphores.
Chapter 6 Interrupts 81
6.2 Operation
To ensure proper operation, all interrupt handler routines should be written according to the following guidelines. Push all registers to be used by the routine onto the stack before use, and pop them off the stack before returning from the ISR. Keep the ISR as short and fast as possible. The use of assembly code is strongly recommended. If the ISR will run for some time, lower the interrupt priority as soon as possible within the ISR to allow other interrupts to occur. A number of special rules apply to interrupts when operating in the system/user mode; please see the appropriate chapter for more details.
6.3 Interrupt Tables

Table 6-1 shows the structure of the internal interrupt vector table. The first column is the vector address offset within the table. The second column shows the vectors in the first 256 bytes of the table, and the third column shows the vectors in the second 256 bytes.
Table 6-1. Internal Interrupt Vector Table Structure
Offset 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 0x0000 + Offset Periodic Interrupt Secondary Watchdog RST 10 RST 18 RST20 RST 28 Syscall instruction RST 38 Slave Port Write Protect Violation Timer A Timer B Serial Port A Serial Port B Serial Port C Serial Port D PWM Sys/User Mode Violation Quadrature Decoder Input Capture Stack Limit Violation Serial Port E Serial Port F Network Port B/C Timer C 0x0100 + Offset
82
Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector falls on a 16-byte boundary inside the table.
Table 6-2. External Interrupt Vector Table Structure
Offset 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 0x0000+ External Interrupt 0 External Interrupt 1 Breakpoints DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 DMA Channel 6 DMA Channel 7
There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3. Interrupts marked as cleared automatically have their requests cleared when the interrupt is first handled.
Chapter 6 Interrupts
83
Table 6-3. Interrupt Priorities

Priority Highest Interrupt Source Breakpoint System Mode Violation Stack Limit Violation Write Protection Violation Secondary Watchdog External Interrupt 1 External Interrupt 0 Periodic Interrupt Quadrature Decoder Timer B Timer A Input Capture PWM Timer C Slave Port DMA 7 DMA 6 DMA 5 DMA 4 DMA 3 DMA 2 DMA 1 DMA 0 Network Port B/C Serial Port E Serial Port F Serial Port A Serial Port B Serial Port C Lowest Serial Port D Action Required to Clear the Interrupt Read the status from BDCR. Cleared automatically. Cleared automatically. Cleared automatically. Restart secondary watchdog by writing to WDTCR. Cleared automatically. Cleared automatically. Read the status from GCSR. Read the status from QDCSR. Read the status from TBCSR. Read the status from TACSR. Read the status from ICCSR. Write any PWM register. Read the status from TCCSR. Rd: Read from SPD0R, SPD1R or SPD2R. Wr: Write to SPD0R, SPD1R, SPD2R or dummy write to SPSR. Cleared automatically. Cleared automatically. Cleared automatically. Cleared automatically. Cleared automatically. Cleared automatically. Cleared automatically. Cleared automatically. Read interrupt status from NBCSR or NCCSR. Rx: Read from SEDR or SEAR. Tx: Write to SEDR, SEAR, SELR or dummy write to SESR. Rx: Read from SFDR or SFAR. Tx: Write to SFDR, SFAR, SFLR or dummy write to SFSR. Rx: Read from SADR or SAAR. Tx: Write to SADR, SAAR, SALR or dummy write to SASR. Rx: Read from SBDR or SBAR. Tx: Write to SBDR, SBAR, SBLR or dummy write to SBSR. Rx: Read from SCDR or SCAR. Tx: Write to SCDR, SCAR, SCLR or dummy write to SCSR. Rx: Read from SDDR or SDAR. Tx: Write to SDDR, SDAR, SDLR or dummy write to SDSR.
84
7. EXTERNAL INTERRUPTS
7.1 Overview
The Rabbit 5000 has six external interrupts available, and they share two interrupt vectors. In the case of multiple interrupts sharing an interrupt vector, the data register corresponding to the parallel port(s) being used can be read. Each interrupt vector can be set to trigger on a rising edge, a falling edge, or either edge. The signal on the external interrupt pin must be present for at least three peripheral clock cycles to be detected. In addition, the Rabbit 5000 has a minimum latency of 11 clocks to respond to an interrupt, so the minimum external interrupt response time is three peripheral clock cycles plus 11 processor clock cycles.
7.2 Block Diagram

External Interrupts PD0 PE0 PE4 Enable and Edge Detection Enable and Edge Detection Enable and Edge Detection I0CR Enable and Edge Detection Enable and Edge Detection Enable and Edge Detection I1CR Interrupt 1 Generation I1CR External Interrupt 1 Request Interupt 0 Generation I0CR External Interrupt 0 Request
PD1 PE1 PE5
Chapter 7 External Interrupts
85
7.2.1 Registers
Register Name Interrupt 0 Control Register Interrupt 1 Control Register Mnemonic I0CR I1CR I/O Address 0x0098 0x0099 R/W R/W R/W Reset xx000000 xx000000
7.3 Dependencies
7.3.1 I/O Pins The external interrupts can be enabled on pins PD0, PD1, PE0, PE1, PE4, and PE5. Each pin is associated with a particular interrupt vector as shown in Table 7-1 below.
Table 7-1. Rabbit 5000 Interrupt Vectors
Vector Interrupt 0 Interrupt 1 Register I0CR I1CR Pins PD0, PE0, PE4 PD1, PE1, PE5
7.3.2 Clocks The external interrupts are controlled by the peripheral clock. A pulse must be present for at least three peripheral clock cycles to trigger an interrupt. 7.3.3 Interrupts An external interrupt is generated whenever the selected edge occurs on an enabled pin. The interrupt request is automatically cleared when the interrupt is handled. The external interrupt vectors are in the EIR at offsets 0x000 and 0x010. They can be set as Priority 1, 2, or 3 in the appropriate IxCR.
7.4 Operation
The following steps must be taken to enable the external interrupts. 1. Write the vector(s) to the interrupt service routine to the external interrupt table. 2. Configure IxCR to select which pins are enabled for external interrupts, what edges are detected on each pin, and the interrupt priority. 3. When an interrupt occurs, read PDDR and/or PEDR to determine which pin has a signal if more than one pin is enabled for a given external interrupt.
86
7.4.1 Example ISR A sample interrupt handler is shown below.

extInt_isr:: ; respond to external interrupt here ; interrupt is automatically cleared by interrupt acknowledge ipres ret
Chapter 7 External Interrupts
87

Interrupt x Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11 (I0CR) (I1CR) Description Parallel Port D low nibble interrupt disabled. Parallel Port D low nibble interrupt on falling edge. Parallel Port D low nibble interrupt on rising edge. Parallel Port D low nibble interrupt on both edges. Parallel Port E high nibble interrupt disabled. Parallel Port E high nibble interrupt on falling edge. Parallel Port E high nibble interrupt on rising edge. Parallel Port E high nibble interrupt on both edges. Parallel Port E low nibble interrupt disabled. Parallel Port E low nibble interrupt on falling edge. Parallel Port E low nibble interrupt on rising edge. Parallel Port E low nibble interrupt on both edges. This external interrupt is disabled. This external interrupt uses Interrupt Priority 1. This external interrupt uses Interrupt Priority 2. This external interrupt uses Interrupt Priority 3. (Address = 0x0098) (Address = 0x0099)
88
8. PARALLEL PORT A
8.1 Overview
Parallel Port A is a byte-wide port that can be used as an input or an output port. Parallel Port A is also used as the data bus for the slave port and external I/O bus. The Slave Port Control Register (SPCR) is used to configure how Parallel Port A is used. Parallel Port A is an input at startup or reset. If the SMODE pins have selected the slave port bootstrap mode, Parallel Port A will be the slave port data bus until disabled by the processor. Parallel Port A can also be used as an external I/O data bus to isolate external I/O from the main data bus.
Table 8-1. Parallel Port A Pin Alternate Output Functions
Pin Name PA[7:0] Slave Port Data Bus SD[7:0] External I/O Bus ID[7:0]
8.1.1 Block Diagram

Parallel Port A SPCR Data PADR Slave Data 7:0 7:0
External I/O Data
7:0
8.1.2 Registers
Register Name Port A Data Register
Chapter 8 Parallel Port A
Mnemonic PADR
I/O Address 0x0030
R/W R/W
Reset xxxxxxxx
89
8.2 Dependencies
8.2.1 I/O Pins Parallel Port A uses pins PA0 through PA7. These pins can be used as follows. General-purpose 8-bit data input (write 0x080 to SPCR) General-purpose 8-bit data output (write 0x084 to SPCR) Slave port data bus (write 0x088 to SPCR) External I/O data bus (write 0x08C to SPCR) All Parallel Port A bits are inputs at startup or reset. See the associated peripheral chapters for details on how they use Parallel Port A. 8.2.2 Clocks Any outputs on Parallel Port A are clocked by the peripheral clock. 8.2.3 Other Registers
Register SPCR Function Used to set up Parallel Port A.
8.2.4 Interrupts There are no interrupts associated with Parallel Port A, except when the slave port is being used.
8.3 Operation
The following steps explain how to set up Parallel Port A. 1. Select the desired mode using SPCR. 2. If the slave port or external I/O bus is selected, refer to the chapters for those peripherals for further setup. Once Parallel Port A is set up, data can be read or written by accessing PADR. Note that Parallel Port A is not available for general-purpose I/O while the slave port or the external I/O bus is selected. Selecting these options for Parallel Port A affects Parallel Port B because Parallel Port B is then used for address and control signals.
90

Parallel Port A Data Register Bit(s) 7:0 Value Read Write (PADR) Description The current state of Parallel Port A pins PA7PA0 is reported. The Parallel Port A buffer is written with this value for transfer to the Parallel Port A output register on the next rising edge of the peripheral clock. (Address = 0x0030)
Slave Port Control Register Bit(s) 7 Value 0 1 6:5 read write 4:2 000 001 010 011 100 101 110 111 1:0 00 01 10 11
(SPCR) Description
(Address = 0x0024)
Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. These bits report the state of the SMODE pins. These bits are ignored and should be written with zero. Disable the slave port. Parallel Port A is a byte-wide input port. Disable the slave port. Parallel Port A is a byte-wide output port. Enable the slave port, with /SCS from Parallel Port E bit 7. Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:2] is used for the address bus. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. Enable the slave port, with /SCS from Parallel Port B bit 6. Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3.
Chapter 8 Parallel Port A
91
92
9. PARALLEL PORT B
9.1 Overview
Parallel Port B is a byte-wide port with each bit programmable for direction. The Parallel Port B pins are also used to access other peripherals on the chipthe slave port, the auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B. The Slave Port Control Register (SPCR) is used to configure how Parallel Port B is used when selecting the slave port or the external I/O bus modes. When the slave port is enabled, either under program control or during parallel bootstrap, Parallel Port B pins carry the Slave Attention output signal, and the Slave Read strobe, Slave Write strobe, and Slave Address inputs. The Slave Chip Select can also be programmed to come from a Parallel Port B pin. When the external I/O bus option is enabled, either six or eight pins carry the external I/O address signals selected in SPCR. Two pins are used for the clocks for Serial Ports A and B when they are configured for the clocked serial mode. These two inputs can be used as clock outputs for these ports if selected in the respective serial port control registers. Note that the clocked serial output clock selection overrides all other programming for the two relevant Parallel Port B pins.
Table 9-1. Parallel Port B Pin Alternate Output Functions
Pin Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Slave Port /SLVATTN /SCS SA1 SA0 /SRD /SWR Serial Ports AD SCLKA SCLKB External I/O Bus IA5 IA4 IA3 IA2 IA1 IA0 IA7 IA6
Chapter 9 Parallel Port B
93
9.1.1 Block Diagram

Parallel Port B SPCR PBDDR SACR SBCR Data PBDR SA1, SA0, /SLAVATTN /SCS, /SRD, /SWR External I/O Address Serial Ports A & B Clocks 7:2 7:2, 7:0 1:0 7:0
9.1.2 Registers
Register Name Port B Data Register Port B Data Direction Register Mnemonic PBDR PBDDR I/O Address 0x0040 0x0047 R/W R/W R/W Reset 00xxxxxx 11000000
9.2 Dependencies
9.2.1 I/O Pins Parallel Port B uses pins PB0 through PB7. These pins can be used individually as data inputs or outputs; as the address bits for the external I/O bus; as control signals for the slave port; or as clocks for Serial Ports A and B. On startup, bits 6 and 7 are outputs set low for backwards compatibility with the Rabbit 2000. All other pins are inputs. Note that when the external I/O bus or slave port is enabled in SPCR, the Parallel Port B pins associated with those peripherals perform those actions, no matter what the settings are in PBDR or PBDDR. See the associated peripheral chapters for details on how they use Parallel Port B. 9.2.2 Clocks All outputs on Parallel Port B are clocked by the peripheral clock (perclk). 9.2.3 Other Registers
Register SPCR Function Sets the Parallel Port B function for some pins if the slave port or external I/O bus is enabled.
94
9.2.4 Interrupts There are no interrupts associated with Parallel Port B, except when the slave port is being used.
9.3 Operation
The following steps must be taken before using Parallel Port B. 1. Select the desired input/output direction for each pin via PBDDR. Note that this setting is superseded for some pins if the slave port or external I/O bus is enabled in SPCR or if the clocked serial mode is enabled for Serial Ports A or B. 2. If the slave port or the external I/O bus is selected, refer to the chapters for those peripherals for further setup information. Once the port is set up, data can be read or written by accessing PBDR. The value in PBDR of an output pin will reflect its current output value, but any value written to an input pin will not appear on that pin until that pin becomes an output.

Parallel Port B Data Register Bit(s) 7:0 Value Read Write (PBDR) Description The current state of Parallel Port B pins PB7PB0 is reported. The Parallel Port B buffer is written with this value for transfer to the Parallel Port B output register on the next rising edge of the peripheral clock. (Address = 0x0040)
Parallel Port B Data Direction Register Bit(s) 7:0 Value 0 1
(PBDDR) Description
(Address = 0x0047)
The corresponding port bit is an input. The corresponding port bit is an output.
Chapter 9 Parallel Port B
95
Slave Port Control Register Bit(s) 7 Value 0 1 6:5 Read Write 4:2 000 001 010 011 100 101 110 111 1:0 00 01 10 11
(SPCR) Description
(Address = 0x0024)
96
10. PARALLEL PORT C

10.1 Overview
Parallel Port C is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port C Data Register (PCDR). All the Parallel Port C pins have alternate output functions, and most of them can be used as inputs to various on-chip peripherals.
Table 10-1. Parallel Port C Pin Alternate Output Functions
Pin Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Alt Out 0 TXA TXA TXB TXB TXC TXC TXD TXD Alt Out 1 I7 I6 I5 I4 I3 I2 I1 I0 Alt Out 2 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 Alt Out 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF
Table 10-2. Parallel Port C Pin Alternate Input Functions

Pin Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Chapter 10 Parallel Port C
Input Capture
Serial Ports AD RXA RXB RXC RXD
Serial Ports EF RXE RCLKE TCLKE RXF RCLKF TCLKF

97
After reset, the default condition for Parallel Port C is four outputs (the even-numbered bits) and four inputs (the odd-numbered bits). For compatibility with the Rabbit 2000 and the Rabbit 3000 microprocessors, these outputs are driven with a logic zero (low) on PC6 and a logic one (high) on PC4, PC2, and PC0. When PCDR is read, the value of the voltage on the pin is returned. If the pin is an output, the value it is set to is returned. 10.1.1 Block Diagram
Parallel Port C PCFR PCALR PCAHR PCDDR PCDCR Data PCDR Serial Ports AF Tx, Rx, Clocks External I/O Strobes PWM Output Timer C Output Input Capture 7:0 7:0 7:4 3:0 7, 5, 3, 1 7:0
10.1.2 Registers
Register Name Port C Data Register Port C Data Direction Register Port C Alternate Low Register Port C Alternate High Register Port C Drive Control Register Port C Function Register Mnemonic PCDR PCDDR PCALR PCAHR PCDCR PCFR I/O Address 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 R/W R/W R/W R/W R/W R/W R/W Reset 00010101 01010101 00000000 00000000 00000000 00000000
98
10.2 Dependencies
10.2.1 I/O Pins Parallel Port C uses pins PC0 through PC7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial ports AF; as clocks for Serial Ports CF; as external I/O strobes; or as outputs for the PWM and Timer C peripherals. The input capture peripheral can also watch pins PC7, PC5, PC3, and PC1. On startup, PC4, PC2, and PC0 are outputs set high, PC6 is set low, and the other pins are inputs for compatibility with the Rabbit 3000. The individual pins can be set to be open-drain via PCDCR. See the associated peripheral chapters for details on how they use Parallel Port C. 10.2.2 Clocks All outputs on Parallel Port C are clocked by the peripheral clock. 10.2.3 Other Registers
Register SACR, SBCR, SCCR, SDCR, SECR, SFCR ICS1R, ICS2R Function Select a Parallel Port C pin as serial data (and optional clock) input. Select a Parallel Port C pin as a start/stop condition for Input Capture input.
10.2.4 Interrupts There are no interrupts associated with Parallel Port C.
10.3 Operation
The following steps must be taken before using Parallel Port C. 1. Select the desired input/output direction for each pin via PCDDR. 2. Select driven or open-drain functionality for outputs via PCDCR. 3. If an alternate peripheral output function is desired for a pin, select it via PCALR or PCAHR and then enable it via PCFR. Refer to the appropriate peripheral chapter for further use of that pin. Once the port is set up, data can be read or written by accessing PCDR. The value in PCDR of an output pin will reflect its current output value, but any value written to an input pin will not appear on that pin until that pin becomes an output.
99

Parallel Port C Data Register Bit(s) 7:0 Value Read Write (PCDR) Description The current state of Parallel Port C pins PC7PC0 is reported. The Parallel Port C buffer is written with this value for transfer to the Parallel Port C output register on the next rising edge of the peripheral clock. (Address = 0x0050)
Parallel Port C Data Direction Register Bit(s) 7:0 Value 0 1
(PCDDR) Description
(Address = 0x0051)
Parallel Port C Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PCALR) Description
(Address = 0x0052)
Parallel Port C bit 3 alternate output 0 (TXC). Parallel Port C bit 3 alternate output 1 (I3). Parallel Port C bit 3 alternate output 2 (TIMER C3). Parallel Port C bit 3 alternate output 3 (SCLKD). Parallel Port C bit 2 alternate output 0 (TXC). Parallel Port C bit 2 alternate output 1 (I2). Parallel Port C bit 2 alternate output 2 (TIMER C2). Parallel Port C bit 2 alternate output 3 (TXF). Parallel Port C bit 1 alternate output 0 (TXD). Parallel Port C bit 1 alternate output 1 (I1). Parallel Port C bit 1 alternate output 2 (TIMER C1). Parallel Port C bit 1 alternate output 3 (RCLKF). Parallel Port C bit 0 alternate output 0 (TXD). Parallel Port C bit 0 alternate output 1 (I0). Parallel Port C bit 0 alternate output 2 (TIMER C0). Parallel Port C bit 0 alternate output 3 (TCLKF).
100
Parallel Port C Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PCAHR) Description
(Address = 0x0053)
Parallel Port C bit 7 alternate output 0 (TXA). Parallel Port C bit 7 alternate output 1 (I7). Parallel Port C bit 7 alternate output 2 (PWM3). Parallel Port C bit 7 alternate output 3 (SCLKC). Parallel Port C bit 6 alternate output 0 (TXA). Parallel Port C bit 6 alternate output 1 (I6). Parallel Port C bit 6 alternate output 2 (PWM2). Parallel Port C bit 6 alternate output 3 (TXE). Parallel Port C bit 5 alternate output 0 (TXB). Parallel Port C bit 5 alternate output 1 (I5). Parallel Port C bit 5 alternate output 2 (PWM1). Parallel Port C bit 5 alternate output 3 (RCLKE). Parallel Port C bit 4 alternate output 0 (TXB). Parallel Port C bit 4 alternate output 1 (I4). Parallel Port C bit 4 alternate output 2 (PWM0). Parallel Port C bit 4 alternate output 3 (TCLKE).
Parallel Port C Drive Control Register Bit(s) 7:0 Value 0 1
(PCDCR) Description
(Address = 0x0054)
The corresponding port bit, as an output, is driven high and low. The corresponding port bit, as an output, is open-drain.
Parallel Port C Function Register Bit(s) 7:0 Value 0 1
(PCFR) Description
(Address = 0x0055)
The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 10-1.
101
Serial Port x Control Register
(SACR) (SBCR) (SCCR) (SDCR) Description
(Address = 0x00C4) (Address = 0x00D4) (Address = 0x00E4) (Address = 0x00F4)
Bit(s) 7:6
Value 00 01 10 11
No operation. These bits are ignored in the asynchronous mode. In the clocked serial mode, start a byte-receive operation. In the clocked serial mode, start a byte-transmit operation. In the clocked serial mode, start a byte-transmit operation and a byte-receive operation simultaneously. Parallel Port C is used for input. Parallel Port D is used for input. Parallel Port E is used for input. Disable the receiver input. Asynchronous mode with 8 bits per character. Asynchronous mode with 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data. Clocked serial mode with external clock. Clocked serial mode with internal clock. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3.
5:4
00 01 10 11
3:2
00 01 10 11
1:0
00 01 10 11
102
Input Capture Source x Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(ICS1R) (ICS2R) Description
(Address = 0x0059) (Address = 0x005D)
Parallel Port C used for Start condition input. Parallel Port D used for Start condition input. Parallel Port E used for Start condition input. This bit combination is reserved and should not be used. Use port bit 1 for Start condition input. Use port bit 3 for Start condition input. Use port bit 5 for Start condition input. Use port bit 7 for Start condition input. Parallel Port C used for Stop condition input. Parallel Port D used for Stop condition input. Parallel Port E used for Stop condition input. This bit combination is reserved and should not be used. Use port bit 1 for Stop condition input. Use port bit 3 for Stop condition input. Use port bit 5 for Stop condition input. Use port bit 7 for Stop condition input.
103
104
11. PARALLEL PORT D

11.1 Overview
Parallel Port D is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port D Data Register (PDDR). All of the Parallel Port D pins have alternate output functions, and all of them can be used as inputs to various on-chip peripherals. When used as outputs, the Parallel Port D bits are buffered, with the data written to PDDR transferred to the output pins on a selected timing edge. Either the peripheral clock or the outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing. Each bit can either be programmed as open-drain or driven high and low. Because of the buffered nature of Parallel Port D, a read-modify-write type of operation can lead to old data being written to PDDR. To alleviate this potential problem, each bit of the port can be written individually using a separate address for each bit.
Table 11-1. Parallel Port D Pin Alternate Output Functions
Pin Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Alt Out 0 IA7 TXA IA6 TXB IA7 SCLKC IA6 SCLKD Alt Out 1 I7 I6 I5 I4 I3 I2 I1 I0 Alt Out 2 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 Alt Out 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF
Chapter 11 Parallel Port D
105
Table 11-2. Parallel Port D Pin Alternate Input Functions

Pin Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input Capture Serial Ports AD RXA RXB RXC SCLKC RXD SCLKD Serial Ports EF RXE RCLKE TCLKE RXF RCLKF TCLKF DMA DREQ1 DREQ0 External Interrupts INT1 INT0 Quad Decode QRD2A QRD2B QRD1A QRD1B
106
11.1.1 Block Diagram

Parallel Port D PDFR PDALR PDAHR PDDDR PDDCR Data PDDR PDBxR Serial Ports AF Tx, Rx, Clocks External I/O Strobes External I/O Address 7:6 PWM Output Timer C Output External Interrupts Slave Port /CS DMA Request Quadrature Decoder Input Capture perclk Timer A1 Timer B1 Timer B2 PDCR 7:0 7:0 3:0 7:4 3:0 5, 4, 1, 0 7 7, 6, 3, 2 3:0 7, 5, 3, 1 7:0
107
11.1.2 Registers
Register Name Port D Data Register Port D Alternate Low Register Port D Alternate High Register Port D Control Register Port D Function Register Port D Drive Control Register Port D Data Direction Register Port D Bit 0 Register Port D Bit 1 Register Port D Bit 2 Register Port D Bit 3 Register Port D Bit 4 Register Port D Bit 5 Register Port D Bit 6 Register Port D Bit 7 Register Mnemonic PDDR PDALR PDAHR PDCR PDFR PDDCR PDDDR PDB0R PDB1R PDB2R PDB3R PDB4R PDB5R PDB6R PDB7R I/O Address 0x0060 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W Reset xxxxxxxx 00000000 00000000 xx00xx00 xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
108
11.2 Dependencies
11.2.1 I/O Pins Parallel Port D uses pins PD0 through PD7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial Ports A, B, E, and F; as clocks for Serial Ports CF; as external I/O strobes; or as outputs for the PWM and Timer C peripherals. The input capture peripheral can also watch pins PD7, PD5, PD3, and PD1. All pins are set as inputs on startup. The individual bits can be set to be open-drain via PDDCR. See the associated peripheral chapters for details on how they use Parallel Port D. 11.2.2 Clocks All outputs on Parallel Port D are clocked by the peripheral clock unless changed in PDCR, where the option of updating the Parallel Port D pins can be synchronized to the output of Timer A1, Timer B1, or Timer B2. 11.2.3 Other Registers
Register SACR, SBCR, SCCR, SDCR, SECR, SFCR ICS1R, ICS2R QDCR I0CR, I1CR DMR0CR, DMR1CR Function Select a Parallel Port D pin as serial data (and optional clock) input. Select a Parallel Port D pin as a start/stop condition for Input Capture input. Select a Parallel Port D pin as a Quadrature Decoder input. Select a Parallel Port D pin as an external interrupt input. Select a Parallel Port D pin as an external DMA request input.
11.2.4 Interrupts External interrupts can be accepted from pins PD1 or PD0; see Chapter 7 for more details.
109
11.3 Operation
The following steps must be taken before using Parallel Port D. 1. Select the desired input/output direction for each pin via PDDDR. 2. Select high/low or open-drain functionality for outputs via PDDCR. 3. If an alternative peripheral output function is desired for a pin, select it via PDALR or PDAHR and then enable it via PDFR. Refer to the appropriate peripheral chapter for further use of that pin. Once Parallel Port D is set up, data can be read or written by accessing PDDR. Read PDDR to learn the current state of a Parallel Port D pin; any value written to an input pin will not appear on that pin until that pin becomes an output.
110

Parallel Port D Data Register Bit(s) 7:0 Value Read Write (PDDR) Description The current state of Parallel Port D pins PD7PD0 is reported. The Parallel Port D buffer is written with this value for transfer to the Parallel Port D output register on the next rising edge of the port transfer clock. The port transfer clock is established by PDCR. (Address = 0x0060)
Parallel Port D Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PDALR) Description
(Address = 0x0062)
Parallel Port D bit 3 alternate output 0 (IA7). Parallel Port D bit 3 alternate output 1 (I3). Parallel Port D bit 3 alternate output 2 (TIMER C3). Parallel Port D bit 3 alternate output 3 (SCLKD). Parallel Port D bit 2 alternate output 0 (SCLKC). Parallel Port D bit 2 alternate output 1 (I2). Parallel Port D bit 2 alternate output 2 (TIMER C2). Parallel Port D bit 2 alternate output 3 (TXF). Parallel Port D bit 1 alternate output 0 (IA6). Parallel Port D bit 1 alternate output 1 (I1). Parallel Port D bit 1 alternate output 2 (TIMER C1). Parallel Port D bit 1 alternate output 3 (RCLKF). Parallel Port D bit 0 alternate output 0 (SCLKD). Parallel Port D bit 0 alternate output 1 (I0). Parallel Port D bit 0 alternate output 2 (TIMER C0). Parallel Port D bit 0 alternate output 3 (TCLKF).
111
Parallel Port D Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PDAHR) Description
(Address = 0x0063)
Parallel Port D bit 7 alternate output 0 (IA7). Parallel Port D bit 7 alternate output 1 (I7). Parallel Port D bit 7 alternate output 2 (PWM3). Parallel Port D bit 7 alternate output 3 (SCLKC). Parallel Port D bit 6 alternate output 0 (TXA). Parallel Port D bit 6 alternate output 1 (I6). Parallel Port D bit 6 alternate output 2 (PWM2). Parallel Port D bit 6 alternate output 3 (TXE). Parallel Port D bit 5 alternate output 0 (IA6). Parallel Port D bit 5 alternate output 1 (I5). Parallel Port D bit 5 alternate output 2 (PWM1). Parallel Port D bit 5 alternate output 3 (RCLKE). Parallel Port D bit 4 alternate output 0 (TXB). Parallel Port D bit 4 alternate output 1 (I4). Parallel Port D bit 4 alternate output 2 (PWM0). Parallel Port D bit 4 alternate output 3 (TCLKE).
Parallel Port D Control Register Bit(s) 7:6 5:4 00 01 10 11 3:2 1:0 00 01 10 11 Value
(PDCR) Description
(Address = 0x0064)
These bits are ignored and should be written with zero. The upper nibble of the port transfer clock is perclk/2. The upper nibble of the port transfer clock is the output of Timer A1. The upper nibble of the port transfer clock is the output of Timer B1. The upper nibble of the port transfer clock is the output of Timer B2. These bits are ignored and should be written with zero. The lower nibble of the port transfer clock is perclk/2. The lower nibble of the port transfer clock is the output of Timer A1. The lower nibble of the port transfer clock is the output of Timer B1. The lower nibble of the port transfer clock is the output of Timer B2.
112
Parallel Port D Function Register Bit(s) 7:0 Value 0 1
(PDFR) Description
(Address = 0x0065)
Parallel Port D Drive Control Register Bit(s) 7:0 Value 0 1
(PDDCR) Description
(Address = 0x0066)
Parallel Port D Data Direction Register Bit(s) 7:0 Value 0 1
(PDDDR) Description
(Address = 0x0067)
Parallel Port D Bit 0 Register Bit(s) 7:1 0 Write Value These bits are ignored.
(PDB0R) Description
(Address = 0x0068)
The port buffer (bit 0) is written with the value of this bit. The port buffer will be transferred to the port output register on the next rising edge of the port transfer clock
Parallel Port D Bit 1 Register Bit(s) 7:2,0 1 Write Value These bits are ignored.
(PDB1R) Description
(Address = 0x0069)
113
Parallel Port D Bit 2 Register Bit(s) 7:3,1:0 2 Write Value These bits are ignored.
(PDB2R) Description
(Address = 0x006A)
(PDB3R) Description
(Address = 0x006B)
(PDB4R) Description
(Address = 0x006C)
(PDB5R) Description
(Address = 0x006D)
114
Parallel Port D Bit 6 Register Bit(s) 7,5:0 6 Write Value These bits are ignored.
(PDB6R) Description
(Address = 0x006E)
Parallel Port D Bit 7 Register Bit(s) 6:0 7 Write Value These bits are ignored.
(PDB7R) Description
(Address = 0x006F)
115
Bit(s) 7:6
Value 00 01 10 11
5:4
00 01 10 11
3:2
00 01 10 11
1:0
00 01 10 11
116
117
Quad Decode Control Register Bit(s) 7:6 Value 00 01 10 11 5 0 1 4 3:2 00 01 10 11 1:0 00 01 10 11
(QDCR) Description
(Address = 0x0091)
Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 7 and 6. Eight-bit quadrature decoder counters (both channels). Ten-bit quadrature decoder counters (both channels). This bit is reserved and should be written as zero. Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement. Quadrature Decoder 1 inputs from Parallel Port D bits 1 and 0. Quadrature Decoder 1 inputs from Parallel Port E bits 1 and 0. Quadrature Decoder 1 inputs from Parallel Port E bits 5 and 4. Quadrature Decoder interrupts are disabled. Quadrature Decoder interrupt use Interrupt Priority 1. Quadrature Decoder interrupt use Interrupt Priority 2. Quadrature Decoder interrupt use Interrupt Priority 3.
118
Interrupt x Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(I0CR) (I1CR) Description
Parallel Port D low nibble interrupt disabled. Parallel Port D low nibble interrupt on falling edge. Parallel Port D low nibble interrupt on rising edge. Parallel Port D low nibble interrupt on both edges. Parallel Port E high nibble interrupt disabled. Parallel Port E high nibble interrupt on falling edge. Parallel Port E high nibble interrupt on rising edge. Parallel Port E high nibble interrupt on both edges. Parallel Port E low nibble interrupt disabled. Parallel Port E low nibble interrupt on falling edge. Parallel Port E low nibble interrupt on rising edge. Parallel Port E low nibble interrupt on both edges. This external interrupt is disabled. This external interrupt uses Interrupt Priority 1. This external interrupt uses Interrupt Priority 2. This external interrupt uses Interrupt Priority 3.
119
DMA Master Request 0 Control Register Bit(s) 7:6 Value 00 01 10 11 5 4:3 00 01 10 11 2:0 000 001 010 011 100 101 110 111
(DMR0CR) Description
(Address = 0x0106)
External DMA Request 0 disabled. External DMA Request 0 enabled from Parallel Port D2. External DMA Request 0 enabled from Parallel Port E2. External DMA Request 0 enabled from Parallel Port E6. This bit is reserved and should be written with zero. External DMA Request 0 falling-edge triggered. One transfer per request. External DMA Request 0 rising-edge triggered. One transfer per request. External DMA Request 0 active low. Transfers continue while low. External DMA Request 0 active high. Transfers continue while high. External DMA Request 0 supplied to DMA Channel 0. External DMA Request 0 supplied to DMA Channel 1. External DMA Request 0 supplied to DMA Channel 2. External DMA Request 0 supplied to DMA Channel 3. External DMA Request 0 supplied to DMA Channel 4. External DMA Request 0 supplied to DMA Channel 5. External DMA Request 0 supplied to DMA Channel 6. External DMA Request 0 supplied to DMA Channel 7.
120
(Address = 0x0107)
External DMA Request 1 disabled. External DMA Request 1 enabled from Parallel Port D3. External DMA Request 1 enabled from Parallel Port E3. External DMA Request 1 enabled from Parallel Port E7. This bit is reserved and should be written with zero. External DMA Request 1 falling edge triggered. One byte per request. External DMA Request 1 rising edge triggered. One transfer per request. External DMA Request 1 active low. Transfers continue while low. External DMA Request 1 active high. Transfers continue while high. External DMA Request 1 supplied to DMA Channel 0. External DMA Request 1 supplied to DMA Channel 1. External DMA Request 1 supplied to DMA Channel 2. External DMA Request 1 supplied to DMA Channel 3. External DMA Request 1 supplied to DMA Channel 4. External DMA Request 1 supplied to DMA Channel 5. External DMA Request 1 supplied to DMA Channel 6. External DMA Request 1 supplied to DMA Channel 7.
121
122
12. PARALLEL PORT E

12.1 Overview
Parallel Port E is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port E Data Register (PEDR). All of the Parallel Port E pins have alternate output functions, and all of them can be used as inputs to various on-chip peripherals. When used as outputs, the Parallel Port E bits are buffered, with the data written to PEDR transferred to the output pins on a selected timing edge. Either the peripheral clock or the outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing. Each bit can either be programmed as open-drain or driven high and low. Because of the buffered nature of Parallel Port E, using a read-modify-write type of operation can lead to old data being written to PEDR. To alleviate this potential problem, each bit of the port can be written individually using a separate address for each bit. Bit 7 of Parallel Port E is used as the default chip select input for the slave port when the slave port is enabled, either for parallel bootstrap or under program control.
Table 12-1. Parallel Port E Pin Alternate Output Functions
Pin Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Alt Out 0 I7 I6 I5 I4 I3 I2 I1 I0 Alt Out 1 /A0 A23 A22 A21 A20 Alt Out 2 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 Alt Out 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF
Chapter 12 Parallel Port E
123
Table 12-2. Parallel Port E Pin Alternate Input Functions

Pin Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Input Capture
I/O Handshake
Serial Serial Ports AD Ports EF RXA RXB RXC SCLKC RXD SCLKD RXE RCLKE TCLKE RXF RCLKF TCLKF
DMA DREQ1 DREQ0 DREQ1 DREQ0
External Interrupts INT1 INT0 INT1 INT0
Quad Decode QRD2A QRD2B QRD1A QRD1B
124

Parallel Port E SPCR PEFR PEALR PEAHR PEDDR PEDCR Data PEDR PEBxR Serial Ports CF Tx, Rx, Clocks External I/O Strobes and Handshake /A0, A[23:20] PWM Output Timer C Output External Interrupts DMA Request Quadrature Decoder Input Capture perclk Timer A1 Timer B1 Timer B2 PECR 7:0 7:0 4:0 7:4 3:0 5, 4, 1, 0 7, 6, 3, 2 7:0 7, 5, 3, 1 7:0
125
12.1.2 Registers
Register Name Port E Data Register Port E Alternate Low Register Port E Alternate High Register Port E Control Register Port E Function Register Port E Drive Control Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register Port E Bit 3 Register Port E Bit 4 Register Port E Bit 5 Register Port E Bit 6 Register Port E Bit 7 Register Mnemonic PEDR PEALR PEAHR PECR PEFR PEDCR PEDDR PEB0R PEB1R PEB2R PEB3R PEB4R PEB5R PEB6R PEB7R I/O Address 0x0070 0x0072 0x0073 0x0074 0x0075 0x0076 0x0077 0x0078 0x0079 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W Reset xxxxxxxx 00000000 00000000 xx00xx00 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
12.2 Dependencies
12.2.1 I/O Pins Parallel Port E uses the pins PE0 through PE7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial Ports E and F; as clocks for Serial Ports CF; as external I/O strobes; as outputs for the PWM and Timer C peripherals; or as the upper address bits A[23:20]. The input capture peripheral can also watch pins PE7, PE5, PE3, and PE1. There is also an option to provide the slave port chip select on PE7. All pins are set as inputs on startup. The individual bits can be set to be open-drain via PEDCR. See the associated peripheral chapters for details on how they use Parallel Port E. 12.2.2 Clocks All outputs on Parallel Port E are clocked by the peripheral clock unless changed in PECR, where the option of updating the Parallel Port E pins can be synchronized to the output of Timer A1, Timer B1, or Timer B2.
126
12.2.3 Other Registers

Register SACR, SBCR, SCCR, SDCR, SECR, SFCR ICS1R, ICS2R QDCR I0CR, I1CR DMR0CR, DMR1CR SPCR IHCR, IHSR, IHTR Function Select a Parallel Port E pin as serial data (and optional clock) input. Select a Parallel Port E pin as a start/stop condition for Input Capture input. Select a Parallel Port E pin as a Quadrature Decoder input. Select a Parallel Port E pin as an external interrupt input. Select a Parallel Port E pin as an external DMA request input. Select slave chip select on PE7. Select a Parallel Port E pin for I/O handshake.
12.2.4 Interrupts External interrupts can be accepted from pins PE5, PE4, PE1 or PE0; see Chapter 7 for more details.
12.3 Operation
The following steps must be taken before using Parallel Port E. 1. Select the desired input/output direction for each pin via PEDDR. 2. Select high/low or open-drain functionality for outputs via PEDCR. 3. If an alternative peripheral output function is desired for a pin, select it via PEALR or PEAHR and then enable it via PEFR. Refer to the appropriate peripheral chapter for further use of that pin. Once the port is set up, data can be read or written by accessing PEDR. Read PEDR to learn the current state of a Parallel Port E pin; any value written to an input pin will not appear on that pin until that pin becomes an output.
127

Parallel Port E Data Register Bit(s) 7:0 Value Read Write (PEDR) Description The current state of Parallel Port E pins PE7PE0 is reported. The Parallel Port E buffer is written with this value for transfer to the Parallel Port E output register on the next rising edge of the port transfer clock. The port transfer clock is established by PECR. (Address = 0x0070)
Parallel Port E Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PEALR) Description
(Address = 0x0072)
Parallel Port E bit 3 alternate output 0 (I3). Parallel Port E bit 3 alternate output 1 (A23). Parallel Port E bit 3 alternate output 2 (TIMER C3). Parallel Port E bit 3 alternate output 3 (SCLKD). Parallel Port E bit 2 alternate output 0 (I2). Parallel Port E bit 2 alternate output 1 (A22). Parallel Port E bit 2 alternate output 2 (TIMER C2). Parallel Port E bit 2 alternate output 3 (TXF). Parallel Port E bit 1 alternate output 0 (I1). Parallel Port E bit 1 alternate output 1 (A21). Parallel Port E bit 1 alternate output 2 (TIMER C1). Parallel Port E bit 1 alternate output 3 (RCLKF). Parallel Port E bit 0 alternate output 0 (I0). Parallel Port E bit 0 alternate output 1 (A20). Parallel Port E bit 0 alternate output 2 (TIMER C0). Parallel Port E bit 0 alternate output 3 (TCLKF).
128
Parallel Port E Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PEAHR) Description
(Address = 0x0073)
Parallel Port E bit 7 alternate output 0 (I7). Parallel Port E bit 7 alternate output 1 (no functionality). Parallel Port E bit 7 alternate output 2 (PWM3). Parallel Port E bit 7 alternate output 3 (SCLKC). Parallel Port E bit 6 alternate output 0 (I6). Parallel Port E bit 6 alternate output 1 (no functionality). Parallel Port E bit 6 alternate output 2 (PWM2). Parallel Port E bit 6 alternate output 3 (TXE). Parallel Port E bit 5 alternate output 0 (I5). Parallel Port E bit 5 alternate output 1 (no functionality). Parallel Port E bit 5 alternate output 2 (PWM1). Parallel Port E bit 5 alternate output 3 RCLKE). Parallel Port E bit 4 alternate output 0 (I4). Parallel Port E bit 4 alternate output 1 (/A0). Parallel Port E bit 4 alternate output 2 (PWM0). Parallel Port E bit 4 alternate output 3 (TCLKE).
Parallel Port E Control Register Bit(s) 7:6 5:4 00 01 10 11 3:2 1:0 00 01 10 11 Value
(PECR) Description
(Address = 0x0074)
These bits are ignored and should be written with zero. The upper nibble peripheral clock is perclk/2. The upper nibble peripheral clock is the output of Timer A1. The upper nibble peripheral clock is the output of Timer B1. The upper nibble peripheral clock is the output of Timer B2. These bits are ignored and should be written with zero. The lower nibble peripheral clock is perclk/2. The lower nibble peripheral clock is the output of Timer A1. The lower nibble peripheral clock is the output of Timer B1. The lower nibble peripheral clock is the output of Timer B2.
129
Parallel Port E Function Register Bit(s) 7:0 Value 0 1
(PEFR) Description
(Address = 0x0075)
Parallel Port E Drive Control Register Bit(s) 7:0 Value 0 1
(PEDCR) Description
(Address = 0x0076)
Parallel Port E Data Direction Register Bit(s) 7:0 Value 0 1
(PEDDR) Description
(Address = 0x0077)
Parallel Port E Bit 0 Register Bit(s) 7:1 0 Write Value These bits are ignored.
(PEB0R) Description
(Address = 0x0078)
The port buffer (bit 0) is written with the value of this bit. The port buffer will be transferred to the port output register on the next rising edge of the peripheral clock.
Parallel Port E Bit 1 Register Bit(s) 7:2,0 1 Write Value These bits are ignored.
(PEB1R) Description
(Address = 0x0079)
130
Parallel Port E Bit 2 Register Bit(s) 7:3,1:0 2 Write Value These bits are ignored.
(PEB2R) Description
(Address = 0x007A)
(PEB3R) Description
(Address = 0x007B)
(PEB4R) Description
(Address = 0x007C)
(PEB5R) Description
(Address = 0x007D)
131
Parallel Port E Bit 6 Register Bit(s) 7,5:0 6 Write Value These bits are ignored.
(PEB6R) Description
(Address = 0x007E)
Parallel Port E Bit 7 Register Bit(s) 6:0 7 Write Value These bits are ignored.
(PEB7R) Description
(Address = 0x007F)
132
Bit(s) 7:6
Value 00 01 10 11
5:4
00 01 10 11
3:2
00 01 10 11
1:0
00 01 10 11
133
134
(QDCR) Description
(Address = 0x0091)
Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 7 and 6. Eight-bit quadrature decoder counters (both channels). Ten-bit quadrature decoder counters (both channels). This bit is reserved and should be written as zero. Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement. Quadrature Decoder 1 inputs from Parallel Port D bits 1 and 0. Quadrature Decoder 1 inputs from Parallel Port E bits 1 and 0. Quadrature Decoder 1 inputs from Parallel Port E bits 5 and 4. Quadrature Decoder interrupts are disabled. Quadrature Decoder interrupt use Interrupt Priority 1. Quadrature Decoder interrupt use Interrupt Priority 2. Quadrature Decoder interrupt use Interrupt Priority 3.
135
Interrupt x Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(I0CR) (I1CR) Description
Parallel Port D low nibble interrupt disabled. Parallel Port D low nibble interrupt on falling edge. Parallel Port D low nibble interrupt on rising edge. Parallel Port D low nibble interrupt on both edges. Parallel Port E high nibble interrupt disabled. Parallel Port E high nibble interrupt on falling edge. Parallel Port E high nibble interrupt on rising edge. Parallel Port E high nibble interrupt on both edges. Parallel Port E low nibble interrupt disabled. Parallel Port E low nibble interrupt on falling edge. Parallel Port E low nibble interrupt on rising edge. Parallel Port E low nibble interrupt on both edges. This external interrupt is disabled. This external interrupt uses Interrupt Priority 1. This external interrupt uses Interrupt Priority 2. This external interrupt uses Interrupt Priority 3.
136
(Address = 0x0106)
137
(Address = 0x0107)
External DMA Request 1 disabled. External DMA Request 1 enabled from Parallel Port D3. External DMA Request 1 enabled from Parallel Port E3. External DMA Request 1 enabled from Parallel Port E7. This bit is reserved and should be written with zero. External DMA Request 1 falling edge triggered. One byte per request. External DMA Request 1 rising edge triggered. One transfer per request. External DMA Request 1 active low. Transfers continue while low. External DMA Request 1 active high. Transfers continue while high. External DMA Request 1 supplied to DMA Channel 0. External DMA Request 1 supplied to DMA Channel 1. External DMA Request 1 supplied to DMA Channel 2. External DMA Request 1 supplied to DMA Channel 3. External DMA Request 1 supplied to DMA Channel 4. External DMA Request 1 supplied to DMA Channel 5. External DMA Request 1 supplied to DMA Channel 6. External DMA Request 1 supplied to DMA Channel 7.
138
(SPCR) Description
(Address = 0x0024)
139
I/O Handshake Control Register Bit(s) 7:5 4 0 1 3 2:0 000 001 010 011 100 101 110 111 Value
(IHCR) Description
(Address = 0x0028)
These bits are reserved and should be written with zeros. I/O handshake is active low (I/O transaction held until signal goes high). I/O handshake is active high (I/O transaction held until signal goes low). This bit is reserved and should be written with zero. Use Parallel Port E bit 0 for I/O handshake. Use Parallel Port E bit 1 for I/O handshake. Use Parallel Port E bit 2 for I/O handshake. Use Parallel Port E bit 3 for I/O handshake. Use Parallel Port E bit 4 for I/O handshake. Use Parallel Port E bit 5 for I/O handshake. Use Parallel Port E bit 6 for I/O handshake. Use Parallel Port E bit 7 for I/O handshake.
140
I/O Handshake Select Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(IHSR) Description
(Address = 0x0029)
Disable I/O handshake for I/O Bank 7. Enable I/O handshake for I/O Bank 7. Disable I/O handshake for I/O Bank 6. Enable I/O handshake for I/O Bank 6. Disable I/O handshake for I/O Bank 5. Enable I/O handshake for I/O Bank 5. Disable I/O handshake for I/O Bank 4. Enable I/O handshake for I/O Bank 4. Disable I/O handshake for I/O Bank 3. Enable I/O handshake for I/O Bank 3. Disable I/O handshake for I/O Bank 2. Enable I/O handshake for I/O Bank 2. Disable I/O handshake for I/O Bank 1. Enable I/O handshake for I/O Bank 1. Disable I/O handshake for I/O Bank 0. Enable I/O handshake for I/O Bank 0.
I/O Handshake Timeout Register Bit(s) 7 Value 0 1 6
(IHTR) Description
(Address = 0x002A)
No I/O handshake timeout has occurred since the last read of this register. An I/O handshake timeout has occurred since the last read of this register. This bit is cleared by a read of this register. This bit is reserved and should be written with zero. Time constant for the I/O handshake timeout counter. This time constant (times 32) selects the number of clocks that the I/O handshake input may delay completion of an I/O transaction before the I/O transaction will complete automatically.
5:0
141
142
13. PARALLEL PORT H

13.1 Overview
Parallel Port H is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port H Data Register (PHDR). All of the Parallel Port H pins have alternate output functions. When used as outputs, the Parallel Port H bits are buffered, with the data written to PHDR transferred to the output pins. Each bit can either be programmed as open-drain or driven high and low. Parallel Port H acts as the upper byte of the data bus when the 16-bit mode is enabled; all other Parallel Port H functionality will be disabled automatically when the 16-bit mode is in effect. Parallel Port H has no alternate input functionality.
Table 13-1. Parallel Port H Pin Alternate Output Functions
Pin Name PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Alt Out 0 Alt Out 1 I7 I6 I5 I4 I3 I2 I1 I0 Alt Out 2 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 Alt Out 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF 16-bit Data Bus D15 D14 D13 D12 D11 D10 D9 D8
Chapter 13 Parallel Port H
143

Parallel Port H MACR PHFR PHALR PHAHR PHDDR PHDCR Data PHDR PHBxR Serial Ports CF Tx, Clocks 16-bit Data Bus (upper byte) External I/O Strobes PWM Output Timer C Output perclk 7:0 7:0 7:0 7:4 3:0 7:0
13.1.2 Registers
Register Name Port H Data Register Port H Alternate Low Register Port H Alternate High Register Port H Function Register Port H Drive Control Register Port H Data Direction Register Mnemonic PHDR PHALR PHAHR PHFR PHDCR PHDDR I/O Address 0x0034 0x0032 0x0033 0x0035 0x0036 0x0037 R/W R/W R/W R/W R/W R/W R/W Reset 00000000 00000000 00000000 00000000 00000000 00000000
144
13.2 Dependencies
13.2.1 I/O Pins Parallel Port H uses pins PH0 through PH7. These pins can be used individually as data inputs or outputs; as the serial port transmit for Serial Ports E and F; as the clock transmit (internal clock mode) for Serial Ports CF; as external I/O strobes; or as outputs for the PWM and Timer C peripherals. In addition, Parallel Port H acts as the upper byte of the data bus (D[15:8]) when 16-bit addressing is enabled. All pins are set as inputs on startup. The individual bits can be set to be open-drain via PHDCR. See the associated peripheral chapters for details on how they use Parallel Port H. 13.2.2 Clocks All outputs on Parallel Port H are clocked by the peripheral clock. 13.2.3 Other Registers
Register MACR Function Enable 16-bit data bus.
13.2.4 Interrupts There are no interrupts associated with Parallel Port H.
13.3 Operation
The following steps must be taken before using Parallel Port H. 1. Select the desired input/output direction for each pin via PHDDR. 2. Select high/low or open-drain functionality for outputs via PHDCR. 3. If an alternative peripheral output function is desired for a pin, select it via PHALR or PHAHR and then enable it via PHFR. Refer to the appropriate peripheral chapter for further use of that pin. 4. All these settings will be superseded if a 16-bit memory interface is selected since Parallel Port H is used for the upper half of the data bus in that mode. Once Parallel Port H is set up, data can be read or written by accessing PHDR. The value of an output pin read in from PHDR will reflect its current output value, but any value written to an input pin will not appear on that pin until that pin becomes an output.
145

Parallel Port H Data Register Bit(s) 7:0 Value Read Write (PHDR) Description The current state of Parallel Port H pins PH7PH0 is reported. The Parallel Port H buffer is written with this value for transfer to the Parallel Port H output register on the next rising edge of the peripheral clock. (Address = 0x0034)
Parallel Port H Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PHALR) Description
(Address = 0x0032)
This value is reserved and must not be used. Parallel Port H bit 3 alternate output 1 (I3). Parallel Port H bit 3 alternate output 2 (TIMER C3). Parallel Port H bit 3 alternate output 3 (SCLKD). This value is reserved and must not be used. Parallel Port H bit 2 alternate output 1 (I2). Parallel Port H bit 2 alternate output 2 (TIMER C2). Parallel Port H bit 2 alternate output 3 (TXF). This value is reserved and must not be used. Parallel Port H bit 1 alternate output 1 (I1). Parallel Port H bit 1 alternate output 2 (TIMER C1). Parallel Port H bit 1 alternate output 3 (RCLKF). This value is reserved and must not be used. Parallel Port H bit 0 alternate output 1 (I0). Parallel Port H bit 0 alternate output 2 (TIMER C0). Parallel Port H bit 0 alternate output 3 (TCLKF).
146
Parallel Port H Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PHAHR) Description
(Address = 0x0033)
This value is reserved and must not be used. Parallel Port H bit 7 alternate output 1 (I7). Parallel Port H bit 7 alternate output 2 (PWM3). Parallel Port H bit 7 alternate output 3 (SCLKC). This value is reserved and must not be used. Parallel Port H bit 6 alternate output 1 (I6). Parallel Port H bit 6 alternate output 2 (PWM2). Parallel Port H bit 6 alternate output 3 (TXE). This value is reserved and must not be used. Parallel Port H bit 5 alternate output 1 (I5). Parallel Port H bit 5 alternate output 2 (PWM1). Parallel Port H bit 5 alternate output 3 (RCLKE). This value is reserved and must not be used. Parallel Port H bit 4 alternate output 1 (I4). Parallel Port H bit 4 alternate output 2 (PWM0). Parallel Port H bit 4 alternate output 3 (TCLKE).
Parallel Port H Function Register Bit(s) 7:0 Value 0 1
(PHFR) Description
(Address = 0x0035)
Parallel Port H Drive Control Register Bit(s) 7:0 Value 0 1
(PHDCR) Description
(Address = 0x0036)
147
Parallel Port H Data Direction Register Bit(s) 7:0 Value 0 1
(PHDDR) Description
(Address = 0x0037)
Memory Alternate Control Register Bit(s) 7 Value 0 1 6 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(MACR) Description
(Address = 0x001D)
Normal 8-bit operation for /CS3. Use MBxCR for wait states. This bit is used only when external memory is present. Normal 16-bit operation for /CS3. Use MBxCR for wait states. When standalone operation is selected (by strapping a pin), this bit is forced high. This bit is reserved and must not be used. Normal 8-bit operation for /CS2. Page-Mode 8-bit operation for /CS2. Normal 16-bit operation for /CS2. Page-Mode 16-bit operation for /CS2. Normal 8-bit operation for /CS1. Page-Mode 8-bit operation for /CS1. Normal 16-bit operation for /CS1. Page-Mode 16-bit operation for /CS1. Normal 8-bit operation for /CS0. Page-Mode 8-bit operation for /CS0. Normal 16-bit operation for /CS0. Page-Mode 16-bit operation for /CS0.
148
14. TIMER A
14.1 Overview
The Timer A peripheral consists of ten separate eight-bit countdown timers, A1A10. Each counter counts down from a programmed time constant, which is automatically reloaded into the respective counter when the count reaches zero. For example, if the reload register contains 127, then 128 pulses enter on the left before a pulse exits on the right (see Figure 14-1). If the reload register contains zero, then each pulse on the left results in a pulse on the right, that is, there is division by one. The reload register can contain any number in the range from 0 to 255. The counter divides by (n + 1).
8-bit Reload Register
Clock IN
LOAD 8-bit Down Counter
Pulse on Zero Count OUT
Input Clock Count Value 2 1 0 N N-1
Figure 14-1. Reload Register Operation
The output pulses are always one clock wide. Clocking of the timers takes place on the negative edge of these pulses. When the counter reaches zero, the reload register is loaded into the counter on the next input pulse instead of a count being performed. The terminal count condition for Timers A1A7 is reported in a status register and can be programmed to generate an interrupt. Six of these seven timers (A2A7) have the option of being cascaded from Timer A1, but the primary clock for all of the timers is the peripheral clock either directly or divided by 2 (the default). Timers A2A7 can be used to generate baud rates for Serial Ports AF, or they can be used as general-purpose timers if the dedicated timers on the Rabbit 5000 serial ports are used. The three remaining timers (A8A10) serve as prescalers for the input capture, PWM, and quadrature decoder peripherals respectively. The peripherals clocked by these timers can
Chapter 14 Timer A 149
generate interrupts but the timers themselves cannot. Furthermore, these timers cannot be cascaded with Timer A1. The individual Timer A capabilities are summarized in the table below. There is a bit in the control/status register to disable all ten timers globally.
Cascade from A1 No Yes Yes Yes Yes Yes Yes No No No
Timer A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
Interrupt Yes Yes Yes Yes Yes Yes Yes No No No
Associated Peripheral Parallel Ports DE, Timers BC Serial Port E Serial Port F Serial Port A Serial Port B Serial Port C Serial Port D Input Capture Pulse-Width Modulator Quadrature Decoder
There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has bits for Timers A1A7 that indicate if the output pulse for that timer has taken place since the last read of the status register. These bits are cleared when the status register is read. No bit will be lost. Either it will be read by the status register read or it will be set after the status register read is complete. If a bit is on and the corresponding interrupt is enabled, an interrupt will occur when priorities allow. However, a separate interrupt is not guaranteed for each bit with an enabled interrupt. If the bit is read in the status register, it is cleared and no further interrupt corresponding to that bit will be requested. It is possible that one bit will cause an interrupt, and then one or more additional bits will be set before the status register is read. After these bits are cleared, they cannot cause an interrupt. The proper rule to follow is for the interrupt routine to handle all bits that it sees set.
150

Timer A TAPR perclk perclk/2 Timer A1 TACR Timer A2 Serial Ports AF Timer A7 Parallel Ports DE Control, Timer B, Timer C
Timer A8
Input Capture
Timer A9
PWM
Timer A10
Quadrature Decoder
Timer Ax
Input Clock
Down Counter 0
= Interrupt Generation TACR TACSR
Output Interrupt Request Timers A1A7
Reload Register TATxR
Chapter 14 Timer A
151
14.1.2 Registers
Register Name Timer A Control/Status Register Timer A Prescale Register Timer A Time Constant 1 Register Timer A Control Register Timer A Time Constant 2 Register Timer A Time Constant 8 Register Timer A Time Constant 3 Register Timer A Time Constant 9 Register Timer A Time Constant 4 Register Timer A Time Constant 10 Register Timer A Time Constant 5 Register Timer A Time Constant 6 Register Timer A Time Constant 7 Register Mnemonic TACSR TAPR TAT1R TACR TAT2R TAT8R TAT3R TAT9R TAT4R TAT10R TAT5R TAT6R TAT7R I/O Address 0x00A0 0x00A1 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB 0x00AD 0x00AF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 00000000 xxxxxxx1 xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
14.2 Dependencies
14.2.1 I/O Pins The Timer A outputs do not come out directly on any of the I/O pins. They can be used to control when the output occurs on Parallel Ports DE, and can affect the output times of Serial Ports AF and the PWM. 14.2.2 Clocks The timers in Timer A can be clocked by either perclk or perclk/2, as selected in TAPR. In addition, Timers A2A7 can be clocked by the output of Timer A1 by selecting that option in TACSR. 14.2.3 Other Registers
Register GCSR Function Select peripheral clock mode.
152
14.2.4 Interrupts A Timer A interrupt can be generated whenever Timers A1A7 decrement to zero by enabling the appropriate bit in TACSR. The interrupt request is cleared when TACSR is read. The Timer A interrupt vector is in the IIR at offset 0x0A0. It can be set as priority 1, 2, or 3 in TACR.
14.3 Operation
The following steps explain how to set up a Timer A timer. 1. Use the default perclk/2 in TAPR as the Timer A input clock. You may instead select perclk in TAPR. 2. Select the source clocks for Timers A2A7 in TACR. 3. Write the desired divider value to TATxR for all timers that will be used. 4. Enable Timer A by writing a 1 to bit 0 of TACSR. 14.3.1 Handling Interrupts The following steps explain how an interrupt is set up and used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Configure TACSR to select which timers will generate an interrupt. 3. Configure TACR to select the interrupt priority (note that interrupts will be enabled once this value is set). This should be done last. The interrupt request is cleared by reading from TACSR. 14.3.2 Example ISR A sample interrupt handler is shown below.
timerA_isr:: push af ioi ld a, (TACSR) ; save used registers ; clear the interrupt request and get status
; handle all interrupts flagged in TACSR here pop af ipres ret ; restore registers
Chapter 14 Timer A
153

Timer A Control/Status Register Bit(s) 7:1 (Readonly) 7:1 (Writeonly) 0 Value 0 1 0 1 0 1 (TACSR) Description The corresponding Timer A counter has not reached its terminal count. The corresponding Timer A counter has reached its terminal count. These status bits (not the interrupt enable bits) are cleared by the read of this register, as is the Timer A interrupt. The corresponding Timer A interrupt is disabled. The corresponding Timer A interrupt is enabled. The clock input for Timer A is disabled. The clock input for Timer A is enabled. (Address = 0x00A0)
Timer A Prescale Register Bit(s) 7:1 0 0 1 Value
(TAPR) Description
(Address = 0x00A1)
These bits are reserved and should be written with zero. The main clock for Timer A is the peripheral clock (perclk). The main clock for Timer A is the peripheral clock divided by two (perclk/2).
154
Timer A Control Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1:0 00 01 10 11
(TACR) Description
(Address = 0x00A4)
Timer A7 clocked by the main Timer A clock. Timer A7 clocked by the output of Timer A1. Timer A6 clocked by the main Timer A clock. Timer A6 clocked by the output of Timer A1. Timer A5 clocked by the main Timer A clock. Timer A5 clocked by the output of Timer A1. Timer A4 clocked by the main Timer A clock. Timer A4 clocked by the output of Timer A1. Timer A3 clocked by the main Timer A clock. Timer A3 clocked by the output of Timer A1. Timer A2 clocked by the main Timer A clock. Timer A2 clocked by the output of Timer A1. Timer A interrupts are disabled. Timer A interrupt use Interrupt Priority 1. Timer A interrupt use Interrupt Priority 2. Timer A interrupt use Interrupt Priority 3.
Timer A Time Constant x Register
(TAT1R) (TAT2R) (TAT3R) (TAT4R) (TAT5R) (TAT6R) (TAT7R) (TAT8R) (TAT9R) (TAT10R) Description
(Address = 0x00A3) (Address = 0x00A5 (Address = 0x00A7)) (Address = 0x00A9) (Address = 0x00AB) (Address = 0x00AD) (Address = 0x00AF) (Address = 0x00A6) (Address = 0x00A8) (Address = 0x00AA)
Bit(s) 7:0
Value
Time constant for the Timer A counter. This time constant will take effect the next time that the Timer A counter counts down to zero. The timer counts modulo n + 1, where n is the programmed time constant.
Chapter 14 Timer A
155
Global Control/Status Register Bit(s) 4:2 Value 000
(GCSR) Description
(Address = 0x0000)
Processor clock from the main clock, divided by eight. Peripheral clock from the main clock, divided by eight. Processor clock from the main clock, divided by eight. Peripheral clock from the main clock. Processor clock from the main clock. Peripheral clock from the main clock. Processor clock from the main clock, divided by two. Peripheral clock from the main clock, divided by two. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The fast clock is disabled. Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six.
001
010
011
100
101
110
111
156
15. TIMER B
15.1 Overview
The Timer B peripheral consists of a ten-bit free running up-counter, two match registers, and two step registers. Timer B is driven by perclk/2, by perclk/16, or by the output of Timer A1. Timer B generates an output pulse whenever the counter reaches the match value. This output pulse can generate an interrupt and will set a status bit in the status register. The processor may then write a new value to the match register. This allows Timer B to be used for pulse-width or pulse-position modulation because the outputs of Timer B can clock the outputs on Parallel Ports D and E. The compare value comes from either the match register or the value internally generated via the step register. When using the match register, a new match value must be written to the match register after each match condition, LSB first. When using the step register, the hardware automatically calculates the next match value by adding the contents of the step register to the current match value. This allows Timer B matches to be generated at regular periods without calculating the new match value during the interrupt service routine. 15.1.1 Block Diagram
Timer B perclk/2 perclk/16 Timer A1 TBCR Counter Interrupt Generation Interrupt Request
Timer Bx = Timer Bx Reload Registers TBMxR TBLxR TBSMxR TBSLxR Parallel Ports DE
Chapter 15 Timer B
157
15.1.2 Registers
Register Name Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register Timer B Step LSB 1 Register Timer B Step MSB 1 Register Timer B Step LSB 2 Register Timer B Step MSB 2 Register Timer B Count MSB Register Timer B Count LSB Register Mnemonic TBCSR TBCR TBM1R TBL1R TBM2R TBL2R TBSL1R TBSM1R TBSL2R TBSM2R TBCMR TBCLR I/O Address 0x00B0 0x00B1 0x00B2 0x00B3 0x00B4 0x00B5 0x00BA 0x00BB 0x00BC 0x00BD 0x00BE 0x00BF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Reset xxxx0000 xx000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
15.2 Dependencies
15.2.1 I/O Pins The output of Timer B does not come out directly on any of the I/O pins. It can be used to control when the output occurs on Parallel Ports DE. 15.2.2 Clocks The timer in Timer B can be clocked by perclk/2, perclk/16, or by countdown Timer A1 as selected in TBCR. 15.2.3 Other Registers
Register GCSR Function Select peripheral clock mode.
15.2.4 Interrupts A Timer B interrupt can be generated whenever the counter equals one of the match registers by enabling the appropriate bit in TBCSR. The interrupt request is cleared when TBCSR is read.
158
15.3 Operation
The following steps explain how to set up a Timer B countdown timer. 1. Select perclk/2, perclk/16, or countdown Timer A1 in TBCR. 2. Use TBCR to select whether countdown Timers B1B2 operate normally with the match registers or whether they use the step registers to calculate match values. 3. Enable Timer B by writing a 1 to bit 0 of TBCSR. 15.3.1 Handling Interrupts The following steps explain how an interrupt is set up and used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Configure TBCSR to select which match register will generate an interrupt. 3. Configure TBCR to select the interrupt priority (note that interrupts will be enabled once this value is set; this step should be done last). The interrupt request is cleared by reading from TBCSR. 15.3.2 Example ISR A sample interrupt handler is shown below.
timerB_isr:: push af ioi ld a, (TBCSR) ; save used registers ; clear the interrupt request and get status
; handle all interrupts flagged in TBCSR here ; reload match register(s) if necessary pop af ipres ret ; restore used registers
Chapter 15 Timer B
159

Timer B Control/Status Register Bit(s) 7:3 2:1 (Readonly) 2:1 (Writeonly) 0 0 1 0 1 0 1 Value These bits always read as zero. The corresponding Timer B comparator has not encountered a match condition. The corresponding Timer B comparator has encountered a match condition. These status bits (but not the interrupt enable bits) are cleared by the read of this register, as is the Timer B interrupt. The corresponding Timer B interrupt is disabled. The corresponding Timer B interrupt is enabled. The clock input for Timer B is disabled. The clock input for Timer B is enabled. (TBCSR) Description (Address = 0x00B0)
Timer B Control Register Bit(s) 7:6 5 0 1 4 0 1 3:2 00 01 10 11 1:0 00 01 10 11 Value
(TBCR) Description
(Address = 0x00B1)
These bits are reserved and should be written with zero. Normal Timer B2 operation using the match registers. Enable Timer B2 to use the step registers to calculate match values. Normal Timer B1 operation, using the match registers. Enable Timer B1 to use the step registers to calculate match values. Timer B clocked by perclk/2. Timer B clocked by the output of Timer A1. Timer B clocked by the peripheral clock divided by 16. Timer B clocked by the peripheral clock divided by 16. Timer B interrupts are disabled. Timer B interrupt use Interrupt Priority 1. Timer B interrupt use Interrupt Priority 2. Timer B interrupt use Interrupt Priority 3.
160
Timer B Count MSB x Register Bit(s) 7:6 5:0 Value
(TBM1R) (TBM2R) Description
(Address = 0x00B2) (Address = 0x00B4)
Two MSBs of the compare value for the Timer B comparator. This compare value will be loaded into the actual comparator when the current compare detects a match. These bits are reserved and should be written with zero.
Timer B Count LSB x Register Bit(s) 7:0 Value
(TBL1R) (TBL2R) Description
(Address = 0x00B3) (Address = 0x00B5)
Eight LSBs of the compare value for the Timer B comparator. This compare value will be loaded into the actual comparator when the current compare detects a match.
Timer B Step LSB x Register Bit(s) 7:0 Value
(TBSL1R) (TBSL2R) Description
(Address = 0x00BA) (Address = 0x00BC)
Eight LSBs of the step size for the Timer B comparator. The new compare value will be loaded into the actual comparator when the current compare detects a match.
Timer B Step MSB x Register Bit(s) 7:2 1:0 Value
(TBSM1R) (TBSM2R) Description
(Address = 0x00BB) (Address = 0x00BD)
These bits are ignored but should be written with zeros. Two MSBs of the step size for the Timer B comparator. The new compare value will be loaded into the actual comparator when the current compare detects a match.
Timer B Count MSB Register Bit(s) 7:6 5:0 Value Read
(TBCMR) Description
(Address = 0x00BE)
The current value of the two MSBs of the Timer B counter is reported. These bits are always read as zeros.
Chapter 15 Timer B
161
Timer B Count LSB Register Bit(s) 7:0 Value Read
(TBCLR) Description
(Address = 0x00BF)
The current value of the eight LSBs of the Timer B counter is reported.
(GCSR) Description
(Address = 0x0000)
001
010
011
100
101
110
111
162
16. TIMER C
16.1 Overview
The Timer C peripheral is a 16-bit up-counter clocked by the peripheral clock divided by 2, by the peripheral clock divided by 16, or by the output of countdown Timer A1. The counter counts from zero to the limit programmed into the Timer C divider registers and then restarts at zero, so the overall cycle count is the value in the divider registers plus one. There are four Timer C outputs that are called Timers C0C3. Each output is controlled by a 16-bit set value and a 16-bit reset value. Each output is set to one when the count matches the value in the corresponding set register and is cleared when the count matches the value programmed in the corresponding reset register. This allows the creation of quadrature signals or three-phase signals with a variable frequency for motor-control applications. The values in all of the Timer C registers are transferred to holding registers for use during the count cycle when the counter is reloaded with zeros, allowing the control registers to be reloaded at any time during the count cycle. Timer C can generate an interrupt when the count limit value is reached. A separate Timer C Block Access Register (TCBAR) and Timer C Block Pointer Register (TCBPR) are available to allow DMA control of Timer C. The pointer register contains the address of the Timer C register to be accessed via the access register. Each read or write of the access register automatically increments the pointer register through the sequence shown below. Note that only the lower five bits of the pointer actually change. This allows the DMA to write to a fixed internal I/O location but still program all of the relevant Timer registers. The pointer register can be written and read if necessary. Normally the pointer register is initialized to 0x02 (the Timer C Divider Low Register), and the DMA then transfers blocks of 18 bytes to completely reprogram Timer C.
0x502 -> 0x503 -> 0x508 -> 0x509 -> 0x50A -> 0x50B -> 0x50C -> 0x50D -> 0x50E -> 0x50F -> 0x518 -> 0x519 -> 0x51A -> 0x51B -> 0x51C -> 0x51D -> 0x51E -> 0x51F ->
When the DMA destination address is the TCBAR, the DMA request from Timer C is connected automatically to the DMA.
Chapter 16 Timer C
163

Timer C TCCR Up Counter = RESET Interrupt Generation Interrupt Request
perclk/2 perclk/16 Timer A1
Divider Registers Timer Cx set x Register
= Set Reset = Parallel Ports CE, H
reset x Register
164
16.1.2 Registers
Register Name Timer C Control/Status Register Timer C Control Register Timer C Divider Low Register Timer C Divider High Register Timer C Set 0 Low Register Timer C Set 0 High Register Timer C Reset 0 Low Register Timer C Reset 0 High Register Timer C Set 1 Low Register Timer C Set 1 High Register Timer C Reset 1 Low Register Timer C Reset 1 High Register Timer C Set 2 Low Register Timer C Set 2 High Register Timer C Reset 2 Low Register Timer C Reset 2 High Register Timer C Set 3 Low Register Timer C Set 3 High Register Timer C Reset 3 Low Register Timer C Reset 3 High Register Timer C Block Access Register Timer C Block Pointer Register Mnemonic TCCSR TCCR TCDLR TCDHR TCS0LR TCS0HR TCR0LR TCR0HR TCS1LR TCS1HR TCR1LR TCR1HR TCS2LR TCS2HR TCR2LR TCR2HR TCS3LR TCS3HR TCR3LR TCR3HR TCBAR TCBPR I/O Address 0x0500 0x0501 0x0502 0x0503 0x0508 0x0509 0x050A 0x050B 0x050C 0x050D 0x050E 0x050F 0x0518 0x0519 0x051A 0x051B 0x051C 0x051D 0x051E 0x051F 0x00F8 0x00F9 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W Reset xxxx0000 xx000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000010
Chapter 16 Timer C
165
16.2 Dependencies
16.2.1 I/O Pins The four Timer C outputs can be directed to PC0-PC3, PD0-PD3, PE0-PE3, pr PH0-PH3. 16.2.2 Clocks The timer in Timer C is a 16-bit up-counter clocked by the peripheral clock divided by 2, by the peripheral clock divided by 16, or by the output of Timer A1 as selected in TCCR. 16.2.3 Other Registers
Register GCSR PCFR, PCALR PDFR, PDALR PEFR, PEALR PHFR, PHALR Function Select peripheral clock mode.
Alternate port output selection
16.2.4 Interrupts A Timer C interrupt is enabled in TCCR, and will occur whenever the count limit value is reached. The interrupt request is cleared when TCCSR is read.
166
16.3 Operation
The following steps explain how to set up a Timer C timer. 1. Select perclk/2, perclk/16, or countdown Timer A1 in TCCR. 2. Load the desired upper limit for the counter into TCDLR and TCDHR. The overall clock count per Timer C cycle will be the value loaded into the divider registers plus one. 3. Load the desired set and reset values for the Timer C outputs into the set and reset registers (TCSxLR, TCSxHR, TCRxLR, and TCRxHR). 4. If you intend to use DMA control of Timer C, use TCBAR to access the Timer C register pointed to by TCBPR. 5. Enable the desired output pins for Timer C by writing to the appropriate parallel port function and alternate output registers. 6. Enable Timer C by writing a 1 to bit 0 of TCCSR. 16.3.1 Handling Interrupts The following steps explain how an interrupt is used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Configure TCCR to select the interrupt priority (note that interrupts will be enabled once this value is set). The interrupt request is cleared by reading from TCCSR. 16.3.2 Example ISR A sample interrupt handler is shown below.
timerC_isr:: push af ioi ld a, (TCCSR) ; save used registers ; clear the interrupt request and get status
; handle all interrupts flagged in TCCSR here pop af ipres ret ; restore used registers
Chapter 16 Timer C
167

Timer C Control/Status Register Bit(s) 7:2 1 (Readonly) 0 0 1 0 1 Value (TCCSR) Description These bits are always read as zero. Timer C divider has not reached its maximum value. Timer C divider has reached its maximum value. This status bit is cleared by the read of this register, as is the Timer C interrupt. The clock input for Timer C is disabled. The clock input for Timer C is enabled. (Address = 0x0500)
Timer C Control Register Bit(s) 7:4 3:2 00 01 10 11 1:0 00 01 10 11 Value
(TCCR) Description
(Address = 0x0501)
These bits are reserved and should be written with zero. Timer C clocked by the peripheral clock divided by 2. Timer C clocked by the output of Timer A1. Timer C clocked by the peripheral clock divided by 16. Timer C clocked by the peripheral clock divided by 16. Timer C interrupts are disabled. Timer C interrupt uses Interrupt Priority 1. Timer C interrupt uses Interrupt Priority 2. Timer C interrupt uses Interrupt Priority 3.
Timer C Divider Low Register Bit(s) 7:0 Value
(TCDLR) Description
(Address = 0x0502)
The eight LSBs of the divider limit value for Timer C are stored.
Timer C Divider High Register Bit(s) 7:0 Value
(TCDHR) Description
(Address = 0x0503)
The eight MSBs of the divider limit value for Timer C are stored.
168
Timer C Set x Low Register
(TCS0LR) (TCS1LR) (TCS2LR) (TCS3LR) Description
(Address = 0x0508) (Address = 0x050C) (Address = 0x0518) (Address = 0x051C)
Bit(s) 7:0
Value
Eight LSBs of the match value to set Timer C Output x.
Timer C Set x High Register
(TCS0HR) (TCS1HR) (TCS2HR) (TCS3HR) Description
(Address = 0x0509) (Address = 0x050D) (Address = 0x0519) (Address = 0x051D)
Bit(s) 7:0
Value
Eight MSBs of the match value to set Timer C Output x.
Timer C Reset x Low Register
(TCR0LR) (TCR1LR) (TCR2LR) (TCR3LR) Description
(Address = 0x050A) (Address = 0x050E) (Address = 0x051A) (Address = 0x051E)
Bit(s) 7:0
Value
Eight LSBs of the match value to reset Timer C Output x.
Timer C Reset x High Register
(TCR0HR) (TCR1HR) (TCR2HR) (TCR3HR) Description
(Address = 0x050B) (Address = 0x050F) (Address = 0x051B) (Address = 0x051F)
Bit(s) 7:0
Value
Eight MSBs of the match value to reset Timer C Output x.
Timer C Block Access Register Bit(s) 7:0 Value
(TCBAR) Description
(Address = 0x00F8)
Access the Timer C register pointed to by TCBPR. TCBPR is automatically updated to the next Timer C register address in the sequence.
Chapter 16 Timer C
169
Timer C Block Pointer Register Bit(s) 7:5 4:0 Value These bits always read as 0x0.
(TCBPR) Description
(Address = 0x00F9)
Five least significant bits of the Timer C register address for indirect access.
(GCSR) Description
(Address = 0x0000)
001
010
011
100
101
110
111
170
17. SERIAL PORTS A D

17.1 Overview
Serial Ports A, B, C, and D are identical, except for the source of the data clock and the transmit, receive, and clock pins. In addition to being used as a regular serial port, Serial Port A can be used to bootstrap the processor. Each serial port can be used in the asynchronous or the clocked serial mode with an internal or external clock. In the asynchronous mode, either 7 or 8 data bits can be transferred, and a parity bit and/or a ninth data bit can be appended as well. Parity and the ninth data bits are also detected when they are received. The asynchronous mode is full-duplex, while the clocked mode can be half or full-duplex. Both transmit and receive have one byte of buffering a byte may be read while another byte is being received, or the next byte to be transmitted can be loaded while the current byte is still being transferred out. The status of each serial port is available in its Serial Port Status Register (SxSR), and contains information on whether a received byte is available, the receive buffer was overrun, a parity error was received, the transmit buffer is empty or busy sending a byte, and the state of the ninth data bit (whether it is an address bit or a stop bit). Each serial port has a separate interrupt vector that will be requested whenever the transmit buffer is emptied or the receive buffer contains a full byte. All four common SPI clock modes are supported, and the bit order of the data may be either MSB or LSB first. The transmit and receive operations are under program control as well.
Chapter 17 Serial Ports A D
171
CLK (Mode00) CLK (Mode 01) CLK (Mode 10) CLK (Mode 11) Tx Rx Tx (bit reversed) Rx (bit reversed)
D0 D0 D7 D7 D1 D1 D6 D6 D2 D2 D5 D5 D3 D3 D4 D4 D4 D4 D3 D3 D5 D5 D2 D2 D6 D6 D1 D1 D7 D7 D0 D0
Figure 17-1. Serial Ports A D Operation in Clocked Serial Mode
In the asynchronous mode, IrDA-compliant RZI encoding can be enabled to reduce the bit widths to 3/16 the normal width (1/8 the normal width if the serial data clock is 8 instead of 16), which allows the serial port signal to be connected directly to an IrDA transceiver. It is possible to select the same pin on Parallel Port C for both transmit and receive operation. This allows glueless support for bidirectional serial protocols. It is possible to synchronize a clocked serial transfer to the match registers of Timer B to generate precisely timed transmissions. The serial port data clocks can be generated from the appropriate 8-bit timer from Timer A shown in Table 17-1 or from a dedicated n+1 15-bit divider. In either case, the resulting bit data rate in the asynchronous mode is 1/8 or 1/16 the data clock rate (selectable). However, the bit data rate in the clocked serial mode is equal to the data clock rate as generated from the appropriate Timer A timer or from the dedicated 15-bit divider.
Table 17-1. Timer A Data Clocks
Serial Port A B C D Data Clock Timer A4 Timer A5 Timer A6 Timer A7
When Serial Port A is used in the asynchronous bootstrap mode, the 32 kHz clock is used to generate the expected 2400 bps data rate. An external clock must be supplied for the clocked serial bootstrap mode.
172
The behavior of the serial port during a break (line held low) is configurable; character assembly can continue during the break condition to allow for timing the break, or character assembly can be inhibited to reduce the interrupt overhead. 17.1.1 Block Diagram
Serial Ports AD Peripheral Clock SxDHR 15-bit Divider SxDHR SxDLR Timer Ax Output Serial Data Clock Serial Port Control SxCR SxER
Rx Pins
Rx Buffer (1 byte)
Latched Rx Buffer SxDR SxAR SxLR Latched Tx Buffer SxDR SxAR SxLR Serial Port Status SxSR Interrupt Request Tx Buffer (1 byte)
Tx Pins
173
17.1.2 Registers
Register Name Serial Port A Data Register Serial Port A Address Register Serial Port A Long Stop Register Serial Port A Status Register Serial Port A Control Register Serial Port A Extended Register Serial Port A Divider Low Register Serial Port A Divider High Register Serial Port B Data Register Serial Port B Address Register Serial Port B Long Stop Register Serial Port B Status Register Serial Port B Control Register Serial Port B Extended Register Serial Port B Divider Low Register Serial Port B Divider High Register Serial Port C Data Register Serial Port C Address Register Serial Port C Long Stop Register Serial Port C Status Register Serial Port C Control Register Serial Port C Extended Register Serial Port C Divider Low Register Serial Port C Divider High Register Serial Port D Data Register Serial Port D Address Register Serial Port D Long Stop Register Serial Port D Status Register Serial Port D Control Register Serial Port D Extended Register Serial Port D Divider Low Register Serial Port D Divider High Register
174
Mnemonic SADR SAAR SALR SASR SACR SAER SADLR SADHR SBDR SBAR SBLR SBSR SBCR SBER SBDLR SBDHR SCDR SCAR SCLR SCSR SCCR SCER SCDLR SCDHR SDDR SDAR SDLR SDSR SDCR SDER SDDLR SDDHR
I/O Address 0x00C0 0x00C1 0x00C2 0x00C3 0x00C4 0x00C5 0x00C6 0x00C7 0x00D0 0x00D1 0x00D2 0x00D3 0x00D4 0x00D5 0x00D6 0x00D7 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 0x00F0 0x00F1 0x00F2 0x00F3 0x00F4 0x00F5 0x00F6 0x00F7
R/W R/W W W R R/W R/W R/W R/W R/W W W R R/W R/W R/W R/W R/W W W R R/W R/W R/W R/W R/W W W R R/W R/W R/W R/W
Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 0xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 0xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 0xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 0xxxxxxx
17.2 Dependencies
17.2.1 I/O Pins Serial Port A can transmit on parallel port pins PC7, PC6, or PD6, and can receive on pins PC7, PD7, or PE7. If the clocked serial mode is enabled, the serial clock is either transmitted or received on PB1. When an internal clock is selected in the clocked serial mode, PB1 is automatically enabled as a clock output. Serial Port B can transmit on parallel port pins PC5, PC4, or PD4, and can receive on pins PC5, PD5, or PE5. If the clocked serial mode is enabled, the serial clock is either transmitted or received on PB0. When an internal clock is selected in the clocked serial mode, PB0 is automatically enabled as a clock output. Serial Port C can transmit on parallel port pins PC3 or PC2, and can receive on pins PC3, PD3, or PE3. If the clocked serial mode is enabled, the serial clock can be transmitted on PC7, PD7, PD2, or PE7, and can be received on PD2 or PE2.
NOTE: When Serial Port C is used as a clocked serial port, the parallel port pin used to transmit the serial clock will not be available for other use.
Serial Port D can transmit on parallel port pins PC1 or PC0, and can receive on pins PC1, PD1, or PE1. If the clocked serial mode is enabled, the serial clock can be transmitted on PC3, PD3, PD0, or PE3, and can be received on PD0 or PE0.
NOTE: When Serial Port D is used as a clocked serial port, the parallel port pin used to transmit the serial clock will not be available for other use. Table 17-2. Pin Usage Serial Ports A D
Function Transmit Receive Transmit Clock Receive Clock Serial Port A PC7, PC6, PD6 PC7, PD7, PE7 PB1 PB1 Serial Port B PC5, PC4, PD4 PC5, PD5, PE5 PB0 PB0 Serial Port C PC3, PC2 PC3, PD3, PE3 PC7, PD7, PD2, PE7, PH7 PD2, PE2 Serial Port D PC1, PC0 PC1, PD1, PE1 PC3, PD3, PD0, PE3, PH3 PD0, PE0
17.2.2 Clocks The data clocks for Serial Ports A D are based on the peripheral clock and are divided by either a Timer A divider or a dedicated 15-bit divider. In either case, the overall clock divider will be the value in the appropriate register plus one.
175
17.2.3 Other Registers

Register TAT4R TAT5R TAT6R TAT7R Function Time constant for Serial Port A Time constant for Serial Port B Time constant for Serial Port C Time constant for Serial Port D
PCFR, PCAHR, PCALR PDFR, PDAHR, PDALR Alternate port output selection PEFR, PEAHR, PEALR
17.2.4 Interrupts A serial port interrupt can be generated whenever one of the following occurs. A byte is available in the receive buffer. A byte is moved from the transmit buffer to the transmitter. A byte has been sent out of the transmitter and the transmit buffer is empty. These occurrences correspond to bits 2, 3, and 7 of the Serial Port Status Registers. The serial port interrupt vectors are located in the IIR as follows. Serial Port A at offset 0x0C0 Serial Port B at offset 0x0D0 Serial Port C at offset 0x0E0 Serial Port D at offset 0x0F0 Each of them can be set as Priority 1, 2, or 3 in SxCR, where x is A D for the four serial ports.
176
17.3 Operation
TIP: Remember to set up the serial port bits before commanding the serial port to send or receive any data.
17.3.1 Asynchronous Mode The following steps explain how to set up Serial Ports A D for asynchronous operation. The serial ports can be used by polling the status byte, but their performance will be better with an interrupt. These instructions also apply to the asynchronous operation of Serial Ports E F. 1. Write the interrupt vector for the interrupt service routine to the internal interrupt table. 2. Set up the desired transmit pin by writing to the appropriate parallel port function register (PxFR) and alternate output register (PxALR or PxAHR). 3. Select the appropriate mode by writing to SxCR (receive input port and 7 or 8 bits). Also select the interrupt priority. 4. Select additional options by writing to SxER (parity, RZI encoding, clock polarity, and behavior during break). 5. Write the desired divider value to TATxR for the appropriate serial port, or else write a divider value to the dedicated 15-bit divider in SxDLR and SxDHR. If the dedicated divider is to be used, write a 1 to the most-significant bit of SxDHR to enable it. A sample asynchronous serial interrupt handler is shown below for Serial Port A.
async_sera_isr:: push af ioi ld a, (SASR) bit 7,a push af jr z, check_for_tx rx_ready: ioi ld a, (SADR) ; ; ; ; save used registers get status check if byte ready in RX buffer save status for next check
; read byte and clear interrupt
; do something with byte here check_for_tx: pop af bit 3,a jr nz, done
; check if TX buffer was emptied
; get next byte to be transmitted into A here ioi ld (SADR), a done: pop af ipres ret ; load next byte into TX buffer and clear interrupt ; restore used registers
To transmit with an address (1) bit appended, write the data to SxAR instead of SxDR; to append a stop (0) bit write to SxLR instead.
Chapter 17 Serial Ports A D 177
17.3.2 Clocked Serial Mode The following steps explain how to set up Serial Ports A D for the clocked serial mode. When the internal clock is selected, the Rabbit 5000 is in control of all transmit and receive operations. When an external clock is selected the other device controls all transmit and receive operation. For both situations the decision between polling and interruptdriven methods is application dependent. 1. Write the interrupt vector for the interrupt service routine to the internal interrupt table. 2. Set up the desired data transmit and clock pins by writing to the appropriate parallel port function register (PxFR) and alternate output register (PxALR or PxAHR). 3. Select the appropriate mode by writing to SxCR (receive input port and clock source). Also select the interrupt priority. 4. Select additional options by writing to SxER (clock polarity, bit order, and clock source if external). 5. Write the desired divider value to TATxR for the appropriate serial port, or else write a divider to the dedicated 15-bit divider in SxDLR and SxDHR. If the dedicated divider is to be used, write a 1 to the most-significant bit of SxDHR to enable it. 6. There are two methods to transfer a byte: write the byte to SxDR and then write 10 (or 11) to bits 6-7 of SxCR to enable the transfer; write the byte to SxAR which will automatically start the transfer. If the internal clock is selected, the transmission will begin immediately; if an external clock is selected, the transmission will begin when the clock is detected. 7. There are two methods to receive a byte: write 01 to bits 67 of SxCR to start the receive operation; read the byte from SxAR which will automatically start the transfer based on whether an internal or an external clock was selected. If the internal clock is selected, the clock will begin immediately and the data will be read; if an external clock is selected, the receive will occur when the clock is detected.
178
A sample clocked serial interrupt handler is shown below for Serial Port B.
clocked_serb_isr:: push af ioi ld a, (SBSR) bit 7,a push af jr z, check_for_tx rx_ready: ioi ld a, (SBDR) ; ; ; ; save used registers get status check if byte ready in RX buffer save status for next check
; read byte and clear interrupt
; do something with received byte here ld a, 0x4D ; ; ; ; set bits 6-7 to 01, the other bits should represent the desired SBCR setup (Parallel Port C, internal clock, Interrupt Priority 1 in this example)
ioi ld (SBCR), a check_for_tx: pop af bit 3,a jr nz, done
; start a new receive operation
; get next byte to be transmitted into Register A here ioi ld (SBDR), a ; load TX buffer with next byte and clear interrupt done: pop af ; restore used registers ipres ret
179

Serial Port x Data Register (SADR) (SBDR) (SCDR) (SDDR) Description Returns the contents of the receive buffer. Loads the transmit buffer with a data byte for transmission. (Address = 0x00C0) (Address = 0x00D0) (Address = 0x00E0) (Address = 0x00F0)
Bit(s) 7:0
Value Read Write
Serial Port x Address Register
(SAAR) (SBAR) (SCAR) (SDAR) Description
Bit(s) 7:0
Value Read
Returns the contents of the receive buffer. Reading the data from this register in the clocked serial mode automatically causes the receiver to start a byte-receive operation, eliminating the need for software to issue the start-receive command. Loads the transmit buffer with an address byte, marked with a zero address bit, for transmission. Writing the data to this register in the clocked serial mode causes the transmitter to start a byte-transmit operation, eliminating the need for the software to issue the start-transmit command.
Write
Serial Port x Long Stop Register
(SALR) (SBLR) (SCLR) (SDLR) Description
Bit(s) 7:0
Value Read Write
Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a one address bit, for transmission.
180
Serial Port x Status Register (Asynchronous Mode Only)
(SASR) (SBSR) (SCSR) (SDSR) Description
Bit(s) 7
Value 0 1
The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. The byte in the receive buffer is data, received with a valid stop bit. The byte in the receive buffer is an address, or a byte with a framing error. If an address bit is not expected, and the data in the buffer is all zeros, this is a break. The receive buffer was not overrun. The receive buffer was overrun. This bit is cleared by reading the receive buffer. The byte in the receive buffer has no parity error (or was not checked for parity). The byte in the receive buffer had a parity error. The transmit buffer is empty. The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register. The transmitter is idle. The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in the asynchronous mode.
0 1
0 1
0 1
0 1
1:0
00
181
Serial Port x Status Register (Clocked Serial Mode Only)
(SASR) (SBSR) (SCSR) (SDSR) Description
Bit(s) 7
Value 0 1
The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. This bit is always zero in the clocked serial mode. The receive buffer was not overrun. The receive buffer was overrun. This bit is cleared by reading the receive buffer. This bit is always zero in the clocked serial mode. The transmit buffer is empty. The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register. The transmitter is idle. The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in the clocked serial mode.
6 5
0 0 1
4 3
0 0
0 1
1:0
00
182
Bit(s) 7:6
Value 00 01 10 11
5:4
00 01 10 11
3:2
00 01 10 11
1:0
00 01 10 11
183
Serial Port x Extended Register (Asynchronous Mode Only)
(SAER) (SBER) (SCER) (SDER) Description
Bit(s) 7:5
Value 000 001 010 011 100 101 110 111
Disable parity generation and checking. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. Enable parity generation and checking with even parity. Enable parity generation and checking with odd parity. Enable parity generation and checking with space (always zero) parity. Enable parity generation and checking with mark (always one) parity. Normal asynchronous data encoding. Enable RZI coding (3/16 bit cell IrDA-compliant). Normal break operation. This option should be selected when address bits are expected. Fast break termination. At the end of break, a dummy character is written to the buffer, and the receiver can start character assembly after one bit time. Asynchronous clock is 16 data rate. Asynchronous clock is 8 data rate. Continue character assembly during break to allow timing the break condition. Inhibit character assembly during break. One character (all zeros, with framing error) at start and one character (garbage) at completion. This bit is ignored in the asynchronous mode.
0 1
0 1
0 1
0 1
184
Serial Port x Extended Register (Clocked Serial Mode Only)
(SAER) (SBER) (SCER) (SDER) Description
Bit(s) 7
Value 0 1 Normal clocked serial operation.
Timer-synchronized clocked serial operation. Timer-synchronized clocked serial uses Timer B1. Timer-synchronized clocked serial uses Timer B2. Normal clocked serial clock polarity, inactive high. Internal or external clock. Normal clocked serial clock polarity, inactive low. Internal clock only. Inverted clocked serial clock polarity, inactive low. Internal or external clock. Inverted clocked serial clock polarity, inactive high. Internal clock only. Normal bit order (LSB first) for transmit and receive. Reverse bit order (MSB first) for transmit and receive. Serial clock (input mode only) from Parallel Port D (SCER and SDER only). Serial clock (input mode only) from Parallel Port E (SCER and SDER only). No effect on transmitter. Terminate current clocked serial transmission. No effect on buffer. No effect on receiver. Terminate current clocked serial reception.
0 1
5:4
00 01 10 11
0 1
0 1
0 1
0 1
Serial Port x Divider Low Register
(SADLR) (SBDLR) (SCDLR) (SDDLR) Description
Bit(s) 7:0
Value
Eight LSBs of the divider that generates the serial clock for this channel. This divider is not used unless the MSB of the corresponding SxDHR is set to one.
185
Serial Port x Divider High Register
(SADHR) (SBDHR) (SCDHR) (SDDHR) Description
Bit(s) 7
Value 0 1
Disable the serial port divider and use the output of Timer A to clock the serial port. Enable the serial port divider, and use its output to clock the serial port. The serial port divider counts modulo n + 1 and is clocked by the peripheral clock. Seven MSBs of the divider that generates the serial clock for this channel.
6:0
186
18. SERIAL PORTS E F

18.1 Overview
Serial Ports E and F are identical to each other, and their asynchronous operation is identical to that of Serial Ports A D except for the source of the data clock, the buffer sizes, and the transmit, receive, and clock pins. Each serial port can be used in the asynchronous or the HDLC mode with an internal or external clock. In the asynchronous mode, either 7 or 8 data bits can be transferred, and both a parity bit and/or ninth data bit can be appended as well. Parity and the ninth data bits are also detected when they are received. The asynchronous mode is full-duplex. The transmit and receive buffers of Serial Ports E and F have 4 bytes each; this reduces the interrupt overhead requirements because an interrupt does not have to be generated as often. A serial port interrupt is generated whenever at least one byte is available in the receive buffer or whenever a byte is shifted out of the transmit buffer. The status of each serial port is available in its Serial Port Status Register (SxSR), and contains information on whether a received byte is available, the receive buffer was overrun, a parity error was received, the transmit buffer is empty or busy sending a byte, and the state of the ninth data bit (whether it is an address bit or a stop bit). Serial Ports E and F support the HDLC mode with either an internal or an external clock; separate pins may be used for the transmit and receive clocks, or the transmit and receive clocks may be combined onto a single pin. The HDLC packet flag encapsulation, flag escapes, and CRC calculation and check are handled automatically by the processor. The serial port can detect end-of-frame, short-frame, and CRC errors. Interrupts are generated by the reception of an end-of-frame, at the end of a transmission of a CRC, by an abort sequence, or by a closing flag. Transmit and receive operations are essentially automatic. The standard CRC-CCITT polynomial (x16 + x12 + x5 + 1) is implemented for the CRC, with the generator and checker preset to all ones. It is possible to send packets with or without a CRC appended. It is also possible to select whether an abort or flag will be transmitted if the transmitter underflows. A packet under transition can be aborted and the abort pattern sent. The idle condition of the line can be flags or all ones. Several types of data encoding are available in HDLC mode: NRZ, NRZI, biphase-level (Manchester), biphase-space (FM0), and biphase-mark (FM1). IrDA-compliant RZI
Chapter 18 Serial Ports E F 187
encoding is also available in HDLC mode; it reduces the bit widths to the normal width, which allows the serial-port signal to be connected directly to an IrDA transceiver. If an internal clock is selected, the serial port data clocks can be generated from the appropriate 8-bit timer (Timer A2 for Serial Port E and Timer A3 for Serial Port F) or from a dedicated 15-bit divider. In HDLC mode, the bit data rate is equal to the data clock rate divided by 16. When using an external clock, a 1 (same speed as the data rate) clock is supported. In this case, the maximum data rate is 1/6 of the peripheral clock rate. The receive clock is generated from the transitions in the data stream via a digital phase-locked loop (DPLL). The timing of this synchronization is adjusted with each incoming transition, allowing for tracking if the two external clocks differ slightly in frequency. For more on the clock synchronization and data encoding, see Section 18.3.3. 18.1.1 Block Diagram
Serial Ports EF Peripheral Clock SxDHR 15-bit Divider SxDHR SxDLR Timer Ax Output Serial Data Clock Serial Port Control SxCR SxER
Rx Pins
Rx Buffer (4 bytes)
Latched Rx Buffer SxDR SxAR SxLR Latched Tx Buffer SxDR SxAR SxLR Serial Port Status SxSR Interrupt Request Tx Buffer (4 bytes)
Tx Pins
188
18.1.2 Registers
Register Name Serial Port E Data Register Serial Port E Address Register Serial Port E Long Stop Register Serial Port E Status Register Serial Port E Control Register Serial Port E Extended Register Serial Port E Divider Low Register Serial Port E Divider High Register Serial Port F Data Register Serial Port F Address Register Serial Port F Long Stop Register Serial Port F Status Register Serial Port F Control Register Serial Port F Extended Register Serial Port F Divider Low Register Serial Port F Divider High Register Mnemonic SEDR SEAR SELR SESR SECR SEER SEDLR SEDHR SFDR SFAR SFLR SFSR SFCR SFER SFDLR SFDHR I/O Address 0x00C8 0x00C9 0x00CA 0x00CB 0x00CC 0x00CD 0x00CE 0x00CF 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF R/W R/W W W R R/W R/W R/W R/W R/W W W R R/W R/W R/W R/W Reset xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 0xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0xx00000 xx000000 00000000 xxxxxxxx 0xxxxxxx
Chapter 18 Serial Ports E F
189
18.2 Dependencies
18.2.1 I/O Pins Serial Port E can transmit on parallel port pins PC6, PD6, PE6, or PH6, and can receive on pins PC7, PD7, or PE7. If the HDLC mode is enabled, the transmit serial clock is either transmitted or received on PC4, PD4, or PE4, while the receive serial clock is either transmitted or received on PC5, PD5, or PE5. The transmit and receive clocks can also be transmitted on PH4 or PH0 if internal clock mode is enabled. Serial Port F can transmit on parallel port pins PC2, PD2, PE2, or PH2, and can receive on pins PC3, PD3, or PE3. If the HDLC mode is enabled, the transmit serial clock is either transmitted or received on PC0, PD0, or PE0, while the receive serial clock is either transmitted or received on PC1, PD1, or PE1. The transmit and receive clocks can also be transmitted on PH5 or PH1 if internal clock mode is enabled.
Table 18-1. Serial Ports E and F Pin Usage
Function Transmit Receive Transmit Clock Receive Clock Serial Port E PC6, PD6, PE6, PH6 PC7, PD7, PE7 PC4, PD4, PE4, PH4 PC5, PD5, PE5, PH5 Serial Port F PC2, PD2, PE2, PH2 PC3, PD3, PE3 PC0, PD0, PE0, PH0 PC1, PD1, PE1, PH1
18.2.2 Clocks The data clocks for Serial Ports E F are based on the peripheral clock and divided by either a Timer A divider or a dedicated 15-bit divider. In either case, the overall clock divider will be the value in the appropriate register plus one. 18.2.3 Other Registers
Register TAT2R TAT3R Function Time constant for Serial Port E Time constant for Serial Port F
PCFR, PCAHR, PCALR PDFR, PDAHR, PDALR Alternate port output selection PEFR, PEAHR, PEALR PHFR, PHAHR, PHALR
190
18.2.4 Interrupts In the asynchronous mode, a serial port interrupt can be generated whenever one of the following occurs. A byte is available in the receive buffer. A byte is moved from the transmit buffer to the transmitter. A byte has been sent out of the transmitter and the transmit buffer is empty. These occurrences correspond to bits 2, 3, and 7 of the Serial Port Status Registers. In the HDLC mode, interrupts are also generated by the reception of an end-of-frame (with abort, valid CRC, or CRC error), at the end of a transmission of a CRC, by an abort sequence, or by a closing flag. The serial port interrupt vectors are located in the IIR as follows. Serial Port E at offset 0x1C0 Serial Port F at offset 0x1D0 Each of them can be set as Priority 1, 2, or 3 in SxCR, where x is E F for the two serial ports.
191
18.3 Operation
TIP: Remember to set up the serial port bits before commanding the serial port to send or receive any data.
18.3.1 Asynchronous Mode The steps to set up Serial Ports E F for asynchronous operation are identical to those described in Section 17.3.1 to set up Serial Ports A D. 18.3.2 HDLC Mode The following steps explain how to set up Serial Ports E F for the HDLC mode. 1. Write the interrupt vector for the interrupt service routine to the internal interrupt table. 2. Set up the desired data transmit and clock pins by writing to the appropriate parallel port function register (PxFR) and alternate output register (PxALR or PxAHR). 3. Select the appropriate mode by writing to SxCR (receive input port and clock source). Also select the interrupt priority. 4. Select additional options by writing to SxER (data encoding, idle line condition, underrun behavior, and combined or separate clocks). 5. Write the desired divider value to TATxR for the appropriate serial port, or else write a divider to the dedicated 15-bit divider in SxDLR and SxDHR. If the dedicated divider is to be used, write a 1 to the most-significant bit of SxDHR to enable it. In either case, the overall clock divider will be the value in the appropriate register plus one. 6. To start transmission of a packet, write the first byte to SxDR. If internal clock is selected, the transmission will begin immediately; if an external clock is selected the transmission will begin when the clock is detected. 7. Continue writing bytes when space is available in the transmit buffer until the final byte of the packet. If a CRC is to be appended to the packet, write the final byte to SxAR. If no CRC is required, write the final byte to SxLR and just a closing flag will be appended. If it is desirable to abort the current packet, write 11 to bits 67 of SxCR, and an abort pattern will be transmitted. 8. The receiver will be synchronized on flag bytes and will reset the CRC. By monitoring the received bytes, decisions can be made about the incoming packet; if it is not desired (i.e., it is not addressed to this device), writing a 01 to bits 67 of SxCR will force the receiver back into the flag search mode.
192
A sample HDLC interrupt handler is shown below for Serial Port E.

hdlc_sere_isr:: push af ioi ld a, (SESR) ; get status bit 7,a ; check if byte ready in RX buffer push af ; save status for next check jr z, check_for_tx rx_ready: ; check status byte in A for abort or invalid CRC flags ioi ld a, (SEDR) ; read byte and clear interrupt
; store byte in A here check_for_tx: pop af bit 3,a jr nz, done
; check status byte in A for transmit finish reason (CRC, abort, etc.) ; get next byte to be transmitted into A here; if it is the last ; byte of the packet, load it into SEAR or SELR instead ioi ld (SEDR), a done: pop af ipres ret ; load next byte into buffer and clear interrupt
18.3.3 More on Clock Synchronization and Data Encoding The transmitter is not capable of sending an arbitrary number of bits, but only a multiple of bytes. However, the receiver can receive frames of any bit length. If the last byte in the frame is not eight bits, the receiver sets a status flag that is buffered along with this last byte. Software can then use the table below to determine the number of valid data bits in this last byte. Note that the receiver transfers all bits between the opening and closing flags, except for the inserted zeros, to the receiver data buffer.
Last Byte Bit Pattern bbbbbbb0 bbbbbb01 bbbbb011 bbbb0111 bbb01111 bb011111 b0111111
Valid Data Bits 7 6 5 4 3 2 1

193
Several types of data encoding are available in the HDLC mode. In addition to the normal NRZ, they are NRZI, biphase-level (Manchester), biphase-space (FM0), and biphasemark (FM1). Examples of these encodings are shown below. Note that the signal level does not convey information in NRZI, biphase-space, and biphase-mark. Instead it is the placement of the transitions that determine the data. In biphase-level it is the polarity of the transition that determines the data.
SERIAL CLOCK NRZ DATA NRZI NRZI BIPHASE LEVEL BIPHASE SPACE BIPHASE SPACE BIPHASE MARK BIPHASE MARK DATA
1 0 1 1 0 0 1 0
Figure 18-1. Examples of Data Encoding In the HDLC Mode
In the HDLC mode the internal clock comes from the output of Timer A2/Timer A3 or the dedicated divider. The timer/divider output is divided by 16 to form the transmit clock, and is fed to the digital phase-locked loop (DPLL) to form the receive clock. The DPLL is basically just a divide-by-16 counter that uses the timing of the transitions on the receive data stream to adjust its count. The DPLL adjusts the count so that the DPLL output will be properly placed in the bit cells to sample the receive data. To work properly, then, transitions are required in the receive data stream. NRZ data encoding does not guarantee transitions in all cases (a long string of zeros, for example), but the other data encodings do. NRZI guarantees transitions because of the inserted zeros, and the biphase encodings all have at least one transition per bit cell. The DPLL counter normally counts by 16, but if a transition occurs earlier or later than expected, the count will be modified during the next count cycle. If the transition occurs earlier than expected, it means that the bit cell boundaries are early with respect to the DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If the transition occurs later than expected, it means that the bit-cell boundaries are late with
respect to the DPLL-tracked bit-cell boundaries, so the count is lengthened by either one or two counts. The decision to adjust by one or by two depends on how far off the DPLLtracked bit cell boundaries are. This tracking allows for minor differences in the transmit and receive clock frequencies. With NRZ and NRZI data encoding, the DPLL counter runs continuously, and adjusts after every receive data transition. Since NRZ encoding does not guarantee a minimum density of transitions, the difference between the sending data rate and the DPLL output clock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding guarantees at least one transition every six bits (with the inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/48 (~2%). With biphase data encoding (either biphase-level, biphase-mark, or biphase-space), the DPLL runs only as long as transitions are present in the receive data stream. Two consecutive missed transitions causes the DPLL to halt operation and wait for the next available transition. This mode of operation is necessary because it is possible for the DPLL to lock onto the optional transitions in the receive data stream. Since they are optional, they will eventually not be present, and the DPLL can attempt to lock onto the required transitions. Since the DPLL can adjust by one count every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/16 (~6%). With biphase data encoding, the DPLL is designed to work in multiple-access conditions where there might not be flags on an idle line. The DPLL will generate an output clock correctly based on the first transition in the leading zero of an opening flag. Similarly, only the completion of the closing flag is necessary for the DPLL to provide the extra two clocks to the receiver to assemble the data correctly. The transition is specified as follows. In the biphase-level mode this means the transition that defines the last zero of the closing flag. In the biphase-mark and the biphase-space modes this means the transition that defines the end of the last zero of the closing flag.
195
Figure 18-2 shows the adjustment ranges and output clock for the different modes of operation of the DPLL. Each mode of operation will be described in turn.
BIT CELL NRZI adj NONE NRZI CLOCK BIPHASE LEVEL adj BIPHASE LEVEL CLOCK BIPHASE SPACE adj NONE BIPHASE SPACE CLOCK BIPHASE MARK adj NONE BIPHASE MARK CLOCK
Figure 18-2. Adjustment Ranges and Output Clock for Different DPLL Modes
ADD ONE IGNORE TRANSITIONS SUBTRACT NONE ONE ADD ONE IGNORE TRANSITIONS SUBTRACT NONE ONE IGNORE SUBTRACT NONE ADD ONE IGNORE TRANSITIONS ONE TRANSITIONS ADD ONE ADD TWO SUBTRACT TWO SUBTRACT NONE ONE
With NRZ and NRZI encoding, all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell. If a transition occurs after the expected bitcell boundary (but before the midpoint), the DPLL needs to lengthen the count to line up the bit-cell boundaries. This corresponds to the add one and add two regions shown. If a transition occurs before the bit-cell boundary (but after the midpoint), the DPLL needs to shorten the count to line up the bit-cell boundaries. This corresponds to the subtract one and subtract two regions shown. The DPLL makes no adjustment if the bit-cell boundaries are lined up within one count of the divide-by-16 counter. The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up. With biphase-level encoding, there is a guaranteed clock transition at the center of every bit cell and optional data transitions occur at the bit cell boundaries. The DPLL only uses the clock transitions to track the bit-cell boundaries by ignoring all transitions occurring outside a window around the center of the bit cell. This window is half a bit cell wide. Additionally, because the clock transitions are guaranteed, the DPLL requires that they always be present. If no transition is found in the window around the center of the bit cell for two successive bit cells, the DPLL is not in lock and immediately enters the search mode. The search mode assumes that the next transition seen is a clock transition and immediately synchronizes to this transition. No clock output is provided to the receiver during the search operation. Decoding biphase-level data requires that the data be sampled at either the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to sample the data.
Biphase-mark encoding and biphase-space encoding are identical as far as the DPLL is concerned, and are similar to biphase-level encoding. The primary difference is the placement of the clock and data transitions. With these encodings the clock transitions are at the bit-cell boundary, the data transitions are at the center of the bit cell, and the DPLL operation is adjusted accordingly. Decoding biphase-mark or biphase-space encoding requires that the data be sampled by both edges of the recovered receive clock.

Serial Port x Data Register Bit(s) 7:0 Value Read Write (SEDR) (SFDR) Description Returns the contents of the receive buffer. Loads the transmit buffer with a data byte for transmission. (Address = 0x00C8) (Address = 0x00D8)
Serial Port x Address Register Bit(s) 7:0 Value Read Write
(SEAR) (SFAR) Description
(Address = 0x00C9) (Address = 0x00D9)
Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a zero address bit, for transmission. In the HDLC mode, the last byte of a frame must be written to this register to enable subsequent CRC and closing flag transmission.
Serial Port x Long Stop Register Bit(s) 7:0 Value Read Write
(SELR) (SFLR) Description
(Address = 0x00CA) (Address = 0x00DA)
Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a one address bit, for transmission.
197
Serial Port x Status Register (Asynchronous Mode Only) Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0
(SESR) (SFSR) Description
(Address = 0x00CB) (Address = 0x00DB)
The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. The byte in the receive buffer is data, received with a valid stop bit. The byte in the receive buffer is an address, or a byte with a framing error. If an address bit is not expected, and the data in the buffer is all zeros, this is a break. The receive buffer was not overrun. The receive buffer was overrun. This bit is cleared by reading the receive buffer. The byte in the receive buffer has no parity error (or was not checked for parity). The byte in the receive buffer had a parity error. The transmit buffer is empty. The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register. The transmitter is idle. The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in the asynchronous mode.
0 1
1:0
00
198
Serial Port x Status Register (HDLC Mode Only) Bit(s) 7 Value 0 1 6,4 00 01 10 11 5 0 1 3 0
(SESR) (SFSR) Description
(Address = 0x00CB) (Address = 0x00DB)
The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. The byte in the receive buffer is data. The byte in the receive buffer was followed by an abort. The byte in the receive buffer is the last in the frame, with valid CRC. The byte in the receive buffer is the last in the frame, with a CRC error. The receive buffer was not overrun. The receive buffer was overrun. This bit is cleared by reading the receive buffer. The transmit buffer is empty. The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer, unless the byte is marked as the last in the frame. Transmit interrupts are cleared when the transmit buffer is written, or when any value (which will be ignored) is written to this register. Transmit interrupt due to buffer empty condition. Transmitter finished sending CRC. An interrupt is generated at the end of the CRC transmission. Data written in response to this interrupt will cause only one flag to be transmitted between frames, and no interrupt will be generated by this flag. Transmitter finished sending an abort. An interrupt is generated at the end of an abort transmission. The transmitter finished sending a closing flag. Data written in response to this interrupt will cause at least two flags to be transmitted between frames. The byte in the receiver buffer is 8 bits. The byte in the receiver buffer is less than 8 bits.
2:1
00
01
10 11 0 0 1
199
Serial Port x Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10
(SECR) (SFCR) Description
(Address = 0x00CC) (Address = 0x00DC)
No operation. These bits are ignored in the asynchronous mode. In HDLC mode, force receiver in flag search mode. No operation. In HDLC mode, transmit an abort pattern. Parallel Port C is used for data (and optional clock) input. Parallel Port D is used for data (and optional clock) input. Parallel Port E is used for data (and optional clock) input. Disable the receiver data input. Clocks from Parallel Port E. Asynchronous mode with 8 bits per character. Asynchronous mode with 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data. HDLC mode with external clock. The external clocks are supplied via parallel port pins. HDLC mode with internal clock. The clock is 16 the data rate, and the DPLL is used to recover the receive clock. If necessary, the receiver and transmitter clocks can be output via parallel port pins. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3.
11 1:0 00 01 10 11
200
Serial Port x Extended Register (Asynchronous Mode Only) Bit(s) 7:5 Value 000 001 010 011 100 101 110 111 4 0 1 3 0 1 2 0 1 1 0 1 0
(SEER) (SFER) Description
(Address = 0x00CD) (Address = 0x00DD
Disable parity generation and checking. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. Enable parity generation and checking with even parity. Enable parity generation and checking with odd parity. Enable parity generation and checking with space (always zero) parity. Enable parity generation and checking with mark (always one) parity. Normal asynchronous data encoding. Enable RZI coding (3/16 bit cell IrDA-compliant). Normal break operation. This option should be selected when address bits are expected. Fast break termination. At the end of break, a dummy character is written to the buffer, and the receiver can start character assembly after one bit time. Asynchronous clock is 16 data rate. Asynchronous clock is 8 data rate. Continue character assembly during break to allow timing the break condition. Inhibit character assembly during break. One character (all zeros, with framing error) at start and one character (garbage) at completion. This bit is ignored in the asynchronous mode.
201
Serial Port x Extended Register (HDLC Mode Only) Bit(s) 7:5 Value 000 010 100 110 111 4 0 1 3 0 1 2 0 1 1 0 1 0
(SEER) (SFER) Description
(Address = 0x00CD) (Address = 0x00DD)
NRZ data encoding for HDLC receiver and transmitter. NRZI data encoding for HDLC receiver and transmitter. Biphase-level (Manchester) data encoding for HDLC receiver and transmitter. Biphase-space data encoding for HDLC receiver and transmitter. Biphase-mark data encoding for HDLC receiver and transmitter. Normal HDLC data encoding. Enable RZI coding ( bit cell IrDA-compliant). This mode can only be used with an internal clock and NRZ data encoding. Idle line condition is flags. Idle line condition is all ones. Transmit flag on underrun. Transmit abort on underrun. Separate HDLC external receive and transmit clocks. Combined HDLC external and transmit clock, from transmit clock pin. This bit is ignored in HDLC mode.
Serial Port x Divider Low Register Bit(s) 7:0 Value
(SEDLR) (SFDLR) Description
(Address = 0x00CE) (Address = 0x00DE)
Eight LSBs of the divider that generates the serial clock for this channel. This divider is not used unless the MSB of the corresponding SxDHR is set to one.
Serial Port x Divider High Register Bit(s) 7 Value 0 1 6:0
(SEDHR) (SFDHR) Description
(Address = 0x00CF) (Address = 0x00DF)
Disable the serial port divider and use the output of Timer A to clock the serial port. Enable the serial port divider, and use its output to clock the serial port. The serial port divider counts modulo n + 1 and is clocked by the peripheral clock. Seven MSBs of the divider that generates the serial clock for this channel.
202
19. SLAVE PORT

19.1 Overview
The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output registers, and a status register. The data input registers are written by the master (the external device) and are read by the processor. The data output registers are written by the processor and are read by the master. Note that the data registers are named from the point of view of the processor. The slave device can only read the data input registers and write to the data output registers. Similarly, the master device can only read the data input registers and write the data output registers. Both devices can read and write to the status register. The status register contains the interrupt status bits and a status flag corresponding to each data input or data output register to indicate the empty or full status of the data register. Data registers are marked full when written by the source side of the interface, and are marked empty when read by the destination side of the interface. The hardware interface to the external master consists of an 8-bit bidirectional data bus with a read strobe, write strobe, and chip select. There are two address lines that select one of the three data registers or the status register.
Table 19-1. Slave Port Addresses
Slave Port Address 00 01 10 11 Slave Port Register Data Register 0 Data Register 1 Data Register 2 Status Register
A slave attention signal is asserted when the processor writes to one of the slave port data registers (SPD0R), and can be deasserted by the master by performing a dummy write to the status register. This signal can be used to interrupt the master to indicate that the master needs to read data from the slave. The slave port interrupt is asserted when the master writes to SPD0R. The processor clears this interrupt condition by writing to the status register.
Chapter 19 Slave Port 203
The slave port can be used to bootstrap the processor by setting the SMODE pins appropriately. See Chapter 3 for more information on this mode. 19.1.1 Block Diagram
Slave Port Slave ATTN Request SPCR Interrupt Generation SPCR Interrupt Request
/SLVATTN
SD0SD7 SA0SA1 /SRD /SWR /SCS Bus Interface
SPD0R Processor SPD1R
SPD2R
SPSR
19.1.2 Registers
Register Name Slave Port Data 0 Register Slave Port Data 1 Register Slave Port Data 2 Register Slave Port Status Register Slave Port Control Register Mnemonic SPD0R SPD1R SPD2R SPSR SPCR I/O Address 0x0020 0x0021 0x0022 0x0023 0x0024 R/W R/W R/W R/W R R/W Reset xxxxxxxx xxxxxxxx xxxxxxxx 00000000 0xx00000
204
19.2 Dependencies
19.2.1 I/O Pins When the slave port is enabled by writing to SPCR, the following pins are enabled for slave port mode. Note that enabling the slave port mode will override any general-purpose I/O or external I/O bus settings for these pins; when the slave port is enabled they will perform slave port functionality.
Table 19-2. Slave Port Pin Functionality
Pin(s) PA0PA7 PB7 PB6 PB4PB5 PB3 PB2 PE7 Slave Port Signal SD0SD7 /SLVATTN /SCS SA0SA1 /SRD /SWR /SCS Direction Bidirectional Slave data bus Output Input Input Input Input Input Slave interrupt request (output) Slave chip select Slave address bus Slave port read strobe Slave port write strobe Alternate slave chip select Functionality
19.2.2 Clocks All slave port operations are based on the processor clock. 19.2.3 Interrupts If slave port interrupts are enabled, a slave port interrupt will occur on the slave device whenever the master writes to SPD0R. The /SLVATTN pin is asserted whenever the slave device writes to SPD0R. Either if these conditions is cleared when either the master or slave reads or writes any of the slave port registers. The slave port interrupt vector is in the IIR at offset 0x080. It can be set as Priority 1, 2, or 3 by writing to SPCR.
Chapter 19 Slave Port
205
19.3 Operation
Figure 19-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves.
MASTER Rabbit
D0D7 /IORD /IOWR A0 A1 CLK PE0 (INT0) PD6 (I6) PE1 (INT1) PD7 (I7)
First SLAVE Rabbit

SD0SD7 /SRD /SWR SA0 SA1 /XTALB1 /SLAVEATTN /SCS
Second SLAVE Rabbit
/SLAVEATTN /SCS
Figure 19-1. Master/Slave Port Connections
206
These connections are summarized in Table 19-3.

Table 19-3. Typical Slave Port Connections
Master Data Bus Address Bus I/O Read Strobe I/O Write Strobe Slave #1 Chip Select (I/O strobe I6) Slave #2 Chip Select (I/O strobe I7) External Interrupt 0 (from Slave #1) External Interrupt 1 (from Slave #2) D0D7 A0A1 /IORD /IOWR PD6 PD7 PE0 PE1 Slave #1 SD0SD7 SA0SA1 /SRD /SWR /SCS /SLVATTN PA0PA7 PB4PB5 PB3 PB2 PB6 PB7 Slave #2 SD0SD7 SA0SA1 /SRD /SWR /SCS /SLVATTN PA0PA7 PB4PB5 PB3 PB2 PB6 PB7
Note that the slave port on the master Rabbit processor is not used; the master uses the data bus to send and receive data to the slave port data registers on the slave devices. In this setup, pins PD6 and PD7 are set up as I/O strobe chip selects for the two slave devices, and PE0 and PE1 are used as external interrupt inputs to monitor the /SLVATTN signals from the slaves. In this setup, the slave port is used as follows: The slave responds to the interrupt and reads the slave port data registers. When the slave wishes to send data to the master, it writes the slave port data registers, writing SPD0R last, which enables the /SLVATTN signal. When the master detects the change on /SLVATTN, it reads the slave port data registers. 19.3.1 Master Setup 1. Enable the I/O strobes on PD6 and PD7 by writing to the appropriate Parallel Port D pin and external I/O registers. 2. Enable the external interrupts on PE0 and PE1 by writing to the appropriate external interrupt registers. 19.3.2 Slave Setup 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Configure SPCR to select the interrupt priority (note that interrupts will be enabled once this value is set).
207
19.3.3 Master/Slave Communication 1. The master writes data to the appropriate external I/O address on the data bus for the slave device and register desired. For example, in the setup described here, the master would write to register SPD2R on the first slave by writing to the address 0xC002 (0xC000 for the I6 strobe, and 0x0002 for SPD2R on that slave). 2. If the master is writing multiple bytes, it should write to SPD0R last since that will trigger an interrupt on the slave device. If only one byte is being sent, it should be written to SPD0R. 3. The slave responds to the interrupt, reading the data from the slave port data registers. 19.3.4 Slave/Master Communication 1. The slave writes data to the appropriate slave port data register. If it is writing multiple bytes, SPD0R should be written last, which enables the /SLVATTN line. 2. The master receives an external interrupt from the /SLVATTN line, and reads the data out of the slave port data registers via external I/O reads on the data bus. 19.3.5 Handling Interrupts The interrupt request on the slave is cleared by either the master or the slave accessing one of the slave port registers. To clear the interrupt without affecting the register values, a dummy write can be made to SPSR. 19.3.6 Example ISR A sample interrupt handler is shown below.
slave_isr:: push af ; save used registers
; read the data sent by the master ioi ld a, (SPD2R) ld (to_slv_d2), a ioi ld a, (SPD1R) ld (to_slv_d1), a ioi ld a, (SPD0R) ld (to_slv_d0), a ; if a response is required, perform it here ld a, (to_mas_d2) ioi ld (SPD2R), a ld a, (to_mas_d1) ioi ld (SPD1R), a ld a, (to_mas_d0) ioi ld (SPD0R), a ; this write asserts /SLVATTN
; the interrupt request is cleared by any read/write of the registers pop af ipres ret ; restore used registers
208
19.3.7 Other Configurations There are other slave port configurations possible: The master could use the external I/O bus instead of the memory bus. All devices could poll the slave port status register to determine when data is present instead of relying on interrupts. The master could write to SPD0R, triggering an interrupt on the slave. The slave could then simply write a response into SPD0R, which the master detects by polling SPSR. This configuration is useful when fewer signals are desired, or the master device has no external interrupts available. If polling is to be used, it is important to note that not all bits in the status register may be updated at once; it is possible to read a transitional value as the register updates. To guarantee a proper polling read, the status register should be read twice; when the same value is read both times the value is correct. Similarly, it is possible to receive a scrambled value from a data register if it is read while being written. The protocol used should take account of this and prevent it from occurring (the protocol described above guarantees this will not occur).
209
19.3.8 Timing Diagrams Figure 19-2 shows the sequence of events when the master reads/writes the slave port registers.
Slave Port Read Cycle

/SCS
Tsu(SCS) Th(SCS)
SA1, SA0
Tsu(SA) Th(SA)
/SRD SD[7:0] /SWR

Ten(SRD) Ta(SRD) Tsu(SWR SRD)
Tw(SRD) Tdis(SRD)
Slave Port Write Cycle

/SCS
Tsu(SCS) Th(SCS)
SA1, SA0
Tsu(SA) Th(SA)
/SWR SD[7:0] /SRD
Tw(SWR) Th(SD) Tsu(SD) Tsu(SRD SWR)
Figure 19-2. Slave Port R/W Timing Diagram
210
The following table explains the parameters used in Figure 19-2.

Symbol Tsu(SCS) Th(SCS) Tsu(SA) Th(SA) Tw(SRD) Ten(SRD) Ta(SRD) Tdis(SRD) Parameter /SCS Setup Time /SCS Hold Time SA Setup Time SA Hold Time /SRD Low Pulse Width /SRD to SD Enable Time /SRD to SD Access Time /SRD to SD Disable Time Minimum (ns) 5 0 5 0 40 0 40 40 10 5 40 Maximum (ns) 30 15
Tsu(SRW SRD) /SWR High to /SRD Low Setup Time Tw(SWR) Tsu(SD) Th(SD) /SWR Low Pulse Width SD Setup Time SD Hold Time
Tsu(SRD SWR) /SRD High to /SWR Low Setup Time
211

Slave Port Data x Registers (SPD0R) (SPD1R) (SPD2R) Description The corresponding byte of the slave port is read. The corresponding byte of the slave port is written. (Address = 0x0020) (Address = 0x0021) (Address = 0x0022)
Bit(s) 7:0
Value Read Write
Slave Port Status Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 Processor wrote to SPSR.
(SPSR) Description
(Address = 0x0023)
Master wrote to Data Register 0. Slave port read byte 2 is empty. Slave port read byte 2 is full. Slave port read byte 1 is empty. Slave port read byte 1 is full. Slave port read byte 0 is empty. Slave port read byte 0 is full. Master wrote to SPSR. Processor wrote to SPD0R. Slave port write byte 2 is empty. Slave port write byte 2 is full. Slave port write byte 1 is empty. Slave port write byte 1 is full. Slave port write byte 0 is empty. Slave port write byte 0 is full.
212
(SPCR) Description
(Address = 0x0024)
213
214
20. ANALOG COMPONENTS

20.1 Overview
The Rabbit 5000 has a 10-bit single-channel A/D converter, a 10-bit two-channel differential-input A/D converter, and a 10-bit two-channel differential-output D/A converter for 802.11 Wi-Fi operation. These analog features are available for customer use when Wi-Fi is not being used. Table 20-1 summarizes the analog features.
Table 20-1. Analog Components
Component Number 0 Function A/D Converter Sampling Rate 10 kilosamples/s to 50 megasamples/s Description 2 channels, 10-bit, differential Continuous Operation 2 channels, 10-bit, differential Continuous Operation 1 channel, 10-bit, single-ended Convert on Signal Pin(s) VINIP + VININ VINQP + VINQN VOUTPI + VOUTNI VOUTPQ + VOUTNQ
D/A Converter
Up to 44 megasamples/s
A/D Converter
Up to 0.3 megasamples/s
VIN8
The actual conversion rates depend on the clock sources used each analog component can accept a clock from an external I/O pin or divide the peripheral clock by a value between 2 and 256.
Chapter 20 Analog Components
215
Table 20-2 lists the detailed features for each analog component.
Table 20-2. Analog Component Specifications
Analog Component Resolution Input Range Operating Current Active Standby Power down Transition Time Standby to active Power down to active Nonlinearity Differential (DNL) Integral (INL) Offset Error I to Q Offset Mismatch Gain Error I to Q Gain Mismatch Channel Isolation Resolution Input Range Allowed Common-Mode Voltage Operating Current Active Standby Power down 1 (fast D/A converter) Transition Time Standby to active Power down to active Offset Error I to Q Offset Mismatch Gain Error I to Q Gain Mismatch Channel Isolation Feature Specification 10 bits 2 Vpp (differential)
56 mA @ 1.8V, 20 mA @ 3.3V 2.5 mA @ 1.8 V 1 mA @ 1.8 V
0 (fast A/D converter)
4 s 1 ms
0.5 LSB typ. 1 LSB typ. 2% of full scale 1% of full scale 5% of full scale 1% of full scale
60 dB typ. 10 bits 2 Vpp (differential) 0.9 V to 1.4 V
22 mA @ 3.3 V < 1 mA @ 3.3 V < 1 A @ 1.8 V
2 s 6 s
2% of full scale 1% of full scale 5% of full scale 1% of full scale

60 dB typ.
216
Table 20-2. Analog Component Specifications (continued)

Analog Component Resolution Input Range Operating Current Active Standby 2 (slow A/D converter) Transition Time Standby to active Nonlinearity Differential (DNL) Integral (INL) Offset Error Gain Error Feature Specification 10 bits 0 V to 3.3 V
35 A @ 1.8 V, 62 A @ 3.3 V < 1 A @ 1.8 V, 3.3 V
15 s
1 LSB typ. 2 LSB max.

-1.5 to +2.5 LSB
2 LSB max
217
20.2 Block Diagram

Analog Components PD4 Fast A/D Converter Clock Select Peripheral Clock
VINIP VININ VINQP VINQN
Component 0 Fast A/D Converter A0ILR A0IMR A0QLR A0QMR A0CR
PD5
Fast D/A Converter Clock Select
VINIP VININ VINQP VINQN
Component 1 Fast D/A Converter A1ILR A1IMR A1QLR A1QMR A1CR
PD6
Slow A/D Converter Clock Select
VIN8
Component 2 Slow A/D Converter A2LR A2MR A2CR
218
20.2.1 Registers
Register Name Analog Component 0 I LSB Register Analog Component 0 I MSB Register Analog Component 0 Q LSB Register Analog Component 0 Q MSB Register Analog Component 0 Control Register Analog Component 1 I LSB Register Analog Component 1 I MSB Register Analog Component 1 Q LSB Register Analog Component 1 Q MSB Register Analog Component 1 Control Register Analog Component 2 LSB Register Analog Component 2 MSB Register Analog Component 2 Control Register Mnemonic A0ILR A0IMR A0QLR A0QMR A0CR A1ILR A1IMR A1QLR A1QMR A1CR A2LR A2MR A2CR I/O Address 0x0800 0x0801 0x0802 0x0803 0x0804 0x0810 0x0811 0x0812 0x0813 0x0814 0x0820 0x0821 0x0824 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 00000000
20.3 Dependencies
20.3.1 I/O Pins The fast A/D converter accepts differential input on the pin pairs VININ/VINIP and VINQN/VINQP. The VREFP, VREFN, ADVCM, and ADVBG pins should be connected as shown in the sample circuit diagrams. The IBIAS pin should remain unconnected. The fast D/A converter provides differential output on the pin pairs VOUTNI/VOUTPI and VOUTNQ/VOUTPQ. The DAVCM pin should be used to provide the common-mode voltage, which can range from 0.9 V to 1.4 V; see the sample circuit diagram for an example. DAVBG should be connected as shown in the sample circuit diagram. The slow ADC accepts a single input on the VIN8 pin. The PD4, PD5, and PD6 pins can be used instead of the peripheral clock as clock inputs for analog component 0, 1, or 2 respectively. 20.3.2 Clocks Each of the analog components can be clocked by the peripheral clock divided by 2, 4, 8, 16, 32, 64, 128, or 256, or by a clock input on PD4, PD5, or PD6, depending on the component. Exercise care when selecting the clock to keep the data rate below the maximum sample rate of the component you are configuring.
219
20.4 Operation
20.4.1 Fast A/D Converter The following steps must be taken to operate the fast A/D converter. 1. Select the clock source and enable the fast A/D converter by writing to A0CR. 2. Read the channel data in the A0IxR and A0QxR registers. Reading the least-significant bit registers first will lock the value in the most-significant bit register until it is read. 3. For faster update, an 8-bit value can be obtained by only reading the most-significant bit registers (A0IMR or A0QMR). 4. To reduce power consumption, the fast A/D converter can be put into a standby or sleep mode by writing to A0CR. 20.4.2 Fast D/A Converter The following steps must be taken to operate the fast D/A converter. 1. Select the clock source and enable the fast D/A converter by writing to A1CR. 2. Write the channel data to the A1IxR and A1QxR registers. Writing the least-significant bit registers first will hold the conversion output until the most-significant bit register is written. 3. For faster update, an 8-bit value can be output by only writing the most-significant bit registers (A1IMR or A1QMR). 4. To reduce power consumption, the fast D/A converter can be put into a standby or power-down mode by writing to A1CR. 20.4.3 Slow A/D Converter The following steps must be taken to operate the slow A/D converter. 1. Select the clock source and enable the slow A/D converter by writing to A2CR. 2. Start a conversion by writing to bit 2 of A2CR. 3. Monitor bit 3 of A2CR to determine when the conversion is complete, then read the data in the A2LR and A2MR registers. Reading the least-significant bit registers first will lock the value in the most-significant bit register until it is read. 4. For faster update, an 8-bit value can be obtained by only reading A2MR. 5. To reduce power consumption, the slow A/D converter can be put into a sleep mode by writing to A2CR.
220
20.5 Sample Circuits

Sample circuits are shown below for the analog components. Since each analog component has dedicated power and ground, be sure to allow enough filtering for each block as shown a range of ferrite beads may be used we obtained good results with ferrite beads rated at 120 at 100 MHz.
+1.8 V
Ferrite Bead 2.2 F 100 nF 100 nF
100 nF VDDI VSSI 100 nF AVDDI AGNDI AGNDREF 2.2 F 100 nF VDD33 A33GNDI AVDDI 100 nF AGNDI VREFP 2.2 F 100 nF RXQ RXQ+ not connected RXI RXI+ 100 nF
+3.3 V
Ferrite Bead
VINQP IBIAS VININ VINIP ADVCM ADVBG
100 nF
Figure 20-1. Sample Fast A/D Converter Circuit
+1.8 V
Ferrite Bead 2.2 F 100 nF VDDI GNDI AVDDI 2.2 F 100 nF AGNDI
+1.8 V 470 W DAVCM
+3.3 V
Ferrite Bead
FAST DAC
DAVBG 100 nF 2.2 F
1 kW
VOUTPI VOUTNQ VOUTPQ
TXI+ TXQ TXQ+
Figure 20-2. Sample Fast D/A Converter Circuit
ANALOG OUTPUTS
221
VOUTNI
TXI
ANALOG INPUTS
100 nF
FAST ADC
VREFN VINQN
+3.3 V
Ferrite Bead 2.2 F 100 nF VDD33 A33GND VIN8
SLOW ADC
ANALOG INTPUT
Figure 20-3. Sample Slow A/D Converter Circuit
222

Analog Component 0 I LSB Register Analog Component 0 Q LSB Register Bit(s) 7:6 Value Read Write 5:0 (A0ILR) (A0QLR) Description The current value of the two least-significant bits of the fast A/D converter are returned. Reading this register locks the value in the corresponding MSB register to guarantee that the full 10 bits are valid. Writes to these bits are ignored. These bits are ignored and will always return zeros when read. (Address = 0x0800) (Address = 0x0802)
Analog Component 0 I MSB Register Analog Component 0 Q MSB Register Bit(s) 7:0 Value Read Write
(A0IMR) (A0QMR) Description
The current value of the eight most-significant bits of the fast A/D converter are returned. Writes to this register are ignored.
223
Analog Component 0 Control Register Bit(s) 7 Value 0 1 6:4 000 001 010 011 100 101 110 111 3 0 1 2 0 1 1:0 00 01 10 11
(A0CR) Description
(Address = 0x0804)
Use peripheral clock as fast A/D converter clock source. Use Parallel Port PD4 as fast A/D converter clock source. Clock divided by 2. Clock divided by 4. Clock divided by 8. Clock divided by 16. Clock divided by 32. Clock divided by 64. Clock divided by 128. Clock divided by 256. Disable fast A/D converter Q channel. Enable fast A/D converter Q channel. Disable fast A/D converter I channel. Enable fast A/D converter I channel. Fast A/D converter powered down. Fast A/D converter in sleep mode. Fast A/D converter active, outputting unsigned binary. Fast A/D converter active, outputting twos complement.
Analog Component 1 I LSB Register Analog Component 1 Q LSB Register Bit(s) 7:6 Value Write Read 5:0
(A1ILR) (A1QLR) Description
The two least-significant bits for the fast D/A converter are stored. These bits will not be transferred to the fast D/A converter until the corresponding MSB register is written to guarantee that the full 10 bits are valid. These bits always return zeros when read. These bits are ignored and will always return zeros when read.
224
Analog Component 1 I MSB Register Analog Component 1 Q MSB Register Bit(s) 7:0 Value Write Read
(A1IMR) (A1QMR) Description
The eight most-significant bits for the fast D/A converter are stored. Writing these bits transfers the entire 10 bits to the fast D/A converter. These bits always return zeros when read.
Analog Component 1 Control Register Bit(s) 7 Value 0 1 6:4 000 001 010 011 100 101 110 111 3 0 1 2 0 1 1 0 0 1
(A1CR) Description
(Address = 0x0814)
Use peripheral clock as fast D/A converter clock source. Use Parallel Port PD5 as fast D/A converter clock source. Clock divided by 2. Clock divided by 4. Clock divided by 8. Clock divided by 16. Clock divided by 32. Clock divided by 64. Clock divided by 128. Clock divided by 256. Disable fast D/A converter Q channel. Enable fast D/A converter Q channel. Disable fast D/A converter I channel. Enable fast D/A converter I channel. This bit is reserved and should be written with zero. Fast D/A converter in normal mode (powered down if both channels are disabled). Fast D/A converter in sleep mode.
225
Analog Component 2 LSB Register Bit(s) 7:6 Value Read Write 5:0
(A2LR) Description
(Address = 0x0820)
The current value of the two least-significant bits of the slow A/D converter are returned. Reading this register locks the value in the corresponding MSB register to guarantee that the full 10 bits are valid. Writes to this register are ignored. These bits are ignored and will always return zeros when read.
Analog Component 2 MSB Register Bit(s) 7:0 Value Read Write
(A2MR) Description
(Address = 0x0821)
The current value of the eight most-significant bits of the slow A/D converter are returned. Writes to this register are ignored.
226
Analog Component 2 Control Register Bit(s) 7 Value 0 1 6:4 000 001 010 011 100 101 110 111 3 (Readonly) 2 (Writeonly) 1 0 0 1 0 1 0 1
(A2CR) Description
(Address = 0x0824)
Use peripheral clock as slow A/D converter clock source. Use Parallel Port PD6 as slow A/D converter clock source. Clock divided by 2. Clock divided by 4. Clock divided by 8. Clock divided by 16. Clock divided by 32. Clock divided by 64. Clock divided by 128. Clock divided by 256. Conversion not complete. Conversion complete. No effect on slow A/D converter. Start conversion. These bits are reserved. Reads return zeros. Slow A/D converter in sleep mode. This bit is ignored if Network Port C is enabled. Slow A/D converter active.
227
228
21. DMA CHANNELS

21.1 Overview
There are eight independent DMA channels on the Rabbit 5000. All eight channels are identical, and are capable of transferring data to or from memory, external I/O, or internal I/O. The priority between the channels can be either fixed or rotating, and the DMA use of the bus can be limited to guarantee interrupt latency or CPU throughput. The DMA channels are capable of special handling for the last byte of data when sending data to selected internal I/O addresses (such as the HDLC serial ports or to the Ethernet peripheral), and can also transfer end-of-frame status after transferring data from selected internal I/O addresses. The DMA channels can watch the data being transferred, and can terminate a transfer when a particular byte is matched. A mask is available for the byte match to allow termination only on particular bit settings in the data instead of an exact byte match. Memory-to-memory transfers proceed at the maximum transfer rate unless they are gated by an external request signal or the internal timed request. Transfers to or from a number of internal I/O addresses are controlled by transfer request signals. These transfer request signals are connected automatically as a function of the internal I/O address loaded into the DMA channel. Note that if both the source and the destination are internal I/O, the source transfer request is used by the DMA channel. The DMA channels are inherently byte-oriented, so while DMA transfers can be done from a 16-bit memory, DMA transfers to a 16-bit memory can only be done if the 16-bit memory is set up to allow byte writes (see Chapter 5 for more information). For memory to memory transfers, a word transfer will occur if both addresses are aligned, but byte writes must still be enabled on the destination memory. The Ethernet and Wi-Fi peripherals are special cases as well when the 16-bit bus is enabled and the DMA source or destination address is a network port register, the DMA will attempt to transfer words if the memory address is aligned. There are two inputs available for requests linked to external I/O devices. These two external requests may be assigned to any DMA channel. These requests may also be used by a channel that has an internal I/O as a destination. In this case, the external request acts as a flow control signal for the DMA transfers because the external request is ANDed with the automatically connected internal request.
Chapter 21 DMA Channels
229
To facilitate periodic DMA transfers, there is also an internal timed request. This request is generated from a programmable 16-bit counter and may be assigned to any DMA channel. As in the case of the external requests, this request is ANDed with any internal or external request that is also assigned to that DMA channel. This periodic request can be programmed to transfer one byte or an entire buffer. The single-byte option is useful for driving an output port to create a sampled waveform, while the entire-buffer option can be used, for example, to send precisely timed serial messages over a serial port. The DMA operation is controlled by memory structures called buffer descriptors. The current buffer descriptor resides in the registers of the DMA channel, but may have been either placed there by the processor or loaded directly by the DMA channel itself. Buffer descriptors may be used singly to transfer one block of data, or they may be linked together for scatter-gather operation. Each DMA channel also contains an initial address that points to the first buffer descriptor in memory and allows the DMA channel to rewind itself automatically in the case of a transmit retry by the network port. Each buffer descriptor contains a pair of control bytes, a byte count for the data, a source address, a destination address, and an optional link address. In addition, each DMA channel retains a count of the number of bytes remaining in the buffer to allow software to determine the amount of valid data in a buffer that are terminated early by the source of the data. A buffer descriptor in memory consists of either 12 or 16 consecutive bytes organized as shown in Table 21-1. The DMA channel uses the information in the control byte to determine the length of the buffer descriptor as well as which information to fetch from the buffer descriptor. If no link address field is present, the buffer descriptor is only 12 bytes long. A memory address for either source or destination causes the DMA channel to fetch three bytes from the corresponding field in the buffer descriptor. An internal I/O or external I/O address for either source or destination causes the DMA channel to fetch two bytes from the corresponding field in the buffer descriptor. DMA memory addresses are always physical addresses, and are never translated by the MMU. All DMA memory addresses use the memory control signals, wait states, and flipped bits as selected in the Master Memory Bank Control registers. All DMA external I/O addresses use the I/O control signals and wait states as selected in the external I/O registers. The first byte in the first buffer descriptor (the byte pointed to by the initial address) is reserved for status information when transferring data from an internal serial or network device. This automatic status transfer means that the processor does not need to service any interrupts from a serial or network receiver except in the case of an error condition. When transferring data to an internal HDLC serial or Ethernet transmitter, the last byte of the last buffer will be written automatically to a special destination address to tag the data as the last in the frame, without processor intervention. However, this function is not available in the case where the buffer contains only one byte of data. If this case should occur, the buffer descriptor must contain the special destination address.
230
All the DMA channels request interrupts at the same priority level, which is set by a field in the DMA Master Control Register, but each DMA channel has its own interrupt vector location. This speeds up interrupt processing for the DMA interrupts by eliminating the need to resolve which DMA channel is actually requesting an interrupt. DMA transfers may be programmed to occur at any priority level. If the programmed level is greater than or equal to the current CPU operating level, DMA transfers will occur on demand. When the CPU operating level is greater than the programmed DMA operating level, no DMA transfers can occur. This allows interrupt services routines, or other critical code, to run with a guarantee that there will be no DMA activity during execution. Note that a simultaneous interrupt request and DMA transfer request will be resolved in favor of the DMA transfer request. Normally all DMA transfers are flow-through, meaning that the DMA does separate read and write transactions to transfer the data. However, the Rabbit 5000 DMA also contains dedicated buses to support fly-by transactions to and from certain internal I/O addresses. A fly-by transfer looks like a single transaction on the internal and external bus, where data are transferred directly to/from the peripheral from/to a memory device. Only the network ports support fly-by transfers, and the DMA automatically recognizes internal I/O addresses that support fly-by transfers.
231

DMA PD[3:2] PE[3:2] PE[7:6] External Requests DMRnCR Peripheral Clock Timed Request Counter DTRCR DTRDLR DTRDHR Master Control DMCSR DMALR DMHR DMCR DMTCR Interrupt Generation DMCR Interrupt Request
DMA Channel y
Buffer Complete Counter DyBCR
Channel n State Machine DySCR DyCR DySMR DyLnR DyLAnR Channel Adresses DyIAnR DySAnR DyDAnR Termination Byte Detect DyTBR DyTMR MMU
Buffer Unused Counter DyBUnR
232
21.1.2 Registers
Register Name DMA Master Control/Status Register DMA Master Auto-Load Register DMA Master Halt Register DMA y Buffer Complete Register DMA Master Control Register DMA Master Timing Control Register DMA Master Request 0 Control Register DMA Master Request 1 Control Register DMA Timed Request Control Register DMA Timed Request Divider Low Register DMA Timed Request Divider High Register DMA y Termination Byte Register DMA y Termination Mask Register DMA y Buffer Unused [7:0] Register DMA y Buffer Unused [15:8] Register DMA y Initial Address [7:0] Register DMA y Initial Address [15:8] Register DMA y Initial Address [23:16] Register DMA y Special Control Register DMA y Control Register DMA y Buffer Length [7:0] Register DMA y Buffer Length [15:8] Register DMA y Source Address [7:0] Register DMA y Source Address [15:8] Register DMA y Source Address [23:16] Register DMA y Destination Address [7:0] Register DMA y Destination Address [15:8] Register DMA y Destination Address [23:16] Register DMA y Link Address [7:0] Register DMA y Link Address [15:8] Register DMA y Link Address [23:16] Register Mnemonic DMCSR DMALR DMHR DyBCR DMCR DMTCR DMR0CR DMR1CR DTRCR DTRDLR DTRDHR DyTBR DyTMR DyBU0R DyBU1R DyIA0R DyIA1R DyIA2R DySCR DyCR DyL0R DyL1R DySA0R DySA1R DySA2R DyDA0R DyDA1R DyDA2R DyLA0R DyLA1R DyLA2R I/O Address 0x0100 0x0101 0x0102 0x01y3 0x0104 0x0105 0x0106 0x0107 0x0115 0x0116 0x0117 0x01y8 0x01y9 0x01yA 0x01yB 0x01yC 0x01yD 0x01yE 0x01z0 (z = y + 8) 0x01z1 (z = y + 8) 0x01z2 (z = y + 8) 0x01z3 (z = y + 8) 0x01z4 (z = y + 8) 0x01z5 (z = y + 8) 0x01z6 (z = y + 8) 0x01z8 (z = y + 8) 0x01z9 (z = y + 8) 0x01zA (z = y + 8) 0x01zC (z = y + 8) 0x01zD (z = y + 8) 0x01zE (z= y + 8) R/W R/W W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W W W W W W W R/W R/W R/W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
NOTE: The y in DMA y expresses the DMA channel number (07).

Chapter 21 DMA Channels 233
21.2 Dependencies
21.2.1 I/O Pins External DMA Request 0 can be enabled from pins PD2, PE2, or PE6. External DMA Request 1 can be enabled from pins PD3, PE3, or PE7. The DMA can use either the memory management unit or the external I/O bus to perform its transfers, and so will use the appropriate pins for each operation. 21.2.2 Clocks The DMA peripheral uses the peripheral clock for all operations. If the timed request option is enabled, then the 16-bit timed request counter will be clocked by the peripheral clock and will provide a DMA request each time it counts down to zero. 21.2.3 Interrupts Each DMA channel has its own dedicated interrupt that can occur at the end of any DMA transfer, as specified in DyCR (normally loaded from the buffer descriptor). The interrupt request is automatically cleared when the interrupt is handled. The DMA interrupt vectors are in the EIR starting at offset 0x080 for DMA Channel 0 and ending at offset 0x0F0 for DMA Channel 7. They can be set as Priority 1, 2, or 3.
234
21.3 Operation
It is possible to set up and start a DMA operation by writing directly to all the relevant address, length, and control registers, but it is expected that the typical operation would be to create a buffer descriptor in memory, write the address of that descriptor to the initial address registers (DyIAnR), and use a write to DMALR to auto-load the values from memory into the registers and start the transfer. The DMA transfer will then continue reading buffer descriptors until a buffer-marked halt is completed. The descriptor can be either 12 or 16 bytes in length; a bit in the channel control byte (which corresponds to DyCR) selects whether the link address is present or not. The processor skips the read of those bytes if a 12-byte descriptor is selected, and always skips the reads of the bytes marked not used.
Table 21-1. DMA Buffer Descriptor
Byte 0 Bytes 03 Bytes 47 Bytes 811 Bytes 1215 Special Channel Control / Frame Status Byte 1 Channel Control Source Address [23:0] Destination Address [23:0] Link Address [23:0] Byte 2 Byte 3
Buffer Length [15:0] Not Used Not Used Not Used
It is possible to abort a DMA transfer by writing the appropriate bit to the halt register, DMHR. It is also possible to restart a DMA transfer using the already-loaded register values by writing to DMCSR. The following steps explain how to set up a DMA channel. 1. Select the DMA transfer and interrupt priorities by writing to DMCR. 2. Select the DMA channel priority, maximum bytes per burst, and minimum clocks between bursts by writing to DMTCR. 3. Write the interrupt vector for the interrupt service routine to the external interrupt table. 4. Enable an external request line by writing to DMR0CR or DMR1CR. Make sure that the pin selected is set up as an input. Note that this enable will be logical-ANDed to any internal DMA enables if the DMA transfer is to/from an internal peripheral. 5. Enable the internal-timed transfer request by writing to DTRCR. Select the divider value by writing to DTRDLR and DTRDHR. Note that this enable will be logical-ANDed to any internal DMA enables if the DMA transfer is to/from an internal peripheral. 6. Select a byte to terminate the transfer on by writing to the appropriate DyTBR and DyTMR registers.
235
7. The desired control, length, and address registers should be written to a buffer descriptor (or descriptors) in memory if not done already. Several automatic options (auto-increment, auto-decrement, special peripheral enables) can be overridden by settings in DySCR. 8. The initial address registers (DyIAnR) should be loaded with the physical address of the first buffer descriptor. 9. The buffer descriptor can be loaded and the DMA transfer started by writing to the appropriate bit of DMALR. 21.3.1 Handling Interrupts The DMA interrupt request is cleared automatically when the interrupt is handled. A DMA interrupt will occur at the end of a transfer for any buffer descriptor that has bit 4 of DyCR set. 21.3.2 Example ISR A sample interrupt handler is shown below.
dma_isr:: push af ; do something with the data in the current buffer ; the interrupt request is automatically cleared pop af ipres ret
21.3.3 DMA Priority with the Processor Since the Rabbit 5000 DMA uses the memory management unit to perform transfers, normal code execution cannot occur while the DMA is active. This includes handling interrupts, so it is important to limit the amount of time that the DMA can operate. This is handled in several ways. First of all, the DMA transfers can be set to take place whenever the processor is operating at one of the four priority levels, 03 (note that there is a single priority level for all DMA transfers).
Table 21-2. DMA Transfer Priority
DMA Transfers at Priority 0 Priority 1 Priority 2 Priority 3 Operation DMA transfers only allowed when processor priority at 0 DMA transfers only allowed when processor priority at 0 or 1 DMA transfers only allowed when processor priority at 0, 1, or 2 DMA transfers allowed at any time
236
Setting an interrupt priority to something greater than the DMA transfer priority will ensure that no DMA activity occurs during that interrupt handler. Note that when both an interrupt and a DMA transfer are pending, the DMA transfer will be selected for execution first (provided its priority is equal or greater than the current processor priority level). When a DMA transfer is occurring, normal code execution will not occur until the transfer is completed. To prevent DMA transfers from excessively blocking interrupts or otherwise interfering with normal code execution, two options can be set in DMTCR. First, the maximum limit of a DMA transfer can be set from 1 to 64 bytes, which sets an upper limit on interrupt latency arising from a DMA transfer. Second, the minimum number of clocks before the DMA can be active again can be set from 12 to 512 clocks, guaranteeing processing time for the application. The values providing roughly equal access to the memory bus for both the processor and the DMA is eight bytes per burst and 64 clocks between bursts. When starting up, the DMA requires several cycles of overhead. This overhead comes about because the DMA actually uses part of the processor to perform the data transfers, and consists of one instruction fetch time plus three clock cycles. The byte fetched during the instruction fetch time is discarded, and will be refetched at the completion of the DMA burst. At the end of the DMA burst, two clock cycles are required before this first instruction fetch starts. An individual DMA channel transfers data without any overhead between bytes, but there is always one clock cycle of dead time when switching between DMA channels. Table 21-3 shows the effective number of clock cycles required per burst, assuming a single DMA channel transfer, 8-bit memory, and no wait states. Access via 16-bit memory would provide up to twice the throughput, depending on address alignment.
Table 21-3. Maximum DMA Transfer Rates
Setting 1 byte per burst 2 bytes per burst 3 bytes per burst 4 bytes per burst 8 bytes per burst 16 bytes per burst 32 bytes per burst 64 bytes per burst Total Clocks 11 clocks 15 clocks 19 clocks 23 clocks 39 clocks 71 clocks 135 clocks 263 clocks Clocks per Byte Transferred 11 7.5 6.3 5.8 4.9 4.4 4.2 4.1
The total number of clocks listed in Table 21-3 is related to the number of bytes per burst by the following formula. Total Clocks = 4 Number of Bytes per Burst + 7 (for overhead)
Chapter 21 DMA Channels 237
21.3.4 DMA Channel Priority It is possible to control the priority between separate DMA channels. There are three channel-priority options in the Rabbit 5000. The first is fixed priority after every byte where the priority of each channel is equal to its number, i.e., if both DMA Channels 3 and 4 have a pending transfer request, DMA Channel 4 will always be enabled first. If at any point a channel with higher priority than the one currently transferring has a DMA request pending, the current transfer will be terminated and the new channels transfer will start. With this setting, DMA Channel 7 will always have priority over all other channels, and DMA Channel 0 will transfer only if no other channels have pending requests. The other two settings rotate the priority between channels as shown in Table 21-4; after the seventh rotation, the priority sequence restarts at the top of the table. One option is to rotate priority after every byte analogous to the fixed-priority setting. The priority list is updated after each byte transferred, and if a higher priority channel has a pending request, the current transfer will be terminated and the new channel transfer will start. The other option is to rotate after every burst; this will guarantee that reasonable amounts of data are transferred by each channel before a switchover occurs.
Table 21-4. Rotating DMA Channel Priority
Rotation Initial (and eighth) First Second Third Fourth Fifth Sixth Seventh Channel Priority, High to Low 7, 6, 5, 4, 3, 2, 1, 0 6, 5, 4, 3, 2, 1, 0, 7 5, 4, 3, 2, 1, 0, 7, 6 4, 3, 2, 1, 0, 7, 6, 5 3, 2, 1, 0, 7, 6, 5, 4 2, 1, 0, 7, 6, 5, 4, 3 1, 0, 7, 6, 5, 4, 3, 2 0, 7, 6, 5, 4, 3, 2, 1
21.3.5 Buffer Descriptor Modes Flags in the control byte of a buffer descriptor (which gets loaded into DyCR) describe whether to halt on completion of the transfer (or load another descriptor) and whether the next descriptor is adjacent in memory (which implies that the current descriptor is only 12 bytes long) or located at the link address. Each descriptor can also be set to generate an interrupt on completion of the transfer. By using these options in various ways, the Rabbit 5000 DMA can be operated in a number of conventional DMA modes. The most common options are described here; others are certainly possible by different use of the available linking methods.
238
21.3.5.1 Single Buffer
In the simplest mode, a single descriptor is set to halt and interrupt on completion.
Single Buffer
Initial Address Buffer Descriptor (12 bytes)
Interrupt
21.3.5.2 Buffer Array
In this mode, an array of 12-byte descriptors is set up adjacent in memory; only the last buffer is set to halt on completion. The last buffer is also typically set to interrupt on completion, but other buffer descriptors in the array can also generate interrupts.
Buffer Array
Initial Address Buffer Descriptor (12 bytes) Buffer Descriptor (12 bytes) Buffer Descriptor (12 bytes) Buffer Descriptor (12 bytes) Interrupt
The advantage of the buffer array is that its descriptors require less memory than a full 16byte descriptor. The simplest version of the buffer array is a double buffer, which is frequently used to provide a reserve buffer in case the application is slow in handling the first buffer once received (in this case, both buffers are enabled to interrupt on completion).
239
21.3.5.3 Linked List
A linked list is similar to a buffer array, except that 16-byte descriptors are used and the descriptors are not necessarily adjacent in memory. The advantage of this mode is the ability to spread descriptors.
Linked List
Initial Address Buffer Descriptor (16 bytes) (12 Link Address Buffer Descriptor (16 bytes) (12 Link Address Buffer Descriptor (16 bytes) (12
Interrupt
240
21.3.5.4 Circular Queue
A circular queue is a buffer array or linked list where the final buffer is linked back to the first buffer in the sequence. This method allows for continuous reception of transfers without having to reload the initial address for the DMA buffer descriptor sequence.
Circular Queue
Initial Address Buffer Descriptor (16 bytes) (12
Interrupt Link Address Buffer Descriptor (16 bytes) (12
Interrupt Link Address Buffer Descriptor (16 bytes) (12
Interrupt Link Address
The ping-pong buffer, where there are only two buffers, is the simplest version of a circular queue. The application can operate on one buffer while the other buffer is being loaded.
21.3.5.5 Linked Array
The linked array is simply a linked list of buffer arrays, where the last buffer in each array is linked to the first buffer in the next array (which can be located anywhere in memory). This method could be useful where a message is broken down into separate transfers, but entire messages could be scattered/gathered from anywhere in memory.
241
21.3.6 DMA with Peripherals When the DMA is directed towards an internal I/O address, the DMA transfer request signals will be connected as appropriate for that peripheral. For example, when a DMA transfer is performed to Serial Port Ds data register, the transfer request will be enabled whenever the serial port transmit buffer is empty, and will be disabled whenever it is not.
21.3.6.1 DMA with HDLC Serial Ports
The HDLC serial ports receive special handing by the DMA. When the DMA destination is Serial Port Es or Serial Port Fs data register (SxDR), the final byte of the transfer will be written to the appropriate last data register (SxLDR) as required to complete an HDLC packet and append the CRC value. In addition, the value in the appropriate status register (SxSR) will be written to the status byte in the buffer descriptor pointed to by the initial address registers (not necessarily the buffer descriptor that is currently being used). These features allow an application to automatically send and receive packets via DMA, only requiring direct handling of a packet when an error occurs.
21.3.6.2 DMA with Ethernet
The Ethernet network peripheral also receives special handing by the DMA. When the DMA destination is the network data register (NBDR), the final byte of the transfer will be written to the last data register (NBLDR) as required to complete an Ethernet packet and append the CRC value. The Ethernet network peripheral also has support for DMA fly-by transfers between the peripheral and external memory.
21.3.6.3 DMA with Wi-Fi
The Wi-Fi network peripheral has support for DMA fly-by transfers between the peripheral and external memory. However, the Wi-Fi peripheral has a minimum access time of 75 ns, and typically requires wait states, so fly-by DMA may not be the most efficient access method.
21.3.6.4 DMA with PWM and Timer C
The PWM and Timer C peripherals have special support for DMA the block access and pointer registers in each of these peripherals provide a means for the DMA to update the settings of these peripherals at some desired rate. This allows complex PWM waveforms to be generated by using the DMA timed request to update the PWM duty cycles at regular intervals.
242

DMA Master Control/Status Register Bit(s) 7:0 (Writeonly) Value 0 (DMCSR) Description No effect on the corresponding DMA channel. Start (or restart) the corresponding DMA channel using the contents of the DMA channel registers. This command should only be issued after all the DMA channel registers (source, destination, length, and link if applicable) have been loaded. The corresponding DMA channel is either disabled or has completed the last buffer descriptor. The corresponding DMA channel is enabled and active. These bits are set by the start command and remain set until the completion of the last buffer. (Address = 0x0100)
7:0 (Readonly)
0 1
DMA Master Auto-Load Register Bit(s) 7:0 Value 0 1
(DMALR) Description
(Address = 0x0101)
No effect on the corresponding DMA channel. Start (using auto-load) the corresponding DMA channel, using the buffer descriptor in memory addressed by the channel initial address register. This command should only be issued after the initial address has been loaded.
DMA Master Halt Register Bit(s) 7:0 Value 0 1
(DMHR) Description
(Address = 0x0102)
No effect on the corresponding DMA channel. Halt the corresponding DMA channel. The DMA registers retain the current state, and the DMA can be restarted using DMCSR.
243
DMA y Buffer Complete Register
(D0BCR) (D1BCR) (D2BCR) (D3BCR) (D4BCR) (D5BCR) (D6BCR) (D7BCR) Description
(Address = 0x0103) (Address = 0x0113) (Address = 0x0123) (Address = 0x0133) (Address = 0x0143) (Address = 0x0153) (Address = 0x0163) (Address = 0x0173)
Bit(s)
Value
7:0
Read
The DMA increments a counter at the start of the next buffer. This count is latched in this register and can be used, along with the buffer unused count, to determine the actual amount of data transferred by the DMA. This counter is initialized by a start command or when the DMA is automatically rewound to the initial address. Writing to this register loads the counter. This feature is intended only for testing, because the DMA automatically resets the counter to all ones when fetching from the initial address. The counter is incremented whenever the DMA fetches a new buffer length value from a descriptor.
Write
DMA Master Control Register Bit(s) 7:4 3:2 00 01 10 11 1:0 00 01 10 11 Value
(DMCR) Description
(Address = 0x0104)
These bits are reserved and should be written with zeros. DMA transfers at Priority 0. No DMA transfers while CPU operates at Priority 3, 2, or 1. DMA transfers at Priority 1. No DMA transfers while CPU operates at Priority 3 or 2. DMA transfers at Priority 2. No DMA transfers while CPU operates at Priority 3. DMA transfers at Priority 3. DMA transfers at any time. DMA interrupts are disabled. DMA interrupts use Interrupt Priority 1. DMA interrupts use Interrupt Priority 2. DMA interrupts use Interrupt Priority 3.
244
DMA Master Timing Control Register Bit(s) 7:6 Value 0x 10 11 5:3 000 001 010 011 100 101 110 111 2:0 000 001 010 011 100 101 110 111
(DMTCR) Description
(Address = 0x0105)
Fixed DMA channel priority. Higher channel number has higher priority. Rotating DMA channel priority. Priority rotates highest channel number to lowest channel number after every byte is transferred. Rotating DMA channel priority. Priority rotates highest channel number to lowest channel number after the current channel request is serviced. Maximum one byte per burst. Maximum two bytes per burst. Maximum three bytes per burst. Maximum four bytes per burst. Maximum eight bytes per burst. Maximum 16 bytes per burst. Maximum 32 bytes per burst. Maximum 64 bytes per burst. Minimum 12 clocks between bursts. Minimum 16 clocks between bursts. Minimum 24 clocks between bursts. Minimum 32 clocks between bursts. Minimum 64 clocks between bursts. Minimum 128 clocks between bursts. Minimum 256 clocks between bursts. Minimum 512 clocks between bursts.
245
(Address = 0x0106)
246
(Address = 0x0107)
247
DMA Timed Request Control Register Bit(s) 7 Value 0 1 6:5 4:3 00 01 10 11 2:0 000 001 010 011 100 101 110 111 Timed DMA request disabled. Timed DMA request enabled.
(DTRCR) Description
(Address = 0x0115)
These bits are reserved and should be written with zeros. Timed DMA request transfers one byte per request. This bit combination is reserved and should not be used. Timed DMA request triggers transfers until current descriptor is complete. DMA channel fetches the next descriptor if appropriate. This bit combination is reserved and should not be used. Timed DMA request supplied to DMA Channel 0. Timed DMA request supplied to DMA Channel 1. Timed DMA request supplied to DMA Channel 2. Timed DMA request supplied to DMA Channel 3. Timed DMA request supplied to DMA Channel 4. Timed DMA request supplied to DMA Channel 5. Timed DMA request supplied to DMA Channel 6. Timed DMA request supplied to DMA Channel 7.
DMA Timed Request Divider Low Register Bit(s) 7:0 Value Write
(DTRDLR) Description
(Address = 0x0116)
The eight LSBs of the limit value for the DMA timed request timer are stored.
DMA Timed Request Divider High Register Bit(s) 7:0 Value Write
(DTRDHR) Description
(Address = 0x0117)
The eight MSBs of the limit value for the DMA timed request timer are stored.
248
DMA y Termination Byte Register
(D0TBR) (D1TBR) (D2TBR) (D3TBR) (D4TBR) (D5TBR) (D6TBR) (D7TBR) Description
Bit(s) 7:0
Value
Byte value that, if matched, will terminate a buffer.
DMA y Termination Mask Register
(D0TMR) (D1TMR) (D2TMR) (D3TMR) (D4TMR) (D5TMR) (D6TMR) (D7TMR) Description
Bit(s)
Value
7:0
Mask for termination byte. A one in a bit position enables the corresponding bit of the termination byte to be used in the compare to generate the termination condition. A zero in a bit position disables the corresponding bit from contributing to the termination condition. A value of all zeros in this register disables the termination-byte match feature.
DMA y Buffer Unused[7:0] Register
(D0BU0R) (D1BU0R) (D2BU0R) (D3BU0R) (D4BU0R) (D5BU0R) (D6BU0R) (D7BU0R) Description
(Address = 0x010A) (Address = 0x011A) (Address = 0x012A) (Address = 0x013A) (Address = 0x014A) (Address = 0x015A) (Address = 0x016A) (Address = 0x017A)
Bit(s)
Value
7:0
Bits 7:0 of the buffer unused length value are stored in this register. The DMA copies the buffer remaining length to this register at the completion of the transfer. Normally the buffer remaining length is zero, but if the transfer terminates early, under source control or because of a termination-byte match, the number of unused bytes in the buffer is written.
249
DMA y Buffer Unused[15:8] Register
(D0BU1R) (D1BU1R) (D2BU1R) (D3BU1R) (D4BU1R) (D5BU1R) (D6BU1R) (D7BU1R) Description
(Address = 0x010B) (Address = 0x011B) (Address = 0x012B) (Address = 0x013B) (Address = 0x014B) (Address = 0x015B) (Address = 0x016B) (Address = 0x017B)
Bit(s) 7:0
Value
Bits 15:8 of the buffer unused-length value are stored in this register.
DMA y Initial Addr[7:0] Register
(D0IA0R) (D1IA0R) (D2IA0R) (D3IA0R) (D4IA0R) (D5IA0R) (D6IA0R) (D7IA0R) Description
(Address = 0x010C) (Address = 0x011C) (Address = 0x012C) (Address = 0x013C) (Address = 0x014C) (Address = 0x015C) (Address = 0x016C) (Address = 0x017C)
Bit(s) 7:0
Value
Bits 7:0 of the initial address are stored in this register.
(Address = 0x010D) (Address = 0x011D) (Address = 0x012D) (Address = 0x013D) (Address = 0x014D) (Address = 0x015D) (Address = 0x016D) (Address = 0x017D)
Bit(s) 7:0
Value
(Address = 0x010E) (Address = 0x011E) (Address = 0x012E) (Address = 0x013E) (Address = 0x014E) (Address = 0x015E) (Address = 0x016E) (Address = 0x017E)
Bit(s) 7:0
Value
250
DMA y Special Control Register
(D0SCR) (D1SCR) (D2SCR) (D3SCR) (D4SCR) (D5SCR) (D6SCR) (D7SCR) Description
(Address = 0x0180) (Address = 0x0190) (Address = 0x01A0) (Address = 0x01B0) (Address = 0x01C0) (Address = 0x01D0) (Address = 0x01E0) (Address = 0x01F0)
Bit(s) 7:4 3
Value
These bits are reserved and will always be read as zeros. 0 1 Auto-connect source DMA request. Disconnect source DMA request (full buffer transfer). Normal source address. Source address fixed, independent of type. Auto-connect destination DMA request. Disconnect destination DMA request (full buffer transfer). Normal destination address. Destination address fixed, independent of type.
0 1
0 1
0 1
251
DMA y Control Register
(D0CR) (D1CR) (D2CR) (D3CR) (D4CR) (D5CR) (D6CR) (D7CR) Description
Bit(s) 7
Value 0 1
Continue to next buffer descriptor. Final buffer descriptor. Stop DMA operation upon completion of this transfer. Use sequential address for next buffer descriptor. The link address field is not present in this buffer descriptor, which is now 12 bytes long. Use the link address field as a pointer to the next buffer descriptor. This buffer descriptor is 16 bytes long. No special treatment for last byte. Internal Source: status byte written to initial buffer descriptor before last data. Internal Destination: Last byte written to offset address for frame termination. All others: No effect. No interrupt on completing this transfer. Interrupt on completing this transfer. Source address is fixed internal I/O (two-byte) address. Source address is fixed external I/O (two-byte) address. Source address is memory (three-byte) address, auto-decrement. Source address is memory (three-byte) address, auto-increment. Destination address is fixed internal I/O (two-byte) address. Destination address is fixed external I/O (two-byte) address. Destination address is memory (three-byte) address, auto-decrement. Destination address is memory (three-byte) address, auto-increment.
0 1
0 1
3:2
00 01 10 11
1:0
00 01 10 11
252
DMA y Length[7:0] Register
(D0L0R) (D1L0R) (D2L0R) (D3L0R) (D4L0R) (D5L0R) (D6L0R) (D7L0R) Description
Bit(s) 7:0
Value
Bits 7:0 of the buffer length value are stored in this register. The DMA does a transfer followed by a decrement of this register, so an initial value of 0x0000 will result in a 65536-byte transfer.
DMA y Length[15:8] Register
(D0L1R) (D1L1R) (D2L1R) (D3L1R) (D4L1R) (D5L1R) (D6L1R) (D7L1R) Description
Bit(s) 7:0
Value
Bits 15:8 of the buffer length value are stored in this register.
253
DMA y Source Addr[7:0] Register
(D0SA0R) (D1SA0R) (D2SA0R) (D3SA0R) (D4SA0R) (D5SA0R) (D6SA0R) (D7SA0R) Description
Bit(s) 7:0
Value
Bits 7:0 of the source address are stored in this register.
Bit(s) 7:0
Value
Bit(s) 7:0
Value
254
DMA y Destination Addr[7:0] Register
(D0DA0R) (D1DA0R) (D2DA0R) (D3DA0R) (D4DA0R) (D5DA0R) (D6DA0R) (D7DA0R) Description
Bit(s) 7:0
Value
Bits 7:0 of the destination address are stored in this register.
Bit(s) 7:0
Value
(Address = 0x018A) (Address = 0x019A) (Address = 0x01AA) (Address = 0x01BA) (Address = 0x01CA) (Address = 0x01DA) (Address = 0x01EA) (Address = 0x01FA)
Bit(s) 7:0
Value
255
DMA y Link Addr[7:0] Register
(D0LA0R) (D1LA0R) (D2LA0R) (D3LA0R) (D4LA0R) (D5LA0R) (D6LA0R) (D7LA0R) Description
(Address = 0x018C) (Address = 0x019C) (Address = 0x01AC) (Address = 0x01BC) (Address = 0x01CC) (Address = 0x01DC) (Address = 0x01EC) (Address = 0x01FC)
Bit(s) 7:0
Value
Bits 7:0 of the link address are stored in this register.
(Address = 0x018D) (Address = 0x019D) (Address = 0x01AD) (Address = 0x01BD) (Address = 0x01CD) (Address = 0x01DD) (Address = 0x01ED) (Address = 0x01FD)
Bit(s) 7:0
Value
(Address = 0x018E) (Address = 0x019E) (Address = 0x01AE) (Address = 0x01BE) (Address = 0x01CE) (Address = 0x01DE) (Address = 0x01EE) (Address = 0x01FE)
Bit(s) 7:0
Value
256
22. 10/100BASE-T ETHERNET

22.1 Overview
Network Port B implements a full 10/100Base-T Ethernet MAC with an industry-standard MII interface for an external PHY chip. The MAC is fully compliant with the IEEE 802.3 Ethernet standard, including support for auto-negotiation, link detection, multicast filtering, and broadcast addresses. A wide variety of transmit and receive options are available, including control over frame size, CRC attachment, maximum allowed frame size, and interpacket gap length. The receiver and transmitter each have a 2048-byte FIFO that is shared with the Wi-Fi peripheral; the I/O pins are also shared. Because of this, only one of the two network peripherals can be enabled at any time. The Network Port B receiver transfers both data and status information to memory via the DMA, eliminating the need for receive data or status interrupts and dedicated receive status registers. The network port appends six bytes of status information to the last byte of the received data. Buffer and byte counts in the DMA can be used to find this status information in memory. In cases where a received frame has been discarded because of an error, only these six bytes of status will be transferred to memory. The DMA must be programmed to close a buffer on end-of-frame, as the network port marks the last byte of status this way. The Network Port B transmitter uses interrupts because the DMA has no way of knowing when (or if) the frame has successfully been sent. Both the receive and transmit FIFOs are capable of DMA fly-by operation. The network port requires an accurate 25 MHz clock to generate the 100 Mbits/s serial rate of 100Base-T. This clock comes from the external PHY chip, and is input on separate pins for the transmit and receive channels. The clock for the network port may also be disabled to conserve power. The network port contains synchronization circuitry to allow operation from the 25 MHz reference clock while the main system clock runs independently. The network port transmitter precedes the transmit data automatically with a preamble and start-frame-delimiter, and appends CRC and the end-frame delimiter after the last byte. Frame transmission starts automatically once the transmit FIFO is complete and any interframe gap time or back-off time has expired. Transmission is aborted if a collision is detected, and is retried up to 16 times using the standard random back-off time algorithm. Detection of a collision causes the transmitter to send a 32-bit jam pattern of all ones to guarantee that all receivers in the network recognize the collision.
Chapter 22 10/100Base-T Ethernet 257
The network port receiver uses the received preamble to synchronize to the phase of the incoming frame, and then waits for the start-frame delimiter. Character assembly begins at this point, and each byte is transferred to the receive FIFO. However, no interrupt or DMA request will occur until after the first six bytes of the frame have been received and checked for an address match. The receiver can receive frames independent of the address (promiscuous mode), or it can receive frames with a physical address match, a broadcast address match, or a multicast address match. Normal DMA transfers of data begin once an address match occurs, and continue until the end-frame delimiter is recognized or the line goes idle because of a collision. The network receiver calculates the CRC across the entire frame in parallel with character assembly, and reports the result when the end-frame delimiter is recognized. Normally frames with bad CRC are discarded. The receiver also reports misaligned end-frame delimiters (those that do not occur on byte boundaries). The network port implements the NLP receive link integrity test state machine, which requires link integrity pulses to be detected at certain intervals in the absence of other network activity. If the network receiver enters the NLP Link Test Fail state because of missing link-test pulses, this state machine requires seven successive properly timed link test pulses (or an equal number of FLP bursts) before reporting that the link is again active. The reset state of this state machine is link-inactive. Note that this is a subtle difference relative to the normal 10Base-T receive link-integrity state machine, which requires either link test pulses or carrier sense to make the link active. The network port implements the auto-negotiation algorithm to determine half-duplex or full-duplex operation. In addition to its normal automatic operation, this feature can be disabled or commanded to execute under software control. The MII interface consists of 20 pins as specified in IEEE 802.3 standard. Two clocks are provided on the interface, one for transmit and one for receive. The two A/D converters and single D/A converter are available for customer use when the Ethernet peripheral is enabled.
258

10/100 Ethernet Peripheral
25 MHz Clock
Network Tx Status NBTSR NBTESR Tx FIFO 2048 bytes NBDR
Transmit MII Interface
TXD [3:0] TXEN TXER CRS COL
NBTCR NBDTR MDC MDO MDOEN MDI
Peripheral Clock
MII Management Clock NBMCFR Network Port Control NBCSR NBPAxR NBCR NBTPxR NBSAxR NBCFxR NBGxR NBRMR NBCWR NBFLxR
MII Management
NBDMR NBMRR NBMCR NBMRAR
NBMPAR NBMWxR NBMRxR NBMSR
Receive MII Interface Rx FIFO 2048 bytes NBDR NBLDR Multicast Filter NBMFxR NBRCR NBDRR
RXD [3:0] RXDV RXER
Chapter 22 10/100Base-T Ethernet
259
22.1.2 Registers
Register Name Network Port B Data Register Network Port B Last Data Register Network Port B Transmit Status Register Network Port B Control/Status Register Network Port B Command Register Network Port B Transmit Pause LSB Register Network Port B Transmit Pause MSB Register Network Port B Transmit Control Register Network Port B Receive Control Register Network Port B Transmit Extra Status Register Network Port B Phys. Addr. [7:0] Register Network Port B Phys. Addr. [15:8] Register Network Port B Phys. Addr. [23:16] Register Network Port B Phys. Addr. [31:24] Register Network Port B Phys. Addr. [39:32] Register Network Port B Phys. Addr. [47:40] Register Network Port B Multicast Filter [7:0] Register Network Port B Multicast Filter [15:8] Register
Network Port B Multicast Filter [23:16] Register Network Port B Multicast Filter [31:24] Register Network Port B Multicast Filter [39:32] Register Network Port B Multicast Filter [47:40] Register Network Port B Multicast Filter [55:48] Register Network Port B Multicast Filter [63:56] Register Network Port B Direct Rx Register Network Port B Direct Tx Register Network Port B Direct MII Register
Mnemonic NBDR NBLDR NBTSR NBCSR NBCR NBTPLR NBTPMR NBTCR NBRCR NBTESR NBPA0R NBPA1R NBPA2R NBPA3R NBPA4R NBPA5R NBMF0R NBMF1R NBMF2R NBMF3R NBMF4R NBMF5R NBMF6R NBMF7R
NBDRR NBDTR NBDMR
I/O Address 0x0200 0x0201 0x0202 0x0204 0x0206 0x0208 0x0209 0x020A 0x020B 0x020C 0x0210 0x0211 0x0212 0x0213 0x0214 0x0215 0x0218 0x0219 0x021A 0x021B 0x021C 0x021D 0x021E 0x021F
0x0228 0x0229 0x022A
R/W R/W W R R/W W R/W R/W R/W R/W R/W W W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R
W R/W
Reset xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
xxxxxxxx xxxxxxxx xxxxxxxx
Network Port B Configuration 0 Register Network Port B Configuration 1 Register Network Port B Configuration 2 Register Network Port B Configuration 3 Register Network Port B Gap 0 Register
260
NBCF0R NBCF1R NBCF2R NBCF3R NBG0R
0x0240 0x0241 0x0242 0x0243 0x0244
R/W R/W R/W R/W R/W
00000000 00000000 00000000 00000000 00000000
Register Name Network Port B Gap 2 Register Network Port B Gap 1 Register Network Port B Retransmit Max Register Network Port B Collision Window Register Network Port B Frame Limit LSB Register Network Port B Frame Limit MSB Register Network Port B MII Configuration Register Network Port B MII Reset Register Network Port B MII Command Register Network Port B MII Register Address Register Network Port B MII PHY Address Register Network Port B MII Write LSB Register Network Port B MII Write MSB Register Network Port B MII Read LSB Register Network Port B MII Read MSB Register Network Port B MII Status Register Network Port B Station Address 0 Register Network Port B Station Address 1 Register Network Port B Station Address 2 Register Network Port B Station Address 3 Register Network Port B Station Address 4 Register Network Port B Station Address 5 Register Enable Network Port Register
Mnemonic NBG2R NBG1R NBRMR NBCWR NBFLLR NBFLMR NBMCFR NBMRR NBMCR NBMRAR NBMPAR NBMWLR NBMWMR NBMRLR NBMRMR NBMSR NBSA0R NBSA1R NBSA2R NBSA3R NBSA4R NBSA5R ENPR
I/O Address 0x0246 0x0247 0x0248 0x0249 0x024A 0x024B 0x0250 0x0251 0x0252 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 0x0430
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W R R R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
261
22.2 Dependencies
22.2.1 I/O Pins The network port MII interface has 20 dedicated pins, which are listed in Table 22-1. These pins can be used as general-purpose inputs and outputs if the network port is not being used via NBDRR, NBDTR, and NBDMR.
Table 22-1. Network Port MII Interface
Section Signal TXD[3:0] TX_EN TX_ER Transmit CRS COL TX_CLK RXD[3:0] RX_DV Receive RX_ER RX_CLK MDC MDI Management MDO MDOEN Output Output Management data output Management data output enable Input Input Output Input Receive data error Receive clock (25 MHz) Management data clock (varies) Management data input Input Input Input Input Input Carrier sense Collision detect Transmit clock (25 MHz) Receive data from PHY Receive data valid Direction Output Output Output Function Transmit data to PHY Transmit enable Transmit error
22.2.2 Clocks The network port requires a 25 MHz clock input for proper 10/100Base-T operation; this clock is normally supplied separately to the receive and transmit portions of the peripheral on the RX_CLK and TX_CLK pins. The management data clock on MDC is generated by the Rabbit 5000 by dividing down the peripheral clock as selected in NBMCFR. 22.2.3 Other Registers
Register EDMR Function Enable 10/100 Ethernet functionality.
262
22.2.4 Interrupts The network interrupt can be generated by an Ethernet frame being transmitted correctly, transmitted with an error, or if a transmit pause occurs (control frame is transmitted but not the data). The events that generate an interrupt can be selected in NBCSR. The receive frame status is attached to the end of the data frame itself, so the DMA interrupt can be used to handle received frame. See Section 22.3 for more details. The network port interrupt vector is shared with Network Port C, the Wi-Fi network port. It is located in the IIR at offset 0x1E0. It can be set as Priority 1, 2, or 3 by writing to ENPR.
22.3 Operation
High-level support for TCP/IP and other protocols is beyond the scope of this manual, but this section will describe the low-level setup and operation of the 10/100Base-T Ethernet peripheral. The contents of the six status bytes are shown below. Note that any status block marked with RxOV (receive overflow) is invalid, as the FIFO could not hold the entire frame. Only the marked frame is invalid, so any previous frames read from the FIFO are fine. Once an overflow is detected, no subsequent frames can be buffered to the FIFO until a FIFO purge command is written to the NBCR.
Status Byte First Second Third Fourth Fifth Last RxOV Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LSB of Rx Checksum MSB of Rx Checksum Receive Status Vector [7:0] (LSB of receive frame length) Receive Status Vector [15:8] (MSB of receive frame length) Receive Status Vector [23:16] Receive Status Vector [30:24]
263
22.3.1 Setup The following steps explain how to set up Network Port B. 1. Write the interrupt vector for the interrupt service routine to the external interrupt table. 2. Select the desired interrupts and interrupt priority by writing to NBCSR. 3. Select the MII interface settings by writing to NBMCFR, NBMRAR, and NBMPAR. 4. Select the desired configuration of transmit and receive operation by writing to NBTCR, NBTESR, and MBRCR. 5. Write the devices physical MAC address to the physical address (NBPAxR) and station address registers (NBSAxR). 6. If desired, write to the multicast filter registers (NBMFxR) to generate a multicast filter. 7. Select other options in the configuration registers NBCFxR, NBGxR, NBRMR, NBCWR, and NBFLxR. 8. Enable the network port transmitter by writing to NBTCR. 9. Enable the network port receiver by writing to NBRCR. 22.3.2 Transmit The following steps explain how to transmit an Ethernet packet. 1. Set up a DMA buffer descriptor that will read the packet data from memory and write it to NBDR. Write the buffer descriptors address to the DMAs initial address registers (see Chapter 21 for more information). 2. Enable the DMA transfer by auto-loading the buffer. 3. The packet transmission will proceed automatically. If any interrupts were enabled for any transmitted packet events, they will occur upon completion (or error). Note that network interrupts will occur when the data appears in the network peripheral, but DMA interrupts will occur when the DMA transfer is complete. 22.3.3 Receive The following steps explain how to receive an Ethernet packet. 1. Set up a DMA buffer descriptor that will read the packet data from NBDR and write it to memory. Write the buffer descriptors address to the DMAs initial address registers (see Chapter 21 for more information). 2. Set up a DMA interrupt to handle the packet once it has been received and copied to memory. 3. Enable the DMA transfer by auto-loading the buffer. 4. The packet transmission will proceed automatically when data come in. When the DMA transfer is complete, the DMA interrupt can be used to start the packet processing. The status of the received packet is appended to the received data.
22.3.4 Handling Interrupts The network port transmit interrupt is automatically cleared by reading NBCSR; received packets are handled via the DMA interrupt, which is automatically cleared when the ISR is called. A sample packet transmit interrupt handler is shown below.
network_isr:: push af ioi ld a, (NBCSR) push af bit 4,a jp nz, handle_tx_err bit 4,a jp nz, handle_pause_err done: pop af ipres ret handle_tx_err: ioi ld a, (NBTSR) ; get transmitter status ; check why error occurred and respond accordingly pop af pop af ipres ret handle_pause_err: ; handle transmit pause ; read the interrupt status ; save status byte for later ; did transmit error occur? ; did transmit pause occur?
pop af
ipres ret
A sample packet receive interrupt handler is shown below.

dma_eth_rx_isr:: ; interrupt is automatically cleared ; check status bytes appended to packet just received ipres ret
265
22.3.5 Multicast Addressing A physical address match requires that the received frame address is a physical address that matches every bit of the programmed receive address. A broadcast address match requires that all 48 bits of the received frame address be ones. A multicast address match requires the received frame address to be a multicast address (LSB of the address is one) and a match in the multicast address filter. The multicast address filter uses the six most significant bits of the CRC calculated on the receive address as an index into a 64-by-1 bit table written under program control. A one in the corresponding table entry constitutes a multicast address match as far as the network port is concerned. A table of one set of unique multicast addresses corresponding to each filter bit is shown below. The table shows the least significant byte of the multicast address; the remaining five bytes of the address are all zeros for this set of multicast addresses.
Register NBMF7R NBMF6R NBMF5R NBMF4R NBMF3R NBMF2R NBMF1R NBMF0R Bit 7 0x17 0xD9 0xCF 0x01 0x5F 0x91 0x87 0x49 Bit 6 0x0B 0xC5 0xD3 0x1D 0x43 0x8D 0x9B 0x55 Bit 5 0x05 0xCB 0xDD 0x13 0x4D 0x83 0x95 0x5B Bit 4 0x19 0xD7 0xC1 0x0F 0x51 0x9F 0x89 0x47 Bit 3 0x85 0x4B 0x5D 0x93 0xCD 0x03 0x15 0xDB Bit 2 0x99 0x57 0x41 0x8F 0xD1 0x1F 0x09 0xC7 Bit 1 0x97 0x59 0x4F 0x81 0xDF 0x11 0x07 0xC9 Bit 0 0x8B 0x45 0x53 0x9D 0xC3 0x0D 0x1B 0xD5
266

Network Port B Data Register Bit(s) 7:0 Value Read Write (NBDR) Description Returns the contents of the receive buffer. This register is not normally accessed by the processor, but is accessed by the DMA channels. Loads the transmit buffer with a data byte for transmission. (Address = 0x0200)
Network Port B Last Data Register Bit(s) 7:0 Value Read
(NBLDR) Description
(Address = 0x0201)
Returns the contents of the receive buffer. This register is not normally accessed by the processor, but is accessed by the DMA channels. Loads the transmit buffer with the last data byte of a frame to enable the subsequent transmission of the CRC. The DMA automatically writes the last byte of the frame to this address.
Write
Network Port B Transmit Status Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(NBTSR) Description
(Address = 0x0202)
Frame transmission not complete. Frame transmission complete. Frame transmission is not deferring. Frame transmission is deferring. No excessive collisions. Frame transmission aborted due to excessive collisions. No transmit underrun. Frame transmission aborted because of a FIFO underrun. Frame transmission not too long. Frame transmission too long. No excessive defers. Frame transmission deferred excessively. No collisions. Frame transmission encountered at least one collision. No late collisions. Frame transmission encountered a late collision (later than one slot time).
267
Network Port B Control/Status Register Bit(s) 7:6 5:3 (Writeonly) 5:3 5 (Readonly) 4 (Readonly) 3 (Readonly) 2 1:0 0 1 Read 0 1 0 1 0 1 0 00 01 10 11 Value
(NBCSR) Description
(Address = 0x0204)
These bits are reserved and will always read as zero. The corresponding interrupt is disabled. The corresponding interrupt is enabled. These bits, and the Network Port interrupt, are automatically cleared by a read of this register. The individual interrupt enables are not affected. No transmit okay interrupt. Transmit okay interrupt. No transmit error interrupt. Transmit error interrupt. No transmit pause interrupt. Transmit pause interrupt (control frame complete). This bit is reserved and will always read as zero. The Network Port interrupt is disabled. The Network Port uses Interrupt Priority 1. The Network Port uses Interrupt Priority 2. The Network Port uses Interrupt Priority 3.
268
Network Port B Command Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3:1 0 0 1 No operation. Transmit start command. No operation.
(NBCR) Description
(Address = 0x0206)
Transmit PAUSE control frame command. No operation. Transmit half-duplex backpressure. No operation. Transmit FIFO purge command. These bits are ignored and should always be written as zeros. No operation. Receive FIFO purge command.
Network Port B Transmit Pause LSB Register Bit(s) 7:0 Value
(NBTPLR) Description
(Address = 0x0208)
LSB of parameter sent in PAUSE control frame.
Network Port B Transmit Pause MSB Register Bit(s) 7:0 Value
(NBTPMR) Description
(Address = 0x0209)
MSB of parameter sent in PAUSE control frame.
269
Network Port B Transmit Control Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:0 Disable transmit FIFO.
(NBTCR) Description
(Address = 0x020A)
DMA request when frame transmission is complete. Reserved. Reserved. Start transmit on command only. Start transmit on command or Last Byte written. Start transmit on command, when FIFO is half full, or Last Byte written. Start transmit on command, when FIFO is one-fourth full, or Last Byte written. These bits are reserved and should be written with zeros.
Network Port B Receive Control Register Bit(s) 7:6 Value 00 01 10 11 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 Disable receive FIFO.
(NBRCR) Description
(Address = 0x020B)
DMA request when frame reception is complete. DMA request when FIFO is half full or frame reception is complete. DMA request when FIFO is one-fourth full or frame reception is complete. Normal receiver operation. Place receiver in Monitor Mode. Receiver operates normally, but does not buffer frames to memory. Receive frames less than 64 bytes in length discarded. Receive frames as short as 8 bytes accepted. Receive frames with errors discarded. Reclaim buffer space. Receive frames with errors accepted. Do not reclaim buffer space. Receive frames with broadcast address ignored. Receive frames with broadcast address accepted Receive frames with multicast addresses ignored. Receive frames with multicast addresses accepted if passing hashing filter. Receive frames with mismatched physical addresses are ignored. Receive frames with any physical address accepted. Promiscuous mode.
270
Network Port B Transmit Extra Status Register (NBTESR) Bit(s) 7 6 0 1 5 0 1 4 0 1 3:0 Value Description
(Address = 0x020C))
This bit is are reserved and will always be read as zero. No transmit length out-of-range, or not checked. Transmit frame had length out-of-range error. No transmit length check error, or transmit length not checked. Transmit frame had length check error. No transmit CRC error, or transmit CRC not checked. Transmit frame had CRC error. Transmit frame collision count.
Network Port B Physical Address x Register
(NBPA0R) (NBPA1R) (NBPA2R) (NBPA3R) (NBPA4R) (NBPA5R) Description
(Address = 0x0210) (Address = 0x0211) (Address = 0x0212) (Address = 0x0213) (Address = 0x0214) (Address = 0x0215)
Bit(s) 7:0
Value Write
Byte of physical address for receive address filtering.
Network Port B Multicast Filter x Register
(NBMF0R) (NBMF1R) (NBMF2R) (NBMF3R) (NBMF4R) (NBMF5R) (NBMF6R) (NBMF7R) Description
(Address = 0x0218) (Address = 0x0219) (Address = 0x021A) (Address = 0x021B) (Address = 0x021C) (Address = 0x021D) (Address = 0x021E) (Address = 0x021F)
Bit(s)
Value
7:0
Write
Eight bits of the multicast filter. At the end of a received multicast address, the upper six bits of CRC are used as an index into this 64-bit table. If the corresponding bit is zero, the frame is discarded. If the corresponding bit is one, the frame is accepted.
271
Network Port B Direct Rx Register Bit(s) 7:4 3 2 1 0 Value Read Read Read Read Read
(NBDRR) Description
(Address = 0x0228)
Returns the state of the RXD pins. Returns the state of the RX_ER pin. Returns the state of the RX_DV pin. Returns the state of the RX_CLK pin. Returns the state of the CRS pin.
Network Port B Direct Tx Register Bit(s) 7:4 3 2 1 0 Value Write Write Write Read Read
(NBDTR) Description
(Address = 0x0229)
Controls the state of the TXD pins if both network ports are disabled. Controls the state of the TX_ER pin if both network ports are disabled. Controls the state of the TX_EN pin if both network ports are disabled. Returns the state of the TX_CLK pin. Returns the state of the COL pin.
Network Port B Direct MII Register Bit(s) 7:4 3 2 1 0 Write Write Write Read Value
(NBDMR) Description
(Address = 0x022A)
These bits are reserved and should be written with zeros. Reads return zeros. Controls the state of the MDO pin if both network ports are disabled. Controls the state of the MDOEN pin if both network ports are disabled. Controls the state of the MDC pin if both network ports are disabled. Returns the state of the MDI pin.
272
Network Port B Configuration 0 Register Bit(s) 7:5 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 Value
(NBCF0R) Description
(Address = 0x0240)
These bits are ignored and will always return zeros when read. Disable loopback. Enable loopback. Disable transmit flow control. Enable transmit flow control (PAUSE control frames). Disable receive flow control. Enable receive flow control (PAUSE control frames). Pass normal receive frames only. Pass all receive frames (normal or control). Disable receiver. Enable receiver.
Network Port B Configuration 1 Register Bit(s) 7 Value 0 1 6 0 1 5:4 3 0 1 2 0 1 1 0 1 0 0 1 No operation. Reset entire MAC. No operation.
(Address = 0x0241)
Reset transmit random number generator. These bits are ignored and will always return zeros when read. No operation. Reset MAC control sublayer/receive domain logic. No operation. Reset receiver. No operation. Reset MAC control sublayer/transmit domain logic. No operation. Reset transmitter.
273
Network Port B Configuration 2 Register Bit(s) 7:5 Value xx0 001 x11 101 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(Address = 0x0242)
Disable transmit pad operation. Check CRC if not appended. Pad transmit frames to 60 bytes, append CRC. Pad transmit frames to 64 bytes, append CRC. Pad transmit frames to 60 bytes (not VLAN tagged) or 64 bytes (VLAN tagged), append CRC. Disable transmit CRC insertion. Enable transmit CRC insertion. Must be set if bit 5 is set. Normal 802.3 frame structure. Enable 4-byte header (ignored by CRC). Normal 802.3 frame length restrictions. Enable huge frames (transmit and receive). Disable frame length checking. Enable frame length checking (transmit and receive). Enable half-duplex. Enable full-duplex.
Network Port B Configuration 3 Register Bit(s) 7 6 0 1 5 0 1 4 0 1 3:2 1 0 1 0 0 1 Value
(Address = 0x0243)
This bit is ignored and will always return zero when read. Abort transmit on excessive deferral. Defer to carrier indefinitely. Normal transmit operation after back-pressure collision. Enable immediate transmission after back-pressure collision. Normal 802.3 back-off operation. Enable immediate retransmit (no back-off). These bits are ignored and will always return zeros when read. Disable preamble length limit checking. Enable preamble length limit checking (12 bytes or less only). Disable preamble checking. Enable preamble checking.
274
Network Port B Gap 0 Register Bit(s) 7 6:0 Value
(NBG0R) Description
(Address = 0x0244)
This bit is ignored and will always return zero when read. Back-to-back interpacket gap. Recommended values are 0x15 for full-duplex operation, and 0x12 for half-duplex operation. These values result in 9.6 s for 10 Mbits/s and 0.96 s for 100 Mbits/s, as specified by 802.3.
(NBG2R) Description
(Address = 0x0246)
This bit is ignored and will always return zero when read. Non-back-to-back interpacket gap for carrier deference. Recommended value is 0x0C, as specified by 802.3.
(NBG1R) Description
(Address = 0x0247)
This bit is ignored and will always return zero when read. Non-back-to-back interpacket gap. Recommended value is 0x12. This value results in 9.6 s for 10 Mbits/s and 0.96 s for 100 Mbits/s, as specified by 802.3.
Network Port B Retransmit Max Register Bit(s) 7:4 3:0 Value
(NBRMR) Description
(Address = 0x0248)
These bits are ignored and will always return zero when read. Number of retransmission attempts after a collision before aborting. Default (and value specified by 802.3) is 0xF.
Network Port B Collision Window Register Bit(s) 7:6 5:0 Value
(NBCWR) Description
(Address = 0x0249)
These bits are ignored and will always return zero when read. Collision window (slot time). Default (and value specified by 802.3) is 0x37.
275
Network Port B Frame Limit LSB Register Bit(s) 7:0 Value
(NBFLLR) Description
(Address = 0x024A)
LSB of maximum frame length.
Network Port B Frame Limit MSB Register Bit(s) 7:0 Value
(NBFLMR) Description
(Address = 0x024B)
MSB of maximum frame length. Default (and value specified by 802.3) is 0x0600.(1536), including preamble, address, length, and CRC fields. Should not be less than 0x05EE (1518) for normal operation.
Network Port B MII Configuration Register Bit(s) 7:5 4:2 000 001 010 011 100 101 110 111 1 0 1 0 0 1 Value
(NBMCFR) Description
(Address = 0x0250)
These bits are ignored and will always return zeros when read. MII Management Clock is system clock divided by 4. This value is reserved and should not be used. MII Management Clock is system clock divided by 6. MII Management Clock is system clock divided by 8. MII Management Clock is system clock divided by 10. MII Management Clock is system clock divided by 14. MII Management Clock is system clock divided by 20. MII Management Clock is system clock divided by 28. Enable MII frame preambles. Disable MII frame preambles. Disable MII scan function. Enable MII scan function.
Network Port B MII Reset Register Bit(s) 7 Value 0 1 6:0 No operation.
(NBMRR) Description
(Address = 0x0251)
Reset the MII management module. These bits are ignored and will always return zeros when read.
276
Network Port B MII Command Register Bit(s) 7:2 1 0 1 0 0 1 Value
(NBMCR) Description
(Address = 0x0252)
These bits are ignored and will always return zeros when read. No operation. Enable scan. MII module performs continuous read cycles. No operation. Perform one MII read cycle.
Network Port B MII Register Address Register (NBMRAR) Bit(s) 7:5 4:0 Value Description
(Address = 0x0254)
These bits are ignored and will always return zeros when read. MII register address.
Network Port B MII PHY Address Register Bit(s) 7:5 4:0 Value
(NBMPAR) Description
(Address = 0x0255)
These bits are ignored and will always return zeros when read. MII PHY address.
Network Port B MII Write LSB Register Bit(s) 7:0 Value LSB of MII write data.
(NBMWLR) Description
(Address = 0x0256)
Network Port B MII Write MSB Register Bit(s) 7:0 Value
(NBMWMR) Description
(Address = 0x0257)
MSB of MII write data. Writing to this register triggers an MII write cycle.
Network Port B MII Read LSB Register Bit(s) 7:0 Value LSB of MII read data.
(NBMRLR) Description
(Address = 0x0258)
277
Network Port B MII Read MSB Register Bit(s) 7:0 Value MSB of MII read data.
(NBMRMR) Description
(Address = 0x0259)
Network Port B MII Status Register Bit(s) 7:4 3 0 1 2 0 1 1 0 1 0 0 1 Value
(NBMSR) Description
(Address = 0x025A)
These bits are ignored and will always return zeros when read. MII link okay. MII link fail. MII read data valid. MII read data not valid. MII not busy scanning. MII scan operation in progress. MII not busy performing a read or write cycle. MII busy performing a read or write cycle.
Network Port B Station Address x Register
(NBSA0R) (NBSA1R) (NBSA2R) (NBSA3R) (NBSA4R) (NBSA5R) Description
(Address = 0x0260) (Address = 0x0261) (Address = 0x0262) (Address = 0x0263) (Address = 0x0264) (Address = 0x0265)
Bit(s) 7:0
Value
Byte of physical address for transmit control frames.
278
Enable Network Port Register Bit(s) 7:6 Value 00 01 10 11 5:2 1:0 0 00 01 10 11
(ENPR) Description
(Address = 0x0430)
Disable both Network Port B and Network Port C. Enable Network Port B (the 10/100Base-T Ethernet port). Enable Network Port C (the Wi-Fi port). This bit combination is forced whenever either SCFG pin is high.* This bit combination is reserved and must not be used. These bits are reserved and should be written with zeros. Network Port C interrupts are disabled. Network Port C interrupts use Interrupt Priority 1. Network Port C interrupts use Interrupt Priority 2. Network Port C interrupts use Interrupt Priority 3.
* Customers wishing to incorporate the Wi-Fi peripheral in their own design should contact Rabbit for more information.
279
280
23. 802.11B/G WIRELESS

23.1 Overview
Network Port C implements an 802.11b/g compatible wireless LAN radio. It consists of a baseband processor, high-speed A/D and D/A converters, and an interface for one of several external radio-frequency (RF) transceivers. The external transceiver is responsible for the up-conversion and down-conversion of the RF signal. The receiver and transmitter each have a 2048-byte FIFO that is shared with the Ethernet peripheral; the I/O pins are also shared. Because of this, only one of the two network peripherals can be enabled at any particular time. Communication with the external transceiver is accomplished through a 3-wire serial interface. Support is also provided for a parallel automatic gain control feedback loop. Control for multiple antennas is available, providing support for separate receive and transmit antennas or switched antenna diversity reception. The MAC processing is handed by a combination of the baseband processor and software on the Rabbit; any timing-critical MAC operations are handled automatically by the baseband. These operations include time management and transmission-interval spacing. The MAC also performs the CRC check of all received frames and handles the virtual carrier sense functionality. The Rabbit 5000 supports both the infrastructure and the ad-hoc modes. Multicast transmissions are supported as well. The external interface to the external transceiver consists of 20 digital pins and 8 analog pins. A 20 MHz clock is required as an input. A separate low-speed A/D converter is available to monitor the transmit power via software. The wireless peripheral also contains an AES encryption/decryption engine for both transmitted and received packets. Up to four expanded keys can be stored in the peripheral at one time.
Chapter 23 802.11b/g Wireless
281

802.11b/g Wireless LAN
Baseband Control
Transceiver Control
Baseband Receiver
Rx FIFO 2048 bytes AES Engine
10-bit ADC
Tx FIFO 2048 bytes
Baseband Transmitter
10-bit DAC
282
23.1.2 Registers
Register Name Enable Network Port Register Network Port C Version 0 Register Network Port C Version 1 Register Network Port C General Control 0 Register Network Port C General Control 1 Register Network Port C General Control 2 Register Network Port C General Control 3 Register Network Port C General Status 0 Register Network Port C General Status 1 Register Network Port C General Status 2 Register Network Port C General Status 3 Register Network Port C RSSI 0 Register Network Port C RSSI 1 Register Network Port C RSSI 2 Register Network Port C RSSI 3 Register Network Port C Interrupt Mask Register Network Port C Interrupt Status Register Network Port C SPI Data 0 Register Network Port C SPI Data 1 Register Network Port C SPI Data 2 Register Network Port C SPI Data 3 Register Network Port C SPI Control Register Network Port C Data FIFO 0 Register Network Port C Configuration-1 Register 0 Network Port C Configuration-1 Register 1 Network Port C Configuration-1 Register 2 Network Port C Configuration-1 Register 3 Network Port C Configuration-2 Register 0 Network Port C Configuration-2 Register 1 Network Port C Configuration-2 Register 2 Network Port C Configuration-2 Register 3 Network Port C AES FIFO Register
Mnemonic ENPR NCV0R NCV1R NCGC0R NCGC1R NCGC2R NCGC3R NCGS0R NCGS1R NCGS2R NCGS3R NCRSSI0R NCRSSI1R NCRSSI2R NCRSSI3R NCIMR NCISR NCSPID0R NCSPID1R NCSPID2R NCSPID3R NCSPICR NCDFR NCC1R0 NCC1R1 NCC1R2 NCC1R3 NCC2R0 NCC2R1 NCC2R2 NCC2R3 NCAFR
I/O Address 0x0430 0x0A00 0x0A01 0x0A04 0x0A05 0x0A06 0x0A07 0x0A08 0x0A09 0x0A0A 0x0A0B 0x0A0C 0x0A0D 0x0A0E 0x0A0F 0x0A10 0x0A14 0x0A18 0x0A19 0x0A1A 0x0A1B 0x0A1C 0x0A20 0x0A28 0x0A29 0x0A2A 0x0A2B 0x0A2C 0x0A2D 0x0A2E 0x0A2F 0x0A30
R/W R/W R R R/W R/W R/W R R R/W R/W R/W R R R R R/W R/W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000 00000000 00000001 00000000 01000000 01111111 00110111 00010000 00000000 00000000 00110000 01111111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011000 00000000 00101100 00000000 01000011 10000000 00010100 10110011 10000010 00001000 xxxxxxxx
283
Register Name Network Port C AES Mode Register Network Port C Output Control Register 0 Network Port C Output Control Register 1 Network Port C Output Control Register 2 Network Port C Output Control Register 3 Network Port C Station ID x Register Network Port C BSS ID x Register
Mnemonic NCAMR NCOCR0 NCOCR1 NCOCR2 NCOCR3 NCSTAIDxR NCBSSIDxR
I/O Address 0x0A38 0x0A3C 0x0A3D 0x0A3E 0x0A3F 0x0A400x0A45 0x0A480x0A4D 0x0A50 0x0A51 0x0A53 0x0A56 0x0A57 0x0A58 0x0A59 0x0A5A 0x0A5B 0x0A5C 0x0A5D 0x0A5E 0x0A5F 0x0A6C 0x0A67 0x0A6A 0x0A6B 0x0A6D 0x0A6E 0x0A6F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000 00000001 00000000 00000000 00000000 xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
Network Port C OFDM Basic Rate Set Register NCOFDMBRSR Network Port C PSK Basic Rate Set Register Network Port C SSID Length Register Network Port C Backoff 0 Register Network Port C Backoff 1 Register Network Port C DTIM Period Register Network Port C CFP Period Register Network Port C Listen Interval 0 Register Network Port C Listen Interval 1 Register Network Port C Beacon Interval 0 Register Network Port C Beacon Interval 1 Register Network Port C CFP Max Duration 0 Register Network Port C CFP Max Duration 1 Register Network Port C MAC Status Register Network Port C MAC Control Register Network Port C Remaining Backoff 0 Register Network Port C Remaining Backoff 1 Register Network Port C Beacon Filter Register Network Port C Beacon Backoff 0 Register Network Port C Beacon Backoff 1 Register NCPSKBRSR NCSSIDLR NCBO0R NCBO1R NCDTIMPR NCCFPPR NCLI0R NCLI1R NCBI0R NCBI1R NCCFPMD0R NCCFPMD1R NCMACSR NCMACCR NCRBO0R NCRBO1R NCBFR NCBBO0R NCBBO1R
284
23.2 Dependencies
23.2.1 I/O Pins The wireless network port interface has 28 dedicated pins, as shown in Table 23-1. Of those, 20 are digital and can be used as general-purpose I/O via NBDRR, NBDTR, and NBDMR if the network port is not being used.
Table 23-1. Wireless Port Interface
Block Section Signal VINQP VINQN Input VINIP VININ Analog Output VOUTPI VOUTNI Clock Auto Gain Correction CLK_IN VGA[4:0] LNA[1:0] TX_ON RX_ON LOCK RXHP Control Digital ANT_SEL /ANT_SEL PA2G_ON PA5G_ON ACT_LED BOOTMUX SCLK Management SDATA /SEN Output I channel differential output Output Input Output Output Output Output Input Output Output Output Output Output Output Output Output Output Output 20 MHz clock input Variable gain amplifier setting Linear amplifier setting Transmit enable Receive enable Transceiver PLL lock input Reserved for future use, may be used as a general-purpose output Antenna select enable Antenna select enable 2G preamplifier enable 5G preamplifier enable Activity LED control General-purpose output 3-wire serial clock 3-wire serial data 3-wire serial enable VOUTPQ VOUTNQ Input I channel differential input Input Output Q channel differential output Output Direction Input Q channel differential input Input Function
285
23.3 Clocks
The wireless network port requires a 20 MHz clock input at CLK_IN for proper operation. 23.3.1 Other Registers
Register EDMR NCWR Function Enable Wi-Fi functionality. Set Network Port C wait states (015).
23.3.2 Interrupts The wireless network interrupt can be generated for any of the following reasons. When data are available in the receive FIFO. When the transmit FIFO becomes empty. When a receive timeout occurs. When a transmit abort occurs. When an Announcement Traffic Indication Message (ATIM) is received. When the receive FIFO is overrun. When a complete packet is received. The events that generate an interrupt can be selected in NCISR. The wireless network port interrupt vector is shared with the Ethernet network port. It is located in the IIR at offset 0x1E0. It can be set as Priority 1, 2, or 3 by writing to ENPR.
23.4 Operation
At the present time, the wireless peripheral is intended to be used only in Rabbit-branded and other products offered by Digi International. The information provided in the Rabbit 5000 Microprocessor Users Manual should be sufficient to explain the operation of the wireless peripheral in these products. Customers wishing to incorporate the wireless peripheral in their own design should contact Rabbit for more information.
286
24. INPUT CAPTURE

24.1 Overview
The input capture peripheral consists of two channels, each of which contains a 16-bit counter and edge-detection circuitry. The input capture channels are usually used to determine the time between events. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 12 input pins that can be selected as the input for either of the two channels. A digital low-pass filter is present on the inputs, as explained in Section 24.2.4. Each channel can be used in one of two modesinput capture or input count. In the inputcapture mode, the channel starts/stops the counter (clocked by Timer A8) according to the signal edges on various parallel port pins, providing the ability to measure pulse widths and time intervals between external events, time-stamp signal changes on a pin, and measure time intervals between a software start and an external event. An interrupt can also be generated when an edge is detected or when a counter rolls over In the input-count mode the channel simply increments the counter each time a desired edge is detected. The start condition is enabled by the first Timer A8 clock after the mode is selected and the stop condition generated when the count matches the value written into the counter registers; this allows an interrupt to be generated when a particular count is reached. A 16 bit counter is used to record the time at which the event takes place. The counter is driven by the output of Timer A8 and can be set to count at a rate ranging from the full clock speed (perclk/2) down to 1/256 the clock speed (perclk/512). Two events are recognized: a start condition and a stop condition. The start condition may be used to start counting and the stop condition to stop counting. However, the counter may also run continuously or run until a stop condition is encountered. The start and stop conditions may also be used to latch the current time at the instant the condition occurs rather than actually start or stop the counter. The same pin may be used to detect the start and stop conditionfor example a rising edge could be the start condition and a falling edge could be the stop condition. The start and stop condition can also be the input from separate pins. The input capture channels can be used to measure the width of fast pulses. This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse. In this case the maximum error in the measurement is approximately 2 periods of the clock used to count the counter. If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on
Chapter 24 Input Capture 287
either start or stop conditions (or both) and cause an interrupt each time the count is captured. The counter can also be cleared and started under software control and then have its value captured in response to an input. The capture counter can synchronized with Timer B outputs to load parallel port output registers. This makes it possible to generate an output signal precisely synchronized with an input signal. Usually it will be desired to synchronize one of the input capture counters with the Timer B counter. The count offset can be measured by outputting a pulse at a precise time using Timer B to set the output time and capturing the output pulse with an input capture channel. Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured, provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B. The minimum time delay needed is probably less than 10 s if the software is done carefully and the clock speed is reasonably high. 24.1.1 Block Diagram
Input Capture Channel x ICCSR 1 perclk Timer A8 TAT8R Count Capture Counter ICMxR ICLxR
Parallel Port Pins
Input Select ICSxR
Trigger ICTxR
Interrupt Generation ICCSR
Interrupt Request
288
24.1.2 Registers
Register Name Input Capture Ctrl/Status Register Input Capture Control Register Input Capture Trigger 1 Register Input Capture Source 1 Register Input Capture LSB 1 Register Input Capture MSB 1 Register Input Capture Trigger 2 Register Input Capture Source 2 Register Input Capture LSB 2 Register Input Capture MSB 2 Register Mnemonic ICCSR ICCR ICT1R ICS1R ICL1R ICM1R ICT2R ICS2R ICL2R ICM2R I/O Address 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F R/W R/W W R/W R/W R R R/W R/W R R Reset 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx
Chapter 24 Input Capture
289
24.2 Dependencies
24.2.1 I/O Pins Each input-capture channel can accept input from one of the following parallel port pins: PC1, PC3, PC5, PC7, PD1, PD3, PD5, PD7, PE1, PE3, PE5, PE7. Use ICTxR to select which input pin to trigger on. Note that these pins can be used for other peripherals at the same time as the input-capture peripheral. For example, you can use input capture to use measure the pulse width on a serial port input to measure the baud rate. 24.2.2 Clocks The 16-bit input-capture counters are clocked from the output of Timer A8, and can run at rates from perclk/2 down to perclk/512 by writing the appropriate value to TAT8R. 24.2.3 Other Registers
Register TAT8R Function Time constant for input-capture clock.
24.2.4 Interrupts Each input capture channel can generate an interrupt whenever a start/stop condition occurs. The interrupt request is cleared when ICCSR is read. The input capture interrupt vector is in the IIR at offset 0x1A0. It can be set as Priority 1, 2, or 3. The input-capture channels synchronize their inputs to the peripheral clock (further divided by Timer A8). Since the inputs are only sampled in synch with the peripheral clock, any faster state faster changes cannot be detected, which is akin to a digital lowpass filter functionality on the inputs. Because of this, there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR.
PERI CLOCK TIMER A8 CPT INPUT INTERRUPT
290
24.3 Operation
24.3.1 Input-Capture Channel The following steps explain how to set up an input-capture channel. 1. Configure Timer A8 via TAT8R to provide the desired input-capture clock. 2. Configure ICTxR to provide the desired start/stop operation and conditions. 3. Configure ICSxR to select the input pins for the start and stop conditions. 4. Configure ICCR to select either the count or the capture mode. 5. Reset the counter by writing to ICCSR. 24.3.2 Handling Interrupts The following steps explain how an interrupt is used. 1. Write the vector to the interrupt service routine to the internal interrupt table 2. Configure the Input Capture Control/Status Register (ICCSR) to select events that will generate an interrupt. 3. Configure the Input Capture Control Register (ICCR) to select the interrupt priority (note that interrupts will be enabled once this value is set; this step should be done last). The following actions occur within the interrupt service routine. If needed, the current counter value can be read from ICLxR and LCMxR (reading from ICLxR latches the value of ICLxR, so ICLxR should always be read first) If the counter is expected to roll over, determine if that is why the interrupt occurred by reading the status bits in ICCSR and adjusting any software counters accordingly The interrupt request should be cleared by reading from ICCSR 24.3.3 Example ISR A sample interrupt handler is shown below.
ic_isr:: push af ioi ld a, (ICCSR)
; clear the interrupt request and get status
; determine which interrupts have occurred ; if rollover, perform any necessary software counter adjustments here ; read counter values pop af ipres ret
291
24.3.4 Capture Mode

Pulse Width or Time Between Events
The following steps explain how to measure the pulse width or time between events. 1. Select the same input pin to perform a pulse-width measurement between the start and stop conditions, or select two different input pins to measure time between events on those pins. 2. Set the counter to start on the start condition and stop on the stop condition, latch on the stop condition, and generate an interrupt on the stop condition. 3. In the interrupt handler, read out the counter to determine the pulse width or time interval between the two events.
Time-Stamp External Events
The following steps explain how to time-stamp external events. 1. Set the trigger for the desired event type. 2. Set the counter to run continuously, latch on the start (and/or stop) condition, and generate an interrupt on the start (and/or stop) condition 3. In the interrupt handler, read out the counter as an event timestamp.
Measure Time Interval from a Software Start to an External Event
The following steps explain how to measure the time interval between a software start and the occurrence of an external event. 1. Set up the counter to run continuously, latch on the stop condition, and generate an interrupt on the stop condition. 2. Set up the stop condition for the event of interest. 3. Reset the counter via ICCSR at the software start. 4. In the interrupt handler, read the counter as a time duration. 24.3.5 Count Mode The following steps explain how to count pulses. 1. Set the counter to run continuously until the stop condition occurs and to latch on the start condition. 2. If an interrupt is desired at a particular count, write that value into the LSB and MSB registers. 3. Set the start condition for the pulse type desired. 4. Reset the counter by writing to ICCSR. 5. Reading the counter at any time will give the current count.
292

Input Capture Control/Status Register Bit(s) 7 (Read) 6 (Read) 5 (Read) 4 (Read) 3 (Read) 2 (Read) 7:2 (Read) 7:4 (Write) 3 (Write) 2 (Write) 1:0 0 1 0 1 0 1 Value 0 1 0 1 0 1 0 1 0 1 0 1 (ICCSR) Description The Input Capture 2 Start condition has not occurred. The Input Capture 2 Start condition has occurred. The Input Capture 2 Stop condition has not occurred. The Input Capture 2 Stop condition has occurred. The Input Capture 1 Start condition has not occurred. The Input Capture 1 Start condition has occurred. The Input Capture 1 Stop condition has not occurred. The Input Capture 1 Stop condition has occurred. The Input Capture 2 counter has not rolled over to all zeros. The Input Capture 2 counter has rolled over to all zeros. The Input Capture 1 counter has not rolled over to all zeros. The Input Capture 1 counter has rolled over to all zeros. These status bits (but not the interrupt enable bits) are cleared by the read of this register, as is the Input Capture Interrupt. The corresponding Input Capture interrupt is disabled. The corresponding Input Capture interrupt is enabled. No effect on Input Capture 2 counter. This bit always reads as zero. Reset Input Capture 2 counter to all zeros and clears the rollover latch. No effect on Input Capture 1 counter. This bit always reads as zero. Reset Input Capture 1 counter to all zeros and clears the rollover latch. These bits are reserved and should be written with zeros. These bits will always be read as zeros. (Address = 0x0056)
293
Input Capture Control Register Bit(s) 7 Value 0 1 6 0 1 5:2 1:0 00 01 10 11
(ICCR) Description
(Address = 0x0057)
Input Capture operation for Input Capture 2. Input Count operation for Input Capture 2. Input Capture operation for Input Capture 1. Input Count operation for Input Capture 1. These bits are reserved and should be written with zero. Input Capture interrupts are disabled. Input Capture interrupt use Interrupt Priority 1. Input Capture interrupt use Interrupt Priority 2. Input Capture interrupt use Interrupt Priority 3.
294
Input Capture Trigger x Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(ICT1R) (ICT2R) Description
(Address = 0x0058) (Address = 0x005C)
Disable the counter. Applies even in Counter operation. The counter runs from the Start condition until the Stop condition. The counter runs continuously. The counter runs continuously, until the Stop condition. Disable the count latching function. In this case, and with Counter operation only, the ICLxR and ICMxR return the programmed match value. Latch the count on the Stop condition only. Latch the count on the Start condition only. Latch the count on either the Start or Stop condition. Ignore the starting input. The Start condition is the rising edge of the starting input. The Start condition is the falling edge of the starting input. The Start condition is either edge of the starting input. Ignore the ending input. These two bits are ignored in Counter operation. The Stop condition is the rising edge of the ending input. The Stop condition is the falling edge of the ending input. The Stop condition is either edge of the ending input.
295
Input Capture LSB x Register Bit(s) Value
(ICL1R) (ICL2R) Description
(Address = 0x005A) (Address = 0x005E)
7:0
Read
The least significant eight bits of the latched Input Capture count are returned. Reading the LSB of the count latches the MSB of the count to avoid reading stale data. Reading the MSB of the count opens these latches on the MSB of the count. In Counter operation, if no latching condition is specified the value written to this register is returned. The eight LSBs of the match value for counter mode are stored.
Write
296
Input Capture MSB x Register Bit(s) 7:0 Value Read Write
(ICM1R) (ICM2R) Description
(Address = 0x005B) (Address = 0x005F)
The most significant eight bits of the latched Input capture count are returned. In Counter operation, if no latching condition is specified the value written to this register is returned. The eight MSBs of the match value for counter mode are stored.
297
298
25. QUADRATURE DECODER

25.1 Overview
The Rabbit 5000 has a two-channel Quadrature Decoder that accepts inputs via specific pins on Parallel Ports D and E. Each channel has two inputs, the in-phase (I) input and the 90 degree or quadrature-phase (Q) input. An 8 or 10-bit up/down counter counts encoder steps in the forward and backward directions, and provides interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00. An interrupt can occur each time the count overflows or underflows. The Quadrature Decoder contains digital filters on the inputs to prevent false counts. The external signals are synchronized with an internal clock provided by the output of Timer A10. Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower nibble of Parallel Ports D and E. The I signal is input on an odd-numbered port bit, while the Q signal is input on an even-numbered port bit. There is also a disable selection, which is guaranteed not to generate a count increment or decrement on either entering or exiting the disabled state. The operation of the counter as a function of the I and Q inputs is shown below.
I Q
INPUT INPUT
8-BIT COUNTER FF 00 01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF 10-BIT COUNTER 3FF

000 001 002 003 004 005 006 007 008 007 006 005 004 003 002 001 0003FF
Interrupt
Interrupt
Chapter 25 Quadrature Decoder
299
The Quadrature Decoders are clocked by the output of Timer A10, giving a maximum clock rate from perclk/2 down to perclk/512. The time constant of Timer A10 must be fast enough to sample the inputs properly. Both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock period wide. In addition, the clock rate must be high enough that transitions on the I and Q inputs are sampled in different clock cycles. Input capture may be used to measure the pulse width on the I inputs because they come from the odd-numbered port bits. The operation of the digital filter is shown below.
PERI CLOCK TIMER A10 REJECTED ACCEPTED
The Quadrature Decoder generates an interrupt when the counter increments from 0xFF (0x3FF in 10-bit mode) to 0x00, or when the counter decrements from 0x00 to 0xFF (0x3FF in 10-bit mode). The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt and status bits are cleared by reading the QDCSR.
PERI CLOCK TIMER A10 I or Q INPUT COUNTER INTERRUPT
0xFF or 0x3FF 0x00
300

Quadrature Decoder Channel x perclk Timer A10 TAT10R
Parallel Port Pins
Input Select QDCR
I Q
Counter QDSCR QDCxR QDCxHR
Interrupt Generation QDCR
Interrupt Request
25.1.2 Registers
Register Name Quad Decode Ctrl/Status Register Quad Decode Control Register Quad Decode Count 1 Register Quad Decode Count 1 High Register Quad Decode Count 2 Register Quad Decode Count 2 High Register Mnemonic QDCSR QDCR QDC1R QDC1HR QDC2R QDC2HR I/O Address 0x0090 0x0091 0x0094 0x0095 0x0096 0x0097 R/W R/W R/W R R R R Reset xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
301
25.2 Dependencies
25.2.1 I/O Pins Each Quadrature Decoder channel can accept the two encoder inputs from one of three different locations, as shown in the table below. Each channel can select a different input option. Note that these pins can be used for other peripherals at the same time as the Quadrature Decoder peripheral; one example of this use is to use measure pulse width on the I channels with the input capture peripheral.
Channel 1 Inputs I Option 1 Option 2 Option 3 PD1 PE1 PE5 Q PD0 PE0 PE4 I PD3 PE3 PE7 Q PD2 PE2 PE6 Channel 2
25.2.2 Clocks The 8/10-bit Quadrature Decoder counters are clocked from the output of Timer A10, and can run at rates from the peripheral clock divided by 2 down to the peripheral clock divided by 512 by writing the appropriate value to TAT10R. The clock rate must be high enough that transitions on the inputs are sampled in different clock cycles. In addition, both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock periods wide. 25.2.3 Other Registers
Register TAT10R Function Time constant for Quadrature Decoder clock
25.2.4 Interrupts Each Quadrature Decoder channel can generate an interrupt whenever the counter increments from 0x0FF (0x3FF in 10-bit mode) to 0x00 or when the counter decrements from 0x000 to 0x0FF (0x3FF for 10-bit mode). The interrupt request is cleared when QDCSR is read. The Quadrature Decoder interrupt vector is in the IIR at offset 0x190. It can be set as Priority 1, 2, or 3. The status bits in the QDCSR are set coincident with the interrupt request and are reset when QDCSR is read.
302
25.3 Operation
The following steps explain how to set up a Quadrature Decoder channel. 1. Configure Timer A10 via TAT10R to provide the desired Quadrature Decoder clock speed. 2. Configure QDCR to select the input pins for the two channels. 3. Reset the counters by writing to QDCSR. 25.3.1 Handling Interrupts The following steps explain how an interrupt is set up and used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Configure QDCR to select the interrupt priority (note that interrupts will be enabled once this value is set). The following actions occur within the interrupt service routine. Since a Quadrature Decoder interrupt occurs when the counter rolls over, determine exactly why the interrupt occurred by reading the status bits in QDCSR and adjust any software counters accordingly. This will also clear the interrupt request. The current counter value can be read from QDCxR (and QDCxHR if the 10-bit counter is enabled). 25.3.2 Example ISR A sample interrupt handler is shown below.
qd_isr:: push af ioi ld a, (QDCSR) ; save used registers ; clear the interrupt request and get status
; perform any necessary software counter adjustments here ; read current counter value(s) pop af ipres ret ; restore used registers
303

Quad Decode Control/Status Register Bit(s) 7 (Readonly) 6 (Readonly) 5 4 (Writeonly) 3 (Readonly) 2 (Readonly) 1 0 (Writeonly) 0 1 0 1 0 1 0 1 Value 0 1 0 1 (QDCSR) Description Quadrature Decoder 2 did not increment from the maximum count. Quadrature Decoder 2 incremented from the maximum count to 0x000. This bit is cleared by a read of his register. Quadrature Decoder 2 did not decrement from zero. Quadrature Decoder 2 decremented from zero to the maximum count. This bit is cleared by a read of this register. This bit always reads as zero. No effect on the Quadrature Decoder 2. Reset Quadrature Decoder 2 to all zeros, without causing an interrupt. Quadrature Decoder 1 did not increment from the maximum count. Quadrature Decoder 1 incremented from the maximum count to zero. This bit is cleared by a read of this register. Quadrature Decoder 1 did not decrement from zero. Quadrature Decoder 1 decremented from zero to the maximum count. This bit is cleared by a read of this register. This bit always reads as zero. No effect on the Quadrature Decoder 1. Reset Quadrature Decoder 1 to all zeros, without causing an interrupt. (Address = 0x0090)
304
(QDCR) Description
(Address = 0x0091)
Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 7 and 6. Eight bit quadrature decoder counters (both channels). Ten bit quadrature decoder counters (both channels). This bit is reserved and should be written as zero. Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement. Quadrature Decoder 1 inputs from Parallel Port D bits 1 and 0. Quadrature Decoder 1 inputs from Parallel Port E bits 1 and 0. Quadrature Decoder 1 inputs from Parallel Port E bits 5 and 4. Quadrature Decoder interrupts are disabled. Quadrature Decoder interrupt use Interrupt Priority 1. Quadrature Decoder interrupt use Interrupt Priority 2. Quadrature Decoder interrupt use Interrupt Priority 3.
Quad Decode Count Register Bit(s) 7:0 Value Read
(QDC1R) (QDC2R) Description
The current value of bits 7-0 of the Quadrature Decoder counter is reported.
Quad Decode Count High Register Bit(s) 7:2 1:0 Value Read Read
(QDC1HR) (QDC2HR) Description
These bits are reserved and will always read as zeros. The current value of bits 9-8 of the Quadrature Decoder counter is reported.
305
306
26. PULSE WIDTH MODULATOR

26.1 Overview
The Pulse Width Modulator (PWM) consists of a 10-bit free running counter and four width registers. A PWM output consists of a train of periodic pulses within a 1024-count frame with a duty cycle that varies from 1/1024 to 1024/1024. Each PWM output is high for n + 1 counts out of the 1024-clock count cycle, where n is the value held in the width register. Any changes to the width registers will not take effect until the next counter rollover. The PWM is clocked by the output of Timer A9 which is used to set the period. Each PWM output high time can optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output. The PWM outputs can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be used to directly drive devices such as motors or solenoids that have intrinsic filtering. The PWM outputs can trigger a PWM interrupt on every PWM cycle, every other cycle, every fourth cycle, or every eighth cycle. In addition, the PWM output can be suppressed every other cycle, three out of every four cycles, or seven out of every eight cycles. These options provide support for driving servos and to generate audio signals. The setup for this interrupt is done in the PWL0R and PWL1R registers. The timing is shown below.
ITERATION 0
1 2 3 4 5 6 7
1/8 OUTPUT 1/4 OUTPUT 1/2 OUTPUT 1/8 INTERRUPT 1/4 INTERRUPT 1/2 INTERRUPT
Chapter 26 Pulse Width Modulator 307
The spreading function is implemented by dividing each 1024-clock cycle into four quadrants of 256 clocks each. Within each quadrant, the Pulse-Width Modulator uses the eight MSBs of each pulse-width register to select the base width in each of the quadrants. This is the equivalent to dividing the contents of the pulse-width register by four and using this value in each quadrant. To get the exact high time, the Pulse-Width Modulator uses the two LSBs of the pulse-width register to modify the high time in each quadrant according to the table below. The n/4 term is the base count, formed from the eight MSBs of the pulse-width register.
Pulse-Width LSBs 00 01 10 11 1st n/4 + 1 n/4 + 1 n/4 + 1 n/4 + 1 n/4 n/4 n/4 + 1 n/4 + 1 2nd n/4 n/4 + 1 n/4 + 1 n/4 + 1 3rd n/4 n/4 n/4 n/4 + 1 4th
The diagram below shows a PWM output for several different width values, for both modes of operation. Operation in the spread mode reduces the filtering requirements on the PWM output in most cases.
n = 255, normal n = 255, spread n = 256, spread n = 257, spread n = 258, spread n = 259, spread n = 259, normal
(64 counts) (65 counts) (65 counts) (65 counts) (65 counts) (256 counts) (64 counts) (64 counts) (64 counts) (65 counts) (65 counts) (260 counts) (64 counts) (64 counts) (65 counts) (65 counts) (65 counts) (64 counts) (64 counts) (64 counts) (64 counts) (65 counts)
The DMA channels on the Rabbit 5000 are designed to work with fixed I/O addresses. To allow DMA control of the PWM, a separate PWM Block Access Register (PWBAR) and PWM Block Pointer Register (PWBPR) are available. The pointer register contains the address of the PWM register to be accessed via the access register. Each read or write of the access register automatically increments the pointer register through the sequence shown below. Note that only the lower three bits of the pointer register actually change. This allows the DMA to write to a fixed internal I/O location but still program all of the PWM registers. The pointer register can be written and read if necessary. Normally the
308
pointer register is initialized to 0x88 (the first PWM register) and the DMA then transfers blocks of eight bytes to completely reprogram the PWM.
0x88 -> 0x89 -> 0x8A -> 0x8B -> 0x8C -> 0x8D -> 0x8E -> 0x8F ->
When the DMA destination address is the PWBAR, the DMA request from the PWM is automatically connected to the DMA. 26.1.1 Block Diagram
Pulse Width Modulator perclk Timer A9 TAT9R Interrupt Generation PWL0R PWL1R Interrupt Request
Counter
PWM Channel x = Pulse Suppress and Spread PWLxR Output Select PyFR PyAHR
Width Register PWLxR PWMxR
26.1.2 Registers
Register Name PWM LSB 0 Register PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register PWM Block Access Register PWM Block Pointer Register Mnemonic PWL0R PWM0R PWL1R PWM1R PWL2R PWM2R PWL3R PWM3R PWBAR PWBPR I/O Address 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x00E8 0x00E9 R/W R/W R/W R/W R/W R/W R/W R/W R/W W W Reset xxxxx00x xxxxxxxx xxxxx00x xxxxxxxx xxxxx00x xxxxxxxx xxxxx00x xxxxxxxx xxxxxxxx 10001000
Chapter 26 Pulse Width Modulator
309
26.2 Dependencies
26.2.1 I/O Pins Each PWM channel can be output on up one of three pins, which can be selected via the parallel port alternate output registers.
PWM Channel 0 Channel 1 Channel 2 Channel 3 Output Pins PC4, PD4, PE4, PH4 PC5, PD5, PE5, PH5 PC6, PD6, PE6, PH6 PC7, PD7, PE7, PH7
26.2.2 Clocks The PWM counter is clocked from the output of Timer A9, and can run at rates from perclk/2 down to perclk/512 by writing the appropriate value to TAT9R. 26.2.3 Other Registers
Register TAT9R PCFR, PCAHR PDFR, PDAHR PEFR, PEAHR PHFR, PHAHR Function Time constant for PWM clock
Alternate port output selection
26.2.4 Interrupts The PWM can generate an interrupt for every PWM counter rollover, every second rollover, every fourth rollover, or every eighth rollover. This option is selected in PWL1R. The interrupt request is cleared by a write to any PWM register. The PWM interrupt vector is in the IIR at offset 0x170. It can be set as Priority 1, 2, or 3 by writing to PWL0R.
310
26.3 Operation
The following steps explain how to set up a PWM channel. 1. Configure Timer A9 via TAT9R to provide the desired PWM clock frequency. 2. Configure PWLxR to select whether to spread the PWM output throughout the cycle. 3. Configure PWLxR to select whether to suppress the PWM output. 4. Configure the duty cycle by writing to PWLxR and PWMxR. Note that any changes to these registers while the PWM is active will not take effect until the next counter rollover. 26.3.1 Handling Interrupts The following steps explain how an interrupt is set up and used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Configure PWL0R to select the PWM interrupt priority and PWL1R to select PWM interrupt suppression (if an interrupt is desired). The following actions occur within the interrupt service routine. Any PWM values may be updated. The interrupt request should be cleared by writing to any PWM register. 26.3.2 Example ISR A sample interrupt handler is shown below.
pwm_isr:: push af ld a, 0x55 ioi ld (PWM0R), a ; save used registers ; update a PWM value
; note that interrupt request is also cleared by register write above pop af ipres ret ; restore used registers
311

PWM LSB 0 Register Bit(s) 7:6 5:4 00 01 10 11 3 2:1 00 01 10 11 0 0 1 Value (PWL0R) Description Least significant two bits for the Pulse Width Modulator count. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter. This bit is ignored and should be written with zero. Pulse Width Modulator interrupts are disabled. Pulse Width Modulator interrupts use Interrupt Priority 1. Pulse Width Modulator interrupts use Interrupt Priority 2. Pulse Width Modulator interrupts use Interrupt Priority 3. PWM output High for single block. Spread PWM output throughout the cycle. (Address = 0x0088)
PWM LSB 1 Register Bit(s) 7:6 5:4 00 01 10 11 3 2:1 00 01 10 11 0 0 1 Value
(PWL1R) Description
(Address = 0x008A)
Least significant two bits for the Pulse Width Modulator count. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter. This bit is ignored and should be written with zero. Normal PWM interrupt operation. Suppress PWM interrupts seven out of eight iterations of PWM counter. Suppress PWM interrupts three out of four iterations of PWM counter. Suppress PWM interrupts one out of two iterations of PWM counter. PWM output High for single block. Spread PWM output throughout the cycle.
312
PWM LSB x Register Bit(s) 7:6 5:4 00 01 10 11 3:1 0 0 1 Value
(PWL2R) (PWL3R) Description
(Address = 0x008C) (Address = 0x008E)
Least significant two bits for the Pulse Width Modulator count. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter. These bits are ignored and should be written with zero. PWM output High for single block. Spread PWM output throughout the cycle.
PWM MSB x Register
(PWM0R) (PWM1R) (PWM2R) (PWM3R) Description
(Address = 0x0089) (Address = 0x008B) (Address = 0x008D) (Address = 0x008F)
Bit(s) 7:0
Value
Most significant eight bits for the Pulse Width Modulator count. With a count of n, the PWM output will be High for n + 1 clocks out of the 1024 clocks of the PWM counter.
PWM Block Access Register Bit(s) 7:0 Value
(PWBAR) Description
(Address = 0x00E8)
Access the PWM register pointed to by the PWBPR. The PWBPR is automatically updated to the next PWM register address in the sequence.
PWM Block Pointer Register Bit(s) 7:3 2:0 Value
(PWBPR) Description
(Address = 0x00E9)
These bits are always read as 0x11. Three least significant bits of the PWM register address for indirect access.
313
314
27. EXTERNAL I/O CONTROL

27.1 Overview
The Rabbit 5000s external I/O space consists of 64KB that is accessed by prefixing a read or write instruction with the IOE instruction. These accesses can go onto the memory bus or onto the external I/O bus (described below). There are three dedicated signal pins (/IORD, /IOWR, /BUFEN) that toggle for all external I/O accesses, and eight I/O strobes that can be associated with this external I/O space and directed out of Parallel Ports C, D, or E. In addition, a handshaking signal input can be enabled on a Parallel Port E pin, and can be used to pause an external I/O transaction until the external device is ready to complete the transaction. A timeout period can be defined to ensure that the processor is not held indefinitely by a misbehaving external device. 27.1.1 External I/O Bus The Rabbit 5000 can enable a separate external I/O bus for external devices to keep bus loading on the memory bus at an acceptable level. This bus consists of eight data lines on Parallel Port A and up to eight address lines on Parallel Port B. This functionality is mutually exclusive with the slave port and regular parallel I/O on Parallel Ports A and B. When enabled, the address lines of the external I/O bus hold their value until a new value is written to them. The data lines return to a tristate mode after each transaction. See Section 27.1.2 for memory timing for external I/O accesses.
Chapter 27 External I/O Control
315
27.1.2 I/O Strobes There are eight I/O strobes available in the Rabbit 5000. Each has a separate 8KB address range that can be enabled as a chip select, read strobe, write strobe, or a read/write strobe. The number of wait states can be set to 1, 3, 7, or 15, and the signal can be active high or low.
Table 27-1. External I/O Strobes
Register IB0CR IB1CR IB2CR IB3CR IB4CR IB5CR IB6CR IB7CR External I/O Address Range 0x00000x1FFF 0x20000x3FFF 0x50000x5FFF 0x60000x7FFF 0x80000x9FFF 0xA0000xBFFF 0xC0000xDFFF 0xE0000xFFFF
The I/O strobes can be used for devices on the memory bus or the external I/O bus, and can be enabled to go out on the memory bus alone or both buses. It is also possible to shorten the read strobe by one clock cycle and the write strobe by one-half a clock cycle by pulling in the trailing edge, which guarantees one clock cycle of hold time for transactions.
T1
Tw
T2
ADDR WRITE DATA WRITE STROBE READ DATA READ STROBE CHIP SELECT STROBE
valid valid
valid
EXTERNAL I/O TIMING (with 1 wait state)

Figure 27-1. External I/O Bus Cycles
316
The strobes can be enabled to come out on Parallel Ports C, D, or E. By default the I/O strobes are configured as read-only chip selects with 15 wait states and normal timing. These settings will affect the /IORD, /IOWR, and /BUFEN signals for external I/O writes even if no other strobe outputs are enabled in the parallel port registers. 27.1.3 I/O Handshake An external I/O handshake input can be enabled on one of the Parallel Port E pins for any combination of the I/O banks. The external device holds this signal (active high or low) when it is busy and cannot accept a transaction. The Rabbit 5000 will then hold midway through the transaction until either the handshake signal goes inactive or a timeout occurs. The timeout can be defined anywhere from 32 to 2048 clocks. When the timeout occurs, the transaction ends and a status bit is set. This bit must be checked by the program attempting the write; no interrupt is generated. The I/O handshake signal is sampled at the end of the first wait state (Tw). When the handshake signal is disabled, the transition will start at the beginning of the Tw phase and continue to completion.
T1 Tw Thalt Tw T2
ADDR WRITE DATA WRITE STROBE READ DATA READ STROBE CHIP SELECT STROBE I/O HANDSHAKE
(ACTIVE LOW)
valid valid
valid
EXTERNAL I/O HANDSHAKE
Figure 27-2. External I/O Handshake Timing Diagram
317

External I/O Control Address and Data Bank Select I/O Handshake Control IHCR I/O Handshake Select IHSR I/O Handshake Timeout IHTR I/O Bank x I/O Bank x Control IBxCR Output Select PyFR PyAHR PyALR Parallel Port E Pin Parallel Port E Pin Parallel Port E Pin Memory Bus or Parallel Ports A and B
IOE Access
External I/O Address Select IBxCR
27.1.5 Registers
Register Name I/O Handshake Control Register I/O Handshake Select Register I/O Handshake Timeout Register I/O Bank 0 Control Register I/O Bank 1 Control Register I/O Bank 2 Control Register I/O Bank 3 Control Register I/O Bank 4 Control Register I/O Bank 5 Control Register I/O Bank 6 Control Register I/O Bank 7 Control Register Mnemonic IHCR IHSR IHTR IB0CR IB1CR IB2CR IB3CR IB4CR IB5CR IB6CR IB7CR I/O Address 0x0028 0x0029 0x002A 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 R/W R/W R/W R/W W W W W W W W W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
318
27.2 Dependencies
27.2.1 I/O Pins The external I/O bus uses PA0PA7 for data, and either PB2PB7 or PB0PB7 for address lines, depending on the setting in SPCR. Address bits 6 and 7 can also be enabled on pins PD1, PD3, PD5, or PD7, which allows PB0 and PB1 to be used as clocked serial I/O instead of as external I/O. The /IOWR, /IORD, and /BUFEN pins are dedicated strobes for external I/O accesses. The I/O strobes can be directed out to pins on Parallel Ports C, D, or E; each bank can be directed to the appropriate pin (bank zero on PC0, PD0, or PE0; bank one on PC1, PD1, or PE1; etc.). The strobes will affect outputs on /IOWR, /IORD, and /BUFEN at all times. The I/O handshake can be input on any one of the Parallel Port E pins (PE0PE7). 27.2.2 Clocks All external I/O accesses, strobes, and handshake timeouts are based on the processor clock. 27.2.3 Other Registers
Register SPCR PCFR, PCALR, PCAHR PDFR, PDALR, PDAHR, PEFR, PEALR, PEAHR Function Enable the external I/O bus. Select Parallel Port C, D, or E pins as I/O strobe outputs. Select PD1, PD3, PD5, or PD7 as address bits 6-7.
27.2.4 Interrupts There are no interrupts associated with external I/O.
319
27.3 Operation
27.3.1 External I/O Bus The following steps must be taken before using external I/O bus: 1. Enable the external I/O bus by writing to SPCR. Select whether 6 or 8 address bits are desired. 2. If PB0 and PB1 are needed for clocked serial use and eight address bits are required, enable the alternate outputs of address bits 6 and 7 on Parallel Port D by writing to PDALR, PDAHR, and PDFR. 3. Set the I/O timing for a particular device by writing to the appropriate IBxCR register for the I/O bank desired. 4. If a strobe other than /IORD, /IOWR, or /BUFEN is required, enable the output of the IBxCR register by writing to the appropriate PxALR, PxAHR, and PxFR registers. Once the external I/O bus is enabled, all memory read/write instructions prefixed with an IOE will go to either the memory bus or external I/O bus, depending on the setup in that banks IBxCR register. 27.3.2 I/O Strobes The following steps must be taken before using an I/O strobe: 1. Set the strobe type and timing for a particular device by writing to the appropriate IBxCR register for the I/O bank desired. 2. If signals other than /IORD, /IOWR, and /BUFEN are required, enable the output of the IBxCR register by writing to the appropriate PxALR, PxAHR, and PxFR registers. On startup, the I/O strobes are set as chip selects with 15 wait states, read-only, active-low signaling, and will use the external I/O bus. These settings will be used for the dedicated I/O strobe pins /IORD, /IOWR, and /BUFEN whenever an external I/O write occurs even if not I/O strobe signals are being output on parallel port pins. 27.3.3 I/O Handshake The following steps must be taken before using the I/O handshake: 1. Select the active level and desired port E bit to use as input by writing to IHCR. 2. Select which I/O banks the handshake is active for by writing to IHSR. 3. Select the handshake timeout value by writing to IHTR. Once enabled, the handshake will be checked for every external I/O transaction in a bank that was enabled in IHSR. After these transactions, the program should check for a timeout by reading IHTR.
320

I/O Handshake Control Register Bit(s) 7:5 4 0 1 3 2:0 000 001 010 011 100 101 110 111 Value (IHCR) Description These bits are reserved and should be written with zeros. I/O handshake is active low (I/O transaction held until signal goes high). I/O handshake is active high (I/O transaction held until signal goes low). This bit is reserved and should be written with zero. Use Parallel Port E bit 0 for I/O handshake. Use Parallel Port E bit 1 for I/O handshake. Use Parallel Port E bit 2 for I/O handshake. Use Parallel Port E bit 3 for I/O handshake. Use Parallel Port E bit 4 for I/O handshake. Use Parallel Port E bit 5 for I/O handshake. Use Parallel Port E bit 6 for I/O handshake. Use Parallel Port E bit 7 for I/O handshake. (Address = 0x0028)
321
I/O Handshake Select Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(IHSR) Description
(Address = 0x0029)
Disable I/O handshake for I/O Bank 7. Enable I/O handshake for I/O Bank 7. Disable I/O handshake for I/O Bank 6. Enable I/O handshake for I/O Bank 6. Disable I/O handshake for I/O Bank 5. Enable I/O handshake for I/O Bank 5. Disable I/O handshake for I/O Bank 4. Enable I/O handshake for I/O Bank 4. Disable I/O handshake for I/O Bank 3. Enable I/O handshake for I/O Bank 3. Disable I/O handshake for I/O Bank 2. Enable I/O handshake for I/O Bank 2. Disable I/O handshake for I/O Bank 1. Enable I/O handshake for I/O Bank 1. Disable I/O handshake for I/O Bank 0. Enable I/O handshake for I/O Bank 0.
I/O Handshake Timeout Register Bit(s) 7 Value 0 1 6
(IHTR) Description
(Address = 0x002A)
No I/O handshake timeout has occurred since the last read of this register. An I/O handshake timeout has occurred since the last read of this register. This bit is cleared by a read of this register. This bit is reserved and should be written with zero. Time constant for the I/O handshake timeout counter. This time constant (times 32) selects the number of clocks that the I/O handshake input may delay completion of an I/O transaction before the I/O transaction will complete automatically.
5:0
322
I/O Bank x Control Register
(IB0CR) (IB1CR) (IB2CR) (IB3CR) (IB4CR) (IB5CR) (IB6CR) (IB7CR) Description
Bit(s) 7:6
Value 00 01 10 11
Fifteen wait states for accesses in this bank. Seven wait states for accesses in this bank. Three wait states for accesses in this bank. One wait state for accesses in this bank. The I signal is an I/O chip select. The I signal is an I/O read strobe. The I signal is an I/O write strobe. The I signal is an I/O data (read or write) strobe. Writes are not allowed to this bank. Transactions are normal in every other way; only the write strobe is inhibited. Writes are allowed to this bank. Active-low I signal. Inverted (active-high) I signal. Normal I/O transaction timing. Shorten read strobe by one clock cycle and write strobe by one-half clock cycle. Transaction length remains the same. This guarantees one clock cycle hold time for both address and data for I/O transactions. Use I/O bus if enabled. Always use memory data bus.
5:4
00 01 10 11
0 1
0 1
0 1
0 1
323
(SPCR) Description
(Address = 0x0024)
324
Parallel Port C Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PCALR) Description
(Address = 0x0052)
Parallel Port C bit 3 alternate output 0 (TXC). Parallel Port C bit 3 alternate output 1 (I3). Parallel Port C bit 3 alternate output 2 (TIMER C3). Parallel Port C bit 3 alternate output 3 (SCLKD). Parallel Port C bit 2 alternate output 0 (TXC). Parallel Port C bit 2 alternate output 1 (I2). Parallel Port C bit 2 alternate output 2 (TIMER C2). Parallel Port C bit 2 alternate output 3 (TXF). Parallel Port C bit 1 alternate output 0 (TXD). Parallel Port C bit 1 alternate output 1 (I1). Parallel Port C bit 1 alternate output 2 (TIMER C1). Parallel Port C bit 1 alternate output 3 (RCLKF). Parallel Port C bit 0 alternate output 0 (TXD). Parallel Port C bit 0 alternate output 1 (I0). Parallel Port C bit 0 alternate output 2 (TIMER C0). Parallel Port C bit 0 alternate output 3 (TCLKF).
325
Parallel Port C Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PCAHR) Description
(Address = 0x0053)
Parallel Port C bit 7 alternate output 0 (TXA). Parallel Port C bit 7 alternate output 1 (I7). Parallel Port C bit 7 alternate output 2 (PWM3). Parallel Port C bit 7 alternate output 3 (SCLKC). Parallel Port C bit 6 alternate output 0 (TXA). Parallel Port C bit 6 alternate output 1 (I6). Parallel Port C bit 6 alternate output 2 (PWM2). Parallel Port C bit 6 alternate output 3 (TXE). Parallel Port C bit 5 alternate output 0 (TXB). Parallel Port C bit 5 alternate output 1 (I5). Parallel Port C bit 5 alternate output 2 (PWM1). Parallel Port C bit 5 alternate output 3 (RCLKE). Parallel Port C bit 4 alternate output 0 (TXB). Parallel Port C bit 4 alternate output 1 (I4). Parallel Port C bit 4 alternate output 2 (PWM0). Parallel Port C bit 4 alternate output 3 (TCLKE).
Parallel Port C Function Register Bit(s) 7:0 Value 0 1
(PCFR) Description
(Address = 0x0055)
The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 101.
326
Parallel Port D Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PDALR) Description
(Address = 0x0062)
Parallel Port D bit 3 alternate output 0 (IA7). Parallel Port D bit 3 alternate output 1 (I3). Parallel Port D bit 3 alternate output 2 (TIMER C3). Parallel Port D bit 3 alternate output 3 (SCLKD). Parallel Port D bit 2 alternate output 0 (SCLKC). Parallel Port D bit 2 alternate output 1 (I2). Parallel Port D bit 2 alternate output 2 (TIMER C2). Parallel Port D bit 2 alternate output 3 (TXF). Parallel Port D bit 1 alternate output 0 (IA6). Parallel Port D bit 1 alternate output 1 (I1). Parallel Port D bit 1 alternate output 2 (TIMER C1). Parallel Port D bit 1 alternate output 3 (RCLKF). Parallel Port D bit 0 alternate output 0 (SCLKD). Parallel Port D bit 0 alternate output 1 (I0). Parallel Port D bit 0 alternate output 2 (TIMER C0). Parallel Port D bit 0 alternate output 3 (TCLKF).
327
Parallel Port D Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PDAHR) Description
(Address = 0x0063)
Parallel Port D bit 7 alternate output 0 (IA7). Parallel Port D bit 7 alternate output 1 (I7). Parallel Port D bit 7 alternate output 2 (PWM3). Parallel Port D bit 7 alternate output 3 (SCLKC). Parallel Port D bit 6 alternate output 0 (TXA). Parallel Port D bit 6 alternate output 1 (I6). Parallel Port D bit 6 alternate output 2 (PWM2). Parallel Port D bit 6 alternate output 3 (TXE). Parallel Port D bit 5 alternate output 0 (IA6). Parallel Port D bit 5 alternate output 1 (I5). Parallel Port D bit 5 alternate output 2 (PWM1). Parallel Port D bit 5 alternate output 3 (RCLKE). Parallel Port D bit 4 alternate output 0 (TXB). Parallel Port D bit 4 alternate output 1 (I4). Parallel Port D bit 4 alternate output 2 (PWM0). Parallel Port D bit 4 alternate output 3 (TCLKE).
Parallel Port D Function Register Bit(s) 7:0 Value 0 1
(PDFR) Description
(Address = 0x0065)
328
Parallel Port E Alternate Low Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PEALR) Description
(Address = 0x0072)
Parallel Port E bit 3 alternate output 0 (I3). Parallel Port E bit 3 alternate output 1 (A23). Parallel Port E bit 3 alternate output 2 (TIMER C3). Parallel Port E bit 3 alternate output 3 (SCLKD). Parallel Port E bit 2 alternate output 0 (I2). Parallel Port E bit 2 alternate output 1 (A22). Parallel Port E bit 2 alternate output 2 (TIMER C2). Parallel Port E bit 2 alternate output 3 (TXF). Parallel Port E bit 1 alternate output 0 (I1). Parallel Port E bit 1 alternate output 1 (A21). Parallel Port E bit 1 alternate output 2 (TIMER C1). Parallel Port E bit 1 alternate output 3 (RCLKF). Parallel Port E bit 0 alternate output 0 (I0). Parallel Port E bit 0 alternate output 1 (A20). Parallel Port E bit 0 alternate output 2 (TIMER C0). Parallel Port E bit 0 alternate output 3 (TCLKF).
329
Parallel Port E Alternate High Register Bit(s) 7:6 Value 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11
(PEAHR) Description
(Address = 0x0073)
Parallel Port E bit 7 alternate output 0 (I7). Parallel Port E bit 7 alternate output 1 (/ACT). Parallel Port E bit 7 alternate output 2 (PWM3). Parallel Port E bit 7 alternate output 3 (SCLKC). Parallel Port E bit 6 alternate output 0 (I6). Parallel Port E bit 6 alternate output 1 (). Parallel Port E bit 6 alternate output 2 (PWM2). Parallel Port E bit 6 alternate output 3 (TXE). Parallel Port E bit 5 alternate output 0 (I5). Parallel Port E bit 5 alternate output 1 (/LINK). Parallel Port E bit 5 alternate output 2 (PWM1). Parallel Port E bit 5 alternate output 3 RCLKE). Parallel Port E bit 4 alternate output 0 (I4). Parallel Port E bit 4 alternate output 1 (/A0). Parallel Port E bit 4 alternate output 2 (PWM0). Parallel Port E bit 4 alternate output 3 (TCLKE).
Parallel Port E Function Register Bit(s) 7:0 Value 0 1
(PEFR) Description
(Address = 0x0075)
330
28. BREAKPOINTS
28.1 Overview
The Rabbit 5000 contains seven hardware breakpoints to support debugging. Each hardware breakpoint consists of a 24-bit address match register and a 24-bit mask register. A breakpoint can be generated on an address match for address execution, data read, data write, or any combination thereof. The mask register serves to mask off selected address bits from the address compare. A one in a particular bit position in the mask register inhibits the corresponding bit in the address match register from contributing to the address match condition. When a match occurs, a Level 3 breakpoint interrupt is generated. Note that this means that breakpoints behave differently when the processor is running at Interrupt Priority 3 the interrupt is generated but will not be handled until the processor drops to a lower priority. In most cases, a code execution interrupt will be handled at the end of the instruction in which the match occurred. However, because of the time required to perform a 24-bit address match in the processor, a code execution breakpoint that is set on a single-byte, 2-clock instruction will not yet be enabled at the end of that instruction, and the interrupt will instead occur at the end of the next instruction. Note that a breakpoint may be forced to be pending by setting the corresponding bit in BDCR. This feature allows a breakpoint request to be used as a virtual single-step request by always setting the appropriate bit in the interrupt handler. There is a particular sequence of instructions required to exit properly when the interrupt is left pending. DMA transfers are treated as normal data reads and writes, although the DMA transfer will complete before the interrupt is taken. Breakpoints can be enabled for the User Mode, the System Mode, or both. Another breakpoint feature is the ability to disable the RST 28h instruction. The RST 28h vector was often used as a breakpoint feature by adding that instruction to code; by enabling a bit in BDCR, the RST 28h instruction will execute as a NOP instead, providing an easy way to disable that type of breakpoint.
Chapter 28 Breakpoints
331

Breakpoint x
Interrupt Generation
Interrupt Request
Code Execution, Data Read, Data Write Address
Match Type Enable BxCR
Address Mask BxM0R BxM1R BxM2R
Address Compare BxA0R BxA1R BxA2R
332
28.1.2 Registers
Register Name Breakpoint Debug/Control Register Breakpoint 0 Control Register Breakpoint 1 Control Register Breakpoint 2 Control Register Breakpoint 3 Control Register Breakpoint 4 Control Register Breakpoint 5 Control Register Breakpoint 6 Control Register Breakpoint 0 Address [02] Register Breakpoint 1 Address [02] Register Breakpoint 2 Address [02] Register Breakpoint 3 Address [02] Register Breakpoint 4 Address [02] Register Breakpoint 5 Address [02] Register Breakpoint 6 Address [02] Register Breakpoint 0 Mask [02] Register Breakpoint 1 Mask [02] Register Breakpoint 2 Mask [02] Register Breakpoint 3 Mask [02] Register Breakpoint 4 Mask [02] Register Breakpoint 5 Mask [02] Register Breakpoint 6 Mask [02] Register Mnemonic BDCR B0CR B1CR B2CR B3CR B4CR B5CR B6CR B0AxR B1AxR B2AxR B3AxR B4AxR B5AxR B6AxR B0MxR B1MxR B2MxR B3MxR B4MxR B5MxR B6MxR I/O Address 0x001C 0x030B 0x031B 0x032B 0x033B 0x034B 0x035B 0x036B 0x030C + x 0x031C + x 0x032C + x 0x033C + x 0x034C + x 0x035C + x 0x036C + x 0x0308 + x 0x0318 + x 0x0328 + x 0x0338 + x 0x0348 + x 0x0358 + x 0x0368 + x R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
333
28.2 Dependencies
28.2.1 I/O Pins There are no I/O pins associated with breakpoints. 28.2.2 Clocks There are no clocks associated with breakpoints. 28.2.3 Other Registers There are no other registers associated with breakpoints. 28.2.4 Interrupts When an enabled address match occurs for a given breakpoint, a breakpoint interrupt occurs. The breakpoint that caused the interrupt must be determined by reading BDCR, which also clears the interrupt. Any of the breakpoint interrupts can be enabled by writing to BDCR. The breakpoint interrupt vector is in the EIR at offset 0x040. It is always set to Interrupt Priority 3, and is the highest priority interrupt; if two Interrupt Priority 3 vectors are pending, the breakpoint interrupt will always be handled first.
28.3 Operation
The following steps must be taken to enable breakpoints: 1. Write the vector to the interrupt service routine to the external interrupt table. 2. Write the desired breakpoint addresses to the appropriate breakpoint address registers (BxAyR, where x is the breakpoint and y is the byte of the address, 0-2). 3. Write an address mask for the given breakpoints (BxMyR). 4. Select the breakpoint address match type (execute, data read, data write) by writing to the appropriate BxCR. 5. Enable the desired breakpoints by writing to BDCR. 28.3.1 Handling Interrupts The following actions occur within the interrupt service routine. Which breakpoints are pending should be determined by reading BDCR. This also clears the pending breakpoints. The desired breakpoint action should be taken. If single-step functionality is desired, the breakpoint interrupt should be re-enabled by writing the appropriate bit to BDCR. If this is done, the interrupt handler needs to be exited in a particular manner (see below).
334
28.3.2 Example ISR A sample interrupt handler is shown below.

breakpoint_isr:: push af ioi ld a, (BDCR)
; determine which interrupts are pending and ; clear the interrupt request
; handle all breakpoints here ; reenable any breakpoints by writing to BDCR pop af ipres ret ; you must exit the handler with these two ; instructions if you reenabled breakpoints
335

Breakpoint/Debug Control Register Bit(s) 7 Value 0 1 6:0 Read 6:0 Write 0 1 0 1 Normal RST 0x28 operation. RST 0x28h is NOP. The corresponding Breakpoint request is not pending. The corresponding Breakpoint request is pending. Reading this register automatically clears all pending breakpoint requests. No effect on the corresponding Breakpoint request. Make the corresponding Breakpoint request pending. (BDCR) Description (Address = 0x001C)
Breakpoint x Control Register
(B0CR) (B1CR) (B2CR) (B3CR) (B4CR) (B5CR) (B6CR) Description
(Address = 0x030B) (Address = 0x031B) (Address = 0x032B) (Address = 0x033B) (Address = 0x034B) (Address = 0x036B) (Address = 0x037B)
Bit(s) 7:6
Value 00 01 10 11
No Breakpoint x on execute address match. Breakpoint x on User Mode execute address match. Breakpoint x on System Mode execute address match. Breakpoint x on System or User Mode execute address match. No breakpoint x on data read address match. Breakpoint x on User Mode data read address match. Breakpoint x on System Mode data read address match. Breakpoint x on System or User Mode data read address match. No breakpoint x on write address match. Breakpoint x on User Mode write address match. Breakpoint x on System Mode write address match. Breakpoint x on System or User Mode write address match. These bits are reserved and should be written with zeros.
5:4
00 01 10 11
3:2
00 01 10 11
1:0
336
Breakpoint x Address 0 Register
(B0A0R) (B1A0R) (B2A0R) (B3A0R) (B4A0R) (B5A0R) (B6A0R) Description
(Address = 0x030C) (Address = 0x031C) (Address = 0x032C) (Address = 0x033C) (Address = 0x034C) (Address = 0x036C) (Address = 0x037C)
Bit(s) 7:0
Value Breakpoint x Address [7:0].
(Address = 0x030D) (Address = 0x031D) (Address = 0x032D) (Address = 0x033D) (Address = 0x034D) (Address = 0x036D) (Address = 0x037D)
Bit(s) 7:0
(Address = 0x030E) (Address = 0x031E) (Address = 0x032E) (Address = 0x033E) (Address = 0x034E) (Address = 0x036E) (Address = 0x037E)
Bit(s) 7:0
337
Breakpoint x Mask 0 Register
(B0M0R) (B1M0R) (B2M0R) (B3M0R) (B4M0R) (B5M0R) (B6M0R) Description
(Address = 0x0308) (Address = 0x0318) (Address = 0x0328) (Address = 0x0338) (Address = 0x0348) (Address = 0x0368) (Address = 0x0378)
Bit(s) 7:0
Value
Breakpoint x Mask [7:0]. (A one in a bit position inhibits the address compare for that bit position.)
(Address = 0x0309) (Address = 0x0319) (Address = 0x0329) (Address = 0x0339) (Address = 0x0349) (Address = 0x0369) (Address = 0x0379)
Bit(s) 7:0
Value
Breakpoint x Mask [15:8]. (A one in a bit position inhibits the address compare for that bit position.)
(Address = 0x030A) (Address = 0x031A) (Address = 0x032A) (Address = 0x033A) (Address = 0x034A) (Address = 0x036A) (Address = 0x037A)
Bit(s) 7:0
Value
Breakpoint x Mask [23:16]. (A one in a bit position inhibits the address compare for that bit position.
338
29. LOW-POWER OPERATION

29.1 Overview
The Rabbit 5000 contains several power-saving features. Since the power consumed by the processor is proportional to the clock speed, the Rabbit 5000 provides 12 clock modes that can go as low as 2 kHz. To further reduce power consumption in those ultra-sleepy modes, various shortened chip select strobes are available to reduce current draw by the attached memory devices. Figure 29-1 shows a typical current draw as a function of the main clock frequency. The values shown do not include any current consumed by external oscillators or memory. It is assumed that approximately 30 pF is connected to each address line.
70 60
CURRENT (mA)
50 40 30 20 10 0 2 10
total
IIO
ICORE
20
30
40
50
60
CPU/PERPHERAL CLOCKS (MHz)

Figure 29-1. Typical Current Draw as a Function of the Main Clock Frequency
The typical current draw in the ultra-sleepy modes is 2 mA for ICORE and 5 mA for IIO, depending on the pin activity.
Chapter 29 Low-Power Operation
339
29.1.1 Registers
Register Name Global Control/Status Register Global Power Save Control Register Global Clock Double Register Mnemonic GCSR GPSCR GCDR I/O Address 0x0000 0x000D 0x000F R/W R/W R/W R/W Reset 11000000 00000000 00000000
340
29.2 Operation
29.2.1 Unused Pins Input (or bidirectional) pins that are unused in a design can pick up noise that may cause the transistors in the input buffer to switch states quickly, causing unnecessary current draw. To avoid this, all unused pins should be connected to a weak pullup or pulldown resistor (approximately 100 k) and left as inputs. This provides protection from noise when the pin is an input, but also limits the current draw if the pin gets inadvertently enabled as an output. 29.2.2 Clock Rates The processor and peripheral clocks in the Rabbit 5000 can be run in six different modes using the main oscillator: full speed; divided by 2, 4, 6, or 8; and the processor clock divided by 8 with the peripheral clock at full speed. If the clock doubler is enabled, the options also include twice the main oscillator frequency and the main oscillator divided by 3. In addition, the 32 kHz clock can be used for the processor and peripheral clocks; the 32 kHz clock can also be divided by 2, 4, 8, or 16, which provides dramatically lower power consumption. Table 29-1 lists the options for the clock modes and the processor clock frequency.
Table 29-1. Clock Modes
Main Oscillator GCSR Setting Full Full Divided by 2 Divided by 2 Divided by 4 Divided by 6 Divided by 4 Divided by 8 Divided by 6 Divided by 8 Clock Doubler On Off Main Oscillator On Off Main Oscillator / 2 On On Off Main Oscillator / 4 On Off Off Disabled Off (32 kHz divider used) /2 N/A /4 /8 / 16
32 kHz Divider
Processor Clock Frequency 2 Main Oscillator
N/A Main Oscillator / 3
Main Oscillator / 6 Main Oscillator / 8 32.768 kHz 16.384 kHz 8.192 kHz 4.096 kHz 2.048 kHz
341
Depending on the application, the processor can continue executing code normally when the main oscillator is divided down to a lower value. However, when the processor clock is running off of the 32 kHz clock, it is recommended that the Rabbit 5000 be performing a tight polling loop, waiting for a wake-up event. 29.2.3 Short Chip Selects When running at a reduced clock speed, it is likely that the chip selects for external devices will not need to be active for an entire clock cycle. By reducing the width of the chip select, the power consumption of the memory chip can be reduced without having any affect on the processor itself. For reduced processor speeds based on the main oscillator, a short chip select can be enabled in GPSCR (this feature is not available when the processor is running at full speed). This feature can be enabled separately for both reads and writes. When enabled, the chip select signals will be the width of two undivided clocks and located at the end of the transaction. The read data in the figures below is sampled by the rising edge of CLKI that terminated the T2 cycle. Wait states are inserted between T1 and T2 so they do not affect the width of the strobe.
T1 CLK1 CLK A[23:0] D[7:0] /CSx /OEx Divide by 8 Mode

valid
T2
342

valid
T2

valid
T2
343

valid
T2
When the processor is running off the 32 kHz clock, the short chip select option will produce chip select signal that is the width of a single 32 kHz clock (30.5 microseconds); otherwise the timing is identical to the short chip select options based off the main oscillator. Read strobe figures are shown below.
T1 32 kHz CLK A[23:0] D[7:0] /CSx /OEx Operation at 2 kHz

valid
T2
344

valid
T2

valid
T2
345
T1 32 kHz CLK A[23:0] D[7:0] /CSx /OEx

valid
T2
Operation at 16 kHz
T1 32 kHz CLK A[23:0] D[7:0] /CSx /OEx

valid
T2
Operation at 32 kHz
346
29.2.4 Self-Timed Chip Selects Self-timed chip selects can be enabled via GPSCR to reduce power consumption even more when running off the 32 kHz oscillator. When self-timed chip selects are enabled, the chip select is only active for a short (selectable) period of time ranging from 110 to 290 ns; this can be enable for both reads and writes, or reads only. A sample read and write timing diagram is shown below.
T1 32 kHz A[23:0] D[7:0] /CSx /OEx

~100 ns valid valid
T2
347

Global Control/Status Register Bit(s) 7:6 (rd-only) Value 00 01 10 11 5 0 1 4:2 000 (GCSR) Description No reset or watchdog timer timeout since the last read. The watchdog timer timed out. These bits are cleared by a read of this register. This bit combination is not possible. Reset occurred. These bits are cleared by a read of this register. No effect on the periodic interrupt. This bit will always be read as zero. Force a periodic interrupt to be pending. Processor clock from the fast clock, divided by 8. Peripheral clock from the fast clock, divided by 8. Processor clock from the fast clock, divided by 8. Peripheral clock from the fats clock. Processor clock from the fast clock. Peripheral clock from the fast clock. Processor clock from the fast clock, divided by 2. Peripheral clock from the fast clock, divided by 2. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The fast clock is disabled. Processor clock from the fast clock, divided by 4. Peripheral clock from the fast clock, divided by 4. Processor clock from the fast clock, divided by 6. Peripheral clock from the fast clock, divided by 6. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. (Address = 0x0000)
001
010
011
100
101
110
111 1:0 00 01 10 11
348
Global Power Save Control Register Bit(s) 7:5 Value 000 001 010 011 100 101 110 111 4 0 1 3 0 1 2:0 000 001 010 011 100 101 110 111
(GPSCR) Description
(Address = 0x000D)
Self-timed chip selects are disabled. 230 ns self-timed chip selects for read and write. 170 ns self-timed chip selects for read and write. 110 ns self-timed chip selects for read and write. 290 ns self-timed chip selects for read only. 230 ns self-timed chip selects for read only. 170 ns self-timed chip selects for read only. 110 ns self-timed chip selects for read only. Normal chip select timing for read cycles. Short chip select timing for read cycles (not available in full speed). Normal chip select timing for write cycles Short chip select timing for write cycles (not available in full speed). The 32 kHz clock divider is disabled. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. 32 kHz clock divided by 2 (16.384 kHz). 32 kHz clock divided by 4 (8.192 kHz). 32 kHz clock divided by 8 (4.096 kHz). 32 kHz clock divided by 16 (2.048 kHz).
349
Global Clock Double Register Bit(s) 7:5 4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10001 10010 10011 other Value
(GCDR) Description
(Address = 0x000F)
These bits are reserved and should be written with zeros. The clock doubler circuit is disabled. 6 ns nominal low time. 7 ns nominal low time. 8 ns nominal low time. 9 ns nominal low time. 10 ns nominal low time. 11 ns nominal low time. 12 ns nominal low time. 13 ns nominal low time. 14 ns nominal low time. 15 ns nominal low time. 16 ns nominal low time. 17 ns nominal low time. 18 ns nominal low time. 19 ns nominal low time. 20 ns nominal low time. 3 ns nominal low time. 4 ns nominal low time. 5 ns nominal low time. Any bit combination not listed is reserved and must not be used.
350
30. SYSTEM/USER MODE

30.1 Overview
The Rabbit 5000 provides support for two tiers of control in the processor: System Mode, which provides full access to all processor resources; and User Mode, a more restricted mode. Table 30-1 describes the essential differences between the System Mode and the User Mode. The System Mode is essentially the same as the normal operation when the System/User Mode is disabled.
Table 30-1. Differences Between System Mode and User Mode
System Mode All peripherals accessible. All processor control registers available. All interrupt priorities available. IDET instruction has no effect. No write protection when 0x00 is written to WPCR (write protection in User mode only) Easy to enter user mode (SETUSR instruction). User Mode No peripherals accessible by default. No processor control registers available. Interrupt Priority 3 not allowed. IDET instruction causes Priority 3 System mode violation interrupt. Write to protected segment causes Priority 3 write protection violation interrupt. Difficult to enter system mode (requires interrupt, SYSCALL, or RST instruction).
The main intent of the System/User Mode is to protect critical code (for example, code that performs remote firmware updates), data, and the current processor state (memory setup, peripheral control, etc.) from inadvertent changes by the users standard code. By removing access to the processors I/O registers and preventing memory writes to critical regions, the users code can run without the danger of locking up the processor to the point where it cannot be restarted remotely and/or new code uploaded.
Chapter 30 System/User Mode
351
30.1.1 Registers
Register Name Enable Dual-Mode Register Real-Time Clock User Enable Register Slave Port User Enable Register Parallel Port A User Enable Register Parallel Port B User Enable Register Parallel Port C User Enable Register Parallel Port D User Enable Register Parallel Port E User Enable Register Input Capture User Enable Register I/O Bank User Enable Register PWM User Enable Register Quad Decode User Enable Register External Interrupt User Enable Register Timer A User Enable Register Analog User Enable Register Timer B User Enable Register Timer C User Enable Register Serial Port A User Enable Register Serial Port B User Enable Register Serial Port C User Enable Register Serial Port D User Enable Register Serial Port E User Enable Register Serial Port F User Enable Register Enable Dual-Mode Register Mnemonic EDMR RTUER SPUER PAUER PBUER PCUER PDUER PEUER ICUER IBUER PWUER QDUER IUER TAUER AUER TBUER TCUER SAUER SBUER SCUER SDUER SEUER SFUER EDMR I/O Address 0x0420 0x0300 0x0320 0x0330 0x0340 0x0350 0x0360 0x0370 0x0358 0x0380 0x0388 0x0390 0x0398 0x03A0 0x03A8 0x03B0 0x3F8 0x03C0 0x3D0 0x3E0 0x3F0 0x03C8 0x3D8 0x0420 R/W W W W W W W W W W W W W W W W W W W W W W W W R/W Reset 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
352
30.2 Dependencies
30.2.1 I/O Pins There are no pin dependencies for the System/User Mode. 30.2.2 Clocks There are no clock dependencies for the System/User Mode. 30.2.3 Other Registers Any writes to the internal I/O registers listed in Table 30-2 are ignored when the System/ User Mode is enabled and the processor is in the User Mode.
Table 30-2. I/O Addresses Inaccessible in User Mode
Register Name Global Control/Status Register Watchdog Timer Control Register Watchdog Timer Test Register Global Clock Modulator 0 Register Global Clock Modulator 1 Register Secondary Watchdog Timer Register Global Power Save Control Register Global Output Control Register Global Clock Double Register MMU Instruction/Data Register Stack Segment Register Data Segment Register Segment Size Register Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register Memory Timing Control Register Stack Segment Low Register Stack Segment High Register Breakpoint/Debug Control Register Memory Alternate Control Register Data Segment Low Register
Mnemonic GCSR WDTCR WDTTR GCM0R GCM1R SWDTR GPSCR GOCR GCDR MMIDR STACKSEG DATASEG SEGSIZE MB0CR MB1CR MB2CR MB3CR MECR MTCR STACKSEGL STACKSEGH BDCR MACR DATSEGL
I/O Address 0x0000 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E
353
Table 30-2. I/O Addresses Inaccessible in User Mode (continued)

Register Name Data Segment High Register DMA registers Network Port B registers User Enable and Breakpoint registers Memory Protection registers Network Port C registers Mnemonic DATSEGH I/O Address 0x001F 0x0100 0x01FF 0x0200 0x02FF 0x0300 0x03FF 0x0400 0x04FF 0x0A00 0x0AFF
30.2.4 Interrupts The System Mode Violation interrupt occurs whenever the IDET instruction is executed while the System/User mode is enabled and the processor is in the User Mode. Its purpose is to trap when system code is being executed while the processor is in the User Mode. The System Mode Violation interrupt vector is in the IIR at offset 0x180. It always occurs at Priority 3. Note that Priority 3 is not available while the System/User Mode is enabled and the processor is in the User Mode. If the processor is placed into Priority 3 either by an instruction or an interrupt, it will respond as if it was set to Priority 2. When the System/User Mode is enabled, it is critical to handle the SU stack in interrupts as well as the IP stack; always perform a SURES before the IPRES at the end of the interrupt.
354
30.3 Operation
The System/User Mode is designed to work with the memory and stack protection features of the Rabbit 5000 processor to provide a seamless framework for protection of critical code. However, there are many levels at which the System/User Mode can be used some examples are described here. 30.3.1 Memory Protection Only At the beginning of the user program, all necessary peripherals are enabled, all peripheral interrupts to be used are set up for the User Mode, critical memory regions are protected, stack limits are set, and the various system/memory/stack violation interrupts are enabled. The processor then enters the User Mode and remains in the User Mode for all operations (interrupts can be handled however the user desires). Obviously the critical interrupts can be handled in the System Mode, but at that point the device is typically reset and the error is logged. Figure 30-1 shows an overview of this level of operation.
System Mode
User Mode
Application code
Critical Interrupts
Critical interrupts
Interrupts
Figure 30-1. System/User Mode Setup for Memory Protection Only
355
30.3.2 Mixed System/User Mode Operation This mode is similar to the previous mode, but with some portions of the program written for System Mode for example, peripheral interrupts where latency is critical. By keeping the System Mode code sections small, potential system crashes are still minimized. Figure 30-2 shows an overview of this level of operation.
System Mode
Return from interrupts
User Mode
Application code User-defined interrupts
Critical interrupts Time-critical interrupts

Critical Interrupts
Figure 30-2. System/User Mode Setup for Mixed Operation
30.3.3 Complete Operating System This section describes a full use of the System/User Mode separating all common functions into a System Mode operating system while letting the application-specific code run in the User Mode. By default, the System Mode handles all peripherals and interrupts, as well as high-level interfaces such as a flash file system. However, the processor will be running the application code in the User Mode most of the time. The application code can request direct access to a peripheral and/or interrupt from the System Mode. If allowed, the System Mode can create an interrupt vector as described in Section 30.3.7 that will execute the user code interrupt handler. When the application code wants to perform an action that is controlled by the System Mode, it can request the particular action by loading the appropriate value into HL and executing SYSCALL. This requires generating a list of all the actions that the application code would want to do, assigning values to each action, and implementing a SYSCALL handler in the System Mode that parses the value passed to it and calls the appropriate function. Write protection should be enabled (User Mode only) for all blocks containing system code and data as well as any critical memory regions. If any critical interrupts occur (stack limit violation, system mode violation, write protection violation), System Mode handlers can perform any of a number of operations: restart the application code, signal another device, halt operation, and so on.
Figure 30-3 shows an overview of this level of operation.

System Mode
Return from interrupts
User Mode
Application code User-defined interrupts
Interrupt handlers Flash file system SYSCALL handler

Interrupts, SYSCALL, RST
Figure 30-3. System/User Mode Setup for Operating System
30.3.4 Enabling the System/User Mode The following steps describe how to enable the System/User Mode. 1. If a peripheral needs to be accessed while in User Mode, write to the appropriate user enable register to allow that access. 2. Write a 1 to bit 0 of EDMR to enable System/User Mode. 3. Execute the SETUSR instruction to enter User Mode. After the User Mode is entered, the limitations described earlier are in effect writes to protected registers will be ignored, Priority 3 is not available, and executing an IDET will cause a System Mode Violation interrupt. Other features such as write protection may be effect for user mode as well.
357
30.3.5 System/User Mode Instructions Seven instructions exist primarily to support the System/User Mode, and are listed in Table 30-3. Note that IDET shares the value of LD E,E in the opcode table, and will always perform that operation (but will have special behavior when the System/User Mode is enabled and the processor is in System Mode). In addition, if the ALTD prefix appears before the instruction, LD E,E is always executed and the special behavior does not occur.
Table 30-3. System/User Mode Instructions
Instruction Bytes 2 2 2 2 clk 4 9 7 4 A I S Z V C Operation Priv Yes Yes Yes Yes
SETUSR PUSH SU POP SU SURES
- SU = {SU[5:0], 0x01} - (SP-1) = SU; SP = SP - 1 - SU = (SP); SP = SP + 1 - SU = {SU[1:0], SU[7:2]} Performs LD E,E, but if (EDMF && SU[0]) then the System Violation interrupt flag is set; if ALTD appears before it always does LD E,E * CF = SU[0] SP = SP - 2; PC = {R,v} where v = SYSCALL offset
IDET
No
RDMODE SYSCALL
2 2
4 10
Yes No
SCALL
15
(SP-1) = PCH; (SP-2) = PCL; (SP-3) = SU; - SP = SP - 3; PC = {IIR, 01100000}; SU = {SU[5:0], 00} SU = (SP); PCL = (SP+1); PCH = (SP+2); SP = SP+3 SU = {SU[7:2], 01}, (SP-1) = m; (SP-2) = n; SP = SP-2
No
SRET
2 4
12 15
No No
SETUSRP mn
SETSYSP mn
12
SU = {SU[1:0], SU[7:2]}; tmpl = (SP); - tmph = (SP+1); SP = SP+2; if {tmp ! = mn} System Violation
No
The processor keeps a one-byte stack (called the SU register) that is analogous to the IP register that keeps track of the interrupt priority. Every time SETUSR is executed (to enter the User Mode), or an interrupt occurs, or SYSCALL or RST is executed (to enter System Mode), the current mode is pushed onto the SU register. When a SURES is executed, the previous mode is popped off the SU register.
358
The effects of each instruction are: The SETUSR instruction puts the processor into the User Mode by pushing the correct value into the SU register. PUSH SU and POP SU push and pop the single-byte SU register on/off the SP stack. SURES pops the current processor mode off the SU register, returning it to the previous mode. IDET causes an interrupt if executed in the User Mode, and does nothing in System Mode. It is intended to be placed in system-level code and trap any execution of that code while in the User Mode. RDMODE returns the current mode in the carry flag (0 for System Mode, 1 for User Mode). SYSCALL is essentially a new RST instruction, and was added to allow User Mode access to the System Mode without using one of the existing RST instructions. It will put the processor into the System Mode and execute code in the corresponding interrupt-vector table entry. SCALL is another RST instruction that vectors to the same address as SYSCALL. The difference is that it also pushes the value of the SU register as well as the return address onto the stack. SRET is the companion instruction to SCALL; it expects both SU and the return address to be on the stack. SETSYSP and SETUSRP are support functions for handing user mode interrupts. pushes a 16-bit compare value onto the stack and enters user mode. SETSYSP pops a 16-bit value off the stack and compares it to the provided value; a system mode violation interrupt occurs if they do not match. These two instructions provide protection for User Mode interrupts by checking for both main stack and SU stack mismatches when the User Mode handler returns. 30.3.6 System Mode Violation Interrupt The following steps describe how to set up the System Mode Violation interrupt. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Enable the system/user mode by writing to EDMR. 3. The interrupt request is cleared automatically when handled. A sample interrupt handler is shown below.
sysmode_isr:: push af ; handle the system mode violation here pop af sures ipres ret
359
30.3.7 Handling Interrupts in the System/User Mode Interrupts, RSTs, SYSCALL, and SCALL all enter the System Mode automatically. There will be times, however, that an interrupt should be handled in the User Mode. The solution to this is for System Mode interrupt vector to reenter the User Mode before calling the User Mode interrupt handler. An example of both system and user interrupt handling is shown in Figure 30-4. When enabled for User Mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Priority 2 or 1.
INTERRUPT UNDER SYSTEM CONTROL
ISR (system)
Application code (user)
INTERRUPT UNDER USER CONTROL

ISR (system) ISR (system)
Application ISR (user)
Figure 30-4. Interrupt Handing in the System/User Mode
360
Some sample code for both System Mode interrupts and User Mode interrupts is shown below. The use of SETUSRP and SETSYSP provides checks against stack mismatches and incorrect System/User Modes coming out of the User Mode handler.
systemmode_isr: ... handle interrupt ... sures ipres ret usermode_isr: push su setusrp 0x1234 call user_handler setsysp 0x1234 sures ipres ret ; jumped to from interrupt vector table ; reenter previous mode ; restore previous interrupt priority
; ; ; ; ; ; ; ;
jumped to from interrupt vector table (still in system mode at this point) preserve current SU stack enter user mode with stack compare value handle interrupt at user level return to system mode reenter previous mode restore previous interrupt priority
361

Real-Time Clock User Enable Register Bit(s) 7 Value 0 1 6:0 (RTUER) Description Disable User Mode access to the RTC (I/O addresses 0x00020x0007). Enable User Mode access to the RTC (I/O addresses 0x00020x0007). These bits are reserved and should be written with zeros. (Address = 0x0300)
Slave Port User Enable Register Bit(s) 7 Value 0 1 6:0
(SPUER) Description
(Address = 0x0320)
Disable User Mode access to the slave port (I/O addresses 0x00200x0027). Enable User Mode access to the slave port (I/O addresses 0x00200x0027). These bits are reserved and should be written with zeros.
Parallel Port A User Enable Register Bit(s) 7 Value 0 1 6:0
(PAUER) Description
(Address = 0x0330)
Disable User Mode access to Parallel Port A (I/O addresses 0x00300x0037). Enable User Mode access to Parallel Port A (I/O addresses 0x00300x0037). These bits are reserved and should be written with zeros.
Parallel Port H User Enable Register Bit(s) 7 Value 0 1 6:0
(PHUER) Description
(Address = 0x0332)
Disable User Mode access to Parallel Port H (I/O addresses 0x00320x0037). Enable User Mode access to Parallel Port H (I/O addresses 0x00320x0037). These bits are reserved and should be written with zeros.
Parallel Port B User Enable Register Bit(s) 7 Value 0 1 6:0
(PBUER) Description
(Address = 0x0340)
Disable User Mode access to Parallel Port B (I/O addresses 0x00400x0047). Enable User Mode access to Parallel Port B (I/O addresses 0x00400x0047). These bits are reserved and should be written with zeros.
362
Parallel Port C User Enable Register Bit(s) 7 Value 0 1 6:0
(PCUER) Description
(Address = 0x0350)
Disable User Mode access to Parallel Port C (I/O addresses 0x00500x0055). Enable User Mode access to Parallel Port C (I/O addresses 0x00500x0055). These bits are reserved and should be written with zeros.
Parallel Port D User Enable Register Bit(s) 7 Value 0 1 6:0
(PDUER) Description
(Address = 0x0360)
Disable User Mode access to Parallel Port D (I/O addresses 0x00600x006F). Enable User Mode access to Parallel Port D (I/O addresses 0x00600x006F). These bits are reserved and should be written with zeros.
Parallel Port E User Enable Register Bit(s) 7 Value 0 1 6:0
(PEUER) Description
(Address = 0x0370)
Disable User Mode access to Parallel Port E (I/O addresses 0x00700x007F). Enable User Mode access to Parallel Port E (I/O addresses 0x00700x007F). These bits are reserved and should be written with zeros.
Input Capture User Enable Register Bit(s) 7 Value 0 1 6:0
(ICUER) Description
(Address = 0x0358)
Disable User Mode access to input capture (I/O addresses 0x00560x005F). Enable User Mode access to input capture (I/O addresses 0x00560x005F). These bits are reserved and should be written with zeros.
363
I/O Bank User Enable Register Bit(s) 7 Value 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1
(IBUER) Description
(Address = 0x0380)
Disable User Mode access to I/O Bank 7 (and internal I/O address 0x0087). Enable User Mode access to I/O Bank 7 (and internal I/O addresses 0x0087). Disable User Mode access to I/O Bank 6 (and internal I/O address 0x0086). Enable User Mode access to I/O Bank 6 (and internal I/O addresses 0x0086). Disable User Mode access to I/O Bank 5 (and internal I/O address 0x0085). Enable User Mode access to I/O Bank 5 (and internal I/O addresses 0x0085). Disable User Mode access to I/O Bank 4 (and internal I/O address 0x0084). Enable User Mode access to I/O Bank 4 (and internal I/O addresses 0x0084). Disable User Mode access to I/O Bank 3 (and internal I/O address 0x0083). Enable User Mode access to I/O Bank 3 (and internal I/O addresses 0x0083). Disable User Mode access to I/O Bank 2 (and internal I/O address 0x0082). Enable User Mode access to I/O Bank 2 (and internal I/O addresses 0x0082). Disable User Mode access to I/O Bank 1 (and internal I/O address 0x0081). Enable User Mode access to I/O Bank 1 (and internal I/O addresses 0x0081). Disable User Mode access to I/O Bank 0 (and internal I/O address 0x0080). Enable User Mode access to I/O Bank 0 (and internal I/O addresses 0x0080).
PWM User Enable Register Bit(s) 7 Value 0 1 6:0
(PWUER) Description
(Address = 0x0388)
Disable User Mode access to the PWM (I/O addresses 0x00880x008F and 0x00E80x00E9). Enable User Mode access to the PWM (I/O addresses 0x00880x008F and 0x00E80x00E9). These bits are reserved and should be written with zeros.
Quad Decode User Enable Register Bit(s) 7 Value 0 1 6:0
(QDUER) Description
(Address = 0x0390)
Disable User Mode access to the Quadrature Decoder (I/O addresses 0x0090 0x0097). Enable User Mode access to the Quadrature Decoder (I/O addresses 0x0090 0x0097). These bits are reserved and should be written with zeros.
364
External Interrupt User Enable Register Bit(s) 7:2 1 0 1 0 0 1 Value
(IUER) Description
(Address = 0x0398)
These bits are reserved and should be written with zeros. Disable User Mode access to External Interrupt 1 (I/O address 0x0099). Enable User Mode access to External Interrupt 1 (I/O addresses 0x0099). Disable User Mode access to External Interrupt 0 (I/O address 0x0098). Enable User Mode access to External Interrupt 0 (I/O addresses 0x0098).
Timer A User Enable Register Bit(s) 7 Value 0 1 6:0
(TAUER) Description
(Address = 0x03A0)
Disable User Mode access to Timer A (I/O addresses 0x00A00x00AF). Enable User Mode access to Timer A (I/O addresses 0x00A00x00AF). These bits are reserved and should be written with zeros.
Analog User Enable Register Bit(s) 7:3 2 0 1 1 0 1 0 0 1 Value
(AUER) Description
(Address = 0x03A8)
These bits are reserved and should be written with zeros. Disable User Mode access to Analog Channel 2 (I/O addresses 0x08200x082F). Enable User Mode access to Analog Channel 2 (I/O addresses 0x08200x082F). Disable User Mode access to Analog Channel 1 (I/O addresses 0x08100x081F). Enable User Mode access to Analog Channel 1 (I/O addresses 0x08100x081F). Disable User Mode access to Analog Channel 0 (I/O addresses 0x08000x080F). Enable User Mode access to Analog Channel 0 (I/O addresses 0x08000x080F).
Timer B User Enable Register Bit(s) 7 Value 0 1 6:0
(TBUER) Description
(Address = 0x03B0)
Disable User Mode access to Timer B (I/O addresses 0x00B00x00BF). Enable User Mode access to Timer B (I/O addresses 0x00B00x00BF). These bits are reserved and should be written with zeros.
365
Timer C User Enable Register Bit(s) 7 Value 0 1 6:0
(TCUER) Description
(Address = 0x03F8)
Disable User Mode access to Timer C (I/O addresses 0x05000x050F and 0x00F80x00F9). Enable User Mode access to Timer C (I/O addresses 0x05000x050F and 0x00F80x00F9). These bits are reserved and should be written with zeros.
Serial Port A User Enable Register Bit(s) 7 Value 0 1 6:0
(SAUER) Description
(Address = 0x03C0)
Disable User Mode access to Serial Port A (I/O addresses 0x00C00x00C7). Enable User Mode access to Serial Port A (I/O addresses 0x00C00x00C7). These bits are reserved and should be written with zeros.
Serial Port B User Enable Register Bit(s) 7 Value 0 1 6:0
(SBUER) Description
(Address = 0x03D0)
Disable User Mode access to Serial Port B (I/O addresses 0x00D00x00D7). Enable User Mode access to Serial Port B (I/O addresses 0x00D00x00D7). These bits are reserved and should be written with zeros.
Serial Port C User Enable Register Bit(s) 7 Value 0 1 6:0
(SCUER) Description
(Address = 0x03E0)
Disable User Mode access to Serial Port C (I/O addresses 0x00E00x00E7). Enable User Mode access to Serial Port C (I/O addresses 0x00E00x00E7). These bits are reserved and should be written with zeros.
Serial Port D User Enable Register Bit(s) 7 Value 0 1 6:0
(SDUER) Description
(Address = 0x03F0)
Disable User Mode access to Serial Port D (I/O addresses 0x00F00x00F7). Enable User Mode access to Serial Port D (I/O addresses 0x00F00x00F7). These bits are reserved and should be written with zeros.
366
Serial Port E User Enable Register Bit(s) 7 Value 0 1 6:0
(SEUER) Description
(Address = 0x03C8)
Disable User Mode access to Serial Port E (I/O addresses 0x00C80x00CF). Enable User Mode access to Serial Port E (I/O addresses 0x00C80x00CF). These bits are reserved and should be written with zeros.
Serial Port F User Enable Register Bit(s) 7 Value 0 1 6:0
(SFUER) Description
(Address = 0x03D8)
Disable User Mode access to Serial Port F (I/O addresses 0x00D80x00DF). Enable User Mode access to Serial Port F (I/O addresses 0x00D80x00DF). These bits are reserved and should be written with zeros.
Enable Dual-Mode Register Bit(s) 7:6 Value 00 01 10 11 5:1 0 0 1
(EDMR) Description
(Address = 0x0420)
Default (Rabbit 2000/3000) instruction set. This bit combination is reserved and must not be used. This bit combination is reserved and must not be used. Enhanced (Rabbit 5000) instruction set. These bits are reserved and should be written with zeros. Normal (System Mode only) operation. Enable System/User Mode operation.
367
368
31. SPECIFICATIONS
31.1 DC Characteristics
Table 31-1. Preliminary DC Electrical Characteristics
Parameter Operating Temperature Storage Temperature Core Supply Voltage Core Current @ 100 MHz, Wi-Fi enabled, 25C Core Core Current @ 100 MHz, Wi-Fi disabled, 25C Core Current @ 50 MHz, Wi-Fi disabled, 25C Core Current @ 32.768 kHz, Wi-Fi disabled, 25C I/O Ring Supply Voltage, 3.3 V I/O Ring Current @ 88.4736 MHz, 25C I/O Ring Current @ 29.4912 MHz, 25C I/O Ring I/O Ring Current @ 32.768 kHz, 25C Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output drive: A[19:0], /CS[2:0], /OE[1:0], WE[1:0] D[7:0] /IOWR, /IORD, /IOBEN PA[7:0], PB[7:0], PC[7:0], PD[7:0], PH[7:0] PE[7:0] All other pins VIL VIH VOL VOH 2.4 V 2.0 V 0.0 V 3.3 V 0.4 V IIO VDDIO 3.0 V ICORE Symbol TA VDDCORE Min -40C -55C 1.65 V 1.8 V 194 mA 32 mA 17 mA 2 mA 3.3 V 22 mA 12 mA 5 mA 0.8 V 3.6 V Typ Max 85C 125C 1.90 V
IDRIVE
16 mA 8 mA 16 mA 8 mA 16 mA 8 mA
Chapter 31 Specifications
369
Table 31-2. Preliminary Battery-Backed DC Electrical Characteristics (VDDCORE = 1.8V 10%, VDDIO = 3.3V 10%, TA = -40C to 85C)
Parameter VBAT Supply Voltage VBAT VBAT Current (rest of device powered) (rest of device powered down) VBATIO Supply Voltage (rest of device powered) (rest of device powered down) VBATIO Current (rest of device powered) (rest of device powered down) Symbol VBAT IVBAT Min 1.65 V Typ 1.8 V Max 1.90 V
22 A 290 nA
VBATIO
VBATIO
1.65 V 1.65 V
3.3 V 1.8 V
3.6 V 3.6 V
IVBATIO
200 nA 200 nA
370
31.2 AC Characteristics
Table 31-3. Preliminary AC Electrical Characteristics (VDDCORE = 1.8 V 10%, VDDIO = 3.3 V 10%, TA = -40C to 85C)
Parameter Main Clock Frequency on CLKI Real-Time Clock Frequency on CLK32K Ethernet Clock Frequency Wi-Fi Clock Frequency Symbol fmain fRTC fEth fWiFi 32.768 kHz 25 MHz 100 ppm 20 MHz 100 ppm Min Typ Max 100 MHz
371
31.3 Memory Access Times

All access time measurements are taken at 50% of signal height. 31.3.1 Memory Reads
Table 31-4. Preliminary Memory Read Time Delays (VDDCORE = 1.8 V 10%, VDDIO = 3.3 V 10%, TA = -40C to 85C)
Parameter Clock to Address Delay Clock to Memory Chip Select Delay Clock to Memory Read Strobe Delay Data Setup Time Data Hold Time Symbol Tadr TCSx TOEx Tsetup Thold Min 3 ns 3 ns 3 ns 1 ns 0 ns Typ Max 8 ns 6 ns 6 ns
31.3.2 Memory Writes

Table 31-5. Preliminary Memory Write-Time Delays (VDDCORE = 1.8 V 10%, VDDIO = 3.3 V 10%, TA = -40C to 85C)
Parameter Clock to Address Delay Clock to Memory Chip Select Delay Clock to Memory Write Strobe Delay High Z to Data Valid Relative to Clock Data Valid to High Z Relative to Clock Symbol Tadr TCSx TWEx TDVHZ TDVHZ Min 3 ns 3 ns 3 ns 3 ns 3 ns Typ Max 8 ns 6 ns 6 ns 8 ns 8 ns
372
Memory Read (no wait states)

T1 T2
CLK A[19:0]
Tadr valid
/CSx /OEx D[7:0]
TCSx
TCSx
TOEx
Tsetup valid Thold
TOEx
Memory Write (no extra wait states)

T1 Tw T2
CLK A[19:0] /CSx /WEx D[7:0]

Tadr TCSx TCSx valid
TWEx
TWEx valid
TDHZV
TDVHZ
Figure 31-1. Memory Read and Write Cycles
373
Memory Read (no wait states)

T1 T2
CLK A[19:0]
Tadr valid
/CSx /OEx D[7:0]
TCSx
TCSx
TOEx
Tsetup valid Thold
TOEx
Memory Write (no extra wait states)

T1 Tw T2
CLK A[19:0] /CSx /WEx D[7:0]

Tadr TCSx TCSx valid
TWEx
TWEx valid TDHZV TDVHZ
Figure 31-2. Memory Read and Write CyclesEarly Output Enable and Write Enable Timing
374
31.3.3 External I/O Reads

Table 31-6. Preliminary External I/O Read Time Delays (VDDCORE = 1.8 V 10%, VDDIO = 3.3 V 10%, TA = -40C to 85C)
Parameter Clock to Address Delay Clock to Memory Chip Select Delay Clock to I/O Chip Select Delay Clock to I/O Read Strobe Delay Clock to I/O Buffer Enable Delay Data Setup Time Data Hold Time Symbol Tadr TCSx TIOCSx TIORD TBUFEN Tsetup Thold Min 4 ns 3 ns 4 ns 3 ns 3 ns 1 ns 1 ns Typ Max 8 ns 6 ns 10 ns 7 ns 6 ns
31.3.4 External I/O Writes

Table 31-7. Preliminary External I/O Write Time Delays (VDDCORE = 1.8 V 10%, VDDIO = 3.3 V 10%, TA = -40C to 85C)
Parameter Clock to Address Delay Clock to Memory Chip Select Delay Clock to I/O Chip Select Delay Clock to I/O Write Strobe Delay Clock to I/O Buffer Enable Delay High Z to Data Valid Relative to Clock Data Valid to High Z Relative to Clock Symbol Tadr TCSx TIOCSx TIOWR TBUFEN TDHZV TDVHZ Min 4 ns 3 ns 4 ns 3 ns 3 ns 3 ns 1 ns Typ Max 8 ns 6 ns 10 ns 7 ns 6 ns 6 ns 2 ns
375
External I/O Read (no extra wait states)

T1 Tw T2
CLK A[23:0]
Tadr valid
/CSx /IOCSx /IORD (normal) /IORD (early) /BUFEN D[7:0] (normal) D[7:0] (early)
TCSx
TCSx
TIOCSx
TIOCSx
TIORD
TIORD
TIORD
TIORD
TBUFEN
TBUFEN Tsetup valid Thold valid
Tsetup Thold
Figure 31-3. I/O Read CyclesNo Extra Wait States
NOTE: /IOCSx can be programmed to be active low (default) or active high.
376
External I/O Write (no extra wait states)

T1 Tw T2
CLK A[23:0]
Tadr valid
/CSx /IOCSx /IOWR (normal) /IOWR (early) /BUFEN D[7:0]
TCSx
TCSx
TIOCSx
TIOCSx
TIOWR
TIOWR
TIOWR
TIOWR
TBUFEN valid TDHZV
TBUFEN
TDVHZ
Figure 31-4. I/O Write CyclesNo Extra Wait States
NOTE: /IOCSx can be programmed to be active low (default) or active high.
377
31.3.5 Memory Access Times In computing memory requirements, the important considerations are the address access time, output-enable access time, and minimum write-pulse required. Increasing the clock doubler delay increases the output-enable time, but decreases the memory write-pulse width. The early write-pulse option can be used to ensure a long-enough write pulse, but then it must be ensured that the write pulse does not begin before the address lines have stabilized. The clock doubler has an affect on the memory access times. It works by ORing the clock with a delayed version of itself. The nominal delay varies from 3 to 20 ns, and is set under program control. Any asymmetry in the main clock input before it is doubled will result in alternate clocks having slightly different periods. Using the suggested oscillator circuit, the asymmetry is no worse than 52%48%. This results in a given clock being shortened by the ratio 50/52, or 4% worst-case. The memory access time is not normally affected because the memory bus cycle is two clocks long and includes both a long and a short clock, resulting in no net change arising from asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly. When the clock spectrum spreader is enabled, clock periods are shortened by a small amount, depending on whether the normal or the strong spreader setting is used, and depending on the operating voltage. If the clock doubler is used, the spectrum spreader affects every other cycle and reduces the clock high time. If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. Of course, the spectrum spreader also lengthens clock cycles, but only the worst-case shortening is relevant for calculating worst-case access times. The numbers given for clock shortening with the doubler disabled are the combined shortening for two consecutive clock cycles, worst case. The required memory address and output-enable access time for some typical clock speeds are given in Table 31-8 below. It is assumed that the clock doubler is used, that the clock spreader is enabled in the normal mode, that the memory early output-enable is on, and that the address bus has a load of 60 pF.
Table 31-8. Preliminary Memory Requirements (VDDCORE = 1.8 V 10%, VDDIO = 3.3 V 10%, TA = -40C to 85C, address bus loading = 60 pF)
Clock Frequency (MHz) 22.11 29.49 44.24 58.98 Period (ns) 45 34 22.5 17 Clock Doubler Nominal Delay (ns) 20 16 10 6 Memory Address Memory OutputAccess Enable Access (ns) (ns) 78 56 33.5 22 51 36 22 19
378
All important signals on the Rabbit 5000 are output-synchronized with the internal clock. The internal clock is closely synchronized with the external clock, which is available on the CLK pin. The delay in signal output depends on the capacitive load on the output lines. In the case of the address lines, which are critically important for establishing memory access time requirements, the capacitive loading is usually in the range of 25100 pF, and the load is due to the input capacitance of the memory devices and PC trace capacitance. Delays are expressed from the waveform midpoint in keeping with the convention used by memory manufacturers. Table 31-9 lists the delays in gross memory access time for several values of VDDIO.
Table 31-9. Preliminary Data and Clock Delays (VDD 10%, Temp. -40C to 85C)
Worst-Case Spectrum Spreader Delay (ns) 2 ns setting no dbl / dbl 4.5 / 9
VDDIO (V)
Clock to Address Output Delay (ns)
Data Setup Time Delay (ns) 0.5 ns setting 1 ns setting no dbl / dbl no dbl / dbl 1 2.3 / 2.3 3 / 4.5
3.3
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is shortened or lengthened by a maximum amount given in the table above. The shortening takes place by shortening the high part of the clock. If the doubler is not enabled, then every clock is shortened during the low part of the clock period. The maximum shortening for a pair of clocks combined is shown in the table. The gross memory access time is 2T, where T is the clock period. To calculate the actual memory access time, subtract the clock to address output time, the data in setup time, and the clock period shortening due to the clock spectrum spreader from 2T.
Example Memory Access Time Calculation
clock = 29.49 MHz, so T = 34 ns clock to address output delay = 6 ns (see Table 31-9) data setup time = 1 ns spectrum spreader is on in 1 ns mode, resulting in a loss of 3 ns worst-case (see Table 31-9) The access time is given by access time = 2T - (clock to address) - (data setup) - (spreader delay) = 68 ns - 6 ns - 1 ns - 3 ns = 58 ns
Similarly, the gross output-enable access time is T + minimum clock low time (it is assumed that the early output enable option is enabled). This is reduced by the spectrum
379
spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetry of the original oscillator clock.
Example Output-Enable Access Time Calculation NOTE: There is some process and temperature variation in the clock doubler settings. As a rule of thumb, a 20% variation should be considered. When the doubler is enabled, 80% of the nominal value should be used for the memory access time calculation.
clock = 29.49 MHz, so T = 34 ns the clock doubler has a nominal delay of 16 ns (see Table 31-8), resulting in a minimum clock low time of 80% 16 ns = 12.8 ns clock to output enable is 5 ns spectrum spreader is on in 1 ns mode, resulting in a loss of 4.5 ns worst-case (see Table 31-9) main clock asymmetry is 52% / 48%, resulting in a loss of 4% of the clock period, or 1.4 ns The output enable access time is given by access time = T + (min. clock low) - (clock to output enable) (spreader delay) - (asymmetry delay) - (data setup time) = 34 ns + 12.8 ns - 5 ns - 4.5 ns - 1.4 ns = 36 ns
380
31.4 Clock Speeds

31.4.1 Recommended Clock/Memory Configurations The preferred configuration for a Rabbit-based system is to use an external crystal or resonator that has a frequency one-half of the maximum internal clock frequency. The oscillator frequency can be doubled or divided by 2, 4, 6, or 8, giving a variety of operating speeds from the same crystal frequency. In addition, the 32.768 kHz oscillator that drives the battery-backable clock can be used as the main processor clock and, to save the substantial power consumed by the fast oscillator, the fast oscillator can be turned off. This scenario is called the sleepy mode, where the clock speed is from 2 kHz to 32 kHz. Table 31-10 describes some recommended clock and memory configurations for both 8-bit and 16-bit memory devices. Optimal configurations for using 12 ns, 15 ns, 4555 ns, and 70 ns memories are shown. Note that there is always at least one wait state in the 16bit mode.
Table 31-10. Some Recommended Clock/Memory Configurations
Input Internal Frequency Frequency (MHz) (MHz) Recommended Memory Timing 8-bit Devices 12 ns, 0 wait states 15 ns, 1 wait state 45 ns, 4 wait states 55 ns, 4 wait states 70 ns not possible 12 ns, 0 wait states 15 ns, 0 wait states 45 ns, 2 wait states 55 ns, 4 wait states 70 ns, 4 wait states 12 ns, 0 wait states 15 ns, 0 wait states 45 ns, 0 wait states 55 ns, 1 wait state 70 ns, 1 wait state 12 ns, 0 wait states 15 ns, 0 wait states 45 ns, 0 wait states 55 ns, 0 wait states 70 ns, 1 wait state 16-bit Devices (1 wait state min.) 12 ns, 1 wait state 15 ns, 2 wait state 45 ns, 4 wait states 55 ns, 5 wait states 70 ns, 6 wait states 12 ns, 1 wait state 15 ns, 1 wait state 45 ns, 4 wait states 55 ns, 4 wait states 70 ns, 5 wait states 12 ns, 1 wait state 15 ns, 1 wait state 45 ns, 1 wait state 55 ns, 2 wait states 70 ns, 2 wait states 12 ns, 1 wait state 15 ns, 1 wait state 45 ns, 1 wait state 55 ns, 1 wait state 70 ns, 2 wait states Optimal Use
44.2368
88.4736
12 ns devices
36.8640
73.7280
15 ns devices
18.4320
36.8640
45 ns devices
14.7456
29.4912
55 ns devices
381
Table 31-10. Some Recommended Clock/Memory Configurations

Input Internal Frequency Frequency (MHz) (MHz) Recommended Memory Timing 8-bit Devices 12 ns, 0 wait states 15 ns, 0 wait states 45 ns, 0 wait states 55 ns, 0 wait states 70 ns, 0 wait states 16-bit Devices (1 wait state min.) 12 ns, 1 wait state 15 ns, 1 wait state 45 ns, 1 wait state 55 ns, 1 wait state 70 ns, 1 wait state Optimal Use
11.0592
22.1184
70 ns devices
The Rabbit 5000 is rated for a minimum clock period of 10 ns for both commercial and industrial specifications. The commercial rating calls for a 5% voltage variation from 3.3 V, and a temperature range from -40 to + 70C. The industrial ratings stretch the voltage variation to 10% over a temperature range from -40 to + 85C. This corresponds to maximum clock frequencies of about 100 MHz (commercial or industrial). If the clock doubler or spectrum spreader is used, these maximum ratings must be reduced as shown in Table 31-11.
382
Table 31-11. Preliminary Maximum Clock Speeds (VDD 10%, Temp. -40C to +85C)
Industrial Ratings Conditions Minimum Period (ns) 17 20 21 19 Maximum Frequency (MHz) 58.8 50.0 47.6 52.6 1 > (clock low clock high) > 0 1 > (clock low clock high) > -1 Duty Cycle Requirements (ns)
No Doubler or Spreader Spreader Only Normal Spreader Only Strong Doubler Only (8 ns delay) Doubler Only (internal 50% clock) Spreader Normal with Doubler (8 ns delay) Spreader Normal with Doubler (8 ns delay), Internal 50% Clock Spreader Only Strong Spreader Strong with Doubler (8 ns delay)
20
50
21
47.6
4 > (clock low clock high) > 2
24
41.6
1 > (clock low clock high) > -1
21.5
46.5 8 > (clock low clock high) > 6
23
43.5
When the doubler is used, the duty cycle of the clock becomes a critical parameter. The duty cycle should be measured at the separate clock output pin (pin 2). The minimum period must be increased by any amount that the clock high time is greater or less than specified in the duty-cycle requirement. For example, consider a design where the spreader and doubler are enabled, with 8 ns nominal delay in the doubler. The high and low clock are equal to within 1 ns. This violates the duty cycle requirement by 3 ns since (clock low - clock high) can be as small as -1 ns, but the requirement is that it not be less than 2 ns. Thus, 3 ns must be added to the minimum period of 21 ns, giving a minimum period of 24 ns and a maximum frequency of 41.6 MHz (commercial).
383
Since the built-in high-speed oscillator buffer generates a clock that is very close to having a 50% duty cycle, to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty-cycle adjustment by changing the resistance of the power and ground connections as shown below.
+3.3 V
Adjust the values of these resistors to vary the duty cycle
XTALA1
Figure 31-5. External Oscillator Buffer
384
31.5 Power and Current Consumption

Various mechanisms contribute to the current consumption of the Rabbit 5000 processor while it is operating, including current that is proportional to the voltage alone (leakage current) and dependent on both voltage and frequency (switching and crossover current). To reduce current consumption, the clock can be divided down in one of the sleepy modes; see Table 29-1 for more details. Figure 31-6 shows a typical current draw as a function of the main clock frequency while Wi-Fi is disabled. The values shown do not include any current consumed by external oscillators or memory. It is assumed that approximately 30 pF is connected to each address line.
70 60
CURRENT (mA)
50 40 30 20 10 0 2 10
total
IIO
ICORE
20
30
40
50
60
CPU/PERPHERAL CLOCKS (MHz)

Figure 31-6. Typical Current Draw as a Function of the Main Clock Frequency (Wi-Fi disabled)
When the 802.11 Wi-Fi peripheral is enabled, the current draw will increase by as much as 210mA, depending on activity.
385
31.5.1 Sleepy Mode Current Consumption The Rabbit 5000 supports designs with very low power consumption by using features such as the ultra-sleepy modes and self-timed chip selects. At the low frequencies possible in the ultra-sleepy modes (as low as 2 kHz), the external memory devices become significant factors in the current consumption unless one of the short or self-timed chip selects are used. The I/O current use will vary with pin activity.
Table 31-12. Typical Sleepy Mode Current Consumption (-40C to +85C)
Pin Voltage 1.8 V 3.3 V Current 2 mA 5 mA
ICORE IIO
386
31.5.2 Battery-Backed Clock Current Consumption For the battery-backed features of the Rabbit 5000 to perform while the processor is powered down, both the VBAT and VBATIO pins need to be supplied properly. The VBAT pin powers the internal real-time clock and the battery-backed SRAM, while VBATIO powers the /RESET, /CS1, CLK32K, and RESOUT pins. Note that the VBATIO pin can be powered at 1.8 V during powerdown even if the processor is running at 3.3 V normally. A circuit to switch between a 1.82.0 V battery and the main power can use the RESOUT pin to switch the power source for the VBATIO pin. R is a current-limiting resistor that should be adjusted for the battery voltage; a good value to use for a 3.0 V battery is 150 k.
VBAT
BAT54
3.3 V Main Power FDV302P (p channel)
R
VBATIO
Rabbit 4000 RESOUT 2.2 nF
Figure 31-7. Switching Circuit for VBATIO Pin
Table 31-13 shows the typical current consumption for these pins while the remainder of the Rabbit 5000 is powered down.
Table 31-13. Typical Battery-Backed Current Consumption (-40C to +85C)
Pin VBAT VBATIO Voltage 1.8 V 1.8 V Current 290 nA 200 nA
387
388
32. PACKAGE SPECIFICATIONS AND PINOUT

32.1 Ball Grid Array Packages
32.1.1 Pinout 17 17 Ethernet Option
1 A B C D E F G H J K L M N P R T U
VDDIO
2
VSS!
3
VDD!
4
VSSIO
5
TXD3
6
VGA1
7
PB4
10 11 12 13 14 15 16 17
RXD1 VSSIO PB0 PE6 A33GND VIN8 VDDIO
TXCLK SYSCFG1 SMODE0
A7
A6
LFT
PB7
TXD1
TX_EN
CLK
CLKI
SMODE1 VSSIO
VDDIO
RX_DV
VDDIO
PC7
TESTIN0 VDD33
VSSIO
A8
A0
PB6
VSSIO
TX_ER
VSSIO
CLKIEN
COL
RXD2
PB3
RX_ER
CRS
PB1
TESTIN1
A4
PD5
PD4
VSSIO
/OE1
PA0
TXD2
PB5
VDDIO /WDTOUT SYSCFG0 RXD3
RXD0
PB2
RX_CLK
PE7
A3
A2
A5
PE3
D13/PH5 VDDINT D14/PH6 D15/PH7 VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSINT
VSSIO /STATUS VDDIO
VDDIO D12/PH4 VSSINT
VDDIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
PE2
VDDIO
PD7
VDDINT
VSSIO
A19
PE4
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D0
D1
VSSIO
A1
VDDINT D9/PH1 D11/PH3 D10/PH2 VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D3
PE1
VDDIO
/CS0
MDIO
VSSINT D8/PH0
A9
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D4
VDDINT
D2
A11
A10
VDDIO
MDC
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D6
D7
D5
VSSINT
VSSIO
VDD!
MDO
MDOEN
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
A17
/WE1
PE0
PE5
VDDIO
VSS!
A12
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VDDIO
VDDINT
PD6
VDDIO
VSSIO
A14
A13
PA1
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
PD1
PD2
VSSINT
PD3
A18
PA2
/CS2
/OE0
AVDD!
ADVCM VDDINT
/IOWR
/RESET
VBAT
PC6
PC2
TESTIN2 VOUTPI
PA7
A16
VSSIO
PA3
VSSIO
/WE0
VREFN A33GND!
VININ
AGND!
VDDIO
VSSIO
CLK32K
VSSIO
PC3
VDDIO
VOUTNI
AGNDI
PD0
A15
VDDIO
AVDD!
VINQN
IBIAS
VINIP
AVDD!
PA4
/IOBEN
VBATIO
VSSIO
PC4
PC0
DAVBG
DAVCM
GND!
PA5
PA6
AGND! AGNDREF VREFP
VINQP
ADVBG VSSINT
/IORD
/CS1
RESOUT
PC5
PC1
VDD!
AVDD! VOUTPQ VOUTNQ
VSSIO
VDDIO
Figure 32-1. Ethernet Option Pinout Looking Through the Top of Package
Chapter 32 Package Specifications and Pinout
389
32.1.2 Pinout 17 17 Wi-Fi Option

1 A B C D E F G H J K L M N P R T U
VDDIO
2
VSS!
3
VDD!
4
VSSIO
5
VGA4
6
VGA1
7
PB4
10 11 12 13 14 15 16 17
PB0 PE6 A33GND VIN8 VDDIO
LOCK SYSCFG1 SMODE0 ANT_SELB VSSIO
A7
A6
LFT
PB7
VGA2
TX_ON
CLK
CLKI
SMODE1 VSSIO
VDDIO
RX_ON
VDDIO
PC7
TESTIN0 VDD33
VSSIO
A8
A0
PB6
VSSIO
VGA0
VSSIO
CLKIEN
RXHP
LNA0
PB3
PA2G_ON ACT_LED
PB1
TESTIN1
A4
PD5
PD4
VSSIO
/OE1
PA0
VGA3
PB5
VDDIO /WDTOUT SYSCFG0 LNA1
ANT_SEL
PB2
PA5G_ON
PE7
A3
A2
A5
PE3
D13/PH5 VDDINT D14/PH6 D15/PH7 VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSINT
VSSIO /STATUS VDDIO
VDDIO D12/PH4 VSSINT
VDDIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
PE2
VDDIO
PD7
VDDINT
VSSIO
A19
PE4
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D0
D1
VSSIO
A1
VDDINT D9/PH1 D11/PH3 D10/PH2 VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D3
PE1
VDDIO
/CS0
CLK_IN VSSINT D8/PH0
A9
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D4
VDDINT
D2
A11
A10
VDDIO
SCLK
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
D6
D7
D5
VSSINT
VSSIO
VDD!
SDATA
SENB
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
A17
/WE1
PE0
PE5
VDDIO
VSS!
A12
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VDDIO
VDDINT
PD6
VDDIO
VSSIO
A14
A13
PA1
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
PD1
PD2
VSSINT
PD3
A18
PA2
/CS2
/OE0
AVDD!
ADVCM VDDINT
/IOWR
/RESET
VBAT
PC6
PC2
TESTIN2 VOUTPI
PA7
A16
VSSIO
PA3
VSSIO
/WE0
VREFN A33GND!
VININ
AGND!
VDDIO
VSSIO
CLK32K
VSSIO
PC3
VDDIO
VOUTNI
AGNDI
PD0
A15
VDDIO
AVDD!
VINQN
IBIAS
VINIP
AVDD!
PA4
/IOBEN
VBATIO
VSSIO
PC4
PC0
DAVBG
DAVCM
GND!
PA5
PA6
AGND! AGNDREF VREFP
VINQP
ADVBG VSSINT
/IORD
/CS1
RESOUT
PC5
PC1
VDD!
AVDD! VOUTPQ VOUTNQ
VSSIO
VDDIO
Figure 32-2. Wi-Fi Option Pinout Looking Through the Top of Package
390
32.1.3 Mechanical Dimensions and Land Pattern
TOP VIEW
1 A B 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
BOTTOM VIEW
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B
0.80
C D E F G
C D E F G
15.00 0.05
H J K L M N P
H J K L M N P
1.10
R T U
R T U
1.10 15.00 0.05
0.80
Figure 32-3. BGA Package Outline
0.15~0.25
1.40 (max.)
Ball Pitch: 0.80 mm Ball Diameter: 0.40 mm
391
Table 32-1. Ball and Land Size Dimensions

Nominal Ball Diameter (mm) 0.40 Tolerance Variation (mm) 0.450.35 Ball Pitch (mm) 0.80 Nominal Land Diameter (mm) 0.35 Land Variation (mm) 0.350.30
The design considerations in Table 32-2 are based on 5 mil design rules and assume a single conductor between solder lands.
Table 32-2. Design Considerations (all dimensions in mm)
Key A B C D E F G Feature Solder Land Diameter NSMD Defined Land Diameter Land to Mask Clearance (min.) Conductor Width (max.) Conductor Spacing (typ.) Via Capture Pad (max.) Via Drill Size (max.) Recommendation 0.356 (0.014) 0.406 (0.016) 0.076 (0.003) 0.127 (0.005) 0.127 (0.005) 0.406 (0.016) 0.203 (0.008)
D A B
G E
Land and Trace
Via
392
32.2 Rabbit Pin Descriptions

Table 32-3 lists all the pins on the Rabbit 5000 along with the data direction of the pin, its function, and the pin number on the die.
Table 32-3. Rabbit 5000 Pin Descriptions
Pin Group Pin Name CLK CLK32K /RESET Hardware RESOUT CLKI CLKIEN A[19:0] CPU Buses D[9:0] /WDTOUT Status & Control STATUS SMODE1 SMODE0 /CS0 Chip Selects /CS1 /CS2 Output Enables Write Enables /OE0 /OE1 /WE0 /WE1 /IOBEN I/O Control /IORD /IOWR PA[7:0] PB[7:0] PC[7:0] I/O Ports PD[7:0] PE[7:0] PH[7:0] Input/Output Input/Output Input/Output I/O Parallel Port D I/O Parallel Port E I/O Parallel Port H various various various
393
Direction Output Input Input Output Input Output Output Bidirectional Output Output Input Output Output Output Output Output Output Output Output Output Output Input/Output Input/Output Input/Output
Function Internal Clock Output 32 kHz Clock In Master Reset Reset Output Main Clock In Main Clock Enable Address Bus Data Bus Watchdog Timer Timeout Instruction Fetch First Byte Bootstrap Mode & Tamper Detect Memory Chip Select 0 Memory Chip Select 1 Memory Chip Select 2 Memory Output Enable 0 Memory Output Enable 1 Memory Write Enable Memory Write Enable I/O Buffer Enable I/O Read Enable I/O Write Enable I/O Parallel Port A I/O Parallel Port B I/O Parallel Port C
LFBGA Ball B7 R10 P9 U9 B8 C7 various various D7 E16 B9, A10 H17 U8 P3 P4 D2 R3 L16 T8 U7 P8 various various various
Table 32-3. Rabbit 5000 Pin Descriptions (continued)

Pin Group Pin Name MDC MDO MDOEN TXD0 TXD1 TXD2 TXD3 TX_EN TX_ER Ethernet COL CRS RX_CLK RX_DV RX_ER RXD0 RXD1 RXD2 RXD3 TX_CLK MDIO Direction Function LFBGA Ball K4 L3 L4 A6 B5 D4 A5 B6 C5 Media-Independent Interface (MII) C8 C12 D12 B12 C11 D10 A11 C9 D9 A8 J1 C12 D10 A11 C9 D9 C11 D12 B17 G8 K4 K3 L4 B6 C5 A6 B5 D4 A5 J1 A8
Output
Input
Bidirectional
Wi-Fi
ACT_LED ANT_SEL ANT_SELB LNA0 LNA1 PA2G_ON PA5G_ON RX_ON RXHP Output SCLK SDATA SENB TX_ON VGA0 VGA1 VGA2 VGA3 VGA4 CLK_IN LOCK Input
Wi-Fi Interface
394
Table 32-3. Rabbit 5000 Pin Descriptions (continued)

Pin Group Pin Name VININ VINIP VINQN VINQP PD4 Analog VOUTNI VOUTPI VOUTNQ VOUTPQ PD5 VIN8 PD6 Direction Function LFBGA Ball R6 T5 T3 U4 C17 R14 P14 U15 U14 C16 Analog Component 2 Slow A/D Converter A16 M16
Input
Analog Component 0 Fast A/D Converter
Clock
Output
Analog Component 1 Fast D/A Converter
Clock Input Clock
395
396
APPENDIX A. PARALLEL PORT PINS WITH ALTERNATE FUNCTIONS

A.1 Alternate Parallel Port Pin Outputs
Table A-1. Alternate Parallel Port A and B Pin Outputs
Alternate Output Options Pin Serial Clock PA[7:0] PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 SCLKA SCLKB External I/O Bus ID[7:0] IA5 IA4 IA3 IA2 IA1 IA0 IA7 IA6 Slave Port SD[7:0] /SLVATTN /SCS SA1 SA0 /SRD /SWR
Appendix A Parallel Port Pins with Alternate Functions
397
Table A-2. Alternate Parallel Port C, D, E, and H Pin Outputs

Alternate Output Option Pin 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 TXA TXA TXB TXB TXC TXC TXD TXD IA7 TXA IA6 TXB IA7 SCLKC IA6 SCLKD I7 I6 I5 I4 I3 I2 I1 I0 1 I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 /A0 A23 A22 A21 A20 I7 I6 I5 I4 I3 I2 I1 I0 2 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 PWM3 PWM2 PWM1 PWM0 TIMER C3 TIMER C2 TIMER C1 TIMER C0 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF 16-bit Data D15 D14 D13 D12 D11 D10 D9 D8
398
A.2 Alternate Parallel Port Pin Inputs

Table A-3. Alternate Parallel Port Pin Inputs
Pin PA[7:0] PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6
Input Capture I/O Handshake
DMA DREQ1 DREQ0 DREQ1 DREQ0
External Network Interrupt
Quadrature Slave Port Decoder
Serial Ports AD SCLKA SCLKB RXA RXB RXC RXD RXA RXB RXC SCLKC RXD SCLKD RXA
Serial Ports EF RXE RCLKE TCLKE RXF RCLKF TCLKF RXE RCLKE TCLKE RXF RCLKF TCLKF RXE
INT1 INT0
ECLK QRD2A QRD2B QRD1A QRD1B
SD[7:0] /SLVATTN /SCS SA1 SA0 /SRD /SWR /SCS
Appendix A Parallel Port Pins with Alternate Functions
399
Table A-3. Alternate Parallel Port Pin Inputs (continued)

Pin PE5 PE4 PE3 PE2 PE1 PE0
Input Capture I/O Handshake
DMA DREQ1 DREQ0
External Network Interrupt
Quadrature Slave Port Decoder
Serial Ports AD RXB RXC SCLKC RXD SCLKD
Serial Ports EF RCLKE TCLKE RXF RCLKF TCLKF
INT1 INT0 INT1 INT0
QRD2A QRD2B QRD1A QRD1B
400
APPENDIX B. RABBIT 5000 ERRATA

The Rabbit 5000 began shipping in 2008 on multiple platforms. Several bugs were found in the design after the chip was released, and are discussed in this appendix.
B.1 Errata
The following bugs have been identified in the Rabbit 5000 design, and are present in all devices currently available. All Dynamic C libraries have been corrected these issues, and the compiler correctly generates operational code from C programs as noted below. However, customers should be aware of them when writing code in assembly.
1. Noise in 802.11b Wi-Fi transmissions The state machine for 802.11b transmissions can generate extra noise outside the allowed 802.11b frequency range in some situations. To avoid this possibility, the following corrections are implemented in the Dynamic C Wi-Fi library: (a) For 1 and 2 Mbps transmission rates, the noise only exists for certain clock alignments with respect to other clocks in the design. When Wi-Fi is enabled, the Wi-Fi clock is checked for proper alignment and restarted repeatedly until the correct alignment occurs. (b) For 5.5 and 11 Mbps, the noise will not exist for packet lengths that are multiples of 11, again due to clock alignment. The Dynamic C Wi-Fi library will pad all outgoing packets to a safe length to avoid the noise issue. Note that this means that the maximum MTU is actually 1441 bytes and not the standard 1450. 2. Instruction alignment issues there are several issues with alignment of particular instructions in 16-bit mode; all instructions function properly in 8-bit mode. Dynamic C will automatically align all instructions appropriately by adding NOP instructions to the generated code. The instructions of concern in 16-bit mode and the required alignment are: (a) LD pd,ps+d must be even-aligned. (b) LD BCDE,d must be odd-aligned. (c) LD HL,(n) must be even-aligned.
Appendix B Rabbit 5000 Errata
401
Additional instructions need to be odd-aligned to avoid an additional wait state being generated; see issue 4 below. 3. IOI/IOE BIT instruction alignment issue if the code sequences IOI BIT b,(HL) or IOE BIT b,(HL) are not even-aligned, the effect of the IOI/IOE prefix will be lost and a memory read will occur instead of a register read. Dynamic C does not manage this automatically, but all instances of these code sequences in Dynamic C libraries have been properly aligned. 4. RET cc bug this instruction requires a single-byte instruction to follow it for proper operation. Dynamic C does not correct this automatically, but it has been corrected in all Dynamic C libraries. 5. Extra wait state generation the instructions listed below will generate an additional wait state during the operation when even-aligned in 16-bit mode: LD A,(ps+d) LD HL,(ps+d) LD HL,(SP+n) LD HL,(IX+d) JR e LD (pd+d),A LD (pd+d),HL LD (SP+n),HL LD (IX+d),HL JR cc,e
Dynamic C does nothing to correct for this issue since an additional wait state will not significantly affect code. 6. Read-modify-write instruction bug this bug has been found to exist in all Rabbit 2000, 3000, 4000, and 5000 processors. The bug manifests itself by using the wait state setting of the code memory for the final write to data memory, instead of the correct data memory wait state setting. This misbehavior has the potential of causing memory timing errors if the data memory requires more wait states than the code memory. The instructions are affected in both 8- and 16-bit modes, and are listed here: DEC (HL) DEC (IX+d) DEC (IY+d) DEC (pp+d) INC (HL) INC (IX+d) INC (IY+d) INC (pp+d) SET b,(HL) RL (HL) RL (IX+d) RL (IY+d) RR (HL) RR (IX+d) RR (IY+d)
RLC (HL) RLC (IX+d) RLC (IY+d)
RRC (HL) RRC (IX+d) RRC (IY+d)
SRA (HL) SRA (IX+d) SRA (IY+d)
RES b,(HL)
CBM
In Rabbit-branded products, this only has the potential to affect fast SRAM products where code executing in high-speed memory performs a write to the slow batterybacked SRAM. Dynamic C does not generate these instructions from C code, and all instances of them in existing libraries where a potential issue would occur have been
402
corrected. Customers writing assembly code that accesses data in battery-backed memory should avoid using these instructions to do so.
Appendix B Rabbit 5000 Errata
403
404
INDEX
Numerics
32 kHz clock ......................... 30 oscillator circuit ................ 30
A
analog components ............. 215 block diagram ................. 218 clocks .............................. 219 dependencies ................... 219 fast A/D converter Analog Component 0 Control Register .............. 224 Analog Component 0 LSB Registers ................... 223 Analog Component MSB Registers ................... 223 fast D/A converter Analog Component 1 Control Register .............. 225 Analog Component 1 LSB Registers ................... 224 Analog Component 1 MSB Registers ................... 225 operation ......................... 220 registers ........................... 219 sample circuits ................ 221 slow A/D converter Analog Component 2 Control Register .............. 227 Analog Component 2 LSB Register .................... 226 Analog Component 2 MSB Register .................... 226 specifications .................. 216 fast A/D converter ....... 216 fast D/A converter ....... 216 slow A/D converter ..... 217
B
block diagram
Index
analog components ......... 218 bootstrap ............................ 38 breakpoints ...................... 332 clocks ................................ 22 DMA channels ................ 232 external I/O control ......... 318 external interrupts ............. 85 input capture channels .... 288 memory management ........ 60 Network Port B ............... 259 Network Port C ............... 282 Parallel Port A ................... 89 Parallel Port B ................... 94 Parallel Port C ................... 98 Parallel Port D ................. 107 Parallel Port E ................. 125 Parallel Port H ................. 144 PWM ............................... 309 Quadrature Decoder ........ 301 Rabbit 5000 ....................... 16 reset ................................... 38 Serial Ports A D ........... 173 Serial Ports E F ............ 188 slave port ......................... 204 system management .......... 46 Timer A ........................... 151 Timer B ........................... 157 Timer C ........................... 164 bootstrap ............................... 37 block diagram ................... 38 dependencies ..................... 39 memory fetch .................... 41 onchip-encryption SRAM . 42 register descriptions .......... 44 registers ............................. 38 breakpoints .......................... 331 block diagram ................. 332 dependencies ................... 334 interrupts ......................... 334 example ISR ................ 335 operation ......................... 334
overview ......................... 331 register descriptions ........ 336 registers ........................... 333 bugs workarounds DMA/HDLC/Ethernet interaction .................... 402 stack protection/DMA interaction ................ 401, 402
C
clock modes .......................... 24 clocks .................................... 21 32 kHz clock ..................... 30 oscillator circuit ............ 30 power consumption ....... 30 block diagram ................... 22 clock doubler .............. 27, 28 clock modes ...................... 24 clock speeds .................... 382 doubling/dividing .............. 21 EMI mitigation .................. 21 Ethernet clock ................... 21 maximum clock speed ...... 29 operation ........................... 24 overview ........................... 21 power consumption ........... 29 register descriptions .......... 32 registers ............................. 22 sleepy clock modes ........... 31 spectrum spreader ..... 21, 378 comparison with other Rabbit microprocessors ............ 18
D
design considerations BGA package .................. 392 dimensions BGA package .................. 391 DMA channels .................... 229
405
block diagram ..................232 buffer descriptor ..............235 buffer descriptor modes ...238 channel priorities .............238 clocks ...............................234 control ..............................230 dependencies ...................234 external requests ..............229 interrupts ..........231, 234, 236 example ISR ................236 memory addresses ...........230 operation ..........................235 overview ..........................229 priorities ..........................236 register descriptions .........243 registers ...........................233 setup ................................235 timed requests ..................230 transfer priorities .............236 transfer priority ................236 transfer rates ....................237 transfers ...........................231 use with peripherals .........242 DMA/HDLC/Ethernet interaction ....................402 Ethernet .......................242 HDLC serial ports .......242 PWM and Timer C ......242 DMA control .......................229
See breakpoints
I
input capture channels .........287 block diagram ..................288 clocks ...............................290 dependencies ...................290 interrupts .................290, 291 example ISR ................291 load parallel port output registers ...............................288 measure pulse widths ......287 modes ..............................287 input-capture mode ......287 input-count mode .........287 operation ..........................291 input-capture mode ......292 input-count mode .........292 overview ..........................287 register descriptions ........293 registers ...........................289 start and stop events ........287 interrupt priorities .................84 interrupts ...............................81 breakpoints ......................334 example ISR ................335 DMA channels 231, 234, 236 example ISR ................236 external interrupt vector table 83 external interrupts ........85, 86 block diagram ................85 clocks .............................86 dependencies .................86 example ISR ..................87 interrupt vectors .............86 operation ........................86 register descriptions .......88 registers .........................86 input capture channels ....290, 291 example ISR ................291 internal interrupt vector table 82 interrupt priorities ..............84 memory management ........62 Network Port B .......263, 265 Network Port C ...............286 operation ............................82 Parallel Port D .................109 Parallel Port E .................127 Parallel Port H .................145 priority levels ....................81 PWM ...............307, 310, 311
example ISR ................311 Quadrature Decoder 300, 302 example ISR ................303 Serial Ports A D ...........176 Serial Ports E F .............191 slave port .........203, 205, 208 example ISR ................208 system management ...45, 48, 49 System/User mode ..354, 360 Timer A ...................150, 153 example ISR ................153 Timer B ...................158, 159 example ISR ................159 Timer C ...................166, 167 example ISR ................167
L
land pattern BGA package ..................391 low-power operation ...........339 clock rates ........................341 clock modes .................341 handling unused pins .......341 operation ..........................341 overview ..........................339 register descriptions ........348 registers ...........................340 self-timed chip selects .....347 short chip selects .............342
E
ESD ESD sensitivity ..................14 external I/O bus ...................315 operation ..........................320 handshake ....................320 strobes ..........................320 external I/O control .............315 block diagram ..................318 clocks ...............................319 dependencies ...................319 external I/O bus ...............315 handshake ........................317 operation ..........................320 external I/O bus ...........320 handshake ....................320 strobes ..........................320 overview ..........................315 register descriptions .........321 registers ...........................318 strobes ..............................316
M
memory read and write cycles (no wait states) ..........................374 memory management ............57 block diagram ....................60 clocks .................................62 dependencies .....................62 interrupts ...........................62 logical memory space ........58 mapping physical memory space ..............................58 MMU operation .................64 operation ............................63 16-bit and page modes ...66 instruction and data space .. 68 memory protection ........68 MMU .............................63 read and write transactions 66 stack protection ..............69 stack protection/DMA inter-
H
hardware debugging.
406
action ................ 401, 402 overview ............................ 57 physical and logical memory mapping ........................ 59 register descriptions .......... 70 registers ................. 61, 62, 63 memory protection ................ 68
N
Network Port B block diagram ................. 259 clock ................................ 257 clocks .............................. 262 dependencies ................... 262 DMA transfers ................ 258 interrupts ................. 263, 265 operation ......................... 263 multicast addressing .... 266 receive ......................... 264 transmit ....................... 264 overview .......................... 257 receiver ............................ 258 register descriptions ........ 267 registers ........................... 260 setup ................................ 264 transmitter ....................... 257 Network Port C block diagram ................. 282 clocks .............................. 286 dependencies ................... 285 interrupts ......................... 286 operation ......................... 286 overview .......................... 281 registers ........................... 283
O
opcodes System/User mode .......... 358
P
Parallel Port A ....................... 89 alternate output functions .. 89 block diagram ................... 89 clocks ................................ 90 external I/O data bus ......... 89 operation ........................... 90 overview ............................ 89 register description ............ 95 register descriptions .......... 91 registers ............................. 89 slave port data bus ............. 89 Parallel Port B ....................... 93 alternate output functions .. 93
block diagram ................... 94 clocks ................................ 94 dependencies ..................... 94 external I/O bus ................. 93 operation ........................... 95 overview ............................ 93 register descriptions .......... 95 registers ............................. 94 slave port enabled ............. 93 SPCR setup ....................... 93 Parallel Port C ....................... 97 alternate input functions .... 97 alternate output functions .. 97 block diagram ................... 98 clocks ................................ 99 dependencies ..................... 99 operation ........................... 99 overview ............................ 97 PCDR setup ....................... 97 default ........................... 98 register descriptions ........ 100 registers ............................. 98 Parallel Port D .................... 105 alternate input functions .. 106 alternate output functions 105 block diagram ................. 107 clocks .............................. 109 dependencies ................... 109 interrupts ......................... 109 operation ......................... 110 overview .......................... 105 PDDR setup .................... 105 register descriptions ........ 111 registers ........................... 108 Parallel Port E ..................... 123 alternate input functions .. 124 alternate output functions 123 block diagram ................. 125 clocks .............................. 126 dependencies ................... 126 interrupts ......................... 127 operation ......................... 127 overview .......................... 123 PEDR setup ..................... 123 register descriptions ........ 128 registers ........................... 126 Parallel Port H .................... 143 alternate output functions 143 block diagram ................. 144 clocks .............................. 145 dependencies ................... 145 interrupts ......................... 145 operation ......................... 145 overview .......................... 143
PHDR setup .................... 143 register descriptions ........ 146 registers ........................... 144 peripherals system management .......... 45 pin descriptions ................... 393 alternate pin functions Parallel Port A and B outputs ........................... 397 Parallel Port C, D, and E outputs ...................... 398 parallel port inputs ...... 399 pin functions ....................... 393 alternate pin functions Parallel Port A and B outputs ........................... 397 Parallel Port C, D, and E outputs ...................... 398 parallel port inputs ...... 399 pinout .................................. 393 BGA package .......... 389, 390 power consumption ............... 29 pulse width modulator. See PWM PWM ................................... 307 block diagram ................. 309 channels .......................... 310 clocks .............................. 310 dependencies ................... 310 DMA channels ................ 308 interrupts ......... 307, 310, 311 example ISR ................ 311 operation ......................... 311 outputs ..................... 307, 308 overview ......................... 307 register descriptions ........ 312 registers ........................... 309 spreading function .......... 308
Q
Quadrature Decoder ............ 299 block diagram ................. 301 clocks ...................... 300, 302 counter operation ............ 299 dependencies ................... 302 inputs ............................... 299 interrupts ......... 300, 302, 303 example ISR ................ 303 operation ......................... 303 overview ......................... 299 register descriptions ........ 304 registers ........................... 301
Index
407
R
Rabbit 2000 ...........................18 Rabbit 3000 ...........................18 Rabbit 4000 revision history ................401 Rabbit 5000 ...........................13 block diagram ....................16 comparison with other Rabbit microprocessors ............18 feature summary ................13 features ..............................14 10/100Base-T Ethernet ..15 EMI mitigation ..............14 input-capture channels ...14 instruction set ................14 memory access ..............14 onchip-encryption RAM 15 parallel ports ..................14 protected operating systems 15 PWM outputs .................15 Quadrature-Decoder channels ..............................14 timers .............................14 specifications .....................17 Rabbit Semiconductor history ................................13 registers alphabetic listing A0CR ...........................224 A0ILR ..........................223 A0IMR .........................223 A0QLR ........................223 A0QMR .......................223 A1CR ...........................225 A1ILR ..........................224 A1IMR .........................225 A1QLR ........................224 A1QMR .......................225 A2CR ...........................227 A2LR ...........................226 A2MR ..........................226 ACSxCR ........................75 AUER ..........................365 BDCR ..........................336 BxA0R .........................337 BxA1R .........................337 BxA2R .........................337 BxCR ...........................336 BxM0R ........................338 BxM1R ........................338 BxM2R ........................338 DATASEG ....................71 DATASEGH .................71
408
DATASEGL ..................71 DMALR .......................243 DMCR .........................244 DMCSR .......................243 DMHR .........................243 DMR0CR .....120, 137, 246 DMR1CR .....121, 138, 247 DMTCR .......................245 DTRCR ........................248 DTRDHR .....................248 DTRDLR .....................248 DyBCR ........................244 DyBU0R ......................249 DyBU1R ......................250 DyCR ...........................252 DyDA0R ......................255 DyDA1R ......................255 DyDA2R ......................255 DyIA0R .......................250 DyIA1R .......................250 DyIA2R .......................250 DyL0R .........................253 DyLA0R ......................256 DyLA1R ......................256 DyLA2R ......................256 DyLnR .........................253 DySA0R ......................254 DySA1R ......................254 DySA2R ......................254 DySCR .........................251 DyTBR ........................249 DyTMR .......................249 EDMR .........................367 ENPR ...........................279 GCDR ....................34, 350 GCM0R .........................33 GCM1R .........................33 GCPU ............................54 GCSR ......32, 51, 156, 162, 170, 348 GOCR ......................35, 54 GPSCR ........................349 GRAM ...........................53 GREV ............................54 GROM ...........................53 IBUER .........................364 IbxCR ..........................323 ICCR ............................294 ICCSR .........................293 ICLxR ..........................296 ICMxR .........................297 ICSxR ..103, 117, 134, 296 ICTxR ..........................295 ICUER .........................363
IHCR ...................140, 321 IHSR ....................141, 322 IHTR ....................141, 322 IUER ............................365 IxCR ..............88, 119, 136 MACR ...................74, 148 MBxCR .........................72 MECR ............................73 MMIDR .........................70 MTCR ............................73 NBCF0R ......................273 NBCF1R ......................273 NBCF2R ......................274 NBCF3R ......................274 NBCR ..........................269 NBCSR ........................268 NBCWR ......................275 NBDMR ......................272 NBDR ..........................267 NBDRR .......................272 NBDTR .......................272 NBFLLR ......................276 NBFLMR .....................276 NBG0R ........................275 NBG1R ........................275 NBG2R ........................275 NBLDR .......................267 NBMCFR ....................276 NBMCR .......................277 NBMFxR .....................271 NBMPAR ....................277 NBMRAR ....................277 NBMRLR ....................277 NBMRMR ...................278 NBMRR .......................276 NBMSR .......................278 NBMWLR ...................277 NBMWMR ..................277 NBPAxR ......................271 NBRCR .......................270 NBRMR .......................275 NBSAxR ......................278 NBTCR ........................270 NBTESR ......................271 NBTPLR ......................269 NBTPMR .............269, 270 NBTSR ........................267 PADR ............................91 PAUER ........................362 PBDDR ..........................95 PBDR .............................95 PBUER ........................362 PCAHR ................101, 326 PCALR ................100, 325
PCDCR ....................... 101 PCDDR ....................... 100 PCDR .......................... 100 PCFR ................... 101, 326 PCUER ........................ 363 PDAHR ............... 112, 328 PDALR ............... 111, 327 PDB0R ........................ 113 PDB1R ........................ 113 PDB2R ........................ 114 PDB3R ........................ 114 PDB4R ........................ 114 PDB5R ........................ 114 PDB6R ........................ 115 PDB7R ........................ 115 PDCR .......................... 112 PDDCR ....................... 113 PDDDR ....................... 113 PDDR .......................... 111 PDFR ................... 113, 328 PDUER ....................... 363 PEAHR ............... 129, 330 PEALR ................ 128, 329 PEB0R ......................... 130 PEB1R ......................... 130 PEB2R ......................... 131 PEB3R ......................... 131 PEB4R ......................... 131 PEB5R ......................... 131 PEB6R ......................... 132 PEB7R ......................... 132 PECR ........................... 129 PEDCR ........................ 130 PEDDR ....................... 130 PEDR .......................... 128 PEFR ................... 130, 330 PEUER ........................ 363 PHAHR ....................... 147 PHALR ....................... 146 PHDCR ....................... 147 PHDDR ....................... 148 PHDR .......................... 146 PHFR ........................... 147 PHUER ....................... 362 PWBAR ...................... 313 PWBPR ....................... 313 PWL0R ....................... 312 PWL1R ....................... 312 PWLxR ....................... 313 PWMxR ...................... 313 PWUER ....................... 364 QDCR ......... 118, 135, 305 QDCSR ....................... 304 QDCxHR ..................... 305
QDCxR ....................... 305 QDUER ....................... 364 RAMSR ......................... 75 RTCCR ......................... 52 RTCxR .......................... 52 RTUER ....................... 362 SAUER ....................... 366 SBUER ........................ 366 SCUER ........................ 366 SDUER ....................... 366 SEGSIZ ......................... 72 SEUER ........................ 367 SFUER ........................ 367 SPCR 44, 91, 96, 139, 213, 324 SPDxR ......................... 212 SPSR ........................... 212 SPUER ........................ 362 STACKSEG .................. 70 STACKSEGH ............... 71 STACKSEGL ............... 71 STKCR .......................... 79 STKHLR ....................... 80 STKLLR ....................... 79 SWDTR ......................... 53 SxAR ................... 180, 197 SxCR ... 102, 133, 183, 200 SxCr ............................ 116 SxDHR ................ 186, 202 SxDLR ................ 185, 202 SxDR ................... 180, 197 SxER (asynch mode) .. 184, 201 SxER (clocked serial mode) 185 SxER (HDLC mode) ... 202 SxLR ................... 180, 197 SxSR (asynch mode) .. 181, 198 SxSR (clocked serial mode) 182 SxSR (HDLC mode) ... 199 TACR .......................... 155 TACSR ........................ 154 TAPR .......................... 154 TATxR ........................ 155 TAUER ....................... 365 TBCLR ........................ 162 TBCMR ....................... 161 TBCR .......................... 160 TBCSR ........................ 160 TBLxR ........................ 161 TBMxR ....................... 161 TBSLxR ...................... 161
TBSMxR ..................... 161 TBUER ....................... 365 TCBAR ....................... 169 TCBPR ........................ 170 TCCR .......................... 168 TCCSR ........................ 168 TCDHR ....................... 168 TCDLR ....................... 168 TCRxHR ..................... 169 TCRxLR ...................... 169 TCSxHR ...................... 169 TCSxLR ...................... 169 TCUER ....................... 366 VRAM00VRAM1F .... 55 WDTCR ........................ 52 WDTTR ........................ 53 WPCR ........................... 76 WPSxHR ....................... 79 WPSxLR ....................... 78 WPSxR .......................... 78 WPxR ............................ 77 analog components ......... 219 bootstrap ........................... 38 breakpoints ...................... 333 Breakpoint x Address 0 Register .................... 337 Breakpoint x Address 1 Register .................... 337 Breakpoint x Address 2 Register .................... 337 Breakpoint x Control Register ............................. 336 Breakpoint x Mask 0 Register ............................. 338 Breakpoint x Mask 1 Register ............................. 338 Breakpoint x Mask 2 Register ............................. 338 Breakpoint/Debug Control Register .................... 336 clocks ................................ 22 Global Clock Double Register ............................... 34 Global Clock Modulator 0 Register ...................... 33 Global Clock Modulator 1 Register ...................... 33 Global Control/Status Register ............................. 32 Global Output Control Register ............................. 35 DMA channels ................ 233 DMA Master Auto-Load Register .................... 243
Index
409
DMA Master Control Register ...........................244 DMA Master Control/Status Register .....................243 DMA Master Halt Register 243 DMA Master Request 0 Control Register .......120, 137, 246 DMA Master Request 1 Control Register .......121, 138, 247 DMA Master Timing Control Register ..............245 DMA Timed Request Control Register ..............248 DMA Timed Request Divider High Register ...248 DMA Timed Request Divider Low Register ...248 DMA y Buffer Complete Register .....................244 DMA y Buffer Unused[15:8] Register ...250 DMA y Buffer Unused[7:0] Register .....................249 DMA y Control Register ... 252 DMA y Destination Addr[15:8] Register .......255 DMA y Destination Addr[23:16] Register .....255 DMA y Destination Addr[7:0] Register .........255 DMA y Initial Addr[15:8] Register .....................250 DMA y Initial Addr[23:16] Register .....................250 DMA y Initial Addr[7:0] Register .....................250 DMA y Length[15:8] Register ..............................253 DMA y Length[7:0] Register ..............................253 DMA y Link Addr[15:8] Register .....................256 DMA y Link Addr[23:16] Register .....................256 DMA y Link Addr[7:0] Register .....................256 DMA y Source Addr[15:8] Register .....................254 DMA y Source Addr[23:16] Register .....................254
DMA y Source Addr[7:0] Register .....................254 DMA y Special Control Register .....................251 DMA y Termination Byte Register .....................249 DMA y Termination Mask Register .....................249 external I/O control .........318 I/O Bank x Control Register 323 I/O Handshake Control Register .............140, 321 I/O Handshake Select Register ...................141, 322 I/O Handshake Timeout Register .............141, 322 Parallel Port C Alternate High Register ............326 Parallel Port C Alternate Low Register ............325 Parallel Port C Function Register .....................326 Parallel Port D Alternate High Register ............328 Parallel Port D Alternate Low Register ............327 Parallel Port D Function Register .....................328 Parallel Port E Alternate High Register ............330 Parallel Port E Alternate Low Register ............329 Parallel Port E Function Register .....................330 Slave Port Control Register 324 external interrupts ..............86 Interrupt x Control Register 88, 119, 136 input capture channels .....289 Input Capture Control Register ...........................294 Input Capture Control/Status Register ...............293 Input Capture LSB x Register ..............................296 Input Capture MSB x Register ..............................297 Input Capture Source x Register ...103, 117, 134, 296 Input Capture Trigger x Register .....................295 low-power operation .......340
Global Clock Double Register ..............................350 Global Control/Status Register ...........................348 Global Power Save Control Register .....................349 memory management ..61, 63 Advanced Chip Select x Control Register ..........75 Data Segment High Register 71 Data Segment Low Register 71 Data Segment Register ..71 Memory Alternate Control Register ...............74, 148 Memory Bank x Control Register .......................72 Memory Timing Control Register .......................73 MMU Expanded Code Register .............................73 MMU Instruction/Data Register .......................70 RAM Segment Register .75 Segment Size Register ...72 Stack High Limit Register . 80 Stack Limit Control Register ................................79 Stack Low Limit Register .. 79 Stack Segment High Register ................................71 Stack Segment Low Register ................................71 Stack Segment Register .70 Write Protect Segment x High Register ..............79 Write Protect Segment x Low Register ..............78 Write Protect Segment x Register .......................78 Write Protect x Register 77 Write Protection Control Register .......................76 Network Port B ...............260 Enable Network Port Register ..............................279 Network Port B Collision Window Register ......275 Network Port B Command Register .....................269 Network Port B Configura-
410
tion 0 Register .......... 273 Network Port B Configuration 1 Register .......... 273 Network Port B Configuration 2 Register .......... 274 Network Port B Configuration 3 Register .......... 274 Network Port B Control/ Status Register .......... 268 Network Port B Data Register .............................. 267 Network Port B Direct MII Register .................... 272 Network Port B Direct Rx Register .................... 272 Network Port B Direct Tx Register .................... 272 Network Port B Frame Limit LSB Register ......... 276 Network Port B Frame Limit MSB Register ........ 276 Network Port B Gap 0 Register ........................... 275 Network Port B Gap 1 Register ........................... 275 Network Port B Gap 2 Register ........................... 275 Network Port B Last Data Register .................... 267 Network Port B MII Command Register ........... 277 Network Port B MII Configuration Register ........ 276 Network Port B MII PHY Address Register ...... 277 Network Port B MII Read LSB Register ............ 277 Network Port B MII Read MSB Register ........... 278 Network Port B MII Register Address Register . 277 Network Port B MII Reset Register .................... 276 Network Port B MII Status Register .................... 278 Network Port B MII Write LSB Register ............ 277 Network Port B MII Write MSB Register ........... 277 Network Port B Multicast Filter x Register ........ 271 Network Port B Physical Address x Register ... 271 Network Port B Receive
Control Register ....... 270 Network Port B Retransmit Max Register ............ 275 Network Port B Station Address x Register ........ 278 Network Port B Transmit Control Register ....... 270 Network Port B Transmit Extra Status Register 271 Network Port B Transmit Pause LSB Register .. 269 Network Port B Transmit Pause MSB Register 269, 270 Network Port B Transmit Status Register .......... 267 Network Port C ............... 283 Parallel Port A ................... 89 Parallel Port A Data Register ............................... 91 Slave Port Control Register 91 Parallel Port B ................... 94 Parallel Port B Data Direction Register ............... 95 Parallel Port B Data Register ............................... 95 Slave Port Control Register 96 Parallel Port C ................... 98 Parallel Port C Alternate High Register ........... 101 Parallel Port C Alternate Low Register ............ 100 Parallel Port C Data Direction Register ............. 100 Parallel Port C Data Register ............................. 100 Parallel Port C Drive Control Register .............. 101 Parallel Port C Function Register .................... 101 Parallel Port D ................. 108 Parallel Port D Alternate High Register ........... 112 Parallel Port D Alternate Low Register ............ 111 Parallel Port D Bit 0 Register ............................. 113 Parallel Port D Bit 1 Register ............................. 113 Parallel Port D Bit 2 Register ............................. 114 Parallel Port D Bit 3 Regis-
ter ............................. 114 Parallel Port D Bit 4 Register ............................. 114 Parallel Port D Bit 5 Register ............................. 114 Parallel Port D Bit 6 Register ............................. 115 Parallel Port D Bit 7 Register ............................. 115 Parallel Port D Control Register ........................... 112 Parallel Port D Data Direction Register ............. 113 Parallel Port D Data Register ............................. 111 Parallel Port D Drive Control Register .............. 113 Parallel Port D Function Register .................... 113 Parallel Port E ................. 126 Parallel Port E Alternate High Register ........... 129 Parallel Port E Alternate Low Register ............ 128 Parallel Port E Bit 0 Register ............................. 130 Parallel Port E Bit 1 Register ............................. 130 Parallel Port E Bit 2 Register ............................. 131 Parallel Port E Bit 3 Register ............................. 131 Parallel Port E Bit 4 Register ............................. 131 Parallel Port E Bit 5 Register ............................. 131 Parallel Port E Bit 6 Register ............................. 132 Parallel Port E Bit 7 Register ............................. 132 Parallel Port E Control Register ........................... 129 Parallel Port E Data Direction Register ............. 130 Parallel Port E Data Register ............................. 128 Parallel Port E Drive Control Register .............. 130 Parallel Port E Function Register .................... 130 Parallel Port H ................. 144 Parallel Port D Alternate Low Register ............ 146 Parallel Port H Alternate
Index
411
High Register ............147 Parallel Port H Data Direction Register ..............148 Parallel Port H Data Register ..............................146 Parallel Port H Drive Control Register ..............147 Parallel Port H Function Register .....................147 PWM ...............................309 PWM Block Access Register ..............................313 PWM Block Pointer Register ..............................313 PWM LSB 0 Register ..312 PWM LSB 1 Register ..312 PWM LSB x Register ..313 PWM MSB x Register .313 Quadrature Decoder ........301 Quad Decode Control Register ...................118, 305 Quad Decode Control/Status Register ...............304 Quad Decode Count High Register .....................305 Quad Decode Count Register ..............................305 quadrature Decoder Quad Decode Control Register ...........................135 reset ...................................38 reset/bootstrap Slave Port Control Register 44 Serial Ports A D ............174 Serial Port x Address Register ..............................180 Serial Port x Control Register ......102, 116, 133, 183 Serial Port x Data Register 180 Serial Port x Divider High Register .....................186 Serial Port x Divider Low Register .....................185 Serial Port x Extended Register (asynch mode) ...184 Serial Port x Extended Register (clocked serial mode) 185 Serial Port x Long Stop Register .....................180 Serial Port x Status Register (asynch mode) ..........181
Serial Port x Status Register (clocked serial mode) 182 Serial Ports E F .............189 Serial Port x Address Register ..............................197 Serial Port x Control Register ..............................200 Serial Port x Data Register 197 Serial Port x Divider High Register .....................202 Serial Port x Divider Low Register .....................202 Serial Port x Extended Register (asynch mode) ...201 Serial Port x Extended Register (HDLC mode) ...202 Serial Port x Long Stop Register .....................197 Serial Port x Status Register (asynch mode) ..........198 Serial Port x Status Register (HDLC mode) ...........199 slave port .........................204 Slave Port Control Register 139, 213 Slave Port Data x Registers 212 Slave Port Status Register . 212 system management ..........47 Battery-Backed Onchip-Encryption RAM .............55 Global Control/Status Register .............................51 Global CPU Register .....54 Global Output Control Register .............................54 Global RAM Configuration Register .......................53 Global Revision Register ... 54 Global ROM Configuration Register .......................53 Real-Time Clock Control Register .......................52 Real-Time Clock x Register 52 Secondary Watchdog Timer Register .......................53 Watchdog Timer Control Register .......................52 Watchdog Timer Test Register .............................53
System/User mode ..........352 Analog User Enable Register ..............................365 Enable Dual-Mode Register 367 External Interrupt User Enable Register .............365 I/O Bank User Enable Register ...........................364 Input Capture User Enable Register .....................363 Parallel Port A User Enable Register .....................362 Parallel Port B User Enable Register .....................362 Parallel Port C User Enable Register .....................363 Parallel Port D User Enable Register .....................363 Parallel Port E User Enable Register .....................363 Parallel Port H User Enable Register .....................362 PWM User Enable Register 364 Quad Decode User Enable Register .....................364 Real-Time Clock User Enable Register .............362 Serial Port A User Enable Register .....................366 Serial Port B User Enable Register .....................366 Serial Port C User Enable Register .....................366 Serial Port D User Enable Register .....................366 Serial Port E User Enable Register .....................367 Serial Port F User Enable Register .....................367 Slave Port User Enable Register ...........................362 Timer A User Enable Register ..............................365 Timer B User Enable Register ..............................365 Timer C User Enable Register ..............................366 Timer A ...........................152 Global Control/Status Register ...........................156 Timer A Control Register .. 155
412
Timer A Control/Status Register .................... 154 Timer A Prescale Register 154 Timer A Time Constant x Register .................... 155 Timer B ........................... 158 Global Control/Status Register ........................... 162 Timer B Control Register .. 160 Timer B Control/Status Register .................... 160 Timer B Count LSB Register .............................. 162 Timer B Count LSB x Register ........................... 161 Timer B Count MSB Register .............................. 161 Timer B Count MSB x Register ........................... 161 Timer B Step LSB x Register .............................. 161 Timer B Step MSB x Register .............................. 161 Timer C ........................... 165 Global Control/Status Register ........................... 170 Timer C Block Access Register ........................... 169 Timer C Block Pointer Register ........................... 170 Timer C Control Register .. 168 Timer C Control/Status Register .................... 168 Timer C Divider High Register ........................... 168 Timer C Divider Low Register ........................... 168 Timer C Reset x High Register ........................... 169 Timer C Reset x Low Register .............................. 169 Timer C Set x High Register 169 Timer C Set x Low Register 169 reset ....................................... 37 block diagram ................... 38 dependencies ..................... 39 operation ........................... 40 register descriptions .......... 44 registers ............................. 38
SMODE pin settings ......... 41 revision history ................... 401
S
serial ports clock synchronization and data encoding ..................... 193 Serial Ports A D ........... 171 block diagram .............. 173 clocks .......................... 175 data clocks ................... 172 dependencies ............... 175 interrupts ..................... 176 operation ..................... 177 asynchronous mode . 177 clocked serial mode 172, 178 overview ...................... 171 pin use ......................... 175 register descriptions .... 180 registers ....................... 174 SPI clock modes .......... 171 SxSR ........................... 171 use of clocked Serial Port C 175 use of clocked Serial Port D 175 Serial Ports E F ............ 187 asynchronous mode ..... 187 block diagram .............. 188 clocks .......................... 190 dependencies ............... 190 HDLC data encoding .. 194 HDLC mode ................ 187 DPLL counter .......... 194 interrupts ..................... 191 operation ..................... 192 asynchronous mode . 192 HDLC mode ............ 192 overview ...................... 187 pin use ......................... 190 register descriptions .... 197 registers ....................... 189 SxSR ........................... 187 slave port ....................... 93, 203 addresses ......................... 203 block diagram ................. 204 bootstrap processor ......... 204 clocks .............................. 205 dependencies ................... 205 interrupts ......... 203, 205, 208 example ISR ................ 208 operation ......................... 206 configurations ............. 209
connections ................. 207 master .......................... 207 master/slave communication ........................... 208 slave ............................ 207 slave/master communication ........................... 208 overview ......................... 203 pin use ............................. 205 R/W timing ..................... 210 register descriptions ........ 212 registers ........................... 204 slave attention ................. 203 timing diagrams .............. 210 sleepy clock modes ............... 31 SMODE pin settings ............. 41 SPCR Parallel Port A setup ......... 89 specifications ................ 17, 369 AC characteristics ........... 371 analog components ......... 216 BGA package .................. 389 dimensions .................. 391 land pattern .................. 391 pinout .................. 389, 390 clock speeds .................... 381 recommended clock/memory configurations ...... 381 DC characteristics ........... 369 memory access times 372, 378 external I/O reads ........ 375 external I/O writes ....... 375 memory reads .............. 372 memory writes ............ 372 package ........................... 389 power and current consumption .............................. 385 battery-backed clock ... 387 sleep modes ................. 386 spectrum spreader ........... 21, 25 stack protection ..................... 69 system management .............. 45 block diagram ................... 46 clocks ................................ 48 dependencies ..................... 48 interrupts ........................... 48 onchip-encryption RAM ... 45 operation periodic interrupt ........... 49 real-time clock .............. 49 watchdog timer .............. 50 other registers .................... 45 GCPU register ............... 45 GOCR register .............. 45
Index
413
GREV register ...............45 periodic interrupt ...............45 real-time clock ...................45 register descriptions ...........51 registers .............................47 watchdog timers ................45 System/User mode ..............351 dependencies ...................353 differences between System mode and User mode ..351 inaccessible addresses in User mode ............................353 interrupts ..................354, 360 opcodes ............................358 operation ..........................355 complete operating system 356 enabling .......................357 memory protection ......355 mixed operation ...........356 overview ..........................351 register descriptions .........362 registers ...........................352 use memory protection ......355
clocks ...........................166 dependencies ...............166 DMA control ...............163 interrupts ..............166, 167 example ISR ............167 operation ......................167 overview ......................163 register descriptions .....168 registers .......................165 timing diagrams I/O R/W cycles ................376 memory R/W cycles ........373 memory R/W cycles (early output enable and write enable) ............................374 slave port R/W cycles .....210, 211
W
watchdog timer primary watchdog timer ....50 primary/secondary watchdog timer bug .......................50 secondary watchdog timer .50 settings ...............................50
T
timers Timer A ...........................149 block diagram ..............151 capabilities ...................150 clocks ...........................152 dependencies ...............152 interrupts ..............150, 153 example ISR ............153 operation ......................153 overview ......................149 register descriptions .....154 registers .......................152 reload register operation .... 149 Timer B ...........................157 block diagram ..............157 clocks ...........................158 dependencies ...............158 interrupts ..............158, 159 example ISR ............159 operation ......................159 overview ......................157 PWM operation ...........157 register descriptions .....160 registers .......................158 Timer C ...........................163 block diagram ..............164

Rabbit® 5000 Microprocessor: User's Manual

Uploaded by

Copyright:

Available Formats

Rabbit® 5000 Microprocessor: User's Manual

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Rabbit® 5000 Microprocessor: User's Manual

Uploaded by

Copyright:

Available Formats

Rabbit 5000 Microprocessor

Rabbit 5000 Microprocessor Users Manual

The latest revision of this manual is available at www.rabbit.com.

Chapter 1. The Rabbit 5000 Processor

Chapter 3. Reset and Bootstrap

Chapter 4. System Management

Chapter 5. Memory Management

Chapter 7. External Interrupts

Chapter 8. Parallel Port A

Rabbit 5000 Microprocessor Users Manual

Chapter 9. Parallel Port B

Chapter 10. Parallel Port C

Chapter 11. Parallel Port D

Chapter 12. Parallel Port E

Chapter 13. Parallel Port H

13.4 Register Descriptions ..................................................................................................................... 146

Chapter 14. Timer A

Chapter 15. Timer B

Chapter 16. Timer C

Chapter 17. Serial Ports A D

Rabbit 5000 Microprocessor Users Manual

17.4 Register Descriptions ......................................................................................................................180

Chapter 18. Serial Ports E F

Chapter 19. Slave Port

Chapter 20. Analog Components

Chapter 21. DMA Channels

Chapter 22. 10/100Base-T Ethernet

Chapter 23. 802.11b/g Wireless

Chapter 24. Input Capture

24.3.5 Count Mode ............................................................................................................................292 24.4 Register Descriptions ......................................................................................................................293

Chapter 25. Quadrature Decoder

Chapter 26. Pulse Width Modulator

Chapter 27. External I/O Control

Chapter 28. Breakpoints

Chapter 29. Low-Power Operation

Chapter 30. System/User Mode

Chapter 31. Specifications

Chapter 32. Package Specifications and Pinout

Appendix A. Parallel Port Pins with Alternate Functions

Rabbit 5000 Microprocessor Users Manual

Appendix B. Rabbit 5000 Errata

B.1 Errata ................................................................................................................................................401

Rabbit 5000 Microprocessor Users Manual

1. THE RABBIT 5000 PROCESSOR

Chapter 1 The Rabbit 5000 Processor

1.3 Block Diagram

D[7:0] (8-bit mode) or D[15:0] (16-bit mode)

Address Buffer Spectrum Spreader

Memory Management/ Control Clock Doubler

/CS2, /CS1, /CS0 /OE1, /OE0 /WE1, /WE0

Global Power Save & Clock Distribution

PA [7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PH[7:0]

Timer C Timer A VBAT RAM

Port H Serial Port A

TXA, RXA, CLKA, ATXA, ARXA

32.768 kHz Clock Input

Serial Ports B,C,D

Watchdog Timer Secondary Watchdog Periodic Interrupt

Asynch Serial IrDA