Austin Datasheet

VRAM
SM55161A
Production
Austin Semiconductor, Inc.

262144 x 16 BIT VRAM
PIN ASSIGNMENT
MULTIPORT VIDEO RAM
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
64-Pin Ceramic Flatpack (HKC)
Military Processing Flow(SM Level)

-55C to 125C temperature
FEATURES
Organization:
DRAM: 262 144 by 16 Bits
SAM: 512 by 16 Bits
Dual-Port Accessibility Simultaneous and Asynchronous
Access From the DRAM and SAM Ports
Bidirectional Data-Transfer Function From the DRAM to
the Serial-Data Register, and from Serial Data Register to DRAM
(8 x 8) x 2 Block Write feature for fast area fill
Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
Byte-Write Control (CASL, CASU) Provides Flexibility
Extended Data Output for Faster System Cycle Time
Enhanced Page-Mode Operation for Faster Access
CAS-Before-RAS (CBR) and Hidden-Refresh Modes
Long Refresh Period: Every 8 ms (Maximum)
Up to 50-MHz Uninterrupted Serial-Data Streams
512 Selectable Serial-Register Starting Locations
SE-Controlled Register-Status QSF
Split-Register-Transfer Read for Simplified Real-Time Register
Load
Programmable Split-Register Stop Point
3-State Serial Outputs Allow Easy Multiplexing of Video-Data
Streams
Pin-out Compatible upgrade from SM55161
Compatible With JEDEC Standards
PIN DESCRIPTIONS
PIN
A0-A8
CASL\, CASU\
DQ0-DQ15
DSF
NC/GND
OPTIONS
Timing
70ns access
75ns access
80ns access
Package
68 pin PGA
64 pin Flatpack
Operating Temperature Ranges
- Military (-55oC to +125oC)
- Industrial (-40oC to +85oC)
SMJ55161A
Rev. 1.6 03/05
MARKING
-70
-75
-80
GB
HKC
DESCRIPTION
Address inputs
Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Special Function Select
Special-Function Select
No Connect/Ground (NOTE: Not
connected internally to VSS)
QSF
RAS\
SC
SE\
SQ0-SQ15
TRG\
Special-Function Output
Row-Address Strobe
Serial Clock
Serial Enable
Serial-Data Output
Output Enable, Transfer Select
VCC
5V Supply (TYP)
VSS
Ground
WE\
DRAM Write-Enable Select
For more products and information

please visit our web site at
www.austinsemiconductor.com
M suffix
I suffix
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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PERFORMANCE RANGES
-70
MAX
-75
MAX
-80
MAX
DESCRIPTION
SYM
Access Time Row Enable
ta(R)
70
75
80
ns
Access Time Serial Data
ta(SQ)
20
23
25
ns
DRAM Cycle Time
tc(W)
130
140
150
ns
DRAM Page Mode
tc(P)
45
48
50
ns
Serial Cycle Time
tc(SC)
22
24
30
ns
Operating Current,
Serial Port Stand-by
Operating Current,
Serial Port Active
MIN
MIN
MIN
UNITS
ICC1
165
165
210
mA
ICC1A
210
210
195
mA
GB PACKAGE (Bottom View) & PIN ASSIGNMENTS
SMJ55161A
Rev. 1.6 03/05
PIN No.
NAME
PIN No.
NAME
J1
J2
J3
DQ1
SQ3
DQ3
E8
E9
D1
VSS1
J4
DQ4
D2
VSS1
J5
DQ5
D3
VDD1
J6
J7
J8
J9
DQ6
SQ7
CASL\
A8
D7
D8
D9
C1
VSS1
A4
SE\
A3
A2
SQ15
H1
DQ0
C2
VSS1
H2
SQ2
C3
VDD2
H3
DQ2
C4
VSS2
H4
SQ4
C6
VDD2
H5
H6
H7
H8
H9
G1
G2
SQ5
SQ6
DQ7
WE\
A7
SQ0
SQ1
C7
C8
C9
B1
B2
B3
B4
CASU\
A1
DQ15
DQ14
DQ13
DQ12
G3
VDD2
B5
DQ11
G4
VSS2
B6
DQ10
G6
VDD2
B7
SQ8
G7
G8
G9
F1
VSS2
RAS\
A6
TRG
B8
B9
A1
A2
DSF
A0
SQ14
SQ13
F2
VSS1
A3
SQ12
F3
VDD1
A4
SQ11
F7
VDD1
A5
SQ10
F8
F9
E1
VDD1
A5
SC
A6
A7
A8
SQ9
DQ9
DQ8
E2
VDD1
A9
QSF
VSS2
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GENERAL DESCRIPTION
The SMJ55161A, a multiport-video random-access memory
(RAM), is a high-speed, dual-port memory device. It consists
of a dynamic RAM (DRAM) module organized as 262 144 words
of 16 bits each interfaced to a serial-data register (serial-access
memory [SAM]) organized as 512 words of 16 bits each. The
SMJ55161A supports three basic types of operation: random
access to and from the DRAM, serial access to/from the serial
register, and transfer of data from any row in the DRAM to the
serial register and vice versa. Except during transfer operations,
the SMJ55161A can be accessed simultaneously and
asynchronously from the DRAM and SAM ports.
The SMJ55161A is equipped with several features designed
to provide higher system-level bandwidth and to simplify design
integration on both the DRAM and SAM ports. On the DRAM
port, greater pixel-draw rates are achieved by the devices
(8 8) 2 block-write feature. The block-write mode allows 16
bits of data (present in an on-chip color-data register) to be
written to any combination of eight adjacent column-address
locations. As many as 128 bits of data can be written to memory
during each CAS\ cycle time. Also, on the DRAM port and
SAM port, a write mask or a write-per-bit feature allows
masking of any combination of the 16 inputs/outputs on any
write cycle. The persistent write-per-bit feature uses a mask
register that, once loaded, can be used on subsequent write
cycles without reloading. The SMJ55161A also offers byte
control which can be applied in read cycles, write cycles, blockwrite cycles, load-write-mask-register cycles, and load-colorregister cycles. The SMJ55161A also offers extended-dataoutput (EDO) mode. The EDO mode is effective in both the
page-mode and standard DRAM cycles.
SMJ55161A
Rev. 1.6 03/05
The SMJ55161A offers a split-register-transfer read

(DRAM-to-SAM) feature for the serial register (SAM port) that
enables real-time-register-load implementation for continuous
serial-data streams without critical timing requirements. The
register is divided into a high half and a low half. While one half
is being read out of the SAM port, the other half can be loaded
from the memory array. For applications not requiring real-time
register load (for example, loads done during CRT-retrace
periods), the full-register mode of operation is retained to
simplify system design.
The SAM port is designed for maximum performance. Data
can be accessed from the SAM at serial rates up to 50 MHz.
During the split-register-transfer read operations, internal
circuitry detects when the last bit position is accessed from the
active half of the register and immediately transfers control to
the opposite half. A separate output, QSF, is included to
indicate which half of the serial register is active.
All inputs, outputs, and clock signals on the SMJ55161 are
compatible with Series 54/74 TTL. All address lines and data-in
lines are latched on-chip to simplify system design. All dataout lines are unlatched to allow greater system flexibility.
The SMJ55161A is offered in a 68-pin ceramic pin-gridarray package (GB suffix) and a 64-pin ceramic flatpack (HKC
suffix).
The SMJ55161A is supported by a broad line of graphic
processors and control devices from Texas Instruments. See
Table 2 and Table 4 for additional information.
Additional features of the 55161A include MASKED
FLASH WRITE which allows for data in color register to be
written into all the memory locations of a selected row.
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FUNCTIONAL BLOCK DIAGRAM
SMJ55161A
Rev. 1.6 03/05
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TABLE 1: DRAM & SAM FUNCTIONS
CASx\
FALL
RAS\ FALL
DQ0-DQ151
ADDRESS
FUNCTION
2
MNE
CASL\
CODE
CASU\
WE\
X
---
CASx\
TRG\
WE\
DSF
DSF
RAS\
CASX\
RAS\
X
Stop
CBR
CBRN
Full-register-transfer read
Row
Address
Tap
Point
RT
Split-register-transfer read
Row
Address
Tap
Point
SRT
DRAM write
(nonpersistent write-per-bit)
Row
Column Write
Address Address Mask
Valid
Data
RWM
DRAM block write

Block
Row
Write Column
Address
BWM
Address
Mask Mask
A3-A8
DRAM write
(persistent write-per-bit)
Row
Column
Address Address
DRAM block write

Block
Row
Address
Address
A3-A8
DRAM write (nonmasked)
Row
Column
Address Address
Valid
Data
RW
DRAM block write (nonmasked)
Block
Row
Address
Address
A3-A8
Column
Mask
BW
Refresh
Address
Write
Mask
LMR
Refresh
Address
Color
Data
LCR
Row
Address
Tap
Point
Write
Mask
MWT
Row
Address
Tap
Point
Write
Mask
MSWT
Row
Address
Write
Mask
---
FWM
Reserved (do not use)

CBR refresh (no reset) and stop4
point set
CBR refresh (option reset)

CBR refresh (no reset)
Load write-mask register
Load color register

Masked Write Transfer
Masked Split Write Transfer
Masked Flash Write Transfer
point
Valid
Data
CBRS
RWM
Column
BWM
Mask
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Dont Care
NOTES:
1. DQ0DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the power-up initialization cycle.
5. A0A3, A8: dont care; A4A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
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TABLE 2: PIN DESCRIPTIONS VS. OPERATIONAL MODE

PIN
A0-A8
CASL\,
CASU\
DQ
DSF
RAS\
DRAM
Row, column address
TRANSFER
Row address, Tap point
Column-address strobe, DQ output enable
Tap-address strobe
DRAM data I/O, write mask

Block-write enable
Write-mask-register load enable
Color-register load enable
CBR (option reset)
Row-address strobe
Split-register-transfer enable
Row-address strobe
SQ output enable,
QSF output enable
Serial clock
Serial-data output
SE\
SC
SQ
TRG\
WE\
QSF
DQ output enable
Write enable, write-pre-bit enable
Special-function output
Either make no external connection or tie to
NC/GND
system GND (VSS)
1
5V supply
Ground
VCC
VSS
SAM
Transfer enable
Serial-register status
NOTES: 1. For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground.
address (A0A8)
row-address strobe (RAS\)
Eighteen address bits are required to decode each one of

the 262 144 storage cell locations. Nine row-address bits are set
up on pins A0A8 and latched onto the chip on the falling edge
of RAS\. Nine column-address bits are set up on pins A0A8
and latched onto the chip on the first falling edge of CASx\. All
addresses must be stable on or before the falling edge of RAS\
and the first falling edge of CASx\.
During the full-register-transfer read operation, the states
of A0A8 are latched on the falling edge of RAS\ to select one
of the 512 rows where the transfer occurs. At the first falling
edge of CASx\, the column-address bits A0A8 are latched.
The most significant column-address bit (A8) selects which
half of the row is transferred to the SAM. The appropriate 8-bit
column address (A0A8) selects one of 512 tap points (starting
positions) for the serial-data output.
During the split-register-transfer read operation, an
internal counter selects which half of the register is used. If the
high half of the SAM is currently in use, the low half of the
SAM is loaded with the low half of the DRAM half row and vice
versa. Column address (A8) selects the DRAM half row. The
remaining eight address bits (A0A7) are used to select one of
256 possible starting locations within the SAM.
RAS\ is similar to a chip enable so that all DRAM cycles

and transfer cycles are initiated by the falling edge of RAS\.
RAS\ is a control input that latches the states of the row
address, WE\, TRG\, CASL\, CASU\, and DSF onto the chip to
invoke DRAM and transfer-read/write functions of the
SMJ55161A.
SMJ55161A
Rev. 1.6 03/05
column-address strobe (CASL, CASU)

CASL\ and CASU\ are control inputs that latch the states
of the column address and DSF to control DRAM and transfer
functions of the SMJ55161A. CASx\ also acts as output enable
for the DRAM output pins DQ0DQ15. In DRAM operation,
CASL\ enables data to be written to or read from the lower byte
(DQ0DQ7), and CASU\ enables data to be written to or from
the upper byte (DQ8DQ15). In transfer operations, address
bits A0A8 are latched at the first falling edge of CASx\ as the
start position (tap) for the serial-data output (SQ0SQ15).
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output enable/transfer select (TRG\)
serial-data outputs (SQ0 SQ15)
TRG\ selects either DRAM or transfer operation as RAS\

falls. For DRAM operation, TRG\ must be held high as RAS\
falls. During DRAM operation, TRG functions as an output
enable for the DRAM output pins DQ0DQ15. For transfer
operation, TRG\ must be brought low before RAS\ falls.
Serial data is read from the SQ pins. The SQ output buffers

provide direct TTL compatibility (no pullup resistors) with a
fanout of one Series 54 TTL load. The serial outputs are in the
high-impedance (floating) state as long as the serial-enable pin,
SE\, is high. The serial outputs are enabled when SE\ is brought
low.
write-mask select, write enable (WE)
serial clock (SC)
In DRAM operation, WE\ enables data to be written to the

DRAM. WE\ is also used to select the DRAM write-per-bit
mode. Holding WE\ low on the falling edge of RAS\ invokes
the write-per-bit operation. The SMJ55161A supports both the
nonpersistent write-per-bit mode and the persistent write-perbit mode.
Serial data is accessed out of the data register during the

rising edge of SC. The SMJ55161A is designed to work with a
wide range of clock duty cycles to simplify system design.
There is no refresh requirement because the data registers that
comprise the SAM are static. There is also no minimum SCclock operating frequency.
special-function select (DSF)
serial enable (SE)
The DSF input is latched on the falling edge of RAS\ or the

first falling edge of CASx\, similar to an address. DSF determines which of the following functions are invoked on a particular cycle:
CBR refresh with reset (CBR)
CBR refresh with no reset (CBRN)
CBR refresh with no reset and stop-point set (CBRS)
Block write
Loading write-mask register for the persistent
write-per-bit mode (LMR)
Loading color register for the block-write mode
Split-register-transfer read
During serial-access operations, SE\ is used as an enable/

disable for the SQ outputs. SE\ low enables the serial-data output while SE\ high disables the serial-data output. SE\ is also
used as an enable/disable for output pin QSF.
IMPORTANT: While SE\ is held high, the serial clock is
not disabled. External SC pulses increment the internal serialaddress counter regardless of the state of SE\. This ungated
serial-clock scheme minimizes access time of serial output from
SE\ low because the serial-clock input buffer and the serialaddress counter are not disabled by SE\.
special-function output (QSF)

QSF is an output pin that indicates which half of the SAM
is being accessed. When QSF is low, the serial-address pointer
is accessing the lower (least significant) 256 bits of the serial
register (SAM). When QSF is high, the pointer is accessing the
higher (most significant) 256 bits of the SAM.
During full-register-transfer operations, QSF can change
state upon completing the cycle. This state is determined by
the tap point loaded during the transfer cycle. QSF is enabled
by SE\; therefore, if SE\ is high, the QSF output is in the highimpedance state.
DRAM data I/O, write mask data (DQ0DQ15)

DRAM data is written or read through the common I/O DQ
pins. The 3-state DQ-output buffers provide direct TTL
compatibility (no pullup resistors) with a fanout of one Series
54 TTL load. Data out is the same polarity as data in. During a
normal access cycle, the outputs remain in the high-impedance
state until TRG\ is brought low. Data appears at the outputs
until TRG\ returns high, CASx\ returns high following RAS\
returning high, or RAS\ returns high following CASx\ returning
high. The write mask is latched into the device through the
random DQ pins by the falling edge of RAS\ and is used on all
write-per-bit cycles. In a transfer operation, the DQ outputs
remain in the high-impedance state for the entire cycle.
SMJ55161A
Rev. 1.6 03/05
no connect / ground (NC/GND)

NC/GND must be tied to system ground or left floating for
proper device operation.
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TABLE 3: DRAM FUNCTIONS
CASx\
FALL
RAS\ FALL
DQ0-DQ151
ADDRESS
FUNCTION
2
MNE
CASL\
CODE
CASU\
WE\
X
---
CASx\
TRG\
WE\
DSF
DSF
RAS\
CASX\
RAS\
X
Stop
CBRS
CBR
CBRN
DRAM write
Row
Column Write
Address Address Mask
Valid
Data
RWM
DRAM block write

Block
Row
Write Column
Address
BWM
Address
Mask Mask
A3-A8
DRAM write
Row
Column
Address Address
DRAM block write

Block
Row
Address
Address
A3-A8
DRAM write (nonmasked)
Row
Column
Address Address
Valid
Data
RW
DRAM block write (nonmasked)
Block
Row
Address
Address
A3-A8
Column
Mask
BW
Refresh
Address
Write
Mask
LMR
Refresh
Address
Color
Data
LCR
Reserved (do not use)

CBR refresh (no reset) and stop4
point set
CBR refresh (option reset)

CBR refresh (no reset)
Load write-mask register

Load color register
point
Valid
Data
RWM
Column
BWM
Mask
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Dont Care
NOTES:
1. DQ0DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the powerup initialization cycle.
5. A0A3, A8: dont care; A4A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
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need to be refreshed consecutively as long as the entire refresh

is completed within the required time period, trf(MA). The
output buffers remain in the high-impedance state during the
CBR refresh cycles regardless of the state of TRG\.
enhanced page mode

Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting random column addresses. This mode eliminates the time required
for row-address setup, row-address hold, and address multiplex. The maximum RAS\ low time and CAS\ page cycle time
used determine the number of columns that can be accessed.
Unlike conventional page-mode operations, the enhanced
page mode allows the SMJ55161A to operate at a higher data
bandwidth. Data retrieval begins as soon as the column
address is valid rather than when CASx\ transitions low. A
valid column address can be presented immediately after the
row-address hold time has been satisfied, usually well in
advance of the falling edge of CASx\. In this case, data is
obtained after ta(C) MAX (access time from CASx\ low) if ta(CA)
MAX (access time from column address) has been satisfied.
hidden refresh
A hidden refresh is accomplished by holding both CASL\
and CASU\ low in the DRAM read cycle and cycling RAS\. The
output data of the DRAM read cycle remains valid while the
refresh is carried out. Like the CBR refresh, the refreshed row
addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS\-only refresh is accomplished by cycling RAS\ at
every row address. Unless CASx\ and TRG\ are low, the output
buffers remain in the high-impedance state to conserve power.
Externally-generated addresses must be supplied during RAS\only refresh. Strobing each of the 512 row addresses with RAS\
causes all bits in each row to be refreshed.
REFRESH
CAS-before-RAS (CBR) refresh
extended data output
CBR refreshes are accomplished by bringing either or both

CASL\ and CASU\ low earlier than RAS\. The external row
address is ignored, and the refresh row address is generated
internally. Three types of CBR refresh cycles are available. The
CBR refresh (option reset) ends the persistent write-per-bit mode
and the stop-point mode. The CBRN and CBRS refreshes (no
reset) do not end the persistent write-per-bit mode or the stoppoint mode. The 512 rows of the DRAM do not necessarily
The SMJ55161A features EDO during DRAM accesses. While

RAS\ and TRG\ are low, the DRAM output remains valid. The
output remains valid even when CASx\ returns high until WE\
is low, TRG\ is high, or both CASx\ and RAS\ are high (see
Figure 1 and Figure 2). The EDO mode functions during all read
cycles including DRAM read, page-mode read, and readmodify-write cycles (see Figure 3).
FIGURE 1: DRAM Read Cycle With RAS\-Controlled Output
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FIGURE 2: DRAM Read Cycle With CASx\-Controlled Output
FIGURE 3: DRAM Page-Read Cycle with Extended Output
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byte operation
Byte operation can be applied in DRAM-read cycles, write
cycles, block-write cycles, load-write-mask-register cycles, and
load-color-register cycles. In byte operation, the column
address (A0A8) is latched at the first falling edge of CASx\. In
read cycles, CASL\ enables the lower byte (DQ0DQ7) and
CASU\ enables the upper byte (DQ8DQ15) (see Figure 4).
In byte-write operation, CASL enables data to be written
to the lower byte (DQ0DQ7), and CASU\ enables data to be
written to the upper byte (DQ8DQ15). In an early write cycle,

WE is brought low prior to both CASx\ signals, and data setup
and hold times for DQ0 DQ15 are referenced to the first falling
edge of CASx\ (see Figure 5).
For late-write or read-modify-write cycles, WE\ is brought
low after either or both CASL\ and CASU\ fall. The data is
strobed in with data setup and hold times for DQ0 DQ15
referenced to WE\ (see Figure 6).
FIGURE 4: Example of a Byte-Read Cycle
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FIGURE 5: Example of an Early-Write Cycle
FIGURE 6: Example of a Late-Write Cycle
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write-per-bit
The write-per-bit feature allows masking any combination of
the 16 DQs on any write cycle. The write-per-bit operation is
invoked when WE\ is held low on the falling edge of RAS\. If
WE\ is held high on the falling edge of RAS\, the write operation is performed without any masking. The SMJ55161A offers
two write-per-bit modes: nonpersistent write-per-bit and persistent write-per-bit.
nonpersistent write-per-bit
When WE\ is low on the falling edge of RAS\, the write mask is
reloaded. A 16-bit binary code (the write-per-bit mask) is input
to the device through the DQ pins and latched on the falling
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edge of RAS\. The write-per-bit mask selects which of the 16

I/Os are to be written and which are not. After RAS\ has latched
the on-chip write-per-bit mask, input data is driven onto the DQ
pins and is latched on either the first falling edge of CASx\ or
the falling edge of WE\, whichever occurs later. CASL\ enables
the lower byte (DQ0DQ7) to be written through the mask and
CASU\ enables the upper byte (DQ8DQ15) to be written
through the mask. If a data low (write mask = 0) is strobed into
a particular I/O pin on the falling edge of RAS\, data is not
written to that I/O. If a data high (write mask = 1) is strobed into
a particular I/O pin on the falling edge of RAS\, data is written
to that I/O (see Figure 7).
FIGURE 7: Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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persistent write-per-bit
The persistent write-per-bit mode is initiated by
performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is
overwritten but remains valid over an arbitrary number of write
cycles until another LMR cycle is performed or power is
removed.
The LMR cycle is performed using DRAM write-cycle
timing with DSF held high on the falling edge of RAS\ and held
low on the first falling edge of CASx\. A binary code is input to
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the write-mask register via the random I/O pins and latched on
either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later. Byte write control can be applied to the
write mask during the LMR cycle. The persistent write-per-bit
mode can then be used in exactly the same way as the
nonpersistent write-per-bit mode except that the input data on
the falling edge of RAS\ is ignored. When the device is set to
the persistent write-per-bit mode, it remains in this mode and is
reset only by a CBR refresh (option-reset) cycle (see Figure 8).
FIGURE 8: Example of a Persistent Write-Per-Bit Operation
SMJ55161A
Rev. 1.6 03/05
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VRAM
block write
The block-write feature allows up to 128 bits of data to be
written simultaneously to one row of the memory array. This
function is implemented as eight columns by eight DQs and
repeated in two halves. In this manner, each of the two 2M-bit
halves can have up to eight consecutive columns written at a
time with up to eight DQs per column (see Figure 9).
Each 2M-bit half has a 8-bit column mask to mask off and
prevent any or all of the eight columns from being written with
SM55161A
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data. Nonpersistent write-per-bit or persistent write-per-bit

functions can be applied to the block-write operation to
provide write-masking options. The DQ data is provided by 8
bits from the on-chip color register. Bits 07 from the 16-bit
write-mask register, bits 0 7 from the 16-bit column-mask
register, and bits 0 7 from the 16-bit color-data register
configure the block write for the first half, while bits 8 - 15 of the
corresponding register control the other half in a similar
fashion (see Figure 10).
FIGURE 9: Block-Write Operation
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FIGURE 10: Block-Write With Masks
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block write (continued)
A set of eight columns makes a block, resulting in 64 blocks
along one row. Block 0 comprises columns 0 7,
block 1 comprises columns 7 15, block 2 comprises columns 16
23, etc., as shown in Figure 11.
During block-write cycles, only the six most significant
column addresses (A3A8) are latched on the first falling edge
of CASx to decode one of the 64 blocks. Address bits A0A2
are ignored. Each 2M-bit half has the same block selected.
A block-write cycle is entered in a manner similar to a DRAM
write cycle except DSF is held high on the first falling edge of
CASx\. As in a DRAM write operation, CASL\ and CASU\
enable the corresponding lower and upper DRAM DQ bytes to
be written. The column-mask data is input via the DQs and is
latched on either the first falling edge of CASx\ or the falling
edge of WE\, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as
described below. Refer to the write-per-bit section for details on
use of the write-mask capability, allowing additional performance
options.
Example of block write:
Block-write column address = 110000000
(A0A8 from left to right)
Color-data register =
Write-mask register =
Column-mask register =
bit 0
1011
1110
1111
1st
Quad
1011
1111
0000
2nd
Quad
1100
1111
0111
3rd
Quad
bit 15
0111
1011
1010
4th
Quad
Column-address bits A0 and A2 are ignored. Block 0 (columns

0 7) is selected for each 2M-bit half. The first half has
DQ0DQ2 written with bits 02 from the color-data register
(101) to first four columns of block 0. DQ3 is not written and
retains its previous data due to write-mask-register-bit 3
being 0. DQ4DQ7 has all four columns masked off due to
column-mask bits 47 being 0 so that no data is written.
The second half (DQ8DQ11 ) has its four DQs written
with bits 8 11 from the color-data register (1100) to columns
13 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to column-mask-register-bit 8
being 0.
DQ12DQ15 has DQ12, DQ14, and DQ15 written with bits
12, 14, and 15 from the color-data register to column 0 and
column 2 of its block 0. DQ13 retains its previous data on all
columns due to the write mask. Columns 1 and 3 retain their
previous data on all DQs due to the column mask. If the previous data for DQ12-DQ15 is all 0s, the upper half (DQ12-DQ15)
contains the data pattern shown in Figure 12 after the blockwrite operation shown in the previous example.
FIGURE 12: Example of Upper

DQ12-DQ15 After A Block-Write
Operation With Previous Data Of 0
FIGURE 11: Block Columns Organization
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load color register
The load-color-register cycle is performed using normal DRAM
write-cycle timing except that DSF is held high on the falling
edges of RAS\, CASL\, and CASU\. The color register is loaded
from pins DQ0 DQ15, which are latched on either the first
falling edge of CASx\ or the falling edge of WE\, whichever

occurs later. If only one CASx\ is low, only the corresponding
byte of the color register is loaded. When the color register is
loaded, it retains data until power is lost or until another loadcolor-register cycle is performed (see Figure 13 and Figure 14).
FIGURE 13: Example of Block Writes
FIGURE 14: Example Of A Persistent Block Write
Legend:
1. Refresh address
2. Row address
3. Block address (A3A8) is latched on the first falling edge of CASx\.
4. Color-register data
5. Write-mask data: DQ0DQ15 are latched on the falling edge of RAS\.
6. Column-mask data: DQiDQi+7 (i = 0, 8) are latched on either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later.
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DRAM-to-SAM transfer operation
full-register-transfer read
During the DRAM-to-SAM transfer operation, one row

(512 columns) in the DRAM array is selected to be transferred
to the 512-bit serial-data register. The transfer operation is
invoked by TRG\ being brought low and WE\ being held high
on the falling edge of RAS\. The state of DSF, which is latched
on the falling edge of RAS\, determines whether the fullregister-transfer read operation or the split-register-transfer read
operation is performed (see Table 4).
A full-register-transfer read operation loads data from a

selected half of a row in the DRAM into the SAM. TRG\ is
brought low and latched at the falling edge of RAS\. Nine rowaddress bits (A0A8) are also latched at the falling edge of
RAS\ to select one of the 512 rows available for the transfer.
The nine column-address bits (A0 A8) are latched at the first
falling edge of CASx\. Address bits A0A8 select one of the
SAMs 512 available tap points from which the serial data is
read out.
A full-register-transfer read can be performed in three ways:
early load, real-time load (or midline load), or late load. Each of
these offers the flexibility of controlling the TRG\ trailing edge
in the full-register-transfer read cycle (see Figure 15).
TABLE 4: SAM Fuction Table

CASx\
FALL
RAS\ FALL
FUNCTION
1
ADDRESS
DQ0-DQ15
MNE
CASx\ CODE
WE\
CASx\
TRG\
WE\
DSF
DSF
RAS\
CASX\
RAS\
Full-register-transfer Read
Row
Address
Tap
Point
RT
Split-register-transfer Read
Row
Address
Tap
Point
SRT
LEGEND:
X = Dont Care
NOTES:
1. Logic L is selected when either CASL\ or CASU\ are low.
FIGURE 15: Example of Full-Register-Transfer Read Operations
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split-register-transfer read
The SMJ55161A features two types of bidirectional data
transfer capability between DRAM and SAM.
1) Conventional (non split) transfer: 512 words by 16 bits of
data can be loaded from DRAM to SAM (Read transfer), or
from SAM to DRAM (write transfer).
2) Split transfer: 256 words by 16 bits of data can be loaded from
the lower/upper half of the DRAM to the lower/uppper half of
the SAM (Split read transfer), or from the lower/upper half to
SAM to the lower/upper half of DRAM (Split write transfer).
The conventional transfer and split transfer modes are
controlled by the DSF input signal. Data transfer is invoked by
holding the TRG\ signal low at the falling edge of RAS\.
The SMJ55161A supports 4 types of transfer operations:
Read transfer, Split read transfer, Write transfer and Split write
transfer as shown in the truth table. The type of transfer
operation is determined by the state of CAS\, WE\, and DSF
latched at the falling edge of RAS\. During conventional
transfer operations, the SAM port is switched from input to
output mode (Read transfer), or output to input mode (Write

transfer). It remains unchanged during split transfer operation
(Split read transfer or Split write transfer).
Both DRAM and SAM are divided by the most significant
row address (AX8), as shown in Figure 16. Therefore, no data
transfer between AX8=0 side DRAM and AX8=1 side DRAM
can be provided through the SAM. Care must be taken if the
split read transfer on AX8=1 side (or AX8=0 side) is provided
after the read transfer or the split read transfer, is provided on
AX8=0 side (or AX8=1 side).
QSF indicates which half of the register is being accessed
during serial-access operation. When QSF is low, the serialaddress pointer is accessing the lower (least significant) 256
bits of the SAM. When QSF is high, the pointer is accessing
the higher (most significant) 256 bits of the SAM. QSF changes
state upon completing a full-register-transfer-read cycle. The
tap point loaded during the current transfer cycle determines
the state of QSF. QSF also changes state when a boundary
between two register halves is reached.
FIGURE 16: DRAM and SAM Configuration
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FIGURE 17: Example Of A Split-Register-Transfer Read After A FullRegister-Transfer Read
FIGURE 18: Example Of Successive Split-Register-Transfer-Read

Operations
SMJ55161A
Rev. 1.6 03/05
21
VRAM
serial-read operation
The serial-read operation can be performed through the
SAM port simultaneously and asynchronously with DRAM
operations except during transfer operations. Serial data can be
read from the SAM by clocking SC starting at the tap point
loaded by the preceding transfer cycle, proceeding
sequentially to the most significant bit (bit 255), and then
wrapping around to the least significant bit (bit 0), as shown in
Figure 19.
For split-register-transfer-read operation, serial data can
be read out from the active half of the SAM by clocking SC
starting at the tap point loaded by the preceding splitregister-transfer cycle. The serial pointer then proceeds
sequentially to the most significant bit of the half, bit 255 or bit
511. If there is a split-register-transfer read to the inactive half
during this period, the serial pointer points next to the tap point
location loaded by that split-register transfer (see Figure 20).
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Rev. 1.6 03/05
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If there is no split-register-transfer read to the inactive half

during this period, the serial pointer points next to bit 256 or bit
0, respectively (see Figure 21).
split-register programmable stop point

The SMJ55161A offers a programmable stop-point mode
for split-register-transfer read operations. This mode can be
used to improve two-dimensional drawing performance in a
nonscanline data format.
For a split-register-transfer-read operation, the stop point
is defined as a register location at which the serial output stops
coming from one half of the SAM and switches to the opposite
half of the SAM. While in stop-point mode, the SAM is divided
into partitions whose length is programmed via row addresses
A4A7 in a CBR set (CBRS) cycle. The last serial-address
location of each partition is the stop point (see Figure 22).
22
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split-register programmable stop point
(continued)
Stop-point mode is not active until the CBRS cycle is
initiated. The CBRS operation is enabled by holding CASx\ and
WE\ low and DSF high on the falling edge of RAS\. The falling
edge of RAS\ also latches row addresses A4A7 which are
used to define the SAMs partition length. The other rowaddress inputs are dont cares. Stop-point mode should be
initiated after the initialization cycles are performed
(see Table 5).
In stop-point mode, the tap point loaded during the splitregister-transfer read cycle determines the SAM partition in
which the serial output begins and at which stop point the
serial output stops coming from one half of the SAM and
switches to the opposite half of the SAM (see Figure 23).
The stop-point mode of the previous revision 55161 is
designed to be compatible with both 256-bit SAM and 512-bit
SAM devices like the 55161A.
IMPORTANT: For proper device operation, a stop-pointmode (CBRS) cycle should be initiated immediately after the
power-up initialization cycles are performed.
TABLE 5: Programming Code for Stop-Point Mode

MAX
PARTITION
LENGTH
ADDRESS AT RAS\ IN CBRS CYCLE
NUMBER OF
PARTITIONS
A8
A7
A6
A5
A4
A0 - A3
16
16
32
64
128
256
X
X
X
X
L
L
L
H
L
L
H
H
L
H
H
H
H
H
H
H
X
X
X
X
8
4
2
1
STOP-POINT LOCATIONS
31, 63, 95, 127, 159, 191, 223, 255, 287,
319, 351, 383, 415, 447, 479, 511
63, 127, 191, 255, 319, 383, 447, 511
127, 255, 383, 511
255, 511
255
FIGURE 23: Example of Split-Register Operation With Programmable

Stop Points
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power up
register-transfer-read cycle and two SC cycles are required to

initialize the SAM port.
After initialization, the internal state of the SMJ55161A is
as shown in Table 6.
To achieve proper device operation, an initial pause of 200 ms is

required after power up followed by a minimum of eight RAS\
cycles or eight CBR cycles to initialize the DRAM port. A full-
TABLE 6: Internal State of SMJ55161A

STATE
QSF
Write Mode
Write-mask Register
Color Register
Serial-Register Tap Point
SAM Port
STATE AFTER INITIALIZATION

Defined by the transfer cycle during initialization
Nonpersistent Mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output Mode
ABSOLUTE MAXIMUM RATINGS*

*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
**All voltage values are with respect to VSS.
Supply voltage range, VCC**........................................-1V to +7 V

Voltage range on any pin................................................-1V to +7 V
Short-circuit output current.......................................................50mA
Power dissipation.........................................................................1.1W
Operating free-air temperature range, TA...................-55C to 125C
Storage temperature range, Tstg..................................-65C to 150C
RECOMMENDED OPERATING CONDITIONS

CONDITION
SYMBOL
MIN
NOM
MAX
UNIT
Supply Voltage
VCC
4.5
5.5
Supply Voltage
VSS
High-level input voltage
VIH
2.4
VCC +0.5
Low-level input voltage
VIL
-0.5
0.8
Operating free-air temperature
TA
-55
125
NOTES:
1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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Rev. 1.6 03/05
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ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
SAM
PORT
CONDITIONS
High-level output voltage
VOH
VOH = -1 mA
Low-level output voltage
VOL
VOL = 2 mA
-70
MIN MAX
-75
MIN MAX
-80
MIN MAX UNIT
2.4
2.4
2.4
0.4
0.4
0.4
10
10
10
10
10
10
VCC = 5.5V,
Input current (leakage)
II
VI = 0V to 5.8V,
All other pins at 0V to VCC
Output current (leakage)
IO
VCC = 5.5V, VO = 0V to VCC
ICC1
See note 4
Standby
140
130
120
mA
ICC1A
tc(SC) = MIN
Active
180
170
160
mA
Standby current
ICC2
All clocks = VCC
Standby
12
12
12
mA
Standby current
ICC2A
tc(SC) = MIN
Active
60
55
50
mA
RAS\-only refresh current
ICC3
See note 4
Standby
130
120
115
mA
RAS\-only refresh current
ICC3A
tc(SC) = MIN
Active
175
165
155
mA
ICC4
tc(P) = MIN
Standby
140
130
120
mA
Page-mode current2
ICC4A
tc(SC) = MIN
Active
190
180
170
mA
CBR current
ICC5
See note 4
Standby
110
100
95
mA
CBR current
ICC5A
tc(SC) = MIN
Active
150
140
130
mA
Data-transfer current
ICC6
See note 4
Standby
120
120
110
mA
Data-transfer current
ICC6A
tc(SC) = MIN
Active
170
160
150
mA
Operating current
Operating current
Page-mode current
5
5
NOTES:
1.
2.
3.
4.
5.
For conditions shown as MAX/MIN, use the appropriate value specified in the timing requirements.
Measured with outputs open.
SE\ is disabled for SQ output leakage tests.
Measured with one address change while RAS\ = VIL; tc(rd), tc(W), tc(TRD) = MIN.
Measured with one address change while CASx\ = VIH.
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Rev. 1.6 03/05
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CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE

AND OPERATING FREE-AIR TEMPERATURE*
PARAMETER
SYMBOL
TYP
MAX
UNIT
Ci(A)
10
pF
Input capacitance, address-strobe inputs
Ci(RC)
10
pF
Input capacitance, write-enable input
Ci(W)
10
pF
Input capacitance, serial clock
Ci(SC)
10
pF
Input capacitance, serial enable
Ci(SE)
10
pF
Input capacitance, special function
Ci(DSF)
10
pF
Input capacitance, transfer-register input
Ci(TRG)
10
pF
CO(O)
12
15
pF
CO(QSF)
10
12
pF
Input capacitance, address inputs
Output capacitance, SQ and DQ

Output capacitance, QSF
MIN
NOTES: *VCC = 5V 0.5V, and the bias on pins under test is 0V.
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1
PARAMETER
SYMBOL
Access time from CASx\
ta(C)
Access time from column address
ta(CA)
Access time from CASx\ high
ta(CP)
Access time from RAS\
CONDITIONS2
-70
MIN MAX
-75
MIN MAX
-80
MIN MAX
UNIT
17
20
20
ns
35
38
40
ns
40
43
45
ns
ta(R)
70
75
80
ns
Access time of DQ from TRG\ low
ta(G)
17
20
20
ns
Access time of SQ from SC high
ta(SQ)
CL = 30 pF
20
23
25
ns
ta(SE)
CL = 30 pF
17
18
20
ns
Access time of SQ from SE\ low

3
td(RLCL) = MAX
tdis(CH)
CL = 50 pF
17
20
20
ns
tdis(RH)
CL = 50 pF
17
20
20
ns
tdis(G)
CL = 50 pF
17
20
20
ns
Disable time, random output from WE\ low
tdis(WL)
CL = 50 pF
17
25
25
ns
Disable time, serial output from SE\ high
tdis(SE)
CL = 30 pF
15
18
20
ns
Disable time, random output from CASx\ high

Disable time, random output from RAS\ high
Disable time, random output from TRG\ high
NOTES:
1. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50pF. Data-out reference level: VOH/VOL = 2V/0.8V.
Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30pF. Serial-data out reference level: VOH/VOL =
2V/0.8V.
2. For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
3. tdis(CH), tdis(RH), tdis(G), tdis(WL), and tdis(SE) are specified when the output is no longer driven.
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TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1
PARAMETER
SYMBOL MIN
-70
MAX
MIN
-75
MAX
MIN
-80
MAX
UNIT
Cycle time, read
tc(rd)
124
140
150
ns
Cycle time, write
tc(W)
124
140
150
ns
tc(rdW)
170
188
200
ns
tc(P)
35
48
50
ns
tc(RDWP)
74
88
90
ns
tc(TRD)
130
140
150
ns
tc(SC)
20
24
30
ns
Pulse duration, CASx\ high
tw(CH)
10
Pulse duration, CASx\ low
tw(CL)
15
Pulse duration, RAS\ high
tw(RH)
50
tw(RL)
70
Pulse duration, WE\ low
tw(WL)
10
13
15
ns
Pulse duration, TRG\ low
tw(TRG)
17
20
20
ns
Pulse duration, SC high
tw(SCH)
10
ns
Pulse duration, SC low
tw(SCL)
10
ns
Pulse duration, TRG\ high
tw(GH)
20
20
20
ns
Pulse duration, RAS\ low (page mode)
tw(RL)P
70
100,000 75
100,000 80
Setup time, column address before CASx\ low
tsu(CA)
ns
Setup time, DSF before CASx\ low
tsu(SFC)
ns
Setup time, row address before RAS\ low
tsu(RA)
ns
Setup time, WE\ before RAS\ low
tsu(WMR)
ns
Setup time, DQ before RAS\ low
tsu(DQR)
ns
Setup time, TRG\ high before RAS\ low
tsu(TRG)
ns
Setup time, DSF low before RAS\ low
tsu(SFR)
ns
Setup time, data valid before CASx\ low
tsu(DCL)
ns
Setup time, data valid before WE\ low
tsu(DWL)
ns
tsu(rd)
ns
Setup time, early-write command, WE\ low before CASx\ low
tsu(WCL)
ns
Setup time, WE\ low before CASx\ high, write
tsu(WCH)
15
18
20
ns
Setup time, WE\ low before RAS\ high, write
tsu(WRH)
17
20
20
ns
Hold time, column address after CASx\ low
th(CLCA)
10
13
15
ns
Hold time, DSF after CASx\ low
th(SFC)
12
15
15
ns
Hold time, row address after RAS\ low
th(RA)
10
10
10
ns
Hold time, TRG\ after RAS\ low
th(TRG)
12
15
15
ns
Hold time, write mask after RAS\ low
th(RWM)
12
15
15
ns
Hold time, DQ after RAS\ low (write-mask operation)
th(RDQ)
12
15
15
ns
Cycle time, read-modify-write

Cycle time, page-mode read, write
Cycle time, page-mode read-modify-write
Cycle time, transfer read
Cycle time, serial clock
Pulse duration, RAS\ low
Setup time, read command, WE\ high before CASx\ low
SMJ55161A
Rev. 1.6 03/05
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10,000
20
10
10,000
55
10,000
75
20
ns
10,000
60
10,000
80
ns
ns
10,000
100,000
ns
ns
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VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1
SYMBOL MIN
PARAMETER
-70
MAX
MIN
-75
-80
MAX MIN MAX UNIT
th(SFR)
10
10
10
ns
Hold time, column address valid after RAS\ low
th(RLCA)
30
33
35
ns
Hold time, data valid after CASx\ low
th(CLD)
12
15
15
ns
Hold time, DSF after RAS\ low

5
th(RLD)
30
35
35
ns
th(WLD)
12
15
15
ns
th(CHrd)
ns
th(RHrd)
ns
Hold time, write, WE\ low after CASx\low
th(CLW)
12
15
15
ns
th(RLW)
30
35
35
ns
th(WLG)
10
10
10
ns
th(SHSQ)
ns
Hold time, DSF after RAS\ low
th(RSF)
30
35
35
ns
Hold time, output valid after CASx\ low
th(CLQ)
ns
td(RLCH)
70
75
80
td(RLCH)
10
13
15
Delay time, CASx\ high to RAS\ low
td(CHRL)
ns
Delay time, CASx\ low to RAS\ high
td(CLRH)
17
20
20
ns
td(CLWL)
40
48
50
ns
Delay time, RAS\ low to CASx\ low
td(RLCL)
15
Delay time, column address valid to RAS\ high
td(CARH)
35
38
40
ns
Delay time, column address valid to CASx\ high
td(CACH)
35
38
40
ns
td(RLWL)
90
100
105
ns
td(CAWL)
55
63
65
ns
td(CLRL)
ns
Delay time, RAS\ high to CASx\ low
td(RHCL)
ns
Delay time, CASx\ low to TRG\ high for DRAM read cycles
td(CLGH)
20
20
20
ns
15
Hold time, data valid after RAS\ low

Hold time, data valid after WE\ low
Hold time, read, WE\ high after CASx\ high

Hold time, read, WE\ high after RAS\ high
Hold time, write, WE\ low after RAS\ low

Hold time, TRG\ high after WE\ low
Hold time, SQ valid after SC high
Delay time, RAS\ low to CASx\ high
Delay time, CASx\ low to WE\ low
See Note 8
9,10
11
Delay time, RAS\ low to WE\ low
Delay time, column address valid to WE\ low
Delay time, CASx\ low to RAS\ low
Delay time, TRG\ high before data applied at DQ

12
Delay time, RAS\ low to TRG\ high
Delay time, RAS\ low to first SC high after TRG\ high
13
Delay time, RAS\ low to column address valid

Delay time, TRG\ low to RAS\ high
Delay time, CASx\ low to first SC high after TRG\ high
Delay time, SC high to TRG\ high
12, 13
Delay time, TRG\ high to RAS\ high
12
14
Delay time, TRG\ high to RAS\ low

Delay time, TRG\ high to SC high
SMJ55161A
Rev. 1.6 03/05
12
13
50
20
50
20
ns
60
ns
td(GHD)
15
15
td(RLTH)
55
58
ns
td(RLSH)
70
75
ns
td(RLCA)
12
td(GLRH)
15
20
20
ns
td(CLSH)
20
23
25
ns
td(SCTR)
ns
td(THRH)
-10
-10
-10
ns
td(THRL)
50
55
60
ns
td(THSC)
15
18
20
ns
35
15
35
15
ns
40
ns
28
VRAM
SM55161A
Production

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1
PARAMETER
Delay time, RAS\ high to last (most significant) rising edge of SC
before boundary switch during split-register-transfer read cycles
Delay time, CASx\ low to TRG\ high in read-time-transfer read
cycles
Delay time, column address to first SC in early-load-transfer read
cycles
Delay time, column address to TRG\ high in real-time-transfer read
cycles
-70
-75
-80
SYMBOL MIN MAX MIN MAX MIN MAX UNIT
td(RHMS)
20
20
20
ns
td(CLTH)
17
15
15
ns
td(CASH)
25
28
30
ns
td(CAGH)
20
20
20
ns
Delay time, data to CASx\ low
td(DCL)
ns
Delay time, data to TRG\ low
td(DGL)
ns
td(MSRL)
20
20
20
ns
Delay time, last (most significant) rising edge of SC to RAS\ low

before boundary switch during split-register-transfer read cycles
Delay time, last (127 or 255) rising edge of SC to QSF switching at
the boundary during split-register-transfer read cycles
td(SCQSF)
25
28
30
ns
15
td(CLQSF)
30
33
35
ns
15
td(GHQSF)
25
28
30
ns
td(RLQSF)
70
73
75
ns
ms
25
ns
15
Delay time, CASx\ low to QSF switching in transfer-read cycles

Delay time, TRG\ high to QSF switching in transfer-read cycles
Delay time, RAS\ lwo to QSF switching in transfer-read cycles
Refresh time interval, memory
15
trf(MA)
tt
Transition time
8
3
25
8
3
25
NOTE:
1. Timing measurements are referenced to VIL MAX and VIH MIN.
2. Cycle time assumes tt = 3 ns.
3. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the transition times, this can require additional CASx\
low time [tw(CL)].
4. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the transition times, this can require additional RAS\
low time [tw(RL)].
5. The minimum value is measured when td(RLCL) is set to td(RLCL) MIN as a reference.
6. Either th(RHrd) or td(CHrd) must be satisfied for a read cycle.
7. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
8. CBR refresh operation only.
9. Read-modify-write operation only.
10. TRG\ must disable the output buffers prior to applying data to the DQ pins.
11. The maximum value is specified only to assure RAS\ access time.
12. Real-time-load transfer read or late-load-transfer read cycle only.
13. Early-load-transfer read cycle only.
14. Full-register-(read) transfer cycles only.
15. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is
VOH / VOL = 2 V/0.8 V.
SMJ55161A
Rev. 1.6 03/05
29
VRAM
SM55161A
Production

SAM TO DRAM WRITE TRANSFER & SERIAL IN TIMINGS
PARAMETER
SYMBOL
-70
-75
-80
UNITS
Last SC to RAS\ set-up time (serial input)
tSRS
25
25
25
ns
RAS\ to serial input delay time
tSDD
35
40
45
ns
Serial input set-up time
tSDS
ns
Serial input hold time
tSDH
ns
Serial input to SE\ delay time
tSZE
ns
Serial input to first SC delay time
tSZS
ns
Serial write enable to set-up time
tSWS
ns
Serial write enable to hold time
tSWH
10
12
12
ns
Serial write disable to set-up time
tSWiS
ns
Serial write disable to hold time
tSWiH
10
12
12
ns
SMJ55161A
Rev. 1.6 03/05
30
VRAM
SM55161A
Production
FIGURE 24: READ-CYCLE TIMING WITH CASx\-CONTROLLED OUTPUT
SMJ55161A
Rev. 1.6 03/05
31
VRAM
SM55161A
Production
FIGURE 25: READ-CYCLE TIMING WITH RAS\-CONTROLLED OUTPUT
SMJ55161A
Rev. 1.6 03/05
32
VRAM
SM55161A
Production

FIGURE 26: EARLY-WRITE-CYCLE TIMING
TABLE 7: EARLY-WRITE-CYCLE STATE TABLE

CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
SMJ55161A
Rev. 1.6 03/05
1
H
L
L
STATE
2
3
Don't Care Valid Data
Write Mask Valid Data
33
VRAM
SM55161A
Production
FIGURE 27: LATE-WRITE-CYCLE TIMING (OUTPUT-ENABLE-CONTROLLED WRITE)
TABLE 8: LATE-WRITE-CYCLE STATE TABLE

CYCLE
SMJ55161A
Rev. 1.6 03/05
1
H
L
L
STATE
2
3
34
VRAM
SM55161A
Production
FIGURE 28: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD)
NOTES:
1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.
SMJ55161A
Rev. 1.6 03/05
35
VRAM
SM55161A
Production
FIGURE 29: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (LATE-WRITE LOAD)
NOTES:
1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.
SMJ55161A
Rev. 1.6 03/05
36
VRAM
SM55161A
Production
FIGURE 30: READ-WRITE/READ-MODIFY-WRITE-CYCLE TIMING
TABLE 9: READ-WRITE/READ-MODIFY-WRITE-CYCLE STATE TABLE

CYCLE
SMJ55161A
Rev. 1.6 03/05
1
H
L
L
STATE
2
3
37
VRAM
SM55161A
Production

FIGURE 31: ENHANCED-PAGE-MODE READ-CYCLE TIMING
NOTES:
A. Access time is ta(CP) or ta(CA) dependent.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write
mode (normal, block write, etc.).
SMJ55161A
Rev. 1.6 03/05
38
VRAM
SM55161A
Production
FIGURE 32: ENHANCED-PAGE-MODE WRITE-CYCLE TIMING
NOTES:
A. Referenced to the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. To ensure page-mode cycle time, TRG\ must remain high throughout the entire page-mode operation if the late write
feature is used. If the early write-cycle timing is used, the state of TRG\ is a dont care after the minimum period th(TRG) from the falling
edge of RAS\..
TABLE 10: ENHANCED-PAGE-MODE WRITE-CYCLE STATE TABLE

CYCLE
Load-write mask on either the first falling edge of CASx\
or the falling edge of WE\, whichever occurs later.
1
L
L
L
2
L
L
L
STATE
3
4
H
Don't Care
L
Write Mask
L
Don't Care
H
5
Valid Data
Valid Data
Valid Data
Don't Care Write Mask
NOTES:
1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a dont care during this cycle.
SMJ55161A
Rev. 1.6 03/05
39
VRAM
SM55161A
Production
FIGURE 33: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE TIMING
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
TABLE 11: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE STATE TABLE

CYCLE
Load-write mask on either the first falling edge of CASx\
or the falling edge of WE\, whichever occurs later.
1
L
L
L
2
L
L
L
STATE
3
4
5
H
L
L
H
Don't Care Write Mask
NOTES:
1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a dont care during this cycle.
SMJ55161A
Rev. 1.6 03/05
40
VRAM
SM55161A
Production
FIGURE 34: ENHANCED-PAGE-MODE READ-/WRITE-CYCLE TIMING
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write
mode (normal, block write, etc.).
SMJ55161A
Rev. 1.6 03/05
41
VRAM
SM55161A
Production
FIGURE 35: LOAD-COLOR-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD)
SMJ55161A
Rev. 1.6 03/05
42
VRAM
SM55161A
Production
FIGURE 36: LOAD-COLOR-REGISTER-CYCLE TIMING (LATE-WRITE LOAD)
SMJ55161A
Rev. 1.6 03/05
43
VRAM
SM55161A
Production

FIGURE 37: BLOCK-WRITE-CYCLE TIMING (EARLY WRITE)
SMJ55161A
Rev. 1.6 03/05
44
VRAM
SM55161A
Production

TABLE 12: BLOCK-WRITE-CYCLE STATE TABLE
1
H
L
L
CYCLE
Block-write operation (nonmasked)
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
STATE
2
3
Write-mask data 0: I/O write disable

1: I/O write enable DQ
Column-mask data DQi DQi + 7 0: column-write disable
(i = 0,8) 1: column-write enable
COLUMN MASK DATA
Lower Byte
Upper Byte
SMJ55161A
Rev. 1.6 03/05
DQ0-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN MASK DATA

Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Low: Mask
High: No Mask
Low: Mask
High: No Mask
45
VRAM
SM55161A
Production

FIGURE 38: BLOCK-WRITE-CYCLE TIMING (LATE WRITE)
SMJ55161A
Rev. 1.6 03/05
46
VRAM
SM55161A
Production

TABLE 13: BLOCK-WRITE-CYCLE STATE TABLE
1
H
L
L
CYCLE
STATE
2
3

COLUMN MASK DATA
Lower Byte
Upper Byte
SMJ55161A
Rev. 1.6 03/05
DQ0-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN MASK DATA

Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Low: Mask
High: No Mask
Low: Mask
High: No Mask
47
VRAM
SM55161A
Production
FIGURE 39: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE TIMING
SMJ55161A
Rev. 1.6 03/05
48
VRAM
SM55161A
Production
TABLE 14: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE

1
H
L
L
CYCLE
STATE
2
3

COLUMN MASK DATA
Lower Byte
Upper Byte
SMJ55161A
Rev. 1.6 03/05
DQ0-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
COLUMN MASK DATA

Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Low: Mask
High: No Mask
Low: Mask
High: No Mask
49
VRAM
SM55161A
Production

FIGURE 40: RAS\-ONLY REFRESH-CYCLE TIMING
SMJ55161A
Rev. 1.6 03/05
50
VRAM
SM55161A
Production

FIGURE 41: CBR-REFRESH-CYCLE TIMING
TABLE 15: CBR-CYCLE STATE TABLE

CYCLE
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop-point set and no reset
SMJ55161A
Rev. 1.6 03/05
1
Don't Care
Don't Care
Stop Address
STATE
2
L
H
H
3
H
H
L
51
VRAM
SM55161A
Production

FIGURE 42: HIDDEN-REFRESH-CYCLE TIMING
TABLE 16: HIDDEN-REFRESH-CYCLE STATE TABLE

CYCLE
CBR refresh with option reset
CBR refresh with no reset
CBR refresh with stop-point set and no reset
SMJ55161A
Rev. 1.6 03/05
1
Don't Care
Don't Care
Stop Address
STATE
2
L
H
H
3
H
H
L
52
VRAM
SM55161A
Production
FIGURE 43: FULL-REGISTER TRANSFER-READ TIMING, EARLY-LOAD OPERATIONS
NOTES:
A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
to from the 512 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive
transition of SC.
C. A0 A8.
D. Early-load operation is defined as th(TRG) MIN < th(TRG) < td(RLTH) MIN.
E. There must be no rising transitions.
SMJ55161A
Rev. 1.6 03/05
53
VRAM
SM55161A
Production
FIGURE 44: FULL-REGISTER TRANSFER READ-TIMING, REAL-TIME

LOAD OPERATION/LATE-LOAD OPERATION
NOTES:
A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
to from the 512 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive
transition of SC.
C. A0A8.
D. Late load operation is defined as td(THRH) < 0 ns.
SMJ55161A
Rev. 1.6 03/05
54
VRAM
SM55161A
Production

FIGURE 45: SPLIT-REGISTER-TRANSFER-READ TIMING
NOTES:
A. A0A7: tap point of the given half; A8: identifies the DRAM row half
SMJ55161A
Rev. 1.6 03/05
55
VRAM
SM55161A
Production

FIGURE 46: SERIAL-READ-CYCLE TIMING (SE\ = VIL)
NOTES:
A. While the data is being read through the serial-data register, TRG\ is a dont care; however, TRG\ must be held high when RAS\ goes low.
This is to avoid the initiation of a register-data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the
read mode by performing a transfer-read cycle.
FIGURE 47: SERIAL-WRITE-CYCLE TIMING
SMJ55161A
Rev. 1.6 03/05
56
VRAM
SM55161A
Production
FIGURE 48: SERIAL-READ TIMING (SE\-CONTROLLED READ)
NOTES:
A. While the data is being read through the serial-data register, TRG\ is a dont care; however, TRG\ must be held high when RAS\ goes low. This
is to avoid the initiation of a register-data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read
mode by performing a transfer-read cycle.
SMJ55161A
Rev. 1.6 03/05
57
VRAM
SM55161A
Production

FIGURE 49: SPLIT-REGISTER OPERATING SEQUENCE
NOTES:
A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer cycle. This is
necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-register-transfer-read cycle
(CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no
minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle.
B. A split-register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of
the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register-transfer cycle into the inactive half. After the
td(MSRL) requirement is met, the split-register transfer into the inactive half must also satisfy the minimum td(RHMS) requirement. td(RHMS) is the
minimum delay time between the rising edge of RAS\ of the split-register-transfer cycle into the inactive half and the rising edge of the serial
clock of the last bit (bit 255 or 511).
SMJ55161A
Rev. 1.6 03/05
58
VRAM
SM55161A
Production
FIGURE 50: MASKED WRITE TRANSFER
NOTES:
1. SE\ = L
2. There must be no rising transitions.
3. QSF = L - Lower SAM (0-255) is active.
QSF = H - Upper SAM (256-511) is active.
SMJ55161A
Rev. 1.6 03/05
59
VRAM
SM55161A
Production

FIGURE 51: MASKED SPLIT WRITE TRANSFER
NOTES:
1. SE\ = L
2. QSF = L - Lower SAM (0-255) is active.
QSF = H - Upper SAM (256-511) is active.
3. Si is the SAM start address in before SWT.
4. STOP i and STOP j are programmable stop addresses.
SMJ55161A
Rev. 1.6 03/05
60
VRAM
SM55161A
Production
MECHANICAL DEFINITIONS*
Package Designator GB
SMD 5962-94549, Case Outline X
NOTES:
1. All linear dimensions are in inches (millimeters).
2. This drawing is subject to change without notice.
3. Index mark may appear on top or bottom depending on package vendor.
4. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38)
radius relative to the center of the ceramic.
5. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
6. The pins can be gold plated or solder dipped.
7. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively
SMJ55161A
Rev. 1.6 03/05
61
VRAM
SM55161A
Production
MECHANICAL DEFINITIONS*
Package Designator HKC
SMD 5962-94549, Case Outline Y
NOTES:
1.
2.
3.
4.
5.
All linear dimensions are in inches (millimeters).

This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
All leads not shown for clarity purposes.
SMJ55161A
Rev. 1.6 03/05
62
VRAM
SM55161A
Production
ORDERING INFORMATION
EXAMPLE: SM55161A-75GBI
Prefix*
SM
SMX
SM
SMX
SM
SMX
Part
Number
55161A
55161A
55161A
55161A
55161A
55161A
Speed
Package
Temp
-70
-70
-75
-75
-80
-80
GB
GB
GB
GB
GB
GB
M or I
M or I
M or I
M or I
M or I
M or I
Speed
Package
Temp
-70
-70
-75
-75
-80
-80
HKC
HKC
HKC
HKC
HKC
HKC
M or I
M or I
M or I
M or I
M or I
M or I
EXAMPLE: SM55161A-80HKCM
Prefix*
SM
SMX
SM
SMX
SM
SMX
Part
Number
55161A
55161A
55161A
55161A
55161A
55161A
SM Prefix: Standard Military Processing using MIL-STD-883C

flow & methods but non-complaint to para 1.2.1
SMX Prefix: strictly commercial flow samples
I suffix: -40C to +85C
M suffix: -55C to 125C
SMJ55161A
Rev. 1.6 03/05
63
VRAM
SM55161A
Production
ASI TO DSCC PART NUMBER

CROSS REFERENCE
Package Designator GB
ASI Part #
Package Designator HKC
SMD Part #
ASI Part #
TO BE COMPLETED WHEN SMD LISTING IS RELEASED
SMJ55161A
Rev. 1.6 03/05
SMD Part #
TO BE COMPLETED WHEN SMD LISTING IS RELEASED
64

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Austin Semiconductor, Inc.

MULTIPORT VIDEO RAM

64-Pin Ceramic Flatpack (HKC)

Military Processing Flow(SM Level)

DRAM Write-Enable Select

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Access Time Row Enable

Access Time Serial Data

DRAM Cycle Time

DRAM Page Mode

Serial Cycle Time

GB PACKAGE (Bottom View) & PIN ASSIGNMENTS

The SMJ55161A offers a split-register-transfer read

FUNCTIONAL BLOCK DIAGRAM

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DRAM block write

DRAM block write

DRAM write (nonmasked)

DRAM block write (nonmasked)

Reserved (do not use)

CBR refresh (option reset)

Load write-mask register

Load color register

Masked Split Write Transfer

Masked Flash Write Transfer

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TABLE 2: PIN DESCRIPTIONS VS. OPERATIONAL MODE

Column-address strobe, DQ output enable

DRAM data I/O, write mask

row-address strobe (RAS\)

Eighteen address bits are required to decode each one of

RAS\ is similar to a chip enable so that all DRAM cycles

column-address strobe (CASL, CASU)

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serial-data outputs (SQ0 SQ15)

TRG\ selects either DRAM or transfer operation as RAS\

Serial data is read from the SQ pins. The SQ output buffers

write-mask select, write enable (WE)

serial clock (SC)

In DRAM operation, WE\ enables data to be written to the

Serial data is accessed out of the data register during the

special-function select (DSF)

serial enable (SE)

The DSF input is latched on the falling edge of RAS\ or the

During serial-access operations, SE\ is used as an enable/

special-function output (QSF)

DRAM data I/O, write mask data (DQ0DQ15)

no connect / ground (NC/GND)

Austin Semiconductor, Inc.

DRAM block write

DRAM block write

DRAM write (nonmasked)

DRAM block write (nonmasked)

Reserved (do not use)

CBR refresh (option reset)

Load write-mask register

Austin Semiconductor, Inc.