Ec 1201digital Electronics

EC 1201DIGITAL ELECTRONICS
A. Jawahar,
Assistant Professor, ECE Dept.
SSN College of Engineering
Phone: 044 32909855 275 (Extn : 359)
91-9444067484
Email: jawahara@ssn.edu.in
AIM
To learn the basic methods for the design of digital circuits and
provide the fundamental concepts used in the design of digital
systems.
OBJECTIVES
To introduce number systems and codes
To introduce basic postulates of Boolean algebra and shows the
correlation between Boolean expressions
To introduce the methods for simplifying Boolean expressions
To outline the formal procedures for the analysis and design of
combinational circuits and sequential circuits
To introduce the concept of memories and programmable logic
devices
UNIT I NUMBER SYSTEMS
Binary, Octal, Decimal, Hexadecimal-Number base conversions
omplements signed Binary numbers. Binary Arithmetic- Binary
codes: Weighted BCD-2421-Gray code-Excess 3 code-ASCII
Error detecting code conversion from one code to another-
Boolean postulates and laws De-Morgans Theorem- Principle of
Duality- Boolean expression Boolean function- Minimization of
Boolean expressions Sum of Products (SOP) Product of Sums
(POS)-Minterm- Maxterm- Canonical forms Conversion between
canonical forms Karnaugh map Minimization Dont care
conditions.
UNIT II
LOGIC GATES: AND, OR, NOT, NAND, NOR, Exclusive OR and
Exclusive NOR- Implementations of Logic Functions using
gates, NAND NOR implementations Multi level gate
implementations- Multi output gate implementations. TTL and
CMOS Logic and their characteristics Tristate gates.
COMBINATIONAL CIRCUITS:
Design procedure Adders-Subtractors Serial adder/
Subtractor - Parallel adder/ Subtractor- Carry look ahead adder-
BCD adder- Magnitude Comparator- Multiplexer/ Demultiplexer-
encoder / decoder parity checker code converters.
Implementation of combinational logic using MUX, ROM, PAL
and PLA.What you should know:
UNIT III SEQUENTIAL CIRCUIT
Flip flops SR, JK, T, D and Master slave Characteristic table and
equation Application table Edge triggering Level Triggering
Realization of one flip flop using other flip flops Asynchronous /
Ripple counters Synchronous counters Modulo n counter
Classification of sequential circuits Moore and Mealy -Design of
Synchronous counters: state diagram- State table State minimization
State assignment- ASM-Excitation table and maps-Circuit
implementation - Register shift registers- Universal shift register
Shift counters Ring counters.
UNIT IVASYNCHRONOUS SEQUENTIAL CIRCUITS
Design of fundamental mode and pulse mode circuits primitive
state / flow table Minimization of primitive state table state
assignment Excitation table Excitation map- cycles Races
Hazards: Static Dynamic Essential Hazards elimination.
UNIT V MEMORY DEVICES
Classification of memories RAM organization Write operation
Read operation Memory cycle - Timing wave forms Memory
decoding memory expansion Static RAM Cell-Bipolar RAM cell
MOSFET RAM cell Dynamic RAM cell ROM organization -
PROM EPROM EEPROM EAPROM Programmable Logic
Devices Programmable Logic Array (PLA)- Programmable Array
Logic (PAL)-Field Programmable Gate Arrays (FPGA).
TEXT BOOKS
M. Morris Mano, Digital Design, 3.ed., Prentice Hall of India Pvt. Ltd., New Delhi,
2003/Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003 (Unit I, II, V)
John .M Yarbrough, Digital Logic Applications and Design, Thomson- Vikas
publishing house, New Delhi, 2002. (Unit III, IV)
REFERENCES
S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 2nd ed., Vikas
Publishing House Pvt. Ltd, New Delhi, 2004
Charles H.Roth. Fundamentals of Logic Design, Thomson Publication Company,
2003.
Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 5 ed.,
Tata McGraw Hill Publishing Company Limited, New Delhi, 2003.
R.P.Jain, Modern Digital Electronics, 3 ed., Tata McGrawHill publishing company
limited, New Delhi, 2003.
Thomas L. Floyd, Digital Fundamentals, Pearson Education, Inc, New Delhi, 2003
Donald D.Givone, Digital Principles and Design, Tata Mc-Graw-Hill Publishing
company limited, New Delhi, 2003.
Complements
Used in digital computers for simplifying the subtraction operation
and for logical manipulation
There are two types of complements for each base-r system
The radix (rs) complement
Diminished radix (r-1) complement
Given a number N in base r having n digits, the (r-1)s complement
is defined as (r
n
1) N
Example
The 9s complement of 546700 is 999999 546700 = 453299
The 9s complement of 012398 is 999999 012398 = 987601
The 1s complement of 1011000 is 0100111
The (r-1) s complement of octal or hexadecimal numbers is
obtained by subtracting each digit from 7 or F (decimal 15),
respectively
Radix complement
The rs complement of a n-digit number N in base r is defined as
r
n
-N, for N0 and 0 for N=0
It is obtained by adding 1 to the (r-1)s complement
Example
If the original number N contains radix point, the point should be
removed temporarily in order to form the rs or (r-1)s complement
The radix point is then restored to the complemented number in the
same relative position
The complement of the complement restores the number to its
original value.
Subtraction with complements
The subtraction of two n-digit unsigned numbers M N in base r can
be done as follows
1. Add the minuend, M, to the rs complement of the subtrahend, N.
This performs M + (r
n
- N) = M N + r
n
2. If M N, the sum will produce an end carry, r
n,
which can be
discarded; what is left is the result M N
3. If M < N, the sum does not produce an end carry and is equal to r
n
(N-M), which is the rs complement of (N-M). To obtain the answer in

a familiar form, take the rs complement of the sum and place a
negative sign in front
Using 10s complement, subtract 72532 3250
Note that M has 5 digits and N has only 4 digits. Both numbers must
have the same number of digits, we write N as 03250 and take 10s
complement of it and add. The occurrence of the end carry signifies
that M N and the result is positive (ans = 69282)
Try 3250 72532.
X = 1010100 and Y = 1000011, perform the subtraction X Y and
Y-X using 2s complements and 1s complements (ans = 0010001;
1101111, using 1s complement the ans 0010001; 1101110)
SIGNED BINARY NUMBERS
In ordinary arithmetic, a negative number is indicated by minus sign
and positive number by a plus sign.
Because of hardware limitations, computer must represent
everything with binary digits
Generally, to represent the sign with a bit placed in the leftmost
position of the number. The convention is to make the sign bit 0 for
positive and 1 for negative
Usually, there is no confusion in identifying the bits if the type of
representation for the number is known in advance
The ways of representing the signed binary numbers are signed-
magnitude representation, signed 1s complement representation
and signed 2s complement representation
Example
Consider 9 represented in binary with eight bits
+9 is represented with a sign bit of 0 in left most position, followed
by the binary equivalent of 9, which gives 00001001
Although, there is only one way to represent +9, there are three
different ways to represent -9 with eight bits:
Signed-magnitude representation : 10001001
Signed-1s complement representation: 11110110
Signed-2s complement representation : 11110111
In signed-magnitude, -9 is obtained from +9 by changing the sign bit
in the leftmost position from 0 to 1
In signed-1s complement, -9 is obtained by complementing all the
bits of +9 including the sign bit
The signed-2s complement representation of -9 is obtained by
taking the 2s complement of the positive number, including the sign
bit
Conversion of a binary number to gray code
A binary number can be converted to its Gray code when
i) the first bit (MSB) of the Gray code is the same as the first bit of
the binary number
Ii) The second bit of the Gray code equals the exclusive-OR, of
the first and the second bits of the binary number, i.e. it will be 1 if
these binary code bits are different and 0 if they are same
Iii) The third Gray code bit equals the exclusive-OR of the second
and third bits of the binary number and so on.
Convert the following binary number to gray code
1) 10110 (11101)
2) 10101101 (11111011)
Conversion from gray code to binary
i) The first bit (MSB) is the same as that of the first Gray code bit
Ii) If the second gray bit is 0, the second binary bit is the same as
that of the first binary; if the second gray bit is 1, the second binary
bit is the inverse of its first binary bit
Iii) Step ii) is repeated for each successive bit
Excess-3 code
An excess-3 code is obtained by adding 3 to a decimal number
For example, to encode the decimal number 6 into an excess-3
code, we must first add 3 in order to obtain 9.
The 9 is then encoded in its equivalent 4-bit binary code 1001
It is self complementing code
It is also a reflective code (a code is said to be reflective when the
code for 9 is the complement of the code for 0, 8 for 1, 7 for 2
Convert the decimal number 643 into its excess-3 code
Decimal number 6 4 3
Add 3 to each digit +3 +3 +3
sum = 9 7 6 converting this sum into its BCD code
1001 0111 0110
Error detecting codes
During the process of binary data transmission, errors may occur.
To detect and correct such errors, error detecting codes and error-
correcting codes may be used
If a single error transforms a valid code into an invalid one, it is said
to be a single error detecting code
The simple error detecting method is the parity check in which an
extra parity bit is included with the binary message, to make the total
number of 1s either odd or even resulting in even-parity and odd-
parity method
Even-parity method the total number of 1s including the parity bit
must be even number
Odd-parity method the total number of 1s including the parity bit
must be an odd number
Any Queries ?
Please Contact
jawahara@ssn.edu.in
Thank You

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EC 1201DIGITAL ELECTRONICS

(N-M), which is the rs complement of (N-M). To obtain the answer in

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