DSP Control Loop Design

DSP based Digital Control Design
for DC-DC Switch Mode

Power Converter
Shamim Choudhury
Texas Instruments Inc.
1
Digital Control of DC/DC Converter
DC/DC Buck Converter
Iin Io Vo
L
Vin C RL
Vin = 4V ~ 6V,
Vo = 1.6V, Io = 16A
L = 1uH, C = 1620uF, ESR = 0.004 ohm
PWM Freq = 250kHz,
Digital Control Loop Sampling Freq, fs = 250kHz,
Voltage Control Loop Bandwidth = 20kHz,
Phase Margin = 45 deg
Settling Time < 75uSec
2
N N+1
Sampling period (Ts) Sampling Scheme 1
Sample to PWM Update Delay Td = 0.5Ts
PWM period n n+1 (Computation Delay)
ADC conv time Update
PWM
PWM/
ADC
Int Int
ISR
Code
execution
Context Back-ground
Execute Context spare t
save
Controller restore
N
Sampling period (Ts) N+1 Sampling Scheme 2
Sample to PWM Update Delay Td = 2.0Ts
PWM period n n+1 (Computation Delay)
ADC conv time
Update Update Update
PWM PWM PWM
PWM/ADC
Int Int
ISR
Code
execution 3
Context spare Back-ground

save Execute Context t
Controller restore
Control Design by Emulation
Iin Kd Output Voltage Sensing Gain
Vo
L
Vin C Vos
RL
Vo(n)
∧ 7FFFFFFF
d A/D
G P (s) =
Vo PWM
∧
d Vo(n)
U(n) Vo
Gc(z) +
E(n) 2V
TMS320F2810 Vref
0 00000000
Vo (n) = Vo K d ⇒ Vo (n) max = Vo max K d
1
⇒ 7 FFFFFFh = Vo max K d ⇒ Kd = , for Vo (n) in Q31
Vo max 4
=> Kd=0.5
Vin=5.0, RL=0.1, Kd=0.5, d Vo

Gp(s)
L=1uH, C=1620uF,
Rc=0.004 ohm,
Fm Kd
Ignore Sample & Hold (S&H) Effect,
PWM Modulator Gain Fm = 1, Vo(n)
Continuous Plant Gp1(s) = Kd.Fm.Gp(s), U(n) E(n)
Gc(z) +
1.62x10-5 s + 2.5
Vref
Gp1(s) = ---------------------------------------
1.685x10-9 s2 + 1.648x10-5 s + 1
Gc(s) = ?, Gc(z) = ?
5
Use Matlab SISOTOOL for the plant Gp1(s) and design the
continuous controller Gc1(s)
Continuous System Bode Plot s-plane root locus
(Matlab) (Matlab)
Settling Time(1%)
< 45uS
BW = 25kHz, PM = 71 deg
14.3 s^2 + 651400 s + 7.2e009

Gc1(s) = ------------------------------------------
s^2 + 125600 s 6
Compute Equivalent Discrete Controller Gc(z)
1. Discrete Equivalents via Numerical Integration
1a. Forward rule, s= (z-1)/Ts
2a. Backward rule, s = (z-1)/zTs
3a. Trapezoidal/Tustin/Bilinear, s = 2(z-1)/Ts(z+1)
2. Pole-Zero Matching Equivalents, z = esTs
3. Hold Equivalents : zero-order-hold (ZOH), first-order-hold (FOH)
In Matlab, Gc_z = c2d(Gc_s, Ts, 'matched')
12.34 z^2 - 22.53 z + 10.28
[pole-zero matched,
Gc1(z) = -------------------------------------------
Ts = 4uSec]
z^2 - 1.605 z + 0.6051
In Matlab, Gc_z = c2d(Gc_s, Ts, ‘tustin')
12.49 z^2 - 22.81 z + 10.41
Gc1(z) = ------------------------------------ [Tustin, Ts = 4uSec]
z^2 - 1.598 z + 0.5985 7
Discrete System Bode Plot, Pole-Zero Matched Controller,
Gp1(z)*Gc1(z)
(Matlab)
BW = 25.2kHz, PM = 53.1 deg, GM = 11.3dB
Transient Response (Fpwm = 250KHz),

Pole-Zero Matched Controller
Gp1(z)*Gc1(z)
Discrete System Bode Plot, Tustin Controller,

Gp1(z)*Gc1(z)
(Matlab)
BW = 25.4kHz, PM = 53.6 deg, GM = 11.2dB
8
Direct Digital Control
Iin Vo
L
Vin C
RL
Kd
Ts
d D/A
∧ (ZOH) Vo(n)
Vo
GP (s) =
∧ Hc U(n) Gc(z)
E(n)
+
d
Comp Delay Model TMS320F2810 Vref

Hc = e-sTd ,
Td = Comp Time Delay 9
Direct Digital Control of DC/DC Converter
Effect of Sampling & Hold
Time Delay Ts/2
Ts
PM = 33.18 deg
ZOH = -ωTs/2
= -180f/fs
fs = 250kHz,
f = 7.25kHz,
additional
phase lag of 5.2°
PM = 28 deg f = 125kHz,
additional
phase lag of 90° 10
Direct Digital Control
Vin=5.0, RL=0.1, Kd=0.5 Gp(z) d Vo

Gp(s)
L=1uH, C=1620uF,
Rc=0.004 ohm ZOH Kd
Ts
1.62x10-5 s + 2.5 Hc
Kd.Gp(s) = -------------------------------------
1.685x10-9 s2 + 1.648x10-5 s + 1 Vo(n)
U(n) E(n)
ZOH(s) = (1 – e-sTs )/s Gc(z) +
Hc = e-sTd
Vref
Discrete Plant Model,
Gp(z) = Z{ZOH(s).Kd.Gp(s).Hc}
Gp1(z) = (0.0494z - 0.0261)/(z2 - 1.952 z + 0.962), [Td=0, Hc = 1]
11
Use Matlab SISOTOOL for Gp1(z), and design Gc2(z)
Discrete System Bode Plot,

2 Pole 2 Zero Type Controller,
Gp1(z)*Gc2(z)
(Td=0)
BW = 27.9kHz, PM = 61.6 deg, GM = 9dB Gp1(z)*Gc2(z)
Settling Time(1%) < 56 uSec
14.87 z^2 - 26.91 z + 12.16

Gc2(z) = -------------------------------------
z^2 - 1.473 z + 0.4731
12
Effect of Computation Delay
Bode Plot (Matlab)
Plant with computation delay [Td = 0.5Ts],
Gp2(z) = (0.022z^2+0.017z - 0.158)/z(z^2 - 1.952 z + 0.962),
Controller with no delay compensation,
Gc2(z)=(14.87 z^2 - 26.91 z + 12.16)/(z^2 - 1.473 z + 0.4731 )
Phase Lag,
Gp2(z)*Gc2(z) Hc = -ωTd
= -360fTd
Loss of PM from
(Gp1*Gc2) to (Gp2*Gc2)
= 61.6-41
= 20.6 deg
BW = 26.9kHz, PM = 41 deg, GM = 7.46dB Hc = 360(26900)(2uS)

= 19.37 deg
13
Bode Plot (Measured)
Gp2(z)*Gc2(z)
BW = 22.45kHz, PM = 40 deg, GM = 10.7dB
14
Transient Response (Fpwm = 250KHz)
Gp2(z)*Gc2(z)
15
Effect of Computation Delay
Bode Plot (Matlab)
Plant with increased computation delay [Td = 2.0Ts],
Gp3(z) = (0.022z^2+0.017z - 0.159)/z^2(z^2 - 1.954 z + 0.963),
Controller with no delay compensation,
Gc2(z)=(14.87 z^2 - 26.91 z + 12.16)/(z^2 - 1.473 z + 0.4731 )
2 Pole 2 Zero Type Controller Phase Lag,

Gp3(z)*Gc2(z) Hc = -ωTd
= -360fTd
Loss of PM from
(Gp1*Gc2) to Gp3*Gc2
= 61.6 – (-19)
= 80.6 deg
BW = 27.9kHz, PM = -19.0 deg, GM = -2.22dB,
Unstable Loop.
Hc = 360(27900)2(4uS)
= 80.35 deg
16
Unstable System, Uncompensated for Computation Delay
Gp3(z)*Gc2(z)
17
Redesigned Controller with Delay Compensation
Bode plot (Matlab)
3 Pole 3 Zero Type Controller

Gp3(z)*Gc3(z)
BW = 16.1kHz, PM = 46.4 deg, GM = 3.77dB
14.4 z^3 – 31.1 z^2 + 20.1 z – 3.376

Gc3(z)=U/E= -------------------------------------------------
z^3 - 1.235 z^2 + 0.2362 z - 0.00115 18
Redesigned Controller with Delay Compensation
Bode plot (Measured)
Gp3(z)*Gc3(z)
BW = 15.28kHz, PM = 41.76 deg, GM = 3.4dB
19
System Compensated for Computation Delay
Gp3(z)*Gc3(z)
20
Voltage Mode Control: Computation Flow, Benchmark Results
14.87 z2 – 26.91 z + 12.16 14.87 – 26.91 z -1 + 12.16 z -2

Gc(z) = U/E = ------------------------------------ = -------------------------------------------
z2 - 1.473 z + 0.4731 1 – 1.473 z -1 + 0.4731 z -2
U (n) = a 2 × U (n − 2) + a1× U (n − 1) + b2 × E (n − 2) + b1× E (n − 1) + b0 × E (n )
Usat ( n ) = min ≤ U ( n ) ≤ max Vref

Dprd
Dprd = Usat ( n ) × PWMPRD Vo Gc(z)
TMS320C28x=150MHz
(32-bit implementation)
Sampling Freq Available
(KHz) Cycles Overhead Cycles Cycles/loop Number of Loops
250 600 41 559 26 21.5
500 300 41 259 26 9.96 21

Sampling Frequency (fs) Selection
Hc = -ωTd = -360fTd = -360f(kTs) = -360k /(fs/f), [ k = Td /Ts]

fc = crossover frequency
120
fs/fc=5
100 fs/fc=10
fs/fc=12.5
Phase Lag (Hc)
80
fs/fc=20
60
40
20
0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
K
Computation Delay per unit Ts, (Td /Ts)
22
Sampling Frequency (fs) Selection
fs = 12.5*fc
fs = 20*fc
fs = 30*fc
23
PWM Resolution & Limit Cycle
DSP Clock Freq = 150MHz, fpwm = 250kHz, ∆Vpwm Vo
PWM Duty Ratio Resolution
= 1/(150M/250k) = 1/600 = 0.167% Vin
Sense
ADC resolution = 10bits, Vo = 2V (max), PWM circuit
Vo Sensing Resolution ∆Vad = 2V/1024 = 1.95mV
A/D
For Vin = 5V, Applied Volt Resolution ∆Vpwm1 = 5V/600 = 8.33mV,
For Vin = 2V, Applied Volt Resolution ∆Vpwm2 = 2V/600 = 3.33mV, ∆Vad
∆Vpwm1 > ∆Vad, ∆Vpwm2 ≈ ∆Vad,

=> Limit Cycle => Negligible Limit Cyc.
Vin = 5V
Vin = 2V
Vo = 1.6V
Vo = 0.8V
24

DSP Control Loop Design

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DSP based Digital Control Design

for DC-DC Switch Mode

Context spare Back-ground

Vin=5.0, RL=0.1, Kd=0.5, d Vo

14.3 s^2 + 651400 s + 7.2e009

BW = 25.2kHz, PM = 53.1 deg, GM = 11.3dB

Transient Response (Fpwm = 250KHz),

Discrete System Bode Plot, Tustin Controller,

BW = 25.4kHz, PM = 53.6 deg, GM = 11.2dB

Comp Delay Model TMS320F2810 Vref

Vin=5.0, RL=0.1, Kd=0.5 Gp(z) d Vo

Discrete System Bode Plot,

BW = 27.9kHz, PM = 61.6 deg, GM = 9dB Gp1(z)*Gc2(z)

Settling Time(1%) < 56 uSec

14.87 z^2 - 26.91 z + 12.16

BW = 26.9kHz, PM = 41 deg, GM = 7.46dB Hc = 360(26900)(2uS)

BW = 22.45kHz, PM = 40 deg, GM = 10.7dB

2 Pole 2 Zero Type Controller Phase Lag,

3 Pole 3 Zero Type Controller

BW = 16.1kHz, PM = 46.4 deg, GM = 3.77dB

14.4 z^3 – 31.1 z^2 + 20.1 z – 3.376

BW = 15.28kHz, PM = 41.76 deg, GM = 3.4dB

14.87 z2 – 26.91 z + 12.16 14.87 – 26.91 z -1 + 12.16 z -2

U (n) = a 2 × U (n − 2) + a1× U (n − 1) + b2 × E (n − 2) + b1× E (n − 1) + b0 × E (n )

Usat ( n ) = min ≤ U ( n ) ≤ max Vref

250 600 41 559 26 21.5

500 300 41 259 26 9.96 21

Hc = -ωTd = -360fTd = -360f(kTs) = -360k /(fs/f), [ k = Td /Ts]

∆Vpwm1 > ∆Vad, ∆Vpwm2 ≈ ∆Vad,

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