Cmos Electronic PDF

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CMOS ELECTRONICS
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IEEE Press
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Stamatios V. Kartalopoulos, Editor in Chief
M. Akay M. E. El-Hawary F. M. B. Periera

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Technical Reviewers
Cecilia Metra, University of Bologna, Italy
Antonio Rubio, Polytechnical University of Catalonia, Barcelona, Spain
Robert Aitken, Artisan Corp., San Jose, California
Robert Madge, LSI Logic Corp., Gresham, Oregon
Joe Clement, William Filler, Duane Bowman, and David Monroe, Sandia National
Laboratories, Albuquerque, New Mexico
Jose Luis Rosselló and Sebastia Bota, University of the Balearic Islands, Spain
Harry Weaver and Don Neamen, Univerisity of New Mexico, Albuquerque, New Mexico
Manoj Sachdev, University of Waterloo, Ontario, Canada
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CMOS ELECTRONICS
HOW IT WORKS, HOW IT FAILS
JAUME SEGURA
Universitat de les Illes Balears
CHARLES F. HAWKINS
University of New Mexico
IEEE Computer Society, Sponsor
IEEE PRESS
A JOHN WILEY & SONS, INC., PUBLICATION

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Copyright © 2004 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
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10 9 8 7 6 5 4 3 2 1
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A Mumara, a la seva memòria, i al meu Pare.

To Patricia, Pau, and Andreu for love, for sharing
life, and for happiness
—Jaume Segura
To Jan, who has shared the mostly ups, the some-

times downs, and the eternal middle road of life.
To our children, Andrea, David, and Shannon,
their spouses, and the grandchildren who are fol-
lowing, I hope this work will be a small record of
an intense period in which all of you were close
to my thoughts.
—Charles F. Hawkins
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CONTENTS
Foreword xiii
Preface xv
PART I CMOS FUNDAMENTALS
1 Electrical Circuit Analysis 3

1.1 Introduction 3
1.2 Voltage and Current Laws 3
1.2.1 Kirchhoff’s Voltage Law (KVL) 5
1.2.2 Kirchhoff’s Current Law (KCL) 7
1.3 Capacitors 17
1.3.1 Capacitor Connections 19
1.3.2 Capacitor Voltage Dividers 20
1.3.3 Charging and Discharging Capacitors 22
1.4 Diodes 24
1.4.1 Diode Resistor Circuits 25
1.4.2 Diode Resistance 28
1.5 Summary 29
Bibliography 29
Exercises 29
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viii CONTENTS
2 Semiconductor Physics 37
2.1 Semiconductor Fundamentals 37
2.1.1 Metals, Insulators, and Semiconductors 37
2.1.2 Carriers in Semiconductors: Electrons and Holes 39
2.1.3 Determining Carrier Population 41
2.2 Intrinsic and Extrinsic Semiconductors 42
2.2.1 n-Type Semiconductors 42
2.2.2 p-Type Semiconductors 44
2.3 Carrier Transport in Semiconductors 44
2.3.1 Drift Current 45
2.3.2 Diffusion Current 46
2.4 The pn Junction 46
2.5 Biasing the pn Junction: I–V Characteristics 48
2.5.1 The pn Junction under Forward Bias 49
2.5.2 The pn Junction under Reverse Bias 49
2.6 Parasitics in the Diode 50
2.7 Summary 51
Bibliography 51
Exercises 52
3 MOSFET Transistors 53
3.1 Principles of Operation: Long-Channel Transistors 53
3.1.1 The MOSFET as a Digital Switch 54
3.1.2 Physical Structure of MOSFETs 55
3.1.3 Understanding MOS Transistor Operation: 56
A Descriptive Approach
3.1.4 MOSFET Input Characteristics 59
3.1.5 nMOS Transistor Output Characteristics 60
3.1.6 pMOS Transistor Output Characteristics 70
3.2 Threshold Voltage in MOS Transistors 77
3.3 Parasitic Capacitors in MOS Transistors 79
3.3.1 Non-Voltage-Dependent Internal Capacitors 79
3.3.2 Voltage-Dependent Internal Capacitors 80
3.4 Device Scaling: Short-Channel MOS Transistors 81
3.4.1 Channel Length Modulation 83
3.4.2 Velocity Saturation 83
3.4.3 Putting it All Together: A Physically Based Model 85
3.4.4 An Empirical Short-Channel Model for Manual Calculations 87
3.4.5 Other Submicron Effects 91
3.5 Summary 94
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CONTENTS ix
References 94
Exercises 94
4 CMOS Basic Gates 99

4.1 Introduction 99
4.2 The CMOS Inverter 100
4.2.1 Inverter Static Operation 100
4.2.2 Dynamic Operation 107
4.2.3 Inverter Speed Property 109
4.2.4 CMOS Inverter Power Consumption 113
4.2.5 Sizing and Inverter Buffers 116
4.3 NAND Gates 118
4.4 NOR Gates 120
4.5 CMOS Transmission Gates 122
4.6 Summary 123
Bibliography 123
Exercises 123
5 CMOS Basic Circuits 127

5.1 Combinational logic 127
5.1.1 CMOS Static Logic 127
5.1.2 Tri-State Gates 131
5.1.3 Pass Transistor Logic 132
5.1.4 Dynamic CMOS Logic 133
5.2 Sequential Logic 137
5.2.1 Register Design 137
5.2.2 Semiconductor Memories (RAMs) 139
5.3 Input–Output (I/O) Circuitry 142
5.3.1 Input Circuitry: Protecting ICs from Outside Environment 143
5.3.2 Input Circuitry: Providing “Clean” Input Levels 144
5.3.3 Output Circuitry, Driving Large Loads 145
5.3.4 Input–Output Circuitry: Providing Bidirectional Pins 146
5.4 Summary 146
References 147
Exercises 148
PART II FAILURE MODES, DEFECTS, AND TESTING OF CMOS ICs
6 Failure Mechanisms in CMOS IC Materials 153

6.1 Introduction 153
6.2 Materials Science of IC Metals 154
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6.3 Metal Failure Modes 159

6.3.1 Electromigration 159
6.3.2 Metal Stress Voiding 169
6.3.3 Copper Interconnect Reliability 176
6.4 Oxide Failure Modes 178
6.4.1 Oxide Wearout 180
6.4.2 Hot-Carrier Injection (HCI) 185
6.4.3 Defect-Induced Oxide Breakdown 191
6.4.4 Process-Induced Oxide Damage 191
6.4.5 Negative Bias Temperature Instability (NBTI) 191
6.5 Conclusion 192
Acknowledgments 192
Bibliography 192
Exercises 195
7 Bridging Defects 199

7.2 Bridges in ICs: Critical Resistance and Modeling 200
7.2.1 Critical Resistance 200
7.2.2 Fault models for Bridging Defects on Logic Gate Nodes (BF) 207
7.3 Gate Oxide Shorts (GOS) 208
7.3.1 Gate Oxide Short Models 209
7.4 Bridges in Combinational Circuits 214
7.4.1 Nonfeedback Bridging Faults 214
7.4.2 Feedback Bridging Faults 214
7.5 Bridges in Sequential Circuits 217
7.5.1 Bridges in Flip-Flops 217
7.5.2 Semiconductor Memories 218
7.6 Bridging Faults and Technology Scaling 218
7.7 Conclusion 219
References 219
Exercises 220
8 Open Defects 223

8.2 Modeling Floating Nodes in ICs 224
8.2.1 Supply–Ground Capacitor Coupling in Open Circuits 224
8.2.2 Effect of Surrounding Lines 226
8.2.3 Influence of the Charge from MOSFETs 228
8.2.4 Tunneling Effects 229
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8.2.5 Other Effects 232

8.3 Open Defect Classes 232
8.3.1 Transistor-On Open Defect 232
8.3.2 Transistor Pair-On and Transistor Pair-On / Off 234
8.3.3 The Open Delay Defect 236
8.3.4 CMOS Memory Open Defect 237
8.3.5 Sequential Circuit Opens 238
8.4 Summary 239
References 239
Exercises 240
9 Parametric Failures 243

9.2 Intrinsic Parametric Failures 246
9.2.1 Transistor Parameter Variation 246
9.2.2 Impact on Device Intrinsic Electrical Properties 249
9.2.3 Line Interconnect Intrinsic Parameter Variation 252
9.2.4 Temperature Effect 255
9.3 Intrinsic Parametric Failure Impact on IC Behavior 256
9.3.1 Interconnect Models 257
9.3.2 Noise 259
9.3.3 Delay 264
9.4 Extrinsic Parametric Failure 271
9.4.1 Extrinsic Weak Interconnect Opens 271
9.4.2 Extrinsic Resistive Vias and Contacts 271
9.4.3 Extrinsic Metal Mousebites 272
9.4.4 Extrinsic Metal Slivers 275
9.5 Conclusion 275
References 276
Exercises 279
10 Defect-Based Testing 281

10.2 Digital IC Testing: The Basics 282
10.2.1 Voltage-Based Testing 283
10.2.2 Speed Testing 288
10.2.3 Current-Based Testing 289
10.2.4 Comparative Test Methods Studies 292
10.3 Design for Test 293
10.3.1 Scan Design 294
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xii CONTENTS
10.3.2 BIST 296

10.3.3 Special Test Structures for Next Levels of Assembly 299
10.4 Defect-Based Testing (DBT) 300
10.4.1 Bridge Defects 301
10.4.2 Opens 304
10.4.3 DBT Summary 307
10.5 Testing Nanometer ICs 309
10.5.1 Nanometer Effects on Testing 311
10.5.2 Voltage-Based Testing 314
10.5.3 Current-Based Testing 315
10.5.4 Delay Testing Using Statisitical Timing Analysis 318
10.5.5 Low-VDD Testing 318
10.5.6 Multiparameter Testing 320
10.6 Conclusions 322
Bibliography 322
References 322
Exercises 326
Appendix A Solutions to Self-Exercises 331

A.1 Chapter 1 331
A.2 Chapter 3 334
A.3 Chapter 4 335
A.4 Chapter 5 336
A.5 Chapter 6 336
A.6 Chapter 7 337
A.8 Chapter 8 337
A.8 Chapter 10 337
Index 339
About the Authors 347

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FOREWORD
Advances in electronics have followed Moore’s Law, by scaling feature sizes every gener-
ation, doubling transistor integration capacity every two years, resulting in complex chips
of today—a treadmill that we take for granted. No doubt that design complexity has
grown tremendously and therefore gets tremendous attention, but often overlooked is the
technology underlying reliability, and cost-effective test and product engineering of these
complex chips. This is becoming especially crucial as we transition from yesterday’s mi-
cro-electronics to today’s nano-electronics.
This book, CMOS Electronics: How It Works, How It Fails, written by Professor Segu-
ra and Professor Hawkins, addresses just that—the technology underlying failure analysis,
testing, and product engineering. The book starts with fundamental device physics, de-
scribes how MOS transistors work, how logic circuits are built, and then eases into failure
mechanisms of these circuits. Thus the reader gets a very clear picture of failure mecha-
nisms, how to detect them, and how to avoid them. The book covers the latest advances in
failure analysis and test and product engineering, such as defects due to bridges, opens,
and parametrics, and formulates test strategies to observe these defects in defect-based
testing.
As technology progresses with even smaller geometries, you will have to comprehend
test and product engineering upfront in the design. That is why this book is a refreshing
change as it introduces design and test together.
I would like to thank Professor Segura and Professor Hawkins for giving me an oppor-
tunity to read a draft of this book; I surely enjoyed it, learned a lot from it, and I am sure
that you the readers will find it rewarding, too.
SHEKHAR BORKAR
Intel Fellow
Director, Circuit Research
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PREFACE
If you find the mysteries and varieties of integrated circuit failures challenging, then this
book is for you. It is also for you if you work in the CMOS integrated circuits (IC) indus-
try, but admit to knowing little about the electronics itself or the important electronics of
failure. The goal of this book is knowledge of the electronic behavior that failing CMOS
integrated circuits exhibit to customers and suppliers. The emphasis is on electronics at
the transistor circuit level, to gain a deeper understanding of why failing circuits act as
they do.
There are two audiences for this book. The first are those in the industry who have had
little or no instruction in CMOS electronics, but are surrounded by the electronic symp-
toms that permeate a CMOS customer or supplier. You may have a physics, chemical en-
gineering, chemistry, or biology education and need to understand the circuitry that you
help manufacture. Part I of the book is designed to bring you up to speed in preparation
for Part II, which is an analysis of the nature of CMOS failure mechanisms. The second
audience is the electrical engineering professional or student who will benefit from a sys-
tematic description of the electronic behavior mechanisms of abnormal circuits. Part II
describes the material reliability failures, bridge and open circuit defects, and the subtle
parametric failures that are plaguing advanced technology ICs. The last chapter assembles
this information to implement a defect-based detection strategy used in IC testing. Five
key groups should benefit from this approach: test engineers, failure analysts, reliability
engineers, yield improvement engineers, and designers. Managers and others who deal
with IC abnormalities will also benefit.
CMOS manufacturing environments are surrounded with symptoms that can indicate
serious test, design, yield, or reliability problems. Knowledge of how CMOS circuits work
and how they fail can rapidly guide you to the nature of a problem. Is the problem related
to test, design, reliability, failure analysis, yield–quality issues, or problems that may oc-
xv
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xvi PREFACE
cur during characterization of a product? Is the symptom an outcome of random defects,

or is it systematic, with a common failure signature? Is the defect a bridging problem, an
open circuit problem, or a subtle speed-related problem?
We know how bridge and open circuit defects cause performance degradation or fail-
ure, and we are closing in on a complete picture of the IC failures that depend upon para-
metric properties of the circuit environment. These properties include temperature and
power supply values. There are cost savings when you can shorten the time to diagnosis
and intelligently plan test strategies that minimize test escapes. Rapid insights into abnor-
mal electronic behavior shorten the time to diagnosis and also allow more deterministic
planning of test strategies. Determination of root cause of failure is much more efficient if
you can isolate one of the failure modes from their electronic properties early in the
process.
Circuit abnormalities are a constant concern, and the ability to rapidly estimate the de-
fect type is the first step: namely, what are we looking for? Or when planning test strate-
gies, what test methods should we use to match against particular defects? The effect of
the many varieties of defects on circuit operation is analyzed in the book with numerical
examples. The early portion of the book assumes little knowledge of circuits and transis-
tors, but builds to a mature description of the electronic properties of defects in Part II.
The book adopts a self-learning style with many problems, examples, and self-exercises
Part I (Chapters 1–5) describes how defect-free CMOS circuits work and Part II
(Chapters 6–10) describes CMOS circuit failure properties and mechanisms. Chapter 1
begins with Ohm’s and Kirchhoff’s laws, emphasizing circuit analysis by inspection, and
concludes with an analysis of diodes and capacitors. Chapter 2 introduces semiconductor
physics and how that knowledge leads to transistor operation in Chapter 3. Chapter 3 has
abundant problem-solving examples to gain confidence with transistor operation and their
interplay when connected to resistors. Chapter 4 builds to transistor circuit operation with
two and four transistors such as CMOS inverters, NAND and NOR logic gates, and trans-
mission gates. Chapter 5 shows how CMOS transistor circuits are synthesized from
Boolean algebra equations, and also compares different design styles.
Part II builds on the foundation of how good, or defect-free, CMOS circuits operate
and extends that to circuit failures. Chapter 6 examines why IC metal and oxide materials
fail in time, producing the dreaded reliability failures. Chapters 7–9 analyze the electronic
failure properties of bridge, open, and parametric variation to formulate a test strategy
that matches suspected defects to a detection method sensitive to that defect type. Chapter
10 brings all of this together in a test engineering approach called defect-based testing
(DBT). The links to test, failure analysis, and reliability are emphasized.
The math used in CMOS electronics varies from simple algebraic expressions to com-
plex physical and timing models whose solutions are suitable only for computers. Fortu-
nately, algebraic equations serve most needs when we manually analyze a circuit’s current
and voltage response in the presence of a defect. A few simple calculus equations appear,
particularly for introducing timing and power relations. A goal is to understand the subtle
pass/fail operation or loss of noise margin for defective circuits.
The rapid pace of CMOS technologies influenced these electronic descriptions. Virtu-
ally all modern IC transistors are now short-channel devices with different model equa-
tions than their long-channel transistor predecessors. Although first-order models for
short-channel transistors may at first seem simpler than long-channel equivalents, we
found that this simplicity bred inaccuracy and clumsiness when used for manual transistor
circuit analysis. We describe these problems and one approach for analyzing short-chan-
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PREFACE xvii
nel devices in Chapter 3, but chose long-channel transistor models to illustrate how to cal-
culate voltages and currents. It was the only expedient way to give readers the intuitive in-
sights into the nature of transistors when these devices are subjected to various voltage bi-
ases.
CMOS field effect transistors do not exist in isolation in the IC. Parasitic bipolar tran-
sistors have a small but critical role in the destructive CMOS latchup condition, in electro-
static discharge (ESD) protection circuits, and in some parasitic defect structures. Howev-
er, we chose to contain the size of the book by only including a brief description of bipolar
transistors in sections where they are mentioned.
The knowledge poured into this book came from several sources. The authors teach
electronics at their universities, and much data and knowledge were taken from collabora-
tive work done at Sandia National Labs and at Intel Corporation. We are indebted to many
persons in our defect electronics education and particularly acknowledge those with
whom we worked closely. These include Jerry Soden and Ed Cole of Sandia National
Labs, Antonio Rubio of the Polytechnical University of Catalonia, Jose Luis Rosselló of
the University of the Balearic Islands, Alan Righter of Analog Devices, and Ali Ke-
shavarzi, who hosted each of us on university sabbaticals at the Intel facilities in Portland,
Oregon and Rio Rancho, New Mexico.
Each chapter had from one to three reviewers. All reviewers conveyed a personal feel-
ing of wanting to make this a better book. These persons are: Sebastià Bota of the Univer-
sity of Barcelona, Harry Weaver and Don Neamen of the University of New Mexico, Jose
Luis Rosselló of the University of the Balearic Islands, Antonio Rubio of the Polytechnic
University of Catalonia, Manoj Sachdev of the University of Waterloo, Joe Clement, Dave
Monroe, and Duane Bowman of Sandia National Labs, Cecilia Metra of the University of
Bologna, Bob Madge of LSI Logic Corp., and Rob Aitken of Artisan Corp. We also thank
editing and computer support from Gloria Ayuso of the University of the Balearic Islands
and Francesc Segura from DMS, Inc.
The seminal ideas and original drafts for the book began in the Spanish city of Palma
de Mallorca on the Balearic Islands. Over the next four years, about two-thirds of the
book was written in Mallorca with the remainder at the University of New Mexico in Al-
buquerque in the United States. Countless editorial revisions occurred, with memorable
ones on long flights across the Atlantic, in the cafes of the ancient quarter of Palma, and in
the coffee shops around the University of New Mexico, where more than four centuries
earlier, Spanish farmers grew crops.
The book is intended to flow easily for those without an EE degree and can be a one-
semester course in a university. We found from class teaching with this material that the
full book is suitable for senior or graduate students with non-EE backgrounds. The EE
students can skip or review Chapters 1–2, and go directly to Chapters 3–10. Chapters 3–5
are often taught at the undergraduate EE level, but we found that the focus on CMOS
electronics here is more than typically taught. The style blends the descriptive portions of
the text with many examples and exercises to encourage self-study. The learning tools are
a pad of paper, pen, pocket calculator, isolated time, and motivation to learn. The rewards
are insights into the deep mysteries of CMOS IC behavior. For additional material related
to this book, visit http://omaha.uib.es/cmosbook/index.html
JAUME SEGURA
CHARLES F. HAWKINS
January 2004
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PART I
CMOS FUNDAMENTALS
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CHAPTER 1
ELECTRICAL CIRCUIT ANALYSIS
1.1 INTRODUCTION
We understand complex integrated circuits (ICs) through simple building blocks. CMOS
transistors have inherent parasitic structures, such as diodes, resistors, and capacitors,
whereas the whole circuit may have inductor properties in the signal lines. We must know
these elements and their many applications since they provide a basis for understanding
transistors and whole-circuit operation.
Resistors are found in circuit speed and bridge-defect circuit analysis. Capacitors are
needed to analyze circuit speed properties and in power stabilization, whereas inductors
introduce an unwanted parasitic effect on power supply voltages when logic gates change
state. Transistors have inherent diodes, and diodes are also used as electrical protective el-
ements for the IC signal input/output pins. This chapter examines circuits with resistors,
capacitors, diodes, and power sources. Inductance circuit laws and applications are de-
scribed in later chapters. We illustrate the basic laws of circuit analysis with many exam-
ples, exercises, and problems. The intention is to learn and solve sufficient problems to
enhance one’s knowledge of circuits and prepare for future chapters. This material was se-
lected from an abundance of circuit topics as being more relevant to the later chapters that
discuss how CMOS transistor circuits work and how they fail.
1.2 VOLTAGE AND CURRENT LAWS
Voltage, current, and resistance are the three major physical magnitudes upon which we
will base the theory of circuits. Voltage is the potential energy of a charged particle in an
electric field, as measured in units of volts (V), that has the physical units of Newton ·
CMOS Electronics: How It Works, How It Fails. By Jaume Segura and Charles F. Hawkins 3
ISBN 0-471-47669-2 © 2004 Institute of Electrical and Electronics Engineers, Inc.
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4 CHAPTER 1 ELECTRICAL CIRCUIT ANALYSIS
m/coulomb. Current is the movement of charged particles and is measured in coulombs

per second or amperes (A). Electrons are the charges that move in transistors and inter-
connections of integrated circuits, whereas positive charge carriers are found in some spe-
cialty applications outside of integrated circuits.
Three laws define the distribution of currents and voltages in a circuit with resistors:
Kirchhoff’s voltage and current laws, and the volt–ampere relation for resistors defined by
Ohm’s law. Ohm’s law relates the current and voltage in a resistor as
V=R×I (1.1)
This law relates the voltage drop (V) across a resistor R when a current I passes through it.
An electron loses potential energy when it passes through a resistor. Ohm’s law is impor-
tant because we can now predict the current obtained when a voltage is applied to a resis-
tor or, equivalently, the voltage that will appear at the resistor terminals when forcing a
current.
An equivalent statement of Ohm’s law is that the ratio of voltage applied to a resistor to
subsequent current in that resistor is a constant R = V/I, with a unit of volts per ampere
called an ohm (⍀). Three examples of Ohm’s law in Figure 1.1 show that any of the three
variables can be found if the other two are known. We chose a rectangle as the symbol for
a resistor as it often appears in CAD (computer-aided design) printouts of schematics and
it is easier to control in these word processing tools.
The ground symbol at the bottom of each circuit is necessary to give a common refer-
ence point for all other nodes. The other circuit node voltages are measured (or calculat-
ed) with respect to the ground node. Typically, the ground node is electrically tied through
a building wire called the common to the voltage generating plant wiring. Battery circuits
use another ground point such as the portable metal chassis that contains the circuit. No-
tice that the current direction is defined by the positive charge with respect to the positive
terminal of a voltage supply, or by the voltage drop convention with respect to a positive
charge. This seems to contradict our statements that all current in resistors and transistors
is due to negative-charge carriers. This conceptual conflict has historic origins. Ben
Franklin is believed to have started this convention with his famous kite-in-a-thunder-
storm experiment. He introduced the terms positive and negative to describe what he
called electrical fluid. This terminology was accepted, and not overturned when we found
out later that current is actually carried by negative-charge carriers (i.e., electrons). Fortu-
nately, when we calculate voltage, current, and power in a circuit, a positive-charge hy-
pothesis gives the same results as a negative-charge hypothesis. Engineers accept the pos-
itive convention, and typically think little about it.
+ + 6 kΩ +
10 nA 1 MΩ I BB 4 µA R
V BB 3V
- - 100 mV-
VBB = (10 nA)(1 M⍀) = 10 mV IBB = 3 V/6 k⍀ = 500 ␮A R = 100 mV/4 ␮A = 25 k⍀
Figure 1.1. Ohm’s law examples. The battery positive terminal indicates where the positive charge
exits the source. The resistor positive voltage terminal is where positive charge enters.
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1.2 VOLTAGE AND CURRENT LAWS 5
An electron loses energy as it passes through a resistance, and that energy is lost as
heat. Energy per unit of time is power. The power loss in an element is the product of volt-
age and current, whose unit is the watt (W):
P = VI (1.2)
1.2.1 Kirchhoff’s Voltage Law (KVL)

This law states that “the sum of the voltage drops across elements in a circuit loop is
zero.” If we apply a voltage to a circuit of many serial elements, then the sum of the volt-
age drops across the circuit elements (resistors) must equal the applied voltage. The KVL
is an energy conservation statement allowing calculation of voltage drops across individ-
ual elements: energy input must equal energy dissipated.
Voltage Sources. An ideal voltage source supplies a constant voltage, no matter the
amount of current drawn, although real voltage sources have an upper current limit. Fig-
ure 1.2 illustrates the KVL law where VBB represents a battery or bias voltage source. The
polarities of the driving voltage VBB and resistor voltages are indicated for the clockwise
direction of the current.
Naming V1 the voltage drop across resistor R1, V2 that across resistor R2, and, subse-
quently, V5 for R5, the KVL states that
VBB = V1 + V2 + V3 + V4 + V5 (1.3)
Note that the resistor connections in Figure 1.2 force the same current IBB through all re-
sistors. When this happens, i.e., when the same current is forced through two or more re-
sistors, they are said to be connected in series. Applying Ohm’s law to each resistor of Fig-
ure 1.2, we obtain Vi = Ri × IBB (where i takes any value from 1 to 5). Applying Ohm’s law
to each voltage drop at the right-hand side of Equation (1.3) we obtain
VBB = R1IBB + R2IBB + R3IBB + R4IBB + R5IBB

= (R1 + R2 + R3 + R4 + R5)IBB (1.4)
= ReqIBB
where Req = R1+ R2+ R3 + R4 + R5. The main conclusion is that when a number of resistors
are connected in series, they can be reduced to an equivalent single resistor whose value is
the sum of the resistor values connected in series.
R1 R2
R3
+ + V1 - + V2 - +
VBB IBB V3
- - V5 + - V4 + -
R5 R4
Figure 1.2. KVL seen in series elements.

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왎 EXAMPLE 1.1
Figure 1.3(a) shows a 5 V source driving two resistors in series. The parameters
are referenced to the ground node. Show that the KVL holds for the circuit.
RA = 12 kΩ
156.25 µA
5V 5V 32 kΩ
B 156.25 µA
RB = 20 kΩ
(a) (b)
Figure 1.3. (a) Circuit illustrating KVL. (b) Equivalent circuit. The power supply cannot
tell if the two series resistors or their equivalent resistance are connected to the power
source terminals.
The voltage drop across RA is
VA = RA × I = 12 k⍀ × 156.25 ␮A = 1.875 V
Similarly, the voltage across RB is 3.125 V. The applied 5 V must equal the series
drops across the two resistors or 1.875 V + 3.125 V = 5 V. The last sentence is a
verification of the KVL. 왎
The current in Figure 1.3(a) through the 12 k⍀ in series with a 20 k⍀ resistance is

equal to that of a single 32 k⍀ resistor (Figure 1.3(b)). The voltage across the two resistors
in Figure 1.3(a) is 5 V and, when divided by the current (156.25 ␮A), gives an equivalent
series resistance of (5 V/156.25 ␮A) = 32 k⍀. Figure 1.3(b) is an equivalent reduced cir-
cuit of that in Figure 1.3(a).
Current Sources. We introduced voltage power sources first since they are more fa-
miliar in our daily lives. We buy voltage batteries in a store or plug computers, appliances,
or lamps into a voltage socket in the wall. However, another power source exists, called a
current source, that has the property of forcing a current out of one terminal that is inde-
pendent of the resistor load. Although not as common, you can buy current power sources,
and they have important niche applications.
Current sources are an integral property of transistors. CMOS transistors act as current
sources during the crucial change of logic state. If you have a digital watch with a micro-
controller of about 200k transistors, then about 5% of the transistors may switch during a
clock transition, so 10k current sources are momentarily active on your wrist.
Figure 1.4 shows a resistive circuit driven by a current source. The voltage across the
current source can be calculated by applying Ohm’s law to the resistor connected between
the current source terminals. The current source as an ideal element provides a fixed cur-
rent value, so that the voltage drop across the current source will be determined by the el-
ement or elements connected at its output. The ideal current source can supply an infinite
voltage, but real current sources have a maximum voltage limit.
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Vo = 400 mV
1 µA 400 kΩ
Figure 1.4. A current source driving a resistor load.
1.2.2 Kirchhoff’s Current Law (KCL)

The KCL states that “the sum of the currents at a circuit node is zero.” Current is a mass
flow of charge. Therefore the mass entering the node must equal the mass exiting it. Fig-
ure 1.5 shows current entering a node and distributed to three branches. Equation (1.5) is
a statement of the KCL that is as essential as the KVL in Equation (1.3) for computing
circuit variables. Electrical current is the amount of charge (electrons) Q moving in time,
or dQ/dt. Since current itself is a flow (dQ/dt), it is grammatically incorrect to say that
“current flows.” Grammatically, charge flows, but current does not.
I0 = I1 + I2 + I3 (1.5)
The voltage across the terminals of parallel resistors is equal for each resistor, and the
currents are different if the resistors have different values. Figure 1.6 shows two resis-
tors connected in parallel with a voltage source of 2.5 V. Ohm’s law shows a different
current in each path, since the resistors are different, whereas all have the same voltage
drop.
2.5 V
IA = ᎏᎏ = 25 ␮A
100 k⍀
(1.6)
2.5 V
IB = ᎏᎏ = 16.675 ␮A
150 k⍀
Applying Equation (1.5), the total current delivered by the battery is
IBB = IA + IB = 25 ␮A + 16.67 ␮A = 41.67 ␮A (1.7)
I0
I1 I2 I3
Figure 1.5. KCL and its current summation at a node.

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VBB
RA RB
IBB
100 kΩ 150 kΩ
2.5 V
Figure 1.6. Parallel resistance example.
and
VBB 2.5 V
ᎏ = ᎏᎏ = 60 k⍀ (1.8)
IBB 41.67 ␮A
Notice that the sum of the currents in each resistor branch is equal to the total current
from the power supply, and that the resistor currents will differ when the resistors are un-
equal. The equivalent parallel resistance Req in the resistor network in Figure 1.6 is VBB =
Req(IA + IB). From this expression and using Ohm’s law we get
VBB
ᎏ = IA + IB
Req
VBB
IA = ᎏ (1.9)
RA
VBB
IB = ᎏ
RB
and
VBB VBB VBB

ᎏ=ᎏ+ᎏ
Req RA RB
1 1 1
ᎏ=ᎏ+ᎏ (1.10)
Req RA RB
1 1
Req = ᎏ = ᎏᎏᎏ = 60 k⍀
1 1 1 1
ᎏ ᎏ + ᎏᎏ ᎏᎏ + ᎏᎏ
RA RB 100 k⍀ 150 k⍀
This is the expected result from Equation (1.8). Req is the equivalent resistance of RA and
RB in parallel, which is notationly expressed as Req = RA||RB. In general, for n resistances
in parallel,
1
Req = (R1||R2|| · · · ||Rn) = ᎏᎏᎏ (1.11)
1 1 1
ᎏᎏ + ᎏᎏ + · · · + ᎏᎏ
R1 R2 Rn
The following examples and self-exercises will help you to gain confidence on the con-
cepts discussed.
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Self-Exercise 1.1
Calculate V0 and the voltage drop Vp across the parallel resistors in Figure 1.7.
Hint: Replace the 250 k⍀ and 180 k⍀ resistors by their equivalent resistance and
apply KVL to the equivalent circuit.
250 kΩ
Vo
500 µA 180 kΩ 3.3 kΩ
Figure 1.7.
Self-Exercise 1.2
Calculate R3 in the circuit of Figure 1.8.
Req = 250 Ω 1200 Ω 950 Ω R3
Figure 1.8. Equivalent parallel resistance.
When the number of resistors in parallel is two, Equation (1.11) reduces to
RA × RB
Rp = ᎏ (1.12)
RA + RB
왎 EXAMPLE 1.2
Calculate the terminal resistance of the resistors in Figures 1.9(a) and (b).
Req = 1 M⍀||2.3 M⍀
(106)(2.3 × 106)
= ᎏᎏ
106 + 2.3 × 106
= 697 k⍀
c01.qxd 2/5/2004 4:47 PM Page 10
1 MΩ 2.3 MΩ
(a)
150 kΩ
75 kΩ 75 kΩ 125 kΩ 53.37 kΩ
35 kΩ
(b)
Figure 1.9. Parallel resistance calculations and equivalent circuits.
The equivalent resistance at the network in Figure 1.9(b) is found by combining

the series resistors to 185 k⍀ and then calculating the parallel equivalent:
Req = 75 k⍀||185 k⍀
(75 × 103)(185 × 103)
= ᎏᎏᎏ
75 × 103 + 185 × 103
왎 = 53.37 k⍀
Self-Exercise 1.3
Calculate the resistance at the voltage source terminals Rin, IBB, and V0 at the ter-
minals in Figure 1.10. If you are good, you can do this in your head.
2 kΩ Vo
10 V
IBB 6 kΩ
Figure 1.10.
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Self-Exercise 1.4
Use Equations (1.11) or (1.12) and calculate the parallel resistance for circuits in
Figures 1.11(a)–(d). Estimates of the terminal resistances for circuits in (a) and
(b) should be done in your head. Circuits in (c) and (d) show that the effect of a
large parallel resistance becomes negligible.
Rin 1 kΩ 2 kΩ Rin 4 kΩ 4 kΩ
(a) (b)
Rin 1 kΩ 100 kΩ Rin 1 kΩ 1 MΩ
Rin 1 kΩ 100 kΩ Rin 1 kΩ 1 MΩ
(c) (d)
Figure 1.11.
Self-Exercise 1.5
Calculate Rin, IBB, and V0 in Figure 1.12. Estimate the correctness of your answer
in your head.
4 kΩ Vo
VBB
12 kΩ 20 kΩ
1V
Figure 1.12.
Self-Exercise 1.6
(a) In Figure 1.13, find I3 if I0 = 100 ␮A, I1 = 50 ␮A, and I2 = 10 ␮A. (b) If R3 =
50 k⍀, what are R1 and R2?
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R1 R2 R3
I0
I1 I2 I3
Figure 1.13.
Self-Exercise 1.7
Calculate R1 and R2 in Figure 1.14.
IO = 650 µA R1 Vo
3.3 V R2 R3 = 8 kΩ
I3 = 200 µA
Figure 1.14.
Self-Exercise 1.8
If the voltage across the current source is 10 V in Figure 1.15, what is R1?
5 kΩ R1
1 mA
10 kΩ 6 kΩ
3 kΩ
Figure 1.15.
Resistance Calculations by Inspection. A shorthand notation for the terminal re-

sistance of networks allows for quick estimations and checking of results. The calcula-
tions are defined before computing occurs. Some exercises below will illustrate this. So-
lutions are given in the Appendix.
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Self-Exercise 1.9
Write the shorthand notation for the terminal resistance of the circuits in Figures
1.16(a) and (b).
150 kΩ
75 kΩ
1 MΩ 2.3 MΩ
35 kΩ
(a) (b)
Figure 1.16.
Self-Exercise 1.10
Write the shorthand notation for the terminal resistance of the three circuits in
Figure 1.17.
R1 R2
VBB
R3 R4
R1 R2
VBB
R3 R4
R5
R2 R3
VBB
R1 R4 R5
Figure 1.17. Terminal resistance using shorthand notation.

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Self-Exercise 1.11
In the lower circuit of Figure 1.17, R1 = 20 k⍀, R2 = 15 k⍀, R3 = 25 k⍀, R4 = 8

k⍀, R5 = 5 k⍀. Calculate Req for these three circuits.
Dividers. Some circuit topologies are repetitive and lend themselves to analysis by in-
spection. Two major inspection techniques use voltage divider and current divider concepts
that take their analysis from the KVL and KCL. These are illustrated below with derivations
of simple circuits followed by several examples and exercises. The examples have slightly
more elements, but they reinforce previous examples and emphasize analysis by inspection.
Figure 1.18 shows a circuit with good visual voltage divider properties that we will il-
lustrate in calculating V3.
The KVL equation is
VBB = IBB(R1) + IBB(R2) + IBB(R3) = IBB(R1 + R2 + R3)

VBB V3 (1.13)
IBB = ᎏᎏ = ᎏ
R1 + R2 + R3 R3
and
R3
V3 = ᎏᎏ VBB (1.14)
R1 + R2 + R3
R1 R2
V2 V3
VBB
IBB R3
Figure 1.18. Voltage divider circuit.
Equation (1.14) is a shorthand statement of the voltage divider. It is written by inspection,

and calculations follow. The voltage dropped by each resistor is proportional to their frac-
tion of the whole series resistance. Figure 1.18 is very visual, and you should be able to
write the voltage divider expression by inspection for any voltage drop. For example, the
voltage from node V2 to ground is
R2 + R3
V2 = ᎏᎏ VBB (1.15)
R1 + R2 + R3
Self-Exercise 1.12
Use inspection and calculate the voltage at V0 (Figure 1.19). Verify that the sum
of the voltage drops is equal to VBB. Write the input resistance Rin by inspection
and calculate the current IBB.
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4 kΩ Vo
VBB
12 kΩ 20 kΩ
1V
Figure 1.19. Voltage divider analysis circuit.
Self-Exercise 1.13
Write the expression for Rin at the input terminals, V0, and the power supply cur-
rent (Figure 1.20).
8 kΩ Vo
VBB
45 kΩ 18 kΩ 30 kΩ
2.5 V
Figure 1.20.
Current divider expressions are visual, allowing you to see the splitting of current as it
enters branches. Figure 1.21 shows two resistors that share total current IBB.
KVL gives
R1 × R2
VBB = (R1||R2)IBB = ᎏ IBB = (I1)(R1) = (I2)(R2) (1.16)
R1 + R2
then
R2 R1
I1 = ᎏ IBB and I2 = ᎏ IBB (1.17)
R1 + R2 R1 + R2
IBB
R1 R2
I1 I2
Figure 1.21. Current divider.

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Currents divide in two parallel branches by an amount proportional to the opposite leg re-
sistance divided by the sum of the two resistors. This relation should be memorized, as
was done for the voltage divider.
Self-Exercise 1.14
Write the current expression by inspection and solve for currents in the 12 k⍀
and 20 k⍀ paths in Figure 1.22.
4 kΩ Vo
VBB
12 kΩ 20 kΩ
1V
Figure 1.22.
Self-Exercise 1.15
(a) Write the current expression by inspection and solve for currents in all resis-
tors in Figure 1.23, where IBB = 185.4 ␮A. (b) Calculate VBB.
8 kΩ Vo
VBB
45 kΩ 18 kΩ 30 kΩ
Figure 1.23.
Self-Exercise 1.16
(a) Solve for current in all resistive paths in Figure 1.24 using the technique of
inspection. (b) Calculate a new value for the 20 k⍀ resistor so that its current is 5
␮A.
10 kΩ 100 µA 15 kΩ 20 kΩ
Figure 1.24.
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1.3 CAPACITORS 17
Self-Exercise 1.17
In Figure 1.25, calculate V0, I2, and I9.
2Ω
Vo
1 mA
5Ω
6Ω 9Ω
Figure 1.25.
Self-Exercise 1.18
(a) Write Rin between the battery terminals by inspection and solve (Figure 1.26).
(b) Write the I1.5k expression by inspection and solve. This is a larger circuit, but
it presents no problem if we adhere to the shorthand style. We write Rin between
battery terminals by inspection, and calculate I1.5k by current divider inspection.
4 kΩ 750 Ω
VO
250 Ω
3 kΩ 1 kΩ 2 kΩ 1.5 kΩ
5V
250 Ω
Figure 1.26.
1.3 CAPACITORS
Capacitors appear in CMOS digital circuits as parasitic elements intrinsic to transistors or

with the metals used for interconnections. They have an important effect on the time for a
transistor to switch between on and off states, and also contribute to propagation delay be-
tween gates due to interconnection capacitance. Capacitors also cause a type of noise
called cross-talk. This appears especially in high-speed circuits, in which the voltage at
one interconnection line is affected by another interconnection line that is isolated but lo-
cated close to it. Cross-talk is discussed in later chapters.
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The behavior and structure of capacitors inherent to interconnection lines are signifi-
cantly different from the parasitic capacitors found in diodes and transistors. We introduce
ideal parallel plate capacitors that are often used to model wiring capacitance. Capacitors
inherent to transistors and diodes act differently and are discussed later.
A capacitor has two conducting plates separated by an insulator, as represented in Fig-
ure 1.27(a). When a DC voltage is applied across the conducting plates (terminals) of the
capacitor, the steady-state current is zero since the plates are isolated by the insulator. The
effect of the applied voltage is to store charges of opposite sign at the plates of the capac-
itor.
The capacitor circuit symbol is shown in Figure 1.27(b). Capacitors are characterized
by a parameter called capacitance (C) that is measured in Farads. Strictly, capacitance is
defined as the charge variation ⭸Q induced in the capacitor when voltage is changed by a
quantity ⭸V, i.e.,
⭸Q
C= ᎏ (1.18)
⭸V
This ratio is constant in parallel plate capacitors, independent of the voltage applied to the
capacitor. Capacitance is simply the ratio between the charge stored and the voltage ap-
plied, i.e., C = Q/V, with units of Coulombs per Volt called a Farad. This quantity can also
be computed from the geometry of the parallel plate and the properties of the insulator
used to construct it. This expression is
␧insA
C= ᎏ (1.19)
d
where ␧ins is an inherent parameter of the insulator, called permittivity, that measures the
resistance of the material to an electric field; A is the area of the plates used to construct
the capacitor; and d the distance separating the plates.
Although a voltage applied to the terminals of a capacitor does not move net charge
through the dielectric, it can displace charge within it. If the voltage changes with time,
then the displacement of charge also changes, causing what is known as displacement cur-
rent, that cannot be distinguished from a conduction current at the capacitor terminals.
Since this current is proportional to the rate at which the voltage across the capacitor
changes with time, the relation between the applied voltage and the capacitor current is
Metal
Insulator plates
A C
d
(a) (b)
Figure 1.27. (a) Parallel plate capacitor. (b) Circuit symbol.

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1.3 CAPACITORS 19
dV
i = Cᎏ (1.20)
dt
If the voltage is DC, then dV/dt = 0 and the current is zero. An important consequence of
Equation (1.20) is that the voltage at the terminals of a capacitor cannot change instanta-
neously, since this would lead to an infinite current. That is physically impossible. In later
chapters, we will see that any logic gate constructed within an IC has a parasitic capacitor
at its output. Therefore, the transition from one voltage level to another will always have a
delay time since the voltage output cannot change instantaneously. Trying to make these
output capacitors as small as possible is a major goal of the IC industry in order to obtain
faster circuits.
1.3.1 Capacitor Connections

Capacitors, like resistors, can be connected in series and in parallel. We will show the
equivalent capacitance calculations when they are in these configurations.
Capacitors in parallel have the same terminal voltage, and charge distributes according
to the relative capacitance value differences (Figure 1.28(a)). The equivalent capacitor is
equal to the sum of the capacitors:
Q1 Q2
C1 = ᎏ , C2 = ᎏ
V V
Q1 Q2 Q1 + Q2
C1 + C2 = ᎏ + ᎏ = ᎏ (1.21)
V V V
Qeq
Ceq = ᎏ
V
where Ceq = C1 + C2, and Qeq = Q1 + Q2. Capacitors connected in parallel simply add their
values to get the equivalent capacitance.
Capacitors connected in series have the same charge stored, whereas the voltage de-
pends on the relative value of the capacitor (Figure 1.28(b)). In this case, the expression
for the equivalent capacitor is analogous to the expression obtained when connecting re-
sistors in parallel:
Q +
C1 V1
-
V
V Q1 Q2 Q +
C1 C2 C2 V2
-
(a) (b)
Figure 1.28. Capacitance interconnection. (a) Parallel. (b) Series.

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Q Q
C1 = ᎏ , C2 = ᎏ
V1 V2
1 1 V1 V2 V1 + V2
ᎏ+ᎏ=ᎏ+ᎏ=ᎏ (1.22)
C1 C2 Q Q Q
Q
Ceq = ᎏ
Veq
where Veq = V1 + V2, and

C1C2
Ceq = ᎏ
C1 + C2
왎 EXAMPLE 1.3
In Figures 1.28(a) and (b), C1 = 20 pF and C2 = 60 pF. Calculate the equivalent

capacitance seen by the voltage source.
(a) Ceq = C1 + C2 = 20 pF + 60 pF = 80 pF
1 1
(b) Ceq = ᎏ1 1 = ᎏᎏ = 15 pF
ᎏᎏ + ᎏᎏ 1/20 pF + 1/60 pF
C1 C2
왎
Self-Exercise 1.19
Calculate the terminal equivalent capacitance for the circuits in Figure 1.29.
50 fF 75 fF
Ceq 60 fF 100 fF Ceq 60 fF

25 fF
(a) (b)
Figure 1.29.
1.3.2 Capacitor Voltage Dividers

There are open circuit defect situations in CMOS circuits in which capacitors couple volt-
ages to otherwise unconnected nodes. This simple connection is a capacitance voltage di-
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1.3 CAPACITORS 21
+
C1 V1
-
VDD
+
C2 V2
-
Figure 1.30. Capacitance voltage divider.
vider circuit (Figure 1.30). The voltage across each capacitor is a fraction of the total volt-
age VDD across both terminals.
왎 EXAMPLE 1.4
Derive the relation between the voltage across each capacitor C1 and C2 in Figure
1.30 to the terminal voltage VDD.
The charge across the plates of the series capacitors is equal so that Q1 = Q2.
The capacitance relation C = Q/V allows us to write
Q1 = Q2 C1V1 = C2V2
or
C1
V2 = ᎏ V1
C2
Since
VDD = V1 + V2
then
C1
V2 = VDD – V1 = ᎏ V1
C2
Solve for
C2
V1 = ᎏ VDD
C1 + C2
and get
C1
V2 = ᎏ VDD
C1 + C2
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The form of the capacitor divider is similar to the resistor voltage divider except
the numerator term differs. 왎
Self-Exercise 1.20
Solve for V1 and V2 in Figure 1.31.
+
45 nF V1
100 mV
-
+
75 nF V2
-
Figure 1.31.
Self-Exercise 1.21
If V2 = 700 mV, what is the driving terminal voltage VD in Figure 1.32?
30 fF
V2 VD
25 fF
Figure 1.32.
1.3.3 Charging and Discharging Capacitors

So far we have discussed the behavior of circuits with capacitors in the steady state, i.e.,
when DC sources drive the circuit. In these cases, the analysis of the circuit is done as-
suming that it reached a stationary state. Conceptually, these cases are different from situ-
ations in which the circuit source makes a sudden transition, or a DC source is applied to
a discharged capacitor through a switch. In these situations, there is a period of time dur-
ing which the circuit is not in a stationary state but in a transient state. These cases are im-
portant in digital CMOS ICs, since node state changes in ICs are transient states deter-
mining the timing and power characteristics of the circuit. We will analyze charge and
discharge of capacitors with an example.
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1.3 CAPACITORS 23
왎 EXAMPLE 1.5
In the circuit of Figure 1.33, draw the voltage and current evolution at the capac-
itor with time starting at t = 0 when the switch is closed. Assume Vin = 5 V and
that the capacitor is initially at 0 V.
t=0 R
+
Vin C VC
-
Figure 1.33.
The Kirchoff laws for current and voltage can be applied to circuits with ca-
pacitors as we did with resistors. Thus, once the switch is closed, the KVL must
follow at any time:
Vin = VR + VC
The Kirchoff current law applied to this circuit states that the current through the
resistor must be equal to the current through the capacitor, or
VR dVC
ᎏ = Cᎏ
R dt
Using the KVL equation, we can express the voltage across the resistor in terms
of the voltage across the capacitor, obtaining
Vin – VC dVC
ᎏ = Cᎏ
R dt
This equation relates the input voltage to the voltage at the capacitor. The solu-
tion gives the time evolution of the voltage across the capacitor,
VC = Vin(1 – e–t/RC)
The current through the capacitor is
Vin – VC
IC = IR = ᎏ
R
Vin
IC = ᎏ e–t/RC
R
At t = 0, the capacitor voltage is zero (it is discharged) and the current is maxi-
mum (the voltage drop at the resistor is maximum), whereas in DC (for t 씮 ⬁)
the capacitor voltage is equal to the source voltage and the current is zero. This
example shows that the voltage evolution is exponential when charging a capaci-
c01.qxd 2/5/2004 4:48 PM Page 24
5 Vin/1 kΩ 5
4 4
3 3
IC (mA)
VC (V)
2 2
1 1
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
t/RC t/RC
Figure 1.34.
tor through a resistor. The time constant is defined for t = RC, that is, the time re-
quired to charge the capacitor to (1 – e–1) of its final value, or 63%. This means
that the larger the value of the resistor or capacitor, the longer it takes to
charge/discharge it (Figure 1.34). 왎
1.4 DIODES
A circuit analysis of the semiconductor diode is presented below; later chapters discuss its
physics and role in transistor construction. Diodes do not act like resistors; they are non-
linear. Diodes pass significant current at one voltage polarity and near zero current for the
opposite polarity. A typical diode nonlinear current–voltage relation is shown in Figure
1.35(a) and its circuit symbol in Figure 1.35(b). The positive terminal is called the anode,
and the negative one is called the cathode. The diode equation is
qVD
ID = IS(e ᎏ
kT – 1) (1.23)
where k is the Boltzmann constant (k = 1.38 × 10–23 J/K), q is the charge of the electron (q
= 1.6 × 10–19 C), and IS is the reverse biased current. The quantity kT/q is called the ther-
mal voltage (VT) whose value is 0.0259 V at T = 300 K; usually, we use VT = 26 mV at that
60
50
40
30
ID (mA)
20 VD
10 + -
0
-10
-20
ID
-0.8 -0.4 0 0.4 0.8 1.2
V (V)
(a) (b)
Figure 1.35. (a) Diode I–V characteristics and (b) symbol.

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1.4 DIODES 25
temperature. When the diode applied voltage is positive and well beyond the thermal volt-
age (VD Ⰷ VT = kT/q), Equation (1.23) becomes
qVD
ᎏ
ID = ISeqVD/kT
kT (1.24)
The voltage across the diode can be solved from Equation (1.23) as
kT ID
q IS 冢
VD = ᎏ ln ᎏ + 1 冣 (1.25)
For forward bias applications ID/IS Ⰷ 1 and this reduces to
kT ID
VD = ᎏ ln ᎏ (1.26)
q IS
Self-Exercise 1.22
(a) Calculate the forward diode voltage if T = 25°C, ID = 200 nA, and IS = 1 nA.
Compute from Equation (1.25). (b) At what current will the voltage drop be 400
mV?
Diode Equations (1.23)–(1.26) are useful in their pure form only at the temperature at
which IS was measured. These equations predict that ID will exponentially drop as temper-
ature rises which is not so. IS is more temperature-sensitive than the temperature exponen-
tial and doubles for about every 10°C rise. The result is that diode current markedly in-
creases as temperature rises.
1.4.1 Diode Resistor Circuits

Figure 1.36 shows a circuit that can be solved for all currents and node element voltages if
we know the reverse bias saturation current IS.
왎 EXAMPLE 1.6
If IS = 10 nA at room temperature, what is the voltage across the diode in Figure

1.36 and what is ID? Let kT/q = 26 mV.
10 kΩ
2V
ID
Figure 1.36. Forward-biased diode analysis.

c01.qxd 2/5/2004 4:48 PM Page 26
Write KVL using the diode voltage expression:
ID
冢
2 V = ID(10 k⍀) + (26 mV) ln ᎏ + 1
IS 冣
This equation has one unknown (ID), but it is difficult to solve analytically, so an
iterative method is easiest. Values of ID are substituted into the equation, and the
value that balances the LHS and RHS is a close approximation. A starting point
for ID can be estimated from the upper bound on ID. If VD = 0, then ID = 2 V/10
k⍀ = 200 ␮A. ID cannot be larger than 200 ␮A. A close solution is ID = 175 ␮A.
The diode voltage is
kT ID
VD = ᎏ ln ᎏ
q IS
175 uA
= 26 mV × ln ᎏ = 244.2 mV
10 nA
왎
Self-Exercise 1.23
Estimate ID and VD in Figure 1.37 for IS = 1 nA.
1 kΩ VDD
500 mV
ID
Figure 1.37.
왎 EXAMPLE 1.7
Figure 1.38 shows two circuits with the diode cathode connected to the positive
terminal of a power supply (IS = 100 nA). What is V0 in both circuits?
Vo
Vo
2V
2V
1 MΩ
(a) (b)
Figure 1.38.
c01.qxd 2/5/2004 4:48 PM Page 27
1.4 DIODES 27
Figure 1.38(a) has a floating node at V0 so there is no current in the diode.

Since ID = 0, the diode voltage drop VD = 0 and
V0 = VD + 2 V = 2 V
Figure 1.38(b) shows a current path to ground. The diode is reversed-biased and
IBB = –ID = 100 nA. Then
V0 = IBB × 1 M⍀ = 100 nA × 1 M⍀ = 100 mV

왎
Both problems in Example 1.7 can be analyzed using Equations (1.23) to (1.26) or ob-
serving the process in the I–V curve of Figure 1.35. In Figure 1.38(a), the operating point
is at the origin. In Figure 1.38(b), it has moved to the left of the origin.
Self-Exercise 1.24
The circuit in Figure 1.39 is similar to IC protection circuits connected to the in-
put pins of an integrated circuit. The diodes protect the logic circuit block when
input pin (pad) voltages are accidentally higher than the power supply voltage
(VDD) or lower than the ground voltage. If VPAD > 5 V, then diode D2 turns on and
bleeds charge away from the input pin. The same process occurs through diode
D1 if the input pad voltage becomes less than ground (0 V). An integrated circuit
tester evaluates the diodes by forcing current (100 ␮A) and measuring the volt-
age. If the protection circuit is damaged, an abnormal voltage is usually read at
the damaged pin.
(a) If diode reverse bias saturation current is IS = 100 nA, what is the expected
input voltage measured if the diodes are good and R1 and R2 are small? Apply
±100 ␮A to assess both diodes.
(b) If the upper diode has a dead short across it, what is VIN when the test ex-
amines the upper diode?
5V
D2
R2
Logic
PAD Circuit
100 µA
R1
D1
Figure 1.39.
c01.qxd 2/5/2004 4:48 PM Page 28
Self-Exercise 1.25
Calculate V0 and VD1 in Figure 1.40, where IS = 100 ␮A and T = 25 °C.
5V ID D1 Vo
D2
Figure 1.40.
1.4.2 Diode Resistance

Although diodes do not obey Ohm’s law, a small signal variation in the forward bias can
define a resistance from the slope of the I–V curve. The distinction with linear elements is
important as we cannot simply divide a diode DC voltage by its DC current. That result is
meaningless.
The diode curve is repeated and enlarged in Figure 1.41. If a small signal variation v(t)
is applied in addition to the DC operating voltage VDC, then the exponential current/volt-
age characteristic can be approximated to a line [given that v(t) is small enough] and an
equivalent resistance for that bias operation can be defined. Bias point 1 has a current
change with voltage that is larger than that of bias point 2; therefore, the dynamic resis-
tance of the diode is smaller at bias point 1. Note that this resistance value depends
strongly on the operating voltage bias value. Each point on the curve has a slope in the
forward bias. Dividing the DC voltage by the current, V1/I1, is not the same as V2/I2.
Therefore, these DC relations are meaningless. However, dynamic resistance concepts are
important in certain transistor applications.
This concept is seen in manipulation of the diode equation, where the forward-biased
dynamic resistance rd is
1 dID d[ISeqVD/kT] qISeqVD/kT qID
ᎏ = ᎏ = ᎏᎏ = ᎏ = ᎏ (1.27)
rd dVD dVD kT kT
60
50
40
30
Bias 1•
ID (mA)
20
10
Bias 2
•
0
-10
-20
-0.8 -0.4 0 0.4 0.8 1.2
VD (V)
Figure 1.41.
c01.qxd 2/5/2004 4:48 PM Page 29
EXERCISES 29
The diode dynamic resistance is

dVD kT
rd = ᎏ = ᎏ (1.28)
dID qID
or at room temperature
26 mV
rd ⬇ ᎏ (1.29)
ID
Self-Exercise 1.26
Find the diode dynamic resistance at room temperature for ID = 1 ␮A, 100 ␮A, 1
mA, and 10 mA.
How do we use the concept of dynamic diode resistance? A diode can be biased at a
DC current, and small changes about that operating point have a resistance. A small sinu-
soid voltage (vD) causes a diode current (iD) change equal to vD/rD. The other important
point is that you cannot simply divide DC terminal voltage by DC terminal current to cal-
culate resistance. This is true for diodes and also for transistors, as will be seen later.
1.5 SUMMARY
This chapter introduced the basic analysis of circuits with power supplies, resistors, ca-
pacitors, and diodes. Kirchhoff’s current and voltage laws were combined with Ohm’s law
to calculate node voltages and element currents for a variety of circuits. The technique of
solving for currents and voltages by inspection is a powerful one because of the rapid in-
sight into the nature of circuits it provides. Finally, the section on diodes illustrated analy-
sis with a nonlinear element. The exercises at the end of the chapter should provide suffi-
cient drill to prepare for subsequent chapters, which will introduce the MOSFET
transistor and its simple configurations.
BIBLIOGRAPHY
1. R. C. Dorf and J. A. Svoboda, Introduction to Electric Circuits, 4th ed., Wiley, 1998.
2. D. E. Johnson, J. R. Johnson, J. L. Hilburn, and P. Scott, Electric Circuit Analysis, 3rd ed., Pren-
tice-Hall, 1989.
3. J. W. Nilsson and S. A. Riedel, Electric Circuits, 6th ed., Prentice-Hall, 2000.
4. A. J. Rosa and R. E. Thomas, The Analysis and Design of Linear Circuits, 4th ed., Wiley, 2003.
EXERCISES
1.1. Write the shorthand expression for Req at the open terminals in Figure 1.42.
1.2. Write the shorthand expression for Req at the open terminals in Figure 1.43.
c01.qxd 2/5/2004 4:48 PM Page 30
R1 R6
R2 R3 R7
R8
R4 R5
Figure 1.42.
R5 R2
R1
R6 R3 R4
R7
Figure 1.43.
1.3. For the circuit in Figure 1.44, (a) calculate V0; (b) calculate I2M.
1.4. Calculate V0 by first writing a voltage divider expression and then solving for V0
(Figure 1.45a and b).
1.5. Write the shorthand notation for current I2 in resistor R2 in Figure 1.46 as a function
of driving current I.
1.6. For the circuit in Figure 1.47, (a) solve for V0 using a voltage divider expression; (b)
solve for I2K; (c) solve for I900.
c01.qxd 2/5/2004 4:48 PM Page 31
EXERCISES 31
4 MΩ Vo
3V
2 MΩ 3MΩ
Figure 1.44.
4 kΩ
15 kΩ Vo
Vo
1.8 V
1.8 V 4 kΩ 6 kΩ
6 kΩ 15 kΩ
(a) (b)
Figure 1.45.
R4
I R1 R2 R3
I2
Figure 1.46.
c01.qxd 2/5/2004 4:48 PM Page 32
400 Ω
Vo
300 Ω
3.3 V
900 Ω 2 kΩ 1.5 kΩ
Figure 1.47.
1.7. Use the circuit analysis technique by inspection, and write the shorthand expression
to calculate I2K for Figure 1.48.
25 kΩ
15 kΩ Vo
3.3 V
50 kΩ 45 kΩ 5 kΩ 2 kΩ
Figure 1.48.
1.8. Given the circuit in Figure 1.49, (a) write the expression for I450 and solve; (b) write
the expression for V800; (c) show that I800 + I400 = 2 mA.
400 Ω
800 Ω 2 mA 900 Ω 450 Ω
Figure 1.49.
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EXERCISES 33
1.9. Find I6k in Figure 1.50. Hint: when we have two power supplies and a linear (resis-
tive) network, we solve in three steps.
1. Set one power supply to 0 V and calculate current in the 6 k⍀ resistor from the
nonzero power supply.
2. Reverse the role and recalculate I6k.
3. The final answer is the sum of the two currents.
This is known as the superposition theorem and can be applied only for linear ele-
ments.
3 kΩ 4 kΩ
5V 6 kΩ 10 V
Figure 1.50.
1.10. Find the equivalent capacitance at the input nodes in Figure 1.51.
150 fF
Ceq 120 fF 90 fF
200 fF
Figure 1.51.
1.11. Find C1 in Figure 1.52.
1.12. Solve for ID and VD in Figure 1.53, where the diode has the value IS = 1 ␮A.
1.13. Calculate V0 in Figure 1.54, given that the reverse-bias saturation current IS = 1 nA,
and you are at room temperature.
c01.qxd 2/5/2004 4:48 PM Page 34
10 nF
+ +
3.3 V C1 2.68 V
18 nF
- -
Figure 1.52.
10 kΩ
12 kΩ
5V
6 kΩ
3 kΩ
Figure 1.53.
10 kΩ
6 nA D2
D1
Figure 1.54.
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EXERCISES 35
1.14. Diode D1 in Figure 1.55 has a reverse-bias saturation current of I01 = 1 nA, and
diode D2 has I02 = 4 nA. At room temperature, what is V0?
5 kΩ
D1
500 kΩ Vo
3V
2 kΩ
D2
Figure 1.55.
1.15. Calculate the voltage across the diodes in Figure 1.56, given that the reverse-bias
saturation current in D1 is I01 = 175 nA and I02 = 100 nA.
5 kΩ
400 mA D1 D2
Figure 1.56.
c02.qxd 2/2/2004 12:22 PM Page 37
CHAPTER 2
SEMICONDUCTOR PHYSICS
2.1 SEMICONDUCTOR FUNDAMENTALS
2.1.1 Metals, Insulators, and Semiconductors

Materials are classified by their physical properties. Conductivity measures the amount of
current through a material when a voltage is applied, and materials are classified into
three conductivity groups: metals, insulators, and semiconductors. Metals present practi-
cally no resistance to carrier flow, whereas insulators allow virtually no electrical carrier
flow under an applied voltage. Semiconductors are unique, and can behave as conductors
or insulators. This chapter introduces the principles of semiconductor physics, using only
a few equations and numerical examples. Emphasis is on providing a common under-
standing of these principles and a basic description of how the devices work. The lan-
guage and visual and mathematical models of semiconductor physics permeate CMOS
manufacturing.
The classic explanation for conduction differences between these materials uses the
energy band model of solids that derives from quantum mechanics. Neils Bohr found that
electrons in an atom could not have arbitrary energy values, but had defined, discrete
(quantum) energy values. A basic principle of quantum mechanics is that energy is dis-
tributed in quantum packets, and cannot take continuous values. Electrons orbit at discrete
distances from the nucleus. Figure 2.1(a) shows the allowed energy levels of a hydrogen
atom electron. These energy levels are those that the electron can take that are discrete.
The s and p energy level symbols are taken from quantum mechanical convention.
In a two-atom system, each energy level in the single atom system splits into two sub-
levels, as shown in Figure 2.1(b). When more atoms are added to construct a crystalline
solid, the energy levels successively split, leading to the picture in Figure 2.1(c), where
c02.qxd 2/2/2004 12:22 PM Page 38
38 CHAPTER 2 SEMICONDUCTOR PHYSICS
2p
2p conduction
2p
band
Energy
bandgap (Eg)
2s 2s
2s
valence Range of
band allowed
energies
1s
1s 1s
One atom Two atoms Crystal
(a) (b) (c)
Figure 2.1. (a) Energy levels in a single atom, (b) two atoms, and (c) a solid.
energy bands separated by gaps of forbidden energies (called band gaps) replace single
energy levels. The band gap width depends on the type of atom used to build the solid, and
it determines the conductive properties of the material.
Energy bands have different conduction properties. The outermost energy band is
called the conduction band, and the next-lower one is called the valence band or outer
shell. An electron having an energy corresponding to the conduction band is not tied to
any atom, and can move “freely” through the solid. Such an electron contributes to current
when a voltage is applied. An electron in the valence band has an energy that is attached
to an atom of the solid, and is not “free” to move within the solid when a voltage is ap-
plied.
Energy bands help us more easily understand the conductive properties of different
materials. Figure 2.2(a) shows the energy bands of a metal; the lowest energy value of the
conduction band is below the maximum energy of the valence band. This means that the
Ec
Ev Ec
Eg Eg
Ec Ev
Ev
GaAs Eg = 1.41 eV
S iO2 Eg = 9 eV Si Eg = 1.12 eV
Diamond Eg = 5.47 eV Ge Eg = 0.66 eV
(a) (b) (c)
Figure 2.2. Energy bands in solids: (a) metal, (b) insulator, (c) semiconductor.
c02.qxd 2/2/2004 12:22 PM Page 39
2.1 SEMICONDUCTOR FUNDAMENTALS 39
metal conduction band has an abundance of electrons that are available for conduction. It
takes very little additional energy to move an electron from the valence to the conduction
band since the bands are merged.
The energy band structure of an insulator is shown in Figure 2.2(b). Insulators have a
large energy gap between the valence and conduction bands. The thermal energy needed
for an electron to go from the valence to the conduction band is so high that only a few
electrons within the material can acquire such an energy and jump over the gap. A voltage
applied to the material will cause almost no current since virtually all electrons are tied to
atoms in the valence band.
Semiconductors are the third class of conducting material, and show an intermediate
behavior. The valence and conduction bands are not merged, but the energy gap is small
enough so that some electrons are energetic enough to jump across it. The energy needed
for electrons to jump across the gap comes from the ambient temperature or photon ener-
gy. We will deal with thermal energy since most integrated circuits are sealed and admit
no light from the environment. The process of gaining enough thermal energy and jump-
ing from the valence to the conduction band is inherently statistical. This means that elec-
trons in a solid are continuously moving up and down between the valence and conduction
bands. However, at a given temperature there is a population of electrons in the conduc-
tion band that contribute to the current.
Since the energy used by an electron to jump the gap is thermal, the population of elec-
trons in the conduction band depends on the temperature. At absolute zero temperature,
there is no thermal energy in a pure semiconductor, so that no electron has enough energy
to jump across the gap. As temperature increases, the number of conducting electrons in-
creases.
The differences in gap energies between insulators and semiconductors are related to
how electrons are arranged within atoms. Electrons are grouped into layers around the
atomic nucleus, and electrons in the internal layers cannot be separated from the nucleus.
Only electrons from the outside valence layer may jump from their bounded valence state
to the conducting state (free from the attractive forces of the atomic nucleus). Atoms of
conducting materials have several layers of orbiting electrons. The number of electrons re-
quired to fill a given layer remains constant and independent of the atomic element. An
atom having all layers completely filled will have all electrons (even those at the outmost
layer) strongly “tied” to the nucleus. A large amount of energy is needed to break such a
layer and take one electron out of the atom. These atoms are known as noble gases, since
they do not react with other elements, as their electrons are closely packed. Atoms in
which the external layer is not “closed” (more electrons are required to completely fill
such layers) have electrons more lightly attached to the atom. As a result, only a small
amount of energy is needed to separate an external electron from the atom. This is the
case in metals; the outside electrons belong to the solid instead of being attached to some
nucleus.
2.1.2 Carriers in Semiconductors: Electrons and Holes

The only contribution to current in a metal is from electrons in the conducting band. In
contrast, semiconductor current has two contributions: one from electrons in the conduc-
tion band and the other from electron vacancies in the valence band caused by electrons
that jumped into the conduction band. The vacancy of an electron in the valence band
leaves an empty local charge space of a value equal to the electron charge, but of opposite
c02.qxd 2/2/2004 12:22 PM Page 40
sign. Therefore, it has a net charge +q (q being the charge value of an electron; q = –1.6 ×
10–19 Coulomb).
The most common semiconductor material for ICs is silicon, that has four electrons
in its outer energy band (Figure 2.3(a)). When silicon is crystalline, each electron of the
valence layer is shared with one electron of a neighbor atom so that by sharing, each Si
atom has eight outer shell electrons. If a valence electron gains enough thermal energy
to jump into the conduction band, it leaves a vacancy position. Such a position is avail-
able to another valence electron to move into and leave a vacancy at its original site.
This process can now be repeated for a third valence electron moving into this last va-
cancy, and so on. It is important to note that this process does not require the moving
valence electron to go to the conduction band to move to such a vacancy. The electron
vacancy can be seen as a “particle” of positive charge that moves in the opposite direc-
tion to the valence electron. Such a virtual particle with associated charge
+q is called a “hole.” When silicon is constructed as a crystal, it behaves as a semi-
conductor.
When the semiconductor is in equilibrium and there is no external electromagnetic
field or temperature gradient, then electrons and holes move randomly in space, and no
net current is observed. When an electric field is applied, the hole movement is not ran-
dom, but drifts in the same direction as the field. This gives a net current contribution
from holes, in addition to the current contribution from electrons in the conduction band.
These dual conduction mechanisms in solids are detailed in the next section.
In a pure silicon material, electrons and holes are created in pairs. The “creation” of a
free electron jumping into the conduction band creates a hole in the valence band, where-
as an electron dropping from the conduction to the valence band implies that a hole disap-
pears. When an electron jumps from the valence to the conduction band, the process is
called an electron–hole pair creation, and when an electron jumps back from the conduc-
tion band to the valence band, the process is referred to as electron–hole recombination,
or simply recombination. Energy is needed for electron–hole pair formation, but in the
opposite process, energy is released when an electron recombines with a hole. This is il-
lustrated in Figure 2.4 for the energy band gap model of a semiconductor and its solid-
state physical representation. It emphasizes that mobile carriers are electrons in the con-
duction band and holes in the valence band. The process of electron–hole creation and
bound electrons valence electrons

silicon
nucleus
outmost
elctron layer Si
(4 electrons) nucleus
(a) (b)
Figure 2.3. (a) Representation of a silicon atom with its four electrons at the outmost layer, and (b)
picture of the silicon structure in a crystalline solid.
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2.1 SEMICONDUCTOR FUNDAMENTALS 41
conduction electrons
mobile
holes
Ec
electron-hole electron-hole
generation recombination
Ev
valence conduction mobile
electrons holes electrons
Figure 2.4. Electron-hole pair creation and recombination in the band gap model (left), and its rep-
resentation in the solid (right).
recombination is inherently statistical—electron–hole pairs are continuously created and

recombined in a semiconductor at a given temperature.
2.1.3 Determining Carrier Population*

We will refer to electrons as the carriers in the conduction band and holes as the carriers
in the valence band. Electrons and holes are mobile carriers, and we must estimate their
populations at each temperature that are statistically available in each band. Fermi–Dirac
statistics accounts for the basic properties of electrons in solids, and gives us a mathemat-
ical model of the electron statistics for the concentration of carriers. Electrons have a du-
ality property, acting as particles or as indistinguishable waves, and follow the Pauli prin-
ciple of exclusion.† Since electrons are quantum elements, we describe the probability of
an electron being at a given energy for a given temperature. The probability of an electron
at a given energy level E is expressed with a probability function ƒ(E), which may be de-
rived from the Fermi–Dirac statistics (see [2] or [1]), obtaining
1
ƒ(E) = ᎏᎏ (2.1)
1 + e(E–EF)/kT
where k is the Boltzmann constant (1.38 × 10–23 J/K), T is temperature in Kelvin, and EF
is known as the Fermi energy level, an important parameter for semiconductors. The Fer-
mi energy level is the energy at which the probability function equals 0.5 (this can be eas-
ily verified by substituting E = EF in the equation), or the energy level below which the
probability function is 1 for T = 0 K. At absolute zero temperature, all possible energy lev-
els are filled. If fe(E) is the probability function of an electron being at a given energy (E),
then holes are the “dual” or complementary particles. The probability of a given hole be-
ing at such an energy is fh(E) = 1 – fe(E).
Since we are describing electrons in a solid, we must account for the number of avail-
able energy states. For example, no state is available within the forbidden energy gap. The
*This subsection can be skipped without loss of continuity.

†The Pauli principle of exclusion states that two quantum objects (electrons in this case) cannot occupy the
same energy levels. As a result, the maximum number of electrons per layer in a given atom is fixed.
c02.qxd 2/2/2004 12:22 PM Page 42
formulation of the number of states N(E) available for an electron at a given energy in a
solid allows us to find the concentration of electrons n having an energy interval dE as
n = ƒ(E)N(E)dE (2.2)
The electron concentration within the conduction band is found by integrating such a con-
centration from E = EC to E 씮 ⬁. Thus,
n0 = 冕 ⬁
EC
ƒ(E)N(E)dE (2.3)
where n0 stands for the number of carriers in equilibrium. Similarly, the hole concentra-
tion is
h0 = 冕Ev
–⬁
[1 – ƒ(E)]N(E)dE (2.4)
A detailed derivation for N(E) and Equations (2.3) and (2.4) are beyond the scope of this
work. For a detailed analysis we refer to any of the books cited at the end of the chapter.
2.2 INTRINSIC AND EXTRINSIC SEMICONDUCTORS
The previous concepts applied to “pure” semiconductors, in which all atoms are of the
same type. This is referred to as an intrinsic semiconductor, implying that the number of
electrons is equal to the number of holes, since they are generated in pairs. Extrinsic
semiconductors are created by intentionally adding impurities* to the semiconductor to
increase the concentration of one carrier type (electrons or holes) without increasing
the concentration of the other, thus breaking the symmetry between the number of elec-
trons and holes. The intentional substitution of a silicon atom by another element is
called doping. This process depends on the type of impurity added and the number of
impurities introduced in a unit volume. There are n-type impurities that increase electron
concentration and p-type impurities that increase hole concentration. The number of
impurities (atoms/unit volume) injected into the solid is much less than the number of
silicon atoms, and the crystalline structure of the semiconductor is not globally dis-
turbed.
2.2.1 n-Type Semiconductors

Silicon has four electrons in its outer layer that form bonds with neighbor atoms. We can
increase the electron concentration without changing the hole concentration by replacing
some silicon atoms with Periodic Table Group V atoms having five electrons in their ex-
ternal layer (arsenic, phosphorus, or antimony). Four of the five external electrons of the
substituting atom create bonds with the neighboring silicon atoms, while the fifth one is
almost free to move within the solid (Figure 2.5). At room temperature, the thermal en-
ergy is enough to activate such a fifth electron and move it into the conduction band.
*Any material, no matter what its quality, always has unintended impurities. The effect of such impurities can
be neglected if they are kept to a minimum. Additionally, crystalline solids are not perfect crystals and may have
some “irregularities” that impact the energy band structure.
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2.2 INTRINSIC AND EXTRINSIC SEMICONDUCTORS 43
extra electron
phosporus
nucleus
Figure 2.5. Adding a donor atom creates a mobile electron without creating a hole.
Ec Ec
Ev Ev
T=0K room temperature
Figure 2.6. Picture of the donor effect in the band-gap energy model with change in temperature.
The electron jumps into the conducting energy band without creating a hole, so no elec-
tron–hole pairs are generated, only free electrons. In this case, each impurity atom is
called a donor, since it implies that an extra electron is donated to the semiconductor.
Silicon is a Group IV atom in the Periodic Table and donor atoms come from the Group
V atoms.
When extrinsic silicon is doped with donors, the number of conducting electrons is
approximately equal to the number of donor atoms injected (ND) plus some electrons
coming from electron–hole pair creation. When donor concentration greatly exceeds the
normal intrinsic population of carriers, then the conducting electron concentration is
essentially that of the donor concentration. By adding a specific concentration of
donors, the population of electrons can be made significantly higher than that of holes.
An extrinsic semiconductor doped with donor impurities is called an n-type semicon-
ductor.
When a considerable number of donor impurities are added (1015–1017 atoms per cm3),
the effect on the bandgap model is creation of an allowed energy level within the gap
close to the Ec (Figure 2.6). At zero Kelvin temperature, all electrons are at this energy
level and are not mobile within the solid. At room temperature, the energy required to
jump into the conduction band is small, and all donor electrons are ionized and remain in
the conduction band.
Doping a semiconductor does not increase its net charge, since the negative q charge
excess of the fifth electron with respect to the “replaced” silicon atom is balanced by the
atomic number* of the donor impurity (5 instead of 4 for silicon) giving an extra positive
charge that compensates the electron charge.
*The atomic number is the number of protons of a neutral (nonionized) atom.

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extra hole boron

nucleus
Figure 2.7. Adding acceptor atoms creates a mobile hole without creating an electron.
2.2.2 p-Type Semiconductors

We can increase the number of holes without increasing the number of electrons by re-
placing silicon atoms with elements from Group III in the Periodic Table that have three
electrons in the outermost layer. The three electrons of the impurity bond with three of the
neighbor silicon atoms, and the fourth bond is missing (Figure 2.7). Impurities having
three electrons in the outermost layer are called acceptors since a vacancy is created that
can accept free electrons. Acceptor doping in the energy-band model creates an energy
level close to the silicon valence band, as shown in Figure 2.8. At room temperature, elec-
trons in the valence band have enough energy to jump to this level. This creates a hole in
the silicon without injecting electrons into the conduction band. At a given temperature,
the concentration of holes in a semiconductor in which a number NA of acceptor impuri-
ties were introduced will be NA plus some of the holes contributed by the electron–hole
pairs created at that temperature. Boron is a Group III atom and is the most popular of ac-
ceptor doping atoms.
2.3 CARRIER TRANSPORT IN SEMICONDUCTORS
The movement of electrons and holes in a semiconductor is called carrier transport. Com-
putation of carrier transport requires knowing the carrier concentration calculated from
the Fermi function and its subsequent derivations. It also requires the laws governing
movement of carriers within the solid. Movement of electrons and holes within a semi-
Ec Ec
Ev Ev
T=0K room temperature
Figure 2.8. Effect of acceptor doping in the band-gap model.

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2.3 CARRIER TRANSPORT IN SEMICONDUCTORS 45
conductor is different from carriers traveling in free space since collisions of carriers with
the lattice impact their mobility. Temperature also plays an important role in carrier trans-
port since it determines the carrier population and also affects carrier movement within
the solid because of atomic thermal agitation. Although carriers are in constant motion
within a solid, an unbiased semiconductor will not register a net current since carrier
movement is random and no preferred direction is collectively chosen. A force is required
for net movement of a charge to occur. The two main carrier movement mechanisms in
solids are drift and diffusion.
2.3.1 Drift Current

Drift is carrier movement due to an electric or magnetic field. An electric field Ᏹ applied
to a semiconductor causes electrons in the conduction band to move in the direction oppo-
site to the electric field, whereas holes in the valence band move in the same direction of
this field. An electric field causes energy band bending, as shown in Figure 2.9(a) and the
carrier movement indicated in Figure 2.9(b). Electron and hole current densities (electron
hopping in the valence band) have the same direction and both contribute to current.
At relatively low electric fields, the velocity acquired by electrons and holes has a lin-
ear dependence on the applied external field. This dependence is maintained until a cer-
tain electric field is reached, and then the carrier velocity saturates. Velocity saturation oc-
curs because carriers collide with the lattice atoms of the crystal. For electric fields
beyond 105 V/cm, electron and hole velocities reach a maximum value in pure silicon at
room temperature and no longer depend on the applied field. Modern deep-submicron
transistors show velocity saturation during switching.
The relation between drift velocity and electric field for carriers is given by
␮0Ᏹ
冤冢冣冥
␤ –1/␤
vd = ␮0Ᏹ 1 + ᎏ (2.5)
vsat
where ␤ ⬇ 1 for electrons, ␤ ⬇ 2 for holes, ␮0 is the proportionality factor between the
electric field Ᏹ and the carrier velocity at low electric fields, and vsat is the velocity satu-
ration value reached for high electric fields. Note that this expression leads to vd = ␮0 Ᏹ
for low electric fields and vd = vsat for large electric field strengths.
Jn electrons Jn
Ec
Ᏹ Ᏹ
Ev
Jp Jp
holes
(a) (b)
Figure 2.9. Band bending by the effect of an external applied field Ᏹ.

c02.qxd 2/2/2004 12:22 PM Page 46
The current density of charge carriers Jd in an electric field is derived from a series of
relations shown below, where v is the velocity of moving charge, N is the moving carrier
concentration, q is carrier charge, and Ᏹ is the electric field pushing the charge through a
solid with mobility ␮.
Jd = vqN = ␮qᏱN (2.6)
2.3.2 Diffusion Current

Diffusion is a thermal mechanism that moves particles from high-density macroscopic re-
gions to low-density ones, so that in the final situation, the particle distribution in space is
uniform. Electrons and holes diffusing in a solid are moving charged particles that create
a diffusion current. Diffusion motion is described by Fick’s law, stating that
J = –D ⵜ N (2.7)
where J is flux in particles/cm2-sec, ⵜN is the gradient of particles, and D is the diffusion

coefficient. The equation states that the flux of particles is zero if there is a uniform distri-
bution (i.e., ⵜN is zero). Electrons and holes diffusing in the same direction give rise to
opposite current densities since their charge signs are opposite. Expressions for electron
and hole diffusion currents are
Jn|diff = qDn ⵜ n
(2.8)
Jp|diff = –qDpⵜp
Dn and Dp are electron and hole diffusion coefficients that differ because electron and
hole mobilities are different. The relation between the diffusion coefficient and the mobil-
ity is
Dx kT
ᎏ=ᎏ (2.9)
␮x q
where x must be replaced by n for electrons and by p for holes. This equation is known as
the Einstein relationship. Drift is the dominant charge transport mechanism in CMOS
field-effect transistors, whereas diffusion plays a secondary role. Velocity saturation of
electrons and holes occurs in the drift mechanism of all modern CMOS transistors.
2.4 THE pn JUNCTION
Diodes are simple semiconductor devices that are the building blocks of MOS transistors.
Diodes have a junction formed by joining a p-type and n-type semiconductor. This is re-
ferred to as a pn junction. To understand pn junction properties, assume an ideal case in
which two pieces of semiconductors with opposite doping are initially separated [Figure
2.10(a)] and then joined [Figure 2.10(b)]. The lattice structure is not lost at the joining
surface, and the doping concentration has a sharp change from the left side (n-doped) to
the right side (p-doped).
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2.4 THE pn JUNCTION 47
donor mobile aceptor mobile

nucleus electrons nucleus holes
n-type Si p-type Si
(a)
electron
diffusion
n -type p-type
side side
hole
diffusion
(b)
Figure 2.10. Two pieces of semiconductor materials with opposite doping: (a) separated and (b)
joined.
Since the n-type and p-type semiconductor bars are in equilibrium, the total net charge
in each bar is zero. At the instant when the semiconductor pieces join, there is a momen-
tary abrupt change in electron and hole concentration at the joining surface. Strong con-
centration gradients exist for electrons on the n-side and holes on the p-side. This non-
equilibrium condition exists for a short time during which electrons at the junction start to
diffuse from the initial n-type bar into the p-type one, while holes close to the junction
move away from the p-doped semiconductor into the n-type one. If electrons and holes
were not charged particles, then this diffusing process would continue until electron and
hole concentrations were uniform along the whole piece of joined semiconductors.
The reality is different, since electrons and holes are charged particles and their diffu-
sion creates electric fields in the semiconductor at both sides of the junction. Carriers
close to the junction are the first particles to diffuse away and recombine when they meet
opposite carrier types on the opposite side of the junction. As a consequence of this carri-
er migration and recombination, all dopant atoms close to the joining surface are ionized.
This creates a zone of net charge (Figure 2.11) around the junction (positive at the n-side
and negative at the p-side) that induces an electric field pointing from the n-side to the p-
side. Carriers moving by diffusion now “feel” the electric field as an opposing force when
trying to diffuse. Their final motion depends on which conducting mechanism is stronger.
As more carriers move by diffusion, more atoms are ionized, and the electric field
strength increases. Finally, the net diffusion mechanism stops when the induced internal
electric field (which increases with the number of carriers moving by diffusion) reaches a
value such that its force exactly balances the force tending to diffuse carriers across the
junction. The result is creation of a depletion region with all donors and acceptors ionized
where the net charge and electric field are nonzero.
c02.qxd 2/2/2004 12:22 PM Page 48
n-type built-in p-type

side electric field side
depletion
Charge region
+Q
-Q
Built-in
electric
field
V
Vbi
Figure 2.11. A diode in equilibrium, showing the charge, electric field, and potential internal distri-
bution.
Figure 2.11 shows a picture of the diode junction in equilibrium (no external electric
field, light, or temperature gradient are present) and the charge, electric field, and po-
tential distribution at each point within the diode. Notice that in the regions where atoms
are not ionized (out of the depletion region), there is charge neutrality, so that no elec-
tric field or potential drop exist. The net charge in the depletion region is positive in the
n-type side and negative in the p-type side. As a result, the electric field increases while
moving from the neutral regions to the junction site. The electric field distribution caus-
es a voltage difference between the two oppositely doped regions that depends mainly
on the doping levels. This is called the built-in junction potential (Vbi) shown at the bot-
tom of Figure 2.11.
At equilibrium, a charge zone exists on both sides of the junction in which all donors
and acceptor atoms are ionized. This zone is known as the depletion region or space-
charge zone with a high electric field and a potential that increases when moving from the
p-type zone to the n-type zone. Outside the boundaries of the space charge region within
the semiconductor, the electric field, net charge, and potential gradient are all zero.
2.5 BIASING THE pn JUNCTION: I–V CHARACTERISTICS
The previous section showed that when two semiconductor bars of opposite doping are
joined, a built-in electric field appears, preventing electrons from diffusing too far away
from the n-side and holes from diffusing away from the p-side. Once the system is in equi-
c02.qxd 2/2/2004 12:22 PM Page 49
2.5 BIASING THE pn JUNCTION: I–V CHARACTERISTICS 49
librium, no current exists since the junction is isolated with no external conducting path.
We will now analyze the behavior of the junction when an external voltage is applied.
2.5.1 The pn Junction under Forward Bias

Assume that an external voltage source is connected to a diode, inducing more positive
voltage at the p-side with respect to the n-side (Figure 2.12). The external voltage creates
an electric field opposed to the built-in one, decreasing its strength. The built-in electric
field is a barrier for electrons diffusing from the n-side to the p-side and for holes diffus-
ing from the p-side to the n-side. An external reduction of the built-in field favors the dif-
fusion process. Since many conducting electrons are on the n-side and many holes are on
the p-side, then many electrons will diffuse into the p-side and many holes will diffuse
into the n-side. This process causes a permanent current since electrons must be replaced
at the n-type side through the voltage source, and holes are required at the p-type side. The
larger the applied voltage bias, the higher the diode current.
2.5.2 The pn Junction under Reverse Bias

When the voltage applied to the diode is positive at the n-side with respect to the p-side, it
induces an external electric field that increases the built-in junction electric field (Figure
2.13). This reduces electron diffusion from the n-side silicon into the p-side, and hole dif-
fusion in the opposite direction. Only electrons or holes within the junction region itself
are accelerated by the junction electric field and contribute to overall current. Since very
few electrons are present in a p-type material, and few holes are in the n-type side, the re-
verse bias current is very small. In fact, this current, called the reverse-bias saturation cur-
rent, arises from thermal generation of electron–hole pairs in the depletion region itself.
The free electron and hole carriers are then rapidly swept out of the junction, forming the
current at the diode terminals.
The device-level current/voltage characteristics of the diode were introduced in Chap-
ter 1. The relation between the applied diode voltage VD and the obtained current ID is ex-
ponential and reproduced here:
冢冣
qVD
ᎏ
ID = IS e kT –1 (2.10)
external
electric field
- + ++
+
- +
+ +
- ++
-
internal
electric field
- +
Figure 2.12. Forward-biased diode showing internal junction depletion-field reduction.

c02.qxd 2/2/2004 12:22 PM Page 50
external
electric field
+ - --
+
+ - --
+ - --
internal
electric field
+ -
Figure 2.13. Reverse-biased diode showing internal junction depletion-field increase.
Remember that I0 is called the reverse-bias saturation current. When VD is large and
negative, then ID = –I0. The I–V characteristic of the diode rapidly increases for positive
diode voltages, whereas very little current is obtained for negative diode voltages.
2.6 PARASITICS IN THE DIODE
Diodes are useful as nonsymmetric components that allow current in one direction but not
in the opposite. All diodes show a behavior that deviates from their ideality and this devi-
ation can be modeled by so-called parasitic elements. Parasitic elements are undesired
and can be resistance, capacitance, or inductance. The diode current leakage in the off-
state (ideally not conducting) can be modeled by a high parasitic (undesired) resistance.
In CMOS technology, two parasitic diodes exist in each transistor. These diodes are al-
ways reverse-biased in ICs, and their main degradation effects at the circuit level are relat-
ed to reverse current leakage or to delay through parasitic capacitors of the diode.
We saw that when a diode is reverse-biased, the external voltage increases the internal
electric field strength. This widens the depletion region. The higher the reverse voltage,
the wider the depletion region, and the larger the total net charge in this region. Converse-
ly, a forward bias narrows the depletion region, and reduces the fixed charges across the
pn junction. Therefore, a diode has an internal capacitor since there is a charge variation
induced by a voltage variation. From Chapter 1, we know that the term capacitance is de-
fined as the charge variation in a component due to voltage variation at its terminals, i.e.,
⭸Q
C= ᎏ (2.11)
⭸V
The parasitic capacitor inherent to the pn junction is different from the passive or par-
allel-plate capacitors seen in Chapter 1 because the charge–voltage ratio varies with the
applied voltage. Since the Q/V quotient is not constant when the applied voltage changes,
a fixed capacitor value cannot be assigned to the parasitic capacitor.
The effect of the diode parasitic capacitor at the circuit level is significant, since it
must be charged and discharged when a gate is switching. This contributes to circuit delay
c02.qxd 2/2/2004 12:22 PM Page 51
BIBLIOGRAPHY 51
0.8
0.6
0
Cj/Cj
0.4
0.2
0
-10 -8 -6 -4 -2 0
VD/Vbi
Figure 2.14. Plot of Cj versus applied voltage (VD) for a diode.
and other secondary effects discussed later. In many cases, the exact dependence of the
diode parasitic capacitor with the applied voltage is replaced by an approximate value.
The value of the capacitor with the applied voltage is
Cj0
Cj = ᎏᎏ (2.12)
冢冣
VD 1/2
1 – ᎏᎏ
Vbi
where Cj0 is a constant depending on the pn doping values, fundamental constants of the
silicon, the area of the surfaces being joined, and the built-in junction potential; VD is the
reverse applied voltage, and Vbi is the built-in junction potential. Figure 2.14 plots the ca-
pacitance normalized to Cj0 with respect to the reverse applied voltage. Equation (2.12)
breaks down in the diode forward-bias regions for large positive values of VD. In the next
chapter, it will be shown how this parasitic device affects device operation, and how it is
modeled at the circuit level.
2.7 SUMMARY
The construction of integrated circuits ultimately depends on a strong physical base.

Chapter 2 provides a brief introduction to these essential concepts. Although a few model-
ing equations were given, the purpose is qualitative understanding of the language and
physical flow of semiconductor conduction, related doping properties, and diode charac-
teristics. These ideas permeate later chapters.
BIBLIOGRAPHY
1. N. W. Ashcroft and N. D. Mermin, Solid State Physics, Saunders College, 1976.

2. C. Kittel, Introduction to Solid State Physics, 6th ed., Wiley, 1986
c02.qxd 2/2/2004 12:22 PM Page 52
3. D. A. Neamen, Semiconductor Physics and Devices—Basic Principles, 3rd ed., McGraw-Hill,

2003.
4. R. F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley, 1996.
EXERCISES
2.1. Discuss the following:

(a) What is the band-gap voltage Eg in the solid state model?
(b) Use the band-gap voltage to distinguish between metals, semiconductors, and
insulators.
2.2. Metal electrical conduction is done by electrons. How does semiconductor conduc-
tion differ?
2.3. What energy process occurs when electron–hole pairs are created, and when they
recombine?
2.4. What is the Fermi Level?
2.5. Electrical conduction in a metal is done entirely by electrons. The dominant form of
conduction in a semiconductor can either be by holes or electrons. How does inser-
tion of a Group III or a Group V element into a host Group IV Si element affect the
choice of dominant hole or electron injection.
2.6. Two forces dominate the net motion of carriers in a semiconductor: drift and diffu-
sion. Describe the conditions that promote these two mechanisms.
2.7. Describe how an electric field appears across a pn junction and the dynamic rela-
tion of this Ᏹ-field to charge movement across the pn junction.
2.8. The diode reverse bias saturation current IS originates in the depletion region with
its high electric field. The sources of this current are the thermal creation of elec-
tron–hole pairs that are then swept out of the junction by this high electric field. If
the reverse-bias voltage is made larger, what is the impact on IS? Will IS increase,
decrease, or stay the same? Explain.
2.9. The diode equation (2.10) predicts an exponential increase in diode current ID as
diode voltage VD increases. Assume that you measured a diode in the forward-bias
region and found an exponential relation at the lower VD, but the curve tended to-
ward a straight line at higher voltages. Explain.
2.10. Chapter 1 described capacitors made of two metal plates separated by a dielectric.
Describe how a pn junction capacitance differs from the simple metal plate dielec-
tric capacitor.
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CHAPTER 3
MOSFET TRANSISTORS
MOSFET transistors are the basic element of today’s integrated circuits (ICs). Our goal
here is to impart the analytical ability and transistor insights that electrical engineers use
in solving IC problems. An abundance of examples and self-exercises are provided to de-
velop intuitive responses to digital transistor circuit operation. We begin with a simple
picture of transistors as switches, and evolve to more developed analytical models. We
want to smoothly lead the way through these topics, providing knowledge and insight
about transistors in the long- and short-channel technologies. The information in this
chapter is a foundation for subsequent chapters, and is a basis for understanding the elec-
tronic aberrations of defective circuits.
3.1 PRINCIPLES OF OPERATION: LONG-CHANNEL TRANSISTORS
Transistors are the basic blocks for building electronic circuits. A major difference be-
tween transistors and passive elements (resistors, capacitors, inductors, and diodes) is that
transistor current and voltage characteristics vary with the voltage (or current) on a con-
trol terminal. There are two types of transistors with different physical principles: bipolar
transistors and field effect transistors (FETs). There is only one type of bipolar transis-
tor—the bipolar junction transistor (BJT)—and two types of FET devices—the junction
field effect transistor (JFET) and the metal oxide semiconductor field effect transistor
(MOSFET). Today’s digital ICs mainly use MOSFETs, whereas bipolars are used in spe-
cific digital technologies and more generally in analog circuits. JFETs have specific ap-
plications and are not used in digital applications. We will focus on MOSFETs since they
appear in more than 90% of today’s digital applications.
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54 CHAPTER 3 MOSFET TRANSISTORS
MOSFETs have three signal terminals: gate (G), source (S) and drain (D), plus the
bulk terminal (B), to which the gate, drain, and source voltages are referenced. Figure
3.1(a) shows a MOSFET with its four terminals and its thin insulator of SiO2 (with thick-
ness TOX) between the gate and bulk. Figure 3.1(b) shows symbols commonly used for
MOSFETs, where the bulk terminal is labeled (B) or implied (not drawn). There are two
types of MOSFET transistors, the nMOS transistor and the pMOS transistor, depending
on the polarity of the carriers responsible for conduction. A simple description of the de-
vice will introduce basic concepts and terms.
3.1.1 The MOSFET as a Digital Switch

The simplest view of MOSFET logic operation treats the transistor as a switch. The gate
terminal is analogous to the light switch on the wall. When the gate has a high voltage, the
transistor closes like a switch, and the drain and source terminals are electrically connect-
ed. Just as a light switch requires a certain force level to activate it, the transistor needs a
certain voltage level to connect the drain and source terminals. This voltage is called the
transistor threshold voltage Vt and is a fixed voltage different for nMOS (Vtn) and pMOS
(Vtp) devices in a given fabrication process. The nMOS threshold voltage Vtn is always
positive, whereas the pMOS threshold voltage Vtp is always negative.
Transistors act as switches with two conducting states, on and off, depending on the
control (gate) terminal voltage. An ideal transistor has a zero ohm resistance between the
drain and source when it is in the on-state, and infinite resistance between these terminals
in the off-state. The ideal device should also switch between on- and off-states with a zero
delay time as soon as the control variable changes state.
Unfortunately, transistors are not ideal switches. MOS transistors have a small, equiva-
lent drain–source resistance in their conducting state and a high but not infinite resistance
in the off-state. Additionally, the delay of a transistor to switch between on- and off-states
is not zero. Several parameters (both geometric and technology related) determine the on
and off equivalent resistance and capacitance that degrade the time needed to switch be-
tween both states.
Figure 3.2 shows switch models for the nMOS and pMOS transistors. In the nMOS,
the source is the reference terminal, which is always at the lower voltage, so that VDS ⱖ 0,
and VGS ⱖ 0. Since Vtn is always positive, the off-state occurs when VGS < Vtn so the de-
G G
Gate
Source
W
Drain S D S D
B B
Tox
G G
L
S D S D
Bulk
nMOS pMOS
Figure 3.1. (a) MOS structure. (b) Symbols used at the circuit level.
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3.1 PRINCIPLES OF OPERATION: LONG-CHANNEL TRANSISTORS 55
D S
D OFF S OFF
RON (VGS > Vtp) RON
(VGS < Vtn) VGS
S D
G G
D S
VGS ON ON
S RON D (VGS < Vtp) RON
(VGS > Vtn)
S D
nMOS (Vtn > 0, VDS ⱖ 0, VGS ⱖ 0) pMOS (Vtp < 0, VDS ⱕ 0, VGS ⱕ 0)
Figure 3.2. Transistor symbols and their equivalent ideal switches.
vice does not conduct, and it is modeled as an open switch. When VGS > Vtn, the device is
in the on-state and modeled as a closed switch in series with a resistor RON. The model in
Figure 3.2 represents this on resistance as constant, whereas in a real transistor the
drain–source current (and therefore its equivalent resistance) depends on the operating
state of the device, and must be determined from the VGS and VDS relations.
The pMOS transistor model is equivalent, but the signals have an opposite terminal po-
larity. The source is the reference terminal, which is always at the highest voltage, so that
VDS ⱕ 0, and VGS ⱕ 0. Vtp has negative voltages in pMOS transistors. The off-state is de-
fined when VGS > Vtp and the on-state for VGS < Vtp. Since Vtp is always negative, the
pMOS transistor turns on when VGS < Vtp, where both are negative numbers. This polarity
confusion will become clear when we address pMOS transistor operation. For now, accept
that the pMOS transistor has polarity control signals opposite to those of the nMOS tran-
sistor.
The ideal device characteristics for this simple model are
IDS = 0, (off-state) when 冦 VV GS

GS
< Vtn nMOS
> Vtp pMOS
(3.1)
VGS ⱖ Vtn nMOS
冦
VDS
IDS = ᎏᎏ, (on-state) when
RON VGS ⱕ Vtp pMOS
We will next consider the simple switch model and deepen our understanding of MOS-
FET structure, operating modes, and behavior models.
3.1.2 Physical Structure of MOSFETs

This section will describe transistors as they are today, and subsequent material will de-
velop why they are so. MOSFET transistors are made from a crystalline semiconductor
that forms the host structure called the substrate or bulk of the device. Substrates for
nMOS are constructed from p-type silicon, whereas the pMOS substrates use n-type sili-
con. The thin oxide of the transistor electrically isolates the gate from the semiconductor
crystalline structures underneath. The gate oxide is made of oxidized silicon, forming a
noncrystalline, amorphous SiO2. The gate oxide thickness is typically from near 15 Å to
c03.qxd 2/5/2004 4:49 PM Page 56
100 Å (1 Å = 1 angstrom = 10–10 m). SiO2 molecules are about 3.5 Å in diameter, so this
vital dimension is a few molecular layers thick. A thinner gate oxide provides more gate
terminal control over the device state.
Drain and source regions are made from crystalline silicon by implanting a dopant
with polarity opposite to that of the substrate. The region between the drain and source
is called the channel. The distance from the drain to the source is a geometrical para-
meter called the channel length (L) of the device, as shown in Figure 3.1(a). Another
geometrical parameter of the device is the transistor channel width (W) [Figure 3.1(a)].
Transistor length and width are geometrical parameters set by the circuit designer. Other
parameters, such as the transistor oxide thickness, threshold voltage, and doping levels,
depend on the fabrication process, and cannot be changed by design; they are technolo-
gy parameters.
The gate is the control terminal, and the source provides electron or hole carriers that
are collected by the drain. Often, the bulk terminals of all transistors are connected to the
ground or power rail that is often the source and, therefore, not explicitly drawn in most
schematics.
Figure 3.3 shows nMOS and pMOS transistor structures. The nMOS transistor has a p-
type silicon substrate with opposite doping for the drain and source. pMOS transistors
have a complementary structure with an n-type silicon bulk and p-type doped drain and
source regions. The gate region in both transistors is constructed with polysilicon, and is
isolated from the drain and source by the thin oxide. The region between the drain and
source under the gate oxide is called the channel, and is where conduction takes place.
The gate is electrically isolated from the drain, source, and channel by the gate oxide
insulator. Since drain and source dopants are opposite in polarity to the substrate (bulk),
they form pn junction diodes (Figure 3.3) that in normal operation are reverse-biased.
CMOS logic circuits typically match one nMOS transistor to one pMOS transistor.
3.1.3 Understanding MOS Transistor Operation: A Descriptive Approach

Transistor terminals must have proper voltage polarity to operate correctly (Figure 3.4).
The bulk or substrate of nMOS (pMOS) transistors must always be connected to the
lower (higher) voltage that is the reference terminal. We will assume that the bulk and
source terminals are connected, to simplify the description. The positive convention cur-
rent in an nMOS (pMOS) device is from the drain (source) to the source (drain), and is
referred to as IDS or just ID, since drain and source current are equal. When a positive
(negative) voltage is applied to the drain terminal, the drain current depends on the volt-
age applied to the gate control terminal. Note that for pMOS transistors, VGS, VDS, and
IDS are negative.
Source Gate Drain Source Gate Drain

n+ n+ p+ p+
bulk (p-type) bulk (n-type)
(a) nMOS transistor (b) pMOS transistor
Figure 3.3. Relative doping and equivalent electrical connections between device terminals for (a)
nMOS and (b) pMOS transistors.
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VGS VGS
G
VDS G
S D D n-type Si S
p-type Si
B B
VDS
D S
VDS
G IDS VDS VGS G
VGS IDS
S D
(a) nMOS (b) pmos
Figure 3.4. Normal transistor biasing (a) nMOS and (b) pMOS.
If VGS is zero, then an applied drain voltage reverse-biases the drain–bulk diode (Fig-
ure 3.5), and there are no free charges between the drain and source. As a result, there is
no current when VGS = 0 for nMOS devices (the same hold for pMOS devices). This is the
off, or nonconducting, state of the transistor.
We will first analyze transistor operation when the source and substrate are at the same
voltage. When the gate terminal voltage of an nMOS (pMOS) transistor is slightly in-
creased (decreased), a vertical electric field exists between the gate and the substrate
across the oxide. In nMOS (pMOS) transistors, the holes (electrons) of the p-type (n-type)
substrate close to the silicon–oxide interface initially “feel” this electrical field, and move
away from the interface. As a result, a depletion region forms beneath the oxide interface
for this small gate voltage (Figure 3.6). The depletion region contains no mobile carriers,
so the application of a drain voltage provides no drain current, since free carriers still do
not exist in the channel.
If the gate voltage of the nMOS (pMOS) device is further increased (decreased), then
the vertical electric field is strong enough to attract minority carriers (electrons in the
nMOS device and holes in the pMOS device) from the bulk toward the gate. These minor-
ity carriers are attracted to the gate, but the silicon dioxide insulator stops them, and the
VGS = 0 VGS = 0
VDS > 0 G
G
D S
S D
B
B
VDS < 0
(a) nMOS (b) pMOS
Figure 3.5. When the gate–source voltage is zero, the drain–source voltage reverses the built-in
drain–bulk diode, preventing current from flowing from the drain to the source.
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Vtn> VGS > 0 Vtp <VGS < 0

VDS = 0 VDS = 0 ---------------
+++++++++++++++
S D D S
B B
(a) nMOS (b) pMOS
Figure 3.6. (a) Depleting the nMOS channel of holes with small positive values of gate–source
voltage, and (b) depleting the pMOS channel of electrons with small negative values of gate–source
voltage.
electrons (holes) accumulate at the silicon–oxide interface. They form a conducting plate
of minority mobile carriers (electrons in the p-type bulk of the nMOS device, and holes in
the n-type bulk of the p-MOS device). These carriers form the inversion region or con-
ducting channel, which can be viewed as a “short circuit” to the drain/source-bulk diodes.
This connection is shown in Figure 3.7.
Since the drain and source are at the same voltage, the channel carrier distribution is
uniform along the device. The gate voltage for which the conducting channels respond is
an intrinsic parameter of the transistor called the threshold voltage, referred to as Vt. As a
first approximation, Vt can be considered constant for a given technology. The threshold
voltage of a nMOS transistor is positive, while for a pMOS transistor it is negative. Since
nMOS and pMOS transistors have a different threshold voltages, Vtn refers to the nMOS
transistor threshold voltage, and Vtp to the pMOS transistor.
An nMOS (pMOS) transistor has a conducting channel when the gate–source voltage
is greater than (less than) the threshold voltage, i.e., VGS > Vtn (VGS < Vtp).
When the channel forms in the nMOS (pMOS) transistor, a positive (negative) drain
voltage with respect to the source creates a horizontal electric field, moving the channel
carriers toward the drain and forming a positive (negative) drain current. If the horizontal
electric field is of the same order or smaller than the vertical one, the inversion channel
remains almost uniform along the device length. This happens when
VDS < (VGS – Vtn) nMOS transistor

(3.2)
VDS > (VGS – Vtp) pMOS transistor
VGS > Vtn VGS < Vtp

VDS = 0 VDS = 0
G
S D D S
B
B
(a) nMOS (b) pMOS
Figure 3.7. Creating the conducting channel for (a) nMOS and (b) pMOS transistors.
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This condition will be explained below. It states that the vertical electric field dominates
the horizontal one. The transistor is in its linear region, also called the ohmic or nonsatu-
rated region.
If the drain voltage increases beyond the limit of Equation (3.2), the horizontal electric
field becomes stronger than the vertical field at the drain end, creating an asymmetry of
the channel carrier inversion distribution. The drain electric field is strong enough so that
carrier inversion is not supported in this local drain region. The conducting channel re-
tracts from the drain, and no longer “touches” this terminal. When this happens, the inver-
sion channel is said to be “pinched off ” and the device is in the saturation region. The
pinch-off point is the location that separates the channel inversion region from the drain
depletion region. It varies with changes in bias voltages. The channel distribution in this
bias is shown in Figure 3.8.
Although there are no inversion charges at the drain end of the channel, the drain re-
gion is still electrically active. Carriers depart from the source and move under the effect
of the horizontal field. Once they arrive at the pinch-off point of the channel, they travel
from that point to the drain, driven by the high electric field of the depletion region.
CMOS ICs use all three states described here: off-state, saturated state, and the linear
state. We will next look at real curves of MOS parameters, and learn how to use the ana-
lytical equations that predict and analyze transistor behavior in normal and defective envi-
ronments. It is important to work through all examples and exercises. The examples will
analyze MOS long- and short-channel transistor circuits.
3.1.4 MOSFET Input Characteristics

MOS transistors cannot be described with a single current–voltage curve, as can diodes
and resistors, since they have four terminals. Transistors require that two sets of cur-
rent–voltage curves be characterized: the input characteristic and the output characteris-
tic. The input characteristic is a single curve that relates drain current to the input
gate–source driving voltage. Since the gate terminal is electrically isolated from the re-
maining terminals (drain, source, and bulk), the current through the gate is essentially
zero, so that gate current is not part of the device characteristics. The input characteris-
tic curve can locate the voltage on the control terminal (gate) at which the transistor
leaves the off-state.
Figure 3.9 shows measured input characteristics for an nMOS and pMOS transistor
with a small, 0.1 V potential across their drain-to-source terminals. As VGS increases for
VGS > Vtn VGS < Vtp

VDS > VGS-Vtn VDS < VGS -Vtp
G
S D D S
B B
(a) nMOS (b) pMOS
Figure 3.8. Channel pinch-off for (a) nMOS and (b) pMOS transistor devices.
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(a) (b)
Figure 3.9. Measured input characteristics (ID vs. VGS ) for (a) an nMOS, and (b) a pMOS transistor.
the nMOS transistor in Figure 3.9(a), a voltage is reached at which drain current begins.
When the nMOS device conducts, the drain current is positive, since the current enters the
drain. For VGS between 0 V and 0.7 V, the drain current is nearly zero, indicating that the
equivalent resistance between the drain and source terminals is extremely high. Once the
gate–source voltage reaches 0.7 V, the current increases rapidly with VGS, indicating that
the equivalent resistance at the drain decreases with increasing gate–source voltage.
Therefore, the threshold voltage of this device is about Vtn ⬇ 0.7 V. When a transistor
turns on and current moves through a load, then voltage changes occur that translate into
logic levels.
The pMOS transistor input characteristic in Figure 3.9(b) is analogous to the nMOS
transistor except that the IDS and VGS polarities are reversed. VDS is negative (VDS ⬇ –0.1
V) and the drain current in a pMOS transistor is negative, indicating that it exits the drain
terminal. Additionally, the gate is at a voltage lower than the source terminal voltage to at-
tract holes to the channel surface. The threshold voltage of the pMOS device in Figure
3.9(b) can be seen as approximately Vtp ⬇ –0.8 V.
3.1.5 nMOS Transistor Output Characteristics

MOS transistor output characteristics plot ID versus VDS for several values of VGS. Figure
3.10 shows such a measurement of an nMOS transistor. When the transistor is in the off-
state (VGS < Vtn), then ID is near zero for any VDS value. When the device is in the on-state,
transistor conduction properties vary with the bias state of the device. Two states, de-
scribed as the ohmic (or nonsaturated) state and the saturated state, are distinguished
when the device is in the on-state. The boundary of the two bias states is seen for each
curve in Figure 3.10 as the intersection of the straight line of the saturated region with the
curving line of the ohmic region. This intersection point occurs at VDsat. In the ohmic
state, the drain current initially increases almost linearly with the drain voltage before
bending and flattening out. The drain current in saturation is virtually independent of VDS
and the transistor acts as a current source. A near-constant current is driven from the tran-
sistor no matter what the drain-to-source voltage is.
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VG = 3.0 V
VG = 2.5 V
VG = 2.0 V
VG = 1.5 V
VG = 1.0 V
VG = 0.5 V
Figure 3.10. nMOS transistor output characteristics as a family of curves. The diamond symbol
marks the pinch-off voltage, VDSAT.
This family of curves is rapidly measured with a digital curve tracer called a parameter
analyzer. Many useful parameters can be measured from data in the family of curves, and
deviations in the curves are also a good indicator of a damaged transistor. Later, we will
deepen our understanding of transistor operation expressed by Figure 3.10. pMOS transis-
tor ID versus VDS curves have shapes similar to those in Figure 3.10, but the voltage and
current polarities are negative to account for hole inversion and drain current that enters
the transistor (pMOS device curves are shown later).
We next develop skills with the equations that predict voltages and currents in a tran-
sistor for any point in the family of curves in Figure 3.10. This capability is needed to an-
alyze electronic behavior of CMOS circuits with bridge, open circuit, or parametric de-
fects.
MOS equations can be derived by calculating the amount of charge in the channel at
each point, and integrating such an expression from the drain to the source. This proce-
dure is found in several books [3, 6, 7], and leads to expressions for the drain current in
the linear and saturated states. Equations (3.3) and (3.4) are these equations for the nMOS
transistor in the saturated and ohmic states.
␮␧ox W
ID = ᎏ ᎏ (VGS – Vtn)2 (saturated state) (3.3)
2Tox L
␮␧ox W
ID = ᎏ ᎏ [2(VGS – Vtn)VDS – V 2DS] (ohmic state) (3.4)
2Tox L
where ␮ is the electron mobility, ␧ox is thin oxide (SiO2) dielectric constant, Tox is the
transistor oxide thickness, and W and L are transistor effective gate width and length. A
constant, K, is introduced to indicate the drive strength of the transistor as
␮␧ox
K= ᎏ (3.5)
2Tox
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If these constants are known, then Equation (3.3) can predict ID for any value of VGS in the
saturated region, and Equation (3.4) can predict any ID in the ohmic region if VGS and VDS
are specified. Equation (3.3) is a square-law relation between ID and VGS that is indepen-
dent of VDS. Equation (3.3) is a flat line for a given VGS, whereas Equation (3.4) is a
parabola. For any VGS, the two equations have an intersect point that is seen in Figure
3.10. The intersection point occurs at a parameter called VDsat, for which either equation
describes the current and voltage relations.
We can solve for this important bias condition at which the saturated and ohmic states
intersect (VDsat), and this knowledge is essential for solving problems that follow. Figure
3.11 plots three parabolas of Equation (3.4) at VGS = 2.0 V, 1.6 V, and 1.2 V. Only the left-
hand sides of the parabolas are used to predict the curves in Figure 3.10, but the parabolas
also have a right-hand side. The dotted lines on the right-hand side of the curves are part
of the continuous solution to the parabolas, but are electronically invalid, as examples will
show.
The midpoint at zero slope defines the useful upper region of Equation (3.4), and also
defines the boundary between the saturated and ohmic bias states. We can define the
boundary bias condition by differentiating Equation (3.4) with respect to VDS, setting the
expression to zero, and then solving for the conditions. Equation (3.6) shows the deriva-
tive of Equation (3.4) set to zero:
dID ␮␧ox W
ᎏ = ᎏ ᎏ [2(VGS – Vtn) – 2VDS] = 0 (3.6)
dVDS 2Tox L
Terms cancel, giving the bias condition at the transition between saturation and nonsatura-
tion states as
VGS = VDS + Vtn (3.7)
Figure 3.11. Plot of parabola of the nonsaturation state equation [Equation (3.4)]. Kn = 100 ␮A/V2,
Vtn = 0.4 V, and W/L = 2. Solid lines indicate valid regions, but dotted lines do not. (a) VGS = 2.0 V,
(b) VGS = 1.6 V, (c) VGS = 1.2 V.
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This equation holds for each of the intersection points in Figure 3.11 denoted at the peak
of each curve. Equation (3.7) can be extended to define the nMOS saturated bias condi-
tion:
VDS > VGS – Vt or VGS < VDS + Vt (3.8)
and the nMOS ohmic condition:
VDS < VGS – Vt or VGS > VDS + Vt (3.9)
We use these relations to analyze the effect of defects on CMOS circuits. A series of ex-
amples and exercises will illustrate their use. We emphasize that drill imparts the intuition
that experienced failure analysts and test, reliability, and product engineers use in CMOS
IC manufacturing.
왎 EXAMPLE 3.1
Determine the bias state for the three conditions in Figure 3.12 if Vtn = 0.4 V.
2.5
2.5VV 0.5
0.5VV 0.5
0.5VV
1.9
1.9VV 2.2
2.2VV 0.9
0.9VV
--2.3
2.3VV -2.5
-2.5VV
(a) (b) (c)
Figure 3.12. Transistor bias-state examples.
(a) VGS = 1.9 V, VDS = 2.5 V, and Vtn = 0.4 V, therefore VGS = 1.9 V < 2.5 V +
0.4 V = 2.9 V. Equation (3.8) is satisfied, and the transistor is in the saturated
state described by Equation (3.3).
(b) VGS = VG – VS = 2.2 V – (–2.3 V) = 4.6 V. VDS = VD – VS = 0.5 V – (–2.3) =
2.8 V. Therefore, VGS = 4.6 V > 2.2 V + 0.4 V = 2.6 V. Equation (3.9) is satisfied,
and the transistor is in the nonsaturated state.
(c) VGS = VG – VS = 0.9 V – (–2.5 V) = 3.4 V. VDS = VD – VS = 0.5 V – (–2.5 V)
= 3 V. Therefore, VGS = 3.4 V = VDS + Vt = 3 V + 0.4 V = 3.4 V, and the transistor
is at the boundary of the saturated and ohmic regions. Either Equation (3.3) or
(3.4) can be used to calculate ID. 왎
Self-Exercise 3.1
Determine the bias state for the three conditions in Figure 3.13 if Vtn = 0.4 V.
After solving bias Example 3.1 and Self-Exercise 3.1 with the proper bias-state equations,
you may check your work by referring to the nMOS transistor family of curves in Figure
c03.qxd 2/5/2004 4:49 PM Page 64
1.4VV
1.4 2.7
2.7VV 33VV
33VV 4V 4.5
4.5VV
22VV 55VV
(a) (b) (c)
Figure 3.13. Bias-state exercises.
3.10. Find the coordinates in the example and exercise, and verify that the bias state is cor-
rect. A series of examples and exercises with the nMOS transistor will reinforce these im-
portant relations.
왎 EXAMPLE 3.2
Calculate ID and VDS if Kn = 100 ␮A/V2, Vtn = 0.6 V, and W/L = 3 for transistor
M1 in the circuit in Figure 3.14.
The bias state of M1 is not known, so we must initially assume one of the two
states, solve for bias voltages, and then check for consistency against that transis-
tor’s bias condition. Initially, assume that the transistor is in the saturated state so
that
␮␧ox W W
ID = ᎏ ᎏ (VGS – Vtn)2 = Kn ᎏ (VGS – Vtn)2
2Tox L L
= (100 ␮A) (3) (1.5 – 0.6)2
= 243 ␮A
Using Kirchhoff’s voltage law (KVL):
VDS = VDD – IDR

= 5 – (243 ␮A)(15 k⍀)
= 1.355 V
5V
15 kΩ
1.5 V
M1
Figure 3.14.
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We assumed that the transistor was in saturation, so we must check the result to
see if that is true. For saturation,
VGS < VDS + Vtn

1.5 V < 1.355 V + 0.6 V
so the transistor is in saturation, and our assumption and answers are correct. 왎
왎 EXAMPLE 3.3
Repeat Example 3.2, finding ID and VDS if VG = 1.8 V.

Assume a transistor saturated state and
ID = (100 ␮A)(3)(1.8 – 0.6)2

= 432 ␮A
VDS = 5 – (432 ␮A)(15 k⍀)
= –1.48 V
This value for VDS is clearly not reasonable since there are no negative poten-
tials in the circuit. Also, the bias check gives
VGS > VDS + Vtn

1.8V > –1.48 V + 0.6 V
The initial saturated state assumption was wrong, so we repeat the analysis
using the ohmic state assumption:
␮␧ox W
ID = ᎏ ᎏ [2(VGS – Vtn)VDS – V 2DS]
2Tox L
W
ID = Kn ᎏ [2(VGS – Vtn)VDS – V 2DS]
L
= (100 ␮A) (3) [2(1.8 – 0.6) VDS – V 2DS]
= 300 ␮A [2.4 VDS – V 2DS]
This equation has two unknowns, so another equation must be found. We will
use the KVL statement,
VDD = IDR + VDS

ID = (VDD – VDS)/R
= (5 – VDS)/15 k⍀
The two equations can be equated to their ID solution, giving
(5 – VDS)
ᎏ = 300 ␮A(2.4 VDS – V 2DS)
15 k⍀
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After some algebra, this reduces to
V 2DS – 2.622VDS + 1.11 = 0
The two quadratic solutions are
VDS = 0.531 V, 2.09 V
The valid solution is VDS = 0.531 V, since this satisfies the nonsaturation condi-
tion that was used in its solution:
VGS > VDS + Vtn

1.8 V > 0.531 V + 0.6 V
and
ID = (VDD – VDS)/15 k⍀
= (5 V – 0.531 V)/15 k⍀
= 298 ␮A
왎
왎 EXAMPLE 3.4
What value of Rd will drive transistor M1 in Figure 3.15 just into nonsaturation if
Kn = 50 ␮A/V2, Vtn = 0.4 V, and W/L = 10?
Since the bias state is at the boundary, either Equation (3.3) or (3.4) can be
used. Equation (3.3) is simpler so
␮␧ox W W
2Tox L L
= (50 ␮A)(10)(1.0 – 0.4)2
= 180 ␮A
2.5 V
Rd
1.0 V
M1
Figure 3.15.
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The bias boundary condition
VGS = VDS + Vtn
becomes
VG – VS = VD – VS + Vtn
VD = VG – Vtn
VD = 1.0 V – 0.4 V = 0.6 V
Then
VDD – VD
Rd = ᎏ
ID
2.5 – 0.6
=ᎏ
180 ␮A
= 10.56 k⍀
왎
왎 EXAMPLE 3.5
Transistors emit light from the drain depletion region when they are in the satu-
rated bias state.
(a) Show whether this useful failure analysis technique will work for the cir-
cuit in Figure 3.16. Vtn = 0.6 V, Kn = 75 ␮A/V2, and W/L = 2.
(b) Find ID, VGS, and VDS.
The saturated bias condition is
VGS < VDS + Vtn
or
VG < VD + Vtn
1.2 V < 3.3 V + 0.6 V
so, transistor M1 is saturated and emitting visible light from its drain-channel re-
gion.
3.3 V
1.2 V
Rd
2 kΩ
Figure 3.16.
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Since M1 is in saturation,
␮␧ox W W
2Tox L L
= (75 ␮A)(2)[(VG – VS) – 0.6]2
= (150 ␮A)[(1.2 – VS) – 0.6]2
= (150 ␮A)(0.6 – VS)2
Also,
VS VS
ID = ᎏ = ᎏ
Rd 2 k⍀
Then,
VS
ᎏ = (150 ␮A)(0.6 V – VS)2
2 k⍀
This reduces to
VS2 – 4.533 VS + 0.36 = 0
whose two solutions are VS = 80.85 mV and 4.452 V. The valid solution is
VS = 80.85 mV
and
ID = IS = VS/Rd = 80.85 mV/2 k⍀ = 40.43 ␮A

VGS = 1.2 – 0.08085 = 1.119 V
VDS = 3.2 – 0.08085 = 3.119 V
왎
Self-Exercise 3.2
Find ID and VD in Figure 3.17. Verify the bias state consistency of your choice of
MOS drain-current model for Vtn = 1.0 V, Kn = 25 ␮A/V2, and W/L = 2.
10 V
50 kΩ
1.5 V
M1
Figure 3.17.
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Self-Exercise 3.3
Repeat Self-Exercise 3.2 (Figure 3.17) if VG = 3.0 V and W/L = 3.
Self-Exercise 3.4
Calculate VGS and give the correct bias state for transistor M1 in Figure 3.18. Vtn
= 0.5 V.
5V
4V
20 kΩ
M1
40 kΩ
Figure 3.18.
Self-Exercise 3.5
Adjust R1 in Figure 3.19 so that M1 is on the saturated/ohmic border where Vtn =

0.5 V.
5V
4V
20 kΩ
M1
R1
Figure 3.19.
Self-Exercise 3.6
Calculate R0 in Figure 3.20 so that V0 = 2.5 V. Given: Kn = 300 ␮A/V2, Vtn = 0.7
V, and W/L = 2.
5V
6V
M1
R0
Figure 3.20.
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3.1.6 pMOS Transistor Output Characteristics

pMOS transistor analysis is similar to that for the nMOS transistor with a major excep-
tion: care must be taken with the polarities of the current and voltages. The pMOS transis-
tor major carrier is the hole that emanates from the source, enters the channel, and exits
the drain terminal as a negative current. The gate-to-source threshold voltage Vtp needed
to invert an n-substrate is negative to attract holes to the channel surface. The equations to
model the pMOS transistor in saturation and nonsaturation conditions have a form similar
to those for the nMOS device, but modified for these polarity considerations. We will
choose a pMOS transistor equation form that is close to the nMOS transistor equations.
Equations (3.10) and (3.11) describe the terminal behavior of a pMOS device. Remember
that VGS, VDS, Vtp, and ID are negative.
␮␧ox W
ID = – ᎏ ᎏ (VGS – Vtp)2 (saturated state) (3.10)
2Tox L
␮␧ox W
ID = – ᎏ ᎏ [2(VGS – Vtp)VDS – V 2DS] (ohmic state) (3.11)
2Tox L
Figure 3.21 shows a measured pMOS transistor family of curves with all voltages given
with respect to the source. The plot is shown in quadrant I, even though the drain current
and voltage are negative. This is an author’s choice, made to to retain similarity to the
nMOS transistor family of curves.
The boundary of the bias states can again be found by differentiating Equation (3.11),
setting the result to zero, and solving for the conditions to get
VDS = VGS – Vtp (3.12)
The condition for transistor saturation is
VDS < VGS – Vtp or VGS > VDS + Vtp (3.13)
VG = -3.0 V
VG = -2.5 V
VG = -2.0 V
VG = -1.5 V
VG = -1.0 V
VG = -0.5 V
Figure 3.21. pMOS transistor family of curves.

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and the condition for transistor nonsaturation is
VDS > VGS – Vtp or VGS < VDS + Vtp (3.14)
An example is given using these equations.
왎 EXAMPLE 3.6
Determine the bias state for the pMOS transistors in Figure 3.22, where Vtp =
–0.4 V. The gate terminal has its most negative voltage with respect to the source
terminal.
2.5
2.5VV 1.5VV
1.5 -1.1VV
-1.1
00VV 1.3 V -2.5
-2.5VV
-2.3 V
-2.3 V 00 V
V
(a) (b) (c)
Figure 3.22. Transistors for Example 3.6, with Vtp = –1.2 V.
(a) VGS = –2.5 V and VDS = –2.5 V, therefore VGS > VDS + Vtp, or – 2.5 V > –
2.5 + (–0.4) V, so the transistor is in saturation.
(b) The gate voltage is not sufficiently more negative than either the drain or
source terminal so that the transistor is in the off-state.
(c) VGS = –2.5 – (–1.1) = –1.4 V and VDS = 0 – (–1.1) = 1.1 V. What is wrong?
The gate voltage is sufficiently negative to turn on the transistor, but the source-
to-drain voltage is negative. Holes must leave the source and flow to the drain,
but they can’t under this condition. The answer is that the drain terminal is on the
top and the source on the bottom so that VGS = –2.5 – 0 = –2.5 V and VDS = –1.1
– 0 = –1.1 V. Therefore VGS < VDS + Vtp, or – 2.5 V < –1.1 + (–1.2) V, so the tran-
sistor is in nonsaturation. The source terminal always has a higher or equal volt-
age than the drain terminal in a pMOS transistor. 왎
Self-Exercise 3.7
Give the correct bias state for the three pMOS’s shown in Figure 3.23, where Vtp
= –0.4 V.
2.2
2.2VV 2.3
2.3VV 0 0VV
0.8
0.8VV 0.5
0.5 V
V -- 0.4
0.4VV
3.5
3.5VV 1.11.1V
V
(a) (b) (c)
Figure 3.23.
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After solving Example 3.6 and Self-Exercise 3.7 with the proper bias state equations,
you may check your work by referring to the pMOS transistor family of curves in Figure
3.21. Find the coordinates in the example and exercise, and verify that the bias state is cor-
rect. A series of examples and exercises with the pMOS transistor will reinforce these im-
portant relations.
왎 EXAMPLE 3.7
Calculate ID and VDS for circuit in Figure 3.24. Vtp = –1.0 V, Kp = 100 ␮A/V2, and
W/L = 4.
5V
1.5 V
M1
Vo
200 Ω
Figure 3.24.
Assume a saturated bias state:
␮␧ox W
ID = – ᎏ ᎏ (VGS – Vtp)2 = –100 ␮A(4)[–3.5 – (–1)]2
2Tox L
= –2.5 mA
V0 = –ID(200 ⍀) = (2.5 mA)(200 ⍀) = 0.5 V
then
VDS = 0.5 V – 5 V = –4.5 V
The bias state consistency is
VGS > VDS + Vtp

–3.5 > –4.5 + (–1.0)
so the transistor is in the saturated bias state and the solutions are correct. 왎
왎 EXAMPLE 3.8
Calculate ID and VDS in Figure 3.25. Vtp = –0.6 V, Kp = 80 ␮A/V2, and W/L = 10.
Assume a saturated bias state:
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3.3 V
0V
M1
Vo
10 kΩ
Figure 3.25.
␮␧ox W
ID = – ᎏ ᎏ (VGS – Vtp)2 = –80 ␮A(10)[–3.3 – (–0.6)]2
2Tox L
= –5.832 mA
Then
V0 = –ID(10 k⍀) = –(–5.832 mA)(10 k⍀)

= 58.32 V
This voltage is beyond the power supply value, and is not possible. The saturated
state assumption was wrong, so we must start again using the ohmic state equa-
tion:
␮␧ox W
ID = – ᎏ ᎏ [2(VGS – Vtp)VDS – V 2DS] = –80 ␮A(10)[2(–3.3 + 0.6)VDS – V 2DS]
2Tox L
Another equation is required to solve the problem, so using the KVL (Ohm’s law,
here)
VD VDD + VDS
–ID = ᎏ = ᎏᎏ
Rd 10 k⍀
3.3 + VDS
= ᎏᎏ = 80 ␮A(10)[2(–3.3 + 0.6)VDS – V 2DS]
10 k⍀
The two quadratic solutions are: VDS = –75.70 mV and –5.450 V. The correct so-
lution is VDS = –75.70 mV. Therefore
V0 = 3.3 V + (–75.70 mV) = 3.224 V
왎 EXAMPLE 3.9
Calculate ID and VSD, and verify the assumed bias state of transistor M1 for the
circuit in Figure 3.26. Vtp = –0.4 V, Kp = 60 ␮A/V2, and W/L = 2.
c03.qxd 2/5/2004 4:49 PM Page 74
2.5 V
10 kΩ
1.2 V
M1
10 kΩ
Figure 3.26.
Assume a saturated bias state and
␮␧ox W
ID = – ᎏ ᎏ (VGS – Vtp)2
2Tox L
Since VGS is not known, we must search for another expression to supplement
this equation. We can use the KVL statement:
VGS = 1.2 – [VDD – (–IDRS)]

= 1.2 – 2.5 + IDRS
= –1.3 + (10 k⍀)ID
We equate this expression to the saturated current expression to get
ID = –60 ␮A(2)[–1.3 + (10 k⍀)ID + 0.4]2

= –120 ␮A[–0.9 + (10 k⍀)ID]2
This quadratic equation in ID gives solutions
ID = –35.56 ␮A and –227.8 ␮A
The valid solution is ID = –35.56 ␮A, since the other solution for ID, when multi-
plied by the sum of the two resistors, gives a voltage greater than the power sup-
ply. VSD is then
VSD = VDD – ID(20 k⍀)
VSD = ID(20 k⍀) – VDD
= 2.5 V – (35.56 ␮A)(20 k⍀)
= 1.789 V
and
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VS = VDD – IDRS = 2.5 + (–35.56 ␮A)(10 k⍀)

= 2.144 V
so that
VGS = VG – VS = 1.2 – 2.144 = –0.944 V
Transistor M1 is in saturation since
VGS > VDS + Vtp

–0.944 V > –1.789 V – 0.4 V
왎
왎 EXAMPLE 3.10
What value of Rd in Figure 3.27 will raise V0 to half of the power supply voltage
(i.e., V0 = 0.5 VDD). Vtp = –0.7 V, Kp = 80 ␮A/V2, and W/L = 5.
3.3 V
0V
M1
Vo
Rd
Figure 3.27.
Check for bias state consistency:
VGS < VDS + Vtp

–3.3 V < –1.65 V – 0.7 V
So M1 is in ohmic bias state. Therefore, we use the ohmic state equation, where
VDS = –1.65 V:
␮␧ox W
ID = – ᎏ ᎏ [2(VGS – Vtp)VDS – V 2DS]
2Tox L
= –80 ␮A(5){2[–3.3 – (–0.7)](–1.65) – 1.652}
= –2.343 mA
Then
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V0 1.65
Rd = ᎏ = ᎏᎏ = 704.2 ⍀
–ID 2.343 mA
Self-Exercise 3.8
Calculate ID and V0 for circuit in Figure 3.28. Vtp = –0.8 V, Kp = 30 ␮A/V2, and
W/L = 2.
5V
3.5 V
M1
Vo
100 kΩ
Figure 3.28.
Self-Exercise 3.9
Repeat Self-Exercise 3.8, but let VG = 1.5 V.
Self-Exercise 3.10
Find ID and V0 for the circuit in Figure 3.29. Vtp = –0.6 V, Kp = 20 ␮A/V2, and
W/L = 3.
- 2.2 V
M1
Vo
7.5 kΩ
-3V
Figure 3.29.
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3.2 THRESHOLD VOLTAGE IN MOS TRANSISTORS 77
Self-Exercise 3.11
The voltage drop across each of the two identical resistors and VDS are equal for
the circuit in Figure 3.30. Vtp = –0.5 V, Kp = 100 ␮A/V2, and W/L = 2. Find the
value of the resistors.
2V
0V
M1
-2V
Figure 3.30.
Self-Exercise 3.12
For the circuit in Figure 3.31, Vtp = –0.8 V and Kp = 100 ␮A/V2. What is the re-
quired W/L ratio if M1 is to pass 0.5 A and keep VSD < 0.1 V.
5V
0V
M1
Figure 3.31.
These many examples and exercises with MOS transistors have a purpose. These prob-
lems, when combined with transistor family of curves plots, should now allow you to
think in terms of a transistor’s reaction to its voltage environment. This is basic to elec-
tronics engineering instruction. It should allow you to quickly anticipate and recognize
aberrations caused by defective circuits, and later to predict what category of defect ex-
ists. The techniques needed to solve these problems should become reflexive.
3.2 THRESHOLD VOLTAGE IN MOS TRANSISTORS
Until now, we assumed that the transistor source and substrate terminals were connected
to the same voltage. This is valid for isolated transistors, but when transistors are connect-
ed in CMOS circuits, this condition may not hold for all devices.
Figure 3.32 is a circuit cross section of two nMOS and one pMOS transistors fabri-
cated in a CMOS process. All devices are constructed on the same p-type silicon sub-
strate. Since pMOS transistors are formed on n-type substrates, there must be a region
of the circuit that is oppositely doped to the initial bulk, forming what is called a well.
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Output
Output VDD
Input
InputBB VV
DDDD
Input
InputAA P2
GND
GND pMOS
pMOS B
nMOS
nMOSnMOS
nMOS
N2
n-Well
n-Well A N1
non
Non- field
Fieldoxide
Oxide
grounded
Grounded
grounded
Grounded source
Source GND
Substrate
Substrate(p-type)
(p-type) source
Source
(a) (b)
Figure 3.32. (a) Structure for two series-connected nMOS transistors and one pMOS transistor in a
CMOS technology. (b) Circuit schematic.
The p-type substrate for nMOS transistors is connected to zero (or ground, GND),
whereas the n-type well is connected to VDD, since it forms the bulk of the pMOS tran-
sistors. The source of the nMOS device N1 is connected to ground, so that previous
equations are valid for this device. The transistor N2 source is connected to the drain of
N1 to make a series connection of both devices, required to implement the operation of
the logic gate (a detailed analysis of transistor interconnection to form gates is given in
Chapter 5). As a result, the source of transistor N2 is not grounded, and it can acquire
voltages close to VDD, whereas its substrate is connected to ground through the polariz-
ing contact. Therefore, the condition VSB = 0 will not hold in some bias cases for tran-
sistor N2.
When the source and substrate voltages differ, the gate–source voltage is not fully re-
lated to the vertical electric field responsible for creating the channel. The effect of the
higher source voltage above (below) the substrate for an nMOS (pMOS) transistor is to
lower the electric field induced from the gate to attract carriers to channel. The result is an
effective raising of the transistor threshold voltage. The threshold voltage can be estimat-
ed as [8]
Vt = Vt0 ± ␥兹V
苶SB
苶 (3.15)
where Vt0 is the threshold voltage when the source and the substrate are at the same volt-
age, and ␥ is a parameter dependent on the technology. The parameter ␥ is called the body
effect constant. The positive sign is used for nMOS transistors, and the negative sign for
pMOS transistors. When the source and substrate are tied together, VSB = 0, and the
threshold voltage is constant.
The significance of the threshold body effect lies with certain circuit configurations
whose transistor thresholds will be altered, generally being higher than expected. This can
lead to conduction states and changes in transistor delay time. We will return to this topic
when we discuss pass transistor properties, particularly in memories, and circuits such as
that in Figure 3.32.
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3.3 PARASITIC CAPACITORS IN MOS TRANSISTORS 79
3.3 PARASITIC CAPACITORS IN MOS TRANSISTORS
We have learned the equations that describe the static operation of the transistor, i.e., the
current into the device when voltage nodes remain stable with time, but the dynamic oper-
ation requires knowledge of other aspects of the devices.
One limitation of high-speed digital ICs is the time required to switch a transistor be-
tween the on- and off-states. This delay mechanism is primarily due to transistor para-
sitic capacitors that fall into two types: voltage-dependent and non-voltage-dependent
capacitors. Non-voltage-dependent capacitors are characterized by physical overlap of
the gate terminal with the drain and source areas. The voltage-dependent capacitors are
the reverse-biased drain–substrate and source–substrate diodes, plus those characterized
by the creation of depletion regions and conducting channels [3]. Another significant
cause of delay in modern ICs is the capacitance of the interconnect wires between tran-
sistors.
3.3.1 Non-Voltage-Dependent Internal Capacitors

Non-voltage-dependent capacitor values are calculated from device dimensions using a
parallel plate model. A parallel plate capacitor has two conductors of area (A) separated
by a distance (d). The space between the conductors can be empty or filled with an insula-
tor to increase the capacitance value. The capacitance is
␧0␧m
Cp = ᎏ A
d冢冣 (3.16)
where ␧0 is the permittivity of free space, and ␧m is the relative permittivity of the materi-
al filling the capacitor. The non-voltage-dependent capacitors in a MOSFET device are
CGDov and CGSov shown in Figure 3.33. Their value is found by applying Equation (3.16)
to the overlap region between the gate and the drain.
␧0␧Si
冢
Cov = ᎏ W · LD
Tox 冣 (3.17)
Cgdov Cgsov Cgo
Cgb Cdep
Csb Cdb
(a) No bias applied (all terminals grounded) (b) Depletion or weak inversion
Cgs Cgd Cgs Cgd
Csb Cdb Csb Cdb
(c) Nonsaturation (d) Saturation
Figure 3.33. Parasitic capacitors of MOS transistors for four operating regions.
c03.qxd 2/5/2004 4:50 PM Page 80
where ␧Si is the relative permittivity of the silicon dioxide, W is the transistor width, LD is
the overlap distance between the gate and the drain or source, and Tox is the gate oxide
thickness.
3.3.2 Voltage-Dependent Internal Capacitors

Once the capacitor is biased, the depletion and inversion regions change the effective in-
ternal parasitic capacitors. These capacitors are voltage-dependent since their value is re-
lated to charge redistribution within the device. We will provide approximate expressions
for such capacitors.
In all operation regions, consider the following three terminal capacitors:
Cgb Gate–substrate (gate–bulk) capacitor. It has a strong dependence on the tran-

sistor biasing.
Cgs, Cgd Gate–channel capacitors. They are divided into gate–drain and gate–source
capacitors, since the channel distribution is not uniform along the device in
saturation.
Csb, Cdb Source and drain-to-bulk capacitors. Their capacitance is due to the reverse-
bias, built-in diodes.
The total voltage-dependent gate capacitance of a MOS is found by summing the capaci-
tors:
Cg = Cgb + Cgs + Cgd (3.18)
The drain/source-to-bulk capacitors do not impact the gate voltage. These capacitors can
be calculated from the reverse diode capacitor expression in Equation 2.12, so that
Cxb0
ᎏᎏ
Vxb 1/2
冢冣
Cxb = (3.19)
1 – ᎏᎏ
Vbi
where x must be replaced by d or s to refer to the drain and source terminals respectively.
The value of Cg must be computed for each transistor operation region.
No Biasing (All Terminals at the Same Voltage). The gate–substrate capacitance

is due to the MOS structure, and is calculated as a parallel plate capacitor filled by the
gate oxide. This “physical” capacitor is referred to as Cg0 and has the expression
␧0␧Si
Cgb = Cg0 = ᎏ W · Leff (3.20)
Tox
where Leff is the transistor effective length. It differs from the physical length L drawn in
the design because the drain and source regions diffuse under the gate making Leff =
–2Loverlap. The only difference between Equations (3.17) and (3.20) is the capacitor area.
In Equation (3.20) the area is that of the whole device, whereas in Equation (3.17) the area
was only the overlap region between the gate and the drain or source.
Depletion or Weak Inversion. Although conceptually different, depletion and weak

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3.4 DEVICE SCALING: SHORT-CHANNEL MOS TRANSISTORS 81
inversion will be treated as equivalent. In these regions, the gate voltage is not sufficient
to create a channel, and the electric field from the gate induces a depletion region within
the bulk (Figure 3.33(b)). The gate capacitor is the series connection of Cg0 and the deple-
tion capacitor Cdep. The computation of the depletion capacitance is complicated, and be-
yond the scope of this book.
Nonsaturation. When the transistor is in nonsaturation, the conducting channel

“touches” the drain and source terminals (Figure 3.33(c)). Thus, Cgs and Ggd dominate
and the gate–bulk capacitor is now negligible, since the conducting layer “disconnects”
the gate from the bulk. As a result, the gate–bulk capacitor Cg0 is shared between Cgd and
Cgs so
␧0␧Si
Cgs = Cgd = ᎏ W · Leff (3.21)
2Tox
Saturation. Once in saturation, the conduction channel no longer touches the drain end.
The gate–drain channel capacitance is now negligible, and all gate capacitances are con-
nected to the source terminal. The gate–source capacitance can be approximated as [8]
2␧0␧Si
Cgs = ᎏ W · Leff (3.22)
3Tox
The simplifications made in the computation of the gate capacitance are summarized in
Table 3.1.
Several forms of transistor capacitances have been described. Although we did not
stress numerical work, you should assimilate the locations and different properties of
each. Dynamic performance of an IC depends upon these capacitances, and also upon
parasitic resistances of the transistors and interconnect wires. The latter elements are dis-
cussed in Chapter 9. We will next explore the influence on the basic transistor properties
described thus far of the extreme scaling of dimensions of modern ICs.
3.4 DEVICE SCALING: SHORT-CHANNEL MOS TRANSISTORS
Device scaling is relentless in the microelectronics industry since transistor miniaturiza-

tion allows faster device operation, yield improvement, and cost savings resulting from
Table 3.1. Simplified Intrinsic MOS Capacitor Expressions for Each Operating Region
Cgb Cgs Cgd
␧0␧Si
Cutoff ᎏ W · Leff 0 0
Tox
␧0␧Si ␧0␧Si
Ohmic 0 ᎏ W · Leff ᎏ W · Leff
2Tox 2Tox
2␧0␧Si
Saturation 0 ᎏ W · Leff 0
3Tox
c03.qxd 2/5/2004 4:50 PM Page 82
more dies per wafer. There is an important barrier encountered when minimum dimen-
sions go below about 0.5 ␮m channel lengths since new device physical properties appear.
Devices with dimensions more than 0.5 ␮m are usually called long-channel devices,
whereas smaller transistors are called deep submicron or short-channel devices. The divi-
sion at 0.5 ␮m is slightly arbitrary, but gives an approximate dimension for entering the
short channel and deep submicron regions of electronics.
Figure 3.34 compares the output current characteristics for a long-channel transistor
(1.2 ␮m technology) and a submicron technology device (0.25 ␮m technology). The ma-
jor differences are
앫 The spacing between equally incremented drain–current versus gate–voltage curves

is constant in short-channel transistors in the saturation region, whereas the long-
channel transistor spacing between these curves increases nonlinearly for increasing
gate voltages.
앫 Once the device reaches saturation, the current remains nearly flat for the long-
channel device (it has small dependence on VDS for this region), whereas for the
short-channel transistor the saturated current shows more slope.
앫 The third difference relates to the total amount of current. If two transistors have
equal gate size and are at the same gate and drain voltage, then the short-channel
transistor passes more drain current than the long-channel one. This is largely due to
the thinner oxides used in short-channel transistors.
We will identify the mechanisms causing these differences, and present equations describ-
ing these behaviors for short-channel transistors. Short-channel transistor analysis has
more complexity than long-channel analysis. It requires detailed concentration on your
part, but we hope that you will obtain an understanding of the difficulty of manual analy-
sis of the sort similar to that for long-channel transistors. We acknowledge that we build
on the impressive work of others, such as Foty [2], Tsividis [7], and Weste and Eshraghian
[8].
There are many submicron effects, but we will focus on channel length modulation, ve-
locity saturation, subthreshold current, DIBL, and hot-carrier effects, since they may have
ID (A) ID (A)
(a) (b)
Figure 3.34. Current characteristics for (a) long-channel, and (b) short-channel transistors.
c03.qxd 2/5/2004 4:50 PM Page 83
a significant impact on IC testing and reliability. Our goal is to understand short-channel

effects, and develop tools that allow manual analysis as we did for long-channel transis-
tors.
3.4.1 Channel Length Modulation

Channel length modulation appears when the device is in saturation and is related to the
pinch-off effect described earlier. When the device reaches saturation, the channel no
longer “touches” the drain and acquires an asymmetric shape that is thinner at the drain
end (Figure 3.33(d)). As the drain–source voltage increases, the channel saturation or de-
pletion region moves further away from the drain end because the drain electric field
“pushes” it back. The reverse-bias depletion region widens, and the effective channel
length decreases by an amount ⌬L (Figure 3.35) for increasing VDS. In large devices, the
relative change of the effective channel length ⌬L with respect to the total channel length
with VDS is negligible, but for shorter devices ⌬L/L becomes important.
The effective length of the device varies with VDS once the device is in saturation, and,
as a result, the curves are no longer flat in this region compared to long-channel devices
(Figure 3.34(b)).
The small drain current dependence on the drain–source voltage in the saturation re-
gion can be modeled by multiplying the saturation current by a slope factor that depends
on this voltage. The resulting equation is
ID = IDsat(1 + ␭VDS) (3.23)
where ␭ is a parameter that can be measured for each particular technology.
3.4.2 Velocity Saturation

When charged carriers move in a solid under the force of an electric field, they acquire a
velocity proportional to the magnitude of this electric field. The applied electric field (Ᏹ)
and the carrier velocity (v) are related through the mobility parameter ␮, introduced in
Chapter 2 as
v = ␮Ᏹ (3.24)
For small electric fields, ␮ is constant and independent of the applied electric field.
∆L
L
Figure 3.35. The channel length modulation effect.

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␮ = ␮0 (constant) (3.25)
As a result when carrier velocity (v) is plotted versus the applied electric field (Ᏹ), the re-
sult is a straight line (low electric field region of Figure 3.36).
The reason for this linear dependence between velocity and small electric fields is that
electrons moving in semiconductors collide with silicon atoms, an effect known as scat-
tering. Electron scattering is linear with small electric fields. If the electric field further
increases, the carrier velocity enters a region in which it is said to move at velocity satura-
tion. As device dimensions scale down, the electric fields within the transistor increase,
making the velocity saturation more important. Velocity saturation due to mobility reduc-
tion is important in submicron devices.
If Equation (3.24) holds for carriers moving in small electric fields and carriers moving
at the velocity saturation, then the mobility ␮ must change with the electric field (Figure
3.36). Two effects are combined in transistors to account for this mobility: reduction due to
the horizontal electric field and mobility reduction due to the vertical electric field.
Horizontal Electric Field Mobility Reduction. Carriers in short-channel devices

reach velocity saturation at lower values of VDS than for long-channel transistors. Figure
3.37(a) illustrates the effect of VDsat moving toward small values, and shows that satura-
tion current is smaller in short-channel transistors. This effect is due to channel length re-
duction that implies higher horizontal electric fields for equivalent drain–source voltages.
The horizontal electric field within the channel is due to the voltage applied to the drain
terminal. Horizontal mobility (␮H) reduction can be related to the drain voltage by
␮0 ␮0
␮H = ᎏᎏ = ᎏᎏ (3.26)
VDS 1 + ␪2VDS
1 + ᎏᎏ
LeffᏱcrit
1/(LeffᏱcrit) is a parameter called drain bias mobility reduction that in some texts is re-
ferred to as ␪2. Ᏹcrit is the electric field shown in Figure 3.36, and depends on the technol-
ogy. For large transistors, ␪2VDS is smaller than 1, and, therefore, the mobility is constant
(␮H ⬇ ␮0), giving the linear relation between velocity and electric field for this region.
When Leff decreases (Leff 씮 0), ␪2 increases, and ␪2VDS becomes important, lowering the
mobility below ␮0. Even for short-channel transistors, when VDS is small, the denominator
Vsat Ᏹcrit
velocity
Carrier
µ = µ sat
µ = µo
High Electric field
Low (max. velocity)
Electric field
(constant slope)
Ᏹ (V/m)
Figure 3.36. Electric field to carrier velocity dependence in a solid.

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(a) (b)
Figure 3.37. Two effects of velocity saturation on submicron devices. (a) The saturation voltage
VDsat moves to lower values, and (b) the ID versus VGS relationship becomes linear.
of Equation (3.26) is almost equal to 1, and the mobility is constant. When VDS increases,
the denominator of Equation (3.26) becomes much larger than one, and the mobility is re-
duced. Equation (3.26) is a simple model of mobility reduction in submicron transistors
caused by the lateral (horizontal) electric field.
Vertical Electric Field Mobility Reduction. There is also a vertical electric field
due to the gate voltage that creates the conduction channel. When carriers move within
the channel under the effect of the horizontal field, they “feel” the effect of this gate–sub-
strate-induced electrical vertical field, pushing carriers toward the gate oxide. This pro-
vokes carrier collisions with the oxide–channel interface, reducing their mobility. The in-
terface of Si and SiO2 is rough and imperfect, so that carriers move with more difficulty.
The mobility reduction from this effect can be described in a similar way to that in the
horizontal field mobility reduction [Equation (3.26)]. Now, the expression of the vertical
mobility (␮V) reduction will contain the gate–source voltage instead of the drain–source
voltage:
␮0
␮V = ᎏᎏ (3.27)
1 + ␪1(VGS – Vt)
Similar to Equation (3.26), ␪1 is a parameter called gate bias mobility reduction that de-
pends on the technology.
3.4.3 Putting it All Together: A Physically Based Model

We discussed two mechanisms that impact transistor behavior when technology scales
down. Although other effects appear in submicron technologies, channel length modula-
tion and mobility reduction are the two main effects used in the device model equations in
CAD simulators. We now introduce model equations to describe the drain current of sub-
micron devices. The objective is to give the reader basic and accurate expressions to ac-
count for the most relevant submicron effects. Device modeling is an active research area.
For deeper discussions refer to [2] and [7].
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The long-channel transistor drain-current square law dependence on the gate–

source voltage for ohmic and saturation conditions are repeated from Equations (3.3) and
(3.4):
W V 2DS
冤
ID = ␮0Cox ᎏᎏ(VGS – Vtn)VDS – ᎏᎏ
L 2 冥 (ohmic)
(3.28)
W
ID = ␮0Coxᎏᎏ(VGS – Vtn)2 (saturation)
L
where Cox = ␧ox/Tox. These expressions can be modified to incorporate the effects de-
scribed previously for short-channel transistors.
Ohmic State. The ohmic region expression for short-channel devices is similar to
Equation (3.28), including the velocity saturation effects:
V 2DS
W (VGS – Vt)VDS – ᎏ ᎏ(1 + ␦)
2
ID = ␮0Cox ᎏ ᎏᎏᎏᎏ (3.29)
冢冣
Leff VDS
[1 + ␪1(VGS – Vt)] 1 + ᎏᎏ
LeffᏱcrit
Equation (3.29) combines the horizontal and vertical mobility reduction [the two expres-
sions in brackets of the denominator taken from Equations (3.26) and (3.27)]. The para-
meter ␦ relates the charge at the inversion channel to the surface potential and the oxide
capacitance, and will not be described in detail.
In addition to the drain current expression, we need an expression for the saturation
voltage VDsat that describes carrier saturation at smaller drain voltages (Figure 3.37(a)).
This saturation voltage depends on the gate voltage, and is calculated by differentiating
the drain current in the ohmic region [Equation (3.29) in this case] and setting the expres-
sion equal to zero. This leads to
2(VGS – Vt)
VDsat = ᎏᎏᎏᎏ (3.30)
冢冪莦莦莦莦莦莦莦莦莦莦莦冣
2(VGS – Vt)
(1 + ␦) 1 + 1 + ᎏᎏ
LeffᏱcrit(1 + ␦)
The short-channel drain saturation voltage depends on the square root of the gate voltage,
whereas for long-channel devices the term in the square root tends to 1, and the saturation
voltage depends on (VGS – Vt).
Saturated State (VDS > VDsat ). The short-channel drain current expression in satura-
tion is obtained from Equation (3.29), substituting VDS by VDsat and including the channel
modulation effect from Equation (3.23):
V 2Dsat
(VGS – Vt)VDsat – ᎏᎏ(1 + ␦)
W 2
ID = ␮0Cox ᎏ ᎏᎏᎏᎏ [1 + ␭(VDS – VDsat)] (3.31)
冢冣
Leff VD sat
[1 + ␪1(VGS – Vt)] 1 + ᎏ ᎏ
L e f Ᏹcrit
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Equations (3.29) and (3.31) describe the drain current of submicron MOS transistors for
the ohmic and saturated states, respectively. The transition of the drain current between
states described by these equations occurs sharply and can lead to computation errors
from derivative discontinuities. Equation (3.32) [7] describes the drain current for a MOS
transistor using only one expression, which is valid for ohmic and saturated states. It is
taken from Equation (3.31), where VDsat is substituted by VDS1. VDS1 is an internal drain
voltage that makes a smooth transition from VDS in Equation (3.29) to VDsat in Equation
(3.31) when changing from the ohmic state to the saturated one, as shown in Figure 3.38:
V 2DS1
(VGS – Vt)VDS1 – ᎏᎏ(1 + ␦)
W 2
ID = ␮0Cox ᎏ ᎏᎏᎏᎏ [1 + ␭(VDS – VDS1)] (3.32)
冢冣
Leff V
[1 + ␪1(VGS – Vt)] 1 + ᎏᎏ
Leff Ᏹcrit
Figure 3.38 shows that the internal voltage VDS1 is mainly the drain–source voltage for
small applied VDS. Once the device enters saturation, the internal drain–source voltage be-
comes VDsat.
Figure 3.39 compares measured drain current for nMOS and pMOS transistors versus
the drain current equation [Equation (3.32)], showing that the model fits the measured
transistor curves.
3.4.4 An Empirical Short-Channel Model for Manual Calculations

Equations (3.29) and (3.31) have a physical basis. They provide understanding of how
these physical effects impact the device characteristics, but lack simplicity for hand calcu-
lations. Another approach derives mathematical expressions that fit transistor curves over
both bias ranges. These expressions use empirical parameters to specifically match mea-
sured device characteristics. These parameters typically do not have a physical relation
with the underlying device mechanism, and are called fitting parameters (they fit a curve
with a mathematical expression).
Empirically based models afford the possibility of deriving a mathematical expression
for hand calculations. This section introduces an empirical model for short-channel tran-
VDS1
VDsat
High
Low Electric Field
Electric Field (saturation)
(linear dependence)
VDS
Figure 3.38. Internal drain–source voltage versus applied drain source voltage [VDS1 in Equation
(3.29)].
c03.qxd 2/5/2004 4:50 PM Page 88
ID (A) ID (A)
(a) (b)
Figure 3.39. Comparison of experimental data (diamonds) with the drain current model of Equa-
tion (3.32) (lines) for submicron (a) n-type and (b) p-type transistors.
sistors applicable for manual calculations. These equations can compute voltage and cur-
rent in simple circuits with just a few transistors. This is valuable when computing electri-
cal parameters in small circuits in which fabrication defects are present. This empirical
model is based on the Sakurai model [5].
We begin with the transistor in saturation. The model introduces a maximum current pa-
rameter ID0 that is the current when VDS = VGS = VDD (VDD is the maximum voltage in the
circuit). The drain current in saturation has a small linear dependence with the drain volt-
age. This dependency is described with a second parameter, ␭, similar to Equation (3.23).
Finally, we know that the drain current has a quadratic dependence with the gate volt-
age for long-channel devices and a linear dependence for submicron devices [Figure
3.37(b)]. To account for this variation, we use a third fitting parameter called ␣ (taken
from Sakurai [5]). This parameter is equal to 1 for short-channel devices and equal to 2
for long-channel transistors, and can be somewhat related to carrier velocity saturation. A
mathematical expression for the drain current in saturation is
冢冣 [1 + ␭(V
VGS – Vth ␣
ID = ID0 ᎏᎏ DS – VDD)] for VDS > VDsat (3.33)
VDD – Vth
We “constructed” this equation to fulfill these conditions:
앫 The drain current is equal to ID0 when VGS = VDD and VDS = VDD.
앫 The drain current dependence on the drain–source voltage is linear with slope ␭.
앫 When ␣ = 1 (submicron transistors), the drain current dependence with the gate
voltage is linear, and for large devices the dependence is quadratic (␣ = 2).
Equation (3.33) was constructed to fit experimental results. None of the parameters intro-
duced are founded on physical phenomena in the transistor, although we could provide a
physical meaning for some of them.
Equation (3.33) holds when the drain voltage is beyond the saturation voltage VDsat that
is empirically defined as
c03.qxd 2/5/2004 4:50 PM Page 89
冢冣
VGS – Vth ␣/2
VDsat = VD0 ᎏᎏ (3.34)
VDD – Vth
where VD0 is the saturation voltage when VDS = VGS = VDD, and the exponential depen-
dence with ␣/2 was observed experimentally.
We next need an expression for the drain current in nonsaturation. In this region,
drain current has a quadratic dependence on the drain voltage, and when VDS = VDsat its
value must match the current value for saturation from Equations (3.33) and (3.34). This
gives
冢冣冢冣 [1 + ␭(V
VDS VDS VGS – Vth ␣
IDS = 2 – ᎏ ᎏ ID0 ᎏᎏ Dsat – VDD)] for VDS < VDsat (3.35)
VDsat VDsat VDD – Vth
We introduced no new parameters for this region. The reader can easily verify that Equa-
tions (3.35) and (3.33) have the same expression for VDS = VDsat. It is also easy to verify
that for ␭ ⫽ 0 there is a slope discontinuity at this point. A discontinuity is not desirable
for models used in CAD tools or simulators because convergence problems must be
avoided. In our case, the aim of this model is hand calculations in which this problem does
not arise.
Combining both expressions and neglecting subthreshold leakage:
0 when VGS < Vth
冦冢2 – ᎏ 冣ᎏ I 冢冣 [1 + ␭(V
D0 ᎏᎏ Dsat – VDD)] when VDS < VDsat (3.36)
V VDsat Dsat VDD – Vth
ID =
冢冣 [1 + ␭(V
VGS – Vth ␣
ID0 ᎏᎏ DS – VDD)] when VDS ⱖ VDsat
VDD – Vth
with VDsat given by Equation (3.34).

Figure 3.40 compares experimental data for a submicron process (0.25 ␮m) and the
ID (A) ID (A)
(a) (b)
Figure 3.40. Comparison of experimental data for (a) nMOS, and (b) pMOS short-channel transis-
tors with the empirical model of Equation (3.36).
c03.qxd 2/5/2004 4:50 PM Page 90
empirical model. The fitting parameters are ␣ = 1.12, ID0 = 13.46 mA, VD0 = 1 V, ␭ = 0.08,
VDD = 2.25 V, and Vth = 0.64 V.
왎 EXAMPLE 3.11
Calculate ID and VDS for the circuit in Figure 3.41 using the empirical model
with the parameters ␣ = 1.12, ID0 = 13.46 mA, VD0 = 1 V, ␭ = 0.08, and Vth = 0.64
V.
2.25 V
200 kΩ
2V
Figure 3.41.
First, find the region of operation for the device. We initially assume that the
device is in saturation. From Equation (3.33), the drain current would be
冢冣 [1 + ␭(V
VGS – Vth ␣
ID = ID0 ᎏᎏ DS – VDD)]
VDD – Vth
冢冣
2 – 0.64 1.12
= 13.46 mA ᎏᎏ [1 + 0.08(VDS – 2.25)]
2.25 – 0.64
= (9.136 + 0.8914VDS) mA
Applying KVL to the circuit,
VDD = VDS + IDR

VDS = VDD – IDR
VDS = 2 V – ID 200 ⍀
Solving both equations:
VDS = 0.147 V
We must verify that the device is in saturation, so we calculate VDsat and make
sure that VDS > VDsat. Using Equation (1.34),
冢冣
VGS – Vth ␣/2
VDsat = VD0 ᎏᎏ
VDD – Vth
c03.qxd 2/5/2004 4:50 PM Page 91
冢冣
2 – 0.65 0.56
= 1 ᎏᎏ
2.25 – 0.65
= 0.91 V
since VDS < VDsat, the device is in the ohmic region. We must recalculate the
drain current using Equation (3.35):
冢冣冢冣 [1 + ␭(V
ID = 2 – ᎏ ᎏ ID0 ᎏᎏ DS – VDD)]
VDSsat VDSsat VDD – Vth
2.25 – VDS
Combining with ID = ᎏᎏ
200
12.01V 2DS – 26.86VDS + 11.5 = 0
Solving with the KVL equation derived above we get
VDS = 0.56 V and VDS = 1.68 V
This solution is valid for the device to be in ohmic state. Therefore, the solution
of the problem is
ID = 8.47 mA
VDS = 0.56 V
왎
Self-Exercise 3.13
Repeat the problem of Example 3.11 with VGS =1.5 V.
Self-Exercise 3.14
Repeat the problem of Example 3.11 with VGS = 0.75 V.
Short-channel transistors require specific constants for each technology, and they are
not intuitive. As a result, many engineers still use long-channel equations for the “back of
the envelope” estimations, acknowledging the increased error. Computers use complicat-
ed models to obtain accurate results [2], but do not give a feel for the underlying electron-
ic physics. This conflict of rapid, more inaccurate hand calculations versus accurate com-
puter calculation is unavoidable. We need an accurate approach, and we need an approach
that rapidly gives us insight into physical behavior.
3.4.5 Other Submicron Effects

MOSFET devices show other effects when scaled down. We will not give analytical de-
scriptions for these effects, but will briefly introduce them. The effects are: subthreshold
current, drain-induced barrier lowering (DIBL), and hot carrier effects.
c03.qxd 2/5/2004 4:50 PM Page 92
Subthreshold Current. Subthreshold current is the drain–source current when the

gate–source voltage is below the transistor threshold voltage. The threshold voltage distin-
guishes the conduction from the nonconduction states of a MOS transistor. This gives the
threshold voltage a vague definition. The transition from the conducting to the noncon-
ducting state is not sharp, but continuous. This means that when the gate–substrate volt-
age increases, the charge in the channel is not created abruptly, but appears gradually with
VGS. There is a range of gate voltages lower than Vt for which there are carriers in the in-
version layer that contribute to the drain current. In this region, the number of carriers that
constitute the channel varies exponentially with the gate voltage.
We want no current when the transistor is in the off-state, i.e., when the gate voltage is
below the threshold voltage. If Vt is large so that |VGS| < |Vt|, then the number of carriers
into the channel approaches zero. However, a high Vt increases the time required to switch
between the on and off conducting states, resulting in slower devices.
Smaller transistors require lower operating voltages to restrict the internal electric field
within reasonable margins. This in turn requires lowering the threshold voltage to main-
tain the operating speed of the device. This tendency is used in today’s processes to main-
tain circuit performance at the cost of power increase. Modern devices show considerable
current leakage even at VGS = 0.
Threshold voltage reduction increases transistor leakage since an appreciable sub-
threshold current occurs during the off-state of the transistor. The subthreshold current can
be easily observed from the device characteristics by plotting the logarithm of ID versus VGS
for the subthreshold region (Figure 3.42). The subthreshold slope (St) is the amount of gate
voltage required to increase the drain current one decade and is measured from Figure 3.42.
Subthreshold current has impact at the circuit level, since it is a fixed current contribu-
tion from all devices in the off-state. A subthreshold current of 10 nA at VGS = 0 is in-
significant for a single device, but in a 100 million transistor circuit the impact on the
overall power consumption can be significant. Some technologies have MOSFETs with
two different Vt’s to reduce this problem. This separates the design into high-speed and
low-speed transistors. High speed devices with lower Vt contribute higher leakage, and are
1.0e-4
1.0e-5
1.0e-6
1.0e-7
ID (A)
1.0e-8
1.0e-9
1.0e-10
1.0e-11
1.0e-12
0 0.2 0.4 0.6 0.8 1
VGS (V)
Figure 3.42. Effect of the subthreshold current in submicron devices.

c03.qxd 2/5/2004 4:50 PM Page 93
used in critical delay paths or circuit blocks that must operate at high speed. Circuit blocks
that do not require high speed are designed with high Vt transistors, and contribute less to
the overall leakage.
Drain-Induced Barrier Lowering (DIBL). The population of channel carriers in

long-channel devices is controlled by the gate voltage through the vertical electric field,
whereas the horizontal field controls the current between the drain and the source. In
large-channel devices, the horizontal and vertical electrical fields can be treated as having
separate effects on the device characteristics. When the device is scaled down, the drain
region moves closer to the source, and its electric field influences the whole channel. In
this situation, the drain-induced electric field also plays a role in attracting carriers to the
channel without control from the gate terminal. This effect is called drain-induced barrier
lowering (DIBL), since the drain lowers the potential barrier for the source carriers to
form the channel. The threshold voltage “feels” the impact of this effect on the transistor
curves. Since DIBL attracts carriers into the channel with a loss of gate control, DIBL
lowers the threshold voltage and increases off-state leakage.
An expression of the subthreshold leakage of a MOSFET including DIBL is given by
Chandrakasan et al. [1]:
Isubth = A · e(1/nVT)VGS–Vt0–␥ · VS+␩ · VDS) · (1 – e–VDS/VT) (3.37)
with
W
A = ␮0 · Cox ᎏ (VT)2e1.8e–⌬VTH/␩VT (3.38)
L
where ␮0 is the zero bias mobility, VT = kT/q is the thermal voltage, ␥ is the linearized body
effect coefficient, ␩ is the DIBL coefficient, and n is the subthreshold swing coefficient.
The term ⌬VTH is introduced to account for transistor-to-transistor leakage variations.
Hot Carrier Effects. In saturation, carriers crossing from the inverted channel pinch-off
point to the drain travel at their maximum saturated speed, and so gain their maximum ki-
netic energy. These carriers collide with atoms of the bulk, causing a weak avalanche effect
that creates electron–hole pairs. These carriers have high energy, and are called hot carriers.
Some carriers interact with the bulk, giving rise to a substrate current. Hot carriers can
significantly affect reliability since some of these carriers generated by impact ionization
have enough energy to enter the gate oxide and cause damage (traps) in the SiO2 region.
The accumulation of such traps can gradually degrade device performance, change the
device Vt, and can increase conduction through the oxide, giving rise to oxide wearout and
breakdown. This phenomena and its effects are detailed in Chapter 6.
Very Short Channel Devices. When the channel length is drastically reduced, the
horizontal electric field increases and the effects of velocity saturation become much
stronger. Horizontal mobility reduction becomes more important than vertical mobility
reduction, and the drain saturation voltage is reduced. In these cases, Equation (3.32) can
be rewritten neglecting the quadratic term in the drain internal voltage (VDS1) since it is
very small, and considering only the horizontal mobility effect (since it becomes predom-
inant), leading to
c03.qxd 2/5/2004 4:50 PM Page 94
W (VGS – Vt)VDS1
ID ⬇ ␮0Cox ᎏ ᎏᎏ VDS1 (3.39)
Leff 1 + ᎏ ᎏ
LeffᏱcrit
and for VDS1/(LeffᏱcrit) Ⰷ 1 gives
ID ⬇ WCox(VGS – Vt)␮Ᏹcrit (3.40)
This assumption and the result states that for very short channel devices, carriers are al-
ways velocity saturated, and the drain current does not depend on the transistor length.
Equations (3.32) and (3.40) apply to transistors saturated and ohmic states under the as-
sumption that VDS1/(LeffᏱcrit) Ⰷ 1.
3.5 SUMMARY
This chapter examined MOSFET transistors using the physical description of semicon-
ductors and diodes in Chapter 2. Transistor operation was explained with figures showing
the interaction of gate, drain, source, and bulk regions with external bias, minority carrier
inversion, and diodes. Abundant examples with nMOS and pMOS transistors model equa-
tions emphasized reflexive approaches to analyze circuits with transistors and resistors.
The chapter closed with descriptions of the body effect and short-channel transistors. A
modeling approach was given for short-channel transistors that stretches the outer limit of
manual calculations for transistors.
REFERENCES
1. A. Chandrakasan, W. Bowhill, and F. Fox (Eds.), Design of High-Performance Microprocessor

Circuits, IEEE Press, 2001.
2. D. Foty, MOSFET Modeling with SPICE, Prentice-Hall, 1997.
3. R. F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley, 1996.
4. J. Rosselló and J. Segura, “Charge-based analytical model for the evaluation of power consump-
tion in submircrometer CMOS buffers,” IEEE Transactions on Computer Aided Design, 21, 4,
433–448, April 2002.
5. T. Sakurai and R. Newton, “Delay analsysis of series-connected MOSFET circuits,” IEEE Jour-
nal of Solid-State Circuits, 26, 122–131, February 1991.
6. Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.
7. Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd ed., McGraw-Hill, 1999.
8. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993.
EXERCISES
3.1. For the three circuits in Figure 3.43, (a) give the transistor bias state, (b) write the
appropriate model equation, and (c) calculate ID, where Vtp = –0.4 V and Kp = 100
␮A/V2.
3.2. Repeat the same steps as in the previous exercise if Vtn = 0.4 V and Kn = 200 ␮A/V2
(Figure 3.44).
c03.qxd 2/5/2004 4:50 PM Page 95
EXERCISES 95
10 V 2V 2V
2V 2V 2V
8 kΩ 18 kΩ 12 kΩ
2 kΩ 2 kΩ 8 kΩ
Figure 3.43.
10 V 2V 2V
2V 2V 2V
8 kΩ 18 kΩ 12 kΩ
2 kΩ 2 kΩ 8 kΩ
Figure 3.44.
3.3. Given Vtp = –0.6 V and Kp = 75 ␮A/V2, and W/L = 5 (Figure 3.45), (a) solve for
source voltage VS, (b) solve for drain voltage.
3V
4 kΩ
3V
2 kΩ
Figure 3.45.
3.4. Given the circuit in Figure 3.46 and the transistor parameters of Problem 3.2, (a)
find the value of RD to satisfy V0 = 1.2 V. (b) As VDD drops, find the value of VD at
the transition point where the transistor enters saturation and the new value of VDD.
3.5. The transistor parameters in the circuit in Figure 3.47 are: Vtp = –0.5 V, Kp = 75
␮A/V2, and W/L = 4. If V0 = 1.2 V, what is VIN?
c03.qxd 2/5/2004 4:50 PM Page 96
1.5 V
RD
Vo
1.5 V
Figure 3.46.
2V
50 kΩ
Vo
VIN
Figure 3.47.
3.6. Calculate VG in Figure 3.48 so that ID = 200 ␮A, given that Vtn = 0.8 V and Kn = 100
␮A/V2, and W/L = 4.
5V
VG
Vo
5 kΩ
Figure 3.48.
3.7. Given that R1 = R2 and Kn = 200 ␮A/V2, determine the resistance values in Figure
3.49 so that VD = 1 V and VS = –1 V.
3.8. Given Vtp = –0.6 V, Kp = 50 ␮A/V2, W/L = 3, and VD = 0.8 V. If V0 = 1.2 V, what is R
in Figure 3.50?
c03.qxd 2/5/2004 4:50 PM Page 97
EXERCISES 97
3V 3V
R1 100 kΩ
0V 2V Vo
R2 R
-3V
Figure 3.49. Figure 3.50.
3.9. In the circuit in Figure 3.51 Vtp = –0.6 V, Kp = 75 ␮A/V2, and W/L = 2. (a) What val-
ue of R will place the transistor on the boundary between saturation and ohmic? (b)
If R doubles its value, what are ID and V0?
3V
2V
Vo
Figure 3.51.
3.10. The pMOSFET in Figure 3.52 has Vtp = –0.5 V, Kp = 150 ␮A/V2, and W/L = 3, and
a body effect constant ␥ = 0.1. The bulk voltage is at –0.3 V. (a) Calculate ID. (b) If
VIN = –1 V, find ID.
2V
1V - 0.3 V
Figure 3.52.
3.11. Repeat Exercise 3.7 using the empirical model of Equation (3.36) with ␣ = 1.14, ID0
= 14 mA, VD0 = 1 V, ␭ = 0.08, and Vth = 0.64 V.
c03.qxd 2/5/2004 4:50 PM Page 98
3.12. MOS transistors have two forms of capacitance. Describe each type and where you
find them in the device.
3.13. What are the major differences between a short-channel transistor and a long-chan-
nel transistor?
3.14. Determine V0 in the circuit of Figure 3.53, assuming that the topmost device is long
channel, while the bottom one is short channel and needs the empirical model of
Equation (3.36). Use: VIN = 1.5 V, Vtn(up) = 0.4 V, Vtn(dwn) = 0.3 V, Lup = 2 ␮m, Wup =
30 ␮m, Kup = 0.9 mA/V2, ID0 = 5 mA, ␣ = 1.2, ␭ = 0.09, and VD0 = 1V.
2V
Vo
VIN
Figure 3.53.
3.15. Observe the log ID versus VGS curve in Fig. 3.22.

(a) Define subthreshold current for short channel transistors
(b) Why is subthreshold current in short channel transistors a problem in advanced
CMOS technologies
3.16. Describe how DIBL lowers Vt in short channel transistors.

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CHAPTER 4
CMOS BASIC GATES
4.1 INTRODUCTION
This chapter describes the electronics of basic logic gates, starting with the CMOS in-
verter whose simple appearance hides its complexity. Knowledge of inverter properties
leads to knowledge of larger gates, such as NAND and NOR gates and their complicat-
ed properties. We will relate CMOS digital circuits to logic behavior and to CMOS
failure mechanisms that typically involve small defects that alter normal inverter prop-
erties.
CMOS logic gates are digital cells, meaning that they perform Boolean algebra and
their input and output voltages take one of the two possible logic states (high/low or 1/0).
The output logic states have terminal voltages that respond to a range of input voltages but
map into one of the two logic states. For example, a 1 V power supply technology has
nominal output logic levels of 1 V (high) and 0 V (low). However, the input may range
from 0 V to 0.3 V and the output still remains at a logic high of about 1 V.
This mapping of an input voltage range to a logic state gives noise immunity to digital
circuits that is a major difference between analog and digital circuits. A small voltage
fluctuation in an analog circuit node can cause significant error in the output signal. The
same fluctuation in digital ICs is tolerated if it remains within the assigned range, and no
error occurs.
There is a third range of digital voltage levels that is not mapped to any logic state.
These voltages are between the logic levels, and they occur during an input/output voltage
transition. None of the circuit nodes take these voltages in a normal or quiescent operation
state since they have no logic meaning.
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100 CHAPTER 4 CMOS BASIC GATES
4.2 THE CMOS INVERTER
An inverter circuit converts a logic high-input voltage, such as 1 V, to a low logic voltage
of 0 V (or 0 V to 1 V). The electronic symbol and truth table are shown in Figures 4.1(a)
and (b). The Boolean statement is Vout = V⬘in. The nMOS and pMOS transistors of the
CMOS inverter (Figure 4.1(c)) act as complimentary switches. A logic high-input voltage
turns on the nMOS transistor, driving the output node to ground, and also turns off the
pMOS transistor. A low input voltage turns on the pMOS transistor and the nMOS off dri-
ving the output node to a high voltage.
Boolean values are read in the quiescent state that occurs when all signal nodes settle
to their steady-state values. Only one inverter transistor is on connecting the output termi-
nal Vout to one of the power rails, and there is no current in the circuit since the other tran-
sistor is off, thus eliminating a DC path between the rails. A capacitor load CL is shown in
Figure 4.1(c) as it is unavoidable in any circuit. The capacitance is from transistor node
and wiring capacitances and does not affect static properties, but hinders the speed of log-
ic transitions. We will analyze the static and dynamic operation.
4.2.1 Inverter Static Operation

Voltage Characteristic. The static voltage characteristic measures the logic gate input
and output voltage over the whole voltage range. This curve defines the voltage levels
mapped to each logic state. Figure 4.2 shows an inverter static voltage transfer curve (Vout
versus Vin). Noise margin refers to the amount of input signal variation allowed before the
output voltage shows significant change. Noise margins are often simplistically defined at
the points of the curve where the slope is –1. There are five bias state regions correspond-
ing to the transistor operating regions.
These five regions are:
1. Region I. nMOS off, pMOS ohmic. This voltage range exists for Vin < Vtn. The
nMOS transistor is off, and the pMOS transistor is driven into nonsaturation since
VGS ⬇ –VDD < VDS + Vtp (see Equation 3.14). The pMOS drain node at Vout is
pulled up to a logic high VDD through the low impedance of the pMOS channel.
2. Region II. nMOS saturated, pMOS ohmic. Vin goes just above the nMOS threshold
voltage (Vin > Vtn), and the nMOS transistor is barely turned on and in saturation
VDD
Vin
in Vout
out
VVin
in VVout VinVin Vout
out
0 1 Vout
0 1
11 00 CL
(a) (b) (c)
Figure 4.1. Inverter (a) symbol, (b) truth table, and (c) schematic.
c04.qxd 2/2/2004 12:25 PM Page 101
4.2 THE CMOS INVERTER 101
1.8
1.6
1.4
1.2
Vout (V)
0.8
Region I Region II Region IV Region V
0.6
Region III
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Vin (V)
Figure 4.2. Inverter Vin versus Vout current transfer curve with five bias states.
(VDS = Vout > Vin – Vtn). Current now passes through both transistors and Vout drops
as Vin is increased. The pMOS transistor remains in the ohmic state, but with de-
creasing gate drive.
3. Region III. nMOS saturated, pMOS saturated. When the output voltage goes be-
low Vin – Vtp and remains above Vin – Vtn, the nMOS and pMOS transistors are
both in saturation, and the region has a straight line. Since Vout and Vin are linear-
ly related, analog amplification occurs here. The drain voltage is a faithful replica
of small changes in the input waveform, but amplified by a value equal to the
slope of the straight line. MOS analog circuit designs use this property. It is also
good for digital circuits that demand rapid Vout change during logic transitions of
Vin. A digital goal is to get through the transition region as quickly as possible,
and what better way than to have the circuit behave as an amplifier.
4. Region IV. nMOS ohmic, pMOS saturated. As Vin further increases, it approaches
a value such that the difference between Vin and VDD is close to the pMOS tran-
sistor threshold voltage. This is similar to Region II, but the roles of the transis-
tors are reversed. The pMOS transistor is in saturation and the nMOS enters non-
saturation.
5. Region V. nMOS ohmic, pMOS off. When Vin goes to a logic high voltage, then Vin
Ⰷ Vout + Vtn. The pMOS transistor is turned off, and the nMOS transistor is in its
ohmic state pulling the drain voltage Vout down to the source ground.
Inverter logic threshold voltage (Vthr) is the point at which Vin = Vout. Vthr is typically
near VDD/2. This is a unique condition since Vin = Vout occurs only once in the inverter
voltage range. The logic state changes as Vin moves through Vthr. Vthr is important when
analyzing defect properties in CMOS circuits, since many defects cause intermediate
voltages at some circuit nodes. Whether these defects cause a logic malfunction depends
on the logic threshold voltage and the input voltage. Voltages slightly less than the log-
c04.qxd 2/2/2004 12:25 PM Page 102
ic high voltages and slightly more than logic low voltages are called weak logic volt-
ages. Weak logic states are read correctly, but noise margins and gate driving voltages
are compromised.
Except for Region I and Region V, the point at which transistors change from one zone
to another depends on the inverter input and output voltages (Regions I and V depend only
on the input). The input voltage at which these changes occur depends on the relative siz-
ing of the devices, since the transistor width-to-length dimension (W/L) determines the
current for a given gate–source voltage and, therefore, the effective equivalent resistance
between drain and source.
In practice, input and output voltage ranges differ partly due to design and partly due to
electrical noise. Figure 4.3 shows the voltage levels for the logic high and low values at a
gate input and output. The following terms are defined
VIL = input low voltage: maximum input voltage recognized as a logic low.
VIH = input high voltage: minimum input voltage recognized as a logic high.
VOL = output low voltage: maximum voltage at a gate output for a logic low for a
specified load current.
VOH = output high voltage: minimum voltage at a gate output for a logic high for a
specified load current.
These voltage-based logic levels define the noise margin or immunity needed when con-
necting logic gates. Noise Margin (NM) is a parameter obtained from these levels and is
defined for each logic value. NMH and NML for the high and low logic values are
NMH = VOH – VIH

NML = VIL – VOL
Noise margins must be positive for proper logic operation and the higher these values, the
better the circuit noise immunity. These parameters are an essential measurement during
production testing of ICs. Board designers must know that ICs that connect to each other
are within specification and interface properly.
The logic threshold voltage of a CMOS inverter is set by the pMOS and nMOS transis-
tor width and length ratios in the aspect ratio (Wp/Lp)/(Wn/Ln) [see Figure 3.1(a)]. Usually,
both transistors have the same channel length set by the minimum value of the technology.
Vin Vout
VDD
VOH
NMH
VIH
VIL
NML
VOL
GND
Figure 4.3. Voltage ranges mapped to logic Boolean values.

c04.qxd 2/2/2004 12:25 PM Page 103
Therefore the Wp/Wn ratio determines the inverter logic threshold voltage. Inverters are
often designed for a symmetric static transfer characteristic, so that the Vout versus Vin
curve intersects the unity–gain line Vin = Vout at about VDD/2. A symmetrical transfer
curve denotes a circuit with equal pullup and pulldown current drive strength. The aspect
ratio giving a symmetric transfer characteristic for constant gate oxide thickness is
冢冣
2Vtn 2
1 – ᎏᎏ
Wp ␮n VDD
ᎏ=ᎏ ᎏᎏ (4.1)
Wn ␮p 2|Vtp|
1 – ᎏᎏ
VDD
Equation (4.1) is found by equating the saturation current for nMOS and pMOS transis-
tors and setting the input voltage equal to VDD/2. If it is possible for the technology to have
␮n = ␮p, and Vtn = |Vtp|, then a symmetric inverter requires Wn = Wp. In practice, electron
and hole mobility are never equal, and the threshold voltages of nMOS and pMOS transis-
tors have slightly different absolute values. Symmetrical CMOS inverter designs often
have (Wp/Wn) ⬇ 2 to compensate for the smaller hole mobility in pMOS transistors.
Self-Exercise 4.1
Compute the ratio between nMOS and pMOS transistor width to obtain a sym-
metric inverter for a 0.18 ␮m technology in which ␮n = 360 cm2/V · s, ␮p = 109
cm2/V · s, Vtn = 0.35 V, and Vtp = –0.36 V with VDD = 1.8 V.
The inverter logic threshold voltage can be made smaller or larger within the range Vtn
< Vthr < VDD+Vtp by setting the ratio Wp/Wn above or below the value of Equation (4.1).
Vthr = 0.5VDD when the pull-up and pull-down transistor current drive strength are equal.
If Vthr < 0.5VDD then the nMOS pull-down transistor is stronger than the pull-up. If Vthr >
0.5VDD then the pMOS pull-up is stronger.
Current Characteristic. The DC power supply current transfer curve is equally im-
portant. Figure 4.4 shows the IDD versus Vin characteristic. At Vin < Vtn in Region I, the
nMOS transistor is off and no current passes through the circuit. When Vin = VDD in Re-
gion V, the pMOS transistor is off and, again, no current passes from the power supply to
ground. Typical inverter current at these quiescent logic levels is in the low pA’s and is
mostly drain–substrate reverse-bias saturation current or subthreshold current (Chapters
2–3). Virtually no power is dissipated in the quiescent logic states, giving CMOS ICs their
traditional technology advantage. The peak current near VDD/2 depends upon transistor
drive strength (the size of the width-to-length ratio). Both transistors are in the saturated
state and the current peaks. When an inverter changes logic state, the transient current is
wasted power. Peak currents in large microprocessor designs are many Amperes, as this is
the sum of the transient currents of millions of logic gates.
Transistor off-state leakage in deep submicron technologies is a concern and the ma-
jor cause is the intentional threshold voltage reduction needed to maintain circuit per-
formance. Deep submicron ICs must reduce VDD to contain the internal electric fields
and power dissipation, but Vt is kept at about 15%–25% of VDD to ensure strong gate
overdrive voltage. The design tradeoff is stronger gate overdrive (faster IC) with lower
Vt versus significantly higher off-state leakage (higher off-state power). Total IC off-
c04.qxd 2/2/2004 12:25 PM Page 104
Figure 4.4. Inverter power supply current transfer curve.
state leakage can approach Ampere levels when high-speed performance is the dominant
issue. Subthreshold current rises rapidly when Vt is lowered. One solution reduces off-
state leakage by using transistors with different threshold voltages in the same circuit.
This technique uses low Vt transistors in the speed-critical paths and high Vt devices in
the noncritical paths. Another approach uses high Vt transistors to disconnect logic gates
(designed with low Vt devices) from the power supply when they are inactive. Low Vt
transistors have higher performance and higher leakage, whereas high Vt devices are
slower with smaller leakage current.
Graphical Analysis of Bias Regions. Figure 4.5 distinguishes the bias state regions
with the voltage transfer function and two 45° lines. The lower unity–slope line separates
the bias condition, mutually satisfying saturation and nonsaturation for an nMOS:
VGS = VDS + Vtn (4.2)
or
Vin = Vout + Vtn ⇒ Vout = Vin – Vtn (4.3)
Equation (4.3) is a straight line superimposed on the voltage transfer curve in Figure 4.5
and labeled as (a). All points on the transfer curve lying above line (a) represent the
nMOS transistor in saturation or the off-state. All points below line (a) represent the
nMOS transistor in the ohmic state. A similar derivation leads to the pMOS transistor bias
boundary line labeled (b) in Figure 4.5. The pMOS transistor is saturated or off for all
points on the curve below line (b) and in the ohmic state above line (b). Both transistors
are saturated in the region between the two lines.
c04.qxd 2/2/2004 12:25 PM Page 105
Figure 4.5. Inverter transfer curves and transistor state.
왎 EXAMPLE 4.1
Figure 4.6 is an inverter transfer curve. Estimate Vtn and Vtp using bias line con-
cepts.
Figure 4.6. CMOS inverter voltage transfer curve.
Put a small mark on the ends of the linear region in Figure 4.6 and draw 45°
lines. The threshold values are the intercepts. Vtn = 0.42 V and Vtp = –0.44 V. 왎
Graphical analysis allows visualization of transistor states during logic transitions. The
maximum gain region is where both transistors are saturated, as seen between the two dot-
ted bias lines (a, b) in Figure 4.5. An example emphasizes this thinking.
c04.qxd 2/2/2004 12:25 PM Page 106
왎 EXAMPLE 4.2
When Vout switches in an inverter from VDD to 0 V, estimate the fraction of this
voltage range (VDD) for which the nMOS transistor is in saturation. Let Vtn =
0.2VDD, Vtp = –0.2VDD, and K⬘n = K⬘p, where K⬘n = Kn (W/L)n, and K⬘p = Kp (W/L)p.
We know IDn = –IDp for all the points in the static curve and also the point on
line (a) in Figure 4.5 where the nMOS transistor leaves saturation. At this point,
both transistors can be treated as in the saturation state. This is the transition be-
tween Regions III and IV in Figure 4.2. So,
K⬘n(VGS – Vtn)2 = K⬘p(VGS – Vtp)2

K⬘n(Vin – Vtn)2 = K⬘p(VDD – Vin – Vtp)2
Solve for
K⬘n
Vin = ᎏᎏᎏ
冪莦莦
VDD + Vtn ᎏᎏ – Vtp
K⬘p
K⬘n
冪莦莦
1 + ᎏᎏ
K⬘p
Substituting
Vin = Vout + Vtn
into the above Vin equation:
VDD – Vtn – Vtp

Vout = ᎏᎏ
K⬘n
1 + ᎏᎏ
冪莦莦
K⬘p
Substituting
K⬘n = K⬘p, Vtn = 0.2VDD, and Vtp = –0.2VDD
then
Vout = 0.5VDD
at the transition point.

The fraction is
VDD – Vout
ᎏᎏ = 0.7 = 70%
VDD
The point is made that for these conditions, the nMOS and pMOS transistors are
individually in saturation for about 70% of the transition and jointly in saturation
for about 40%. This has strong implications for failure analysis and design de-
bug tools.왎
c04.qxd 2/2/2004 12:25 PM Page 107
CMOS inverter theory underlies failure analysis, test, and reliability electronics. For
example, Chapter 3 described drain region light (photon) emission when a transistor was
saturated. The high electric field of the drain depletion region accelerates channel charge,
causing impact ionization and subsequent photon emission. Figure 4.5 shows where and
when light is expected in the inverter. During normal logic transitions, light is emitted
from the nMOS transistor in the saturated state region above line (a). The pMOS transistor
emits light in the region below line (b). Both transistors emit light in the region between
lines (a) and (b). The IBM PICA timing path analyzer with 15 ps timing resolution is
based on these principles [7]. Failure analysts must know when defects force a transistor
into an inadvertent saturated bias state, causing light emission [4]. Visible light from a de-
fect location is an efficient failure analysis tool that, in addition to locating a defect re-
gion, says that a transistor is in its saturated state (or a diode is breaking down) with a
weak gate and drain voltage. Failure analysts must describe defect properties consistent
with all electrical clues.
Self-Exercise 4.2
A CMOS inverter has transistor parameters: Kn (W/L)n = 265 ␮A/V2, Kp (W/L)p

= 200 ␮A/V2, Vtn = 0.55 V, Vtp = 0.63 V, and VDD = 2.5 V. (a) For what fraction of
the total output voltage swing will the nMOS transistor be in saturation. (b)
Same question for the pMOS transistor. (c) What fraction will both be in satura-
tion at the same time.
Self-Exercise 4.3
Estimate the voltage analog gain for the inverter whose transfer curve is in Fig-
ure 4.5
4.2.2 Dynamic Operation

The transfer curve of Figure 4.2 gives essential inverter information, but does not repre-
sent the circuit behavior during its rapid transition. The switching time for modern invert-
ers can be a few tens of picoseconds, and parasitic capacitance of the transistors and the
external wiring load alter the phase relation between Vin and Vout. An inverter and its
transfer curve phase relation are drawn in Figure 4.7 for different input speed transitions,
showing that for rapid transitions, the drain voltage lags input gate voltage.
The circuit model for the inverter dynamic analysis in Figure 4.7(a) shows two para-
sitic capacitors that are important during the transition. The input–output capacitor (called
the coupling capacitor Ccoup) comes from the gate–channel device capacitance that is
strongly bias-dependent and the overlapping gate–drain capacitors from both the nMOS
and pMOS devices. For high-speed transitions, the coupling capacitor tries to maintain its
initial voltage difference between the input and the output (–VDD for a low–high input
transition and VDD for a high–low one). This temporarily drives the output voltage beyond
VDD (overshoot) for an input rising transition and below ground for a falling edge (under-
shoot). This induces noise in the supply (ground) node while increasing transition delay
since the output voltage swing is higher than VDD.
c04.qxd 2/2/2004 12:25 PM Page 108
V
Vin V
Vout
out
in
C
CCLL
Ccoup
coup L
Figure 4.7. (a) Dynamic CMOS inverter circuit model, and (b) transfer curves for high-to-low out-
put and low-to-high output for different input ramp speeds.
Curves (2) and (3) in Figure 4.7(b) correspond to very high speed input transistors and
show that the output drain node remains at a relatively high voltage when the gate input
has almost completed its transition. The same phenomena holds when the gate input
switches rapidly from high to low. The drain remains in a low-voltage state until the input
has almost completed its transition. The circuit parasitic capacitances cause this phase re-
lation. The slow transition response of the static curve allows time for the drain nodes to
exactly follow the input gate voltage in time. Curve (1) is an intermediate case for a medi-
um speed input transition, in which the output is beyond VDD/2 when the input reaches its
final value, although it is far from the almost-static transfer curve.
This effect is more important at the beginning of the transition since for a rising
(falling) input swing the nMOS (pMOS) device is off until Vin = Vtn (Vin = VDD + Vtp).
During this period, the output voltage is disconnected from ground (supply) and there is
no pull-down (pull-up) element to compensate for the charge injected from the input. This
effect is shown in Figure 4.8 for the input and output voltage evolution for high–low and
low–high input transitions.
Three parameters determine the duration and magnitude of overshoot (undershoot):
1. The value of the input–output coupling capacitance. The larger the capacitance, the
more charge is transferred to the output during the input rising (falling) transition
and the higher (lower) the output voltage overshoot (undershoot).
2. The input transition time. The charge injection from the input to the output through
the coupling capacitance depends on the time derivative of the input voltage (i = C
dV/dt). The shorter the input transition times, the higher the overshoot or under-
shoot.
3. The width of the nMOS (pMOS) transistor. Overshoot (undershoot) occurs at the be-
ginning of the input transition, since the nMOS (pMOS) device is off and does not
pull down (pull up) the output voltage. Once the input voltage goes beyond (below)
Vtn (VDD + Vtp) the nMOS (pMOS) device turns on and pulls the output voltage
c04.qxd 2/2/2004 12:25 PM Page 109
Vin
1.5
1
V (V)
0.5
Vout
0
0 10 20 30 40 50
t (ps)
Figure 4.8. Time evolution of the input and output voltage of an inverter for an input high–low and
low–high transitions. The output voltage exceeds the power and ground levels during the transition.
down (up). The larger the W/L, the larger its current drive and the smaller the time
required to pull down (pull up) the output.
The inverter output capacitance is the sum of the drain diffusion capacitance, intercon-
nect wiring, and the input capacitance of the load gates. The transition time is sensitive
to the load capacitance since the output must be charged–discharged during the transi-
tions. Figure 4.8 also illustrates the definition of logic gate propagation delay time TPD,
which is the time between the input and output waveform measured at the 50% ampli-
tude points.
4.2.3 Inverter Speed Property

The dynamic relation between the input and the output voltages defines the different oper-
ating regions, but in the dynamic case the input voltage transition time does not uniquely
determine the output voltage transition time. Sometimes, the input reaches its final value
while the output voltage is still close to its initial value because the transistor that must
sink or source current is too small compared to the output load. Different situations ap-
pear depending on transistor-to-load capacitance sizing.
Figure 4.9 plots the output voltage responses for different values of the output capaci-
tance when the input low–high transition time is fixed. Curve V03 corresponds to a small
output capacitor, and the output voltage is almost zero when the input reaches VDD. This
case is similar to the static transfer curve. In curve V02, the output voltage is equal to Vin –
Vtn when the input voltage reaches VDD, whereas in curve V01 the output is still above that
value when the input gets to its steady state. In all cases, the output voltage initially goes
beyond VDD due to overshoot caused by the charge injected from the input through the
coupling capacitor. During this period, there is current from the output node through the
pMOS transistor back to the supply terminal. In none of the three cases does the output
voltage start to decay until the input voltage goes beyond Vtn at time t = tn. Fast and slow
input ramps can distinguish the operating regions of the nMOS transistor when the input
voltage reaches VDD. In Curve V03, the nMOS device is in its linear region when the input
c04.qxd 2/2/2004 12:25 PM Page 110
Figure 4.9. Different cases for a dynamic inverter transition.
transition is finished, whereas in curve V01 this transistor is still saturated when Vtp reach-
es VDD.
Curve V01 is interesting because the pMOS transistor never passes a positive current.
When overshoot ceases and the output voltage goes below VDD, the input is below Vtp and
the pMOS is off. This condition results in a slight reduction in power consumption.
An exact calculation of the propagation delay of an inverter requires a complex differ-
ential equation. We derive a simple formulation, assuming that the device is an ideal cur-
rent source (i.e., the transistor is always in saturation).
The speed with which an inverter switches logic states depends on Vtn, Vtp, VDD, W/L,
temperature, and the coupling and load capacitances. A simple model shows these para-
meters that affect inverter rise and fall time. The current source I0 in Figure 4.10(a) repre-
sents the MOS transistor in saturation since that bias state dominates the transition time
and CL is the load capacitance. The Shockley MOSFET model is
␮nCox W
I0 = ID = ᎏ ᎏ (VGS – Vtn)2 (4.4)
2 L
VV
IIo0
VVout
out VVout
out ∆V
⌬V²= =
VDD
VDD
IIo0
CL CL
C
C L L
tt
⌬t==τ␶
∆t
(a) (b)
Figure 4.10. (a) Circuit model to estimate rise and fall delays in a CMOS inverter, and (b) voltage
response of capacitor to constant current.
c04.qxd 2/2/2004 12:25 PM Page 111
50
40
30
τD (ns)
20
10
0
0 1 2 3 4 5 6
VDD (V)
Figure 4.11. Delay versus supply voltage for the model in Equation (4.8).
The capacitor expression for current, voltage, and time from Chapter 1 is
dV(t)
i(t) = CL ᎏ (4.5)
dt
If i(t) = I0 (a constant current) and we approximate dv(t)/dt = ⌬V(t)/⌬t, then
I0
⌬V(t) = ᎏ ⌬t (4.6)
CL
If ⌬t is the delay time ␶D in Figure 4.10(b) for the signal to rise to ⌬V(t) = VDD, then Equa-
tion (4.6) is rewritten as
CLVDD
␶D = ᎏ (4.7)
I0
Equation (4.7) adequately matches experimental data [2]. Substituting Equation (4.4) into
Equation (4.7) with VGS = VDD gives
2L 1
␶D = CLVDD ᎏ ᎏᎏ2 (4.8)
W␮nCox (VDD – Vtn)
Equation (4.8) shows that time delay is geometrically related to the difference in VDD and
Vt. Figure 4.11 plots the time delay versus VDD for CL = 20 fF, ␮nCox = 150 ␮A/V 2, Vt =
0.5 V, and W/L = 2. Time delay asymptotically approaches infinity as VDD approaches Vt.
Self-Exercise 4.4
If a pMOS transistor has ␮nCox = 56 ␮A/V 2, Vtp = –0.6 V, and W/L = 6, what is
the expected additional time delay if the gate VDD is reduced from a normal VDD
= 2.5 V to VDD = 1.8 V with CL = 25 fF?
c04.qxd 2/2/2004 12:25 PM Page 112
20
15
τD (ns)
10
0
0 0.5 1 1.5 2 2.5 3
Vt (V)
Figure 4.12. Delay versus threshold voltage for the model in Equation (4.8).
The result is similar if Vt varies for a fixed VDD. Figure 4.12 is a plot similar to Figure
4.11, but with time delay plotted against Vt. These figures illustrate why deep submicron
technologies strive for low Vt. This is a complicated trade-off for logic speed against the
increase in off-state leakage current when Vt is lowered. Chapter 3 discussed these mech-
anisms.
왎 EXAMPLE 4.3
It is given that CL = 10 fF, ␮nCox = 118 ␮A/V2, W/L = 6, and VDD = 2.3 V. Initial-
ly, Vt = 0.6 V. If Vt is reduced to 0.2 V, what is the percent decrease in speed and
what is the percent increase in IOFF if subthreshold slope of ID versus VG is 83
mV/decade?
You can substitute the values into Equation (4.8) and take the ratio or divide
Equation (4.8) by itself, substituting Vt = 0.6 V and Vt = 0.2 V. You get
␶D(Vt = 0.6 V) (2.3 – 0.2)2

ᎏᎏ = ᎏᎏ2 = 1.526
␶D(Vt = 0.2 V) (2.3 – 0.6)
The threshold setting of Vt = 0.6 V slows the transistor by about 53%

The reduction is Vt affects the off-state leakage current by shifting the log (ID)
versus VG curve to the right by (0.6 V – 0.2 V) = 400 mV (see Chapter 3). The in-
crease in off-state leakage current is
400 mV
ᎏᎏ = 4819 decades ⇒ 65.96 × 103
83 (mV/decade)
The off-state leakage is increased over four orders of magnitude. A battery-oper-

ated circuit, such as a watch or pocket calculator, would choose the higher
threshold voltage setting as speed is not a concern and power reduction is. 왎
Equation (4.8) is valid for long-channel devices, since the current expression in Equa-
tion (4.4) has a quadratic dependence on the gate voltage. An analysis for deep-submicron
c04.qxd 2/2/2004 12:25 PM Page 113
devices substitutes any of their equations for the drain current into Equation (4.7). In this
case, the delay is approximately [1]
CLVDD
␶D = K ᎏᎏ (4.9)
(VDD – Vtn)
K is a constant that depends on device size and technology parameters. The main differ-
ence is the inverse dependence on VDD instead of the inverse square in Equation (4.9). Al-
though deep-submicron delay appears larger than for long-channel transistors, the transis-
tor thin oxide (TOX) is much smaller, reflecting a larger value of K in Equation (4.8).
4.2.4 CMOS Inverter Power Consumption

The energy dissipated by an inverter has static and dynamic components. Dynamic dissi-
pation is due to the charge–discharge of the gate output load capacitance (transient com-
ponent) and to the short-circuit current from the supply to ground created during the tran-
sition. Static dissipation for long-channel transistors is due mainly to reverse bias
drain–substrate (–well) pn junction leakage current from transistors in the off-state. The
deep-submicron off-state current is mostly subthreshold leakage, and it dominates with
technology scaling, since the threshold voltage Vth is reduced to maintain circuit perfor-
mance [6]. Gate oxide tunneling current in ultrathin oxides also contributes significantly
to IC off-state leakage. The dynamic power calculation requires computation of transient
and short-circuit components.
Transient Component. The dynamic power (Pd) to charge and discharge a capacitor
CL for a period T of frequency f is
1
Pd = ᎏ
T
冕 i (t)v (t)dt
0
T
L 0 (4.10)
In one period interval, the output voltage changes from 0 to VDD and vice-versa. Equation
(4.5) relates the current and voltage of the output capacitor, so Equation (4.10) is rewritten
as
冤冕冕
1 VDD 0
Pd = ᎏ
T 0
CLv0dv0 +
VDD
CL(VDD – v0)d(VDD – v0) 冥 (4.11)
giving
2
CLV DD
Pd = ᎏ = CLV DD
2
f (4.12)
T
Equation (4.12) shows that transient power can be lowered by reducing the output capaci-
tance, the supply voltage, or the operating frequency. Since the power dependence on the
supply voltage is quadratic, lowering VDD is more efficient for reducing power dissipation
than the other two parameters.
Short-Circuit Component. When the input is changing and its voltage is between Vtn
and VDD – |Vtp|, then both transistors are simultaneously conducting creating a current
c04.qxd 2/2/2004 12:25 PM Page 114
path from VDD to ground. This power component (Psc) depends on device size, input tran-
sition time, and the output and coupling capacitors that consume about 10%–20% of the
overall power. It was recently shown that the ratio of the short-circuit to the dynamic cur-
rent remains constant for submicron technologies if the ratio Vth/VDD is constant. The ex-
act computation is complex, so we present an approximation.
Consider a symmetric inverter (i.e., Kn⬘ = Kp⬘, and Vtn = –Vtp) with no output load and an
input voltage transition having equal rise and fall times. The time interval when both tran-
sistors simultaneously conduct is from t1 to t3 in Figure 4.13. During the interval t1 – t2,
the short-circuit current increases from zero to its maximum value Imax. Since the nMOS
transistor is saturated during this period, its drain current is Equation (4.4)
I = Kn⬘(Vin – Vtn)2 for 0 < I < Imax
where
␮nCox W
Kn⬘ = ᎏ ᎏ (4.13)
2 L
Since the inverter was assumed to be symmetric with no load, the maximum current oc-
curs at Vin = VDD/2 and its shape is symmetric along the vertical axis at t = t2. We compute
a mean current by integrating from t = 0 to t = T and dividing by the period T. There are
four equal area current segments to integrate in Figure 4.13 over the whole period T:
1
Imean = ᎏ
T
冕 I(t)dt = ᎏT4 冕 K ⬘(V (t) – V ) dt
0
T t2
t1
n in t
2
(4.14)
If the input voltage is a linear ramp of duration ␶,
VDD
Vin = ᎏ t (4.15)
␶
t1 and t2 are given by

Vt ␶
t1 = ᎏ ␶ and t2 = ᎏ (4.16)
VDD 2
isc
VDD
VDD - |Vtp|
Vin
Vtn
t1 t2 t3 t=T
t=0
Figure 4.13. A simplified view of the short-circuit current contribution.

c04.qxd 2/2/2004 12:25 PM Page 115
Substituting (4.15) and (4.16) into (4.14)
冕冢
Imean = Kn⬘
␶/2
ᎏ
Vt
VDD
␶
VDD
冢
ᎏ t – Vt
冣 ␶ 冣 dt
2
(4.17)
This integral is of the type 兰xdx with x = (VDD/␶)t – Vt, so the result is
1 Kn⬘ ␶
Imean = ᎏ ᎏ (VDD – VT)3 ᎏ (4.18)
6 VDD T
Finally, the power contribution is given by

Psc = VDDImean
Power Supply Scaling. The ratio of Vt to VDD impacts several inverter properties.
Equation (4.4) is repeated:
␮n␧ W
ID = ᎏ ᎏ (VGS – Vtn)2 (4.19)
2Tox L
VGS = VDD for logic circuits, so that Equation (4.19) becomes
␮n␧ W
ID = ᎏ ᎏ (VDD – Vtn)2 (4.20)
2Tox L
When VDD drops, several things happen:
앫 The voltage difference in the parentheses (the gate overdrive) is smaller, so the cur-
rent drive is lower.
앫 When VDD < (Vtn – Vtp) ⬇ |2Vt| the transition still occurs, but only one transistor is
on at a time. There is essentially no transient current spike. Figure 4.14 shows a
transfer curve at VDD = 1 V and VDD = 0.5 V for transistors with thresholds on the
order of 0.35 V. There is no current spike for the VDD = 0.5 V measurement since
VDD < 2 × |Vt|. Vin was swept from 0.5 to 0 V. The power reduction for this condition
is large. Low-power, battery-operated products such as electronic watches and med-
ical implants use this technique.
앫 The fraction of the Vin sweep in which both transistors are simultaneously on also
drops, reducing the peak IDD current.
There is a trade-off between power savings and delay increase when reducing the supply
voltage. Technology scaling includes thinner gate oxides, forcing lower voltages to contain
the gate oxide and drain–substrate electric fields to subcritical values. We present some ap-
proaches to power supply voltage scaling that focus on reliability, speed, or energy–delay.
Reliability Driven Supply Scaling. The most general voltage scaling trades off long-
term reliability, operating speed, and energy. Circuit speed increases with higher VDD but
the higher device electric fields increase carrier velocity, creating more hot carriers. Hot
carriers contribute to oxide degradation and can limit circuit lifetime. It is possible to de-
c04.qxd 2/2/2004 12:25 PM Page 116
Figure 4.14. Inverter transfer curves at two VDD values. Notice the absence of a short-circuit cur-
rent spike for VDD = 0.5 V, where Vin was swept from 0.5 to 0 V.
velop a model in which circuit delay and hot carrier effects are included and from which
an optimum power supply can be determined [2].
Technology Driven Supply Scaling. Transistor current drive in the saturated state for
submicron technologies is not quadratic but linear. It is dominated by carrier velocity sat-
uration (vmax), as explained in Chapter 3 through Equation (3.40). Since vmax = ␮Ᏹcrit,
Equation (3.40) is rewritten as
I = WCox(VDD – Vt)vmax (4.21)
The first-order delay model of Equation (4.7) with this current expression gives a delay
almost independent of the supply voltage, provided that carriers move at the velocity satu-
ration vmax i.e., at high electric fields. Mathematically, this implies that VDD – Vt ⬇ VDD
and VDD vanishes in the delay equation. A “technology” based criterion chooses the pow-
er supply voltage based on the desired speed–power performance for a given deep-submi-
con technology [5]. The relative independence of delay on supply voltage at high electric
fields allows voltage reduction for a velocity-saturated device with little penalty in speed
performance. This concept of operating above a certain voltage was formalized by Kaka-
mu and Kingawa [5], where the concept of a “critical voltage” was developed.
Energy–Delay Minimum Supply Scaling. Another approach reduces the voltage sup-
ply by minimizing the energy–delay product [2]. For a fixed technology, there is a supply
voltage that trades off the quadratic dependence of energy and the increased circuit delay.
4.2.5 Sizing and Inverter Buffers

A speed design problem exists when a signal passes through a series of logic gates. A fast
charge–discharge of a load capacitor requires large W/L of the driving transistors. Howev-
c04.qxd 2/2/2004 12:25 PM Page 117
er, the large W/L is defeating since its large gate area increases the load capacitance for its
own driving logic gate. Working backward, that would cause all preceding logic gates to
have ever larger W/L ratios. A better solution exists.
A better approach for driving large loads at high speed uses successively larger channel
widths in a cascade of inverters to sufficiently increase the current drive of the last stage.
A circuit driving a large load is commonly known as a buffer, and a circuit designed with
successive inverters is known as a tapered buffer (Figure 4.15). When the area of each
stage increases by the same factor, the circuit is called a fixed-taper buffer, and if this ra-
tio is not constant it is called a variable-taper buffer.
The fixed-taper buffer structure was proposed by Linholm in 1975 [8]. He used a sim-
ple capacitance model, making the output load of a stage proportional to the size of the in-
put capacitance of the next stage, while the area of each inverter was proportional to the
channel width of the transistors. The overall buffer delay was optimized by minimizing
the delay of each stage. A better result is obtained if the system delay is considered instead
of individual stages.
Let each succeeding stage in the buffer in Figure 4.15 have transistor widths larger
than the previous one by a factor ␣. The first inverter is the smallest, with an input capac-
itance Cin, whereas the ith stage has an input capacitance given by
Ci = ␣i–1Cin i = 1, 2, . . . , n (4.22)
The number of stages n is computed from
CL = ␣nCn (4.23)
then
CL
␣n = ᎏ (4.24)
Cin
and
ln (CL/Cin)
n = ᎏᎏ (4.25)
ln ␣
␣ is computed by optimizing the delay. Assuming that the delay of the first stage driving
an identical one is ␶0, the delay of the ith stage is
tdi = ␣␶0 i = 1, 2, . . . , n (4.26)
1 α α2 αi-1 αn-1
Vout
Vin
Cin CL
Ci = αi-1 Cin
Figure 4.15. Tapered buffer structure.

c04.qxd 2/2/2004 12:25 PM Page 118
The global delay of the n stages is

n
td = 冱 tdi = n␣␶0 (4.27)
i=1
giving
␣
冢冣
CL
td = ln ᎏ ᎏ ␶0 (4.28)
Cin ln ␣
Differentiating (4.28) with respect to ␣ and equating to zero, the optimum ␣opt is
␣opt = e ⬇ 2.7 (4.29)
and the optimum number of stages nopt is
nopt = ln (CL/Cin) (4.30)
Other buffer designs addressed power dissipation, circuit area, and system reliability,
many of them leading to results different than shown here. Additionally, more accurate
models for capacitance and delay estimation exist. Methods exist that consider interrelat-
ed issues of circuit speed, power dissipation, physical area, and system reliability [3]. The
point of this section is to impress upon the reader that care must be taken in a design when
a logic gate of one size and capacitance drives a logic gate of larger size and capacitance.
4.3 NAND GATES
CMOS technology implements negated functions. This means that the output signals, al-
though controlled by many input lines, are inverted with respect to one or more control-
ling inputs. Simple examples are the inverter, the NAND gate, and the NOR gate.
A 2NAND gate symbol and truth table are shown in Figures 4.16(a) and (b). There are
two properties to note. The first is that any logic 0 to the inputs of a NAND gate causes
logic 1 output. The other property is more subtle, but vital to logic design and testing ICs.
Certain input levels are called noncontrolling states. When A = 1 in rows 3 and 4, then the
A
A B
B C
C
A 00 00 11
A C 00 11 11
B C
1 0 1
B
1 1 0
(a) (b)
Figure 4.16. (a) 2NAND gate symbol and (b) truth table.
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4.3 NAND GATES 119
output C is the negation or complement of B (C = B⬘). The output C depends only on the
value of B if A = 1. If B = 1, C is the complement of A. IC testing requires that signal in-
formation from specific nodes be read at an output pin without interference from the oth-
er input lines of that gate. The property is essential for passing specific logic values deep
in the logic blocks to an observable circuit node such as an output pin.
When a NAND gate input is set to logic 1, then the effects of that signal node are neu-
tralized with respect to signals on the other input lines. For example, if a fault were sus-
pected on the input of B, then a test pattern would drive a signal to B and measure C, but
ensure that node A = 1. The noncontrolling logic state for an AND gate is also logic 1.
왎 EXAMPLE 4.4
If in Figure 4.17 you want to examine the signal at (a) node B, what should node
I1 be set to? (b) To examine node A, what should I2 and I3 be set to? (c) To exam-
ine node I3, what should I1 and I2 be set to?
I1 A
O1
I2 B
I3
Figure 4.17.
(a) To pass a signal from node B to the output O1 requires that node A is set at
logic 1. Therefore I1 must be logic 0.
(b) To pass a signal from node A to the output O1 requires that node B is set at
logic 1. Therefore I2I3 must be 00, 01, or 10.
(c) To pass a signal from node I3 to the output O1 requires that node I2 be set
at logic 1 and I1 is set at logic 0. 왎
Figure 4.18 shows the 2NAND gate transistor schematic. The electronic operation fol-
lows the truth table in Figure 4.16(b). A logic 0 on any input line turns off an nMOS pull-
down transistor and closes the path from the output VC to ground. A logic 0 ensures that a
pMOS is turned on. Therefore, for any logic 0 on the inputs, the output is at logic 1, or VC
= VDD. If both logic inputs are logic 1 (VA = VB = VDD), then both nMOS transistors turn
on, both pMOS transistors are off, and VC = 0 V. The noncontrolling logic state for a
NAND (and AND gate) input node is logic 1. AND gates can be made by adding an in-
verter to the output of a NAND gate.
The NAND gate has most of the inverter properties developed in Sections 4.1.2–4.1.5.
If we set input B in Figure 4.18 to its noncontrolling state VB = VDD, then a voltage sweep
at node A produces static and dynamic transistor curves similar to those measured for the
inverter and shown in Figures 4.2 and 4.7.
Inverter speed and power properties apply to the NAND gate with minor exceptions.
The goal of matching inverter rise and fall times led to design of Kn⬘ = Kp⬘. This was done
c04.qxd 2/2/2004 12:25 PM Page 120
VDD
A
B
C
CL
Figure 4.18. Transistor level structure of a static CMOS NAND gate.
by making (W/L)p > (W/L)n by a factor of about 2–3.3 depending upon the technology.
This ratio compensates for the lower pMOS transistor carrier mobility. The NAND gate
has more input signal possibilities to deal with if equal rise and fall times are desired. The
pull-up current drive strength depends upon the number of pMOS transistors that are acti-
vated. Two parallel pMOS transistors have twice the pull-up strength of a single pMOS.
Also, when the pull-down path is activated, two series nMOS transistors have about half
the current drive strength of just a single nMOS. Compromises are made with NAND gate
pMOS transistors and, typically, the (W/L)p ratios are not as large as the nMOS transistor
(W/L)n ratios of inverters.
4.4 NOR GATES
A NOR gate symbol and truth table are shown in Figures 4.19(a) and (b). There are
again two properties to note. The first is that any logic 1 to the inputs of a NOR gate
causes a logic 0 output. The noncontrolling states are different than the NAND and AND
gates. When A = 0 in rows 1 and 2, then the output C is the complement of B (C = B⬘).
A similar property is seen in rows 1 and 3, where the output C = A⬘ when B = 0. When
an input to a NOR gate is set to logic 0, then the effects of that signal node are removed
with respect to signals on the other input lines. The noncontrolling logic state for a NOR
A
A B
B C
C
A 0 0 1
A
C 0 1 0
B C
B 11 00 00
11 11 00
(a) (b)
Figure 4.19. (a) 2NOR gate symbol and (b) truth table.
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4.4 NOR GATES 121
VDD
B
C
CL
Figure 4.20. 2NOR transistor-level schematic.
gate (and OR gate) is logic 0. OR gates can be made by adding an inverter to the output
of a NOR gate.
The NOR gate schematic in Figure 4.20 shows that any high logic input of VDD turns
on one of the nMOS transistors, forcing the output node C to 0 V. If both inputs are driven
high with VDD, then the pull-down strength is large since the nMOS transistor mobility is
higher than the series pMOS transistors and the nMOS transistors are in parallel. Two
pMOS transistors in series are potentially very slow, so the W/L adjustments for equal rise
and fall times favor larger pMOS transistors. The NOR gate also has inverter static and
dynamic properties. These are seen by setting one of the inputs to its noncontrolling logic
state and measuring a transfer curve at the other terminal.
Self-Exercise 4.5
(a) Specify the input signals that allow node I3 contents to be measured at O1
(Figure 4.21). (b) Repeat for reading node I2.
I1
I2
O1
I3
I4
Figure 4.21.
Self-Exercise 4.6
(a) Specify the input signals that allow node I5 contents to be measured at O1
(Figure 4.22). (b) Repeat for reading node I3. (c) Repeat for reading node I1.
c04.qxd 2/2/2004 12:25 PM Page 122
I1
I2
O1
I3
I4
I5
Figure 4.22.
4.5 CMOS TRANSMISSION GATES
A CMOS transmission gate, or T-gate, is a switch with many useful functions. Figure 4.23
shows an early T-gate design with symbol, truth table, and schematic. Signal transmission
is controlled by the gating or control signal G in Figure 4.23. When G = 1, both transistors
turn on and the signal passes to the output node B. When G = 0, no signal can pass since
both transistors are off. The T-gate shown in Figure 4.23 can cause circuit problems in
combinational logic since it has a high impedance state (also called floating, hi-Z, or tri-
state) when the control signals turn off. Floating nodes allow voltage drift on transistor
gates that can upset logic states. T-gates typically appear in CMOS flip-flop designs and to
control tri-state levels in IC output buffers. In both applications, the floating node does
not cause core logic instability.
Single transistors acting as T-gates are called pass transistors, but have a weakness. As-
sume that only the n-channel transistor in Figure 4.23(c) drives CL and the pMOS transis-
tor is removed. When the input A is high, the T-gate opens and charge passes through to
CL. When node B rises to a voltage one threshold drop below VG, then the n-channel tran-
sistor turns off, so node B cannot rise above VG – Vtn. An n-channel transistor passes a
weak logic high. Similarly, a p-channel transistor will pass a weak logic zero that is one
threshold drop above ground.
The cure is to put the n-channel and p-channel transistors in parallel. The nMOS tran-
sistor passes low logic levels with no voltage degradation, while the pMOS transistor
passes the high logic levels with no Vt degradation. Ideally, a switch should have a con-
stant resistance once turned on for any voltage that is transferred from node A to node B
G
GG A
A G
G CC
0 1 0
0 1 0 B
AA BB 1 1 1 A
1 1 1
00 00 ZZ CLL
GG 11 00 ZZ
G
(a) (b) (c)
Figure 4.23. (a) Transmission gate symbol, (b) truth table, and (c) transistor-level representation.
c04.qxd 2/2/2004 12:25 PM Page 123
EXERCISES 123
(Figure 4.23), but since MOS transistors are nonlinear elements, the on resistance is not
constant.
4.6 SUMMARY
This chapter examined detailed electronic properties of the inverter. Much of design and
failure analysis uses this information. The inverter properties also align with NAND,
NOR, and other logic gates. Static and dynamic transfer curves explain much of the speed
and power behavior of integrated circuits. The important design technique of tapered
buffers is commonly used in design to match small logic gate drives to larger high-input
capacitance load gates. It is essential to understand the operation of NAND, NOR, and
transmission gates at the transistor schematic level. The next chapter expands these con-
cepts to show how design of higher functions is achieved.
BIBLIOGRAPHY
1. A. Bellaouar and M. Elmasry, Low-Power Digital VLSI Design; Circuits and Systems, Kluwer
Academic Publishers, 1995.
2. A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Pub-
lishers, 1995.
3. B. Cherkauer and E. Friedman, “A unified design methodology for CMOS tapered buffers,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3, 1, March 1995.
4. C. Hawkins, J. Soden, E. Cole, and E. Snyder, “The use of light emission in failure analysis of
CMOS ICs,” in International Symposium on Test and Failure Analysis (ISTFA), pp. 55–67, 1990.
5. M. Kakamu and M. Kingawa, “Power supply voltage impact on circuit performance for half and
lower submicrometer CMOS LSI,” IEEE Transactions on Electron Devices, 37, 8, 1902–1908,
Aug. 1990.
6. A. Keshavarzi, K. Roy, and C. Hawkins, “Intrinsic leakage in low power deep submicron CMOS
ICs,” in IEEE International Test Conference (ITC), pp. 146–155, Oct. 1997.
7. T. Tsang, J. Kash, and D. Vallett, “Time-resolved optical characterization of electrical activity in
integrated circuits,” Proceeding IEEE, 1440–1459, Nov. 2000.
8. H. C. Lin and L. Lindholm, “An optimized output stage for MOS integrated circuits,” IEEE
Journal of Solid State Circuits, SC-10, 2, 106–109, April 1975.
EXERCISES
4.1. A logic gate noise margin parameters are: VIH = 1.6 V, VIL = 0.3 V, VOH = 1.7 V, and
VOL = 0.2 V.
(a) Calculate NMH.
(b) Calculate NML.
(c) The input voltage is down to 1.7 V and a negative 50 mV noise spike appears.
What happens to the circuit fidelity?
(d) The input voltage is down to 1.7 V and a negative 150 mV noise spike appears.
What happens to the circuit fidelity?
c04.qxd 2/2/2004 12:25 PM Page 124
4.2. Given an inverter A whose voltage transfer curve has a logic threshold at VDD = 3 V
of VTL = 1.5 V, and a second inverter B with a logic threshold of VTL = 1.2 V for the
same VDD:
(a) When the n-channel transistor goes into nonsaturation, is Vin more or less for B
than for A?
(b) When the p-channel transistor in B goes into nonsaturation, is Vin more or less
that that of the p-channel transistor in A when it goes into nonsaturation?
(c) What is the design difference between the transistors in inverters A and B?
4.3. Graphically determine the change in logic threshold of the CMOS inverter transfer
curve in Figure 4.24 if the curve shifts 0.2 V to the right in the mid-region.
Figure 4.24.
4.4. Figure 4.7 shows how a CMOS inverter transfer curve changes for fast input transi-
tions taking into account the load capacitance.
(a) Do these curves affect logic threshold?
(b) The hot carrier injection phenomenon that was described in Chapter 3 (Section
3.4.5) is aggravated by the electric field of the drain depletion region. Will hot
carrier injection damage differ on the rising and falling input signal?
4.5. Calculate the power dissipated by a cardiac pacemaker circuit if fclk = 32.6 kHz,
VDD = 1.5 V, CL (per gate) = 300 fF, and the number of logic gates = 10 k.
4.6. Figure 4.9 shows that logic gate spikes can go above VDD and below 0 V (GND).
Why does this happen? Where does the charge come from, and where does it go?
4.7. Use the transition time delay model of Figure 4.10 if CL = 30 fF, VDD = 1.5 V, Kp =
200 ␮A/V2, Vtp = –0.35 V, Vtn = 0.35 V, and Kn = 125 ␮A/V2. What is the difference
between rise and fall time of the transition if defined between 0 V and 1.5 V?
4.8. Repeat previous problem using the short channel model of Equation (4.9).
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4.8 EXERCISES 125
4.9. Figure 4.14 show CMOS transfer curves as VDD goes above and below Vtn + |Vtp|. If
VDD goes below a single threshold voltage (i.e., Vtn), then the inverter still exhibits a
valid transfer curve, although the curve is not as sharp. From your knowledge of
transistors in Chapter 3, how is operation for VDD < Vt possible?
4.10. An output buffer has an input capacitance of 95 fF and a load capacitance of 100 pF.
How many inverters are required in a fixed-taper design to minimize the propaga-
tion delay?
4.11. Figure 4.25 shows a single transistor transmission gate. At t = 0 the gate voltage
moves to VG = 2 V. The load capacitance CL is initially at zero volts. As the node ca-
pacitance (the source) charges VGS becomes smaller until it is less than Vtn. The
transistor cuts off and the node is less than the input drain voltage by VS = VD – Vtn.
If the body coefficient is ␥ = 0.2V1/2 and Vt0 = 0.4 V, calculate VGS and VS when the
capacitor fully charges before cutoff.
VG
D S
2V
CL
Figure 4.25.
4.12. Given an inverter with Vtn = 0.4 V and Vtp = –0.4 V, calculate the peak current dur-
ing the transition if W/L = 3, Kp = 50 ␮A/V2, and Kn = 125 ␮A/V2.
4.13. Given the logic circuit in Figure 4.26:

(a) What signal values must the input nodes be set to in order to read the contents
of node C at output H?
(b) What signal values must the input nodes be set to in order to read the contents
of node G at output H?
A
B
C
D H
E
F
G
Figure 4.26.
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CHAPTER 5
CMOS BASIC CIRCUITS
The previous chapter covered CMOS basic gate construction, emphasizing switching de-
lay and power consumption characteristics. We now look at CMOS logic design styles, in-
cluding static, dynamic, and pass-transistor logic. Input–output (I/O) circuitry and its pro-
tection problems are also discussed.
5.1 COMBINATIONAL LOGIC
Several design options exist for CMOS combinational gates. One reliable, lower-power
design style uses complementary static gates, whereas high-performance circuits may use
dynamic logic styles more suitable for high speed. Dynamic logic is more sensitive to
noise and requires synchronization of signals (with a clock), even for combinational logic.
Another logic design style uses pass-transistor or pass-gate elements as basic switches
when fewer transistors are needed to implement a function. We want to understand these
combinational logic design styles and their trade-offs.
5.1.1 CMOS Static Logic

Static, fully complementary CMOS gate designs using inverter, NAND, and NOR gates
can build more complex functions. These CMOS gates have good noise margins and low
static power dissipation at the cost of more transistors when compared with other CMOS
logic designs. CMOS static complementary gates have two transistor nets (nMOS and
pMOS) whose topologies are related. The pMOS transistor net is connected between the
power supply and the logic gate output, whereas the nMOS transistor topology is connect-
ed between the output and ground (Figure 5.1). We saw this organization with the NAND
and NOR gates, but we point out this topology to lead to a general technique to convert
Boolean algebra statements to CMOS electronic circuits.
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128 CHAPTER 5 CMOS BASIC CIRCUITS
VDD
p-MOS
p-MOS
Inputs Output
n-MOS
n-MOS
GND
Figure 5.1. Standard configuration of a CMOS complementary gate.
The transistor network is related to the Boolean function with a straightforward design
procedure:
1. Derive the nMOS transistor topology with the following rules:

앫 Product terms in the Boolean function are implemented with series-connected
nMOS transistors.
앫 Sum terms are mapped to nMOS transistors connected in parallel.
2. The pMOS transistor network has a dual or complementary topology with respect
to the nMOS net. This means that serial transistors in the nMOS net convert to par-
allel transistors in the pMOS net, and parallel connections within the nMOS block
are translated to serial connections in the pMOS block.
3. Add an inverter to the output to complete the function if needed. Some functions are
inherently negated, such as NAND and NOR gates, and do not need an inverter at the
output state. An inverter added to a NAND or NOR function produces the AND and
OR function. The examples below require an inverter to fulfill the function.
This procedure is illustrated with three examples.
왎 EXAMPLE 5.1
Design a complementary static CMOS 2NAND gate at the transistor level.

The Boolean function is simply A · B, therefore the nMOS net consists of two
series-connected transistors, whereas the pMOS net will use the complementary
topology, i.e., two transistors in parallel. The transistor structure was shown in
Figure 4.18. 왎
왎 EXAMPLE 5.2
Design a complementary static CMOS XOR gate at the transistor level.

The XOR gate Boolean expression F has four literals and is
F = x 丣 y = 苶xy + xy苶
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5.1 COMBINATIONAL LOGIC 129
F is the sum of two product terms. The design steps are:

1. Derive the nMOS transistor topology with four transistors, one per literal in
the Boolean expression. The transistors driven by 苶x and y are connected in
series, as well as the devices driven by x and 苶y. These transistor groups are
connected in parallel, since they are additive in the Boolean function. The
signals and their complements are generated using inverters (not shown).
The nMOS transistor net is shown in Figure 5.2.
out
x x
y y
nMOS net
Figure 5.2.
2. Implement the pMOS net as a dual topology to the nMOS net. The pMOS
transistors driven by 苶x and y are connected in parallel, as are the devices
driven by x and 苶y (Figure 5.3). These transistor groups are connected in se-
ries, since they are parallel connected in the nMOS net. The out node now
implements 苶 F.
pMOS net
x y
x y
out F
x x
y y
nMOS net
Figure 5.3.
3. Finally add an inverter to obtain the function F, so that F = 苶ou

苶t苶
Steps 1–3 show that any Boolean function, regardless of its complexity, can
be implemented with a CMOS complementary structure and an inverter. A more
complicated example is developed below. 왎
왎 EXAMPLE 5.3
Design the nMOS transistor net for a Boolean function F = x + {y苶 · [z + (t · w

苶)]}.
We design this gate with a top-down approach. The nMOS transistor network
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is connected between the output and ground terminals, i.e., the lower box in Fig-
ure 5.1. The higher-level function F is a sum of two terms
F = x + {operation A}
where operation A stands for the logic within the brackets of F. The transistor
version of this sum is shown in Figure 5.4.
out
x + {Operation A} y
x Operation A z
t
w
parallel
connection nMOS net
Figure 5.4.
Now we design the transistor topology that implements the block “operation
A,” whose higher level operation is an AND, i.e.:
operation A = 苶y · {operation B}
Hence, the design topology is a transistor controlled by input y苶 in series with a

third box that will implement operation B, as shown in Figure 5.5.
We then design the topology of box B. This is a transistor controlled by input
z, in parallel with two transistors connected in series; one controlled by input t,
w. The complete nMOS network is shown in Figure 5.6.
and the other by input 苶
out
out
serial connection
x y
x y
y . {Operation B}
t
Operation B z
t z
w w
nMOS net
nMOS net
Figure 5.5.
Figure 5.6.
Once the nMOS block is designed, we build the pMOS block with a dual
topological structure and then connect an inverter to its output, as shown in Fig-
ure 5.7. 왎
Self-Exercise 5.1
Design the transistor level schematic of function F = (x + y)[z + (wt)(z苶 + x)].

c05.qxd 2/2/2004 12:26 PM Page 131
pMOS net
w t
y
z
x
F
out
x y
t
z
w
nMOS net
Figure 5.7.
5.1.2 Tri-State Gates

Many logic gates require a tri-state output—high, low, and high-impedance states. The
high-impedance state is also called the high-Z state, and is useful when connecting many
gate outputs to a single line, such as a data bus or address line. A potential conflict would
exist if more than one gate output tried to simultaneously control the bus line. A control-
lable high-impedance-state circuit solves this problem.
There are two ways to provide high impedance to CMOS gates. One way provides tri-
state output to a CMOS gate by connecting a transmission gate at its output (Figure 5.8).
The control signal C sets the transmission gate conducting state that passes the non-tri-
stated inverter output out⬘ to the tri-stated gate output out. When the transmission gate is
off (C = 0), then its gate output is in the high-impedance or floating state. When C = 1, the
transmission gate is on and the output is driven by the inverter.
A transmission gate connected to the output provides tri-state capability, but also con-
sumes unnecessary power. The design of Figure 5.8 contributes to dynamic power each
time that the input and output (out⬘) are switched, even when the gate is disabled in the tri-
state mode. Parasitic capacitors are charged and discharged. Since the logic activity at the
input does not contribute to the logic result while the output is in tri-state, the power con-
sumption related to this switching is wasted.
This can be avoided by putting a transmission gate “inside” the inverter (Figure 5.9).
In out' Out
C
Figure 5.8. Inverter with a transmission gate to provide tri-state output.
c05.qxd 2/2/2004 12:26 PM Page 132
C
Out
In In Out
Figure 5.9. Schematic and symbol. The transmission gate “inside” the inverter provides tri-state
output.
The pMOS and nMOS transistors of the transmission gate are in series within the con-
ducting path between the power and ground rails and the inverter transistors. When the
gate is in the tri-state mode, the inner transistor source nodes float, and the output is iso-
lated from supply and ground. The activity at the inverter output signal node does not con-
sume power as long as the gate is in the high-Z state (C = 0).
A tri-state capability adds delay independent of the configuration, due to the extra re-
sistance and capacitance of the transistors driven by the tri-state control signal.
5.1.3 Pass Transistor Logic

There are many pass transistor (pass gate) logic subfamilies [3], and we will describe a
few. Pass transistor logic uses transistors as switches to carry logic signals from node to
node, instead of connecting output nodes directly to VDD or ground. If a single transistor is
a switch between two nodes, then a voltage degradation equal to Vt for the high or low
logic level is obtained, depending on the nMOS or pMOS transistor type (Chapter 4).
CMOS transmission gates avoid these weak logic voltages of single-pass transistors at the
cost of an additional transistor per transmission gate.
Advantages are the low number of transistors and the reduction in associated intercon-
nects. The drawbacks are the limited driving capability of these gates and the decreasing
signal strength when cascading gates. These gates do not restore levels since their outputs
are driven from the inputs, and not from VDD or ground [6].
A typical CMOS design is the gate-level multiplexer (MUX) shown in Figure 5.10 for
a 2-to-1 MUX. A MUX selects one from a set of logic inputs to connect with the output.
In Figure 5.10, the logic signal c selects either a or b to activate the output (out). Figure
5.10(b) shows a MUX design with transmission gates. The complementary CMOS gates
(Figure 5.10(a)) require 14 transistors (four transistors for each NAND and two transistors
to complement the control signal), whereas the transmission gate design requires only six
devices (more than 50% reduction). Each transmission gate has two transistors plus two
more to invert the control signal.
Another pass gate design example is the XOR gate that produces a logic one output
when only one of the inputs is logic high. If both inputs are logic one or logic zero, then
the output is zero. Figure 5.11 shows an 8-transistor XOR gate having a tri-state buffer
and transmission gate with their outputs connected. Both gates are controlled by the same
input through a complementary inverter (A-input in this case).
c05.qxd 2/2/2004 12:26 PM Page 133
c
a a
a out out
c c
out
c b
b
b c
(a) (b)
Figure 5.10. (a) Standard 2-to-1 MUX design. (b) Transmission (pass) gate-based version.
The XOR gate of Figure 5.11 is not a standard complementary static CMOS design
since there is no nMOS transistor network between the output and ground, nor is there a
pMOS transistor net between the output and the power rail. The XOR standard CMOS de-
sign built in Example 5.2 requires fourteen transistors, whereas the design in Figure 5.11
requires only eight.
5.1.4 Dynamic CMOS Logic

Previous sections showed conventional static CMOS circuit design techniques and de-
signs based on tri-state gates and pass transistors. These designs are static, since they do
not require a clock signal for combinational circuits. So, if circuit inputs are stopped
(elapsed), then the circuits retain their output state (all circuit nodes remain at their valid
quiescent logic values) as long as power is maintained. Dynamic CMOS logic families do
not have this property, but do have the following advantages:
앫 They use fewer transistors and, therefore, less area.

앫 Fewer transistors result in smaller input capacitance, presenting a smaller load to
previous gates, and therefore faster switching speed.
앫 Gates are designed and transistors sized for fast switching characteristics. High-
performance circuits use these families.
A B out
out 0 0 0
A
0 1 1
B 1 0 1
1 1 0
Figure 5.11. 8-transistor XOR gate and truth table.

c05.qxd 2/2/2004 12:26 PM Page 134
앫 The logic transition voltages are smaller than in static circuits, requiring less time to
switch between logic levels.
The disadvantages of dynamic CMOS circuits are
앫 Each gate needs a clock signal that must be routed through the whole circuit. This
requires precise timing control.
앫 Clock circuitry runs continuously, drawing significant power.
앫 The circuit loses its state if the clock stops.
앫 Dynamic circuits are more sensitive to noise.
앫 Clock and data must be carefully synchronized to avoid erroneous states.
Dynamic CMOS Logic Basic Structure. A dynamic CMOS gate implements the
logic with a block of transistors (usually nMOS). The output node is connected to ground
through an nMOS transistor block and a single nMOS evaluation transistor. The output
node is connected to the power supply through one precharge pMOS transistor (Figure
5.12). A global clock drives the precharge and evaluation transistors. The gate has two
phases: evaluation and precharge. During precharge, the global clock goes low, turning
the pMOS transistor on and the evaluation nMOS off. The gate output goes high (it is
precharged) while the block of nMOS transistors float.
In the evaluation phase, the clock is driven high, turning the pMOS device off
and the evaluation nMOS on. The input signals determine if there is a low or high im-
pedance path from the output to ground since the global clock turns on the nMOS eval-
uation transistor. This design eliminates the speed degradation and power wasted by the
short-circuit current of the n- and p-channel transistors during the transition of static
complementary designs. If the logic state determined by the inputs is a logic one (VDD)
then the rise time is zero. The precharge and evaluation transistors are designed to nev-
er conduct simultaneously.
Dynamic circuits with an n-input gate use only n + 2 transistors instead of the 2n de-
vices required for the complementary CMOS static gates. Dynamic CMOS gates have a
drawback. If the global clock in Figure 5.12 is set high, then the output node could be in
high-Z state with no electrical path to VDD or ground. This exposes the node to noise fluc-
tuations and charge sharing within the logic block, thus degrading its voltage. Also, the
output load capacitor will slowly discharge due to transistor off-state leakage currents and
lose its logic value. This limits the low-frequency operation of the circuit. The gate inputs
Global Precharge
clock transistor
Inputs
Logic out
block
Evaluate
transistor
Figure 5.12. Basic structure of a dynamic CMOS gate.

c05.qxd 2/2/2004 12:26 PM Page 135
can only change during precharge, since charge redistribution from the output capacitor to
internal nodes of the nMOS logic block may drop the output voltage when it has a logic
high.
Finally, dynamic gate cascading is challenging since differences in delay between
logic gates may cause a slow gate to feed an erroneous logic high (not yet evaluated
to zero because of the delay) to the next gate. This would cause the output of the second
gate to be erroneously zero. Different clocking strategies can avoid this, as shown
next.
Domino CMOS Logic. Domino CMOS was proposed in 1982 by Krambeck, et al.,
[4]. It has the same structure as dynamic logic gates, but adds a static buffering CMOS
inverter to its output. In some cases, there is also a weak feedback transistor to latch the
internal floating node high when the output is low (Figure 5.13). This logic is the most
common form of dynamic gates, achieving a 20%–50% performance increase over stat-
ic logic [3].
When the nMOS logic block discharges the out⬘ node during evaluation (Figure 5.13),
the inverter output out goes high, turning off the feedback pMOS. When out⬘ is evaluated
high (high impedance in the dynamic gate), then the inverter output goes low, turning on
the feedback pMOS device and providing a low impedance path to VDD. This prevents the
out⬘ node from floating, making it less sensitive to node voltage drift, noise, and current
leakage.
Domino CMOS allows logic gate cascading since all inputs are set to zero during
precharge, avoiding erroneous evaluation from different delays. This logic allows static
operation from the feedback latching pMOS, but logic evaluation still needs two subcy-
cles: precharge and evaluation. Domino logic uses only noninverting gates, making it an
incomplete logic family. To achieve inverted logic, a separate inverting path running in
parallel with the noninverted one must be designed.
Multiple output domino logic (MODL) is an extension of domino logic, taking internal
nodes of the logic block as signal outputs, thus saving area, power, and performance.
Compound domino logic is another design that limits the length of the evaluation logic to
prevent charge sharing, and adds other complex gates as buffer elements (NAND, NOR,
etc., instead of inverters) to obtain more area compaction. Self-resetting domino logic
(SRCMOS) has each gate detect its own operating clock, thus reducing clock overhead
and providing high performance. These and other dynamic logic designs are found in [3].
Latch
transistor
Global
clock
out
out'
Inputs
Logic
block
Evaluate
transistor
Figure 5.13. Domino CMOS logic gate with feedback transistor

c05.qxd 2/2/2004 12:26 PM Page 136
GC GC GC
nMOS pMOS nMOS

logic logic logic
block block block
Figure 5.14. NORA CMOS cascaded gates.
NORA CMOS Logic. This design alternative to domino CMOS logic eliminates the
output buffer without causing race problems between clock and data that arise when cas-
cading dynamic gates. NORA CMOS (No-Race CMOS) avoids these race problems by
cascading alternate nMOS and pMOS blocks for logic evaluation. The cost is routing two
complemented clock signals. The cascaded NORA gate structure is shown in Figure 5.14.
When the global clock (GC) is low (G 苶C苶 high), the nMOS logic block output nodes are
precharged high, while outputs of gates with pMOS logic blocks are precharged low.
When the clock changes, gates are in the evaluate state.
Other CMOS Logic Families. Dynamic circuits have a clock distribution problem,
since all gates must be functionality synchronized. Self-timed circuits are an alternative to
dynamic high-performance circuits, solving the clock distribution by not requiring a glob-
al clock. This simplifies clock routing and minimizes clock skew problems related to
clock distribution. The global clock is replaced by a specific self-timed communication
protocol between circuit blocks in a request–acknowledge scheme. Although more robust
than dynamic circuits, self-timed logic requires a higher design effort than other families.
These gates implement self-timing (i.e., derivation of a completion signal) by using a dif-
ferential cascode voltage switch logic (known as DCVS) based on an extension of the
domino logic.
Local
reset out
out
Inputs
Dual complementary
logic block
Figure 5.15. Basic DCVS logic gate.

c05.qxd 2/2/2004 12:26 PM Page 137
5.2 SEQUENTIAL LOGIC 137
The DCVS logic family (Figure 5.15) uses two complementary logic blocks, each
similar to the domino structure. The gate inputs must be in the true and complementary
form. Since output true and output negated are available, they can activate a completion
signal when the output is evaluated. Since the gate itself signals when the output is
available, DCVS can operate at the maximum speed of the technology, providing high-
performance asynchronous circuits. The major drawbacks are design complexity and in-
creased size.
5.2 SEQUENTIAL LOGIC
Nonstandard complementary CMOS designs are widely used in sequential logic to

achieve compaction, high speed, and data storage. Latches, flip-flops, and registers are ba-
sic to many IC circuit designs. We present some of the better known static and dynamic
memories.
5.2.1 Register Design

Registers are made with flip-flops that are in turn made with latches. Latches are memory
elements whose transparent/memory states depend on the logic value (level) of a control
signal. Flip-flops are constructed using latches to obtain a memory element that is trans-
parent during the transition (edge) of the control signal for a better command of the time
instant at which data are captured. We describe the basic latch, and then build the higher
blocks.
CMOS Latch with Tri-State Inverters. Figure 5.16 shows the gate level and tri-state
inverter design of a compact CMOS latch with two tri-state inverters and one regular in-
verter (Figure 5.16(b)). When clk = C = 1, the outputs of the first set of 2NOR gates are
logic zero. This is the noncontrolling logic state feeding the D signal to the two output
2NOR gates. Therefore, the Q and Q signals feeding the inputs of the two output 2NOR
gates set a stable logic condition. If 苶
Q = 1, then the bottom output 2NOR gate is driven to
苶 = 0. The 苶
Q Q signal feeds a logic zero to the upper 2NOR gate, setting and holding Q = 1
(and Q苶 = 0). The latch holds its logic state indefinitely unless input signals change or the
power is lost. When C = 0 (noncontrolling logic state to the input 2NOR gates), the Q out-
puts respond to the data input signal D. This is an example of a circuit that loads data on
the low or negative portion of the clock signal.
In Figure 5.16(b), a level-sensitive clock controls the tri-state input of both inverters
D D
D Q D QQ
C Q
C
Q
Q
CC
(a) (b)
Figure 5.16. (a) Basic gate-level CMOS latch design. (b) Tri-state inverter-level schematic.
c05.qxd 2/2/2004 12:26 PM Page 138
such that when one is in tri-state, the other one is not. When the output of the first tri-state
inverter stage is active (C = high), the feedback inverter is in tri-state (off), and the latch
output is transparent. When C is low, the output of the first inverter floats, and the feed-
back tri-state inverter latches the value maintaining a feedback recovery configuration,
holding the value. When C = 0, the latch is in its memory state. This is an example of a
circuit that loads data on the positive portion of the clock.
Self-Exercise 5.2
Compare the number of transistors in the latch of Figure 5.16(a) with a D latch
designed with tri-state inverters [Figure 5.16(b).]
CMOS Latch with Transmission Gates. Another transmission gate latch design
further reduces transistor count. The circuit in Figure 5.17 uses two transistors less than
that shown in Figure 5.16(b).
CMOS Flip-Flop with Tri-State Inverters. Flip-flops are edge-sensitive memory el-
ements using latches in a “master–slave” (MS) configuration. This edge-sensitive circuit
changes logic state not on the level of the clock, but on the leading or falling edge of the
clock. This eliminates the transparency properties of the latch since the output signal nev-
er sees a direct path to the input. The output is sensitive to change on one of the clock
edges, and insensitive to the clock level.
The clock drives the master latch with the slave latch clock signals inverted. The mas-
ter and slave are coupled through a transmission gate. The master latch configuration cap-
tures data at one clock level (high or low), and the slave captures data on the opposite val-
ue. The transmission gate between the master and slave latches controls the timing for
capture of output data Q.
Figure 5.18 shows a flip-flop design with unequal master and slave cells. The master
cell (left portion of the circuit) is the latch design described earlier, and is connected to the
slave (right portion of the circuit) through a transmission gate. When the clock is low, the
master and slave are isolated, with the master active and the slave in memory. The action
of the master tri-state circuit generates a logic value at the master inverter output that
equals the input data D. When the clock goes high, the transmission gate connecting the
master and slave opens, and data are transferred. Data are read directly to the Q output on
the rising edge of the clock. The data could be transferred on the clock falling edge if the
coupling transmission gate (and the other clocked signals) reversed their clock signal po-
larities. The MS design differs from a latch, since the MS output Q sees very little of the
D Q
Q
C C
Figure 5.17. Alternate design of a latch cell with transmission gates.

c05.qxd 2/2/2004 12:26 PM Page 139
clk clk clk

clk
D Q
clk
clk clk clk
Q
Figure 5.18. CMOS design of a flip-flop combining tri-state inverters and transmission gate de-
sign. The slave cell (right side) is only half of the master latch design to further reduce the number
of transistors. Data are loaded into the first master latch on the negative clock edge, and data are
read by the output Q on the rising clock edge. Then data are stored when the clock returns to logic
zero.
input signal D directly. There is a small transient period when all transmission gates are in
switching conduction states, and an electrical path may exist throughout the MS flip-flop.
However, modern transition times are in the tens of picoseconds, and small clock timing
skews make the overlap time very short.
5.2.2 Semiconductor Memories (RAMs)

Memories are a high-volume product in the IC market. The original phrase “random ac-
cess memory” (RAM) refers to a memory in which all data have equal access procedures.
There is no shifting of registers to capture a data bit. Test and reliability engineers also use
memories to screen and verify emerging technologies, since they are relatively easy to test
and failure analyze for process debugging. Their regularity and high density make them
2n
col k
bit
cell
n
row i
data 2m
in
I/O
data
out
m
Figure 5.19. General architecture of a semiconductor memory.
c05.qxd 2/2/2004 12:26 PM Page 140
good process monitors. Design regularity makes failure analysis easier than in random
logic, since it is straightforward to map a logic failure to a physical location. High-density
design provides good process monitoring, since transistors are designed for minimum di-
mensions of the technology, and conducting lines are kept as close as possible. These tight
dimensions increase the probability of exposing process deficiencies.
The architecture of a static or dynamic semiconductor memory is shown in Figure
5.19. Memories have three major blocks: the memory array cells, the decoders, and the
input–output circuitry. Memories can be bit- or word-oriented, accessing a single bit of
the memory or the whole word (8, 16, 32, or 64 bits). In any case, the memory array is
organized in rows and columns, with bits located at the intersection between a row and
a column.
Each bit (or word) has a unique address that is mapped to physical locations with row
and column decoders. The input–output circuitry performs the read or write data opera-
tions, i.e., store or retrieve the information in the memory.
Row and column decoders take an address of n + m bits, and select one word line out of
2n and one column out of 2m for bit-oriented memories. In word-oriented memories, the
column decoder selects as many columns as the number of bits per word.
Static and dynamic memories have different cell designs. Dynamic memories store in-
formation in a capacitor, retaining data for a limited time, after which the information is
lost due to leakage. Information can be retained at the expense of additional external cir-
cuitry and dedicated working modes to allow memory refreshment. When the memory is
being refreshed, it cannot be accessed, and is said to be in a latency period.
Static memories store information in feedback structures (two cross-coupled invert-
ers). They are faster than dynamic memories since static RAMs do not have latency peri-
ods, whereas dynamic memory cost per bit is cheaper because fewer transistors per cell
are required.
Static Memories (SRAMs). Static semiconductor memories use two inverters in a bi-
stable feedback design (Figure 5.20(a)). Bi-stable operation is illustrated by plotting the
output versus input voltages on the same axes for both inverters [Figure 5.20(b)]. The sta-
ble quiescent states of the circuit are at the intersections where Vi = 0 and Vi = VDD,
whereas the intersection voltage at Vi = V0 is not a stable state (called a metastable state).
The system is called bi-stable, since only two states are stable.
The inverter feedback circuit retains its state as long as the power supply is maintained.
1.8
I1
1.5
VDD
II1 1.2 I1
I11
I2
Vo (V)
0.9
V0 I2 I2
Vi V0 0.6
Vi Vo
I2
0.3
I1
0
I2 0
0
0
0.3 0.6 V0.9 1.2
VDD
1.5 1.8
V i(V)
in
(a) (b)
Figure 5.20. (a) Basic storage mechanism for static memories. (b) Input–output characteristics of
the circuit.
c05.qxd 2/2/2004 12:26 PM Page 141
precharge
six
transistor
cell
word
line
column column
line line
(bit) (bit)
Figure 5.21. Six-transistor CMOS SRAM cell architecture.
Any “soft” voltage perturbation or possible current leakage in one node tending to switch
the cell will be compensated for and overridden by the inverter output connected to this
node. Vi in Figure 5.20(a) must have a stronger drive than the output of I2. Memory cells
typically set the memory state by driving Vi and V0 simultaneously with opposite polarity
signals.
The six-transistor cell architecture for a CMOS static RAM is given in Figure 5.21. All
cell transistors and their interconnections are minimally sized to keep the array as small as
possible. The word line controls the access transistors connecting the cell nodes to the col-
umn bit lines that run in pairs bit and b苶i苶t苶. When the word line is high, all cells in that row
are connected to their corresponding bit and b苶i苶t苶 lines, and can, therefore, be accessed to
read or write.
Memory read–write access time is reduced by precharging the bit and 苶bi苶t苶 lines, i.e.,
forcing lines to the same voltage before any operation takes place. The precharge signal at
the top of Figure 5.21 turns on all three p-channel transistors, forcing VDD on both bit
lines. When a write operation is performed, the bit and 苶bi苶t苶 line drivers rapidly unbalance
these lines, so that the correct value is stored in the memory. The precharge avoids the sig-
nificant time for charging the highly capacitive bit lines when signals go from low to high.
nMOS transistors pull down faster than equal sized pMOS pull-up transistors.
Memory cell inverters are minimally sized, but must drive long bit lines through a pass
transistor during read operations. This potential delay can be improved using small analog
circuits, called sense amplifiers, that are placed at each bit column output. Figure 5.22
M4 M5
out
bit M1 M2 bit
CS M3
Figure 5.22. A differential sense amplifier used in SRAM memories.

c05.qxd 2/2/2004 12:26 PM Page 142
read
read bit line
select
select bit line
(read/write)
(read/write)
M1
M1 M3
M3 read/write
M2
M2 read/write
write
write select
select
select
select
write
write read
read
line
line line
line
(a) (b)
Figure 5.23. DRAM cells (a) Three-transistor cell. (b) One-transistor cell.
shows a typical differential sense amplifier used in CMOS SRAM designs. When the con-
trol signal CS is low, M3 is off, and the sense amplifier output is floating. This corre-
sponds to write operations. When CS is high, the circuit is activated. The sense amplifier
reads bit and 苶bi苶t苶 line voltages after precharge, and quickly transfers the cell value to the
input–output circuitry, even before internal bit and b苶i苶t苶 lines reach steady voltages. If bit
and CS are high, then M1 drives current through M4. The voltage drop across M4 reduces
the drain voltage at M1. M2 is off, and the out signal is pulled to VDD through M5. When
bit is low and CS high, then M2 turns on and out goes low. Sense amplifiers are only used
during the read phase, and are disabled in other operations.
Dynamic Memories (DRAMs). Dynamic memory retains data as charge stored on a

capacitor. This allows smaller memory cells, but since charge is not maintained by a feed-
back structure, stored values are lost with time and require refresh periods.
Two dynamic cell configurations are shown in Figure 5.23. Both cells use the parasitic
gate capacitance of a MOS transistor to store the charge. The three-transistor cell (Figure
5.23(a)) has separate read and write select lines, giving a faster operation, but occupying
more space. When the write select line is high, M1 acts as a pass transistor, transferring the
write line logic state to M2 and putting M2 in the off or conducting state. The drain M1 – M2
node capacitance holds that state. The read signal turns on M3 and the data bit on the M2
drain is passed through M3 to the read line. This configuration allows for a nondestructive
read operation, meaning that the cell does not lose its contents after a read is performed.
The single-transistor cell (Figure 5.23(b)) is popular since it has the smallest memory
cell area. The charge stored in the cell storage capacitor is lost during the read operation
because of charge sharing with the bit line parasitic capacitor, thus requiring a refresh op-
eration during the same access cycle. The refresh operation uses circuitry that restores the
original value in the cell once it is read.
5.3 INPUT–OUTPUT (I/O) CIRCUITRY
Input–output circuitry must link logic signals inside the IC to the outside world. The ma-
jor I/O design problems are sufficient signal strength to drive large loads on printed cir-
cuit boards (PCBs) and IC internal circuitry protection from outside electrical assaults.
Output current drive is typically achieved by using large output buffers that can have W/L
c05.qxd 2/2/2004 12:26 PM Page 143
5.3 INPUT–OUTPUT (I/O) CIRCUITRY 143
ratios in the range of 1000–4000. I/O design is challenging and very technology depen-
dent.
5.3.1 Input Circuitry: Protecting ICs from the Outside Environment

CMOS circuits need protection from electrical assaults of the outside environment, espe-
cially for circuit inputs since they are connected to transistor gates. Input devices are often
exposed to electrical overstress (EOS) and electrostatic discharge (ESD) phenomena that
are responsible for gate oxide ruptures and interconnect damage [1]. A person walking on
a carpeted floor can accumulate over 20 kV of static charge. Contact between a charged
human body and an IC pin can cause a several nanosecond discharge, leading to Ampere
current peaks and pin voltages up to 4,000 V or greater!
ESD is the rapid transient discharge from picoseconds to nanoseconds of static charges
when two dissimilar bodies come in contact. The transistor thin silicon dioxide (SiO2)
film of less than 25 Å is easily damaged. The operating electric fields that gate oxides
typically use are between 2–5 MV/cm, whereas breakdown occurs between 10–18
MV/cm. It takes only a small extra gate voltage to push the oxides into rupture. Some IC
fabrication steps induce ESD on internal transistors of the circuit, so that the phenomena
are not just related to those transistors physically driven by pin connected inputs. ESD
protection structures are designed within the IC, and can protect the circuit if designed
well.
EOS delivers a high voltage for a longer time than ESD. EOS times between microsec-
onds to seconds cause more visible damage to the IC than ESD. ESD and EOS have differ-
ent properties and root causes, but both destroy ICs. ESD typically occurs when a circuit
contacts a charged machine or human, and EOS comes from aberrant longer pulses from
power supplies, testers, lightning, or general misuse, such as mounting a package back-
ward. EOS protection strategies often seek to eliminate the problem at the system level.
Different strategies are adopted to protect input structures against ESD. Elements are
connected between the input PAD, the transistor gates, and the power rails to provide safe
discharge paths when ESD occurs. These elements are inactive as long as the voltage lev-
els of the node are within the normal operating conditions of the device.
When ESD assaults the IC, the protection circuit must drive the excess charge to the
power or ground rails, steering that damaging energy away from the transistor gate oxide
or metal interconnects. These protection devices are diodes and/or transistors working out
of their normal operating ranges at high voltages and currents. Protection devices must
sink large currents in nanosecond response times, suppressing heating effects and high
electric fields. The protection circuits must survive the static energy assault to continue
their protective function.
primary element secondary element

(field oxide) device (thin oxide) device
to input
PAD
device
isolation
resistor
Figure 5.24. Example of input protection scheme against ESD.

c05.qxd 2/2/2004 12:26 PM Page 144
ESD protection circuit design greatly depends on the technology, and is very layout
sensitive. A common protection circuit with two protecting elements and a resistor is
shown in Figure 5.24. The primary element takes most of the current during the ESD
event, whereas the secondary element gives rapid initial protection to the logic gate input
until the primary device turns on. The resistor provides a voltage drop to isolate both ele-
ments, allowing high voltage operation of the primary element while the voltage at the
gate input can be maintained at a lower value. There are several ways to design the prima-
ry and secondary elements, so only the basics are described here (for more information
refer to [1]).
The primary input protection circuitry in MOS technologies may use a field oxide tran-
sistor with a triggering voltage of about 30–40 V (this greatly depends on the technology).
The secondary protection device is a grounded gate nMOS transistor reaching its trigger
breakdown voltage (called snapback) rapidly before the primary protection circuit turns
on. The current through this secondary device causes a voltage drop across the resistor
that increases the PAD voltage to a value at which the field oxide transistor triggers, and
takes most of the current.
5.3.2 Input Circuitry: Providing “Clean” Input Levels

Input circuitry must provide “clean” or noise-free logic levels to the internal circuitry. An
external noisy or ringing input transition may induce multiple switching at the gate out-
put. A solution uses a circuit with a static hysteresis transfer characteristic. The input volt-
age for which the output responds to a low-to-high or high-to-low transition depends on
the output voltage. This circuit is known as an Schmitt trigger. Figure 5.25 shows both the
Schmitt trigger transistor-level design and the input–output transfer characteristic. The
feedback transistors whose gates are connected to the output provide the hysteresis [2].
The Schmitt trigger circuit in Figure 5.25 has only six transistors, but it has complexity
whose explanation will bring together many CMOS concepts [2]. Start by setting Vin = 0
V and tracking the three nMOS transistors as they change state. When Vin = 0 V, M1 and
M2 are off and M3 is a pass transistor driven fully by the high logic voltage at Vout. M3 will
pass VDD to the source of M2 (drain of M1) with a weak voltage of VDD – Vtn3. As Vin rises
to Vtn1, M1 turns on. M2 is still off since VGS2 = Vtn1 – (VDD – Vtn3). As Vin rises above Vin =
Vtn1, M1 conducts through M3 and VS2 begins to fall. M2 will turn on when Vin – VS2 =
Vtn2. M2 source and bulk are at different voltages so M2 will have an elevated threshold
voltage, the same as M3. M2 conduction now allows a more rapid drop in VS2 and Vout with
1.8
M6
1.5
M5
1.2
Vo (V)
M4 0.9
Vin Vout 0.6
M2
0.3
M3 0
0 0.3 0.6 0.9 1.2 1.5 1.8
M1
Vin (V)
Figure 5.25. (a) Schmitt trigger CMOS design and (b) transfer characteristic.
c05.qxd 2/2/2004 12:26 PM Page 145
5.3 INPUT–OUTPUT (I/O) CIRCUITRY 145
the onset of transition higher than Vt as in a normal inverter. A similar analysis exists,
starting with Vin = VDD, that watches the transistor actions as Vin drops. The p-channel
transistors respond to a different level when switching the output voltage to a logic high.
Analytically, the design is examined by equating the saturated state drain current ex-
pressions for M1 and M3:
K1⬘(VGS1 – Vt)2 = K3⬘(VGS3 – Vt)2 (5.1)
We define the switching point of the low- to high-input transition VSPH as the input volt-
age at which M2 starts to conduct (VGS2 = Vt2), i.e.,
Vin – VS2 = Vt2 (2.2)
Setting the body effect threshold voltages of M2 and M3 equal, from Equation (5.2) the
switch point is VSPH = VS3 – Vtn3, giving
K1⬘ (VDD – VSPH)2 L3 W1

ᎏ = ᎏᎏ = ᎏᎏ (5.3)
K3⬘ (VSPH – Vtn1)2 W3 L1
The conduction control of the pMOS transistors follows a similar analysis, giving
K6⬘ (VSPL)2 W6 L5
ᎏ = ᎏᎏᎏ = ᎏᎏ (5.4)
K5⬘ (VDD – VSPL – Vtp6)2
L6 W5
The transistor widths and lengths can be designed to achieve a given VSPH and VSPL.
5.3.3 Output Circuitry, Driving Large Loads

IC output circuitry must have strong signal strength to drive other circuits at the PCB lev-
el. Large capacitive loads driven at high speed require a large current in a small time. Dri-
ving large capacitances is not only an I/O design problem, it also appears within the de-
vice when driving long lines or bus lines. This drive is achieved with large transistors that
have large input capacitance values because of their size. Specific circuits can drive large
loads such as the tapered buffers described in Section 4.2.
Latchup in CMOS Technologies.* Large currents can be triggered by a bipolar

mechanism called latchup. CMOS technology uses n-type and p-type transistors on the
same substrate. Many processes start with a uniformly doped substrate, and construct
wells of opposite doping to fabricate both MOS transistor types. This structure has an in-
herent pnpn parasitic bipolar transistor structure shown in Figure 5.26 that is off in normal
operation and does not contribute to the circuit behavior. Latchup occurs when a parasitic
pnpn structure underlying the CMOS structure is turned on, driving large currents and
damaging the whole circuit.
The underlying parasitic bipolar transistors are connected with positive feedback, so
that once the structure is triggered, the current increases until the device is destroyed. If
proper rules are not followed during design or the circuit is operated improperly, then the
parasitic bipolar structure may be triggered on, causing severe circuit damage.
*This subsection requires the reader to have a knowledge of bipolar (BJT) transistor princicples.
c05.qxd 2/2/2004 12:26 PM Page 146
n+ p p+ n
p-well
n-substrate
Figure 5.26. Cross section of a CMOS circuit fabricated with a single well and parasitic bipolar
devices associated with such a technology.
The CMOS structure with diffused wells in Figure 5.26 shows the parasitic bipolar
transistor structure underlying the circuit. The parasitic bipolar devices are connected
such that the collector terminal of one device is connected to the base of another in a
closed positive-feedback loop.
If an excess of carriers reach the base of some of the parasitic bipolar transistors, the cur-
rent is amplified at its collector terminal, driving the base of the other bipolar device. This
positive feedback connection can increase the current without limit. Figure 5.27 shows the
current–voltage characteristic of the parasitic bipolar structure within a CMOS single-well
process. Once the structure is triggered (the voltage goes beyond Vtrig), lowering the voltage
does not decrease the current because of the positive feedback. The only way to cut the cur-
rent through the device is to completely switch off the power supply of the circuit.
Latchup is prevented by proper design that avoids activating a parasitic structure, since
this cannot be eliminated. One latchup mechanism uses hot electrons from saturated MOS
devices, causing holes to be injected into the substrate. If those holes are not properly col-
lected at substrate and bulk contacts, they may diffuse and cause a voltage drop within the
substrate (or well) that is enough to turn on a parasitic bipolar device. High substrate cur-
rents are another latchup source. Design strategies to avoid latchup are beyond the scope
of this book and can be found in [1]. The modern trend toward SOI technologies and pow-
er supplies lowered to around VDD = 1 V lessen the threat of latchup
5.3.4 Input–Output Circuitry: Providing Bidirectional Pins

Microprocessors, microcontrollers, programmable logic (FPGA), and memories use bidi-
rectional (i.e., input–output) pins. Depending on the circuit design, certain pins are logic
inputs for some operations and logic outputs for others. Bidirectional pins reduce the
overall circuit pin count. These pins must have proper protections for the gates that will
process the inputs, and also provide enough driving capability when acting as outputs.
Figure 5.28 shows a commonly used design to control bidirectional I/Os. When the
control signal OE is low, the logic from inside the circuit (data out) is driven onto the out-
put PAD through the strong output transistors. When the control signal input/output (OE)
is high, both output devices are off, and the PAD acts as an input to the circuit.
5.4 SUMMARY
This chapter raises the level of transistor integration, showing how primitive CMOS com-
plementary combinational logic gate designs are built from Boolean algebra equations.
More compact circuits that have different power dissipation and speed properties illustrate
c05.qxd 2/2/2004 12:26 PM Page 147
REFERENCES 147
0.25
0.2
0.15
IDD (A)
0.1
0.05
Vtrig
0
0 0.5 1 1.5 2 2.5 3
VDD (V)
Figure 5.27. Current voltage characteristics of a parasitic bipolar structure underlying a CMOS
single-well process.
data
(out) I/O
PAD
input/ output
control
(OE) data
(in)
Figure 5.28. A bidirectional I/O circuit.
the popular tri-state gate, pass transistors, and dynamic logic gates. All versions appear in
modern CMOS IC design. Sequential or memory-storing circuits partner with combina-
tional logic to build complete ICs. Latches are the first building block, but have trans-
parency properties eliminated by combining latches and transmission gates into flip-flops.
Finally, the latchup failure mechanism and important input/output circuits were described.
REFERENCES
1. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, Wiley, 1995.

2. R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE
Press, 1997.
3. K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, and N. Rohrer, High
Speed CMOS Design Styles, Kluwer Academic Publishers, 1998.
4. R. H. Krambeck, et al., “High speed compact circuits with CMOS,” IEEE Journal of Solid State
Circuits, 17, 3, June 1982, 614–619.
5. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, Prentice-Hall, 2003.
6. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, 2nd ed.,
Addison-Wesley, 1993.
c05.qxd 2/2/2004 12:26 PM Page 148
EXERCISES
5.1. Given the Boolean function F = z[x苶yz + xz苶], draw the static CMOS transistor
schematic.
5.2. Write the Boolean expression F for A, B, and C in the circuit in Figure 5.29.
A B C
A B B
Figure 5.29.
5.3. Draw the static CMOS transistor schematic that performs the Boolean function F =
(g + f) · (m + n).
5.4. Draw the CMOS transistor schematic that fulfills the function F = 苶[(苶A
苶苶·苶苶B
苶)苶苶+
苶苶C
苶]苶苶·苶苶D
苶
for both a static and a domino CMOS logic gate.
5.5. Given the schematics of Figure 5.30:

(a) If it corresponds to the CMOS pull-up network of a static circuit, what is the
resultant Boolean expression F?
(b) If the p- and the n-channel transistors are sized for equal drive current, discuss
whether the pull-up will be faster than the pull-down network, or they will they
be the same.
A B C D E
Figure 5.30.
5.6. What Boolean function will the circuit in Figure 5.31 perform?
5.7. Determine the logic function of the circuit in Figure 5.32.
5.8. Given the circuit of Figure 5.33:

(a) Determine the role of A, B, and C nodes (input or output).
(b) Determine its Boolean function.
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EXERCISES 149
clk
A B
Figure 5.31.
B
C
Figure 5.32.
A B
Figure 5.33.
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5.9. The circuit of Figure 5.34 has the same function as a basic block used in sequential
circuits. Identify the circuit type and the conventional names given to the inputs and
outputs. Hint: analyze the equivalent circuit for y = 0, and then for y = 1.
x
y z
t
Figure 5.34.
5.10. Figure 5.20(b) shows the transfer properties of a simple static memory circuit. Sup-
pose the input Vi is a short pulse with amplitude 0.6 VDD. If V0 drives another latch,
what is the effect on (a) overall timing, (b) noise sensitivity (margin).
5.11. Identify the function and the input/output conventional node names for the circuit
in Figure 5.35.
z
t
Figure 5.35.
5.12. Combine two circuits of Exercise 5.11 to get a flip-flop.
5.13. (a) What is the difference between EOS and ESD?

(b) If an input protection circuit protects the inner core logic from an ESD assault,
but it is damaged, has the protection circuit done its job?
5.14. The DRAM circuits in Figure 5.23 store the bit (voltage) information on a capaci-
tor. Use knowledge from Chapter 2 to determine the affect on refresh frequency if
the temperature rises.
5.15. Observe the Schmitt trigger circuit in Figure 5.25(a). Explain how the transfer
curves in Figure 5.25(b) behave as the input signal drops from VDD to 0 V. Describe
the transistor action.
5.16. If latchup occurs in a CMOS circuit and draws a large current, how do you stop
it?
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PART II
FAILURE MODES, DEFECTS,

AND TESTING OF CMOS ICs
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CHAPTER 6
FAILURE MECHANISMS IN
CMOS IC MATERIALS
6.1 INTRODUCTION
A single modern IC may have more than a billion transistors, miles of narrow metal inter-
connect ions, and billions of metal vias or contacts. As circuit entities, metal structures
dominate the semiconductor transistors, and their description is as challenging and neces-
sary as that of semiconductors. Transistor oxides have shrunk, and dimensions are now on
the order of 5–7 SiO2 (silicon dioxide) molecules thick. Metal and oxide materials have
failure modes that have always been with us, but are now even more significant in the
deep-submicron technologies. This chapter addresses these IC failure modes that are
caused by failure of materials.
This chapter has three sections:
1. Materials Science of IC Metals

2. Metal Failure Modes
3. Oxide Properties and Failure Modes
We do not seek to overwhelm the reader with mathematical detail, but rather to use visual
models and learn the conditions that cause IC materials to fail in time due to interconnect
bridges opens or damaged oxides. Circuit failure modes challenge the quality and reliabil-
ity of large deep-submicron ICs. High-performance ICs now push safety margins closer to
expected product lifetimes than before to achieve high clock frequencies. Added concerns
are that previously dormant metal and oxide failure modes may now appear at test or dur-
ing product life.
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154 CHAPTER 6 FAILURE MECHANISMS IN CMOS IC MATERIALS
We refer to intrinsic material as defect-free, and extrinsic material as containing de-

fects. Reliability failure modes are typically identified with failures of intrinsic material,
whereas extrinsic material is linked to burn-in yield or production test failures. There are
gray areas in this division, since some latent failure modes are related to (extrinsic) de-
fects present during fabrication, but are too difficult to detect at test. Also, violation of
fabrication procedures or design rules are known to cause postfabrication failures. Defec-
tive thin oxide that leads to rupture of the oxide, or metal stress voiding as a serious metal
open failure mechanism are examples that are described later. Parts can fail at the next
level of assembly or in the field, but detection of defects causing these serious failures
may be almost impossible earlier in the product cycle. Test engineering deals with extrin-
sic materials, whereas reliability and failure analysis engineers deal with both material
types.
Materials science studies the defects of a solid and their relation to the solid’s physical
properties [2, 3, 4]. The materials foundation of modern ICs were built on this old science.
Several material classes exist, but we will only study metals and dielectrics. For many
years, Al (aluminum) dominated signal and power interconnections, and SiO2 was the thin
and thick oxide material of the IC. Cu (copper) is now the popular interconnect material
and new dielectrics are being developed to replace SiO2. It is a nontrivial challenge to in-
troduce new materials into the known and controlled CMOS IC manufacturing process.
6.2 MATERIALS SCIENCE OF IC METALS
Interconnect metals are thin films made of small, single crystals called grains. Metal
grains are crystals similar to silicon crystals, but their grain surfaces are irregular and not
smooth like silicon crystals. Figure 6.1 is a photograph of a polycrystalline Al line with its
grain boundaries marked artificially for clarity. The irregular grain boundaries are impor-
tant interface regions that influence the metal resistance against forces that can move
atoms and lead to open or bridge metal lines. Metal failures involve extrusions or voids,
and so require movement of Al atoms along easy paths, such as grain boundaries. Grain
boundaries are about 1–2 atoms wide and are relatively open spaces, allowing easy travel
for moving atoms. If a line has large grains and thus fewer grain boundaries, atoms have
less opportunity for displacement. The metal in Figure 6.1 has many paths for a mobile
metal atom to follow, increasing the likelihood of net Al atom dislocation in the presence
of forces in the metal. This chapter looks at these metal forces that derive from electron
current, temperature gradients, atomic concentration gradients, and mechanical stress
forces.
Figure 6.2 shows two of the 14 possible crystal structures (Bravais lattices). The dots
represent the center of the atoms since atomic volume usually extends to neighboring
atoms. Figure 6.2(a) shows the corner atoms of a unit crystal with an additional atom
Figure 6.1. Al grains in IC interconnect. (Reproduced by permission of Bill Miller, Sandia Nation-
al Labs.)
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6.2 MATERIALS SCIENCE OF IC METALS 155
33
1
1
5
5
(a) (b)
Figure 6.2. (a) Body-centered cubic cell (W). (b) Face-centered cubic cell (Al, Cu).
placed in the middle of the cube. This structure is called a body-centered cubic (bcc) cell,
and is found in W (tungsten). The dots on the corners are drawn larger than the one in the
middle for viewing clarity. Figure 6.2(b) shows a face-centered cubic (fcc) cell with an
atom placed in the center of each face of the unit crystal. This is the structure of Al and
Cu.
The unit crystals in Figure 6.2 can interpret the variable strength of a metal when
forces are applied in any direction. Some directions are very resistant to applied force, and
other directions are weak. Figure 6.2b numbers corner atoms 1, 3, and 5. If the unit crystal
is viewed perpendicular to the plane of these three atoms, and the atoms are enlarged to
represent their full diameters, then we see six atoms (Figure 6.3). The corner and face-
centered atoms touch, and that surface is called the close-packed plane. The atoms bond
strongly in this plane, and lateral forces that try to pull the atoms apart find it difficult to
do so. This plane is called the 111 plane, following crystal convention. A force perpendic-
ular to the close-packed plane dislodges atoms more easily because nearest neighbor
atoms in this direction are further apart, and bonding strength is less. A fortunate result of
laying down Al interconnections on the substrate of an IC is that the 111 texture is ener-
getically favorable. Deposited atoms fill up available space next to the substrate just as or-
anges do when dumped on the bottom of a grocery fruit bin. This forms a crystal in the
111 plane that is the densest plane, so that more atoms can get closer to the substrate. This
places the close-packed plane parallel to the majority of forces that act on the horizontal
plane (especially electron flow), providing a natural resistance to dislocation of atoms.
1 3
5
Figure 6.3. Close packed plane of fcc metal.
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Metal crystals are imperfect. They have defects that can be intentional, such as alloyed
metals, or unintentional from contamination by other atoms or thermal dislocations in a
pure metal. Figure 6.4 illustrates three important metal crystal defects. Small atoms, such
as B (boron) or H (hydrogen), can squeeze between larger metal atoms and form intersti-
tials. Their small size allows easy diffusion within the host material. Some atoms can re-
place a host metal atom and are called substitutionals. Copper forms substitutionals in Al,
and is intentionally alloyed with Al to strengthen the metal. A third defect appears natural-
ly due to thermal vibration in otherwise perfect crystals, and is called a vacancy.
The vacancies in Figure 6.4 are locations in the metal lattice where an atom is missing.
This is a natural condition of the high-frequency, thermal-induced vibrations of atoms. At
any instant, there is a probability that an atom has vibrated out of its host position. There
are no vacancies at 0 K, but they increase exponentially as temperature rises. Vacancy ex-
istence is a condition for movement of metal atoms. When metal atoms move within the
lattice, such as in Figure 6.4, they must have a place to go. If an atom jumps into a vacan-
cy, then it creates a vacancy at the location it left. Motion of vacancies is similar to the
hole motion concept in semiconductors, except that vacancies don’t have an electrical
charge.
Metals have line, area, and volume defects besides the atomic defects in Figure 6.4.
Volume defects are large metal voids or precipitates. A common line defect called an edge
dislocation is drawn in Figure 6.5. The regular array of metal atoms is missing a few
atoms in one of the crystal planes. Stress forces appear in the region of the circle. The top
three atoms in the circle are in compression, and the bottom two atoms are in tension. The
metal wants to relieve this energy. The compressive and tensile forces encourage a move-
ment of atoms along the slip plane. The significance of these defects is that the metal is
less resistant to holding its structure in the face of external forces (described later). Its
strength is less than that of a perfect metal. When stresses are relieved to lower energy
states, such as in heat annealing of metal, then conductivity increases. Electrons move
easier in a crystal without alloy elements or other defects, although alloy elements are in-
tentionally added to provide mechanical strength.
Grain boundaries are area defects. Figure 6.6 is a photograph of a narrower metal line
than the one in Figure 6.1. The arrows locate points where three grain boundaries merge
to form a triple point. If Al atoms move in a single grain boundary that merges with two
other grain boundaries, then at the merger, more atoms can leave that point than enter (or
vice versa). This is called a flux divergence site. For example, if Al is moving from right to
left in Figure 6.6, then the first triple point will show more atoms entering the point than
Vacancy
Interstitial
(B,H)
Substitutional
(Cu)
Figure 6.4. Imperfections in a metal crystal. Cu is not drawn to scale; it is about two times larger
than Al.
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6.2 MATERIALS SCIENCE OF IC METALS 157
Slip
Plane
Figure 6.5. Edge dislocation and slip plane.
leaving, causing compressive buildup of atoms. At the second triple point, more atoms
will leave than enter, causing tensile forces. The opposite polarity stress sets up a stress
gradient.
The vertical grain boundary shown toward the left in Figure 6.6 is typical for metal
lines of <0.5 ␮m, in which grains are large compared to the metal width. The very small
lines in deep-submicron ICs have mostly these vertical or bamboo structures. You will no-
tice that whereas an Al atom may move laterally in Figure 6.6 along longitudinal grain
boundaries, it virtually stops when it encounters an orthogonal grain boundary. Metal
lines with bamboo structures are generally stronger than those with triple points
The last topic in this capsule view of materials science concerns the physical gradients
that can drive metal atoms. The link between physical gradients and particle (atoms) mo-
tion is subtle. Consider four potential gradients that drive metal atoms:
1. dC/dx Concentration gradient of atoms—diffusion

2. dT/dx Temperature gradient in solids—thermotransport
3. dV/dx Voltage gradient in solid—electromigration
4. d␴/dx Stress gradient in solid—stress voiding
The concentration gradient causes net atom motion because all atoms are in thermally in-
duced motion. The direction of motion is random, so the region of denser atoms will have
more atoms diffusing toward the region of lower density than vice versa. A net dislocation
of atoms occurs. Similarly, a temperature gradient has a region of higher-energy (chemi-
cal potential) atoms, and the more energetic ones can move to the lower chemical poten-
tial energy, similar to the motion induced by a concentration gradient. The voltage and
stress gradient forces are discussed in detail since they relate to the electromigration and
Figure 6.6. Al metal and (marked) grain boundaries. (Reproduced by permission of Bill Miller,
Sandia National Labs.)
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stress voiding metal failures discussed later. Fick’s diffusion laws and the concept of
chemical potentials underlie all four forces.
Diffusion can be measured for the many atomic elements under diverse conditions
such as solid, liquid, or gas phases, or for different structural conditions. Diffusivity de-
notes the measurement of diffusion, and is defined by Einstein’s relation: D = ␮ · kT
(cm2/s), where ␮ = particle mobility and k = 1.38 × 10–23 Joules/K (Boltzmann’s con-
stant). D is exponentially related to Kelvin temperature (T), an activation energy (Ea), and
a material-dependent constant (D0) by
D = D0e–Ea/kT (6.1)
Figure 6.7(a) shows the exponential diffusivity (D) relation to temperature, and Figure
6.7(b) plots the commonly presented straight line of ln(D) versus T–1.
Generic curves are shown for diffusivity (Figure 6.7b) when the metal atoms are in a
GB (grain boundary) or diffusing within the crystal lattice. GBs have a diameter that is
about twice the size of an atomic diameter, and at low temperatures (right-hand side of x-
axis), the grain boundaries have a higher diffusivity than the tightly packed crystal lattice
region. As temperature rises, the diffusivity of atoms in the lattice increases and surpasses
that of grain boundaries. Metallurgists estimate that the crossover temperature is between
0.4 Tmp to 0.6 Tmp (Tmp = metal melting point). Al melts at Tmp = 660°C = 933 K, so that
the estimated temperatures at which diffusivity crossover occurs are between 100°C to
287°C.
Modern high-performance ICs have average package temperatures above 100°C and
IC hot spots of even higher temperatures. The junction temperature of an IC is defined as
the temperature of the silicon substrate, and it is a crucial parameter of reliability-predic-
tion procedures and burn-in testing. The measured junction temperature of a 1 GHz 64-bit
RISC microprocessor implemented in 0.18 ␮m CMOS technology was reported as 135°C
at VDD = 1.9 V [1]. This microprocessor had 15.2 million transistors packed in the 210
mm2 chip area. High temperature allows higher diffusivity of metal atoms, which can lead
to shorter failure times.
Review. Metal studies began over 100 years ago, and their application to IC thin metal
films (interconnections) has a solid knowledge base. Metals are polycrystalline, with
Lattice
D ln D
D = Doe -Ea/kT
GB
T (oK) 1/T (oK)-1

(a)
(a) (b) (b)
Figure 6.7. Diffusivity of grain boundary and lattice with temperature.
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6.3 METAL FAILURE MODES 159
grain boundaries that separate the grains and influence the quality of the metal. Metal de-
fects and high temperature make it easier for atoms to move within a metal, and reduction
of these effects requires strong effort by industry. Concentration, voltage, temperature,
and mechanical-stress gradients will move metal atoms within an interconnect. The move-
ment of atoms leads to open or bridging circuit defects that are the next topics.
6.3 METAL FAILURE MODES
6.3.1 Electromigration
Electromigration is the net movement of metal under the influence of electron flow and
temperature. A metal line will fail if sufficient current density and high temperature are ap-
plied. Metals can form a void or may form an extrusion that projects from one of the sur-
faces of the metal. This failure mechanism is called electromigration (EM). The abundant
knowledge about aluminum (Al) failures is presented first, followed by a description of
copper (Cu) failure mechanisms.
Figure 6.8 is an unusual photograph of two electromigration failure sites in a wide, un-
passivated Al line. Here, Al atoms presumably exited the voided region and moved to the
extruded bulging region on the left. Electromigration almost stopped the IC industry in
the 1960s until methods were found to control electromigration. Electromigration studies
began over 35 years ago, and much is known about this failure mechanism.
Electrons are believed to transfer a small but sufficient momentum to thermally active
metal atoms forcing those atoms, out of their lattice sites, and moving them under diffusion
in the same direction as the electrons. Figure 6.9 illustrates an Al metal line with electrons
moving from right to left and colliding with Al atoms. If the thermal energy of Al is at a lev-
el such that a small nudge from many electrons dislodges it, then it will move if there is a
vacancy to move into. That critical energy is called a saddle point. A small tensile stress is
Figure 6.8. Electromigration SEM photo in a wide, unpassivated metal line. (Reproduced by per-
mission of Joe Clement, Sandia National Labs.) Electron current and Al atom motion is from right
to left.
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Al atom Electron
Figure 6.9. Representation of moving electrons and metal atoms during electromigration.
created where an atom is knocked from its lattice site, while downstream, the displaced
metal atom creates compressive forces and possible extrusions. The region between the
compressive and tensile stresses is under a stress gradient. Figure 6.8 shows these concepts,
where the electron current (j) direction displaces Al atoms in the region of the void, and
those atoms pile up downstream, forming an extrusion through passivation.
The variables that affect electromigration are clues used to reduce the threat, and we
will present a model of electromigration using these variables. A flux J is the number of
particles (atoms in this case) crossing a unit area per unit time. Table 6.1 lists the equa-
tions and subequations that lead to an expression for the atomic flux Jem of an electromi-
grating metal atom [9]. Equations are given in the middle column and substituted vari-
ables are given in the right column.
The final flux expression for electromigrating atoms is
冢冣
D atoms
Jem = ᎏ (Z* · q)␳ · je · N ᎏ (6.2)
kT cm2 · s
Equation (6.2) is not typically used to calculate numbers, but to identify variables that in-
fluence electromigration. The flux is governed by diffusion and electromigrating atoms,
and is said to be under a biased or directed diffusion. The temperature sensitivity of elec-
tromigration diffusion in Equation (6.2) is seen in Equation (6.1) showing the exponential
temperature dependence.
Table 6.1. Electromigration Flux Jem Derivation

Magnitude Equation Symbols
Atomic flux Jm Jem = vN v = mean velocity of metal atoms
N = concentration of moving metal atoms
Effective charge Q Q = Z*q Z* = effective charge factor
q = electron charge
Atom mobility ␮ = QD/kT D = diffusivity
kT = Boltzmann’s thermal energy
Atom mean velocity v = ␮Ᏹ ␮ = atom mobility
Ᏹ = electric field
Electric field Ᏹ = ␳je ␳ = metal resistivity
je = electron current density
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The RHS of Equation (6.2) has an electron current flux term je, whereas the LHS is a flux
of atoms. The Z* term performs a cross coupling in the equation from electron current den-
sity to metal atom flux. One qualitative interpretation of Z* is that it is the ratio of imping-
ing electrons to a single metal atom that is moved. The driving electric field for electrons is
the product of resistivity and electron current density across a 1 cm length, and the units are
V/cm. Equation (6.2) reinforces that at a given current density and temperature, metal
atoms will move along the metal stripe in the same direction as the electrons.
Electromigration Failure Time. A different analysis looks at the electromigration

variables that affect the time for a metal line to fail, tF. James Black made major contribu-
tions to understanding electromigration failure [5]. He empirically derived Black’s law,
which states that the median time to failure (tF) of a group of Al interconnects is
A0 E /kT
tF = ᎏ e a (6.3)
j e2
A0 is a technology-dependent constant, T is temperature in Kelvin, je is electron current

density (A/cm2), and Ea is the activation energy (eV) for electromigration failure. Metal
grain structures vary considerably, so that tF is a statistical quantity not a predictor of sin-
gle line failure time. Black’s law shows the electromigration failure dependence on j e–2.
When a design is shrunk, current density usually increases, so that designers must work to
reduce je. An older DC design rule for CMOS technologies kept je < 0.2 – 1 mA/␮m2.
This was a crude estimate with a built-in safety factor. Electromigration design rules for
metal dimensions are now taken from circuit simulators that compute average current
density and expected temperature in a local interconnection. The waveshape of the current
pulses and the dimensions of the metal line needed to assure metal safety are calculated
from these variables. Although je reduction is important, the exponential temperature term
has a more acute effect on tF.
The Black’s law exponent of je is given as n = 2, as the original equation stated. Subse-
quent knowledge showed that n can vary from 1 < n < 2 depending on the metal structure.
We will use n = 2 for simplicity.
Black’s law predicts failure time, and that is useful in test structure studies under accel-
erated temperature and current density. tF is typically measured as the median time to fail-
ure of many test structures. However, Equation (6.3) is more often used to calculate Ea for
the metal when tF is measured. Ea is the accepted parameter to assess the electromigration
quality of a metal technology. If tF is measured over a temperature range, then Ea can be
calculated from the slope of a plot of ln (tF) versus (1/kT). If Ea is in the low range of Ea ⬇
0.4 to 0.6 eV, then the quality of the metal is poor, usually indicating an abundance of
grain boundary paths. If Ea ⬇ 0.8 eV to 1.0 eV, then metal quality is good and indicative
of bamboo structures. The calculated upper limit on Ea is that of a pure Al crystal, where
Ea ⬇ 1.48 eV. A metal interconnect line made of a pure, single Al crystal would be the
best structure possible, but this has not yet been practical.
왎 EXAMPLE 6.1
Use Black’s law [Equation (6.3)] to estimate the reduction in useful product life
if a metal line is initially run at 55°C at a maximum line current density of 0.6
c06.qxd 2/2/2004 12:31 PM Page 162
MA/cm2, and then run at 110°C and 2 MA/cm2. Use Ea = 0.7 eV and Boltz-
mann’s constant of k = 86.17 ␮eV/K.
Black’s law can be written for T = 55°C = 328 K and je = 0.6 MA/cm2. Then
divide by Black’s law for T = 110 °C = 383 K and je = 2 MA/cm2. A0 cancels, and
we get the electromigration acceleration factor AEM
2
tF1(328 K) j e2 (2.0 MA)2 0.7/k[(1/328)–(1/383)]
AEM = ᎏᎏ = ᎏ 2
= eEa/k[(1/328)–(1/383)]
= ᎏᎏ e = 389.4
tF2(383 K) j e1 (0.6 MA)2
왎
Typical practice rounds AEM off to a single digit, or AEM = 400. The result is that the
hotter part has an estimated useful life shortened by a factor of 400. If nominal life is pro-
jected for 15 years for the cool part, then the hot part has a predicted life of about 2 weeks.
This example is realistic since modern high-performance ICs have package temperatures
of 100 °C, and the dies are even hotter. Designers push the je limits, since this increases
clock frequency performance. This is one example where reliability margin and improved
performance can be traded off.
Self-Exercise 6.1
An IC part has an operating temperature 10°C above its specification due to

mounting in a package with poor thermal impedance. If metal Ea = 0.8 eV and
normal use temperature is 85°C, (a) what percentage must the metal current den-
sity be reduced to maintain the same expected time to fail (tF), and (b) if the part
is run 10°C hotter, what is the reduction in lifetime.
How Metals Fail in Electromigration. Metals need an imperfection or defect in the

structure to begin the failure process. Unfortunately, metals have unavoidable vacancies
and irregular grain boundary patterns that can initiate electromigration. The ultimate fail-
ure may be an open circuit, or the metal may exert pressure at a site and break the passiva-
tion layer, and possibly form a defective bridge. Figure 6.10(a) shows an electromigration
failure caused by extrusion of the Al through the passivation material, forming a bridge to
another interconnection. Figure 6.10(b) shows a commonly seen open circuit notching
characteristic of narrow metal lines (< 0.5 ␮m).
Failures commonly occur at a flux divergence site, and Figure 6.11 sketches two exam-
ples. Figure 6.11(a) shows a region of increased granularity that provides many more
paths for Al to move in. The left side of the granular region undergoes tension as atoms
leave this location and are easily transported in the granular region. The right border of the
granular region undergoes compression as atoms find fewer travel paths and are stuffed
into a volume smaller than their natural spacing. The tension and compression regions set
up a stress gradient that actually acts to retard the left-to-right motion of Al atoms under
electromigration. That is an important failure relief concept that will be developed later.
Figure 6.11(b) shows temperature differences along a line that can lead to flux diver-
gence. The hot region has a higher concentration of vacancies, and Al atoms will diffuse
more readily here than in the cold region. The Jm1 flux tends to cause voiding and tension
in and near the hot region, and compression as the moving atoms leave the hot region and
approach the cold region. Since the mechanism for motion is diffusion, the cold region
c06.qxd 2/2/2004 12:31 PM Page 163
(a)
(a) (b)
(b)
Figure 6.10. (a) Extrusion and bridging defect from EM. (b) Narrow metal line electromigration.
(Reproduced by permission of Rod Augur of Philips Semiconductors; reprinted with permission
from “Diffusion at the Al/Al oxide Interface during Electromigration in Wide Lines,” J. Appl.
Physics, 79, 6, 15 March 1996, pp. 3,003–3,010. Copyright 1996, American Institute of Physics.)
relatively stops the moving atoms (Jm2). The compression can be large enough to rupture
the passivation material, allowing extrusion of the metal into the ruptured region [Figure
6.10(a)].
Another serious flux divergence site appeared when W (tungsten) was adapted as a via
material in multilayer Al metal ICs. Tungsten has a high melting point, stronger atomic
bonds, and high resistance to electromigration. Figure 6.12(a) sketches a metal intercon-
nect with W vias and a TiN (titanium nitride) liner over the top and bottom of the Al line.
Electrons entering the structure at the upper right direct Al atoms toward the W via. There
is no net motion of atoms in the W, so the Al atoms pile up, causing compression at the top.
Since electrons move unimpeded through the W via, they can dislodge Al atoms on the oth-
er side of the via, leading to voiding at the bottom (Figure 6.13). The left-side via experi-
ences the opposite effect—compression on the bottom and tension (voiding) at the top.
Figure 6.12(b) shows a metal structure with Al vias. Here, Al atoms will pass through
all structures. Unless there are local flux divergence sites along the path, there will not be
voiding or compression. W replaced Al as the via material several years ago when reduced
scaling made it difficult to retain Al. Cu (copper) interconnections with Cu vias unfortu-
(a)
JJm1m 1 JJm2m 2
jjee
( b)
JJm1
m1 JJm2m2
jjee Ho t C old
Figure 6.11. Flux divergence sites due to (a) granularity differences, (b) temperature gradient.
c06.qxd 2/2/2004 12:31 PM Page 164
W
Al
TiN
(a)
(b)
Figure 6.12. Metal–via structures (a) Al–W–Al. (b) Al–Al.
nately have a thin barrier metal interrupting the Cu flow at the bottom of the via. This flux
divergence site is a common location for Cu electromigration voiding.
The TiN metal adjacent to the Al is a safeguard against breaks that might occur in the
Al (Figure 6.13). If an open circuit forms in the Al, then current will pass through the TiN
shunt path. This open-circuit protection does not prevent extrusions that occur horizontal-
ly and form bridges. However, barrier metals on the Al are a good retardant to electromi-
gration voids, and one reason why electromigration is not more prevalent. Barrier metals
such as TiN safely shunt current around an Al void location, but resistivity of barrier met-
als can be 30–40 times higher than Al. Voltage drops are typically small, but surprisingly
large amounts of heat may be generated. Self-Exercise 6.2 illustrates this.
Figure 6.13. Void at the bottom of the blocking tungsten plug in metal-1 aluminum–copper alloy
due to accelerated electromigration stressing [7].
c06.qxd 2/2/2004 12:31 PM Page 165
Self-Exercise 6.2
The Al void in Figure 6.14 is 2.5 ␮m long and 1 ␮m wide, and the resistance of
the TiN conduction path is 3 ⍀. The current shunts through the 2.5 ␮m of TiN
and then back to the Al. Calculate the heat flux (Watts/cm2) at the TiN surface,
assuming that all heat goes out the bottom surface when: (a) current is 100 ␮A
and (b) current is 10 mA. (c) What are voltage drops across the shunted void?
(The problem assumes only one side of the Al is shunted by TiN.)
1 µm
Al 2.5 µm
Al
TiN
Figure 6.14. Al metal line with a void.
Current Polarity and Pulse Frequency. Three current waveform types exist in met-
al: pure DC, unipolar pulse currents with an average DC value, and bidirectional (bipolar)
currents. DC currents exert the most electromigration stress, and are the typical condition
for process characterization and long-term reliability studies. With the exception of off-
state leakage, pure DC currents do not appear in CMOS circuits that are fully static and
fully complementary. Fully static means that the circuit can operate at zero clock frequen-
cy, and fully complementary means that there are equal numbers of pMOS and nMOS
transistors per gate. DC currents may appear if pull-up or pull-down resistors are used, or
in any design that allows a continuous path from VDD to VSS. A significant reliability im-
plication is that CMOS DC currents are also caused by most bridge defects and certain
open-circuit defects. If these defect-induced currents exceed electromigration design
rules in a given interconnect, electromigration may unexpectedly occur.
Unipolar pulses have an average DC current that occurs in drain or source terminals.
Positive current always enters the source of a pMOS transistor (dotted line in Figure 6.15)
and exits the drain, whereas current always enters the drain of an nMOS transistor and ex-
its the source. The transistor gate voltage turns source–drain current on and off. The aver-
age (DC) current is used as the stress parameter for electromigration.
Bipolar current (solid line in Figure 6.15) occurs in the interconnections from a gate out-
put terminal to the next logic gate input. Current enters the load gate interconnection,
charging the capacitance during pull-up. The current reverses direction during pull-down.
Interconnects carrying bipolar current have a low susceptibility to electromigration be-
cause damage caused on the forward current phase tends to heal on the reverse current
phase. Metal atoms move in one direction during pull-up, and then reverse their direction
during pull-down.
Blech Effect and Electromigration. The force between atoms at a given temperature
is similar to the force between balls attached by a mechanical spring. If you push against a
crystal of Al atoms, they compress and exert a back force. That back force acts on the com-
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Unipolar
Bipolar
CL
Figure 6.15. Unipolar and bipolar currents.
pressed atoms, tending to eject them from the stressed space. If tension is put on a crystal,
then the opposite effect occurs as the region will tend to pull atoms back into the tensile
space. Ilan Blech found an interesting and beneficial relation between electromigration and
stress gradients [6]. He discovered that for a fixed metal line length, there was a current den-
sity below which electromigration would not occur. Conversely, for a given current density,
there was a line length below which electromigration failure also would not occur. This so-
called Blech effect is important in containing electromigration in deep-submicron ICs. We
will derive the Blech effect flux equations as we did earlier for electromigration in Table 6.1.
Stress analysis uses mechanical concepts. We will derive the Blech effect starting with
the definition of stress (␴):
F
␴= ᎏ (6.4)
A
where F is the force across a material with area (A). A material or atom with high stress
(␴), but no stress gradient (d␴/dx = 0) has no driving force to move it. However, when a
stress gradient is present, then the force on an atom with atomic volume ⍀ is
d␴
F␴ = ⍀ ᎏ (6.5)
dx
This expression is subtle, but quite important for understanding stress voiding in metals.
The equation predicts that applying equal high stress throughout a material has no dis-
placement influence on particles, molecules, or atoms, but a difference in stress across a
material will tend to move an atom. How is this so?
Figure 6.16 shows a unit cube representing a small solid. Initially, the block has no net
force on its sides, but when a force F is applied to the right-hand face, the x-dimension
compresses by ⌬x. If the left-hand side is constrained, we can derive the relation between
the force, cube dimensions, pressure (p), and induced stress ␴.
The energy statement (w) including pressure (p) and volume (v) is
dw = F · ⌬x = ⌬p · ⌬v (6.6)
or
⌬p
F = ⌬v ᎏ (6.7)
⌬x
c06.qxd 2/2/2004 12:31 PM Page 167
⌬x
Figure 6.16. Element volume of particle or atom under stress forces.
Since stress ␴ = p, and the smallest volume is an atom of volume ⍀, then
⌬V = ⍀ (smallest unit volume, approximately an atomic volume) (6.8)
and in the limit
d␴
F = ⍀ᎏ (6.9)
dx
If a stress gradient exists in the metal, then Equation (6.9) provides the force on atoms to
move them with the stress gradient. Equation (6.9) allows us to derive the flux equation
using an electromigration-induced stress gradient, and then an equation for the Blech ob-
servation. The initial flux equations are
D
J␴ = vC = (␮F)C = ᎏ FN (6.10)
kT
Substituting Equation (6.9) into Equation (6.10) gives the flux term for metal under a
stress gradient J␴:
D d␴
J␴ = ᎏ ⍀ ᎏ N (6.11)
kT dx
The diffusion mechanism is evident in the stress effect. Electromigration simultaneously

creates a tensile force and a compressive force as an atom is displaced. Blech recognized
that the electromigration force and an oppositely directed stress gradient force may
achieve a flux balance, thus stopping the net flow of atoms. Those two electromigration
(Jem) and stress driven (J␴) fluxes are repeated:
D
Jem = ᎏᎏ(Z* · q)␳ · je · N
kT
(6.12)
D d␴
J␴ = ᎏᎏ⍀ᎏᎏN
kT dx
At equilibrium, the absolute values of the fluxes are equal, J␴ = Jem.

c06.qxd 2/2/2004 12:31 PM Page 168
σmax
0
σ
-σmax
-lm/2 0 lm/2
x
Figure 6.17. Stress versus distance curve for a thin film of metal.
Figure 6.17 shows a stress versus distance curve for a passivated metal. The stress gra-
dient is assumed to be due to metal atom migration from the LHS of the curve to the RHS.
␴max is the maximum stress that the passivation can take before it cracks.
We can rearrange Equations (6.12) as
⍀d␴
jedx = ᎏ (6.13)
Z*q␳
This balance equation requires one last concept. The balance ends when the passivation
ruptures at a distance lm under the high pressure of a maximum stress ␴max. If dx is inte-
grated from x = –lm/2 to +lm/2 and stress from –␴max to +␴max we get
冕 lm/2
–lm/2
jedx = 冕
␴max
–␴max
⍀
ᎏ d␴
Z*q␳
(6.14)
or
2⍀␴max
lmax je = ᎏ (6.15)
Z*q␳
The labor needed for this derivation is worth the result. The RHS of Equation (6.15) is a
constant for a given technology. If we raise je, then lmax must drop and vice versa. Equation
(6.15) explains Blech’s law. Experimental measurements find the lmax · je product is about
1,000–3,000 A/cm for unpassivated metal. An example and exercise will illustrate this.
왎 EXAMPLE 6.2
An Al interconnect has a length of 100 ␮m. If the (lmax · je) product is 3,000
A/cm, what current density limit should be assigned to prevent electromigration?
lmax · je = 3,000 A/cm = (100 ␮m)( je)
So if je < 3 mA/␮m2, electromigration will not occur in this unpassivated line. 왎

c06.qxd 2/2/2004 12:31 PM Page 169
Self-Exercise 6.3
If the (lmax · je) product is 3,000 A/cm, what maximum length should the IC in-
terconnect lengths be if designers keep effective current densities in all lines at
less than 1.2 mA/␮m2.
Electromigration and High Frequency. Lines carrying pulsed currents show more
resistance to electromigration as the frequency increases. Figure 6.18 shows the increase
in tf for a 50% duty cycle as current pulse frequency increases from DC [16]. During the
off-portion of the cycle, a back stress is exerted on the metal from atoms moved during the
on-cycle. As pulse frequency increases, average line temperature rises, increasing back-
diffusion efficiency and healing during the off-state. This is an unusual case of metal reli-
ability increasing with temperature.
6.3.2 Metal Stress Voiding

A bad “discovery” was made in the early 1980s when certain metal lines pulled apart,
forming open circuits even if the IC was not powered. This failure mechanism, called
stress voiding, (or stress-induced voiding) was linked to the TCE (thermal coefficient of
expansion) differences of metal and the passivation materials surrounding it. When de-
posited metal is taken to 400°C or higher for a passivation step, the metal expands and
tightly bonds to the passivation material. When cooled to room temperature, enormous
tensile stresses arise from the differences in the TCE of the metal and passivation materi-
al. The passivation material basically does not move, so the metal bonded to the passiva-
tion material undergoes extreme tensile stress. These stresses are parallel to the metal line,
and can pull lines apart if stress gradients appear. The time required to do this varies with
the quality of the metal. It can happen during the fabrication process itself, or can take
weeks to years for voiding to appear. Figure 6.19 shows photographs of two stress void
failures.
20
DC 10 kHz
15
∆R0 (%)
10
5
8.6 MHz 499 MHz
0
-5
0.0e+0 2.0e+3 4.0e+3 6.0e+3 8.0e+3
Time (s)
Figure 6.18. Time to failure versus current pulse frequency [16].

c06.qxd 2/2/2004 12:31 PM Page 170
Figure 6.19. Stress void photos. (Reproduced by permission of Bill Filter, Sandia National Labs.)
Stress void analysis uses concepts from materials science, physics, and mechanical
engineering. It is a mechanical failure mechanism that involves no electron current, but
often it is the most prevalent metal failure mode in modern ICs. We will examine un-
passivated and passivated metal line responses to the large mechanical forces that they
undergo in normal IC environments. Passivation layers provide electrical isolation and
protection to the metals, but the unavoidable problem lies in the sharp differences of
thermal expansion coefficients. Al has a TCE = ␣ = 23.6 × 10–6 parts per °C, and sili-
con dioxide has an ␣ = 0.5 × 10–6 parts per °C. This means that a 1 meter Al line will
expand by 24 ␮m for each degree of elevation in temperature, and SiO2 by 0.5 ␮m per
degree.
When SiO2 is deposited and tightly bonded to Al at 400°C, there are no thermally gen-
erated stresses between the materials. However, when the two bonded materials cool to
room temperature, enormous lateral stresses are generated, since the SiO2 moves little
while the Al strains to contract. A related problem is when Al reacts with a metal such as
Ti. If both materials are passivated before the reaction, then the formation of TiAl3 occurs
with an approximate volume reduction of 5%. This is another high-stress-generating
mechanism. We will calculate the stresses on Al for an unpassivated and a passivated met-
al line, developing simple equations that predict the stresses and strains in modern IC
metals. We will then use numerical examples to show these enormous values, and con-
clude with methods to reduce the probability of stress void occurrence.
We begin with a simple example of metal stress forces, using a metal rod suspended in
air and pulled at its ends. Figure 6.20(a) shows a metal rod with an applied force F, an
area A, and a stress ␴ = F/A. When F is applied, the rod has a uniform stress along its axi-
al length, and stretches a small amount, ⌬L. The amount of stretching is called strain ␧,
and its measurement is normalized with respect to its original unstressed length L, or ␧ =
⌬L/L [Figure 6.20(b)]. When metal is pulled in air, lengthening corresponds to a decrease
in the diameter or circumference of the metal. The length increase is compensated for by a
diameter reduction in the lateral walls, so that the volume remains constant. The surface
atoms have no restraining force to prevent them from moving inward. Accurate strain
measurements take this area change into account.
Figure 6.20(b) shows a generic stress–strain curve. Material in the linear region can be
stretched to a point that upon release of the force returns the material to its original length.
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σ = F/A Final Fracture

F
F (MPa )
Yield Strength
LL ∆L L
ε = ⌬L/L
(a) (b)
Figure 6.20. (a) Measurement setup for stress and strain. (b) Stress (␴) versus strain (␧) curve.
Atoms in this region are acting in accordance with the atomic spring model. The slope of
this straight line is called Young’s modulus, Ym. Ym characterizes a material’s resistance to
an applied force, and also allows calculations of strain given the stress (or vice versa).
Stress is related to strain by a simple but important relation:
␴ = Ym␧ (6.16)
The stress point at which the material enters the nonlinear or plastic deformation region is
called the yield strength of the material. Metal stretched beyond the yield strength will not
return to its original length. It has undergone plastic deformation, after which atoms no
longer act as springs, but slide past each other. Finally, the material ruptures. The pressure
unit is Pascals (Pa) (Newtons per meter2), where 1 MPa ⬇ 146 lb/in2. Al alloys have a
yield strength of about 95 MPa (about 14,000 psi) and a Young´s modulus of about 71.5
GPa.
Temperature and length are typically linear, and related by the thermal coefficient of
expansion (TCE) where
⌬L/L ␧
␣= ᎏ = ᎏ (6.17)
⌬T ⌬T
Stress, strain, and temperature are combined from these equations to give
␴ = Ym␧ = Ym␣⌬T (6.18)
Equation (6.18) is an important link between stress, temperature, and the material con-
stants Ym and ␣. An example will show how to estimate the stress forces on an unpassivat-
ed Al line.
왎 EXAMPLE 6.3
Given an unpassivated Al line surrounded by air [except at the ends, where

forces are applied (Figure 6.21)]. Let the length at 430°C be L + ⌬L, and the
length at 30°C be L. When the metal shrinks as temperature drops from T =
430°C to 30°C, what stress is required to hold the ends at the T = 430°C dimen-
sion (L + ⌬L). Assume ␣Al = 23.6 × 10–6/°C and Ym = 71.5 GPa.
c06.qxd 2/2/2004 12:31 PM Page 172
F L
Figure 6.21. Unpassivated Al line.
The fractional change in the Al line is equal to the strain ␧, where
⌬L
␧ = ᎏ = ␣⌬T = 23.6 10–6 × (430 – 30) = 0.00944
L
Since Ym = 71.5 GPa and
␴
Ym = ᎏ
␧
then
␴ = ␧ Ym = 0.00944 × 71.5 GPa = 675 MPa

왎
This 675 MPa stress greatly exceeds the yield and fracture strength of Al, therefore the
TCE forces would tear the Al line apart. Most Al metal interconnections do not pull apart,
so what protects the thin metal lines? The answer lies in the unique properties that passi-
vation brings to these material systems. Surprisingly, even higher stress forces are gener-
ated in passivated metals than for the case of Al in air.
Self-Exercise 6.4
Assume a 100 ␮m long unpassivated Al metal line (Figure 6.22) with width of 1
␮m, height of 0.4 ␮m, and yield strength of 95 MPa.
(a) How many pounds of force F are required to cause the metal to enter the
plastic deformation region? How many kg?
(b) How far can you pull the 100 ␮m line before it goes into plastic deforma-
tion?
We next look at the more relevant situation in which the metal is bound and con-
strained by a dielectric. We are indebted to Bill Filter of Sandia National Labs for his
stress void lectures at the University of New Mexico, giving his insights and examples of
stress void calculations. Unpassivated metal atoms on the surface of the line do not have a
bond to another atom on the surface plane, since there is only air at the surface. As the
metal line is pulled at the ends, all atoms feel a tension, but the surface atoms, having no
c06.qxd 2/2/2004 12:31 PM Page 173
1 µm
100 µm
0.4 µm
F
Figure 6.22. Al line.
restraint at the surface plane, tend to move inward, reducing the section of the metal line.
The inward displacement provides some stress relief, but the stress remains high.
When a metal line is passivated, its surface atoms bond strongly to the fairly rigid pas-
sivation material and, basically, these metal atoms cannot move, even under very large
stresses. The stresses are larger when a metal is passivated, and unless there are defects
present in the metal, it maintains its shape. A key issue is that the surface atoms that could
move inward under tensile stress now remain in position, and a stress exists at the surface
of the metal that is orthogonal to the stress applied at the ends of the line. The stress equa-
tion is modified from that of Figure 6.20 to reflect this increase, using a parameter called
Poisson’s ratio. Equation (6.19) shows this modification for passivated metal stress [18]:
Ym␧
␴= ᎏ (6.19)
1 – 2v
where v is called Poisson’s ratio; v = 0.35 for aluminum. When two materials are bonded,
the thermally induced strain must consider the differences in their TCE, so that using
Equations (6.16)–(6.18),
⌬L2 – ⌬L1 L␣2⌬T – L␣11⌬T

␧ = ᎏᎏ = ᎏᎏ = ⌬␣ ⌬T (6.20)
L2 L
where L1 = L2 = L for constrained metal. When we substitute Equation (6.19) into Equa-
tion (6.20) we get
⌬␣⌬TYm
␴= ᎏ (6.21)
1 – 2v
A simplified example shows the even larger stress calculation for a passivated metal.
왎 EXAMPLE 6.5
Given a passivated Al line [Figure 6.23)], if ␣Al = 23.5 × 10–6/°C, ␣SiO2 = 0.5 ×
10–6/°C, v = 0.35, and Ym = 71.5 GPa, calculate the stress on the Al at its ends af-
ter the material drops from 430°C to 30°C. In other words, what is the required
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TiN
⌬L
2
Al ⌬L
2
TiN
Figure 6.23. Passivated Al.
stress on the ends needed to maintain the longitudinal dimension when the metal
and passivation material cool to 30 °C?
The fractional change in the Al line is equal to the strain ␧, where
␧ = ⌬␣ ⌬T = (23.6 × 10–6 – 0.5 × 10–6)(430 – 30) = 0.00924
Since
␧Ym
␴= ᎏ
1 – 2v
then
(0.00924)(71.5 Gpa)
␴ = ᎏᎏᎏ = 2,202 MPa
1 – 2 × 0.35
왎
The stresses in this calculations are enormous, far exceeding the Al yield and fracture
strengths. Again, why doesn’t Al instantly pull apart? The answer lies in the ability of the
passivation molecules to bond to the metal atoms. They can withstand stresses of GPa’s,
whereas Al–Al bonds permanently deform at less than a hundred MPa. Al is a soft metal.
How does this impact an integrated circuit? Stresses of hundreds of MPa have been
measured in passivated Al lines. The everyday ICs that we use, such as wristwatch ICs,
and those in personal computers, pocket calculators, etc., are subject to these large stress-
es throughout their product life. What is the concern? It is the threat of stress voiding, and
that is final subject of this section.
How do stress voids appear in this high-stress environment? Voids in the metal do not
just appear spontaneously. Voids form only in a stress gradient. Equation (6.22) is the flux
equation for materials under a stress gradient:
D d␴
J␴ = ᎏ ⍀ ᎏ N (6.22)
kT dx
Net atomic displacement at room or operational temperature can only happen if d␴/dx is
not zero. If the whole material has an equal stress of 2.2 MPa, then net atomic displace-
c06.qxd 2/2/2004 12:32 PM Page 175
ment does not happen. Metals and their passivation material can lie in these large stresses,
and nothing much happens unless a gradient occurs. That is what causes stress voids.
A void requires an imperfection in the metal, such as a small nucleation at the
metal–passivation material boundary. The surface of the metal atoms of a void nucleus
have zero stress, so that a large stress gradient forms in the metal. The metal atoms now
want to move and relieve the stress gradient. The last condition for destructive stress void
growth is a diffusion path and sufficient temperature for these metal atoms to move. A
neighboring grain boundary unfortunately satisfies this condition. In summary, there are
three conditions for a stress void to occur:
1. A large stress must be present in the metal.

2. A defect must be present to convert the stress to a stress gradient.
3. A diffusion path and sufficient temperature must be present that allow the void to
grow.
The flux J␴ in Equation (6.22) is proportional to the stress gradient, but atomic travel is
still controlled by the diffusivity of the metal. These two factors combine to give an inter-
esting temperature dependence to stress void sensitivity. Figure 6.24 shows a family of ac-
celeration factor curves relative to room temperature as a function of processing tempera-
ture. The top curve has a deposition temperature of 435°C and the bottom curve of 300°C.
Each curve has a peak with zero acceleration factors at high temperatures and near zero at
low temperatures. At high temperatures, the TCE-induced stress differences are small, so
little net metal atomic motion occurs, even though diffusivity is large. At low ambient
temperatures, the TCE-induced stress is very large, but diffusivity is small, and, again, lit-
tle net motion of the metal occurs. A peak occurs at which diffusivity and stress gradients
140
120
435
100
Acceleration factor
400
80
375
60
350
40
300
20
0
0 50 100 150 200 250 300 350 400 450
Temperature of Passivation (oC)
Figure 6.24. Stress void sensitivity versus test or ambient temperature. (Reproduced by permission
of Bill Filter, Sandia National Labs.)
c06.qxd 2/2/2004 12:32 PM Page 176
combine for maximum effect. The peak sensitivity shifts at lower process temperature,
and the magnitude of the peak sensitivity is lower. A warning from Figure 6.24 is that
modern high-performance ICs have die temperatures above 100°C.
Stress Voiding and Electromigration Comparisons. Electromigration and stress

voiding have distinctions that are important when seeking the root cause of a failure
(Table 6.2). Electromigration requires circuit operation that provides the necessary cur-
rent density and elevated temperature, and it worsens with temperature. Stress voiding
needs only a moderate temperature; it has a temperature peak in sensitivity, and it requires
no power. When small stress voids nucleate during the cool-down or quenching process,
then lines become more sensitive to electromigration during circuit operation. The small
stress voids finitely reduce the metal area, thus increasing je.
6.3.3 Copper Interconnect Reliability

Cu appeared in 1998 as a substitute for Al in some high-performance ICs. Cu resistivity is
about 1.9 ␮⍀ · cm compared to Al–Cu alloy resistivity of about 3 ␮⍀ · cm. This is about a
37% reduction in interconnect resistivity and RC time constant. Cu has interesting proper-
ties besides resistivity. Its melting point is 1358 K, considerably higher than Al at 933 K.
This means that Cu has stronger bonds than Al, and should be more resistant to atomic
motion by electromigration or stress voiding. Lee et al. reported a Cu Young’s modulus of
110 GPa compared to 70 GPa for Al [10]. They also reported a Blech threshold of 3700
A/cm for passivated Cu lines.
It was originally thought that Cu would never electromigrate or have stress void fail-
ures, but that is not the case. Cu electromigration activation energies can show Ea ⬇ 0.8
eV, about the same as bamboo Al. Why the similarity if Cu–Cu bonds are stronger? Metal
Table 6.2. Comparison of Electromigration and Stress Voiding Failure Mechanisms

Property Electromigration Failure Stress Voiding Failure
Powered On Necessary Not necessary
Defect Class Bridges and opens Only opens
Ambient Temperature Gets exponentially worse as Has a temperature peak sensitivity
temperature rises to failure
Passivation Strength Blech Length gets longer as TCE-induced stress gets worse as
passivation hardness increases, hardness increases; thus, more
making metal more durable vulnerable to failure
Initial Event Displaced atoms cause tension Stress gradient appears due to
and compression regions; void nucleation before metal
stress gradient formed from atoms are displaced
displaced atoms
Atomic Displacement Diffusion Diffusion
Mechanism
Final Failure Mode Displaced atoms cause voiding Displaced atoms cause voiding
(opens) and compression
(bridging)
c06.qxd 2/2/2004 12:32 PM Page 177
migration in Al bamboo structures primarily takes place at the Al2O3–passivation inter-

face. Cu electromigration also takes place at the Cu–passivation interface, and Cu granu-
larity is higher than Al. Al bonds much tighter to the passivation than does Cu, so that Cu
migration at its interface is larger. Improvements in Cu processing have raised its mea-
sured activation energies.
The Cu advantage in RC time constant can be taken from the R or C. For example, if a
Cu and Al metal line have the same geometry, then the Cu line resistance is about 37%
lower than the Al with the C unchanged. However, if the height of the Cu metal line is re-
duced, then its resistance increases, but its sidewall capacitance drops. The load CL and
crosstalk capacitance are smaller for Cu, and the IC power dissipation drops, as we saw in
Chapter 4:
2
P = CLV DD fclk (6.23)
Cu has a unique reliability risk not found in Al and that is the high diffusivity of Cu in
SiO2 and Si. Cu lines must be bound with a thin (⬇ 150 Å) barrier metal liner such as
TaN. Cu can ruin transistor pn junctions if it is not contained. TaN liners bind three sur-
faces of the Cu line: the bottom and the two sides. A partial containment solution uses W
(tungsten) at the first metal layer that connects drain, source, and gate contacts. This fur-
ther separates Cu from the transistor pn junctions. Although W resistivity is higher, the
signal lines are kept short so that IC performance is not compromised.
A Cu process uses the dual-damascene process, which is quite different from the Al
metal sputtering process. The metal regions are first etched as trenches in the dielectric.
Then a thin barrier metal layer is deposited on the bottom and two sidewalls of the
trench. Next, a thin Cu seed layer is deposited in the trenches using PVD or CVP tech-
niques followed by a Cu electroplating that fills the trenches and upper dielectric sur-
face. The surface is then polished flat using the chemical mechanical planarizing (CMP)
technique. This removes the excess Cu on the top surface, leaving Cu interconnects in
the trenches.
The quality of the Cu interconnects depend critically on the properties of the seed lay-
er. A rough Cu seed layer promotes small grain sizes, and this degrades the ability of Cu
to resist EM fluxes. The dual-damascene process is more complex, with its required barri-
er protection metal liner as an essential part of Cu interconnect integrity. Cu is also a
strong contaminant of the ICs in a fabrication facility if it spreads to the equipment in the
lab. Originally, Cu was thought to be a perfect metal, without electromigration or stress
void reliability risk. However, studies show otherwise [8, 10, 13, 15].
Song et al. noted that Cu is a noble metal that is less reactive than Al [15]. This may
seem to be an advantage, but Cu forms weaker bonds with the surrounding dielectric than
Al. Therefore, we see higher EM fluxes occurring at the Cu-to-dielectric interface, and
even see lateral (intrametal layer) breakdown leakage paths.
The high via aspect ratios make liner dimension and liner continuity integrity challeng-
ing for the billions of vias that may populate an IC. The total metal length of a modern IC
is on the order of several kilometers. The initial via etch through the dielectric must be
taken just to the level of the bottom metal and no more. A shallow etch will leave a thin
layer of dielectric in the serial path of the via. A 90 nm technology can use minimum vias
on the order of 90 nm in diameter, subject to via–metal interconnect line design rules. The
via fabrication challenges translate to lower IC yield, more test escapes, and increased re-
liability concerns.
c06.qxd 2/2/2004 12:32 PM Page 178
Many via electromigration failures occur at the bottom of the vias, where the liner in-
tersects and interrupts the Cu via path [8]. The subsequent Cu flux divergence identifies
an electromigration weak spot. This site is similar to the electromigration voiding found
under a tungsten via in Al systems. Also, an initial defect-induced voiding in the Cu could
electromigrate to a complete open in the via. This forces the via current to pass through
the parallel path of the liner. Although this offers protection, failure analysis showed that
about 20% total via voiding could lead to excessive heat in the high-resistive liner, and
even lead to a thermal opening of the liner itself.
The evolution of Cu interconnects to low-k dielectrics will impact Cu reliability. Lee et
al. studied Cu with the low-k dielectric SiLK™ and found that t50 values were 3 to 5 times
lower for Cu–SiLK™ than for Cu–oxide materials [10].
Doong et al. reported design rules for stress-induced voiding (SIV) in a 130 nm
Cu–damascene technology [19]. The interconnect variables were width of the metal lead,
via location in a wide metal lead, and width of the other connecting metal. They found that
SIV was more severe on a via fed by a wide metal line than on one fed by a narrow line.
Design rules are a key ingredient to preventing stress voiding in an IC.
6.4 OXIDE FAILURE MODES
Transistor gate oxides made of SiO2 (silicon dioxide) are the beating hearts of a MOS
transistor. Gate control of channel charge depends on the dimensions and quality of this
oxide. Although SiO2 appears in different parts of an IC, this section specifically uses the
word oxide to refer to the thin dielectric material that separates the transistor gate from the
channel substrate. Financial penalties for poor quality oxides are longer time to market
and customer dissatisfaction. Oxide thickness in the 1970s was about 750 Å, and now ox-
ide dimensions are below 20 Å. Gate oxide electric fields at the turn of this century were
higher than burn-in field strengths in the early 1990s. Test, field failure, and burn-in are
just three examples of why we must understand the chemical and electronic nature of ox-
ides. We will look at the chemical structures of the thin oxide and then two oxide failure
mechanisms: wearout and hot carrier injection. We will close with a description of a rela-
tively recent pMOS transistor oxide reliability concern called negative bias temperature
instability (NBTI).
Figure 6.25 is a remarkable TEM (transmission electron microscope) photograph of a
MOS capacitor structure, showing the atoms of the single-crystal Si material, the non-
crystalline or amorphous SiO2 thin oxide molecules, and the polysilicon gate material
above [24]. Imperfections cannot be avoided when the amorphous SiO2 surface abuts the
Si crystal. The interface is the site of numerous dangling bonds in which Si atoms or SiO2
molecules have unshared bonds, leading to charges that are readily filled if an electron,
hole, or hydrogen atom (H+) is near. Process steps use or generate hydrogen and water that
can bond with the unfulfilled states at the interface. The transistor threshold Vt is altered
by these charge exchanges, with an important impact on speed.
Figure 6.26 shows the molecular orientation of SiO2 molecules. A Si atom (open cir-
cle) appears to bond to four O atoms (shaded circles), but since each O atom also bonds to
another Si atom, the chemical ratio is one Si to two O atoms, or SiO2. McPherson and
Mogul described the oxide structure in which each SiO2 tetrahedron molecule forms rigid
109° angle bonds between Si and O [41]. Significantly the bonding between tetrahedrons
is not rigid, but bond angles form from about 120° to 180°, with a mean of about 150°.
c06.qxd 2/2/2004 12:32 PM Page 179
6.4 OXIDE FAILURE MODES 179
Polycrystalline
Polycrystolline
Silicon
27Å oxide
100 Silicon
Substrate
3 13 Å
Figure 6.25. MOS capacitor cross section. (Reproduced by permission of Doug Buchannan, IBM
Corporation.)
The bond angle weakens as the angle deviates from the mean. The variable bond strength
is one source of the statistical behavior of oxide wearout and breakdown. Another weak
bond occurs when an O atom is absent, allowing two Si atoms to bond to each other (Fig-
ure 6.26). These weaker (strained) bonds are more susceptible to rupture, leaving sites for
holes, electrons, or atoms such as hydrogen to attach to.
The dangling bonds, the variable bond strength of SiO2–SiO2 molecular angles, and
the absence of O atoms in the normal pairing leads to defects in the oxide called traps. A
trap is an oxide defect, and the electronic charge on that trap is called a state. Traps can
Figure 6.26. Si and O bond geometry in SiO2 [41].

c06.qxd 2/2/2004 12:32 PM Page 180
exist after the processing steps, or can be created when bonds are broken by energetic par-
ticles such as electrons, holes, or radiation.
Traps lying at the Si–SiO2 border are called interface traps. Interface traps can rapidly
exchange charge with channel carriers, since they are in close proximity to the channel. A
trap 25 Å into the oxide will exchange channel charge in about one second. The oxide
depth of the trap from the interface determines the exchange rate with the channel. Each
trap that is 2.5 Å deeper in the oxide increases charge tunneling time by about one decade
[30]. Border traps are those that lie deeper than interface traps, but less than 50 Å deep.
Fixed oxide traps lie deeper than 50 Å and, basically, do not exchange charge with the
channel. Most oxide dimensions are now less than 50 Å, so that these deep traps are less
relevant to modern failure mechanisms. Charge exchange between the channel carriers
and the oxide traps has a negative influence on transistor performance. The next section
builds on these physical descriptions, describing oxide wearout and subsequent rupture.
6.4.1 Oxide Wearout

Good oxides wear out and rupture if a charge is continuously injected. This has nothing to
do with defects from the fabrication, and the actual failure mechanism has eluded good
people doing expensive experiments for many years. Each time a logic circuit has a volt-
age put across its gate oxide, a small amount of charge is injected into the oxide. The
question is how long will it take for a normally operating transistor to wear out and rup-
ture. That time must exceed expected product lifetime, since miscalculation could have
severe consequences if premature oxide wearout caused ICs to fail during product life.
Oxide wearout time decreases as oxide stress increases, and a concern is that the voltages
and electric fields of thin oxides will cause premature oxide wearout. Oxide field strength
is the force that accelerates electrons across the oxide. The example below illustrates the
rising oxide field occurring for deep-submicron transistors in their use condition. The val-
ues are typical for the succession of technologies since the late 1980s.
왎 EXAMPLE 6.6.
Calculate the oxide field strengths in V/cm for the following technologies: (1) 5
V and Tox = 300 Å, (2) 5 V and Tox = 200 Å, (3) 3.3 V and Tox = 100 Å, (4) 2.8 V
and Tox = 60 Å, (5) 2.5 V and Tox = 40 Å, and (6) 1.2 V and Tox = 20 Å.
1 Å = 108 cm, so:
1. Ᏹox = 5 V/300 × 10–8 cm= 1.7 MV/cm

2. Ᏹox = 5 V/200 × 10–8 cm = 2.5 MV/cm
3. Ᏹox = 3.3 V/100 × 10–8 cm = 3.3 MV/cm
4. Ᏹox = 2.8 V/60 × 10–8 cm = 4.7 MV/cm
5. Ᏹox = 2.2 V/40 × 10–8 cm = 5.5 MV/cm
6. Ᏹox = 1.2 V/20 × 10–8 cm = 6 MV/cm
왎
Significant tunneling of electrons through the gate oxide can occur when the oxide
thickness becomes less than about 40 Å. As Tox goes to 20 Å and 15 Å, the tunneling cur-
rent is worse. These increased gate currents are reliability and power concerns in modern
ICs.
c06.qxd 2/2/2004 12:32 PM Page 181
Most of the research on oxide reliability has used MOS capacitor structures. Some ear-
ly work on transistor gate oxide shorts showed that the gate capacitance could store suffi-
cient energy (½ CV2) so that when a breakdown rupture occurred, this energy was re-
leased into the small, weakened oxide site, causing severe local damage. The silicon on
either side of the oxide became temporally molten and joined; i.e., the polysilicon gate
material physically bonded to the silicon substrate. An n-doped polysilicon gate joined
with the p-well (nMOSFET) or n-well (pMOSFET) to form parasitic diodes or resistors.
As transistors were scaled to modern technologies, power supply voltages dropped from
5–10 V to 1.0–1.2 V. Gate dimensions scaled from channel lengths of 1–5 ␮m to 90–130
nm. The gate area scaled by (0.7)2 for each technology node so that gate capacitance
scaled on the order of 27 as we went from 1.0 ␮m to 130 nm technologies. This dropped
the gate capacitance by a factor of over 100 and V 2DD by about 20–25. The stored gate ca-
pacitance then became sufficiently small so that the violent thermal ruptures were re-
placed with the more gradual and subtle breakdowns that are described next.
What causes oxide wearout? The answer lies in which technology we work with. The
older-technology oxides greater than 40 Å thick have a breakdown model quite different
than the oxides we now build (below 30 Å). Oxides less than 30 Å thick are known as the
ultrathins. Ultrathin oxide breakdown shows a distinct soft breakdown. Soft breakdown
results in an irreversible damage to the oxide. Its most significant effect is an increase in
noise of the gate voltage or current. Figure 6.27(a) shows this breakdown for oxide thick-
nesses from 2.4 nm to 5.5 nm [52]. The oxides were stressed with a constant current and
the 5.5 nm oxide shows a precipitous drop in gate voltage at 75 s when a stressing gate
current is applied. The 2.4 nm gate oxide did not change gate voltage with the oxide dam-
age event, but shows an increase in noise.
The noise plotted in Figure 6.27(b) shows a four orders of magnitude increase after
soft breakdown. Noise increase is the only certain evidence of the irreversible damage to
ultrathin oxides. The noise associated with soft breakdown is thought to be trap-assisted
conduction through a small conducting path in the oxide. The electrons hop noisily from
trap to trap. In contrast, hard breakdowns in the thick oxides of older technologies showed
severe gate voltage or current changes (Figure 6.27(a)). A hard breakdown was defined as
a thermal event that merged the material above and below the oxide. The physical touch-
(a) (b)
Figure 6.27. (a) Oxide breakdown with stress time. (b) 1/f noise before and after breakdown [52].
c06.qxd 2/2/2004 12:32 PM Page 182
ing of two differently doped materials can create diodes, or resistors if the doping is of op-
posite polarity.
The normal functioning of a transistor with an ultrathin oxide is not as effected as
those with thicker oxides following rupture [49]. The ultrathin wearout and breakdown
model shows that rupture is primarily related to the gate voltage VG and the amount of
charge driven through the oxide (fluence). Evidence for the voltage model is shown in
Figure 6.28, which plots the log of time to breakdown (TBD) versus VG. The interpretation
is that electrons tunnel through the gate oxide, accelerating in the oxide field. The oxide
electric field is constant across the oxide, but the internal oxide voltage drops as the elec-
tron reaches the anode of the structure. The relation of oxide rupture to gate voltage im-
plies that the electron travels through the oxide without interaction, achieving a maximum
kinetic energy before striking the anode, where it causes bond breakage. The likely weak
bonds are H–Si and H–O. One subsequent damage mechanism is believed to be release of
a hydrogen ion that reenters the oxide, causing trap damage. This is the anode hydrogen
release model (AHR). The other damage mechanism is thought to be creation of a hole
that migrates back into the oxide. This is the anode hole injection model (AHI). H+ and a
hole feel the attractive pull of the oxide electric field, causing trap damage as they enter
and interact with the oxide molecules. There is evidence that both AHI and AHR con-
tribute to wearout and breakdown [37].
Oxides do not breakdown after a single hole or electron are reinjected into the oxide.
Oxides have a wearout and a breakdown phase. The wearout is believed to be the continu-
ous addition of damage sites (traps) distributed throughout the oxide. When a statistical
distribution of these traps is critically aligned in a vertical path supporting an increase in
conduction, then a thermally damaging current goes through the oxide. This model is
known as the percolation model of wearout and breakdown [28]. Figure 6.29 sketches
such a statistical distribution of traps. The path in the middle of the figure indicates a trap
distribution that is sufficiently close to form a breakdown percolation path.
Ultrathin breakdown has been characterized into three stages:
1. Slow defect generation within the oxide (wearout) until a defect path links the gate
terminal to the substrate (percolation model)
105
104
High Poly Doping

(s)
103
TBD
Low Poly Doping

102
101
4.0 4.2 4.4 4.6 4.8 5.0

Gate Voltage (V)
Figure 6.28. TBD as function of VG [37].

c06.qxd 2/2/2004 12:32 PM Page 183
Figure 6.29. Percolation model of wearout and breakdown [28].
2. A soft breakdown (SBD) at low voltages that permanently increases gate current (<
100 nA at 1.2 V in 150 Å oxide) and gate noise
3. The appearance of a “hard breakdown” (HBD), showing continuous exponential in-
crease in IG.
There is evidence that SBD and HBD may be independent events [40, 44].
An ultrathin-oxide, voltage-dependent time-to-breakdown model (Tbd) has been pro-
posed [43]. This breakdown model [Equation (6.24)] includes the gate oxide thickness
(Tox) and the gate voltage (VG):
Ea
Tbd = T0 · e 冢冣
␥ ␣·T ox + ᎏ – VG
kTj (6.24)
where ␥ is the acceleration factor, Ea is the activation energy, ␣ is the oxide thickness ac-
celeration factor, T0 is a constant for a given technology, and Tj is the average junction tem-
perature. Time-to-breakdown physical parameter values were extracted from experiments
as follows: (␥ · ␣) = 2.0 1/Å, ␥ = 12.5 1/V, and (␥ · Ea) = 575 meV [43]. The voltage model
and its supporting data suggest that ultrathin oxide rupture will be a greater concern with
the increased electron tunneling (fluence) of thin oxides. VGB decreases with each shrink-
ing technology, but it is still high enough to support electron tunneling and subsequent reen-
try of high-energy particles into the oxides. However, recent data suggest that the soft rup-
tures of ultrathin oxides may not pose as serious a reliability threat to actual transistors.
There is general agreement on the ultrathin voltage-driven wearout model and the per-
colation theory of breakdown, but there is need for ultrathin technology data relating
wearout and breakdown to logic circuit failure, not just to oxide capacitors. The ultrathin
oxide experiments indicate that reliabilities may not be as risky as for breakdown in older
technologies, but we must take care with these conclusions from wearout studies since
they are predominantly done on capacitor oxides and to a lesser extent on transistors hav-
ing drain, channel, and source regions. The studies reported on the effect of transistor ox-
ide rupture on circuit functionality are now reviewed.
The evolution of ultrathin oxide studies from MOS capacitors to MOSFET transistors
shows distinct characteristics. A rupture of the older technology gate oxide shorts may or
may not cause logic failure in the IC [32, 33, 49]. However, the effect of ultrathin oxide
soft breakdown on transistor Vt and gm was reported as negligible [52]. Figure 6.30 shows
the small time-varying changes in Vt and gm during the pre-soft-breakdown stress and af-
terward—Vt dropped by 1.3% and gm increased by 3.1%.
Crupi et al. [27] stressed 24 Å thin oxide transistors, and found breakdown in the over-
whelming majority of nMOSFET devices. IDoff was significantly increased, and the |VG/IG|
ratio showed hard breakdown values in the range from about 1 k⍀ to 100 k⍀. High IDoff
c06.qxd 2/2/2004 12:32 PM Page 184
Figure 6.30. Time-varying change in Vt and gm of an ultrathin oxide during current stress [52].
drain currents from about 1 ␮A to 1 mA occurred only for breakdown in the in the gate-
to-drain region. Soft breakdown with much lower IDoff occurred dominantly in the gate-to-
source and gate-to-channel regions of the transistor. Hard breakdowns were not found for
any of the three regions in the p-channel MOSFETs. The implication is that only the gate-
to-drain breakdowns of nMOSFETs are serious reliability threats. Although the experi-
ment clearly shows a sensitivity of the n-MOSFET, it should be noted that the oxides were
protected from harder breakdown by a 1 k⍀ series resistor in the gate electrical path. A
normal logic IC may show more variation in breakdown hardness from soft to hard cate-
gories. Also, the implications for a logic circuit with damaged transistors, such as a
NAND gate, were not shown.
Rodriguez et al. measured the effect of ultrathin gate oxide breakdowns on inverter
properties [48]. Inverter transfer curves showed weakened logic voltages and, finally,
functional failure for inverters that underwent a stronger stress. The weak logic voltage
compromises noise margins, and could also cause IDDQ elevation if the weak voltage out-
put is sufficient to turn on downstream load gates. HBD can significantly load a previous
logic gate stage to the point of logic failure or severe weakening of noise margin.
Dumin et al. showed an interesting result that the stress on an nMOS transistor oxide is
greater if VG = 0 V and VD = VDD [29]. An inverter in the high-output-logic state would
show this stress. This contrasts with traditional thinking, which assumed that the gate volt-
age was set at VDD and source and drain terminals were at ground potential.
E versus E–1 Models for Oxide Breakdown. The research community debated for
several years two oxide breakdown models that pertain to oxides of Tox > 40 Å [51]. These
c06.qxd 2/2/2004 12:32 PM Page 185
are the E-model and the E–1 (or 1/E) model. The E- and E–1 models are increasingly less
relevant with ultrathin technology use, but these models consumed large research re-
sources, and they taught us a great deal about oxide properties. The E-model is thermody-
namic, and one interpretation is that the initial event is field emission of an electron in the
oxide. When field strength is high enough, an electron can be pulled from an atom in the
material. This field emission causes a trap, and when a sufficient number of traps are ver-
tically lined up, the oxide field strength exceeds that needed to rupture it. The E–1 model
assumes an initial preferential tunneling of charge into a spot that has local thinning with
respect to neighboring regions. A trap occurs at the thinner spot, resulting in a higher ox-
ide field strength and leading to more tunneling and damage. The damage increases the
oxide field in the region of traps until rupture occurs. The difficulty in distinguishing be-
tween the two models is that test data must be taken at abnormally high field strengths to
accelerate the failures in a reasonable time. Wearout and breakdown data would take
months or years to collect at normal use field strengths. The data on high oxide field
stress (> 8 MV/cm) overlay almost exactly for the E- and E–1 models, and that was the
problem.
Figure 6.31 compares time to breakdown, tBD, found when plotting the data with the E-
model or E–1 model. Although tBD predictions are virtually identical in the high field re-
gion, a wide discrepancy is seen for projections of data to user conditions between 2–5
MV/cm. Experiments done at lower field strengths and elevated temperatures show that
high-temperature breakdowns occurred with the same mechanism as those at lower tem-
peratures. Suehle and colleagues then used this observation to fit tBD data to the E-model
over a broad range, including the user region [50].
6.4.2 Hot Carrier Injection (HCI)

This second major oxide failure mechanism occurs when the transistor electric field at the
drain-to-channel depletion region is too high. This leads to the hot carrier injection (HCI)
1e+22
1e+20
1e+18
tBD 1e+16
(s) 1e+14
1e+12
(A)
1e+10
1e+8
1e+6
(B)
1e+4
1e+2
1e+0
1e-2
0 2 4 6 8 10 12 14 16
Field (MV/cm)
Figure 6.31. Time to breakdown tBD for E–1 model plot (A) and E model plot (B) using extrapola-
tion of data from high-oxide fields (8–10 MV/cm) [51].
c06.qxd 2/2/2004 12:32 PM Page 186
effects that can alter circuit timing and high-frequency performance. HCI is a systematic
failure resulting in a decline in the maximum operating frequency (Fmax) of the IC. It sel-
dom leads to catastrophic failure. The typical parameters affected are: IDsat, transistor
transconductance (gm), threshold voltage (Vt), weak inversion subthreshold slope (S), and
increased gate-induced drain leakage (GIDL).
HCI can happen if the power supply voltage is higher than intended for the design, the
effective channel lengths are too short, there is a poor oxide interface or poorly designed
drain–substrate junctions, or overvoltage accidentally occurs on the power rail. Figure
6.32 sketches an nMOS transistor cross section showing the drain depletion field. The
horizontal electric field in the channel Ᏹch gives kinetic energy to the free electrons mov-
ing from the inverted portion of the channel to the drain. When the kinetic energy is high
enough, electrons strike Si atoms around the drain–substrate interface causing impact ion-
ization. Electron–hole pairs are produced in the drain region and scattered. Some carriers
go into the substrate, causing an increase in substrate current ISUB, and a small fraction
have enough energy to cross the oxide barrier and cause damage. It is estimated that an
electron needs at least 3.1 eV to cross the barrier and a hole needs 4.6 eV. Even more en-
ergy is needed to break bonds leading to trap formation. Typically, damage is creation of
acceptor-type interface traps near the drain by electrons with energies of 3.7 eV or higher.
A possible mechanism is that a hot electron breaks a hydrogen–silicon bond at the
Si–SiO2 interface. If the silicon and hydrogen recombine, then no interface trap is created.
If the hydrogen diffuses away, then an interface trap is created [42].
The energy follows a Boltzmann distribution in which particle thermal energy is Et =
kT/q where k is Boltzmann’s constant, T is degrees Kelvin, and q is the electron charge.
An electron of 3.1 eV then has an equivalent mean temperature of T = Et/k = 3.1
eV/(86.17 ␮eV/K) = 36,000 K. This is the basis for the expression “hot electrons.” Ambi-
ent temperature has an interesting relation to HCI since carrier mobility increases as tem-
perature decreases. Carriers with higher mobility more efficiently create hot holes and
electrons, so that HCI increases as temperature is lowered. This property is sometimes
used when using HCI reliability test structures to rapidly show damage.
Once a hot carrier enters the oxide, the vertical oxide field Ᏹox determines how deeply
the charge will go. If the drain voltage is positive with respect to the gate voltage, then
holes entering the oxide near the drain are accelerated deeper into the oxide, and electrons
in the same region will be retarded from leaving the oxide interface. Ᏹch restricts the dam-
age to oxide over the drain–substrate depletion region, with only a small amount of dam-
Polysilicon Gate
Vs VD
Ᏹox
Ᏹch
Charge Charge
Inversion Depletion
VB
Figure 6.32. Saturated-state nMOS transistor and its internal electric fields Ᏹch and Ᏹox.
c06.qxd 2/2/2004 12:32 PM Page 187
age just outside the depletion region. In practice, the IDsat parameter is typically used to
measure HCI degradation. IDsat is the transistor parameter that most closely approximates
the impact on circuit speed, since it impacts the charge and discharge of load capacitors.
Also, the MOSFET current model equations in Chapter 3 showed that IDsat is a function of
Vt. The increased trap density and subsequent charging of the traps alters transistor thresh-
old voltage Vt. Typically, nMOS transistors show increased Vtn causing the transistor to
slow, and decreased Ioff and gm. pMOS transistors typically show the opposite effect: |Vtp|
decreases, Ioff and gm increase, and the transistors switch faster.
Figure 6.33 shows time degradation for a nMOS transistor under a hot-carrier stress.
The important circuit speed parameter is the IDsat parameter that shows only slight degra-
dation in time. This is the parameter that largely controls the oscillation frequency of a cir-
cuit such as a ring oscillator or a microprocessor. Vtn also changes slightly in time. Other
parameters change more readily such as the gm, IDsat reverse, and IDsat forward. The for-
ward and reverse designations refer to normal bias of the drain and source (forward), and
reversing the normal bias of the drain and source (reverse). The point is that whereas some
transistor parameters change markedly, IDsat is the overall speed determining parameter,
and it changes slowly.
Figure 6.34 shows ID = Ioff (off-state leakage current) versus gate voltage for a pMOS
transistor subjected to a drain-to-source overvoltage. This nominal 2.8 V transistor had
VDS = –4.5 V during the time of the measurements. After 1 minute of stress, Ioff increased
over two orders of magnitude. The damage is quick and easily measured, but, surprisingly,
such damage does not affect circuit performance to the same degree. Chatterjee et al. re-
ported that a stressed ring oscillator failure, defined as a 5% reduction in oscillation fre-
quency, occurred for a time 100 times longer than the 10% damage criteria for measuring
2
Vt forward lin
0
Id forward sat
-2
Change (%)
-4
gm forward lin
-6
Id reverse sat
-8
Id forward lin
-10
0.0e+0 2.0e+3 4.0e+3 6.0e+3 8.0e+3 1.0e+4
Time (s)
Figure 6.33. Plot of HCI degradation for transistor parameters. (Reproduced by permission of Du-
ane Bowman, Sandia National Labs.)
c06.qxd 2/2/2004 12:32 PM Page 188
Stressed 60 minutes at VDD=4.5 V

1.0e-3
1.0e-5
ID (A)
1.0e-7
1.0e-9
1.0e-11
0 0.5 1 1.5 2
-VGS (V)
Figure 6.34. Stress time and pMOS transistor damage due to hot-carrier injection in a 0.35 ␮m
technology.
ILIN, the drive current of the transistor in an ohmic bias state [25]. Reasons for this para-
dox are developed next.
Why does the obvious damage to a transistor by HCI not evoke the same measure of IC
performance reduction? One reason is that the dominant speed parameter IDsat is minimal-
ly affected by HCI stress. The oxide damage occurs dominantly in the oxide over the
drain-depletion–substrate-depletion region when the transistor is in the saturated bias
state, and that only occurs during the logic transition. If HCI damage is present in a nMOS
oxide, then Vtn is increased only in the drain-depletion region. Charge inversion and Vtn
are irrelevant in the depletion region during the logic transition. In the transition from VDD
to GND, the transistors are in the depletion state for about 75% of the excursion. The dam-
age is in an unusual “don’t care” location. If a transistor drain and source are electrically
exchanged, then much more damage is observed, since the threshold voltage is critically
altered near the source region affecting normal carrier inversion. Another effect offsetting
IC performance is that a pMOS transistor undergoes a drop in Vtp and operates faster than
normal.
The typical HCI effect is reduction in Fmax (maximum measured operating frequency).
A production concern is that ICs with statistically short effective channel lengths will
have better Fmax performance, but higher drain depletion fields. The question is whether
Fmax will degrade by HCI during customer use. Unless HCI is severe, then expected re-
ductions in operating frequency are on the order of 1–3%. Guardbanding at test by raising
the Fmax limit by 5% is one protection. However, all manufacturers must make these deter-
minations from their own parts characterization.
Hot-Carrier Injection and Bias State. Figure 6.35(a) shows the substrate current
ISUB versus VGS when VDS is high, holding the transistor mostly in the saturated state. The
schematic for this measurement is shown in Figure 6.35(b). Hot-carrier generation in the
drain-depletion region causes impact ionization with holes and electrons entering the sub-
strate as well as the oxide. ISUB is larger and more easily measured than IG, and is often
used as a proportionality indicator of hot-carrier generation.
c06.qxd 2/2/2004 12:32 PM Page 189
The plot for an n-channel transistor in Figure 6.35(a) peaks near VGS ⬇ 0.5 VDS. When
VG is below threshold, few carriers exist in the channel, and ISUB is near zero. When VGS
approaches and becomes larger than VDS, the transistor enters the nonsaturation state, and
the depletion field at the drain disappears. Again no hot carriers are generated. When VGS
goes just above Vt then the device is in saturation and free carriers exist in the channel,
some of which cause hot-carrier generation. Holes and electrons that enter the gate expe-
rience an oxide electric field whose positive field is at the drain. The gate voltage is lower
than the drain voltage so that holes are preferentially attracted to the gate.
The left-hand portion of the curve in Figure 6.35(a) is the region in which holes enter the
oxide and become gate current. When VGS goes well beyond the peak, the gate voltage ris-
es, and electrons are drawn to the gate. The peak in the ISUB curve is a condition in which
both holes and electrons are entering the oxide, but neither with maximum field attraction
such as at the ends of the curve. The holes and electrons in the middle portion of the curve
tend to cause more interface damage here, in contrast to traps deeper in the oxide.
These bias curves are useful for engineers who design reliability monitor structures for
measuring HCI. Wafer-level reliability (WLR) monitor structures are designed for rapid
measurement of damage. The HCI is maximized by biasing transistors at these worst-case
conditions (i.e., VGS ⬇ VDD/2) and even at lower temperatures. The curves also show that
HCI occurs during the logic state transitions, and not during the quiescent states. HCI re-
quires the saturated bias state of the transistor, and that only occurs during the logic gate
transition. The terminal polarities of an inverter are more dynamic than the curves in Fig-
ure 6.35 since VDS is not constant, but drops as VGS increases. Ᏹch and Ᏹox vary in a com-
plex manner over a wide range during a logic transition.
Prediction of Integrated Circuit HCI Reliability. One method of estimating how

long an IC will perform in a normal hot-carrier injection environment surprisingly uses
5e-05
4e-05
3e-05
Isub (A)
2e-05
VGS VDS
A
1e-05
0
0 0.5 1 1.5 2 2.5 3
Vgs (V)
(a) (b)
Figure 6.35. (a) n-channel transistor hot-carrier generation curves as function of VGS and ISUB. (b)
Schematic for measurement.
c06.qxd 2/2/2004 12:32 PM Page 190
data collected from individual transistors. These data are then combined with estimates of
the IC duty cycle and other operating parameters. We thank Steve Mittl of IBM, who lec-
tured on these subjects at the University of New Mexico, for the following discussion.
A theoretical model forms the basis of HCI reliability prediction for most companies
[34]. The end result is a calculation of transistor lifetime ␶ as
冢冣
W ISUB –␾it/␾i
␶ = C⬘ ᎏ ᎏ (6.25)
ID ID
where C⬘ is a constant, W is transistor width, ID is drain current, ISUB is substrate current,

␾it is the interface state activation energy (⬇ 3.7 eV), and ␾i is the impact ionization acti-
vation energy (⬇ 1.2 eV). The ratio of ␾it/␾i is a constant of about 3. ␶ is the defined life-
time degradation due to HCI (i.e., a 10% drop in Vt or gm, etc.). If we rearrange the terms,
we get
␶ID
冢冣
ISUB –␾it/␾i
ᎏ⬀ ᎏ (6.26)
W ID
We can measure ␶, ID, and ISUB for each transistor in the stress experiment, and we know
W and ␾it/␾I ⬇ 3. If we plot these variables on log-log scale, we get a straight line such as
shown in Figure 6.36. The data on the lower right are for transistors that failed in a few
seconds under a HCI stress condition.
The slope in Figure 6.36 is constant. The line will be offset for transistors of different
quality. The next step is to estimate chip HCI lifetime. The method predicts chip HCI life-
time by estimating ID and ISUB at use conditions, and then derives ␶ from those use condi-
tions in Figure 6.36. We then use the conversion equation from DC stress into chip power-
on hours (POH)
DC stress time = duty factor × switch factor × chip POH (6.27)
where duty factor is (device DC equivalent stress per cycle)/(cycle time). Switch factor is a
fraction that may consider that stress only occurs during low-to-high input transitions, and
Figure 6.36. Lifetime projection of HCI degradation for several transistors (from [42]).
c06.qxd 2/2/2004 12:32 PM Page 191
then you solve for chip POH. Remember that HCI damage occurs only in normal operation
when the transistor is in saturation, and that occurs only during the logic transitions. The
method is tedious, but does provide HCI estimated lifetimes. Power-on hours are typically
10 years, but will vary with product expectations. Typical HCI reliability goals are about
0.1–1.0 years of DC stress. Practical stresses of test structures are 10–100 hours.
6.4.3 Defect-Induced Oxide Breakdown

Foreign particulates or poor quality oxides typically lead to early breakdown of the oxide
for lower applied voltages. These are called gate oxide shorts. The origins of particulate-
driven gate shorts are different than those for HCI or wearout, but the end result can be
similar to breakdown by wearout. The time to failure tF is shorter for defect-related gate
oxide shorts appearing as early as the production test or from field returns weeks to years
later. Manufacturers try to eliminate defect-induced gate shorts by stressing the ICs at
high voltages for short time periods (burn-in). Chapter 7 will analyze the electronic ef-
fects that occur when gate oxide shorts are present in an IC.
6.4.4 Process-Induced Oxide Damage

Plasma and ion implantation process techniques are manufacturing steps used for etching
or doping some areas of the circuit during semiconductor device fabrication. During these
steps, devices may be exposed to charges collected by aluminum or polysilicon conduct-
ing lines (called “antennas”) connected to the gate terminals of MOSFETs. As a result,
gate oxides can be damaged, affecting Vt, the subthreshold slope, and the transconduc-
tance of transistors. The stress currents to which these charges give rise may eventually
cause oxide breakdown. For oxides that do not experience breakdown, oxide trapped
charges and interface states can be created. These damaging processes can be avoided by
providing alternative conducting paths to the charge collected during these fabrication
steps and thus protecting the gate oxides. Often, reverse-biased diodes are tied to the “an-
tennas” to provide a charge path to ground.
6.4.5 Negative Bias Temperature Instability (NBTI)

A recent oxide reliability issue has appeared that impacts short-channel pMOS transistors
with their p-doped polysilicon gates. It is called negative bias temperature instability
(NBTI), and it is a wearout mechanism with positive charge buildup at the channel inter-
face of pMOS transistors. It causes threshold voltage absolute magnitude increase and re-
duction in IDsat. The damage has been referred to as caused by “cold holes” [38], and is
identified as getting worse with scaling of oxide thickness. The “instability” refers to the
time variation in Vtp and IDsat [21]. The affected pMOS transistor has higher Vtp than a
transistor in normal inversion.
Several mechanisms have been proposed for NTBI but, presently, the accepted one is a
hole-assisted electrochemical reaction [38]. Interface states are formed when a hole
breaks a silicon bond, forming trivalent silicon in the interface region. Hydrogen is be-
lieved to be the spun-off element, and as H diffuses away, a positive charge is left on the
trivalent Si atom. H2O and holes are believed to be reactants. The exact nature of the reac-
tion is still not well understood. The necessary components for NBTI are holes, hydrogen
(either as H2, H+, or H2O moisture), high temperature (> 100°C), and oxide voltage [38].
c06.qxd 2/2/2004 12:32 PM Page 192
NBTI occurs in the pMOS transistor when Vin = 0 V, but NBTI shows some recovery
phenomena when Vin = VDD, especially at high temperatures such as at burn-in. Chen et al.
reported that for inverter experiments, NBTI was less during dynamic stressing than that
of DC stressing, and that NBTI damage was overestimated for the DC studies [26]. NBTI
is a significant problem in pMOSFET performance for advanced technologies [38]. Cir-
cuit design and lifetime projections must consider the competing degradation from hot-
carrier injection.
6.5 CONCLUSION
Metal and oxide failure mechanisms were described that showed the relation between ma-
terial properties and potential IC failure. Electromigration and stress voiding are constant
challenges for deep-submicron transistor ICs. Oxide wearout, hot-carrier injection, oxide
ruptures due to defects, and NBTI are other materials concerns. Engineers in the CMOS
IC industry need to understand these reliability failure mechanisms.
ACKNOWLEDGMENTS
We thank Bill Filter, Joe Clement, Bill Miller, Ted Dellin, Dave Monroe, Duane Bowman
and Steve Yazzie of Sandia National Labs, and Shannon Hawkins of Boeing Aircraft
Corp. for critical reviews and suggestions. Bill Filter´s stress void lectures and Joe
Clement’s electromigration lectures in the University of New Mexico Microelectronics
Reliability class were particularly beneficial. We also thank Steve Nelson and Rod Augur
of Philips Semiconductors, Steve Mittle, Jim Lloyd, Tim Sullivan, and Bob Rosenberg of
IBM, Cleston Messick of Fairchild Semiconductors, Tim Turner of Keithley Instruments,
and Don Pierce and Eric Snyder of Sandia Technologies, who lectured in the University of
New Mexico Microelectronics Reliability Series Lectures and influenced us.
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EXERCISES 195
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EXERCISES
6.1. Why would a Cu alloy in an Al base interconnect (a substitutional interconnect) in-

crease the resistivity over pure Al?
6.2. When ICs increase their operating temperature from about 85°C to 120°C, how
does this impact metal reliability?
6.3. When electromigration time to fail is plotted against the width of metal samples, a
typical curve looks like the one sketched in Figure 6.37. From your knowledge of
electromigration and grain boundary models, why does tF increase for very narrow
and very wide interconnects?
tF
Metal Width
Figure 6.37. Time to failure versus interconnect width.
6.4. Aluminum metal lines using tungsten vias have increased sensitivity to electromi-
gration at the Al/W interface due to the inert nature of W to electromigration. Do
copper interconnect systems using Cu vias form a perfect interface, thus avoiding
the W/Al problem?
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6.5. The line that interconnects a 2NAND gate drive circuit to a load 2NOR gate input
has certain electromigration design rules. If an n-channel transistor in the 2NOR
gate connected to this line acquires a gate-to-source oxide rupture, discuss the elec-
tromigration risk.
6.6. Two walls in an airtight room move slowly inward and stop. The room pressure is now
10 atmospheres. There is no net motion of air molecules under this high stress. Why?
6.7. Why does electromigration failure rate decrease at higher clock frequencies?
6.8. An unpassivated interconnect line has a Blech constant of 3500 A/cm and a Blech
length of 95 ␮m. If the same structural interconnect is passivated, the Blech con-
stant goes to 6500 A/cm. How is the Blech length effected?
6.9. Given for an Al interconnect that ␣Al = 23.5 × 10–6/°C, ␣SiO2 = 0.5 × 10–6/°C, Ym =
71.5 GPa, and ␯ = 0.35. Compare the stress at 30°C when the passivation deposition
temperature is lowered from 430°C to 400°C to 300°C.
6.10. Cu with its higher melting temperature of 1085°C was expected to offer total pro-
tection from electromigration. What prevented Cu from being the perfect electromi-
gration metal?
6.11. Copper interconnects require barrier metal lines to confine Cu. Compare the via-re-
sistive effect of a Ta liner that occupies 10% of the damascene space to that of a
pure Cu via. The dimensions of a cylindrical interconnect are given in Figure 6.38
(␳Cu = 1.7 ␮⍀ · cm and ␳Ta = 200 ␮⍀ · cm).
100 nm
200nm
Pure Cu Cu with Ta liner
Figure 6.38.
6.12. An oxide dielectric has a shorter time to failure if the oxide has greater area and
thinner dimensions. Use the percolation model to explain why.
6.13. Explain what effect large load capacitance has on hot-carrier injection.
c06.qxd 2/2/2004 12:32 PM Page 197
6.8 EXERCISES 197
6.14. Assume that an aluminum line of 0.5 ␮m thickness and 0.5 ␮m width is overlaid
with TiN of 0.1 ␮m thickness. When the Al opens, it leaves a void of 0.5 ␮m length.
The current density is J = 20 MA/cm2. If the resistivities are ␳Al = 2.66 ␮⍀ · cm and
␳TiN = 2.66 ␮⍀ · cm, what is the power dissipation in the TiN section of the break?
Give your answer in power per unit area (Watts/cm2), where area is the bottom face
of the TiN.
6.15. Electromigration T50 data: two metals evaluated from two different processes.
Boltzman’s constant = 1.38 × 10–23 eV/°K.
(a) Find the thermal activation energy for both metals and state which metal is bet-
ter.
(b) Give reasons why the quality might be different for (A) and (B) in Figure 6.39.
18
10
10 0
(A)
2
T50 J
(B)
1/T x 1E3
17
10 10
1 2 3 4 5 6
1.62 1.69 1.76 1.83 1.90 1.97 2.04
Figure 6.39.
6.16. An overall stress acceleration factor of 5 × 105 is desired for a particular defect in a
qualification test. The thermal activation energy is 1 eV, normal temperature is
55°C, normal voltage is 5 V, stress voltage is 7 V, and the oxide voltage acceleration
constant B = 400 Å/Tox, where Tox = 100 Å. Calculate the stress temperature Ts in
°C to provide the acceleration factor of 5 × 105.
6.17. A company had been using an oxide defect thermal activation of Ea = 0.3 eV and a
calculated failure rate of 500 FITs (1 FIT = 10–9 fails/hour). From new extrapolated
data, they found that Ea = 0.6 eV. What would the failure rate calculation be if Ea =
0.6 eV? The experimental temperatures were T1 = 55 °C and T2 = 125 °C.
6.18. An aluminum stress experiment is conducted in which T1 = 27 °C, T2 = 227 °C, and
J1 = J2 = 107 A/cm2. The average times to fail are: tF1 = 5000 hour and tF2 = 15 hour.
(a) Calculate the Al activation energy Ea.
(b) If J2 increases to 3 × 107 A/cm2, calculate the expected failure time tF2.
c07.qxd 2/20/2004 9:49 AM Page 199
CHAPTER 7
BRIDGING DEFECTS
7.1 INTRODUCTION
The previous chapter showed failure mechanisms resulting in shorts between IC conduct-
ing paths. A bridge or shorting defect is an unintentional connection between two or more
circuit nodes. Bridges in ICs induce abnormal electrical behaviors that depend on certain
circuit parameters and the resulting circuit topology. The major bridge defect variables are
앫 Ohmic or nonlinear
앫 Intragate-connections across transistor internal nodes
앫 Connections across the I/O nodes of separate logic gates
앫 Power rail to ground rail
앫 Combinational or sequential resulting circuit topology
앫 Interconnect material types—metal, polysilicon, diffusion region
앫 Critical resistance—transistor drive strength and W/L ratios
Ohmic bridge defects can be metal slivers bridging two interconnections (Figure 7.1(a),
large amounts of material shorting more than one interconnect (Figure 7.1(b)), or certain
forms of transistor gate oxide shorts. Gate oxide short defects are ruptures of the transis-
tor thin oxide that electrically connect the gate to the silicon structures underneath. Gate
shorts are well controlled in some fabrication processes and a plague in others. Bridging
defects in memory cells or flip-flops may or may not show responses different than those
in combinational circuits. Power rail shorts between VDD and GND are common and
though they do not involve signal paths of the IC, they need to be recognized and con-
c07.qxd 2/20/2004 9:49 AM Page 200
200 CHAPTER 7 BRIDGING DEFECTS
(a) (b)
Figure 7.1. (a) Metal sliver. (b) Metal blob. (Reproduced by permission of Jerry Soden, Sandia Na-
tional Labs.)
trolled. Low-power and battery-powered products cannot sustain predicted life if defect-
induced power supply leakage occurs.
This chapter characterizes bridge defect behavior at the circuit level, showing how to
calculate signal node voltages and power supply currents that are altered. We introduce
the parameters related to bridging defects, and then analyze their effect at the circuit level
for combinational and sequential circuits.
7.2 BRIDGES IN ICs: CRITICAL RESISTANCE AND MODELING
7.2.1 Critical Resistance

Critical resistance may be the most important concept in bridge defect electronics. It re-
lates the defect resistance to the electrical properties of the surrounding circuitry and its
induced logic behavior [18]. The critical resistance is the defect resistance value above
which the circuit will not functionally fail. Contamination particles like the ones shown in
Figure 7.1 cause shorts between two or more lines, resulting in bridging resistance be-
tween the shorted nodes.
Figure 7.2(a) shows one inverter (I1) driving a second inverter (I2) with an ohmic defect
bridge that shorts the output of I1 (V2) to the VDD rail. When the input to I1 is at 0 V, the
VDD
Rshort Rshort
Vin =VDD
Vin Vout Vout
V2 V2
I1 I2 I2
Ishort
Figure 7.2. Power rail to signal node bridge defect.

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7.2 BRIDGES IN ICS: CRITICAL RESISTANCE AND MODELING 201
nMOS transistor is off, whereas the pMOS is on and V2 is pulled to a logic one state.
Since there is no voltage drop across the bridging defect, no current passes through the
short. In this situation, it is said that the defect is not activated, since it has no effect on the
circuit in this logic state. When the input gate is at logic one, the pMOS transistor shuts
off and the nMOS transistor turns on. The pMOS transistor is not conducting, and current
is drawn through the resistor (Ishort in Figure 7.2(b)) with a subsequent voltage drop from
the VDD rail. The defect is said to be activated for the logic one input signal.
When the defect is activated in Figure 7.2, there is a competition between the nMOS
transistor of the first inverter that pulls node V2 to ground and the short resistance that
pulls this node to VDD. The final node voltage will depend on the relationship between the
value of the short resistance and the current drive of the inverter nMOS transistor. Figure
7.3(a) plots a set of voltage measurements at this node versus the input voltage Vin for dif-
ferent resistance values obtained for an inverter chain taken from [18]. Figure 7.3(b)
shows the power supply current versus the input voltage of the circuit for each resistance
value. Figure 7.3(a) shows that the higher the resistance value, the closer the transfer volt-
age curve to the fault-free one (note that a defect of infinite resistance would be equiva-
lent to a fault-free circuit). When the voltage at the input is at VDD, the nMOS transistor
transconductance takes its maximum value, and the inverter output is reduced for each de-
creasing defect resistance value.
When the defect resistance is 1 k⍀, the lowest possible voltage at the I1 inverter output
is around 4.3 V. Clearly, the circuit will exhibit a logic error for this defect resistance val-
ue, and also for any other short resistance in the 0–5 k⍀ range. For larger defect resistance
values, the voltage in node V2 is correct but logically weak. The successive gates can re-
cover the full logic response so that the static logic behavior remains correct, but the logic
gate whose input is near the defect has little protection against electrical noise spikes.
Since the critical resistance is defined as the defect resistance value beyond which the log-
ic operation is correct, this example shows a value of about 5 k⍀. All bridges except pow-
er rail shorts have a critical resistance whose value depends on the strength of the con-
tending transistor(s) across that bridge.
The impact of a given bridging defect on the logic behavior of a circuit does not de-
pend only on the resistance value and the transconductance of the transistors that compete
v2 IDD QRB
(V)
(µA)
1.0 kΩ
5.000 700.0
3.2 kΩ
1.0 kΩ 5.1 kΩ
.5000 70.00
/div /div
3.2 kΩ 10.0 kΩ
14.6 kΩ
5.1 kΩ
19.7 kΩ
10.0 kΩ 29.6 kΩ
14.6 kΩ 51.0 kΩ
.0000 51.0 kΩ .0000
.0000 5.000 .0000 5.000
VIN .5000/div (V) VIN .5000/div (V)
Figure 7.3. (a) Voltages and (b) consumption current for different resistance values of an internal
node to VDD short for an inverter chain [18].
c07.qxd 2/20/2004 9:49 AM Page 202
with the shorting resistance. The transfer characteristic of the gates driven by the weak
node will determine the impact of the defect, since they will interpret the logic value that
corresponds to each intermediate voltage. The driver gate may have a symmetrical Vout
versus Vin transfer curve, or it could be skewed to the left or right depending upon the in-
dividual p- and n-channel transistor drive strength (W/L ratio).
Functional failure is defined by a parameter called the logic threshold voltage VTL and
it is measured on the inverter voltage transfer curve at the point where Vin = Vout. VTL is
easily found as the intersection of a 45° line from the origin and the Vout versus Vin trans-
fer curve. VTL is typically about VDD/2 which is a convenient parameter to define failure
for the critical resistance calculations that follow. Some examples illustrate critical resis-
tance calculations.
왎 EXAMPLE 7.1
For the defective circuit in Figure 7.2(a), K n = 75 ␮A/V2, W/L = 4, VDD = 1.5 V,
Vtn = 0.4 V, and the logic threshold voltage is 0.75 V. Find the current and voltage
V2 when Rshort = 100 ⍀ and (b) Rshort = 4 k⍀.
(a) Figure 7.2(b) shows the equivalent circuit for analysis. The pMOS transis-
tor is removed and the input activates the defect. The saturated state equation for
the transistor is
W ␮A
IDn = Kn ᎏ (VDD – Vtn)2 = 75 ᎏ 4(1.5 – 0.4)2 = 363 ␮A
L V2
KVL gives
VDS = V2 = VDD – IDnRshort = 1.5 – (363 ␮A)(100) = 1.46 V
Check the bias state:
VGS < VDS + Vtn 1.5 V < 1.46 + 0.4
The transistor is saturated, so the answer is correct and V2 = 1.46 V. This is an er-
ror voltage since Vin = 1.5 V should produce V2 of about 0 V, or at least below the
logic threshold voltage VTL = 0.75 V.
(b) Rshort increases to 4 k⍀ and the saturated state equation again gives IDn =
363 ␮A, as in (a) and
VDS = V2 = VDD – IDnRshort = 1.5 – (363 ␮A)(4 k⍀) = 48 mV
Check the bias state:
VGS < VDS + Vtn 5 V < 1 + 0.4
The transistor is in the nonsaturated state so we must try again by combining the
nonsaturated state equation:
␮A ␮A
IDn = 75 ᎏ2
4[2(Vin – Vtn)V2 – V 22] = 300 ᎏ [2(1.5 – 0.4)V2 – V 22]
V V2
c07.qxd 2/20/2004 9:49 AM Page 203
with KVL:
VDD – V2 1.5 – V2
IDn = ᎏ = ᎏ
Rshort 4 k⍀
Solving both equations simultaneously:
V2 = 0.492 V, or 2.54 V
the solution is
V2 = 0.492 V
V2 is below the logic threshold value of 0.75 V; therefore, a correct logic value
would be read. 1 k⍀ is above the critical resistance, but this defective circuit has
lost significant noise immunity at the V2 node, making it vulnerable to logic up-
set by noise spikes. Also, IDDQ = (1.5 – 0.492) V/4 k⍀ = 252 ␮A is considerably
above the normal quiescent power supply current value for the gate. 왎
Critical resistance was evident in these two examples. The 100 ⍀ defect resistance was
small, and V2 failed its intended logic value. The larger 4 k⍀ resistance did not cause V2 to
fail. The critical resistance Rcrit lies between 100 ⍀ and 4 k⍀. The next example calculates
its exact value.
왎 EXAMPLE 7.2
Calculate the exact value of the critical resistance Rshort = Rcrit for the circuit of
Figure 7.2(a), using K n = 75 ␮A/V2, W/L = 4, Vtn = 0.4 V, VDD = 1.5 V, and the
logic threshold voltage VTL = 0.75 V.
This problem is not as bad as it looks. The logic threshold of VTL = 0.75 V de-
fines the V2 voltage point where failure just occurs. If V0 = 0.75 V, then the
nMOS transistor is in the nonsaturated state since
Vin > V0 + Vtn 1.5 V > 0.75 V + 0.4 V
The nonsaturated equation gives
␮A
IDn = 75 ᎏ 4[2(1.5 – 0.4)0.75 – 0.752] = 326 ␮A
V2
VDD – V0 (1.5 – 0.75) V
Rcrit = ᎏ = ᎏᎏ = 2.3 k⍀
IDn 326 ␮A
The circuit will functionally fail if the bridge defect resistance is below 2.3
k⍀. 왎
왎 EXAMPLE 7.3
Calculate the critical resistance for the bridge defect in Figure 7.4, given Kp =
300 ␮A/V2, Kn = 500 ␮A/V2, W/L = 1 Vtn = 0.35 V, Vtp = –0.35 V, VDD = 1.2 V,
and the logic threshold for high/low distinction is VTL = 0.6 V.
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1.2 V 1.2 V
MP1
0V 0V
Vo1 Vo1
RDef RDef
1.2 V
Vo2 Vo2
1.2V 1.2 V
MN2
(a) (b)
Figure 7.4.
Figure 7.4(b) shows the equivalent circuit when the off-transistors are re-
moved. We must first choose which node attached to RDef will fail first. If Vo1
drops below 0.6 V, then it fails, or if Vo2 rises above 0.6 V, then it fails. The clue is
that MP1 has weaker drive strength than MN2 and, therefore, cannot win the
contest with MN2. The drain at MP1 will fail first. At failure, we can assign VDP1
= VTL = 0.6 V. We then know all node voltages except the drain of MN2. Since
VGP1 = 0 V, VDD = 1.2 V, and VDP1 = 0.6 V, you can verify that MP1 is in the non-
saturated state. The drain current through both transistors and the defect is
␮A
IDP1 = 300 ᎏ [2(1.2 – 0.35)0.6 – 0.62] = 198 ␮A
V2
We can find the voltage Vo2 and Rcrit is found by Ohm’s law. We know that Vo2 <
0.6 V, since we deduced that it had not failed. MN2 is then in the nonsaturated
state since
Vin > Vo2 + Vtn 1.2 V > 0.6 V + 0.35 V
The nonsaturated equation allows calculation of Vo2:
␮A
IDN1 = 500 ᎏ 2
[2(1.2 – 0.35)Vo2 – V o2] = 198 ␮A
V2
where the valid solution is Vo2 = 279 mV.

Rcrit is
Vo1 – Vo2 (0.6 – 0.279) V

Rcrit = ᎏ = ᎏᎏ
IDN1 198 ␮A
Rcrit =1.62 k⍀
왎
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Self-Exercise 7.1.
For the circuit and problem in Figure 7.4, all parameters are the same except
(a) Calculate Rcrit if Kp = 150 ␮A/V2 and Kn = 250 ␮A/V2.
(b) What is the ratio of Kp/Kn when Rcrit goes to zero; what does that mean?
These problems deepen insight into critical resistance properties. The single transistor
bridged to a power rail has a critical resistance that is dependent upon the current drive
strength of the transistor. When the defect resistance connects a pull-up to a pull-down
transistor, the Rcrit is a function of the current drive mismatch and the current drive
strengths. The signal node with the weaker current drive will fail first. The weaker a tran-
sistor’s current drive, the larger the resistance needed to protect that node from failure.
Rcrit increases as the mismatch in pull-up and pull-down current strength gets larger,
but Rcrit goes to zero when the pull-up and pull-down transistor current strengths are
equal. The product significance is that real IC bridging defects have a range of resistance
or impedance values, and many ICs will still function for bridge defects with quite low re-
sistances. It is not known a priori whether a particular bridge will fail or pass the IC when
voltage-based tests are applied.
Different logic combinations affect Rcrit since pull-up and pull-down strengths vary
with the logic input signals. Figure 7.5 shows a 3NAND contending with a 2NAND. The
critical resistance values were simulated from a standard cell library for various input
combinations, and results are in Table 7.1. The pMOS transistor widths were double the
nMOS transistor widths. The minimum Rcrit of 150 ⍀ occurred when a single pMOS tran-
sistor contended with two nMOS transistors in series. The pull-down was only slightly
stronger than the pull-up strength for this logic state. The maximum Rcrit of 1750 ⍀ oc-
curred for the worst-case contention of three n-channel series pull-down transistors
(weak) against two parallel p-channel pull-ups (strong). This example shows the strong in-
fluence of input logic states on electrical response in the presence of a bridging defect.
These bridging defects cause weak node voltages or logic failure, but the quiescent power
supply current IDDQ is always elevated.
Self-Exercise 7.2
Two inverters have a bridge defect connection at their output terminals. The
nominal K⬘n = 100 ␮A/V2 and inverter current drives (K⬘n, K⬘p) are matched within
10% of the worst case. What is the range of Rcrit if Vtn = 0.5 V, Vtp = –0.5 V, VTL =
0.75 V, and VDD = 1.5 V?
A
B
C
Rcrit
D
E
Figure 7.5. Bridging defect between two NAND gate outputs.

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Table 7.1. Critical Resistance as a Function of Logic State

A B C D E Rcrit(⍀)
0 0 0 1 1 950
0 0 1 1 1 725
0 1 1 1 1 150
1 1 1 0 1 1250
1 1 1 0 0 1750
왎 EXAMPLE 7.4
Use the short channel nMOS transistor curves from Figure 3.34(b) in Figure
7.2(a) to graphically find the critical resistance when that transistor has a bridge
defect tied between its drain and VDD rail.
We repeat the transistor curves in Figure 7.6 for convenience. The supply volt-
age for this technology is 2.5 V, and we will assume that the value for the gate
logic threshold voltage is VTL = VDD/2 = 1.25 V. To compute the critical resis-
tance value, we must find the resistor load curve that intersects the drain current
curve with VGS = VDD at VDS = 1.25 V.
We plot a vertical line at VDS = 1.25 V and look at the intersection with the
topmost drain current curve (corresponding to VGS = VDD). The intersection point
(VDS = 1.25 V, IDS = 12.8 mA), gives the drain current that will pass through the
nMOS device and the resistor short for the critical resistance value. We can com-
pute this critical resistance from the slope of the line joining the VDS = VDD, IDS =
0 point to the intersection point found (IDS = 12.8 mA), or from the Ohm’s law
using the obtained current value, i.e:
0.5VDD 1.25 V
Rcrit = ᎏᎏᎏ = ᎏ = 97.6 ⍀
ID(VGS = VDD, VDS = VDD/2) 12.8 mA
VGS = 2.5 V
VGS = 2.25 V
VGS = 2.0 V
VGS = 1.75 V
VGS = 1.5 V
VGS = 1.25 V
VGS = 1 V
VDS (V)
Figure 7.6. Transistor curves and resistor load to compute the critical resistance.
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7.2.2 Fault Models for Bridging Defects on Logic Gate Nodes (BF)
We saw that when a bridge defect is activated, it causes intermediate voltages at the short-
ed nodes. An accurate description of the induced behavior may use analog-based circuit
simulators, such as SPICE, to determine the operation region of the affected transistors,
the intermediate voltages at the short nodes, and the induced power supply current in-
crease. A test and diagnosis goal is to predict the faulty behavior of the circuit to find ap-
propriate circuit stimuli (called test vectors) that can expose the bridging fault (BF).
Most circuit test pattern generators derive test vectors from a logic description (net list)
of the IC. Unfortunately, logic circuit simulators cannot describe the behavior induced by
a BF since the altered node voltages may not fit defined logic values. Analog simulators
take too long to calculate the state of large circuits, and in many cases a detailed circuit
analysis by analog simulators is not required. Several methods try to overcome this diffi-
culty using logic fault models. A logic fault model is an approximation at the logic level of
the behavior induced by a defect within an IC.
Generally, fault models try to overcome the gap between the logic description and the
analog behavior induced by defects in the circuit. Since logic fault models are widely used
in industry to calculate test vectors, we describe some bridging fault models intended for
bridge defects at the logic gate I/O level. These models include:
앫 Stuck-at
앫 Pseudo stuck-at
앫 Logic-wired AND/OR
앫 Voting
앫 Biased voting
A brief view of each logic model will be given with more details found in [1, 8, 10, 21].
Stuck-at Fault Model (SAF). The stuck-at model, further discussed in Chapter 10, is
the simplest and most used logic fault model in the industry. It came from the bipolar tran-
sistor IC era, and was accurate for that technology. Many authors showed that stuck-at
faults are inadequate for CMOS technology, but its substitution by more accurate models
has been slow, given the SAF’s easy computational efficiency and its established practice.
Stuck-at fault models applied to bridging defects at the logic level assume that one sig-
nal node is permanently tied to the power rail or to ground, and is therefore referred to as
stuck-at–1 or stuck-at–0. As shown in previous examples, the SAF model can only quanti-
fy detection of low-resistance (sub-Rcrit) BFs between a signal node and the power/ground
rails. Literally, the SAF models a zero Ohm bridge defect to one of the power rails. The in-
efficiency of the SAF model in detecting BFs motivated the search for more accurate log-
ic fault models.
Pseudo Stuck-at Fault Model. This fault model, initially proposed in [7], exploits
the leakage current mechanism induced by bridging faults to simplify the computation ef-
fort for ATPG and increase fault coverage. Schematically, this fault model targets stuck-at
faults at primitive logic gate inputs, and considers a defect to be detected if its effect is
propagated to the output of such a gate. The effect of the fault does not need to be propa-
gated to the IC primary outputs, since it will be detected at the circuit power supply pin by
measuring the quiescent current. The advantage of this model is at the computational lev-
c07.qxd 2/20/2004 9:49 AM Page 208
el, since only small changes to conventional stuck-at tools are required to adopt this fault
model.
Logic-Wired AND/OR Model. Logic-wired models for BFs were taken from bipolar
technologies (ECL and TTL), in which defective shorted logic gate outputs are logically
equivalent to a logic OR or logic AND gate. This behavior appears in technologies where
one of the logic levels is always stronger than the other. Therefore, when two nodes are
shorted, the stronger node overrides the weaker. Although this logic fault model is more ver-
satile than the stuck-at model, it is not well suited for CMOS technologies, since CMOS ICs
have no logic value always stronger than the other. We know that the voltage at a shorted
node depends on the relative sizing of the gates involved, the bridge resistance, and the in-
put logic states. An experimental study of wired-logic BFs showed poor correlation be-
tween this fault model and real defects [3]. A detailed analysis of logic wired fault models
for BFs is in [1].
Voting Model. The voting model was a step forward in modeling BFs [2]. It observes
that when shorted nodes are driven to opposite voltages, there is a competition between
conducting pMOS and nMOS transistors. The model assumes that the set of drivers hav-
ing the largest driving strength (i.e., those driving more current) will decide the final log-
ic value.
The voting model does not account for the nonzero bridging resistance value or the
logic threshold voltage of the fan-out gates. Nonzero BFs allow the output of the shorted
gates to be at different voltages (because of the voltage drop at the bridge), and therefore
be interpreted as different logic values for the subsequent gates. Maxwell showed that two
logic gates whose inputs are shorted could interpret the bridge-defect-related analog volt-
age differently [8].
Biased Voting. This model overcomes the limitations for circuits with variable logic
gate thresholds [8]. The biased voting model finds the conductances of the transistors in-
volved in the bridge, taking into account the particular voltage of the bridged node. The
voting model assumes a fixed initial voltage to calculate the conductance of the involved
transistors. Therefore, the biased voting model accounts for the nonlinear transistor char-
acteristics in calculating the driving strength of a device. Additionally, it takes into ac-
count the different thresholds of the logic gates connected at the shortened outputs.
Mixed Description. Since the electrical behavior induced by a bridge defect is analog,
an accurate model of the induced behavior uses a mixed description. The whole circuit is
described logically, except for the fault site that is described with an analog simulator.
This method, described in [13], joins the accuracy of analog simulators for the defect site
with the efficiency of simulating large circuits with logic-based tools.
7.3 GATE OXIDE SHORTS (GOS)
This section describes a form of intratransistor bridge defect caused by hard transistor ox-
ide breakdown from particles or oxide imperfections. Chapter 6 described oxide wearout
and rupture, and hot-carrier degradation of oxide material that inherently had no defects.
The particle-induced oxide failures described here are found at production test, or during
the infant mortality phase of the product life cycle.
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7.3 GATE OXIDE SHORTS (GOS) 209
Gate oxide shorts (GOS), or gate shorts, have troubled MOS technology since its be-
ginning in the mid-1960s. The thin oxide of the MOSFET is the control region in which a
transistor modulates charge population in the channel. A gate oxide short is a rupture in
the thin silicon dioxide (SiO2) between the polysilicon gate and any of the silicon struc-
tures beneath the oxide. The undamaged regions of the thin oxide generally still show nor-
mal charge inversion. In some cases, the transistor may still support functionality, al-
though IDsat may be degraded.
Figure 7.7 shows two forms of gate oxide shorts. Figure 7.7(a) shows thermal filament
growth on the gate edge, caused by high overvoltage on the gate. The electric field is
higher on the edge of the gate, causing breakdown, and filament growth between gate and
source. Figure 7.7(b) shows a gate short to the p-well caused by a small particle. The elec-
trical response is different for the two types of gate shorts.
7.3.1 Gate Oxide Short Models

Figure 7.8 shows an inverter cross section in an n-well technology. Gate drain/source ox-
ide shorts have simple electrical models, depending on the relative doping of the short-
ened terminals. There are six places where a gate short acquires a distinct parasitic con-
nection when the gate material merges with the substrate material. Since gate oxide shorts
connect the gate polysilicon with the drain, source, or bulk of the device, the electrical
properties of the contact depend on the doping type of the terminals being shorted. If the
gate and diffusion are of the same doping type, then the electrical model is a resistor be-
tween both terminals. If the shorted region has opposite doping, the electrical model is a
pn junction diode. A detailed description of all the possibilities is given next.
nMOS Transistor Gate–Drain/Source Oxide Shorts. An Ohmic connection

forms in an nMOS transistor when the rupture is from the n-doped polysilicon gate to the
n-doped drain or source (Figure 7.8) [4, 19]. The result is similar to that of an external re-
sistor connected between the gate to drain/source terminals. Figure 7.9 shows an I-V
(a) (b)
Figure 7.7. (a) Thermal filaments across gate to source. (b) Particle-induced gate short from gate
to p-well [4, 19].
c07.qxd 2/20/2004 9:49 AM Page 210
thin
oxide
n-well
p-substrate
Figure 7.8. Possible GOS defects in a CMOS inverter.
curve (a) taken with probes placed across the gate and source terminals. This signature is
an Ohmic gate short between the n-doped gate to n-doped source region. These forms of
gate shorts can result from weak oxides or, preferentially, because electric fields are high-
er at the edges of the gate structure than in the middle. Typical resistances for nMOS tran-
sistor gate drain/source shorts formed in the lab ranged from about 1 k⍀ to 20 k⍀, putting
them above most critical resistances. The gate short resistance in Figure 7.9, curve (a), is
about 20 k⍀.
nMOS Transistor Gate–Substrate Oxide Shorts. An nMOS transistor gate short

between the n-doped polysilicon gate to substrate doping results in a diode with its cath-
ode, or negative end, at the gate. Under normal positive biasing on the gate, this parasitic
diode is reversed-biased and might never conduct, but its depletion region behaves as an
additional “parasitic” drain diffusion region, taking electrons from the channel. The dam-
Gate
100
Source
(a)
(b)
(a)
IG (µA)
0 Gate
- 100
-VDD 0 VDD Source
VG (V) (b)
Figure 7.9. I-V curves for different parasitic elements forms of nMOS transistor gate oxide shorts.
(a) Gate to source. (b) Gate to p-well short [sketched from 4].
c07.qxd 2/20/2004 9:49 AM Page 211
7.3 GATE OXIDE SHORTS (GOS) 211
age-induced depletion region is surrounded by an inversion layer of electrons in the non-

damaged portion of the transistor. A parasitic nMOS transistor forms, with its gate and
drain connected (Figure 7.9(b)).
Chapter 3 showed that a transistor with its gate connected to its drain is always in the
saturated state when VGS > Vt. Therefore the IG versus VG curve is always that of a saturat-
ed nMOS transistor. Curve (b) in Figure 7.9 shows this quadratic curve for a gate short be-
tween the n-doped polysilicon gate and the p-well. Quadrant I is the normal bias operation
of the transistor. Quadrant III shows the parasitic diode response in forward bias as the
gate voltage is reversed. The defect can be modeled with two parameters describing the
defect position within the transistor and its effective resistance [19].
Self-Exercise 7.3
An inverter has an nMOS transistor with a gate short whose I-V properties are
shown in Figure 7.9, curve (a). Given Kn = 200 ␮A/V2, Kp = 150 ␮A/V2, W/L =
1, VTL = 1.25 V, Vtn = 0.5 V, Vtp = –0.5 V, and VDD = 2.5 V, show by calculation
whether the circuit will functionally fail. Hint: you must include the relevant dri-
ving transistor.
pMOS Transistor Gate–Drain/Source Oxide Shorts. Short-channel technology

changed the pMOS transistor polysilicon gate doping from n-doped arsenic to p-doped
boron to reduce short-channel effects. We will review responses of n-doped polysilicon
gates taken from measurements, and relate them to expected behavior in p-doped polysili-
con gates.
pMOS transistor gate shorts form diodes when the rupture is across an n-doped poly-
silicon gate to a p-drain or p-source. Such a diode gate short at the source clamps the
pMOS transistor gate voltage at one diode drop below VDD when a preceding pull-down
transistor attempts to pull the gate node to a logic zero. A gate short to the drain is a little
more complicated since the diode acts as a nonlinear feedback element from the drain
(output node) to the gate (input node). A p-doped polysilicon gate short to the
drain/source diffusion regions causes an Ohmic short.
pMOS Transistor Gate–Substrate Oxide Shorts. When the defect appears be-
tween the n-doped polysilicon gate and substrate of a pMOS transistor, the GOS is a low-
resistive Ohmic contact to the device substrate since they have the same doping type [19].
However, when power is applied, the total pMOS transistor structure combines with the
defect to form a parasitic pnp (bipolar) transistor. The parasitic GOS resistance allows
base terminal current injection to the pnp transistor. The gate current acts as the base cur-
rent of a bipolar transistor, and the resulting device characteristics mix MOSFET and
bipolar transistor current characteristics. When the gate voltage drops toward logic zero,
the pMOS transistor now provides an impedance path to the previous logic gate nMOS
transistor. This action raises the pMOS transistor gate voltage, weakening its correct sig-
nal. Figure 7.10 draws the parasitic bipolar structure.
An important circuit effect occurs within a single-well CMOS structure. The parasitic
bipolar device biased by the defect is connected to other parasitic bipolar devices inherent
to the structure that may cause latchup (See Chapter 5). Figure 7.11(a) shows a GOS de-
fect in a pMOS transistor causing light emission. Figure 7.11(b) shows the subsequent
c07.qxd 2/20/2004 9:49 AM Page 212
Drain Gate Source Bulk
p+ p+ n+
Well
Substrate
Figure 7.10. Electrical equivalent of a gate–substrate GOS for a pMOS transistor.
measured latchup behavior at the circuit level. When sufficient current passes through the
latchup structure, a negative I-V slope region rapidly locks the structure into a high-
current state.
General Electrical Model Equivalents for Hard Gate Oxide. All combinations
of transistor type, defect location, and polysilicon doping type lead to a generalized gate
oxide rupture model with 12 subcircuits. The electrical principles are: gate–drain/source
shorts form diodes or resistors, depending on whether the relative doping type is the same
(short) or opposite (diode). For gate–substrate shorts, defects connecting regions of differ-
ent doping type create a parasitic MOSFET, whereas shorts between same doping type re-
gions activate the parasitic bipolar transistor. Figure 7.12 summarizes the parasitic electri-
cal elements. The nMOS transistor equivalent defect circuits are shown in the first row,
and the pMOS transistors in the second row.
The p-doped polysilicon gate to n-well short creates a pn junction diode with its anode
at the pMOS transistor gate. This situation is similar to the nMOS transistor gate to p-well
short, where a parasitic MOSFET is formed. In the pMOS transistor gate short, the con-
I DD 10
(mA)
7.5
2.5
0
0 1 2 3 4 5
VDD (V)
(a) (b)
Figure 7.11. (a) A pMOS transistor GOS emitting light. (b) Latchup current response at the circuit
level.
c07.qxd 2/20/2004 9:49 AM Page 213
7.4 BRIDGES IN COMINATIONAL CIRCUITS 213
n- type polysilicon p-type polysilicon

GS GB GD GS GB GD
Figure 7.12. Generalized electrical model for gate oxide short defects.
nection forms a parasitic pMOS transistor that is always in the saturated state when gate
drive is greater than threshold voltage. In all gate short cases, the power supply quiescent
current, ID, is elevated, and logic voltages are either weakened or erroneous. ICs that have
GOSs, but still pass functional testing are reliability risks [5].
Soft Gate Oxide Shorts in Ultrathin Oxides. Recent studies show that wearout
and breakdown in the ultrathin oxides below 30 Å shows different properties than for the
thicker oxides in large-channel-length transistors [23, 24, 25, 26]. The older oxides were
well characterized, emphasizing the elevation of IDDQ and the reliability risk when gate
shorts passed through the test process. Ultrathin oxides show a soft breakdown in addition
to the hard breakdowns of thicker transistor oxides. Soft breakdown is an irreversible
damage to the oxide, the most significant effect of which is the increase in noise of the
gate signal. IDDQ is not elevated for the soft gate–substrate ruptures of ultrathin oxides.
The noise can show up to four orders of magnitude increase after soft breakdown, and this
is the only certain evidence of the irreversible damage to ultrathin oxides.
Degraeve et al. found that uniformly stressed 24 Å gates oxides have a uniform area
breakdown in transistors [23]. Breakdown over the channel had a high resistance from
105–109 ⍀, whereas breakdowns over the drain and source had resistances of 102–104.
Since the drain and source gate overlap area was much smaller than the area over the
channel, most of the breakdowns occurred over the channel. By measuring breakdowns in
200, 180, and 150 nm transistors, they found that the percentage of gate to drain and
source breakdowns increased as the transistors became smaller. The drain and source gate
overlap area becomes a larger fraction of the transistor gate area. The gate-to-drain or
source breakdowns were likely to cause hard failure, whereas the gate-to-channel break-
down showed no failure effects. A 41-stage ring oscillator with seven transistor gate rup-
tures continued to function with a 15% decrease in oscillator frequency [25]. Part of the
frequency reduction was due to hot-carrier damage during a prestress. Significantly, the
ring oscillator did not fail despite having several gate oxide breakdowns present.
Henson et al. also found that gate oxide breakdown was more severe at the drain and
source than over the channel [24]. They fabricated three channel-length transistors at
4.65 ␮m, 1.3 ␮m, and 0.45 ␮m, where the percentages of gate-to-drain–source break-
downs were 30%, 25%, and 75%. The data show that failure may occur for gate-to-drain
or source breakdowns, and the shrinking size of the transistors will begin to shift a
greater percentage of breakdowns from the channel region to the critical drain–source
region.
Detection of softly ruptured ultrathin oxide at production does not appear possible at
c07.qxd 2/20/2004 9:49 AM Page 214
this time, nor is the reliability status clear. The normal functioning of the transistor with
an ultrathin oxide is not as effected as the killer ruptures of the thicker oxides. The re-
cent ultrathin oxide experiments indicate that test escape and subsequent reliabilities
may not be as risky as for breakdown in older technologies. These different properties of
the transistor oxide demand more studies at the circuit level to assess the implications of
test escapes.
Percolation paths are high-impedance paths in the oxides connecting the gate to the
substrate regions. This negates the hard breakdown diode and low resistance gate-diffu-
sion paths. It also replaces parasitic MOSFETs with parasitic bipolar transistors with the
path percolation path forming a high-resistance base lead. There is need for more research
of these types of shorts at the logic gate level.
Three Other Transistor Node Shorts. There are also drain-to-bulk, source-to-bulk,
and gate-to-well (substrate) shorts. These can form pn junctions with soft or hard break-
downs between diffusion regions and the well (substrate), or from drain to source.
Drain–source shorts can arise from channel punchthrough, or mask particle-related short-
ened Leff, causing increased leakage.
7.4 BRIDGES IN COMBINATIONAL CIRCUITS
At the circuit level, we distinguish between intragate and intergate BFs. Intragate BFs are
shorts between internal nodes of a gate, whereas intergate shorts are between two or more
logic gates. This distinction is important for automatic test pattern generation (ATPG)
tools since the circuit description (at the gate level or at the transistor level) determines
which set of BFs is targeted. The behavior induced by BFs in combinational and sequen-
tial circuits is different. BFs in combinational circuits are of two types: nonfeedback
bridging faults and feedback bridging faults.
7.4.1 Nonfeedback Bridging Faults

A nonfeedback bridging fault is a short that does not create a logic path between a gate
output and a node that can determine the value of any of its inputs. This distinction is
made because nonfeedback bridging faults in combinational circuits cannot induce se-
quential behavior. This is the simplest bridging fault, and corresponds to the BFs dis-
cussed to this point. When the defect is activated, the shorted nodes assume intermediate
voltages whose values depend on the bridge resistance and the current drive strength of
the transistors involved. The logic behavior depends on the critical resistance of the short-
ed nodes and the logic threshold of fan-out gates.
When the defect is activated, the resulting logic value may or may not be correct, but
the power supply current will be elevated. This significantly impacts the coverage
achieved with different voltage-based test techniques, as explained in Chapter 10.
7.4.2 Feedback Bridging Fault

A feedback bridging fault is a short in which some logic input combinations to the circuit
create a logic path from a gate output to one of its inputs. Specifically, a BF between two
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7.4 BRIDGES IN COMINATIONAL CIRCUITS 215
i Logic Block j
(B)
DI DJ
BF
Figure 7.13. Feedback bridging fault.
nodes i and j is a feedback bridging fault if the logic value of j depends on the logic value
of i. Node i is called predecessor, while node j is called successor. Figure 7.13 shows such
a bridge between inverters DI and DJ. The output of DJ is connected to the output of in-
verter DI, and this may determine the logic state of DJ.
Feedback bridging faults are complex, since they can induce sequential behavior in a
combinational circuit. The behavior induced by a feedback-bridging fault depends on the
logic connecting the shorted gates (Block B in Figure 7.13). For a given input to the cir-
cuit, three situations may appear:
Case A. The input to the circuit is such that the logic value of node j is independent of
the logic value of node i.
Case B. The logic value of node j is equal to the logic value of node i.
Case C. The logic value of node j is opposite to the logic value of node i.
The first case is equivalent to a nonfeedback bridging fault since the logic values of the
shorted nodes are not related. The second case creates a noninverted feedback bridging
fault, whereas the third is referred to as an inverted feedback bridging fault. The two latter
cases are discussed after an example.
왎 EXAMPLE 7.5
Determine the logic values of A, B, and C in Figure 7.14 that categorize the cir-
cuit as Case A, Case B, or Case C. Assume that the NAND gate is always
stronger than the inverter.
We redraw the circuit to better identify the role of each gate in the circuit (Fig-
A
F
B
C
Figure 7.14. A combinational circuit with a BF.

c07.qxd 2/20/2004 9:50 AM Page 216
B A Logic
Block
F
i j
C
Figure 7.15.
ure 7.15). Node i is the output of the first inverter, whereas node j is the output of
the NAND gate (predecessor and successor, respectively).
Case A. When A = 0, the NAND gate output is j = 1, independent of any other
input to the circuit. When B = 1, the output of the NOR gate is 0 for all value of
i, thus making the value of j again independent of i. These two conditions cover 6
of the 8 possible combinations.
苶 + (B
Case B. In the fault free case, j can be put in terms of i: j = A 苶 · 苶i). There is
no condition under which j = i.
Case C. From the expression derived in the previous case, when A = 1 and B
= 1, then j = 苶i. This covers the two remaining cases. 왎
Noninverted Feedback Bridging Fault. These faults were traditionally thought to

be redundant, since the shorted nodes are at the same logic level. This is only true when
the strength of the predecessor gate (DI in Figure 7.13) is much stronger than the dri-
ving capability of the successor gate. If the successor gate (DJ) has a stronger driving
capability than the predecessor gate (DI), then the value of node i is determined by DJ.
If both drivers have the same logic output, then there is no conflict, and the defect is not
activated. If DI makes a transition against the stronger DJ gate, then node i will not
change and a competition between gates will appear. This causes an intermediate volt-
age and a quiescent supply current elevation. The situation can be described as a latched
state.
A subtle effect appears when gates DI and DJ have similar driving capabilities, with DI
slightly stronger than DJ. This case causes a significant delay because of a transient be-
havior appearing while the drivers are competing to set the final node value.
Inverted Feedback Bridging Faults. Inverted feedback BFs appear when the logic
values of the shorted gates are opposite. Two behaviors may occur, depending on which
gate is stronger. When the gate driving the predecessor (gate DI in Figure 7.13) is stronger
than the successor (gate DJ), then the defect causes a logic error and current elevation,
since driver DI overrides the output of DJ.
If the successor gate is stronger than the predecessor one, then the defect causes oscil-
lation in the circuit. The period of oscillation is related to the delay of the logic connecting
the predecessor output to the successor (logic block B in Figure 7.13).
Figure 7.16 shows experimental data from a test circuit. When the input was at logic
zero, then the predecessor dominated and no voltage oscillations were observed. When
the circuit input was set to a high logic value, the successor driver was dominant, causing
oscillations.
c07.qxd 2/20/2004 9:50 AM Page 217
7.6 BRIDGING FAULTS AND TECHNOLOGY SCALING 217
Figure 7.16. Oscillating behavior caused by an inverted feedback BF.
7.5 BRIDGES IN SEQUENTIAL CIRCUITS
The electrical behavior induced by BFs in sequential circuits may differ from combina-
tional ones, since the conditions to detect a BF in combinational circuits may not hold for
sequential ones. This depends on the circuit topology and defect site location. Lee intro-
duced the concept of control loops to designate groups of transistors that control each oth-
er to create memory elements [6]. A control loop is said to be in a floating state when it is
in a memory state, so that its value cannot be changed by the driving logic. If the memory
element is driven by its preceding logic, then it is said to be in a forced state. In some situ-
ations, a control loop in a floating state may prevent quiescent current elevation since the
internal nodes cannot be forced to the values required to elevate this magnitude. Since
these defects swap memory values, they may be detected with logic-voltage-based testing,
depending on the circuit implementation (shown in Chapter 10). The next section discuss-
es the effect of BFs in flip-flops as the basic memory element in sequential circuits, and
also BFs in semiconductor memories.
7.5.1 Bridges in Flip-Flops

The behavior induced by BFs in flip-flops depends on the circuit implementation. Flip-
flops can be designed with a standard NAND gate configuration, but when using CMOS
technology, tri-state inverter gates or pass gate transistor-based designs are often used.
The induced BF behavior differs with the design.
Rodriquez et al. showed that flip-flops implemented with tri-state inverters and pass
gate transistors may exhibit behavior in which the defect is not current-testable because of
the floating state control loop [15]. These BFs change the logic state of the memory ele-
ment and are therefore logically testable. Sachdev proposed a design modification using
an additional inverter to make these cells current-testable [16].
Metra et. al. showed that flip-flops may have BFs that do not change the logic behavior
c07.qxd 2/20/2004 9:50 AM Page 218
of the gate, and do not elevate the quiescent current of the circuit [9]. The defect impacts
the timing parameters of the cell, changing the set-up or hold time of the cell.
7.5.2 Semiconductor Memories

Bridging defects in SRAMs were analyzed by several researchers [12, 16, 22]. Bridging
defects at SRAM cells may or may not cause quiescent current elevation. The main reason
for not elevating the quiescent current is similar to the effect in flip-flops, and is due to
floating control loops. BFs between cells are not generally current-testable because the
cells that are not accessed do not maintain their logic value, and do not create a logic con-
flict required to elevate quiescent current. These defects may be detected using logic test-
ing.
Sachdev showed that internal timing restrictions inherent to asynchronous operations
in the memory may prevent current elevation for a desired period of time [17]. This sig-
nificantly impacts current-based test techniques since the time window required to mea-
sure the quiescent current is not guaranteed. The proposed solution requires design modi-
fications to improve current-testability coverage.
A detailed analysis of the behavior induced by gate oxide shorts in SRAMS was given
in [20]. Although gate oxide shorts (GOS) are inherent to a single transistor, they may in-
volve more than one single SRAM cell. GOS defects are responsible for many failures in
RAM cells such as data retention (a memory cell looses its value a short time after it was
written), coupling faults (more than one cell is accessed simultaneously), sense amplifier
recovery (the memory sense amplifier does not respond at the normal frequency of opera-
tion), and stuck-at behavior.
Sachdev analyzed BFs in DRAMs [17]. DRAM cells made of a storage capacitor (typ-
ically 50 fF) need refreshing because of leakage currents. BFs in these cells cause logic
errors, but the quiescent current is not elevated since there is no voltage stress or drive.
Moreover, since the charge stored in a DRAM cell is very small, even a high-impedance
defect can seriously affect the storage capability since there is no feedback structure to
compensate for the defect-induced leakage.
7.6 BRIDGING FAULTS AND TECHNOLOGY SCALING
Technology scaling does not have a direct impact on the bridging defect’s inherent charac-
teristics. The physical mechanisms for these defects that appear during IC manufacturing
or operation generally remain invariant. The same holds for the electrical properties of the
short.
Since the effect of a short on IC behavior is related not only to the defect itself, but also
to the surrounding circuitry characteristics, the impact of these defects is expected to
change with technology scaling. The main parameters affected are the critical resistance
and the quiescent current detectability of the defect. As technology scales down, the dri-
ving strength of transistors increases. Therefore, following the analysis made at the initial
part of the chapter, the critical resistance values are expected to decrease, thus making
logic testing even less effective in detecting BFs.
On the other hand, traditional quiescent current testing based on a single pass/fail
threshold (this technique will be introduced in detail in Chapter 10) is becoming less ef-
fective in submicron technologies due to elevated current leakage values and variability.
c07.qxd 2/20/2004 9:50 AM Page 219
REFERENCES 219
From this perspective, BFs are expected to be a challenge in submicron technologies since
more sophisticated techniques based on monitoring the delay induced by this defect or
variations in current leakage will be required.
7.7 CONCLUSION
This section described the many variables affecting the response of a circuit with a bridge
defect. The critical resistance concept is perhaps the most important, as it explains why
flagrant visual bridging defects may not cause a functional test of the circuit to fail.
Bridges between logic gate transistor nodes and bridges between signal nodes of two or
more gates have slightly different responses. Gate oxide shorts are a major source of the
intratransistor node bridges. They have linear and nonlinear properties depending on rela-
tive doping levels and location of the gate short. The bridge models developed to assist the
test vector generation problem were described. Finally, the behavior of bridging defects in
memory circuits was explained. Bridging defects cause IDDQ elevation and either a correct
but weakened node voltage or functional failure occurs. An exception to IDDQ elevation is
found in certain forms of memory bridges.
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EXERCISES
7.1. A 2 k⍀ defect resistance connects the inverter output to ground (Figure 7.17). Kn⬘ =
200 ␮A/V2, Kp⬘ = 100 ␮A/V2, Vtn = 0.6 V, Vtp = –0.6 V, and the logic threshold volt-
age is VTL = 1.5 V. Will the circuit logically fail?
7.2. (a) As VDD is reduced, explain why the critical resistance increases and how this re-
lates to more or less defect detection sensitivity by voltage-based testing.
(b) As temperature is reduced, carrier mobility increases and normal circuits run
c07.qxd 2/20/2004 9:50 AM Page 221
EXERCISES 221
I1 I2
Vin Vout
2 kΩ
Figure 7.17.
faster. Assume that the defect does not change resistance, What affect would
lowering temperature have on the values of critical resistance. Is the defect easi-
er to detect at low temperature for any given value of VDD?
7.3. Figure 7.1(a) shows a metal sliver between two metal interconnections.
(a) Calculate the sliver resistance if the height, width, and length are 0.5 ␮m, 0.4
␮m, and 1 ␮m. Assume that an Al sliver has a resistivity of 3.4 ␮⍀ · cm.
(b) A physical measurement of the resistance between the two metals interconnects
gives a resistance of about 500 ⍀. Why is there a discrepancy between the calcu-
lated and measured resistance?
(c) What is the impact on detection of this defect by a conventional voltage test that
tests for functionality?
7.4. Repeat the calculation for the critical resistance of the circuit shown in Figure 7.4(a)
when the pull-up and pull-down drive strengths are closer. Let Kp = 300 ␮A/V2 and
Kn = 310 ␮A/V2 when W/L = 1, Vtn = 0.35 V, Vtp = –0.35 V, VDD = 1.2 V, and VTL =
0.6 V. Comment on the significance of this.
7.5. (a) An integrated circuit is suspected of having a hard gate oxide short in an n-chan-
nel transistor. With measurements at the IC pin level, can you distinguish
whether this short is to the channel or diffusion regions (drain, source)?
(b) Repeat (a) for an ultrathin-oxide transistor.
7.6. (a) When a nMOSFET hard gate short occurs between a n-doped gate to a p-doped
substrate or a pMOSFET p-doped gate to a n-doped substrate, then a parasitic
MOSFET appears. When power is applied to an IC with such a short, explain
why these parasitic transistors are in either the saturated or nonsaturated state
bias.
(b) What is the effect when a soft-gate oxide rupture occurs on an ultrathin oxide?
7.7. (a) Assume that all transistors in the gates of Figure 7.14 have Kn(Wn/Ln) =
Kp(Wp/Kp), and Vtn = –Vtp, except for the NOR gate that has VTL = VDD/3 for the
input driven by the inverter. If the defect resistance is negligible, determine
which input combinations will lead to oscillations. Hint: the circuit needs to be
in Case C.
(b) If the transistor sizes of the inverters are doubled with respect to (a), and for all
devices Vt is 20% of VDD, compute the critical resistance that will lead the in-
verter override the NAND output.
c07.qxd 2/20/2004 9:50 AM Page 222
7.8. Compute the critical resistance trend for the circuit in Exercise 7.4 when scaling the
technology if VDD is reduced by 16%, Vt’s are reduced by 28.55%, and the transistor
drive current (Kn and Kp) increases by 15%.
7.9. An IC shows no functional failure, but IDDQ is abnormally elevated for every test
vector measurement. What type of defect might this indicate? What are the reliabili-
ty implications?
7.10. A functionally failing IC shows abnormal IDDQ for certain test vectors. What might
you conclude about this IC?
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CHAPTER 8
OPEN DEFECTS
8.1 INTRODUCTION
Open circuit defects are unintended breaks or electrical discontinuities in IC interconnect

lines occurring in metal, polysilicon, or diffusion regions.* Figure 8.1 shows two CMOS
open circuit defects. Figure 8.1(a) is a via not well bonded to the metal liner in the via
hole. Figure 8.1(b) shows locations in the metal where two vias are missing. This caused
an open circuit to two inverter logic gates. Open defects have greater behavioral complex-
ity than bridge defects.
The major open circuit defect variables are
앫 Size of the open defect. Is the crack wide or narrow?

앫 Defect location:
—Open gate to a single transistor
—Open drain or source
—Open to a logic gate input affecting a CMOS complementary transistor pair
앫 Open on a metal line driving several gates
앫 Capacitive coupling of open node to surrounding circuit nodes
Deep-submicron CMOS technologies use metal line widths of 130 ␮m or less and via
height-to-width ratios of more than 5:1. These dimensions, when coupled with IC via
*In the context of this chapter, an open is a complete disconnect. Resistive or weak opens are described in Chap-
ter 9 as extrinsic parametric failures.
c08.qxd 2/2/2004 12:34 PM Page 224
224 CHAPTER 8 OPEN DEFECTS
(a) (b)
Figure 8.1. (a) A resistive open with poor bonding between the via metal and via liner (reproduced
by permission of Bruce Draper of Sandia National Laboratories), (b) Missing vias (arrows) [6].
counts from hundreds of millions to over a billion and total metal lengths of several kilo-
meters, make via- and contact-related open defects more probable than before. Open de-
fects are unavoidable, and their detection is sometimes nearly impossible. We will start by
modeling the behavior of a floating node within an IC, and then analyze its impact on cir-
cuit behavior.
8.2 MODELING FLOATING NODES IN ICs
The main effect of an open IC signal line is that one circuit node is no longer driven by
any gate, but may be left in a floating or high-impedance (high-Z) state. The node does
not have a conducting path to VDD or ground through a low impedance connection. The
voltage on the floating node depends on the properties and topology of the surrounding
circuitry. Two primary variables determine the final voltage value of a floating node: (1)
the size of the crack and (2) the amount of charge present at the floating node.
The size of the crack determines if electrons can tunnel across the open, thereby con-
trolling the amount of charge injected from the original driver (the gate that should drive
the node in the fault-free circuit) toward the floating node. The charge at the floating node
also depends on the capacitive coupling to the surrounding nodes, and the charge at the
gate and drain terminals of the transistors to which the node may be connected. It is im-
portant to emphasize that the complete problem is often a complex combination of all
these factors. We will describe each effect and then summarize with a model that includes
all the effects.
8.2.1 Supply–Ground Capacitor Coupling in Open Circuits

Capacitor voltage dividers appear in some MOSFET open circuits. Figure 8.2(a) shows an
open on a metal line over a field oxide (floating node V2). Part of the floating metal line
runs over the IC substrate (tied to ground), and part of it runs over the well area (connect-
ed to VDD). The metal–oxide–semiconductor structure is a capacitor, so that the floating
c08.qxd 2/2/2004 12:34 PM Page 225
8.2 MODELING FLOATING NODES IN ICs 225
Signal from
Driver
VVDD
DD
Floating
node
(V2)
++
C1
C1 VV11
--
++
Field
oxide CC22 VV22
--
Substrate Well
(at GND) (at VDD)
(a) (b)
Figure 8.2. (a) Open crack in a metal line and (b) its electrical equivalent: a capacitor voltage
divider.
node is capacitatively coupled to ground and supply. The values of the coupling capacitors
to VDD and to ground depend on the length of the metal track running over the well and
the substrate.
The equivalent circuit of the floating metal has two capacitors in series (Figure 8.2(b)).
The voltages V1 and V2 are functions of VDD and the values of C1 and C2. From Chapter 1,
we review
Q Q
C1 = ᎏ and C2 = ᎏ (8.1)
V1 V2
then
冢冣
Q Q 1 1
VDD = V1 + V2 = ᎏ + ᎏ = Q ᎏ + ᎏ (8.2)
C1 C2 C1 C2
Substituting
冢冣
1 1
VDD = V2C2 ᎏ + ᎏ (8.3)
C1 C2
or
冢冣
C1
V2 = VDD ᎏ (8.4)
C1 + C2
In general, the voltage at the floating node can be expressed as
V2 = ␣VDD (8.5)
where ␣ is a constant ranging between 0 and 1.

c08.qxd 2/2/2004 12:34 PM Page 226
Self-Exercise 8.1
In Figure 8.2, (a) If VDD = 2.8 V, C1 = 10 fF, and C2 = 18 fF, calculate V2. (b) If V2
= 0.768 V, C2 = 25 fF, and C1 = 11 fF, calculate VDD.
The circuit in Figure 8.2(b) is used in open circuit defect analysis. For example, when
the transistor gate is open, it is in a high-impedance state but the parasitic capacitive envi-
ronment can often be reduced to a form of Figure 8.2(b). The defective circuit responds to
transistor gate voltages set up by the capacitor voltage divider.
8.2.2 Effect of Surrounding Lines

Typically, an IC metal line is surrounded by other conducting lines. When two conducting
lines at different metal levels cross over, there is a parasitic capacitance that couples both
nodes. The value of this capacitance depends on the metal lines’ intersecting area, which
in this case is not large. A similar situation occurs for two conducting lines running paral-
lel on the same metal level for a given distance, but in this case the coupling capacitance
is bigger.
Figure 8.3(a) shows two metal lines running adjacent on the same metal level (Vm and
VF nodes), while a third metal line (V3 node) on a higher level crosses both metals. One of
the lower metal lines has an open defect, and it is floating. The coupling capacitance from
the adjacent line in the same metal level will be higher than the coupling capacitance to
the upper metal, so that the influence of the adjacent line is much stronger.
The equivalent electrical circuit for the floating node in Figure 8.3(a) is shown in Fig-
ure 8.3(b). Neglecting the coupling influence of the metal-2 line (which is much smaller
than the influence of the metal-1 line), the voltage of the floating node (VF) will depend
on the logic value of the metal-1 line (Vm). An analysis similar to that developed previous-
ly leads to
冢冣
C1 + Cm
VF = VDD ᎏᎏ if Vm = H
C1 + C2 + Cm
(8.6)
冢冣
C1
VF = VDD ᎏᎏ if Vm = L
C1 + C2 + Cm
In general, when n nodes with voltage Vi are each coupled to the floating metal line, the
final voltage is expressed as
n
VF = ␣VDD + 冱 ␣iVi (8.7)
i=1
where ␣ and ␣i are constants ranging between 0 and 1.

In a real IC, the signal nodes that influence the floating node experience logic transi-
tions, thus changing the floating voltage with time. We can compute the floating voltage
after a transition of the influencing metal, using charge conservation. If the influencing
metal (Vm node) makes a high-to-low transition, then the initial voltage at the floating line
before the transition (VFin) is computed from
(Cm + C1)(VDD – VFin) = C2VFin (8.8)

c08.qxd 2/2/2004 12:34 PM Page 227
Signals from Metal-2

Floating Drivers coupling V DD
Metal-1 node node V m VDD
(VF) (V3) Vm
coupling
node
(Vm) CC
mm CC1
1
VVF
F
Field CC2
oxide 2
Well
VV3
Substrate 3
(at GND) (at VDD )
(a) (b)
Figure 8.3. (a) Two metal-1 signal lines crossing one metal-2 line. The coupling capacitance of
each metal-1 line to the other will be higher than the coupling capacitance to the metal-2 line. (b)
Equivalent electrical model with the signal drivers shown as inverters.
which gives
冢冣
Cm + C1
VFin = ᎏᎏ VDD (8.9)
Cm + C1 + C2
Once the transition is finished, the final voltage at the floating line (VFend) is computed
from
C1(VDD – VFend) = (Cm + C2)VFend (8.10)
which gives
冢冣
C1
VFend = ᎏᎏ VDD (8.11)
Cm + C1 + C2
Subtracting Equation (8.9) from Equation (8.11), the floating voltage change ⌬VF is
冢冣
Cm
⌬VF = ᎏᎏ VDD (8.12)
Cm + C1 + C2
Equation (8.12) shows that the influence of the surrounding metals depends proportional-
ly on the coupling capacitance value.
왎 EXAMPLE 8.1
Consider the dynamic NAND gate shown in Figure 8.4, where part of the metal-
1 interconnect layout is shown (the interconnect between metal-1 and the transis-
tor gate runs in polysilicon and is not illustrated). Determine the output value in
the evaluation phase (clock = 1) if transistor N2 input makes a transition from 0
c08.qxd 2/2/2004 12:34 PM Page 228
Clock
Metal 1
Lines out
N2
N1
10 µm
Figure 8.4. Dynamic NAND gate.
to VDD when the metal-1 input to N1 has an open (a) 5 ␮m away from the poly-
silicon, (b) 280 ␮m away from the polysilicon. Discuss the results in both cases.
The metal lines shown are at the minimum distance. Consider that the input
gate transistor capacitor and the polysilicon-substrate capacitor are negligible.
The circuit is fabricated with a technology that has Vtn = 0.35 V, VDD = 1 V, a
metal-1 to bulk capacitance of 0.05 fF/␮m, and a metal-1 to metal-1 capacitance
of 0.35 fF/␮m for minimum distance metal-1 lines.
(a) The metal-1 substrate capacitance of the metal portion connected to the
N1 gate is Cms = 5 ␮m × 0.05 fF/␮m = 0.25 fF, whereas the capacitance to the
metal line driving the N2 transistor input is Cmm = 5 ␮m × 0.35 fF/␮m = 1.75 fF.
Assuming that the gate of N1 is initially grounded, the final voltage of the N1
gate input node will be given by the voltage of a capacitor divider between
VDmetal-1 to metal-1 (N2 input) and ground.
冢冣冢冣
Cmm 1.75 fF
VGN1 = VDD ᎏᎏ = 1 V ᎏᎏ = 0.875 V
Cmm + Cms 1.75 fF + 0.25 fF
This voltage will turn on N1, since Vtn = 0.35 V. The circuit function will be cor-
rect if the gate driving N1 in the fault-free circuit also makes a low-to-high tran-
sition, but an erroneous logic behavior would occur if N1 was off in the fault-free
circuit.
(b) The N1 input to ground capacitance is Cms = 280 ␮m × 0.05 fF/␮m = 14
fF, and Cmm = 10 ␮m × 0.35 fF/␮m = 3.5 fF, since both metal lines run parallel
for 10 ␮m. The N1 gate voltage after the N2 transition is
冢冣
3.5 fF
VGN1 = 1 V ᎏᎏ = 0.2 V
3.5 fF + 14 fF
In this case, N1 will remain off and the gate output will stay high. This will lead
to a logic error if N1 input is supposed to switch in the fault-free circuit.
In general, the lower the interconnect level and the farther away the defect
from the gate input, the more unperturbed the value of the floating node. 왎
8.2.3 Influence of the Charge from MOSFETs

In many cases, the floating node drives the gate of one or more transistors. Renovell and
Cambon [8], Champac et al. [1], and Johnson [4] analyzed the device terminal’s charge in-
c08.qxd 2/2/2004 12:34 PM Page 229
fluence on the gate voltage. The charge stored at the gate terminal of a MOSFET has a
strong dependence on the coupling from the drain and channel terminals. Hence, the drain
voltage plays an important role on the final gate voltage value. Neglecting the effects
from other nodes, the floating gate voltage can be expressed as [4]
QFG
VFG = ᎏ + ␣VDS (8.13)
CG
where QFG is the charge at the floating gate, CG its capacitance, and ␣ ranges between
zero and one. A detailed expression for QFG can be found in [1].
Experimental results [1, 4] report floating voltage values up to 3 V for a 5 V technolo-
gy, demonstrating that the device can conduct significant drain current while its gate is
floating.
8.2.4 Tunneling Effects

Narrow cracks can appear in metal lines or in a contact or via. Figure 8.5 shows such a de-
fect whose electrical behavior is another unusual feature of open defects. The crack is nar-
row enough to support quantum mechanical electron tunneling when an applied voltage
creates an electric field [3]. Barriers must be on the order of less than 100 Å to support a
probability of significant tunneling. Another study proposed tunneling conduction mecha-
nisms caused by incomplete etching or native (room temperature grown) oxidation after
etching [5].
Tunneling is a quantum effect by which a small particle can cross through a finite po-
tential barrier as a consequence of the wave–particle duality. There are different tunneling
mechanisms, one of which is electric-field dominated. This field-dependent tunneling is
called Fowler–Nordheim tunneling, and the current density Je associated with this mecha-
nism can be quantitatively described by
Je = ␣ · Ᏹ 2 · e–␤/Ᏹ (8.14)
where Je is the current density in A/m2, and ␣ and ␤ are constants depending on the
physical properties of the structures through which tunneling takes place. The electric
field in the metal void depends on the size of the open, the applied voltage, and the mor-
phology.
Figure 8.5. SEM photo of metal tunneling open [3].

c08.qxd 2/2/2004 12:34 PM Page 230
As the crack narrows, direct tunneling increases. The direct tunneling current relation
to the electric field is more complex than Equation (8.14). An important observation is
that metal has a high thermal coefficient of expansion (TCE) so that tunneling efficiency
increases as the metal is heated and expands to close the crack. An IC will show faster op-
eration at higher temperatures when metal cracks are present. No defect-free circuit ever
shows this behavior.
Electron tunneling across opens enables a logic gate to function at low frequencies but
fail at high frequencies, depending on the size of the open. Therefore, detection of these
defects strongly depends on the careful application of speed testing discussed later in
Chapter 10.
왎 EXAMPLE 8.2
A metal-1 line of width 0.3 ␮m has a crack of d = 25 Å located 10 ␮m away

from the transistor gate that the line is driving. The node line has been at 0 V for
a long time, thus completely discharging the transistor gate node. Determine the
final voltage at the transistor gate if the node driver connects its output at VDD for
1 ␮s. Assume that the polysilicon capacitance is negligible and that for this tech-
nology VDD = 3.5 V, metal-1 height t = 5500 Å, Vtn = 0.35 V, ␣ = 1 ␮A/V2, and ␤
= 3 × 108 V/cm.
The initial voltage difference across the crack is 3.5 V, while the crack size is
25 Å indicating that the dominant conduction mechanism will be Fowler–
Nordheim tunneling [Equation (8.14)]. Figure 8.6 illustrates the problem.
Initially, C is discharged and when the node driver switches to a logic 1, the
voltage across the crack is V = VDD. This creates an initial electric field of value
Ᏹ = V/d = 3.5 V/25 Å = 14 MV/cm, which creates a tunneling current that
charges the capacitor and reduces the electric field. Hypothetically, the charging
mechanism would continue until the capacitor is charged at VDD. In practice,
when the voltage across the metal crack goes below around 3 V, direct tunneling
also takes place and Equation (8.14) is no longer valid.
The current through the crack is given by
V2 –␤ · d/V
I = Je · s = s · ␣ · Ᏹ 2 · e–␤/Ᏹ = s · ␣ · ᎏ ·e
d2
where s is the crack section area given by
VDD
+ V -
VDD
I
VO
+
Small Crack Vc C
d = 25 Å
-
GND
Figure 8.6. Tunneling through a metal crack.
c08.qxd 2/2/2004 12:34 PM Page 231
s = w · t = 0.3 ␮m · 5500 Å = 165 fm2
The current–voltage equation at the parasitic capacitor is
冢冣
dVC
I=C ᎏ
dt
since
VDD = V + VC ⇒ VC = VDD – V
then
冢冣
dV
I = –C ᎏ
dt
Equating this current to the current through the crack, the equation describing
the problem is
冢冣
dV V2 –(␤ · d)/V
–C ᎏ = s · ␣ · ᎏ ·e
dt d2
that can be rewritten as
␣·s
冢ᎏ
V 冣冢冣
1 (␤ · d)/V
2
e dV = – ᎏ2 dt
C·d
To solve this equation we define
y = e(␤ · d)/V
and rewrite
␤·s·␣
冢
dy = ᎏ dt
C·d 冣
Integrating
冕
y(t=T)
y(t=0)
␤·s·␣
dy = ᎏ
C·d
冕t=T
t=0
␤·␣·s
dt ⇒ e(␤ · d)/Vf – e(␤ · d)/VDD = ᎏ T冢
C·d 冣
where Vf is the final voltage at t = T = 1 ␮s in this case. The solution is:
␤·d
Vf = ᎏᎏᎏ ␤·␣·s
冤
ln e(␤·d)/VDD + ᎏᎏ T
C·d 冢冣冥
Note that the solution is consistent since for T = 0, Vf = VDD, whereas if T 씮 ⬁,
then Vf goes to zero. Substituting the interconnect and technology values, and
making T = 1 ␮s, Vf = 3.3 V. Since the voltage across the crack is beyond 3 V, the
c08.qxd 2/2/2004 12:34 PM Page 232
equation is valid during the charging process. The voltage at the gate capacitor is
VC = 0.17 V, which is not enough to turn on the nMOS device. 왎
8.2.5 Other Effects

Additional charge components may be present when a floating node due to an open defect
affects a transistor gate. These components come from the charge induced during the fab-
rication processes such as plasma etching or ion implantation. Although this charge can
be removed or masked during subsequent annealing steps, the oxide traps created by these
reactive process steps may manifest later due to hot-carrier injection during circuit opera-
tion [14]. The final trapped charge due to this mechanism depends on the amount of
charge injected during the reactivation process step, the amount of charge removed during
successive annealing, and, finally, the amount of charge trapped in the oxide during circuit
operation. This makes the contribution of these effects on the total charge in the floating
node difficult to compute if an open defect occurs, thus further complicating the exact
modeling of opens in ICs.
8.3 OPEN DEFECT CLASSES
This section organizes the diverse behavior of CMOS open circuit defects into six classes
or models. Each class is described with supporting evidence. The outward effect of an
open defect in an IC can give immediate clues to the type of defect. Importantly, the clues
also eliminate what the possible defect is not. The impact of an open on circuit behavior
depends on the transistors driven by such a floating gate and the gate topology to which
they belong.
Six general classes of opens are identified from failure analysis and test research:
1. Transistor on
2. Transistor pair on
3. Transistor pair on/off
4. Delay
5. Memory (transistor off)
6. Sequential
Although the names are awkward, they roughly describe open defect class behavior. The
first five open categories appear in combinational logic circuits, and in certain instances
in sequential circuit open defect behavior. We will look at each type and the supporting
behavioral data.
8.3.1 Transistor-On Open Defect

An open gate to a single transistor is called a transistor-on defect class, and it has an un-
usual response [1, 2, 7]. Figure 8.7(a) shows a CMOS test inverter whose polysilicon gate
to metal was removed at the mask level. Its static transfer curve is shown in Figure 8.7(b).
Surprisingly, the curve shows functionality despite the loss in noise margin caused by the
shift of the voltage curve to the right [2].
When Vin – VDD Ⰶ Vtp, the pMOS transistor in Figure 8.7(a) turns on strongly into the
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8.3 OPEN DEFECT CLASSES 233
VOUT (V) IDD
5 VOUT
5V 1 mA
4 IDD
3 1 µA
VIN
VOUT 2 1 nA
1
1 pA
0
0 1 2 3 4 5
VIN (V)
(a) (b)
Figure 8.7. Transistor-on open defect class. (a) Open transistor in inverter. (b) Transfer characteris-
tic [2].
nonsaturated state and 5 V is fed to the output drain. The nMOS transistor initially has no
gate drive and is off. When the drain voltage rises and approaches VDD, the DC capacitive
coupling to the nMOS transistor from drain to gate and from gate to source creates a ca-
pacitive voltage divider to the gate. When the capacitively induced voltage at VGSn is larg-
er than Vtn the nMOS transistor turns on, drawing current from the pMOS transistor.
The static transfer curve in Figure 8.7(b) shows Vout = 4.96 V for Vin < 2.5 V in a tech-
nology with Vtn ⬇ |Vtp| ⬇ 0.8 V. Above Vin = 2.5 V, the pMOS transistor begins to turn off,
but charge continues to pass from the output node to the nMOS transistor, as shown by the
IDD curve. Vout drops until the attenuated signal VGSn is below threshold. The nMOS tran-
sistor turns off when Vout ⬇ 1.8 V, and the output node is in a high-impedance state with
slow discharge leakage through the reverse-bias junctions of the MOSFETs. The flat por-
tion of the curve at the lower-right-hand side reflects this slow discharge. Power supply
current is strongly elevated at 96 ␮A for 0 < Vin < ⬇ 2.8 V. It is elevated in only one logic
state, which is typical for many defects that elevate IDDQ. It is important to observe that
contrary to electrical intuition, open circuit defects often elevate power supply current.
왎 EXAMPLE 8.3
The circuit in Figure 8.7(a) approximates the DC conditions of a transistor gate

open. If VDD = 5 V, Vtn = 0.8 V, Vtp = –0.8 V, Kn = 200 ␮A/V2, Kp = 125 ␮A/V2,
W/L = 1, Cgd = 20 fF, and Cgs = 9 fF, what is Vout when the nMOS transistor just
turns off?
冢冣
Cgd
VG = VD ᎏ
Cgs + Cgd
冢冣
Cgs + Cgd
Vout = VD = VG ᎏ
Cgd
Vout = (29/20) × 0.8 V = 1.160 V
왎
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A dynamic transfer curve would include the effects of the Cgd capacitance from the
pMOS transistor. Cgd would allow charge injection quickly out of the output drain node,
causing the voltage on that node to drop quicker. This would tend to shift the voltage
transfer curve to the left of the static curve shown in Figure 8.7, providing some assistance
to the logic change.
8.3.2 Transistor Pair-On and Transistor Pair-On/Off

A wide open-circuit interconnect defect on a logic gate input affects two transistors—the
pMOS transistor and its complement nMOS transistor. Figure 8.8(a) shows such a defect
situation. The affected node floats in a high-impedance state, searching for a voltage that
satisfies its environment. The node electrically lies between VDD and ground coupled by
parasitic capacitances. The local topology will settle the node somewhere between VDD
and 0 V. It is typically not predictable where a floating node finds a steady state value,
therefore we expect a range, and that range has three distinct regions. Figure 8.8(b) illus-
trates the variable region where the floating node can settle. If the gate floats to a value in
region B, then both transistors turn on, V0 is at a weak stuck voltage, and quiescent power
supply current IDDQ is elevated.
If the node voltage is near the power rails at a value outside region B, then only one
VVDD
DD
Large
Large
Open
Open
VVINin VVfG
fG
VVOO
GND
GND
(a)
nMOS pMOS
VDD
AA VDD +Vtp
VfG VDD A On Off

AB
VDD+Vtp
Vtn
V fG C B On On
BC GND
Vtn
C C Off On
GND
(b)
Figure 8.8. Transistor pair on and pair on/off open defects. (a) Large open defect and (b) its float-
ing gate voltage range.
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IDDQ (A) V OUT (V)
1E-2 A 5.0 A = 2039 µm from cell

B = 140 µm " "
C = 15 µm " "
decade/div IDDQ VOUT
0.5 / div D = cell boundary
E = M1 via to poly
B
C
D E
1E-2 0
0 1 2 3 4 5
V IN (V)
Figure 8.9. Floating node response to decreasing gates capacitance (A–E) [2].
transistor is on and the other off (regions A and C). V0 is then a strong stuck voltage, and
IDDQ is not elevated in regions A and C. Thus, a wide open defect to a logic gate can cause
(1) a weak stuck voltage and IDDQ elevation (transistor pair on), or (2) a strong stuck volt-
age and no IDDQ elevation (transistor pair on/off). The table in Figure 8.8 summarizes this.
Supporting data for these two open defect classes are shown in Figure 8.9 [2]. Points
A–E are results from five CMOS inverter test structures in which the length of the metal
interconnect floating node to the inverter was varied from 2039 ␮m (A) down to an open
polysilicon gate to metal missing contact (E). The longer floating metal structures had a
larger capacitance to ground, pulling the floating gate voltage lower (an effect similar to
the one analyzed in Example 8.1).
The measured output voltages and IDDQ were superimposed on a normal inverter trans-
fer curve from the same die to estimate the floating gate voltage on the x-axis. Experi-
mental points A–D are measured from transistor pair on open defects (region B in Figure
8.8) and Point E is a transistor pair on/off defect (region A in Figure 8.8). Circuits A–D
showed weak stuck output voltage behavior and significant elevated IDDQ. Circuit E
showed strong stuck output voltage behavior and no IDDQ elevation. The floating gate volt-
age for structure E was VGfl ⬇ 4.8 V. This turns off the pMOS transistor clamping Vout at 0
V. These distinctions are important when understanding symptoms in failure analysis or
devising test detection methods.
왎 EXAMPLE 8.4
Assume that the two open defects in Figure 8.10 lie (a) 50 ␮m to the right and (b)
50 ␮m to the left of the lower-left node. What electronic behavior differences
would you expect?
The defect in Figure 8.10(a) affects one transistor. It is a transistor-on defect
whose response is linked to capacitive coupling between its drain and source. It
will probably pass a functional test, but have elevated IDDQ in one logic state (AB
= 10). Figure 8.10(b) shows a transistor pair on or pair on/off defect. If the tran-
sistors connected to node B float between the threshold voltages, then IDDQ will
c08.qxd 2/2/2004 12:34 PM Page 236
VDD VDD
C C
A A
B B
(a) (b)
Figure 8.10. Open defect difference. (a) Open defect to transistor gate. (b) Open defect
to logic gate.
elevate, and a weak stuck VC appears for the AB = 10, 11 states. If the floating
nodes clamp hard to one of the rails, then IDDQ is not elevated and the output is a
strong stuck voltage. 왎
8.3.3 The Open Delay Defect

This effect was discussed earlier in the chapter where tunneling was the main conduction
mechanism through the open [3]. Figure 8.11 shows an equivalent circuit with a tunneling
current density Je crossing the crack. ICs with these defects can operate into the hundreds
of MHz, depending on the small dimension of the crack.
This metal defect has an interesting temperature property that relates to test and failure
Je VDD
VIN VfG
VO
Small
Crack
GND
(a)
VIN
V
VO
t
(b)
Figure 8.11. (a) Tunneling open and (b) response to electron tunneling.
c08.qxd 2/2/2004 12:34 PM Page 237
analysis. When metal is cooled, it contracts and the crack widens. Fewer tunneling elec-
trons are supported, and the maximum operating frequency drops. This is an unusual
property for an IC since, normally, ICs increase their maximum operating frequency as
the circuit is cooled. It is a clue to the presence of incomplete metal arising, perhaps, from
stress voiding, electromigration, or a flaw in fabrication to a via or contact. These defects
are often referred to as tunneling defects. They can be difficult to detect in test or locate in
failure analysis. Resistive interconnect opens (specifically, high-resistive vias) are dis-
cussed further in Chapter 9, as they are also classed as parametric delay defects.
8.3.4 CMOS Memory Open Defect

Figure 8.12 shows a 2NAND with an open defect in a pMOS transistor source—no cur-
rent can pass through this transistor. The truth table in Figure 8.12 shows correct logic re-
sults for the first two rows. These are expected. When AB = 00, both n-channel pull-down
transistors are off, and the good p-channel transistor pulls the output to a correct logic
one. When AB = 01, the pull-down transistor is again blocked, but the good p-channel
transistor pulls node C to a correct logic one. However, row 3 gives a correct result that is
subtle. The AB = 10 puts node A in a noncontrolling logic state, but the result seems to de-
pend on conduction through the defective pMOS transistor. The reality is that the AB = 10
vector puts the output node in a floating or high-impedance state, and there is no outlet for
rapid discharge of its high logic voltage charge from the previous logic state. The previous
logic high state was stored in the load capacitance CL and a correct value was read. The
fourth vector AB = 11 pulls node C down to its expected 0 V.
This is a dramatic defect causing no error even though the logic gate was stepped
through the whole truth table, and one transistor was incapable of conduction. The same re-
sult would have occurred if the defective transistor were removed from the circuit. The clue
to potential error is the sequence of vectors. If the AB = 11 state was followed by the AB =
10 state, then an error of 0 V is measured on the second vector (last two rows in table).
We could examine an IC for this defect by testing each transistor with a sequence of
A B C
VDD
0 0 1
VDD
0 1 1
C 1 0 1
A C
CL 1 1 0
A CL
B M M M
B
1 1 0
1 0 0
Figure 8.12. Stuck-open defect.

c08.qxd 2/2/2004 12:34 PM Page 238
two-vectors [15]. This test may become numerically intractable for large circuits not de-
signed for easy testing. Design for testability (DfT) circuits such as the scan circuits de-
scribed in Chapter 10 partition the larger circuit into smaller combinational logic blocks.
In this case, two-vector-sequenced patterns may be feasible.
Figure 8.13 shows a logic gate output voltage and IDDQ timing response when a memo-
ry defect was placed in its high-impedance state at room temperature [13]. The circuit was
a 2NOR driving a ROM row decoder inverter whose V0 node was probed. At t = 12 s, the
circuit was put in the high-impedance state of the memory defect. The output voltage
shows a drift and change in logic state over about 6–8 s. This altered logic state under nor-
mal operating conditions might occur many millions of clock cycles after setting the high-
impedance state.
IDDQ responds with about a 200 ms step followed by instability to about 30 s and then a
slow decline. IDD(t) reflects the biasing of one or more transistors as the floating node
drifts through a range of values. In practice this defect is usually caught by an accidental
sequence of voltage-based test patterns or by IDDQ as shown here. The memory defect is
difficult for test detection and failure analysis.
8.3.5 Sequential Circuit Opens

Figure 8.14 shows several wide open circuit defect locations in a sequential circuit. Open-
1 (O1) affects the nMOS and pMOS transistor gates of the two transmission gates. O1 will
cause those nodes to float to the same voltage. If the node floats to an intermediate volt-
age that turns on the n- and p-channel transistors, then the latch loses its signal isolation.
Transistor contention or conflict occurs since both transmission gates are always on. The
incoming signal conflicts with the stored feedback signal 苶 Q. The latch will functionally
fail, and IDDQ will elevate during contention.
If the O1 node floats to near VDD, then the n-channel pass transistor is permanently on,
and the p-channel transistor is permanently off. The feedback transmission gate still
works with a single n-channel pass transistor, but conflict again occurs when the input
transmission gate is supposed to be off. A similar situation occurs when the O1 node floats
near ground. The p-channel transistor of the feedback transmission gate is always on, and
the n-channel transistor of the input transmission gate always off. Signal contention oc-
IDD V O (V)
10
10 mA I DD
8
1 mA 6
4
1 µA
VO 2
1 nA 0
0 24 48 72 96 120
T ime ( s )
Figure 8.13. Timing response of 2NOR memory open defect [13].

c08.qxd 2/2/2004 12:34 PM Page 239
REFERENCES 239
O2
Signal Q
O3
Q
O5
O4
O1
Figure 8.14. Open circuit defects in a sequential circuit.
curs when the feedback transmission gate is supposed to be off. IDDQ elevation and signal
error occur during the contention. The transistor contention is between one of the transis-
tors of the second inverter (Q 苶) through the transmissions gates to the transistors driving
the signal input.
Defect O2 will float the input to the inverter when the feedback transmission gate is off
and the response will be a transistor pair on or pair on/off. The returned signal in the latch
will alter the floating node voltage and try to drive it to a strong voltage when the CLK
signal turns on the latch T-gates. When the latch T-gate is off, then the floating node will
again seek its steady-state level. The latch is dysfunctional with O2 and an error is detect-
ed when applying a functional voltage test. IDD may or may not be elevated. Defect O3
also gives a response similar to that described for transistor pair on or pair on/off; the latch
is again dysfunctional.
Defect O4 exhibits the transistor-on open response of Figure 8.14 that should elevate
IDDQ, and it may or may not fail a functional test. O5 opens the pMOS transistor so the T-
gate will pass weak logic low voltages and unattenuated logic high voltages. Overall, the
open circuit responses in the flip-flop are similar to the open behaviors described in Sec-
tion 8.3. The failing symptom can be either that of a functional (voltage-based) test or an
IDDQ failure, or both simultaneously. All these defects affect the critical setup and hold
times.
8.4 SUMMARY
The variety of open circuit responses is due to the sensitivity to (1) open defect location
(drain, source, gate), (2) open to logic gate input, (3) sequential circuit, or (4) narrow
cracks in flat metal or vias. Local topography determines capacitive coupling, and temper-
ature changes will affect the dimensions of some opens. Although these responses are
more complex than bridging defects, they are electronically understood so that later we
can intelligently apply test methods that target each form of open circuit behavior.
REFERENCES
1. V. Champac, A. Rubio, and J. Figueras, “Electrical model of the floating gate defect in CMOS
IC’s: Implications on IDDQ Testing,” IEEE Transactions on Computer-Aided Design of Integrat-
ed Circuits and Systems, 13. 3, 359–369, March 1994.
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2. C. Hawkins, J. Soden, A. Righter, and J. Ferguson, “Defect classes—An overdue paradigm for
testing CMOS ICs,” in IEEE International Test Conference (ITC), pp. 413–424, October 1994.
3. C. Henderson, J. Soden, and C. Hawkins, “The behavior and testing implications of CMOS IC
Open Circuits,” in IEEE International Test Conference (ITC), pp. 302–310, October 1991.
4. S. Johnson, “Residual charge on the faulty floating gate MOS transistor,” in IEEE International
Test Conference (ITC), pp. 555–560, October 1994.
5. J. Li and E. McCluskey, “Testing for tunneling opens,” in IEEE International Test Conference
(ITC), pp. 85–94, October 2000.
6. T. Miller, J. Soden, and C. Hawkins, “Diagnosis, analysis, and comparison of 80386EX IDDQ
and functional failures,” IEEE IDDQ Workshop, Washington D.C., October 1995.
7. W. Maly, P. Nag, and P. Nigh, “Testing oriented analysis of CMOS ICs with opens,” in Interna-
tional Conference on Computer Aided Design (ICCAD), pp. 344–347, 1988.
8. M. Renovell and G. Cambon, “Electrical analysis and modeling of floating-gate fault,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11, 1450–1458,
Nov. 1992.
9. M. Renovell, A. Ivanov, Y. Bertrand, F. Azais, and S. Rafiq, “Optimal conditions for Boolean
and current detection of floating gates,” in IEEE International Test Conference (ITC), pp.
477–486, October 1999.
10. W. Riordan, R. Miller, J. Sherman, and J. Hicks, “Microprocessor performance as function of
die location for a 0.25 ␮m five layer metal CMOS logic process,” in International Reliability
Physics Symposium (IRPS), pp. 1–11, April 1999.
11. R. Rodriquez-Montanes, J. Segura, V. Champac, J. Figueras, and A. Rubio, “Current vs. logic
testing of gate oxide shorts, floating gates, and bridging failures in CMOS,” in IEEE Interna-
12. A. Singh, H. Rasheed, and W. Weber, “IDDQ testing of CMOS opens: An experimental study,” in
13. J. Soden, R. Treece, M. Taylor, and C. Hawkins, “CMOS IC stuck-open fault electrical effects
and design considerations,” pp. 423–430, in IEEE International Test Conference (ITC), pp.
302–310, August 1989.
14. R. Tu, J. King, H. Shin, and C. Hu, “Simulating process-induced gate oxide damage in circuits,”
IEEE Transactions on Electron Devices, 44, 9, 1393–1400, September 1997.
15. R. Wadsack, “Fault modeling and logic simulation of CMOS and MOS integrated circuits,” Bell
Systems Technical Journal, 1449–1488, May-June 1978.
EXERCISES
8.1. Observe the schematic and transfer curve in Figure 8.7. Would the shape of the
curve change if the input were swept from Vin = 5 – 0 V instead of being swept from
Vin = 0 – 5 V as shown in Figure 8.7(b)?
8.2. A 2NOR gate has an open defect in one of the pull-down source leads (Figure 8.15).
Verify whether this defective circuit will
(a) Correctly pass an ordered truth table beginning with 00
(b) Correctly pass an ordered truth table beginning with 11
8.3. The stuck-open fault behavior was described as a behavior related to the parallel
transistors in a logic gate. In theory, a stuck-open behavior can occur in a logic gate
c08.qxd 2/2/2004 12:34 PM Page 241
8.6 EXERCISES 241
VDD
B
Out
Figure 8.15.
series stack of transistors initiated by events occurring during power-up of the cir-
cuit. Figure 8.16 illustrates this with a single series stack (an inverter) in which an
open defect appears in the drain of the n-channel transistor. Describe how a stuck-
open behavior could occur in this series stack circuit.
MP
Vin Vout
MN
Figure 8.16.
8.4. An integrated circuit has the following failure symptoms: It fails a functional
(Boolean) test and IDDQ is elevated. If you suspect an open circuit defect is causing
this, what type of open defect class would it be? Explain.
8.5. An integrated circuit has the following failure symptoms: The maximum clock fre-
quency of the IC declines as the temperature is increased. There is no Boolean fail-
ure at slow clock frequency, nor is there IDDQ elevation. If you suspect an open cir-
cuit defect is causing this, what type of open defect class would it be? Explain.
8.6. An integrated circuit has the following failure symptoms: It fails a functional
(Boolean) test and IDDQ is not elevated. If you suspect an open circuit defect is caus-
ing this, what type of open defect class would it be? Explain.
8.7. A metal-6 interconnect that is 3 ␮m wide has a 27 Å crack located 50 ␮m away

from its end where it goes down to a gate node. Assuming that the floating portion
of the metal is at 0 V, compute the final node voltage when the portion of the line
connected to its driver is settled to VDD during 1 ␮s. For this technology, the metal-
6 height is t = 1.04 ␮m, its capacitance to the substrate is 0.008 fF/␮m, and VDD =
3.5 V. Determine the dominant conduction mechanism and the validity of the equa-
tion used.
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8.8. The dynamic NAND shown in Figure 8.17 has been unpowered for a long time. De-
termine the voltage at the gate of N1 2 ␮s after the signal lines driving the gates of
N1 and N2 simultaneously make a 0 to 1 transition. Assume the technology values
given in Example 8.2 and a crack of 20 Å.
Clock
Metal 1
Lines out
N2
N1
20 Å 10 µm
crack
20 µm
Figure 8.17.
8.9. Two different failure symptoms were found upon speed testing a microprocessor at
30°C and at 100°C. If you suspect an open defect, describe which it might be if:
(a) The parts run faster at 100°C than at 30°C.
(b) The parts run slower at 100°C than at 30°C.
8.10. An ASIC showed peculiar failure symptoms. The failure was isolated to a subcircuit
that failed certain verification tests and not others. It did not seem to make sense.
What type of an open defect might it be?
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CHAPTER 9
PARAMETRIC FAILURES
9.1 INTRODUCTION
Parametric failures are the third and most difficult class of IC failures. They have elusive
properties that may let a CMOS circuit function under specific conditions, but not under
all environmental possibilities. A part may function at certain power supply voltages, but
not over its whole specified VDD range. There can be unusual temperature properties; the
IC may pass a high-speed test at a hot temperature, but fail at a colder temperature. It may
have windows of pass/fail. There are even regions on the Earth where the IC can show dif-
ferent pass/fail properties, such as high-latitude, mountainous regions having high cosmic
radiation.
Parametric failures can be defined as failures due to the variation in one or a set of cir-
cuit parameters such that their specific distribution in a circuit makes it fall out of specifi-
cation. Parametric variation has always been present in digital ICs, but their variance grew
spectacularly in deep-submicron technologies. Parametric failures show two general
forms: one failure form is caused by defect-free (intrinsic) parameter shifts; a second fail-
ure form affects functionality through environmentally sensitive defects on the die (extrin-
sic). The intrinsic failures can be due to physical factors that come from variations in the
electrical and physical parameters of transistors and interconnects, and the failures can
arise from an unfortunate statistical distribution of these parameters. Intrinsic failures can
be also due to environmental factors such as variations in supply voltage and/or tempera-
ture, or due to crosstalk and switching noise influence. These broad failure classes are
called parametric because the intrinsic or extrinsic failures are either due to variation of
IC process parameters, or due to sensitivity to environmental parameters such as power
supply, temperature, clock frequency, and/or radiation.
c09.qxd 2/5/2004 4:51 PM Page 244
244 CHAPTER 9 PARAMETRIC FAILURES
Individual transistor and interconnect parameters vary widely within a die, from die to
die, wafer to wafer, and from lot to lot, making exact transistor drive (speed), and intercon-
nect properties (resistance, capacitance, and inductance) prediction difficult [4, 7, 8, 9, 15,
41, 49]. These variations come from optical effects during lithography patterning process-
es, resulting in wafer images that can be very different from those drawn on the layout. In
particular, optical proximity effects such as pitch-dependent critical dimension (CD) vari-
ation and line shortening can degrade transistor parameters or even lead to catastrophic de-
fects (shorts or opens) when occurring in the polysilicon layer. The loss of pattern fidelity
may happen during mask making, wafer imaging, and/or etch steps. Many researchers have
studied CD variation in polysilicon and interconnect metal lines, and different techniques
such as optical proximity correction (OPC) or phase shift mask (PSM) have been proposed.
These methods require modification of the physical design layout on the photo mask to
compensate for the proximity effects [24], and automated solutions are devised [3].
Although some of the variations can be corrected using OPC, significant discrepancies be-
tween measurements and models even after corrections still exist [35].
Another source of variability in the metal interconnect system comes from chemical-
mechanical polishing (CMP) that has emerged as the primary technique for planarizing
interlayer dielectrics (IDL) [54]. Its present applications include important process steps
like shallow-trench isolation (STI) and multilevel inlaid copper interconnection [24].
However, it has been observed that the post-CMP topography shows an important varia-
tion that is strongly dependent on the layout pattern. This causes certain regions on a chip
to have differences in dielectric layers thickness, depending on the underlying topography
[54]. A method to reduce this layout-pattern-dependent dielectric thickness variation is to
fill large metal-free areas with dummy metal. This extra dummy metal structure changes
the parasitic capacitance of the interconnect system, and may complicate RLC extraction
and impact timing and noise, as explained later in this chapter.
Both sources of variation impact circuit performance and may lead to parametric fail-
ures. Table 9.1 lists several forms of intrinsic and extrinsic parametric failure mechanisms
and the physical effects that may significantly alter circuit speed.
Table 9.1. Parametric Failure Sources and Effects

Failure Mechanism Physical Effect
Intrinsic Process Fabrication Vt shift
Parameter Variation ILD variation
Interconnect ⍀ shift, metal width,
spacing, thickness, granularity
Leff shift
Weff shift
nMOS-to-pMOS length ratio shift
Diffusion resistance
Extrinsic or intrinsic Metal: Resistive metal
Via-interconnect defect;
Electromigration
Stress Void
Oxide: Gate oxide short
Defect or wearout; Hot carrier injection
Hot Carriers
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9.1 INTRODUCTION 245
Parametric failures are typically insensitive to many test methods such as IDDQ, stuck-
at fault, delay fault, or functional tests (these methods will be covered in Chapter 10), and
can emerge as failures in the field [13, 18, 39, 49]. Tim Turner of Keithley Instrument’s
yield test structures group estimates that among the several hundred CMOS process steps,
there are on the order of 10,000 variables that can affect the final performance of an IC
[59]. He refers to interactive effects when two or more variables act in synergy to cause an
IC to go out of specification. These interactive effects are one form of the parametric fail-
ures discussed here.
We emphasize that most of these parametric failures are speed-related, and are not con-
ditions causing DC parametric failures such as I/O pin leakage or continuity. Since para-
metric defects are mainly speed-related failures, they usually require expensive test equip-
ment and fixturing for detection and characterization. The IC maximum operating
frequency (Fmax) or propagation delay times are timing measurements that can indicate
the presence of a parametric failure.
Process-induced parameter variation in IC manufacturing has mainly impacted die-to-
die shifts in the past, and worst-case analysis was enough to predict its impact [37]. In
deep-submicron and nanometer technologies, integrated circuits are large enough that
within-die variations have become as important as interdie ones. These variations have
two components; one is systematic and the other is random. A substantial portion of with-
in-die variations are layout-dependent and, therefore, deterministic. These parameter vari-
ations may not be treated deterministically in many environments due to several reasons
[37]:
앫 The models describing the dependence of a particular parameter on the design may
not exist, be inaccurate, or be too expensive to evaluate.
앫 In the early design cycles, the circuit is described in high levels of abstraction, caus-
ing any interaction with physical implementations to be only estimates.
앫 A reusable design (like an IP core) cannot predetermine the physical design envi-
ronment in which it will operate.
In these cases, the parameter can be effectively treated as random. This characteristic
makes intrinsic parameter variations nonsystematic in circuits fabricated in the same lot,
or even in the same wafer [32, 49]. This leads to inaccuracies that impact circuit quality,
and can provoke erroneous behaviors that occur at very specific circuit states or environ-
mental conditions. Present design technology is unable to characterize the whole com-
plexity of parameter combinations, so that present strategies usually characterize only the
corner parameters. Therefore, unfortunate parameter combinations can be very difficult to
detect and screen. For example, an IC that is normally on the fast edge of the distribution
could have a delay defect that puts it at the slow edge, but in an acceptable range, so the
part passes. Defective parts that pass function tests are an increased reliability risk. Rior-
dan et al. measured over one million ICs and reported Fmax as a function of wafer location
and yield [44]. This is an example of the uncontrollable parameter variations that affect
performance.
Another source of uncertainty arises from the rapid picoseconds of signal rise and fall
times of intrinsic nanotechnology ICs. This can cause specific noise mechanisms such as
crosstalk or switching noise (these mechanisms are discussed later) that may lead to tim-
ing errors with associated Boolean upsets that may not be systematic for circuits manu-
factured from the same design. Although crosstalk and switching noise are traditionally
categorized as design-related problems, technology-scaling complexity has diffused the
c09.qxd 2/5/2004 4:51 PM Page 246
boundaries between design and functionality, so that designers must take statistical varia-
tion into account in their designs [33].
Production ICs are characterized by measuring speed performance at different environ-
mental conditions. Since there are many sets of conditions with which to do this, one effi-
cient practice is to characterize performance at two sets of power supply voltage and tem-
perature maximum and minimum points. These two sets are done at high (H) and low (L)
VDD and T, and are designated VLTH, and VHTL [9]. The speed performance of the IC will
vary from slowest at VLTH to fastest at VHTL. Process variation may affect corner values
through parameters involving transistors and interconnects, so that some circuits from the
same fabrication lot fail, while others do not.
If parametric failures sound difficult, you are correct. When the failure analysis lab
characterizes these failures, they often find that we lack the technology to economically
detect them at the test and failure analysis stages. Several failure analysis experiences
with parametric delay defects showed that one to three months of effort may be necessary
to locate one defect in an IC. This is intolerable, and research efforts are currently directed
at more efficient location techniques [10, 18].
There is presently no unified view of what must be considered within the umbrella of
parametric failures. The material collected in this chapter does not pretend to define any
new effects under a given defect class, but intends to organize and structure a number of
“deviations” that have not previously been systematically categorized.
We will next detail three distinct origins of parametric failures. The first describes
these origins as they relate to fabrication process variations that affect IC performance.
Data are shown to illustrate how these parametric failures impact the speed capability of
individual transistors and ICs. The next section describes parametric failures due to inher-
ent noise generation within the chip. The final section describes how certain defects cause
parametric failures.
9.2 INTRINSIC PARAMETRIC FAILURES
Two factors cause intrinsic parameter variation: environmental and physical [15]. Envi-
ronmental factors include variation of the power supply levels within the die, or on the
board, or switching activity and temperature variation across the circuit. Physical variation
comes from the inherent weaknesses in circuit manufacturing that allow transistor and in-
terconnect structural variations. These deviations from targeted values are limitations or
imperfections in process and mask steps.
9.2.1 Transistor Parameter Variation

Individual transistor parameters vary widely within a die, die to die, and lot to lot, making
transistor drive (speed) prediction difficult. The main parameters that determine the tran-
sistor drive properties are [7, 15]:
앫 Channel length variation

앫 Channel width variation
앫 nMOS-to-pMOS length ratio variation
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9.2 INTRINSIC PARAMETRIC FAILURES 247
앫 Effective gate oxide thickness variation

앫 Doping variation—threshold voltage and diffusion resistance
These parameters directly modulate two of the most important speed parameters of the
device: the drain saturation current (IDsat) and the threshold voltage (Vt). Vt and IDsat are
interrelated, and have a significant impact on the delay of the logic gates in the IC.
Subthreshold leakage current (Ioff) is another electrical parameter that is affected, and is
now significantly elevating static power dissipation levels in modern submicron tech-
nologies.
Channel Length Variation. Channel length has a first-order influence on transistor de-
lay, and thus on circuit performance. The MOSFET model equations given in Chapter 3
show that effective channel length (Leff) lies in the denominator of the drain current expres-
sion. As Leff gets smaller, drain current rises, and load capacitances can be charged and dis-
charged faster. Channel length variations also directly impact the threshold voltage, reduc-
ing Vt as Leff gets smaller. Channel length variations are due to a combination of
photolithography, gate etching, ion implant, spacer formation, and thermal processing ef-
fects. Present limitations in optical photolithography make the variance worse as technolo-
gies scale to 90 nm and below. Bernstein et al. presented data showing that variation in Leff
has the greatest affect on IC performance compared to other process parameters [7].
Channel Width Variation. Channel width variation has a second-order impact on de-
vice switching speed, but is important in minimum-width devices due to narrow-channel
effects. The main narrow-channel effect is that the transistor effective threshold voltage
varies across the transistor width, changing from the nominal value at the center region to
an altered value toward the device edge. The shift in threshold voltage may be positive or
negative depending on the technique used to isolate the device. The main techniques are
“local oxidation of silicon” (LOCOS) and “shallow trench isolation” (STI). LOCOS pat-
terns silicon dioxide areas that isolate adjacent devices, and was the dominant technique
until shallow-trench isolation was adopted. In general, LOCOS shifts the threshold volt-
age positive, whereas STI tends to decrease the effective Vt at the edges.
The narrow-width effect is typically seen for channel widths ⱕ 0.4 ␮m. This means
that the effect will influence the 180 nm technology when transistor W/L ratios are ⱕ 2.
The effect on Vt occurs more often for 130 nm, 90 nm, and below since more transistors
have widths below 0.4 ␮m. It is difficult to compensate for this narrow-width modulation
on Vt since it implies that different doping implants be done for transistors that are scat-
tered across the die.
nMOS to pMOS Length Ratio Variation. This variation is important in ICs that use
ratioed logic styles. The width-to-length aspect ratio between nMOS and pMOS transis-
tors determines the noise margins and switching point of the logic gates. The channel
length variation attributed to the two types of devices may come from implant dose, ener-
gy, and diffusion tolerances of the dopants associated with the different MOSFET types
[7]. Bernstein et al. offered guidelines that nMOS-to-pMOS transistor tracking tolerance
is about 10% of measured length and that nMOS-to-pMOS IDsat ratios can vary by ± 10%
[7]. This statistically modulates the individual gate-voltage transfer curves, affecting pull-
up and pull-down speed and noise margins.
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Effective Gate Oxide Thickness Variation. Gate oxide thickness has a first-order
impact on device performance, directly affecting transconductance, threshold voltage, and
device drive current. Gate oxide physical thickness variance is related to the tolerance of
the thermal growing process. Analysis of the oxide thickness must distinguish between
physical and electrical equivalent insulator thickness [7]. The electrically equivalent insu-
lator thickness of the oxide takes the polysilicon gate depletion into account, since its
depth is no longer negligible in front of the oxide physical thickness. Gate oxide variation
occurs across wafer lots over an extended period of time, whereas little variation is typi-
cally observed across a given wafer. In modern processes, this variation is kept below
0.5% of the effective oxide thickness. However, for the ultrathin oxides, ⱕ 25 Å, the SiO2
molecules show surface monolayers about 3.5 Å thick. The absence or presence of a por-
tion of a monolayer can cause Tox to discretely vary by 15–20% in local oxide regions
[11], as shown in Figure 9.1. This figure shows the crystalline silicon, the amorphous
SiO2, and the polycrystalline gate material.
Random Doping Fluctuations. Doping variations may differ even for devices in the
same die and are due to variations in the implant dose, angle, or energy. These variations
change the junction depth and doping profiles that impact the effective channel length and
threshold voltage. The angled halo doping implant technologies used in modern submi-
cron technologies to reduce short-channel effects further increase parameter variations
since the angle of implant is critical.
Another performance noise source that impacts the threshold voltage is related to the
distribution of dopant atoms. A variation in doping density beneath the gate makes local
threshold voltage uneven under the gate. Also, short-channel effects are controlled if sub-
strate doping density is larger near the drain. This suppresses pn junction depletion width.
When variations occur here, the drain-induced barrier lowering (DIBL) reduces the tran-
sistor threshold voltage.
This effect is starting to be identified in SRAM circuits, and is expected to increase in
importance [15]. For small devices on the order of 100 nm and less, it is possible to track
the locations of silicon and dopant atoms, considering the impact of their distribution on
Figure 9.1. Gate oxide photo of a 27 Å oxide showing thickness variation. (Reproduced by permis-
sion of Doug Buchannan, IBM Corporation.)
c09.qxd 2/5/2004 4:51 PM Page 249
the device behavior. A detailed study on 25 nm devices quantified the magnitude in

threshold voltage variation, reporting a Vt uncertainty of 10/W1/2 (mV/␮m1/2) (W being
the width of the device) [23].
9.2.2 Impact on Device Intrinsic Electrical Properties

The parameter variations listed earlier cause fluctuations of drain saturation current,
threshold voltage, or both, in devices from the same circuit. The transistor effective length
Leff and threshold voltage Vt are the main parameters that determine current drive and,
therefore, the circuit clock speed. These parameters relate to each other in deep-submi-
cron technologies such that the effective transistor length and width impact the Vt value.
The threshold variation modulates off-state current, impacting the static power consump-
tion that is increasingly important in high-performance applications.
Transistor Threshold Voltage ( Vt ) Variation. Figure 9.2 shows threshold voltages

measured for transistors designed with two different target channel lengths; the inset illus-
trates the threshold voltage dependence with the effective transistor length. The spread in
effective transistor length is typical of parameter variations in submicron technologies.
Ideally, since all devices are designed to have one of two target transistor lengths, only two
points should appear in the graph. In practice, the spread in transistor effective length
translates to a spread in device threshold voltages and circuit speed performance.
Figure 9.3 shows threshold voltages measured in 4,000 devices with different sizes and
Vt adjustments using superretrograde halo implants to control Vt for these devices. Square
devices were designed with large, equal L and W values, whereas the small devices target
smallest length and width for that technology. Narrow devices were designed for mini-
mum width and large length, whereas short devices refer to wide devices with minimum
transistor length.
Short devices show a mean transistor target threshold voltage of about 350 mV, but
width reduction (when moving from short to small devices) provides a mean Vt of about
500
500
n
o
400
400
r
Normalized m
Vt (mV) a 300 300 Vt Less Ioff
li
z200200 Higher Ioff
e
d Leff
V100100
t 100
100 120
120 140
140 160
160 180
180
( normalizedLe (nm)
m Normalized Leff (nm)
Figure 9.2. Measured transistor threshold voltages for two set of nMOS devices with differently
designed channel lengths. The inset plot shows the Vt roll-off dependence with the effective transis-
tor length [31].
c09.qxd 2/5/2004 4:51 PM Page 250
400
Short
300
Small
Normalized
200 Square
Vt (mV) length
100 Narrow
width
0
0 1000 2000 3000 4000 5000
Device Number
Figure 9.3. Measured threshold voltages for four sets of nMOS transistors. Square refers to transis-
tors designed with large length and width, whereas small refers to devices with minimum length and
width. Short devices are wide minimum length transistors, whereas narrow transistors have large L
and small W [49].
300 mV due to STI. This widens threshold voltage variations, since Leff and Weff varia-
tions are worsened for minimum dimensions. Square test devices have a small spread in Vt
so that the impact of process variation in large-sized devices (both length and width) is
smaller. The lowered Vt value of the square and narrow transistors is due to the superretro-
grade halo implant effect on a large-dimension transistor.
The short and small transistors are the typical geometries expected in digital ICs, for
which the W/L ratio varies from unit size to integer values from 2–20 (and larger for
buffer drivers). The short devices are typically the targeted threshold voltages for the tran-
sistors of the IC. As technology nodes go from 130 nm to 90 nm and below, the number of
transistors affected by the narrow width Vt reduction effect increases since this effect typ-
ically occurs for transistor widths below 0.4 ␮m. We emphasize the significant variation
when the channel lengths or widths are taken to their minimum dimension.
Figure 9.4 shows the 3␴ variation of transistor threshold voltage at three technology
nodes. Variation ranges from 12% at the 360 nm die to more than 29% for the 180 nm die
[36]. Figure 9.5 shows the percentage of Vt variation within the die for three technologies,
showing that at 130 nm, the variation in Vt is markedly increased. This occurs while the
absolute value of threshold is reduced from about 0.45–0.4 V at the 0.23 ␮m and 0.18 ␮m
nodes, respectively, to about 0.3 V at the 130 nm node [36].
Impact on IDsat. Transistor Leff intrinsic variation is the primary variable that influences
Fmax [7]. Keshavarzi et. al., also presented Leff variation data and its impact on IDsat, which
is the transistor speed parameter [31]. Figure 9.6 plots transistor drain saturation current
versus device threshold voltage [31]. IDsat measures the current drive of a transistor in the
saturation region, reflecting its ability to drive load capacitance during logic transitions.
This graph illustrates how threshold voltage fluctuations translate to the transistor satura-
tion current and circuit operation speed.
Transistor length variations impact circuit operation speed not only through Vt varia-
tions, but also directly, as was shown in the device model equations discussed in Chapter
c09.qxd 2/5/2004 4:51 PM Page 251
40
voltage variation (mV)

30
3␴ threshold
20
10
0
0.18 0.36 0.72
L (µm)
Figure 9.4. 3␴ variation of transistor threshold voltage at three technology nodes [36].
12
% Vt Variation (%)
0
0.13 0.18 0.23
Te chnology Ge nertion (µm)
Figure 9.5. Threshold voltage variation within the die [36].
0.6
0 .6
0.5
0 .5
Normalized
IDsat (mA/µm) 0.4
0 .4
0.3
0 .3
0.2
0 .2
100
100 200
200 300
3 00 400
4 00 500
500
Normalized
n o r m a liz e d VV
t ( m(mV)
t
V)
Figure 9.6. Relationship between transistor threshold voltage and drain saturation current IDsat[31].
c09.qxd 2/5/2004 4:51 PM Page 252
3. Figure 9.7 shows this length effect in the saturated drain current versus the transistor ef-
fective length plot. Again, the spread in IDsat is an indication of device-to-device variation
in speed capability.
Impact on Ioff. Leakage or off-state current is another important transistor parameter,

since it directly relates to the total static dissipation power at the IC level. Ideally, noncon-
ducting transistors should pass negligible current. However, a characteristic of submicron
technologies is an increase in subthreshold current due to the reduced transistor threshold
voltages required to maintain performance when the supply voltage is lowered (see Chap-
ter 3). Transistor length has a first-order impact on the device subthreshold current,
threshold voltage modulation, and IC speed performance.
Figure 9.8 plots transistor intrinsic leakage current versus the inverse of the linear
drain current (1/IDlin, an indicator of Leff) for two groups of devices designed with differ-
ent target effective lengths. It shows the dependence of the subthreshold current on the
transistor effective length. The spread of the effective transistor length induces changes in
the leakage current of about one order of magnitude between target or nominal Leff (Lnom)
and worst-case Leff (Lwc). The impact of subthreshold current variation on main circuit pa-
rameters and its implication for test technology are described in detail in the next chapter.
These data illustrate the manufacturing variation that we expect in modern transistor
parameters. The variations are larger than in the past, so that overall IC performance also
has wider variation. This increased variance property of modern ICs profoundly affects
testing, since testing traditionally assumes a single test limit. We might say that “modern
dies won’t hold still.”
9.2.3 Line Interconnect Intrinsic Parameter Variation

Traditionally, device and design engineers target transistor drive strength and reduced in-
put capacitance as the most effective ways to improve IC performance. Transistor parame-
ter variance was the dominant statistical influence on speed in older technologies, but a
worse statistical influence on speed failures now comes from the interconnections. The
smaller interconnect sizes and increased packing density of deep-submicron technologies
0.6
0. 6
0.5
0. 5
Normalized
IDsat (mA/µm) 0.4
0. 4
0.3
0. 3
0.2
0. 2
100 100 120

120
140
140 160
1 60 180
1 80
n o r m a liz e d L e ( n m )
Normalized L eff (nm)
Figure 9.7. Measured saturation current values for two groups of nMOS transistors with two sepa-
rately designed transistor lengths [31].
c09.qxd 2/5/2004 4:51 PM Page 253
-5
10
150 n m te chno logy 110 C
V D=1V
-6
10
Intrinsic Ioff (A) 10

-7
10-8
L wc
10 -9 L nom
500 2000 2500 3000 3500

<- Shorter L 1/IDlin
Figure 9.8. Transistor leakage current versus 1/IDlin for a 150 nm technology showing worst-case
(Lwc) and nominal (Lnom) channel length values. (Reproduced by permission of Intel Corporation.)
add line resistance and cross-couple capacitance that make metal statistical distribution
equally if not more important than transistors [56]. Additionally, the increasing clock
speed and length of selected global interconnect lines (clock distribution and buses) make
inductive effects important not only at VDD and GND, but also in signal lines.
Parasitic capacitance, resistance, and inductance effects in IC interconnections depend
on the driver and line characteristics that determine the signal properties traveling the line.
The statistical fluctuation of device and interconnect characteristic parameters combine to
impact delay variation and noise fluctuation that can lead to incorrect, unpredictable be-
haviors.
Interconnection coupling is the source of undesired noise called crosstalk and/or
switching noise. These mechanisms are discussed later. Analysis of crosstalk and sup-
ply/ground bounce and their effects on ICs for half-micron and larger technologies are un-
derstood. There are even CAD software tools that take these effects into account and assist
in preventing circuit malfunctions at the design stage. The crosstalk and supply/ground
noise that affect deep-submicron technologies also relate to parameter fluctuation and de-
sign, similar to that of the transistors. The intrinsic variation of the fundamental parame-
ters that determine these noise-related effects at the interconnection (as parasitic resis-
tance, capacitance, and inductance) and device level (as driver strength) may cause
well-designed circuits to fail due to parameters lying at process corners.
Figure 9.9 shows two cross sections of ICs with six and eight levels of metal. Lower
metal levels are used for local interconnect and power distribution of custom logic cells
that require high density to minimize area and achieve high clock frequency. The upper
metal layers are typically used for the global VDD, GND, clock, and control lines. The low-
er-level metal lines and vias lie closer to each other since they have minimum width. No-
tice the different aspect ratios (H/W) between 2–3 and the pitch of the vias and contacts.
Each technology node has a minimum metal width of about that technology node number.
A 90 nm node has a minimum metal width of about 90 nm [28]. The dielectric spacing be-
c09.qxd 2/5/2004 4:51 PM Page 254
(a) (b)
Figure 9.9. Cross section of an IC with (a) six [60], and (b) eight metal levels. (Reproduced by per-
mission of Bob Madge, LSI Logic.)
tween minimum metal geometry is also about 90 nm. The vias and contacts have diame-
ters on the order of the metal widths, and since the intermetal level dielectric vertical
spacing scales more slowly, the via and contact aspect ratios tend to get larger. Via aspect
ratios between 5–10 are used on modern ICs that have hundreds of millions or billions of
these structures, and defect-free vias cannot be guaranteed. Vias and contacts are a diffi-
cult challenge for fabrication, test engineering, and failure analysis.
Figure 9.10 shows the lower two metal layers of a large microprocessor die. The upper
layers of metal interconnect were etched off. Metal–1 is tungsten, and metal-2 is copper.
The narrow, high-aspect-ratio lines on metal-1 and metal-2 are for local signal connection
of drains, sources, and gates. The small cross sections result in line resistances that can
range from 1000 ⍀/cm to 3000 ⍀/cm even for higher-conductivity copper metallization
[22]. The higher-aspect signal lines show the trend that lateral area capacitance is larger
Figure 9.10. First two metal layers in a microprocessor IC. (Reproduced by permission of Chip-
works Inc.)
c09.qxd 2/5/2004 4:51 PM Page 255
than vertical area capacitance. This increases crosstalk while still providing a load capaci-
tance. Lateral signal coupling capacitance depends on the design spacing, the metal length
and height, the dielectric material, and the statistical variation. The longer flat lines in Fig-
ure 9.10 are power and GND interconnections, and it is here that power line inductance
can cause problems. Signal-induced current surges raise the GND voltage, and lower the
VDD rails due to induced Ldi/dt changes. The 90 nm and 60 nm nodes are increasingly at
risk if crosstalk from narrow spacing is not characterized and controlled [22]. The power
lines have more horizontal surface area so their major capacitance is at top and bottom.
Higher capacitance in VDD and GND lines is usually a good feature, since it helps buffer
the power lines against transient voltage changes.
The 10–30 ps rise times of modern ICs aggravate these inductive and capacitive con-
ditions, causing increased noise and transient errors. Induced timing delays and
speedups can result from these phenomena as well as from large surges induced by the
simultaneous switching of large output buffers (⌬I noise). Figure 9.10 illustrates the R,
L, and C parametric complexity of modern IC interconnections and via/contact metals.
This complexity is aggravated by the dummy metal structures added to meet density re-
quirements.
Process variations can induce worst-case sheet resistance fluctuation ranging from
10% in metal lines to about 38% in polysilicon, as reported for a 0.8 ␮m CMOS process
[38]. Line width metal variations of about 10% and area capacitance variations from 17%
to more than 25% were measured for intermetal lines. These parameter fluctuations were
measured in a 0.8 ␮m process, but deep-submicron processes have larger process-induced
variation, especially below 180 nm.
In summary, we saw that significant variations occur in Vt, Leff, Weff, IDsat, Ioff, and in-
terconnect capacitance and resistance. These variations translate directly to performance
and potential failures of the ICs. This is the new reality of dealing with deep-submicron
circuits and that is what this chapter is about.
9.2.4 Temperature Effect

Temperature impacts the electrical properties of both devices and transistor interconnects,
although devices are more sensitive to this parameter. Carrier mobility and threshold voltage
are the two transistor parameters most impacted by temperature, and their dependencies have
compensating effects. Mobility decreases with increasing temperature, as moving carriers
experience more collisions with the Si-crystal lattice whose vibration thermal energy gets
higher with temperature. The effective mobility in the inversion layer can be expressed as
冢冣
T –m
␮(T) = ␮(T0) ᎏ (9.1)
T0
where T0 is room temperature (T0 = 300 K) and m is the mobility temperature exponent
that depends on the channel doping, typically taking values between 1.5 and 2.
The temperature dependence of the threshold voltage is of the form
Vt(T) = Vt(T0) – ␣(T – T0) (9.2)
where ␣ is a constant for each scaled technology, and has a typical value of about –0.8
mV/K [31].
c09.qxd 2/5/2004 4:51 PM Page 256
(a) (b)
Figure 9.11. Drain current versus gate voltage for a nMOS transistor at different temperatures. (a)
Shows the drain current in logarithmic scale for the Ioff component; (b) shows the linear dependence
for the saturation current.
The threshold voltage temperature variation mainly impacts the leakage current since
Ioff has an exponential dependence with Vt. The mobility temperature variation has an im-
pact on the transistor drain saturation current. Figure 9.11 shows simulations of the drain
current of a nMOS transistor from a 0.18 ␮m technology in logarithmic and linear scales to
show the variation of the off-state and saturation currents, respectively. Figure 9.11(a)
shows an Ioff reduction of about three orders of magnitude when lowering the temperature
from 120°C to 0°C. Figure 9.11(b) shows that drain current increases when temperature is
lowered, although its variation is not as high as that of Ioff (there is about 15% improvement
in ID when cooling from 120°C to 0°C). The reduced leakage current and increased drain
saturation current gained at lower temperatures makes active cooling a promising technique
for future scaled technologies if power-efficient cooling technologies can be developed.
Figure 9.11(b) shows an interesting common intersection of the lines when tempera-
ture is varied. If the transistor were biased at VGS ⬇ 0.8 V for the given VDS, then drain
current would not change with temperature. Analog designers have long known of this
property. The temperature-invariant intersection is a result of decreased mobility as tem-
perature rises versus the decrease in Vt. The mobility drops, but the gate overdrive voltage
(VDD – Vt) increases in the drain current equation.
Interconnect resistance rises with temperature, thus increasing circuit delay. It has been
reported that in modern fabrication processes, copper has a temperature coefficient of re-
sistivity of 3.6% to 3.8%/10°C [1]. This implies a change of the load resistance with tem-
perature and an impact on delay due to interconnect variation.
9.3 INTRINSIC PARAMETRIC FAILURE IMPACT ON IC BEHAVIOR
Capacitive, resistive, and inductive noise were always present in previous IC technologies,
but were considered design problems due to their systematic and well-characterized low-
c09.qxd 2/5/2004 4:51 PM Page 257
9.3 INTRINSIC PARAMETRIC FAILURE IMPACT ON IC BEHAVIOR 257
impact behavior. As technology scales, more noise sources appear as ICs lose noise mar-
gins. Moreover, the increasing process parameter variations cause larger fluctuations in
the predicted design parameters with technology scaling. Noise is now less predictive,
causing more potential “nonsystematic” circuit malfunctions. This nonsystematic behav-
ior and the growing percentage of circuit malfunctions in current technologies due to
noise-related issues motivated us to categorize these interconnect and/or signal routing
noise sources as parametric failures, as well as design issues.
The impact of device and interconnect parameter variations on noise and delay mecha-
nisms requires knowledge of electrical models and parameters that characterize these ele-
ments. MOSFET behavior and its modeling were covered in detail in Chapter 3. The elec-
trical models that describe the interconnect and related coupling mechanisms are briefly
described in the first part of this section.
9.3.1 Interconnect Models

We introduce the digital IC interconnect models that depend on the characteristics of the
logic gates and the interconnect line parameters. These models will be required later to
understand the effects of signal coupling and noise mechanisms.
Line Capacitance Model. The line capacitance model is a first-order model of the ef-
fects of gate-to-gate delay. The near-infinite resistive component of the MOSFET transis-
tor gate allows us to model the load effect of a CMOS logic gate as a capacitor. One in-
verter driving another inverter [Figure 9.12(a)] can be modeled with the first inverter
driving the equivalent input impedance of the second one, i.e., a lumped capacitor [Figure
9.12(b)]. This has inaccuracies since the input capacitance of a CMOS gate changes with
the applied bias (Chapter 3). However, the lumped capacitor load can be computed from
the various components of the gate input capacitance, as explained in Chapter 3. This
Interconnect
Field
Oxide
Cross-section
Bulk
Driver
Load
(interconnect)
Driver
Load Load
(gate)
(a) (b)
Figure 9.12. (a) CMOS gate driving another CMOS gate through a short interconnect. The field
lines from the interconnect to the substrate (shown in the figure inset) result in parasitic capaci-
tance. (b) Simplest equivalent electrical model in which the electrical effect of the interconnect and
gate load gate are modeled with a single capacitor.
c09.qxd 2/5/2004 4:51 PM Page 258
first-order lumped capacitor is a pragmatic choice when metal interconnect properties can
be neglected.
A more accurate interconnect line model would include capacitive, resistive, and in-
ductive effects. However, if the interconnected gates are close to each other, and the inter-
connect length is small, then none of these effects are important and the electrical effects
of the interconnect can be neglected.
When the distance between logic gates increases, the metal line lengthens, and the
first effect that becomes important is the line parasitic capacitance. Metal lines form
small capacitor plates with the substrate isolated by the field oxide (as illustrated in
Figure 9.12), thus forming a capacitance with one terminal grounded. Line capacitance
is measured as (F/mm) so that a longer line has a larger capacitance. When the inter-
connect capacitance is of the same order of magnitude or larger than the load gate input
capacitance, then its value is simply added to that input capacitance. IC local connec-
tions around the compactly designed standard cells have maximum lengths of about
10–100 ␮m, and they can be described as lumped capacitive loads, since their resistive
components are negligible [20].
Line RC Model. A long interconnect has considerable effective resistance that must be
taken into account. For frequencies up to several hundred megahertz, the interconnect is
well modeled by a distributed RC line segmenting the line into several RC sections [Fig-
ure 9.13(a)] [4]. The effect is that the resistance component [Figure 9.12(a)] now shields
the gate driver from the capacitance at the distal end of the line. In other words, the effec-
tive capacitance seen by the driver is smaller [42]. Therefore, the transition of the signal
at the output of the gate will now be faster, since the effective capacitance that the driver
must charge is smaller [46]. This does not imply that the total signal delay is smaller for
longer interconnects, only that the signal transition at the gate output is faster, and that the
transition at the input of the load gate will occur later.
A good circuit-level load model for signal delay requires only two capacitors and one
resistor [Figure 9.13(b)], and is referred to as the ␲-model [40]. A detailed description
about RC models can be found in [4].
Line RLC Model. The upper interconnect levels of an IC are typically used for global
wiring to drive signals among blocks far away in the IC. They are mainly data buses, con-
trol signals, and clock distribution networks. These high-speed signals operate synchro-
nously, and seek the minimum path delay over long distances. Power supply distribution
trees are also used at higher interconnect levels, since they must connect to all the blocks
in the IC.
R
RR RR RR RR RR RR
R
CC CC CC CC CC CC C/2 C/2
C /2 C /2
(a) (b)
Figure 9.13. (a) Distributed RC model of an interconnect line. (b) Equivalent model of the circuit
in Figure 9.12(a) when the line resistance plays a role.
c09.qxd 2/5/2004 4:51 PM Page 259
Transmission line effects become important when the interconnect line is very long
and transistor signal rise/fall times are fast. The RC model is no longer adequate. Deutsch
showed that RC models can underestimate delay by more than 20% compared to models
that account for transmission line effects [21]. Although global interconnects are a small
fraction of the total wiring in an IC, they are usually part of critical paths that limit the
system maximum speed. These global wiring interconnects are expected to grow in num-
ber and complexity from 10k–20k lines to 100k lines in the future [21].
A straightforward single-line model that takes these inductances into account connects
a lumped inductance in series with each lumped RC segment, forming an RLC model
(Figure 9.14). The line inductance effects in ICs are complex, since not only is the induc-
tive component important, but also its inductive coupling to other lines [6, 22, 27]. An ad-
ditional challenge to these models is related to parameter extraction, i.e., the determina-
tion of the R, L, and C values. In a complex design, these components are distributed and
depend on the surrounding structures to the line. Moreover, the adoption of dummy metal
structures to alleviate CMP induced IDL thickness complicates the extraction problem.
9.3.2 Noise
Diminishing noise immunity challenges deep-submicron technologies. Noise is now
viewed as a design metric comparable to timing, area, and power [51]. The aggressive scal-
ing of power supply voltage from 5 V to 1 V or less in current nanotechnologies severely re-
duces the noise margin budget. The values of modern supply voltages were the noise mar-
gins for older technologies. Threshold voltages are scaled accordingly as VDD scales to
maintain circuit performance, contributing even more to the noise margin reduction. The
noise sources come from many factors with the constant increase in IC operational speed,
rise and fall times, leakage currents, capacitive and inductive crosstalk effects, and power
supply noise. All are predicted to further aggravate noise immunity of future technologies.
Noise can induce transient voltage perturbations on nodes that are at quiescent logic
voltage states. If this noise propagates through the circuit and arrives at a memory ele-
ment, it may cause a permanent logic error. In other cases, noise acts on nodes in transi-
tion, impacting circuit delay and, thus, operation speed. The former type of noise is known
as static noise, whereas the second one is referred to as noise on delay [50].
Signal coupling and switching are two of the most important noise sources in modern
digital CMOS ICs. Coupling noise is a form of crosstalk, impacting signal delay and am-
plitude. Noise and delay are related parameters [15]. Noise due to switching occurs at the
supply lines (VDD and GND), and comes from the parasitic resistance and inductance of
the supply/ground distribution tree. The frequency components of this noise identify IR
drop noise (resistive mid–low frequency range noise) or delta-I noise. Delta-I noise (in-
ductive high-frequency noise) occurs when large currents are drawn during simultaneous
switching of many logic gates, particularly output buffers.
L L L L L
R R R R R
C C C C C
Figure 9.14. Distributed RLC model for a single line.

c09.qxd 2/5/2004 4:51 PM Page 260
Coupling Noise. Crosstalk or coupling noise is the most common effect of signal cou-
pling between closely spaced interconnect lines. It produces a noise spike in one static
line (called the victim line) when a neighboring line (aggressor line) makes a transition.
Rubio et al. analyzed crosstalk noise due to the capacitive coupling between interconnect
lines [47]. Figure 9.15(a) illustrates this type of coupling: two metal lines running parallel
within the circuit are coupled through their parasitic capacitor. The capacitive coupling
between the signal lines provokes an undesired voltage spike at the victim line when the
aggressor transitions. We saw in Chapter 8 that if the victim line is floating, then the in-
duced voltage change can be significant. Figure 9.15(a) shows a victim line driven by a
gate (an inverter) that maintains the static logic levels at this node. The noise amplitude
and duration are dependent on many factors such as the aggressor and victim driver’s rel-
ative strength, capacitive coupling, resistive losses, and the receiver circuit bandwidth
[21]. Figure 9.15(b) shows simulation results of noise spikes induced at the victim line.
The victim line (Voutv) has a positive induced 0.2 V peak voltage that is prolonged for
Line
Drivers
Aggressor
Victim
Parasitic
Coupling
Capacitor
(a)(a)
(b)
Figure 9.15. Illustration of (a) capacitive crosstalk circuit, and (b) simulation of electrical behavior.
c09.qxd 2/5/2004 4:51 PM Page 261
about 500 ps. That bump in signal voltage would speed up a circuit transition. Speeding
up a signal is not inherently good since timing synchronous success depends on pre-
dictable arrival times.
Crosstalk noise in modern technologies is quite complex since the length of metal lines
and clock operation speed may require transmission line models that take inductive com-
ponents into account. If the inductive component is important, but only the RC compo-
nents are considered, then the noise levels will be underestimated. This is an important is-
sue for circuit failures since functional errors can occur if noise margins are unexpectedly
violated.
Modeling IC interconnect capacitive coupling is relatively simple, since it occurs only
between signal lines that are physically close. Capacitors are conductive plates separated
by insulators, and capacitance increases with decreasing plate separation. Modern IC lo-
cal logic gate metal spacing can be less than 130 nm.
Inductive coupling originates when an electromagnetic field created by a time-varying
current in one line (aggressor) induces a current in the metal lines influenced by such a
field (victims) (Figure 9.16). These currents are known as return currents, since they close
the current path. The victim line has a resistance component to the ground node large
enough to build a potential drop caused by the return current. This potential opposes the
return current. As a result, the victim line close to the aggressor can sustain only a fraction
of the return current. Other victim lines further away in physical distance must sustain the
remaining return current. The inductive coupling extends across large distances in the IC
if nearby low-resistance return paths to ground are not present (Figure 9.16) [15]. Induc-
tance-noise modeling is difficult. The identification of the return paths in the ICs is not
straightforward, complicating the whole modeling process [22].
Power Supply Noise. This noise appears at the supply and ground distribution net-
works with two components: one is associated with the resistance of the distribution net-
work and the other with its inductance. The former is referred to as IR drop noise, where-
as the second is named delta I-noise (or ⌬I-noise) [16, 51], although the term “IR drop” is
used sometimes to refer to both cases.
IR drop noise causes variations in the DC level of the supply/ground lines due to the
localized current demand of the various gates in the circuit. This current causes a voltage
Magnetic
Flux
Iagg
Victims
Victims
Figure 9.16. Inductive coupling showing the electromagnetic field extending over a large area.
c09.qxd 2/5/2004 4:51 PM Page 262
Clk
1 out
1
Ground interconnect Vnoise
parasitic resistance
Figure 9.17. Illustration of the IR drop effect on a ground line and possible logic error if for a giv-
en time Vnoise ⱖ Vtn.
drop between different parts of the circuit due to the line resistance, such that different
gates may be at different supply/ground levels. The VDD level drops while the VSS (GND)
level rises. Figure 9.17 shows this effect for a ground line and its possible impact on cir-
cuit behavior. If the first logic gate ground terminal has a voltage above zero because of
IR drop, then the logic zero at the output of the first inverter will not lead to zero voltage
at the input of the second inverter. If the second gate is a static inverter, then the IR drop
noise will probably not impact its logic value unless the ground reference difference goes
significantly beyond the transistor threshold voltage. A different situation might appear if
the second gate is a dynamic logic gate. The IR noise could trigger an nMOS device to the
on-state when the gate is the evaluation phase, and lead to a permanent logic error. In
practice, a well-designed robust distribution power grid, with appropriate packaging tech-
nologies, makes the effect of IR drop negligible when compared to delta-I noise.
Delta-I noise occurs when several gates switch simultaneously, and they are coupled to
the parasitic inductive components of the supply/ground lines. This effect is illustrated in
Figure 9.18(a), where the supply and ground nodes of an inverter are connected through
inductors (representing the parasitic inductance of the supply lines) to the main supply
nodes. When the input changes, a transient current is demanded by the logic gate to
charge its output capacitor. This transient current causes an inductive voltage drop at the
VDD terminals of magnitude Vdrop = L(di/dt) so that the supply and ground values seen by
the gate are degraded. The parasitic inductance causes the GND terminal voltage to tem-
porarily rise while the VDD line voltage falls. The voltage degradation increases with the
inductance value and the rate of change of the current. This last parameter is related to the
fast rise and fall times at the gate input. Rise and fall times are decreasing to 10–30 ps in
leading-edge technology. These effects are illustrated in Figure 9.18(b), where we show
simulation results of the circuit in Figure 9.18(a).
왎 EXAMPLE 9.1:
Calculate vdrop = Ldi/dt if ⌬i = 2 A, ⌬t = 20 ps, line inductance = 5 pH.
⌬i/⌬t = 2 A/20 ps = 1011 (A/s)

vdrop = (5 pH) · (1011 A/s) = 500 mV
왎
c09.qxd 2/5/2004 4:52 PM Page 263
Main VDD
idd(t) + di/dt
_} drop
VDD
Input (at circuit)
Output
+ di/dt
_} drop
Main GND
(a) (b)
Figure 9.18. Illustration of supply/ground bounce, (a) circuit representation, and (b) electrical be-
havior.
Power line inductance is minimized in flip-chip packaging that has many closely
spaced I/O leads. Microprocessors may use two out of every three leads for power and
ground connections. This reduces line inductance, since the power lines are in parallel.
Figure 9.19 shows noise spikes simulated on a 2,601 node circuit power grid versus
planar ij position using a 1 ns clock period [34]. We will see that these many mVs of VDD
noise have a significant impact on delay. Design margins try to incorporate these noise ef-
fects; however, designs are now too complex to accurately predict all temperature, ground
bounce, and cross-coupled effects.
Figure 9.19. VDD versus ij plot on chip [34].

c09.qxd 2/5/2004 4:52 PM Page 264
The main problem is that the power supply variation effects on delay cannot be fully
analyzed in detail since it is not feasible to simulate the entire power grid together with the
circuit [14]. The voltage and current at a given point in the grid are dependent on the cur-
rents at all points in the grid, thus requiring a whole simulation. A typical IC power grid
may have between 1M–100M nodes, and the analysis required for a 10M node grid might
take about 5 months [14]. Some simplification techniques can analyze power grids by
treating the effects of devices separately from those of the power grid model. This may
lead to a number of effects combining at a given gate or IC region that provoke a malfunc-
tion of the circuit. These effects were not characterized together.
The impact on timing is due to the effective supply voltage reduction seen by the af-
fected gates; they become weaker, and the propagation delay through them increases.
Chapter 4 discussed fundamental aspects of gate delay in CMOS circuits from the analy-
sis of inverter gates. IR drop is critical in the clock distribution networks since the clock
activity is large. Delta-I noise also affects line delay since the transient change in the sup-
ply/ground levels change the driving capabilities of the gates, thus impacting speed. These
transient power supply reductions are sometimes referred to as brownout.
Delta-I noise was traditionally identified with I/O driver switching activity. Recently,
the simultaneous switching noise from internal circuitry was found to have a similar
delta-I impact in high-performance ICs. Delta-I noise voltage was reported as high as 0.35
V (30%) at gigahertz frequencies and a 1.2 V supply technology [58]. Delta-I noise is
minimized by using decoupling capacitors within the IC and at the package level. Decou-
pling capacitors are high-frequency capacitors connected between VDD and ground, close
to the gates. These capacitors are charged during the circuit power-up and static operation
periods, and support the sudden transient current demands of the switching gates. The
closer the capacitor to the gate supply node, the lower the impedance of the power line and
the smaller the induced noise.
Noise spikes from interconnect coupling or supply/ground noise can cause circuit fail-
ure in static CMOS circuits if they travel a signal path and eventually reach a memory el-
ement. Dynamic circuits have worse noise margins than CMOS static designs since both
dynamic and static stages are unbalanced toward the evaluate-signal direction for perfor-
mance purposes (see Chapter 5). Therefore, static noise in dynamic circuits is more sensi-
tive to logic errors, even for combinational gates. A noise spike arriving at a dynamic gate
input whose output was not discharged in the evaluate phase may switch the logic value,
causing a permanent logic error.
Substrate Noise. CMOS circuits are fabricated on conductive substrates. The substrate
and wells serve to polarize the bulk terminals of devices, but they are also a conductive
layer for noise. Although substrate noise injection is not as significant as other sources in
current technologies for standard digital CMOS applications, it was shown to increase
with substrate doping [2]. Future technologies are expected to increase substrate doping,
potentiality increasing this noise.
9.3.3 Delay
All ICs eventually fail as the clock frequency increases. If the same test pattern sequence
is repeated at successive decreasing clock periods, a Boolean error will occur at a given
frequency. This frequency is called Fmax (i.e., the maximum operating frequency), and it is
usually related to the minimum time required for a signal to travel between internal mem-
c09.qxd 2/5/2004 4:52 PM Page 265
ory elements (generally flip-flops) within the circuit. If the signal arrives later than the
next clock period, then a timing error can occur.
Figure 9.20 illustrates this concept. The circuit state is temporarily stored in flip-flop
memory cells. If the circuit is static and the clock is stopped, then the present state is unal-
tered as long as power is maintained. The flip-flops at the left in Figure 9.20 hold the out-
puts of the previous combinational block (not shown in the figure), and these data are the
input to the combinational logic block shown. This block processes its inputs from the flip-
flops, and places the result temporarily at the inputs to the subsequent flip-flops. When the
next clock edge arrives, these combinational block outputs are evaluated, and stored by the
flip-flops on the right side in Figure 9.20. The longest time required for the combinational
blocks to process the inputs and deliver the output (for all the blocks in the circuit) limits the
maximum operating frequency Fmax. The period of the clock that drives the memory ele-
ments must be larger than the delay of the longest signal path in the combinational circuits.
Not all signal paths in the circuit have the same propagation time between memory el-
ements. The signal paths imposing the strongest limitations to signal propagation (i.e., the
slower ones) are called critical paths. A design challenge is to identify critical paths in the
circuit, and redesign their topology, allowing faster signal travel and overall higher speed.
Process parameter variations alter signal delays for the same given path signal when
changing from chip to chip within a wafer, or die from different wafers in a lot, or differ-
ent lots. This causes equivalently designed circuits to operate at different maximum
speeds. Dies are tested for Fmax and ICs are then separated, or binned, into different speed
groups. If the required Fmax is fixed by the design specification, such as in ASICS, then
faster chips have more margin, whereas slow ones are yield loss. In other applications,
like microprocessors, they are then sold at a price depending on their maximum operating
frequency. This availability of parts at different clock rates and prices is not intentional,
but a result of not controlling process variations.
When a defect in the signal path slows signal propagation, no Boolean error may be
detected or generated at that defect site, but, rather, the signal waveform is simply shifted
by a few nanoseconds or less. The actual Boolean failure may occur at a flip-flop whose
setup, hold, or clock pulse width time requirements are violated (see Chapter 5). The Q
output of the flip-flop then incorrectly reads the data at the D input.
Memory elements
(flip-flops)
Clock
signal
latch
input
Combinational
Logic
latch
output
propagation
delay (tp)
Figure 9.20. Propagation delay of a combinational block between state memory elements.
c09.qxd 2/5/2004 4:52 PM Page 266
Figure 9.21 illustrates the statistical timing variation measured on 25 wafers in a 0.25
␮m technology with cumulative propagation delays measured on 910 dies in each wafer
[5]. The initial rise in the plots shows a near-straight-line relation to the normal distribu-
tion. The difference in propagation delay in Figure 9.21(a) between fastest and slowest
dies at VDD = 2.5 V is about 4 ns against a mean of about 8 ns. When the power supply was
reduced to VDD = 1.2 V [Figure 9.21(b)], the propagation delays increased almost three
times. The break in the curve at the 95% cumulative point is more distinct. Test limits
could be set tightly at the 95% cumulative point to reject the outliers for high-reliability
products, or set somewhat higher, trading yield loss against product reliability expecta-
tions; however, tight limit setting is not practical in a production test environment.
There is a physical difference between parts in the normal and outlier distributions.
The outliers have defects causing delay in addition to the part’s otherwise normal varia-
tion. An important point is that real tests that target delay faults do not have the capability
and resolution to measure to this fine degree for each delay path. Each timing test pattern
does not have an individual test limit, so that delay fault testing typically uses the period
of the system clock, and adds an amount to account for tester noise and parameter vari-
ance.
Similar results were obtained in [38] from process variation data measured in a 0.8 ␮m
process. A test limit must take into account the slowest parameter measurement. Slower
outliers from faster dies overlap normal data in the slower die. This is part of the challenge
in detecting these statistical variance failures. We must look for properties that distinguish
normal from outlier data.
Parametric failures identified in the preceding sections impact the circuit delay in a dif-
ferent fundamental manner. We now discuss four forms of parametric-induced delay: in-
terconnect, crosstalk, supply noise, and temperature-induced delay.
Interconnect Delay. Path-line resistance is influenced by the statistical variation in

metal granularity, width, height, length, and via quality. Variations in metal separation and
dielectric uniformity affect line capacitance, as well as the height and length variation.
The interactive effects of these parameters contribute to the signal path variation in propa-
gation delay shown in Figure 9.21.
More complex problems frequently arise when parallel signal paths converge at a
common gate. We may also see abnormalities when VDD is increased, such as reduced
Fmax, thus contradicting the principle that circuits run faster if VDD is increased. VDD
changes can affect the timing failures describe above. When VDD increases, the transis-
tor gate drive increases, allowing the device to switch faster. If the data path has a de-
fect delay insensitive to VDD increase, but the clock path reduces its propagation delays
due to the VDD increase, then the clock pulse can arrive too early and violate data setup
time. A similar effect of a VDD-insensitive delay defect in the clock line can cause hold
time violations.
Crosstalk Delay. Crosstalk can significantly impact circuit delay [12]. It has a unique
property of increasing or reducing signal delay depending on the swing direction of the
aggressor and victim nodes. Although delay reduction might initially seem an advantage,
it is not, especially if the node being speeded up is the clock node. Clock speedup is
equivalent to data-path slowdown (all the paths in the combinational block of Figure
9.20), thus leading to violation of setup and hold times and logic malfunction.
c09.qxd 2/5/2004 4:52 PM Page 267
Probability
(a)
Probability
(b)
Figure 9.21. Cumulative distributions for propagation delay from 25 wafers with data including
910 dies per wafer. (a) VDD = 2.5 V. (b) VDD = 1.2 V [5].
c09.qxd 2/5/2004 4:52 PM Page 268
(a) (b)
Figure 9.22. Illustration of crosstalk-induced (a) delay, and (b) speedup.
Figure 9.22 illustrates both types of crosstalk-induced delay, showing signal speedup
and slowdown. The crosstalk-induced delay happens when the victim node and the ag-
gressor node make simultaneous transitions in opposite directions [Figure 9.22(a)]. The
crosstalk-induced delay can be quantified as the additional time required for the victim
line to reach its 90% signal swing with respect to the case in which the aggressor does not
switch [12]. Signal speedup [Figure 9.22(b)] occurs when a node makes a transition in a
given direction (say, low to high), and a neighboring coupled node also makes a transition
in the same direction.
Supply Voltage Variation Induced Delay. Chapter 4 showed that the delay of a
CMOS gate is determined by the supply voltage, the output capacitance, and the transis-
tor’s drain saturation current. Once the design is fixed for a given circuit, its speed de-
pends mainly on the supply voltage.
Figure 9.23 shows the VDD sensitivity of an Intel 1 GHz, 6.6 million transistor, router
chip built with 150 nm technology. The chip has an approximate 1.8 MHz change per mV
of power supply voltage at VDD = 1.3 V. Figure 9.23 shows about a 14% increase in Fmax
1600
1600
1400
1400
Fmax 1200
1200
(MHz) 1000
1000
800
800
600
600
400
400
0.8
0.8 1.0
1.0 1.2
1.2 1.4
1.4 1.6
1.6 1.8
1.8
VVDD
DD(v (V)
)
Figure 9.23. Fmax versus VDD for a 150 nm IC [49].

c09.qxd 2/5/2004 4:52 PM Page 269
when VDD increases 10% from VDD=1.3 V. The sensitivity is higher at the low end VDD and
saturates above VDD = 1.6 V. Bernstein et al. reported a change in Fmax with VDD of 200
kHz/mV for a 180 nm microprocessor, and gave a performance rule of thumb that chips
vary by 7–9% when the power supply varies by about 10% [7]. Vangal et al. showed Fmax
versus VDD plots for a 130 nm dual-Vt 5 GHz technology with a sensitivity of 11.3
MHz/mV at VDD = 1.0 V [61]. Figure 9.23 emphasizes that noise-induced millivolt
changes in VDD induced on a critical signal node in normal operation can measurably af-
fect IC speed. A related system problem occurs when board power supplies have a ±5%
accuracy. This could move a test-verified 1 GHz IC in Figure 9.23 to an operational range
of about 883 MHz to 1.18 GHz on the board. One protection used by manufacturers is to
guard-band the shipped product, anticipating power supply influences, but this is wasteful
of IC capability. Parts at the low end of a particular bin are moved to the next lower bin as
a safety precaution, but it is a yield and financial loss for ICs at the higher bins.
Figure 9.19 gave simulation results showing many millivolts of VDD noise spikes over
the die. These intrinsic noise disturbances can cause large MHz changes in Fmax, especial-
ly if a critical path is affected. The timing of the clock distribution network is one of the
most critical control signals in the circuit. IR drop impacts clock skew, which is the maxi-
mum difference between the arrival times of the clock signal to the memory elements in
the circuit. It was reported that an X% IR drop in the supply voltage of a gate can cause
from X/2% to X% increase in gate delay [17, 48]. Saleh et al. simulated an industrial de-
sign, and found that nodal IR drops caused a 30% change in the skew value [48]. They
also found an approximate rule of thumb that a 10% drop in VDD caused a 5–10% change
in clock timing. The complexity of today’s large IC power supply grid does not allow a full
simulation of the entire circuit to check for the impact of supply noise spikes on localized
signal paths. Designers usually check for maximum and minimum temperature and VDD
conditions (called process corners), using oversimplified models that can miss these com-
bined effects [9].
Temperature-Induced Delay. Figure 9.24 shows temperature data taken from a

small, 20,000 transistor test circuit [49]. The temperature sensitivity in the regression
equations in Figure 9.24 is –13.1 kHz/°C and –12.3 kHz/°C for the fast and slow ICs. We
24
y = -0.0 13 1x + 21 .29 1
22
Fa st
20
18
y = -0.0 12 3x + 15 .01 5
16
S lo w
14
12
-100 -50 0 50 100 150
Temperature (C)
Figure 9.24. Speed versus temperature dependence on a 20k transistor circuit [49].
c09.qxd 2/5/2004 4:52 PM Page 270
say that the major effect that slows an IC with temperature rise is the decrease in carrier
mobility. A compensating speed effect is that the absolute values of the n- and p-channel
transistor threshold voltages decrease as temperature rises. For VDD = 0.5 V and Vt = 200
mV technologies, the compensation of the threshold behavior can even lead to ICs with a
positive temperature performance [30]. There may be thermal instability issues, but tem-
perature characterization must be known for each technology to allow recognition of
anomalous parametric behavior.
Interconnect properties also vary with temperature, as explained previously. Since the
total line resistance change with temperature depends on the line total length [22], differ-
ent interconnect paths may change their resistance in different amounts due to tempera-
ture and local thermal impedance variation. This may change the relative delay of the dif-
ferent signal and clock paths on the critical path signal distribution.
The temperature distribution within the circuit is difficult to predict since it is strongly
related to the activity of each block and the local thermal impedance. Figure 9.25 shows a
temperature map corresponding to IR emission from the back side of the die, illustrating
that different regions of the circuit can have more than 40–50°C differences. There is no
circuit simulator to date that can link temperature as an intrinsic parameter to current in a
way that predicts the intrinsic interaction between temperature-induced current variation
and current-induced temperature changes. As a result, temperature spreads out the distrib-
ution of circuit fundamental parameters with a corresponding impact on prediction of its
behavior.
Figure 9.25. Within-die temperature gradients due to different activity zones. (Reproduced by per-
mission of Intel Corporation.)
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9.4 EXTRINSIC PARAMETRIC FAILURE 271
9.4 EXTRINSIC PARAMETRIC FAILURE
We will describe five extrinsic IC mechanisms associated with parametric failures: (1) weak
interconnect opens, (2) resistive vias and contacts, (3) metal mousebites, (4) metal slivers,
and (5) gate oxide shorts in ultrathin technologies. The weak opens and resistive vias are ma-
jor defect-related parametric failure mechanisms. Mousebites occur when sections of metal
are missing from an interconnect line. Slivers are common defects in which a metal particle
lies between two metal conductors and barely contacts the signal lines. Another failure that
shows a variety of responses is the gate oxide short. Some gate shorts show timing- and
power-supply-dependent failures, and the recent ultrathin oxides have a unique failure mode
that raises questions about the implied reliability risk for some gate oxide shorts.
9.4.1 Extrinsic Weak Interconnect Opens

Chapter 8 dealt with open defects. Weak opens are included here since they cause a rela-
tively small increase in interconnect resistance, and do not prevent current in the line.
These defects include a continuous range of resistances, and only those having a very
large value (beyond 1 G⍀) are considered hard opens.
Figure 9.26 shows a photo of a weak open in which the line resistance is locally higher
due to aluminum overetching caused by the presence of a crack. The Ti barrier provides a
parallel current path, although its resistance is much higher than aluminum.
A recent study [45] characterized both interconnect and via resistance distributions for
a six-metal-layer, aluminum-based CMOS, 0.18 ␮m process technology analyzing yield
evaluation monitor structures. Table 9.2 summarizes their results, providing the resistance
distribution for each metal level. Among the total number of opens, between 65%–70% of
opens in metal-1 to metal-4 levels were hard opens, whereas for the two top interconnect
levels, 100% of opens were hard opens. Weak opens in the four lower metal levels ranged
from 15% to 25%. Weak opens are a significant portion of the open defect population.
9.4.2 Extrinsic Resistive Vias and Contacts

Vias are the short, vertical metal structures that connect the layers of horizontal metal in-
terconnections. Contacts are the short, vertical metal structures that connect the transistor
Metal
Ti barrier
Figure 9.26. Weak open due to crack-induced metal overetching. The current goes through the Ti
barrier with a much higher resistance [45].
c09.qxd 2/5/2004 4:52 PM Page 272
Table 9.2. Resistance (RM) Distribution for Weak Opens

Resistance [⍀] Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6
3k< RM < 100k 0.4% 10.9% 12.02% 6.90% 0% 0%
100k < RM < 1M 5.2% 3.5% 6.25% 4.31% 0% 0%
1M < RM < 10M 9.2% 4.9% 6.25% 5.17% 0% 0%
Partial total 14.8% 19.3% 24.52% 16.38% 0% 0%
weak opens
10M < RM < 100M 8.9% 5.7% 2.88% 9.48% 0% 0%
100M < RM < 1G 7.0% 6.0% 1.92% 8.62% 0% 0%
RM > 1G 69.77% 69.0% 70.67% 65.52% 100% 100%
Total 100% 100% 100% 100% 100% 100%
Note: From [45].
drain, source, or gate to the first level of metal interconnections. The physics and fabrica-
tion of contacts and vias are different, but their resistive failure modes can be similar.
Modern ICs can have billions of transistors and perhaps ten times that number of vias, so
that defective vias with elevated resistance are not surprising. Figure 9.9 showed vias and
contacts with different sizes depending upon the metal level. Cracks in flat metal lines
also show properties similar to resistive vias, but are a less common failure mechanism,
particularly with the shunting barrier metals deposited around the Al or Cu metal inter-
connect (see Chapter 6).
Several fabrication-related mechanisms can cause resistive via failures [5, 18].
앫 Via pushups
앫 Etch ash polymers left in the via bottom after the reactive ion etch
앫 Incomplete etches that leave a thin dielectric layer across the bottom of the via
앫 Residual moisture that occupies a space in the via, creating voids when W is de-
posited and leading to increased resistance and possibly corrosion
앫 Insufficient metal filling of via
앫 Via misalignment that affects connecting areas and via size
앫 Small random particles that lie within the via, or large particles that can cause mask
defects, even where the via is missing
앫 Chemical reaction between W and Fl
Figure 9.27 shows a defective via with poor etching [45]. The via makes contact only at
the edges. This can and does cause temperature-dependent timing failures.
The same study that characterized weak interconnect opens also analyzed the resistance
distribution of resistive vias and contacts [45]. Table 9.3 lists their results. Contact problems
resulted in hard opens for more than 90% of the cases, whereas via problems caused be-
tween 52% to 81% of strong opens. Weak opens ranged from 11% to 36% in via contacts.
Resistive vias and contacts are electromigration-sensitive, especially weak opens.
9.4.3 Extrinsic Metal Mousebites

Missing regions of interconnect metal are called mousebites. They can be due to particle
defects, electromigration, or stress voids. Mousebites have a minor electrical effect, but
c09.qxd 2/5/2004 4:52 PM Page 273
Via
M1
Figure 9.27. Defective via in a deep-submicron CMOS IC [45].
are a major reliability risk [49]. Figure 9.28(a) sketches a defect-free and a defective
(mousebite) section of interconnect. If sheet resistance is R䊐 ⬇ 70 m⍀/䊐 and a 90% bite
is taken out of the middle section, then that line resistance changes from 210 m⍀ to 840
m⍀. This major defect in the line would not elevate resistance sufficiently to be detected
by a speed test. Analysis shows that line resistance rises exponentially, but not significant-
ly, until the mousebite exceeds about 95% [Figure 9.28(b)]. These conclusions extend to
voided vias and contacts that also show this resistance dependency on volume voiding.
The via or contact must be well voided to cause an RC delay failure sensitive to tempera-
ture.
There will be some increase in local temperature due to the resistance increase in the
mousebite region, but this defect is virtually undetectable with present technology. The
failure analysis lab may simply find an open circuit, or the defect would not open com-
pletely if protected by a barrier metal sheath.
Analysis is easier using the sheet resistance parameter. Resistance of a structure with
resistivity ␳, length L, area A, height H, and width W is
冢冣冢冣
L L
R=␳ ᎏ =␳ ᎏ (9.3)
A HW
Table 9.3. Distribution of Resistive (RM) Open Contacts and Vias

Resistance [⍀] Contacts Via 1 Via 2 Via 3 Via 4 Via 5
RM < 10k 0.8% 13.8% 1.45% 15.69% 7.33%
10k < RM < 100k 6.9% 1.45% 1.96% 9.38% 6.00%
100k < RM < 1M 0.8% 3.44% 4.35% 5.88% 3.12% 12.67%
1M < RM < 10M 2.8% 17.24% 4.35% 11.76% 6.25% 10.00%
Weak opens 4.4% 41.38% 11.6% 35.29% 18.75% 36.00%
10M < RM < 100M 4.4% 3.92% 12.00%
RM > 1G 91.2% 58.62% 88.4% 60.78% 81.25% 52.00%
Total 100% 100% 100% 100% 100% 100%
Note: From [45].
c09.qxd 2/5/2004 4:52 PM Page 274
7 7
6 6
5
5
4
4
3
Ohms
3 2
2 1
0
1
0 20 40 60 80 100
0 P e rce nt Mous ebite
0 10 20 30 40 50 60 70 80 90 100
Percent Mousebite
(a) (b)
Figure 9.28. (a) Control metal line: normal metal line (bottom) and one with mousebite (top). (b)
Voided metal resistance (m⍀) versus percent metal voiding using R = 70 m⍀/䊐 [49].
Since metal height is constant in an IC metal layer for each technology, we can divide ␳ by
H to get the sheet resistivity R䊐
␳
R䊐 = ᎏ (9.4)
H
This equation assumes that L = W so that R䊐 is the symbol for the resistance of one square
of metal no matter the size. We use R䊐 to quickly estimate the resistance of an intercon-
nect line by counting the number of squares in the metal line. The number of squares in a
line is the length L divided by the width W
L
R = R䊐 ᎏ (9.5)
W
An example will show its use.
왎 EXAMPLE 9.2
Let resistivity ␳ = 3 ␮⍀ · cm, W = 0.5 ␮m, L = 1.5 ␮m, and H = 0.5 ␮m. (a) If
90% of the middle segment of an Al line is removed [Figure 9.28(a)], what is the
increase in resistance? (b) If the line is 100 ␮m long, what is the percent increase
in resistance if, again, 90% of one square is removed?
(a) The sheet resistance is
R䊐 = ␳/H = 3 ␮⍀ · cm/0.5 ␮m = 60 m⍀/䊐
The resistance of the defect-free line in Figure 9.28 (3 squares) is
R = (60 m⍀/䊐)(3 䊐) = 180 m⍀

c09.qxd 2/5/2004 4:52 PM Page 275
If 90% of the middle square is missing [Figure 9.28(a)], then the middle square
becomes 0.5 ␮m / 0.05 ␮m, or it has 10 squares. The middle resistance is
R䊐 = (60 m⍀/䊐)(0.5 ␮m/0.05 ␮m) = 600 m⍀
The resistance of the original segment of one square was 60 m⍀ and it has now
increased to 600 m⍀. The resistance of the original three squares was 180 m⍀
and that has increased to 720 m⍀. A speed test could not detect such a small
change in RC time constant despite this gross defect.
(b) If the line was initially 100 ␮m long, then the resistance would increase
from 12 to 12.54 ⍀, an increase of 4.5%. Again, a speed test could not come
close to detecting this small resistance change for such a flagrant defect. 왎
9.4.4 Extrinsic Metal Slivers

Metal slivers gained importance with the advent of CMP (chemical mechanical polish-
ing). A small metal sliver lies between two interconnect lines, barely or not even touching
them (Figure 9.29). When the temperature rises, the metal will expand, and the sliver will
now touch the signal lines. Higher voltages at burn-in can promote the rupture of the
high-resistance oxide surface of the metals, bonding the three metal elements [43]. When
the temperature returns to lower values, the metals are now tightly bonded. The bridge re-
sistance is now low enough to reduce noise margins or even cause functional failure.
9.5 CONCLUSION
This chapter brought together a diverse failure set different from the study of hard open
and bridging defects. Intrinsic parametric failures arise from skewed statistical distribu-
tion of circuit-speed-related parameters, and from extrinsic subtle defects causing the
same type of failure modes. The mechanisms for these failures were described in figures
and plots. Cross-coupled noise, ground bounce, IR drop, and delta-I inductive noise are
intrinsic failure modes that span design, test, reliability, and failure analysis issues. The
extrinsic failure modes from resistive vias, mousebites, and metal slivers were described.
Their detection depends on variation of circuit environmental parameters. Parametric fail-
ures are expected to worsen in occurrence and diversity as circuit dimensions shrink with
technology.
Figure 9.29. Metal sliver [43].

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9.7 EXERCISES
9.1. Parametric failures are basically insensitive to our present test methods, such as
stuck-at fault testing, IDDQ testing, delay fault testing, and functional tests. There-
fore, why do we care about parametric failures?
9.2. Discuss why IDsat is an indicator of circuit speed performance.
9.3. Transistor gate width dimensions have a statistical variation as does channel length.
Discuss two effects that ⌬w has on circuit speed performance.
9.4. Figure 9.1 shows a monolayer step change in oxide thickness Tox. What would this
effect have on the thin oxide reliability? Why would it be a negligible effect on old-
er technologies?
9.5. Use the model equation for a saturated long-channel transistor, and explain why
variation in Leff has a larger effect on IDsat than a similar variation in Weff.
9.6. Ioff is the small drain leakage current when the transistor is in the off-state. Why do
we worry about this small current?
9.7. The reliability and test issues of vias and contacts were not a great concern in older
technologies as they are now. Explain.
9.8. Temperature affects the transistor threshold voltage and carrier mobility. Typically,
Vt drops in magnitude as temperature increases (increases gate drive voltage), and
carrier mobility degrades (reduces IDsat). Can you locate the transistor bias point in
Figure 9.11(b) where the device parameters are invariant with temperature? What
does this imply?
9.9. What circumstances determine whether you would use the line RC model or the
line RLC model in taking logic gate loading effects into account.
9.10. Crosstalk noise is an increasing source of parametric failures in modern ICs. Ex-
plain the variables that worsen crosstalk noise.
9.11. Describe the variables that worsen ground bounce noise.

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9.12. All ICs have an upper maximum frequency of operation called Fmax. Explain why
Fmax is not a constant value for identically designed parts from the same wafer.
9.13. Figure 9.23 shows Fmax variation with VDD. How might a customer experience neg-
ative effects of this property?
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CHAPTER 10
DEFECT-BASED TESTING
10.1 INTRODUCTION
The life cycle of an IC from conception to market to obsolescence requires many engi-
neering man-hours plus complex equipment. The goal is to ensure that the product meets
its specifications and performs as predicted. Two main verification processes are in-
volved: (1) design verification is the process that ensures that the design (not a physical
entity) meets specifications before the IC is manufactured, and (2) testing verifies that the
ICs were manufactured correctly, assuming a good design. A perfect design can lead to
ICs that do not meet specifications because of errors or imperfections during the fabrica-
tion process. This chapter is about testing, not design verification.
Testing evolved from simple practices to complex procedures with the growth of IC
technology. Testing can now be more than 50% of the overall development/fabrication
cost, and it starts with the design. Testing must ensure that the circuit was manufactured
correctly, and that it will function during the lifetime of the product. This involves reliabil-
ity and test escape issues. We start with a historical perspective, and then define the vari-
ous types of IC testing.
Test practices began with simple ICs, and we will describe its evolution, introducing
the concepts of automatic test pattern generation (ATPG) and illustrate these concepts
with examples. We will describe design for test (DfT) practices since test is an integral
part of design in today’s technologies. We follow with a detailed look at defect-based test-
ing (DBT) since this is the strongest foundation on which to build a test plan.
DBT develops a detection strategy that matches defect-class electronic properties to
particular test methods. We describe those test methods, and also special designs for test
structures now necessary to understand test practices and provide test success. We then
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282 CHAPTER 10 DEFECT-BASED TESTING
link that test knowledge to the defect properties of Chapters 7–9. There are many test de-
tails, but our goal is to provide introductory concepts of testing, and focus on the physical
strengths and weaknesses of the various tests. The chapter ends with a description of the
serious negative impact of nanometer technologies on all test methods.
The practice of DBT dates back in electronics history to when printed wire boards
were visually inspected for solder blobs (bridges), wire trace opens, or mousebites. The
tests were visual, but they targeted specific defects. The formal study of CMOS IC defect
properties grew rapidly in the 1980s. A paper presented at the International Test Confer-
ence in 1994, titled “Defect Classes—An Overdue Paradigm for Testing CMOS ICs,” col-
lated diverse data on bridges, opens, and parametric delay defects, and then proposed a
unified test strategy based on these defect electronic properties. About the same time,
Manual d’Abreu is believed to have first coined the phrase “defect-based testing” at an In-
tel Corp. test workshop.
10.2 DIGITAL IC TESTING: THE BASICS
Testing does several things. Digital testers must evaluate whether ICs meet their product
specifications by looking for gross or random defects that cause failure. Testers also sort
products into performance bins, such as maximum frequency performance. Customers
pay considerable price differences for microprocessors or microcontrollers that run faster
than others. Testers are also useful tools in failure analysis.
Testers are expensive computers with special I/O features and large memory capacity,
and they are often referred to as automatic test equipment, or ATE. ATEs apply a logic sig-
nal to the IC input pins on each clock cycle. This signal is a test vector, and a sequence of
test vectors is a test pattern. The measured result at the output pins is compared with an
expected good result from a simulation. Digital ICs are also subjected to DC and AC para-
metric tests in addition to the logic testing. Testers measure analog parameters, such as in-
put and output pin voltages and currents, or propagation delay times. Testing faces the
complex challenge of finding the oftentimes obscure defects in the IC.
The major test costs are (1) test development to create and simulate the test vectors, (2)
the initial ATE purchase (several million dollars per ATE), and (3) the recurring costs of
the actual manufacturing tests. We know much about the test process, and use that knowl-
edge to minimize defective ICs escaping to the customer. Our primary philosophy is de-
tection of defects. That may seem obvious, but it is not. It is a critical decision made early
in product planning. The goal of testing is to determine if a given IC will follow specifica-
tions or it will not because of a defect. The primary test purpose is not to find the defect
and its location within the IC. Finding defects within ICs is referred to as failure analysis.
Most ICs that do not pass testing are just discarded, but in some cases, certain ICs are di-
agnosed to monitor deviations in the fabrication process.
Digital IC testing uses voltage-based and current-based measurements. Voltage-based
testing measures the potential at IC output pins. It examines Boolean correctness by ap-
plying logic voltages to the input pins and measuring the voltage levels at the output pins
of the IC. The expected high and low logic output voltages are computed from expensive
logic simulations and stored in computer memory. Voltage-based testing, in practice, is
often done at slow application rates, using fault models, or at high clock rates that evalu-
ate subsets of IC functionality over a range of temperatures and power supply voltages
(VDD). ATE testing is done at the wafer and package-part level.
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10.2 DIGITAL IC TESTING: THE BASICS 283
Current-based testing analyzes the rich information content of the IC power supply
current in either the DC quiescent logic state or in the transient current pulse. The quies-
cent current test, called the IDDQ test, measures the power supply current when all logic
states are settled at their stable, steady-state values. The IDDQ test is by far the most sensi-
tive of the CMOS digital IC tests [39, 44]. The transient current test takes several forms,
depending upon when in the transient time period the current is measured, or it may use
statistical techniques on the whole waveform. We will describe the various forms of volt-
age-based and current-based testing.
10.2.1 Voltage-Based Testing

The major voltage-based test techniques are (1) functional testing, (2) stuck-at fault test-
ing, and (3) delay fault testing. These three sometimes overlap, but understanding their
strengths and weaknesses is necessary for defect-based test practice.
Functional Testing. Functional testing literally means to test the IC for its intended
use by the customer, but there are different interpretations. Functional testing may refer to
applying all of the logic states of the truth table to the part. Or it can refer to the case when
the input voltage signals are applied only to the IC primary input pins, as opposed to spe-
cial test pins called scan pins (discussed later in this chapter). We will describe later the
design for test structures that support this interpretation.
Functional testing to replicate customer function is appealing. We might say, “If the
part passes a functional test for the customer, what could be better.” However, the state-
ment is flawed, as an example will illustrate.
왎 EXAMPLE 10.1
Calculate the time to functionally test a 1K static RAM for all of the memory
states that a customer might use. Assume a test clock rate of 100 MHz.
There are 1024 memory bits in the 1K SRAM and each bit has two possible
states (zero or one). Therefore, the total number of logic states (test vectors) is
21024 = 1.8 × 10308 logic states
The time for one test is (100 MHz)–1 = 10 ns. Therefore, the total time for the
functional test is
10308(tests) × 10(ns/test)
ᎏᎏᎏ ⬇ 10292 years
31.5 × 106 (5/year)
The point is made. Even relatively simple ICs are numerically intractable to the
task of replicating customer function. Microprocessors, microcontrollers, and
DSP (digital signal processing) ICs are worse. 왎
Functional testing has this profound weakness, but it has a pragmatic role in testing.
When a large number of test vectors are cycled through an IC at fast clock rates, we find
that defect detection is significant enough to warrant its use even though we cannot pre-
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dict what defect classes are actually detected. Also, functional testing is the method of
choice for testing at high clock rates to separate the product into its various speed perfor-
mance bins. These test patterns usually originate with the designer’s design verification
simulations. Functional testing is useful, but beware of its limitations.
Stuck-At-Fault (SAF) Testing. Test engineers in the early days of digital IC produc-
tion quickly found that the time to generate test vectors became prohibitive as die com-
plexity rose. Test development costs and lost time to market forced new ways of thinking.
Why not let a computer generate the test if it is simply fed the logic design netlist? Since
computers do not understand defects, the notion of a fault model arose. A fault model is a
hypothesis of how a circuit will fail. It is imaginary, and the fault model test process does
not care what caused the failure. A wonderfully simple fault model is the stuck-at fault
(SAF), mentioned in Chapter 7, whose hypothesis is that the IC failed its Boolean logic
exercise. A signal node is assumed to be stuck, or tied to one of the power rails. The SAF
test method does not concern itself with bridge defects and their critical resistance, or
even open defects. It just tests for a Boolean upset at a signal node. Faults are not real. No
one has ever photographed a fault, but defects are real and have been photographed.
Figure 10.1(a) shows the SAF concept applied to inverter. The output node C is
clamped at zero ohms to the strong power supply VDD so node C is stuck at logic-1 (SA-
1). This is one electrical equivalent of how a SAF might occur. Another SAF behavior
arises when an open defect causes a floating gate that goes to one of the rail voltages. If it
floated to VDD, then the nMOS transistor would be permanently on, and the pMOS tran-
sistor would be permanently off, causing a permanent output stuck at zero (SA-0).
The number of SAFs is twice the number of signal nodes, or four SAFs for the invert-
er. The 2NAND in Figure 10.1(b) has three signal nodes and six SAFs. Input node B on
the 2NAND is shown with a symbolic stuck-at-zero (SA-0) fault. Since computers are the
perfect machine for Boolean algebra, automatic test pattern generation (ATPG) for SAF
testing developed rapidly in the 1960s, and it is now a convenient adjunct tool to the de-
sign process [5]. We will look next at how SAF test patterns are derived.
Stuck-At-Fault Test Pattern Generation. Computers read a logic circuit netlist,

and then compute a list of test vectors that test for a particular failure mode. There is
broad value in understanding how SAF test patterns are generated. The stuck-at fault is
the earliest and simplest of fault models, and despite its many weaknesses, it is still a
commonly used fault model [20].
A test for a SAF would try to drive the node under test to a logic value opposite to
the one being tested. If we were testing the 2NAND gate in Figure 10.1(b) for a SA0 at
node B, then we would attempt to drive node B to a logic-1. We could not test node B
for a SA0 by driving it to a logic-0, since the error would not be exposed. This is the
VV
DD AA
DD C
B C
B
A C
A C
(a) (b)
Figure 10.1. SAFs shown for (a) an inverter, (b) a 2NAND.

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1 1
1 0/1 1/0 1/0
1/0 1
0/1 0/1
1/0 0/1
0 0
Figure 10.2. Logic gates showing path sensitization signals for a NAND, AND, NOR, and OR gate.
first rule of fault testing: always drive the node under test to the opposite logic state of
the suspected error.
Figure 10.2 illustrates how signal information from a node under test can be passed from
one logic gate to another until finally reaching a primary output pin where it is evaluated by
a tester. When a logic gate has multiple inputs, there is a way to disable the influence of
those input nodes not under investigation using the concept of the noncontrolling logic state
(Chapter 4). For example, if we want the 3NAND gate in Figure 10.2 to pass the lower in-
put node signal through the gate, then we set the other inputs to a logic-1. When the top two
inputs are at logic-1, then the output signal is the complement of the signal at the bottom in-
put terminal. Construction of a 3-bit truth table will show this. The logic-1 has the effect of
turning off the parallel pMOS transistor tied to that node, and turning on the series nMOS
transistor in a NAND or AND gate. The two complementary transistors then have no effect
on the output if the other logic inputs change. The process of using noncontrolling input
states to pass a signal from the inner core logic to a primary output is called path sensitiza-
tion. Path sensitization can be confirmed for the other three logic gates in Figure 10.2, lead-
ing to two rules to memorize: (1) the noncontrolling logic state for an AND and a NAND
gate is logic-1, and (2) the noncontrolling logic state for a NOR and an OR gate is logic-0.
There are four basic steps in generating a SAF vector for a selected node:
1. Select a node for testing and select one of the two SAFs for that node.
2. The logic value of that node must be set to the logic state opposite to the SAF con-
dition under test.
3. A sensitive path must be constructed between the node under test and a primary
output, using the principle of noncontrolling logic states.
4. Do a backward trace of the logic to set primary input nodes at values that will
achieve steps 2 and 3 above.
왎 EXAMPLE 10.2
Use the circuit in Figure 10.3 and derive the SAF test vector to test the designat-
ed node for a SA-0.
Repeating the step procedure:
1. Select a node to test for a SA0 (see designated node in Figure 10.3).
2. We set that node to the opposite logic state and pencil in a logic-1 in the fig-
ure.
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I1
I2
I3
SA-0
I4
I5 O1
I6
Figure 10.3. A circuit showing SAF test vector generation for the designated SA0 node.
3. The path sensitization to a primary output would pencil-in a logic-0 at the

2NOR gate upper terminal and a logic-1 at the 2AND lower terminal that dri-
ves primary output O1.
4. The backward trace would set inputs I3 and I4 to the 11 state, forcing the node
under test to a logic-1. I1 and I2 are set at logic-1 to sensitize the 2NOR gate at
logic-0. I5 and I6 are set to any combination that forces a logic-1 out of the
2OR gate. That could be 11, 10, or 01.
Therefore, three possible test vectors will test the designated node in Figure
10.3 for a SA0: 11 11 11, 11 11 10, or 11 11 01. Notice that the same test vectors
would test the inverter input node for a SA1. Another fault-equivalency example
is that the output node O1 is driven to logic-0 in a good circuit. If we measured a
logic-1 state at O1, then that is equivalent to detecting a SA1 error on O1. These
fault equivalence properties reduce the number of vectors to test the whole cir-
cuit, since one vector detects more than one SAF.
The number of signal nodes bound the number of SAFs in a given circuit.
When the SAF test generation software is completed, the percentage of detected
SAFs can be calculated. Fault models have the ability to provide a test coverage
metric in contrast to functional testing. 왎
왎 EXAMPLE 10.3
Determine the test vector that detects node-m SA0 (Figure 10.4) (a) when the
primary output is Node A, and (b) when the primary output is Node B.
Follow the four-step procedure and get
(a) Node-m is selected
Set to logic-1
Path sensitization for the 2-OR gates sets I1 = 0, I2 = 0
The backward trace assigns I3 = 1 and I4 = 1 to set node m at logic-1.
The test vector 0011 tests for node m stuck at zero.
(b) Node-m is selected
Set to logic-1
Path sensitization for the 2-OR gates sets I1 = 0, I2 = 0.
c10.qxd 2/7/2004 2:51 PM Page 287
I1 A
I2
I3 m
B
I4
Figure 10.4.
The backward trace has a problem. If I3 and I4 are set to logic-1 to force node-
m to logic-1, then the path sensitization on the 2NAND gate (or the 2NOR gate)
feeding node B has a conflict. We cannot simultaneously set a logic-1 at node-m
and the noncontrolling logic state of the 2NAND. Therefore, a SAF vector can-
not detect the node-m SA0. Node-m is said to be redundant when tested through
output node B.
Redundant nodes appear in circuitry, and a typical SAF coverage statement
might be, “The circuit has 98.7% SAF coverage; the 1.3% undetected are redun-
dant nodes.” Redundant nodes often occur in designs to achieve timing con-
straints or as leftovers resulting from design reuse. 왎
Self-Exercise 10.1
Derive SAF test vectors to test node-c SA1 and node m SA0 in Figure 10.5.
c
I1
I2
I3 W
I4 m
I5
I6
Figure 10.5.
The SAF test is the most popular of the structural test methods. However, it has weak-
nesses. SAF vectors applied through special scan test structures (described later) are typi-
cally clocked in at about 50 MHz–400 MHz limited by test clock layout and thermal heat-
ing of the die. The SAF test targets no bridge defects. It will detect a signal-to-rail bridge
only if the defect is below the critical resistance. It will detect signal-node-to-signal-node
bridges if, again, the bridge is less than Rcrit, and also if a sensitive path exists by chance
for that test vector. The SAF test method does target two of the five combinational logic
open-circuit defect classes, but targets none of the parametric failure classes.
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Despite these shortcomings, there are diverse applications for the SAF test pattern gen-
eration algorithm. We will show in later sections how it forms the basis for delay fault and
IDDQ test pattern generation.
10.2.2 Speed Testing

Speed testing refers to any voltage-based test that examines the IC at its user-specified
clock frequency or clock period. This test is also used to classify and separate parts de-
pending on their operating frequency. This procedure is called speed binning. SAF testing
is done at slower clock rates, but ICs must be tested at their rated speeds and also need
other forms of testing. We will describe the Fmax and the delay fault test.
The Fmax Test. The Fmax test applies several thousands to millions of functional test
vectors to the IC in a certain clock period. If the part passes, then the clock period is
shortened until failure occurs. Fmax is equal to the reciprocal of the minimum period
of functionality. It measures how fast an individual IC can be clocked. Typically, the
Fmax test is done on parts that passed all other tests, so that Fmax is often considered a
speed binning procedure on good parts rather than a test. However, the Fmax measure-
ment has a significant role in testing resistive vias and contacts. If Fmax is compared at
two temperatures such as room temperature and hot (100°C), then resistive vias and
contacts have a definite signature—an IC with resistive vias and contacts will typically
run faster at the hot temperature. This defies normal circuit behavior and is explained
later.
The Fmax test is expensive in tester time since it replicates many test patterns until fail-
ure occurs, but it is the only test that is known to detect these forms of parametric defects.
The Fmax test has little knowledge of what paths and logic gates are being speed tested, but
it is essential for speed binning and resistive via detection.
Delay Fault Test. Delay fault testing seeks to quantify speed test coverage of the IC.
Delay fault tests evaluate individual timing paths, or evaluate the signal nodes of each
logic gate, testing for their rise- and fall-time capability. The delay fault test uses a two-
vector sequence. The first vector sets the initial conditions of the test, and the second
vector activates a signal that typically tests for transition time of a gate or a path propa-
gation delay. When the second vector is activated, only one primary input should change
on the clock command. Multiple input changes on the same clock “confuse” the circuit
and may present a noisy result. The resulting signal at the designated logic gate must be
carefully steered through a sensitive path in the logic between that gate and a primary
output where the tester makes a pass–fail timing measurement. The number of delay
paths in most ICs is usually numerically intractable so that targeting gate node transi-
tions is more practical. However, targeting only gate delays may result in a bad delay
test for many parts since gate level test usually target shorter timing paths, leaving long
ones untested.
The delay fault test presently cannot resolve timing defects at other than a gross level.
Die-to-die statistical variation and inability to test propagation delay in different signal
paths forces delay fault testing to gross test limits. Typically, the period of a test is set at
the nominal clock period of the product plus a guard band for tester noise and product
variances, and adjustment for “yield considerations.” This frustrates the ability to detect
finer-resolution defects that may cause customer failures.
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Delay Fault Test Pattern Generation. Delay faults (DF) require a two-sequence
pattern of test vectors, and both patterns use the SAF vector algorithm. The first DF pat-
tern sets a node to a logic state, and is not concerned with reading a result (i.e., path sensi-
tization). The SAF algorithm can do that by defining all logic gate outputs as primary out-
puts, so that path sensitization is disabled. The second DF test vector forces a change in
the designated node, and develops a sensitized path to a primary output. The second vec-
tor should change only one node input to force the transition. This is a pure SAF vector,
but used for timing in this case. An example will illustrate this procedure.
왎 EXAMPLE 10.4
Generate the two-pattern delay fault test vectors for the node slow to rise in Fig-
ure 10.6.
I1
I2
I3 Node
I4 slow
to rise
I5 O1
I6
Figure 10.6. Delay fault patterns for a node slow-to-rise test.
Steps in solution:
1. Set the node to logic-0 (no path sensitization is required).
2. Set up path sensitization for the second vector. I1 . . . I6 = 11 01 11.
3. Change I3 from I3 = 0 to I3 = 1 with I4 fixed at logic-1.
First vector = 11 01 11
Second vector = 11 11 11
(You could interchange the roles of I3 and I4.)
4. Measure the time between the clock edge on the second vector and signal
detection at the output. This is typically done with a timing limit, although
the time value itself can be measured by test pattern iteration as the clock
period is decreased.
왎
10.2.3 Current-Based Testing

Data taken during the late 1980s and early 1990s showed that many CMOS IC defects
caused intermediate voltages at internal nodes (i.e., voltage values out of the established
ranges for logic 0 and logic 1). This caused circuit behaviors that could not be described
using voltage-based approaches since internal mode intermediate voltages are restored by
successive gates, and nonintermediate voltages are generated at the circuit outputs. These
defect-induced behaviors were better described by circuit parameters other than the logic
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response. Current-based testing techniques were shown to be effective parametric test

methods for CMOS ICs. Technology scaling pushed current-based testing methods from
single-threshold IDDQ to more elaborate quiescent current techniques. These techniques
are covered at the end of the chapter, whereas the basic single-threshold IDDQ is covered
next.
IDDQ Test. The quiescent power supply current test grew up with the CMOS IC industry
in the 1970s and 1980s [30, 33, 38, 43], and later became known as the IDDQ test [59]. Test
engineers quickly concluded that since CMOS circuits had virtually zero supply current in
the quiescent state, then an elevation in this current indicated the presence of a defect, de-
sign error, or fabrication problem. The tester measures IDDQ when all transient currents
have settled. The IDDQ signature contains sensitive defect information.
Figure 10.7 illustrates the IDDQ test applied to a pair of inverters. The signal timing wave-
forms show V1, V2, and the current through the power supply iDD(t). During the signal tran-
sition, both n and pMOS transistors are on, making a conductive path from VDD to ground,
and a current pulse appears (Chapter 4). When the signal reaches its post-transition levels,
the current goes to near zero in a defect-free circuit since one of the complementary tran-
sistors is off. The IDDQ test measures current in this quiescent state. A bridge defect shown
between the N2 gate and its source (or drain) elevates IDDQ when V1 is low and V2 is high.
The iDD(t) waveform in Figure 10.7(b) shows this. The IDDQ measurement must be taken af-
ter the transient current settles, and this time is found by electrical characterization. Most
defects elevate IDDQ, but there are certain defect classes that do not, as we will review later.
The IDDQ test has many positive features described in the bridge and open defect Chap-
ters 7 and 8. The weaknesses of the IDDQ test relate to certain open circuit defects, lack of
direct detectability of parametric delay defects, the slow speed of the measurements, and
the noisy background current of advanced technology ICs. Five open circuit defect class-
es for combinational logic were described in Chapter 8, and the IDDQ test quantifies detec-
tion of two. IDDQ has good nontarget detection of the memory or stuck-open defect [58,
68], but fails to detect the transistor pair-on/off and the narrow open defect. The open
transistor pair on/off defect occurs when a floating gate acquires a voltage near VDD or
GND, thus turning off one of the complementary transistors. The IDDQ measurement
VVDD VV11
DD
PP11 VV22
PP2 IIDDQ
2 (defect)
DDQ(defect)
V
V
VV11 2
VVo0
iddiDD
(t)(t)
NN1 NN2
1 2
IIDDQ IIDDQ
DDQ(normal)
(normal)
DDQ
time
time
(a) (b)
Figure 10.7. (a) One 2-inverter circuit with gate-source defects at N2 and, (b) waveform showing
IDDQ elevation.
c10.qxd 2/7/2004 2:51 PM Page 291
GB
GD DB
DS
GS SB
In
Out
GD DB
DS
GS SB
GB
Figure 10.8. Inverter showing 12 possible transistor bridges.
speed can be solved with the Wallquist Quic-Mon load board circuit capable of submi-
croampere measurements above 100 kHz [67]. Although this rate is slow compared to
voltage-based testing, considerably fewer IDDQ vectors are needed for defect coverage.
Measurement environments vary with different manufacturers, making instrumentation
still not universally solved. Despite these weaknesses, the IDDQ test is still the most power-
ful of the several test techniques [39, 44].
IDDQ Test Pattern Generation. IDDQ test patterns are typically generated for bridge
defects across transistor nodes. Figure 10.8 shows an inverter for which IDDQ transistor
bridge vectors will be written. We count six possible transistor terminal bridge connec-
tions—GD, GS, GB, DS, DB, and SB—so that the inverter has 12 possible transistor
bridge defect locations to test.
Inverters have only two logic states, and if IDDQ is measured during the application of
logic-1 and logic-0, we find the transistor node detection shown in Table 10.1. The IDDQ
coverage across a transistor node is defined as the presence of opposite voltage polarity
across the bridged nodes with DC paths to VDD and GND. Twelve transistor bridges are
detected by the two logic states (Figure 10.8). Exceptions occur when terminals are in-
tentionally connected, such as test-redundant source-to-substrate and well connections.
The two inverter logic states are also the test vectors that give 100% SAF coverage to
the circuit. An extension of this observation asks whether IDDQ vectors will detect all
transistor bridges in any circuit if the 100% SAF test vectors are applied to every logic
gate. The answer is yes, and these patterns are called pseudo-stuck-at fault (PSAF) pat-
terns [6, 39].
The three test vectors for 100% SAF coverage of a 2NAND gate are 01, 10, and 11 and
01, 10, and 00 for the 2NOR gate. If we apply these three test vectors to the 2NAND or
Table 10.1. IDDQ Test on Inverter

Vector Bridges detected with IDDQ
In = logic-1 GSn, GDn, GBn, GDp, DBp, and DSp
In = logic-0 GDn, DBn, DSn, GSp, GBp, and GDp
c10.qxd 2/7/2004 2:51 PM Page 292
V
VDD
DD V
VDD
DD
V
VAA
V
Vout
out VB
B V
Vout
out
V
VAA
VB
B
2NAND 2NOR
Figure 10.9. 2NAND and 2NOR circuits for IDDQ test pattern verification.
2NOR gates and measure IDDQ at each vector, then we attain 100% IDDQ transistor node
bridge defect coverage. You can manually verify the SAF and IDDQ coverage using these
vectors on the 2NAND and 2NOR circuits shown in Figure 10.9. There is no path sensiti-
zation since the power supply current pin monitors the test results, and not the primary
signal output pins. This simplifies ATPG, and a SAF test pattern generator can generate
the IDDQ vectors by simply defining all logic gate outputs as primary outputs. The SAF
patterns are applied to each gate, but the Boolean result is irrelevant to the test.
Transient Current Tests. Some defects, such as certain opens, do not induce interme-
diate voltages into the circuit, and, therefore, cannot be detected with the IDDQ test
method. In addition, IDDQ testing has limitations when applied to deep-submicron ICs, as
will be explained in this chapter. To solve some of these limitations, a number of tech-
niques based on analyzing the transient portions of the supply current have been studied
[10, 27, 37, 51, 53, 57].
The transient portion of the supply current contains information about the parts of the
circuit registering activity, and the intent is to relate this information to the presence of de-
fects in the circuit. There are many approaches to transient current testing, but a solution
for production testing has not been demonstrated. However, some of the proposed tech-
niques have been applied experimentally to commercial circuits [7, 31, 47].
One challenge of transient current testing relates to instrumentation since the transient
portion of the current waveform contains very high frequency components that are diffi-
cult to measure. Additional challenges relate to noise on the supply pins when the circuit
is switching. There is also possible information masking due to the internal and external
decoupling capacitors that supply part of the transient current.
10.2.4 Comparative Test Methods Studies

Independent studies by Hewlett-Packard and IBM compared the relative defect detection
efficiency of IDDQ, delay fault, stuck-at fault (SAF), and at-speed functional tests. Figure
10.10(a) shows the Hewlett-Packard results; 758 total defects were found in a population
of 26,000 ICs [39]. The uniquely detected defects are shown in bold, and the mutual
detections are shown in smaller, regular type. Figure 10.10(b) shows the IBM results,
a total of 665 defects from about 20,000 ICs in a joint study with the Sematech organi-
zation [44]. One of the IBM mutual detection numbers was omitted to disguise yield.
c10.qxd 2/7/2004 2:51 PM Page 293
10.3 DESIGN FOR TEST 293
I DDQ At-Speed I DDQ Delay Fault

Funcional
731 1
7 624 34
15
0 5
0 179 22 21 102
3 17
3
0 20 7
SAF
SAF Delay Fault
(a) (b)
Figure 10.10. Test methods comparison of detection efficiency. (a) Hewlett-Packard [39], (b) IBM
[44].
The data of Figure 10.10 are compared in Table 10.2. Since one set of overlapping data
is missing in Figure 10.10(b), the unique detection percentages are compared. There were
differences in the type of delay fault patterns by each company and other details, but the
IDDQ, delay fault, and stuck-at fault data match well in the two experiments. Defect elec-
tronic studies also correlate with the results of Figure 10.10, but do not provide compara-
tive numbers. Bridging defects are dominant, and IDDQ detects virtually all of these,
whereas voltage-based tests detect only a small percentage. Open circuit defects are de-
tected by voltage- and current-based tests. The lower detection rate of pure delay defects
might correlate with the gross insensitivity of that technique.
10.3 DESIGN FOR TEST
Test and diagnosis are more efficient using design for test (DfT) structures. We will de-
scribe three major IC DfT techniques: (1) scan design, (2) built-in self-test (BIST), and
(3) special test structures for the next level of assembly. The urgency in using DfT is that
without it adequate testing is now virtually impossible given the complexity of present
and future-generation designs. DfT is not an option, but required in nanometer ICs to
meet overall product quality and reliability goals. Manufacturers and customers must ac-
cept DfT, or quality goals and time to market will be seriously jeopardized for most prod-
ucts.
DfT has several properties that slowed its acceptance. DfT circuits add active area to a
die, reducing yield, increasing cost per die, and adding extra I/O pins. When DfT was in-
troduced many years ago, ICs had small, fixed pin counts, such as 14, 24, 40, or 44 pins.
Table 10.2. Comparative Test Method Studies

Hewlett-Packard IBM–Sematech
Test % Unique-Detect Test % Unique-Detect
IDDQ 96.4 IDDQ 93.8
Delay fault 2.6 Delay fault 5.1
Stuck-at fault 0 Stuck-at fault 1.1
Note: From [39, 44].
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An extra four pins for DfT could not be added. Now, pin grid array packages allow hun-
dreds to thousands of pins with more flexibility in their assignment. Extra pins for DfT
are not usually an issue with modern packaging technologies. DfT structures must yield
well or the whole die will fail. Increased die area also reduces the number of dies per
wafer.
10.3.1 Scan Design

Circuit scan design is a popular design for test technique that dates back to the 1960s as a
technique practiced on boards in Japan. Williams and Angel at Stanford University later
described IC scan testing as a technique in which all circuit memory elements (flip-flops)
had two modes: (1) normal circuit mode and (2) test mode [71]. The testability features of
the flip-flops are transparent to normal operation. However in test mode, the flip-flops are
transformed into a serial scan chain that could shift long test vectors deep inside the IC.
Test vectors can now be efficiently delivered to deep logic portions of the IC, and the log-
ic results can then be read and transported out of the IC by these same scan chains.
Figure 10.11(a) illustrates a single-phase clock design for a circuit with four combina-
tional logic blocks separated by storage registers. Parallel storage registers hold informa-
tion from each logic block until those data are clocked through to the next block. The tim-
ing is set so that all logic states are settled prior to the next clock.
In test mode, the flip-flop elements convert the parallel-in-to-parallel-out register into a
serial-in-to-serial-out register [Figure 10.11(b)]. Four test pins are required: data-in, data-
out, mode-select, and Clock. Test vectors serially enter the IC through the data-in pin, and
are shifted a certain number of clock pulses. The shifting stops when bits in the chain are
lined up with targeted combinational logic block input nodes. The bit pattern in the long se-
rial register contains the segmented test vectors for each combinational logic block.
Primary
Primary Combinational Combinational Combinational Primary
Primary
SR0
SR1
SR2
Combinational Combinational Combinational

SR0
SR1
SR2
Input Combinational Combinational Combinational Output

Output
SR0
SR1
SR2
Input LogicBlock
Logic Block LogicBlock
Logic Block LogicBlock
Logic Block
Logic1 Block Logic2 Block Logic3Block Pins
Pins
Pins 1
1
2
2
3
3
Pins
Clock
Clock
(a)
Data-out
Data-out
Primary Combinational Combinational Combinational Primary

Primary Primary
SR0
SR1
SR2
Combinational
Combinational Combinational
Combinational Combinational
Combinational Output
Input
SR0
SR1
SR2
Logic
LogicBlock
Block Logic
LogicBlock
Block Logic
LogicBlock
Block
Input Logic
11Block Logic
22Block Logic
33Block Output
Pins
Pins 1 2 3
Pins Pins
Data-in
Data-in
Clock
Clock
Mode-
Mode-select
Select
(b)
Figure 10.11. (a) Normal system mode. (b) Scan testing operation.
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When the mode-select is activated for capture of the combinational logic output data,
the results of each logic block are clocked into the scan chain registers at the output nodes
of the block. This overrides any previous data in those storage cells. Once data are entered
in the scan chain, the mode-select signal activates the scan chain, and the results are shift-
ed out of the IC through the data-out pin to the tester. The scan clock controls the shifting
operation. There are various clocking schemes and flip-flop designs, and we illustrate a
simple one in Figure 10.11. The serial mode of testing is inefficient for test vector deliv-
ery, but it reduces the signal test pins to two. Scan circuit DfT is a brute force technique
that succeeded.
Figure 10.12 is an expanded view of a typical scan flip-flop. The mode-select signal
sets the 2-MUX so that it directs data from either the combinational logic block outputs or
from a previous scan cell output path. A MUX mode-select signal of logic-0 directs the
system signal data into a D flip-flop, and a logic-1 asserts the serial scan-in path.
A significant scan circuit property is that the combinational logic block nodes (Q1 to
Qn) respond continuously to each pattern in the registers driving them. The combinational
logic blocks move to a new state with each scan clock pulse. This causes excessive node
toggling during the shifting process. It might make no difference, except that this is a
source of unnecessary heat generation. The sum of the heat generated by the node tog-
gling, the scan cells themselves, and the scan clock tree is large enough to melt test fixtur-
ing if clocked at high scan test rates [52]. This restricted typical scan clocks to the 5–50
MHz range, but thermal reduction techniques have increased the scan clocking to 50–400
MHz. These are described next.
Recent scan designs use techniques to isolate the Q-outputs of the scan registers to in-
hibit or defeat the high nodal activity in the combinational logic blocks during the scan
phase. This can be done with a simple transmission gate inserted between the scan output
nodes and the combinational logic block inputs. Saxena et al. found that the clock tree and
scan cells themselves generated much more heat than the combinational logic blocks [52].
They redesigned their scan elements and their clock routing to reduce the heat generated
by about a factor of two, allowing the scan clock frequency to double for the same heat
generated. This thermal limitation has important effects, since virtually all stuck-at and
delay fault testing is now done with scan chains.
Ideally, SAF tests should be applied at rates from 500 MHz to 2 GHz to keep pace with
modern ICs, but a minor modification of the test allows some timing assessment. The last
clock that shifts the scan test vector to its final position launches a test vector into the
combinational logic block. If the capture clock driving the output scan registers is pulsed
Z1 Z2 Zn
0 0 0
Scan-In 1 D 1 D 1 D
Q Q Q
Mode-Select
Clock
Scan-out
Q1 Q2 ......... Qn
Figure 10.12. Scan flip-flop with MUX to convert between system and scan test mode.
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a short interval later, then some measure of timing is achieved. This is sometimes called
the AC scan technique [39].
The scan registers are tested first by putting them in the test mode. A test pattern of
logic ones and zeros is shifted through the chain, and the tester compares the data-out
pin result to the expected good result. When the scan chains are verified, then the com-
binational logic blocks are tested. This simple test procedure solved the numerically in-
tractable problem of testing sequential elements as they normally exist in an IC. Flip-
flops must be put in known logic states before they can drive combinational logic
circuitry, and when controlled only from the IC primary inputs, it is a numerically in-
tractable problem.
Delay fault test patterns require scan chains for test vector delivery and evaluation. The
two-vector sequence makes the test more complex. The first vector is scanned in, setting
the initial conditions in the combinational logic blocks. Since the second vector must im-
mediately drive the nodes under test to allow for a pass–fail timing measurement, the sec-
ond vector cannot be scanned in. A cleaver trick loads the second vector from the preced-
ing combinational logic block, and then releases it with the mode-select signal into the
scan register. The system clock releases the scan chain contents at the combinational logic
block output. The delay between the launch and capture clocks sets the timing test limit
that the circuit must pass, and this period is set by the system clock. This is called the
“launch from capture” technique. When data are taken after the last data shift, the method
is referred to as “launch from shift.”
Scan circuits can deliver other types of test vectors, such as IDDQ vectors; the ease of
test pattern generation and node control make it ideal. Test patterns are generated rapidly
only for the individual combinational logic blocks.
The development of scan-based test vectors can now be done in hours or days com-
pared to months or years of functional test development. Short TTM (time to market) can-
not tolerate long test development times. The benefits of scan design extend beyond test-
ing. Designers can debug circuits much faster with efficient control and observation of
nodes. Failure analysis can more easily narrow the area of the defect causing failure. Scan
designs are efficient to further isolate the failure region to gates, transistors, and even in-
terconnections. It is virtually impossible with ICs of any complexity to find an alternative
to scan-based testing in order to meet TTM demands and good quality levels.
10.3.2 BIST
BIST (built-in self-test) refers to the process of letting the ICs test themselves [15]. BIST
uses DfT circuits that are intended to reduce ATPG and ATE costs by letting the chip test
itself. A totally self-testing chip has never been demonstrated, but many applications of
partial BIST exist. BIST designs generate test stimuli internally on the IC and then can
run them at system clock rates. It is a way to get high-frequency test patterns inside the
IC. An early BIST system design is shown in Figure 10.13. A test pattern generator called
a pseudorandom number generator (also called a linear feedback shift register—LFSR)
[15] drives a circuit logic block with a few million patterns. The output of the logic block
feeds an evaluation circuit called a MISR (multiple input shift register). The results of the
output patterns are coded on-line into a single register result. The application of built-in
self-test to combinational logic circuits is called LBIST.
One design area that systematically uses BIST is the embedded core memory, called
MBIST. MBIST is relatively easy since x- and y-decoders can be stepped by a counter,
and simple memory patterns can be generated internally bit by bit. The correct result of a
c10.qxd 2/7/2004 2:51 PM Page 297
LFSR - Random Patterns
System LOGIC
Clock BLOCK
MISR
MISR - Evaluator Signature
to Tester
Figure 10.13. Built-in self-test block diagram.
read command is simple to generate and compare with the actual read result. Embedded
core memory could not be adequately tested using the IC primary input pins, since access
to the memory would require too many indirect control instructions.
Figure 10.14 illustrates a simple BIST structure that generates near-random patterns
called pseudorandom patterns. The LFSR takes an ordinary serial shift register and adds
feedback paths through exclusive-OR circuitry (XOR). The XOR gate delivers a logic-1 if
a single high input is present. The all-zeros state (and several ones and zeros patterns) pro-
duces a logic-0 out of the XOR gate.
The LFSR example in Figure 10.14 first clears the register to the all-zeros state, and
then a single logic-1 is placed on the input line. That logic-1 appears at the output of the
XOR, and it is subsequently clocked into the first D flip-flop. Table 10.3 follows the logic
states after each clock. If we pick up on the pattern of the second clock, we see a pseudo-
random sequence of ones and zeros at the Q outputs of the three flip-flops. The ninth
clock result is identical to the second clock, and the tenth clock is the same as the third
clock result, etc. The sequence repeats because the total possible number of states for a 3-
bit register is eight. The patterns show seven clock periods before repetition. The missing
eighth state is the all-zero state. The circuit will not change state if the all-zero pattern is
loaded and then clocked. The total number of logic states before repetition occurs are 2n –
1 where n is the number of flip-flop elements.
The test response of the logic block under test changes after each clock. These large
Output
D1 Q1 D2 Q2 D3 Q3
Input
Clock
Figure 10.14. Clock-driven simple LFSR (linear feedback shift register) that generates pseudoran-
dom vectors.
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Table 10.3. Logic States of BIST LFSR Circuit

Clock XOR Q1 Q2 Q3
0 0 0 0 0
1 1 1 0 0
2 1 0 1 0
3 1 1 0 1
4 1 1 1 0
5 0 1 1 1
6 0 0 1 1
7 1 0 0 1
8 0 1 0 0
9 1 0 1 0
10 1 1 0 1
numbers of responses would be a problem to analyze except the LFSR technique process-
es the output data by compacting it. In effect, each response is “added” to the previous
output, using a MISR (multiple input shift register) (Figure 10.13). The exact value or sig-
nature of the MISR bits is not important since each good circuit will have the same values
in the bits of the MISR. When all LFSR input patterns are clocked through the circuit un-
der test, then the actual output MISR bit signature is compared to the good result. There
are large savings in data storage and analysis.
There are varieties of LBIST construction, particularly in the LFSR construction [15].
LBIST can drive parallel scan circuit chains by using one LFSR, where each Q-output
stage drives one of the parallel scan chains. The output results are then scanned into a
MISR. In Figure 10.14 this means that each Q-output stage drives a scan chain, and the
pattern seen by the chain is the vertical pattern under each Q output in the table. Figure
10.15 shows this now popular BIST style. It is efficient and based on the IBM STUMPS
system [5]. The STUMPS design merges scan DfT with BIST DfT.
The at-speed LBIST circuit has certain weaknesses. Although it can apply virtually the
LFSR
Q1 Q2 Q3 Qn
LOGIC LOGIC
BLOCK 1 BLOCK 2
D1 D2 D3 Dn
MISR
Figure 10.15. BIST schematics.

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whole truth table to a circuit, this voltage-based test does not predict high success for
bridging defects or certain opens. When driven at a maximum clock rate, a LBIST struc-
ture will detect some speed-related defects, but exactly which gate nodes or paths are ex-
amined is not known since none are targeted.
Another problem is the number of shift registers forming the LBIST. These registers
are often modified from those in a scan circuit, and their number can be a problem. Since
the number of possible test vectors is (2n – 1) where n is the number of storage elements,
then registers with more than about 25 elements are of a size for which more vectors can
be generated than are economically justified to deliver. A 30-bit register can generate ⬇
230 = 1.07 × 109 vectors before repeating. This will take valuable test time and illustrates
that LBIST patterns have a limit. Die overhead issues weighed against a virtually un-
known defect coverage is another challenge to overcome in at-speed LBIST. A counterar-
gument for LBIST in complex, modern ICs is that SAF test rates are relatively slow, ex-
pensive to generate, and require large ATE memory.
10.3.3 Special Test Structures for Next Levels of Assembly

Printed wire boards (PWB) and multchip modules (MCM) present special test challenges
that can be partially or wholly solved by putting test structures on the IC I/O pad areas.
The primary purpose of these test structures is to examine the interconnects at the higher
level of circuit integration and, to a lesser extent, the ICs themselves. Electromechanical
probers are too large, and data pathways through the module or board functional I/O pins
are numerically impossible to achieve 100% testing. One solution designs special I/O DfT
test circuits on the chip. We will briefly describe these techniques to complete the test de-
scription.
The IEEE organization exerted considerable good influence when volunteers from in-
dustry and the universities of the world wrote test method standards to solve these prob-
lems. The first one was the IEEE 1149.1 Test Access Port and Boundary Scan Architecture
(BSCAN) standard, approved in 1990. The IEEE 1149.1 standard states that all nonmem-
ory ICs have an input and output pin board test capability [1]. The board or MCM would
have a serial test mode in which test vectors could be scanned in a chain through all I/O
pins on the PWB. The principle is similar to the circuit scan used for testing ICs, but the
primary purpose of the BSCAN is to test the interconnections between all ICs on the
board. BSCAN does this by loading test vectors in the output ports of the ICs, and then
capturing the result of those vectors as they travel to the input pin of another IC. BSCAN
has the ability to shift data, retrieve data, and, secondarily, to drive input vectors into indi-
vidual ICs. Virtually all microprocessors, microcontrollers, and digital signal processor
chips now use BSCAN. More details can be found in [1, 12, 15].
Another IEEE Standard deals with testing mixed-signal components at the board level,
where analog and digital ICs exist along with discrete components. The purpose of the
IEEE 1149.4 Mixed Signal Test Bus Standard is “To define, document, and promote the
use of a standard mixed-signal test bus that can be used at the device, sub-assembly, and
system levels to improve the controllability and observability of mixed-signal designs,
and to support mixed-signal built-in test structures in order to reduce test development
time and costs, and improve test quality” [2]. Special analog boundary modules are insert-
ed at the chip I/O pins. These modules are compatible with the 1149.1 BSCAN test
modes, and have an analog mode that allows communication with analog source currents
and voltages from a tester. More mixed-signal details can be found at the 1149.4 Web site
[2], and in [48].
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To deal with system test complexity, the IEEE 1149.5 Module Test and Maintenance
Bus standard was approved in 1995 to provide an extensible and robust infrastructure for
the communication of test and maintenance messages within a system [3]. Its bus protocol
is designed for the communication of test, diagnostic, and maintenance information be-
tween a system test control module, or master, and up to 250 modules (slaves) within a
system. This infrastructure was created to offer enhanced test solutions at the system level
in terms of extensibility and error handling capabilities. Additional details can be found at
[3] and in [25].
Digital networks are another important area in which testability needs special standard-
ization efforts. The IEEE 1149.6 Boundary Scan Testing of Advanced Digital Networks
draft proposal is an ongoing standard focussed on special features of advanced digital net-
works not adequately addressed by existing standards, especially those networks that are
AC-coupled, differential, or both [4]. It is intended to work in parallel with the IEEE Std.
1149.1 testing of conventional digital networks and in conjunction with the IEEE Std.
1149.4 testing of conventional analog networks. The IEEE 1149.6 project seeks to com-
plement IEEE 1149.4, specifically targeting parallel testing of advanced digital networks,
whereas IEEE 1149.4 focuses on serial testing of more traditional analog networks.
The influence of these standards extends to the system on chip (SoC) test challenges.
Here, embedded modules, such as microprocessors, digital signal processors (DSPs),
RAMs, ASICs, mixed-signal and even RF subcircuits are incorporated into one IC design.
The pin counts of the embedded cores may exceed that of the overall chip, illustrating the
rapid explosion in test complexity. The IEEE P1500 Embedded Core Test Interface stan-
dard proposes common test structure approaches to deliver and retrieve test data from
these complex circuits. More details can be found at the P1500 working group web site at
[46].
Other test-related standards are IEEE 1450 Standard Tester Interface Language (STIL)
for Digital Test Vector Data, IEEE 1532 In-System Configuration, and IEEE P1581 Static
Component Interconnection. For additional information refer to [65].
These brief test standard descriptions are given here since they are an integral part of
dealing with the complexity of testing in deep-submicron ICs. Our primary purpose is to
understand failure mechanisms, but in so doing we will often be dealing with those high-
level structures.
10.4 DEFECT-BASED TESTING (DBT)
DBT differs from fault model approaches. A fault model hypothesizes how a circuit will
fail, and applies test patterns looking for failures of that hypothesis. Defect-based testing
identifies the spectrum of defects that cause IC failure, and then develops test methods
that are matched to the electronic properties of that particular defect class. We will briefly
review the defect classes and mechanisms studied in the past chapters, and then assess
their testability. We discuss each physical defect, analyzing when different failure mecha-
nisms leading to the same defect type may cause different circuit malfunctions. Then we
analyze which are the best options to detect these defects within the different test technol-
ogy solutions.
An example of distinguishing faults from defects at the board level is a pattern of de-
lay faults applied to a board. An IC is found to fail the delay fault test and removed from
the board. Failure analysis shows the IC to be perfectly good, but failing due to an open
connection from IC pin to board. The removal is costly considering the many, small pins
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10.4 DEFECT-BASED TESTING (DBT) 301
involved. A defect-based approach would apply a test method targeted to open (or
bridge) defects that is sensitive to that test. Defect-based testing at the integrated circuit
level is the same. We identify the spectrum of defects that cause IC failure, and then de-
velop test methods that are matched to the electronic properties of that particular defect
class.
10.4.1 Bridge Defects

Physical defects resulting in bridges may be caused by electromigration, gate oxide shorts
due to contamination or oxide wearout, and defect particles or fabrication-imperfection-
caused shorts. Defect particle shorts exhibit low resistance when the mask defect causes a
missing oxide region between two metal lines that is then filled with conducting material.
If the bridging defect particle is a metal sliver between two lines then high ohmic resis-
tances are more probable. Electromigration shorts may not have clean contacts and can
cause higher-resistance bridges. Gate oxide shorts can have ohmic or nonlinear behaviors,
as shown previously. In Chapter 7, we saw that bridges cause intermediate voltages, ele-
vate the quiescent current, and may impact delay. We also saw that the critical resistance is
an important concept when characterizing bridging defects, since it relates the defect re-
sistance to the device properties and its impact on circuit logic behavior. A bridging defect
will impact the quiescent current and/or delay depending on its critical resistance and may
cause a voltage error. Each bridge-defect-induced behavior requires a different detection
test strategy. Figure 10.16 shows microbridge connections for a 110 nm technology.
Only zero-ohm defects between a logic node and power/ground rails will guarantee a
SAF without causing intermediate voltages when activated. A zero-ohm defect between
two signal nodes will always cause an intermediate voltage when activated (different than
VDD or GND) due to the finite resistance and competition of the transistors driving the
shorted nodes. Voltage errors will be observed depending on the relative strength of the
shortened gates and the electrical properties of surrounding logic. Chapter 7 described ex-
perimental results that characterized bridging faults and gate oxide shorts, showing weak
voltages and elevated IDDQ for several defect resistances.
Bridge defects are predominantly sensitive to current-based testing. Voltage-based test-
ing requires that the bridge resistance be less than the critical resistance for the nodes af-
Figure 10.16. High-resistive shorts due to fabrication imperfections (reproduced by permission of

Bob Madge, LSI Logic).
c10.qxd 2/7/2004 2:51 PM Page 302
fected by the defect, and that a sensitive signal path exist between the SAF node and an
output pin. We cannot predict when a voltage-based test will accidentally have a clear sen-
sitive path to a primary output node, and we cannot predict defect resistance. Failure
analysis results show that defect bridges have a wide ohmic range. We know that many
gate oxide shorts are traditionally prone to escape detection by voltage-based tests [19, 60,
70], therefore, a strong risk of bridge defect escapes exists unless current-based test tech-
niques are used.
The impact of bridging defects on circuit speed was also described. Comparative
bridge defect simulations of static voltage testing, speed testing, and IDDQ were done on
many combinations of intratransistor bridging defects in a 2 ␮m technology. The results
are repeated here for a 180 nm technology with near-identical results. Simulations corre-
sponding to a bridge defect across the gate to drain of the upper n-channel transistor in the
2NAND are shown in Figure 10.17, and a sample result is shown in Figure 10.18. The re-
sistance was varied over a wide range and the signal responses are shown. The DC voltage
transfer curve [Figure 10.18(a)] starts to show a significant change in the drain output
voltage when the bridge resistance went below 5 k⍀. At 5 k⍀, the bridge defect drops the
high logic voltage by 17%. When the defect resistance was between 1.5 k⍀ and 1 k⍀, the
circuit failed. We would conclude that the particular bridge and its location in this gate re-
sults in a critical resistance of about 1.5 k⍀. The speed test [Figure 10.18(b)] was also
sensitive to the bridging defect, showing functionally significant timing degradation at a
resistance lower than about 3.5 k⍀. The definition of timing failure becomes smaller as
circuits go beyond GHz frequencies, with clock periods less than 1 ns. When a bridge de-
fect causes a pulse that is too narrow, then flip-flop setup and hold timing and pulse width
requirements might initiate failure.
The IDDQ test results in Figure 10.18(c) showed sensitive detection of the bridge up
to resistances on the order of a megohm (out of the scale). It is the overwhelming choice
to test bridging defects. Bridging defects are the dominant Pareto bin in CMOS manu-
facturing defects. The data indicate that companies that use only voltage-based testing
should experience bridging defect escapes. Speed tests showed a reduced timing degra-
dation sensitivity to the bridging defect, failing at a resistance lower than the DC criti-
cal resistance.
Bridge defects in sequential circuits have additional properties to those in combina-
tional logic. The presence of bridge defects may impact the memory control loop, as ex-
plained in Chapter 7. Chapter 7 also showed that a bridge defect that connects one of the
VDD
V2
V3
Vin2
Figure 10.17. 2NAND gate with an input–output short.

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(a)
(a)
(b)
(b)
(c)
(c)
Figure 10.18. Test method comparison of (a) slow voltage (transfer curve), (b) timing voltage, and
(c) IDDQ.
c10.qxd 2/7/2004 2:51 PM Page 304
nodes of a flip-flop to the output of a combinational logic gate has two responses depend-
ing on the size of the resistance. Assume that there are opposite polarity voltages across
the bridge defect. If the resistance is high, then the combinational circuit has a weak effect
on the flip-flop state, and the correct memory state is held. IDDQ is elevated under this
condition when opposite but weak logic states appear across the defect. If the resistance
becomes small, then the combinational circuit can pull the flip-flop to a strong voltage er-
ror state, since memory transistors are typically designed to be small with little current
drive strength. Both signal nodes are at full logic strength, and IDDQ is not elevated. It is a
paradox that if the resistance is smaller, then there is no IDDQ elevation, but if the resis-
tance is large, then we do see IDDQ elevation [50].
Sequential circuits are now typically connected as scan circuits, and good testing
would use both voltage-based and current-based tests. However, in practice, scan chains
are tested by a voltage-based test that injects a simple sequence of logic-1 and logic-0 pat-
terns. IDDQ tests for bridges in the flip-flops are typically not done for economic reasons.
Some of these bridge defects might be caught as nontarget detections when IDDQ is ap-
plied to combinational logic portions of the circuit.
10.4.2 Opens
Opens have many causes, and may exhibit up to six circuit behavior classes. They may be
due to electromigration, metal voiding, defect particles, fabrication imperfections, or
missing or imperfect interconnect/vias. Partial opens are similar to bridges, exhibiting a
spread of resistance values ranging from the nominal interconnect resistance (the resis-
tance of the line when no defect is present) to virtually infinite resistance. Opens causing
a relative small increase of the nominal interconnect line resistance are referred to as weak
opens, whereas opens providing a significant increase in line resistance (say beyond 1
G⍀) or a total disconnect (Figure 10.19) are referred to as hard or strong opens since the
current through these defects is negligible. The behavior induced by weak and strong
opens and the test methods oriented to each of them is significantly different, so we treat
them separately.
Hard Opens. Open defects require voltage, current, and Fmax testing for best test cover-
age. Floating gates to single transistors are detected with IDDQ tests, whereas floating log-
ic gates affecting two complementary transistors are only detected by voltage testing
Figure 10.19. Hard open causing a total disconnect (reproduced by permission of Bob Madge, LSI
Logic).
c10.qxd 2/7/2004 2:51 PM Page 305
(SAF or delay fault) when the gate voltage floats to one of the rails. Logic gate opens
whose node floats to an intermediate voltage between the rails are detected by either volt-
age or current-based tests. Sequential circuits require both forms of testing.
Tests for the CMOS stuck-open (memory) defect require a two-vector sequence to ex-
amine each of the parallel transistors in a logic gate and another two-vector sequence to
test for the series stuck-open defect. Failure will occur if the drains or source are open, or
if the transistor is otherwise prevented from passing drain current. A 100% stuck-open
test also provides 100% delay fault coverage, but a 100% delay fault test only provides
partial stuck-open-fault coverage. The delay fault test patterns are a subset of the complete
stuck-open fault patterns.
In summary, open defects require a combination of voltage, current, and time-based
tests. Delay fault testing using scan circuits and IDDQ testing are the most efficient combi-
nation. Metal interconnect resistive vias are difficult to test. Metal interconnect defects
are also a subset of the parametric delay class, and will be addressed in the next section.
Weak Opens and High-Resistive Vias. The dominant failure mode of resistive vias
is a functional speed dependency on temperature. A typical IC with a resistive via may fail
a speed test such as Fmax or a delay fault test at a given clock frequency, but pass at that
same clock frequency when the temperature is raised. This glaring failure signature means
that the IC runs faster when hot than cold, defying all our experiences with circuits and
temperature. Present technology ICs always slow down when temperature is raised be-
cause carrier mobility dominates performance, and it declines markedly with temperature.
There may also be power supply amplitude dependencies (VDD).
Why would a defective via allow better speed performance when heated? Figure
10.20(a) sketches a defective via at room temperature, showing metal voids. Figure
10.20(b) models how the voids shrink when temperature rises. Notice that the voided
structure is a via whose volume is constrained by dielectric and interconnect metal. If the
voided metal was unconstrained, then the void would enlarge as temperature increases.
However, the passivation structures around the via outer surface force the metal at the
void surface to grow inward with temperature, reducing the via resistance of the void at
hotter temperatures. The result is a lower resistance via that imparts less delay to the sig-
nal through it. The signal has sufficient margin at this lower-resistance to pass a speed test
that it failed at the cooler temperature [14]. One microprocessor test approach does speed
testing at two temperatures for just this reason [42].
M3
Via
M2
Cold (RT) Hot
(a) (b)
Figure 10.20. Sketches of (a) normal via at room temperature, and (b) defective via at higher tem-
perature. Voids are shown as dark regions.
c10.qxd 2/7/2004 2:51 PM Page 306
The typical intrinsic resistance of a via/contact may range from 2–20 ⍀ depending on
material, liner dimensions and resistivity, annealing steps, aspect ratio, minimum diame-
ters, and process variations. Resistive vias may range from a few ohms to M⍀, as shown
in Chapter 9 [50]. SPICE simulations of via resistances show that logic gate timing fail-
ures occurred only when via resistance exceeded 150 k⍀ to over 1 M⍀ in two studies [8,
42]. We basically cannot detect most resistive vias at a single VDD and temperature setting
using a speed test (Fmax or delay fault). Defect-based studies indicate that speed tests must
be run with a multiparameter test method in order to detect these subtle defects. The rela-
tively slower IC speed capability at lower temperature is the resistive defect indicator, not
Boolean upset. Resistive vias are reliability risks if not detected and rejected at test [8, 14,
42, 69].
Weak opens impact circuit delay only as they increase the RC constant of the signal
path in which the defect is located. Given the nature of the defect, it can only be detected
using test strategies that verify timing. Fmax and delay fault tests are the best candidates to
detect these defects, although the percentage of delay must be significant for the defect to
be detected. Simulation experiments on a 120 nm technology for an inverter driving an
RC interconnect line showed that resistance must experience one order of magnitude in-
crease beyond the critical value to increase delay by less than 4% [72]. Delay test methods
practiced today have a small chance of detecting such weak opens due to parameter varia-
tions along with timing guard bands related to tester timing accuracy.
One might argue that if these weak opens have such a small impact on circuit timing
and cannot be detected using delay fault testing methods, then why should we care about
these defects. The problem of weak opens is that they are high-reliability risks. A weak
open due to a missing portion of metal interconnect causes all the current through the line
to go through a reduced area of via metal and the thin high-resistive Ti material. Current
density increases, and as a result, increased local Joule heating appears and a weak open
at a contact, metal flat line, or via is susceptible to electromigration. A better technique for
our present technology is to burn-in the IC and displace the open resistance value from a
weak to a complete open. Once a hard open is induced, detection probability increases
significantly.
There are reports supporting these failure descriptions for vias. Campbell et al. report-
ed failure analysis on an older technology for a part that failed cold-temperature testing in
the field [14]. The failure was a drain contact in a memory cell. The contact had voids and
eventually electromigrated to a complete open with continued testing in the failure analy-
sis lab. Figure 10.21 shows a timing pass–fail histogram taken at test before the part was
shipped. The test limit at 350 ns gave assurance that the part would function at the system
level if its delay was less than 350 ns. Interestingly, the part that failed in the field was the
outlier at 340 ns. A cardinal rule for a high-reliability product is that you do not ship parts
whose test data indicate that they are outliers. This situation indicated in Figure 10.21 was
a mistake, and root cause corrective action was taken. The difference between the normal
population and the outliers in Figure 10.21 is that the outliers have a defect causing them
to be slower. In this case, the defect was a resistive contact that electromigrated to failure.
The risk of resistive vias in modern ICs is believed to be electromigration or stress void-
ing [69].
Needham et al. reported temperature-sensitive interconnect failures on three Pentium
microprocessors [42]. All ICs failed at cold temperature and passed at hot. Failure analy-
sis found a resistive via, a missing via, and a cracked polysilicon interconnect line. The
study emphasized the inadequacy of best traditional test methods to detect these paramet-
ric defects that cause field failures. Resistive vias are a major reliability concern.
c10.qxd 2/7/2004 2:51 PM Page 307
120
100
80
60
40
20
0
80 100 120 140 160 180 200 220 240 260 280 300 320 340
Time (ns )
Figure 10.21. Pass–fail timing histogram of a sample of parts [14].
Resistive via detection strategies are clear, but there are complexities. ICs must be
speed tested at two temperatures. The complexities lie in the two-temperature measure-
ment procedure and in what will be compared in the speed measurements. Measurement
temperatures should be as separated as much as economically feasible. The wider the sep-
aration, the more sensitive the speed tests. Wafer hot chucks can easily test from
125°C–140°C which is a good upper temperature. The cold-temperature tests can be done
around room temperature, and the logical place to do this is at the package level. If the
temperature is taken below the dew point, then water condenses, making the test more ex-
pensive. Testing at temperatures below 0°C is routinely done for military and other high-
reliability parts, but requires an enclosure for the IC through which dry, cold nitrogen is
blown. These more expensive, very cold temperature measurements are fortunately not
necessary for resistive via testing.
Both temperature tests will not be done at the same time as the wafer probe or package
tests. The thermal delay time to reach another temperature and the I/O pin thermal conti-
nuity issues with the tester suggest that one of the temperatures be done at wafer probe
and one at package level. The tests at two temperatures may also be done at pre- and post-
burn-in. That introduces the challenge of how to keep track of the die being tested. The
second temperature test must compare its result with the other temperature measurement
on the same die, and match the dies after they are cut and packaged from the wafer. Intel
reported a technology that burns a die identification code into each die at the wafer probe
test [49]. This identifies the die throughout its product life. Other companies use a similar
strategy that has many uses in test and failure analysis. Two-temperature testing requires
this or any equivalent technique that allows die identification throughout the test process.
10.4.3 DBT Summary

Table 10.4 summarizes many of the defect mechanisms that can appear in CMOS ICs. The
information is taken from the past section and previous chapters. Defects are grouped into
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Table 10.4. Physical Defects, with Failure Mechanism Source and Induced Circuit Malfunction
Bridging defects Open defects Parametric defects
Circuit malfunction
Source
Failure Physical Intermediate Elevated Floating Memory Delay Crosstalk VDD/GND

mechanism defect stuck-at Voltage IDDQ node effect impact impact bounce
Metal short rarely always always no FTC probable no no
Interconnect
Electromigration
reliability
Broken rarely probable very MP probable if small no no

metal likely cracks
Metal void rarely probable very MP probable no no no

Metal stress
likely
reliability
Oxide
Oxide GOS rarely MP always no no very no no

wearout likely
GOS rarely MP always no no very no no

reliability
Device
Hot-carrier likely
injection
Vt shift no no no no no MP no no
Short probable always always no FTC very no no

Defect particle/ likely
fabrication
imperfection Open rarely probable very MP probable no no no
likely
Open rarely probable very MP probable if small no no

Via/interconnect likely cracks
problem High R no no no no no yes no no
Process Fabrication
line/via
Process GOS rarely MP always no no very no no

control likely
Vt shift no no no no no MP no no
IDL variation no no no no no MP very rarely

likely
Interconnect no no no no no MP rarely very

Process ␳ shift likely
variation
Metal width no no no no no MP very very
shift likely likely
Leff shift no no no no no MP rarely rarely
Weff shift no no no no no MP rarely rarely

Note: MP: most probable; FTC: few topological cases.
two large categories relating to reliability problems (interconnect, oxide, or device), or

manufacturing imperfections/contamination (particle defects, via problems, process con-
trol, or parameter variation).
In each case, we identify the mechanism responsible for the defect, and the impact on
the circuit behavior. In some cases the same defect type can have different failure mecha-
nism roots. An open due to electromigration or a particle defect can have a different im-
pact on the circuit behavior. A small electromigration open may lightly impact timing due
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10.5 TESTING NANOMETER ICs 309
to tunneling current, whereas a particle defect open may not cause that behavior. There are
three basic types of defects: bridging defects (black background and white type in Table
10.4) as those inducing an undesired connection between two or more nodes; open defects
(heavily shaded cells and white type)—those causing an interconnect to be broken or
highly resistive; and parametric defects (lightly shaded background and black type)—
those that cause a variation of an electric parameter either for devices or interconnects.
A defect-based analysis and testing plan depends upon the particular product and the
company’s test capability. However, once tests for gross defects have been applied, a gen-
eral logic test sequence to optimize early detection of the most probable defects described
to this point might be to do
앫 Scan chain testing with a sequence of logic ones and zeros.

앫 Wafer-level IDDQ testing to detect bridge and certain open circuit defect classes.
앫 Wafer level delay fault testing for gross timing failures, and to quantify detection of
two of the six open classes missed by the IDDQ test: the transistor pair on/off defect
and the stuck-open defect.
앫 Fmax testing is difficult at the wafer level, but can be done for some ICs, especially if
VDD is reduced to a minimum value.
앫 At-speed package testing at cool temperature. Resistive vias and contacts have high
probability of detection by comparing speed capability, using either Fmax or delay
fault tests.
The exact sequence of the tests and how they are economically implemented are compa-
ny- and part-specific. However, the thought process of electrically evaluating the expected
CMOS IC defects, and then applying a specific test to detect that targeted defect remains
the core of defect-based test practice.
Faulty behaviors due to parameter variation are listed at the end of Table 10.4. These
defects mainly impact delay, and/or aggravate noise and crosstalk problems. Parameter-
variation-induced defects appear mainly in deep-submicron and nanometer technologies
as technology nodes get to 90 nm and below. These effects are discussed in detail in the
next section.
10.5 TESTING NANOMETER ICs
We will relate the nanometer effects of device and interconnect scaling to the IC parame-
ters and higher speeds that impact the test and diagnosis functions. We then discuss the
difficulties of the several test methods in dealing with defect detection in this environ-
ment. Most defect properties typically do not change as ICs are scaled, but the efficiency
of the available test methods does. After analyzing these limitations, we will describe a
number of test methods that were proposed in the few past years to deal with nanometer
effects on testing.
The term deep-submicron technology refers to CMOS ICs whose transistor channel
lengths are below about 0.5 ␮m, whereas nanometer ICs refer to dimensions approximate-
ly below 180 nm, at which noticeable changes appear in the physical characteristics of the
transistors and in the chips themselves. Technology scaling follows Moore’s law, in which
the number of transistors per die doubles about every two years [26]. The goal of scaling
for each technology node is to reduce gate delay by 30%, double transistor density, and re-
c10.qxd 2/7/2004 2:51 PM Page 310
duce energy per transition by 30% to 60% [13, 18]. The industry has gone through gener-
ations of planned decrease in critical dimensions in the deep-submicron era from 350 nm,
250 nm, 180 nm, 130 nm, 90 nm, to 60 nm, and below. We call these technology nodes;
each node usually demands new fabrication and test equipment and design tool capabili-
ties. The nodes are defined by the minimum interconnect pitch of a DRAM divided by
two [26]. Pitch is defined as the minimum metal width plus the minimum spacing be-
tween metal lines. DRAMS are the standard, since that technology has led the micro-
processor and ASIC technology by about 2–3 years. The node geometric decrease derives
from multiplying one generation by 0.7 to get the next size reduction (180 nm × 0.7 ⬇
130 nm, etc.). The 0.7 scale reduction on a side is significant since die area will halve.
Each new technology node can place the same amount of transistors in half of the area.
However, the true die size is actually growing by 14%–25% per technology node as more
logic per chip is included [13].
At the smaller geometries, memory ICs have grown to billions of transistors, and
ASICs and microprocessors to tens and hundreds of millions. The via counts are now in
the billions, so that one effect on testing is simply the raw size of the ICs in the nanometer
world. A staggering number of circuit structures must be examined in the test process.
Test development must include a plan to generate test patterns quickly and cheaply. Sud-
denly, virtually all companies embrace scan DfT, whereas previously, individual compa-
nies might have viewed DfT as a cult practice. Historically, loud complaints have been
that too much area was alloted for DfT. That extra area could be equilibrated to construc-
tion of another fabrication plant in some high-volume companies, just to make up for the
lost space on the wafer. DfT also “slows the part down.” However, the economics of test
development and practice and diagnostics are overwhelming if primary pins are the sole
entry and exit points for test patterns. Although scan DfT reduces the complexity of the
task, unsolved challenges still remain in the testing and diagnosis of deep-submicron ICs.
A second challenge is the subnanosecond timing of these circuits. Testers must test
leading edge performance ICs using the previous generation chip. ATE must place timing
edges with picosecond resolution, overcoming the challenge of timing skew on several
hundred signal pins. The applied test vector files, the measured response, and the expect-
ed response requires large data storage and retrieval capacity. The old standard of less than
a second for an IC test has given way to minutes. Gigabit memories may take up to 30
minutes of test time, and a single wafer test may take an entire 8-hour work shift.
Another challenge is managing the test process for ICs with up to 1,000 I/O pins. Pla-
narity must be exceedingly good for test probes to make assured electrical contact at the
wafer probe. Open circuits at wafer- and package-level testing are a growing menace. The
packages are typically flip-chips that put arrays of solder-interconnection balls on the
backside of the chip.
Testers now deal with deep-submicron ICs generating from 20–200 W of power. Wafer
probing and package sockets have a thermal differential interface to the chip on the order
of 100°C, and the tester power current delivery can be 100 A or more. ATE companies are
under pressure to create equipment to handle these environments and produce a tester
product that is reliable, easy to operate, “affordable,” and rapidly developed to keep pace
with the technology nodes.
Another deep-submicron feature is the shortened time between technology nodes and
the intense time-to-market pressure. Technology nodes have been achieved at a pace of
about one every two years [26]. In this interval, the characterization and test development
of the part must not lag behind the fabrication. The test engineering method must rapidly
c10.qxd 2/7/2004 2:51 PM Page 311
get it right the first time, or face large error costs. Defect-based testing practice forces me-
thodical planning and best-test strategies.
Products have a wide range of cost, reliability, and performance needs. It is said that
companies often pick one of these three as a priority and then try to manage the other two.
Our discussion will deal mainly with the high-performance ICs, but we are not forgetting
that the majority of products in the world created using nanometer technologies do not
deal with GHz speeds or 200 Watt power supplies. Many high-performance ICs are high-
volume products and this aggravates test problems to the extreme.
10.5.1 Nanometer Effects on Testing

Chapters 7 and 8 looked at bridge and open defect properties, mostly ignoring the para-
metric variance effects of modern circuits. This provided a clean look at how defects be-
have when undisturbed by the effects caused by the inability of manufacturing to achieve
tight tolerances of key parameters in the deep-submicron era. It gave us a baseline of
knowledge to assess the changes. Defects in deep-submicron and nanometer ICs do not
lose their class distinctions. Bridges, opens, and parametric delay failures exist with no
new categories; however, a shift in the defect spectrum has occurred. Bridges are still
dominant in most technologies, but open circuits and parametric delay failures are grow-
ing in number, particularly as they relate to vias, contacts, and interconnect line noise.
This means more possible defects for which we cannot guarantee detection. We know that
parametric delay failure sites will escape testing. Bridge defect escapes will grow because
we are losing sensitivity in the current-based tests. The electronics of defect responses
have changed little, so we will examine the effects that deep-submicron technologies have
on the test method.
Spread of Parameters. Deep-submicron structures do not affect testing and diagnosis

just because they are necessarily small. They primarily impact testing because the manu-
facturing parameters are not tightly controlled. Wide variances exist in Leff, Weff, Vt, Ioff,
and IDsat, as shown in Chapter 9, and these variances give a wide distribution to the perfor-
mance of each IC. As a first order, test limits must be set at the worst-case values for the
intrinsic part performances. The background variance and amplitude leakage that increase
with technology scaling limit the effectiveness of IDDQ testing as introduced earlier. New,
sophisticated IDDQ and low-VDD-based testing techniques are in use to extend these tech-
niques to nanometer technologies.
Propagation delay and IDDQ test limits must deal with the wide spread in values from
intrinsic ICs described in Chapter 9. Figure 10.22 shows two normal plots with arbitrary
units on the x-axis. The x-axis may represent propagation delay Tpd, memory access time,
Fmax, IDDQ, or some other test parameter for intrinsic material. The narrow curve has a
mean of 50 and a standard deviation of 4 units. This curve might represent older, long-
channel technologies, for which parameters were more tightly controlled. The wider curve
symbolizes the nanometer technologies. The mean in the wider curve is still 50, but the
standard deviation is 10. If ± 3␴ test limits are followed, then the nanometer ICs have a
greater tolerance for pass–fail. Test limits must accommodate the weakest ICs in the dis-
tribution. This means that defective ICs can be buried at one end of the spectrum, but still
not be detected as a defect. The better-performing ICs in modern technologies need a test
limit adjusted to their level and not to the weakest level in the population.
The variance gets larger as transistor channel lengths and widths get smaller (Chapter
c10.qxd 2/7/2004 2:51 PM Page 312
10
σ=3
Normal Percent
6
σ=10
0
0 20 40 60 80 100
Arbitrary (FMAX, Delay, IDDQ)
Figure 10.22. Effect of parameter variance on test limits for normal distributions.
9) . Optical lithography has lost its ability to maintain accurate dimensions for Leff and
Weff. Vt is affected by changes in Leff, and Weff, and also by ion implant fluctuations [11].
These parameters and IDsat vary widely from die to die and even among transistors within
the same die. The wide range of clock speeds available from a company’s technology arise
from these statistical variations at the transistor level, not from design intent. These varia-
tions weaken testing, and test engineers and failure analysts are left to deal with it. The
major test methods affected are IDDQ, delay fault testing, Fmax, and other at-speed testing
methods that use limits characterized from the ICs.
Background Current Increase. MOSFET miniaturization causes high electric

fields, and the maximum supply voltage is limited by gate oxide wearout and power con-
straints. Voltage scaling reduces transistor gate drive (VDD – Vt), which is partially com-
pensated for by lowering Vt. The threshold voltage is scaled about 30% per technology
node to compensate for VDD reduction and to maintain a sufficiently large VDD/Vt ratio.
The final result of the scaling process is an Ioff increase of about 5× per technology node
[18], since the off-state current depends exponentially on Vt. Figure 10.23 shows the off-
state current versus temperature, and its evolution per technology node as projected for
deep-submicron ICs [13].
Leakage current can significantly contribute to the total power dissipated. Transistor
off-state leakage is a primary design parameter for large deep-submicron ICs whose qui-
escent currents can reach several Amperes. Dynamic power (the power related to CMOS
through current and charge and discharge of internal nodes) is the other major power com-
ponent. The leakage power contribution is shortly expected to increase to about 50% of
the total circuit power at high temperatures, as shown in Figure 10.24 [13]. The increase
of leakage current variance and amplitude impacts the effectiveness of quiescent current
testing since the intrinsic background may mask the current contribution from defects.
Radiation-Induced Soft Errors. Soft errors (SEs) are caused by alpha particles
emitted by packaging materials, and high-energy neutrons resulting from cosmic rays
c10.qxd 2/7/2004 2:51 PM Page 313
104
0.10 µm
103 0.13 µm
Ioff (nA/µm)
0.18 µm
102
0.25 µm
101
100
30 40 50 60 70 80 90 100 110
Temp (oC)
Figure 10.23. Estimated subthreshold leakage current of deep-submicron transistors [13].
colliding with particles in the atmosphere. These energetic particles traverse through the
silicon bulk, creating minority carrier charges that can be collected by source/drain dif-
fusion nodes and alter the logic state of the node. The existence of this radiation has
been known for more than 50 years, and the capacity for this radiation to create what is
called transient faults has been studied since the 1980s. Traditionally, memories have
been victims of soft errors because smaller transistors are used in this circuitry, which is
the densest part of the system. Additionally, when a soft error flips a memory bit (re-
ferred to as a single event upset, or SEU), then it provokes a state change that may im-
pact the system-level behavior. This problem is handled in memories by adopting special
error-detecting codes that allow SEU detection and posterior correction, or by special
hardened packages in space applications (where radiation levels can be two orders of
magnitude higher [24]).
As technology scales, the total charge required to toggle a node from particle-induced
charge injection is the node charge Q = C × V, where both the node capacitance and volt-
age decrease at each technology node [55]. Recent work predicted that soft error rates
50
Subthreshold Leakage Power (%)
40
30
20
10
0
0.18 µ 0.13 µ 0.1 µ 0.07 µ 0.05 µ
Figure 10.24. Circuit-level subthreshold leakage power contribution as percentage of total power
[13].
c10.qxd 2/7/2004 2:51 PM Page 314
(SER) could increase nine orders of magnitude from 1992 to 2011, and that the impact of
SER on combinational logic will be comparable to that of (unprotected) memory [55].
The impact of radiation particles on combinational logic depends on the logic type (static
or dynamic) and the clock speed [54]. The main reasons for this impact on combinational
logic in nanometer technologies comes from the smaller critical charge required to flip a
node. In addition, the smaller and faster transistors can help propagate a SE-induced
glitch to a memory element and cause a permanent error. Moreover, higher operation
speed of processor pipelines allows latches to cycle more frequently, with a higher proba-
bility of latching one of these SE-induced glitches.
There are no definite solutions to ensure combinational logic SE reliability, since the
time or logic redundancy techniques used in memory cannot be adopted directly in ran-
dom logic blocks [55]. This problem remains yet another challenge for reliability of
nanometer technology ICs.
Impact of Nanometer Effects on Traditional Test Methods. The three dominant

nanometer technology effects presented in the previous section pose a challenge to IC
testing and verification. In the next subsection, we analyze the impact of these effects on
the test techniques presented earlier in this chapter, and we present various test method-
ologies that have appeared in the past few years to specifically deal with these nanometer
technology problems.
10.5.2 Voltage-Based Testing

Stuck-at-Fault Testing (SAF). The stuck-at-fault test is unique in that its actual
measurement is reasonably unaffected by all the parametric variance of the deep-submi-
cron technologies. Its only parametric relation to scaling is in the analog voltage setting
of digital test parameters VOH and VOL. SAF testing is a straightforward, low-frequency,
Boolean test that can be done efficiently as long as scan circuits deliver the vectors.
However, SAF testing uses large amounts of tester memory in deep-submicron ICs to
store the test vectors and their correct responses. The relatively slow scan delivery of
test vectors in the 50–400 MHz range is a deficiency. Comparative test method studies
show that SAF testing has the weakest defect detection efficiency of the major test
methods (Figure 10.10) [39, 44]. In summary, we find the SAF still in common use be-
cause test patterns can be generated for scan-designed ICs. ATE has over 30 years ex-
perience in testing with the SAF. The reasons for continued dominance of SAF testing
may have to do with habit, convenient test tool availability, inexperience with delay fault
testing, and lack of DBT knowledge.
Delay Testing (DF). Transition delay fault testing has test limit challenges caused by
parameter variations on delay, since DF testing must address problems inherent in mea-
suring delay for a large variety of paths. Intrinsic propagation delay varies considerably
for each path, and delay fault testing is not close to a capability that adjusts for a different
propagation delay test limit in each path under investigation. When a single delay test lim-
it is set, such as the operating clock period, it must then guardband against tester noise as
well as die and intrinsic wafer variations. The delay fault is then limited to gross timing
failure detection and not to the finer-resolution delay anomalies. To cope with these prob-
lems, several authors are investigating the adoption of statistical models for path selec-
tion, trying to maximize the probability of covering critical paths or detecting defects
c10.qxd 2/7/2004 2:51 PM Page 315
causing delay disturbances. Statistical methods for timing analysis have been around since
the mid-1980s [62] and seem to be inevitable in the near future to predict delays in ICs af-
fected by the statistical process variations and noise sources.
Delay fault testing should replace SAF testing, since it targets more defects, and the
SAF test set is a subset of the transition delay fault test set. The availability of delay fault
test generator tools is encouraging.
Fmax Testing in Deep-Submicron ICs. Fmax testing remains an essential IC test

method now and will be in the near future. There is no replacement test that can bin the
ICs for speed prior to customer delivery. Its weaknesses include no quantifying property
to determine how good the Fmax test is, and developing the large number of test vectors to
reflect activity in critical paths. This is not an automated process. The Fmax test is expen-
sive in tester time, since the tester must do an iterative search for the minimum functional
clock period.
Critical Path Timing Test. The critical paths of an IC are identified, and each can be
evaluated for propagation delay. These path numbers may be on the order of 1000–2000,
and their identification can be difficult. This test is quite useful, but has its own problems
with parameter variation. The advanced technology ICs are reported to show die-to-die
variation on the order of the critical paths due to parameter variations [45].
10.5.3 Current-Based Testing

IDDQ testing has made significant progress in working around the background leakage
variance and amplitude problems. At the end of the 1990s, alternative methods to single-
threshold IDDQ testing were investigated, and several techniques are available today that
implement current-based test techniques in a production environment. We introduce these
pioneer techniques and focus on those presently being used in production testing.
Single-Threshold IDDQ. This test technique suffers from die parameter variation, as
does delay testing, with the added disadvantage of increased intrinsic background leak-
age amplitude. This would not be a real problem in the absence of parameter variations,
since the exact value of predicted intrinsic IDDQ could be removed from the measure-
ment. Also, the ±1% accuracy of an ATE current measurement is often not accurate
enough for Ampere-level currents. It is the combination of background current ampli-
tude increase and parameter variation that makes single-threshold IDDQ unaffordable in
nanometer ICs.
Current Signatures. This technique relies on a concept that does not compare mea-
sured IDDQ values to a single pass/fail threshold [21, 22]. The method measures the quies-
cent current values for the whole test vector set (a set that contains a number of test vec-
tors that completely exercise the circuit) and then generates a current signature by
rank-ordering all the IDDQ measurements from the smallest to the largest value. The
method looks for jumps in the current signature. A smooth plot of the current value indi-
cates a fault-free circuit, whereas significant jumps or discontinuities in the current signa-
tures indicate faulty behavior.
This technique introduced a new concept in the adoption of quiescent current testing
since a given circuit is not rejected at the first failure indication during testing, but only
c10.qxd 2/7/2004 2:51 PM Page 316
after all tester data are collected. The main limitation of this posttest data processing tech-
nique is related to its sensitivity to parameter variations since it requires setting a pass/fail
threshold not for the absolute IDDQ value, but for the magnitude of the jump at the signa-
ture. This threshold should be valid over a range of process variations.
Delta-IDDQ. Thibeault proposed a similar conceptual method called delta-IDDQ, in which

the test observable is not the absolute IDDQ value, but the differences in IDDQ among suc-
cessive test vectors [61]. This difference is treated probabilistically to determine if a given
circuit is defective or not. Delta-IDDQ was applied to commercial memory and processor
circuits with a mean leakage current of 2 mA [41]. These circuits were not appropriate for
single-threshold IDDQ since the single-threshold IDDQ 3 ␴ limit was 22 mA, posing a sig-
nificant IDDQ yield loss. The study showed that for a reduced population of samples sent to
burn-in, more than 50% of the units that failed delta-IDDQ but passed functional testing
and single-threshold IDDQ became functional failures after the experiment. Delta-IDDQ has
a parameter variation limitation similar to current signatures. An absolute threshold for
the delta value must be set, and this can suffer from variation in the quiescent current from
die to die or lot to lot.
Current Ratios. A third test technique called current ratios was proposed by Maxwell
et. al., and uses a concept similar to current signatures with the added features of tolerat-
ing parameter variations [40]. This is done by setting a specific quiescent current limit for
each die for any vector of the test set. This limit is computed individually for each part
once the first minimal quiescent current vector measurement is taken. Therefore, the first
IDDQ value (obtained from the expected vector giving the smallest intrinsic IDDQ value) es-
tablishes a range of quiescent current values that are acceptable for that part.
This technique is based on the observation that the slope of the rank-ordered quiescent
current signatures for dies having significant different absolute IDDQ values are similar, as
shown in Figure 10.25 for two dies. The die leakages varies by about 5×, but the slopes are
similar. The test limit for a given die is determined from the ratio of the maximum to min-
Current in ␮A
Current in ␮A
Figure 10.25. Current signatures for two dies having significantly different absolute IDDQ values
[40].
c10.qxd 2/7/2004 2:51 PM Page 317
imum IDDQ value and the slope of the rank-ordered currents. This was observed to remain
reasonably constant for all the devices no matter the mean of the IDDQ measurements for
each die. This ratio is determined from a small population of devices having as wide a
spread of current as possible, and is done through an iterative process in which the maxi-
mum current is plotted versus the minimum current for all dies. This plot is a straight line
and provides a slope and an intercept value. Outliers are iteratively removed from the re-
gression line, and the min to max ratio is computed. Once the ratio is established, the out-
lier regions are set to account for uncertainties in the measurement process. The minimum
current is found by characterizing the response of many dies, and identifying the vector
that typically gives a minimal reading for each die. The maximum current of a die under
test (DUT) is computed from the measured minimum IDDQ vector using the previously
computed slope values.
This technique overcomes the two main limitations of other quiescent current tech-
niques since it tolerates both high background currents and parameter variations. Another
benefit of this technique is its suitability for production testing environments since the test
limits are adjusted for each part once the first measurement is taken.
Nearest Neighbor Statistics. The previous techniques achieved IDDQ variance reduc-
tion by considering different die patterns. Another test method reduces the IDDQ variance
using die nearest neighbor statistics to identify die outliers [16, 56]. This technique can be
applied not only to IDDQ data, but to any test data that changes continuously over the wafer
or lot.
This method is based on the identification of residuals whose variance is larger than
the IDDQ variance. The residual is the difference between the actual measured IDDQ value
and an estimate of this value. For the results presented in [16] IDDQ was an average of the
quiescent current measured for a number of vectors on the tested die, whereas the esti-
mate was the median of the IDDQ values computed from at least eight die closest to the
tested die. The median was used instead of the mean since it reduces the effect of outliers.
Daasch et al. presented production data on six wafers, showing the merits of this tech-
nique, that bins the dies according to the leakage measured from neighbors [16]. Some
dies that were classified as faulty from a single-threshold IDDQ technique were classified
as good since they belong to a high-IDDQ neighborhood, whereas other dies with an IDDQ
value below the single-threshold limit were considered faulty as their leakage was abnor-
mally high when compared to dies in their proximity. Nearest neighbor test assumes that
defects and fabrication variation cluster on the wafer, so that dies in close proximity on
the wafer will have similar average chip values of Leff, Vt, IDDQ, and Fmax. The measure-
ments of Fmax and IDDQ are referenced to the nearest eight neighboring chips to establish a
level of performance consistent with nearest chips. An expression used is to distinguish
“bad dies in good neighborhoods, or good dies in bad neighborhoods.” More sophisticated
techniques also correlate parameters in the rows and columns. The nearest neighbor test
method was demonstrated using IDDQ, VDDmin, and Fmax, but it has general applicability to
other variables. It is a valuable tool in parametric failure detection, especially as it evalu-
ates IC data at varying VDD and temperature. Nearest neighbor testing is a production test
method at LSI Logic Corp.
The method proposed in [16] was generalized in [17] in terms of neighborhood selec-
tion. The die selection used in [16] to compute the estimate was based on data from the
eight neighboring dies adjacent to the die under test. This method of selecting the die by
only considering position works well when the data pattern varies smoothly. In some
c10.qxd 2/7/2004 2:51 PM Page 318
cases, data can follow systematic stepper patterns, and in general, test data may show a
combination of both smooth and step patterns. This variation, although systematic within
a wafer, changes from lot to lot, making variation difficult to predict. To cope with this ef-
fect Daasch et al. presented a method to select neighborhood dies from the data itself, in-
stead of considering physical location only [17]. This technique measured data from a
0.18 ␮m technology using 75 wafers and 25,000 dies. The results demonstrated signifi-
cant IDDQ variance reduction, and outlier detection was improved. The possibilities of ap-
plying this method to production testing were demonstrated on a single lot by considering
a single IDDQ measurement per die.
In summary, the nearest neighborhood, posttest statistical analysis method implement-
ed by Daasch and Madge is a powerful demonstration of adjusting IDDQ limits to the qual-
ity environment that each die sees in its immediate vicinity [17].
10.5.4 Delay Testing Using Statisitical Timing Analysis

Parameter variations and noise-induced fluctuations aggravated in nanometer technolo-
gies significantly impact the variation in the delay of signal paths from die to die and
within dies. There can be some deterministic components in the parameters influencing
delay, such as topological dependencies of device and interconnect processing or lithogra-
phy correlation. However, their complexity in large designs, together with the impact of
environmental effects (such as supply voltage fluctuations, temperature, etc.), and the ex-
istence of real random variables (random doping fluctuation) requires us to treat these
variations as random. This creates the need for statistical timing models whose gate delays
are modeled as random variables.
These approaches have been applied to timing analysis and delay testing to capture
random effects and their sensitivity to internal signals subjected to a given type of defect
or variation source. There are several approaches used to incorporate statistical methods
in delay testing, Liou et al. showed how these methods are effective in selecting the most
probable critical paths [34]. The problem of determining the delay pass/fail limit on the
tester is still unsolved.
10.5.5 Low-VDD Testing

Chapter 4 discussed the strong influence of the supply voltage on the gate delay for an in-
verter. The relationship applies to any CMOS gate under test and, therefore, to the overall
IC speed. The need for alternative and/or complementary parametric test methods to IDDQ
in submicron ICs motivated the investigation of the test effectiveness in lowering the IC
supply voltage to expose the presence of weak defects by correlating VDD to timing [23].
The latest concept lowers the supply voltage at a given clock frequency, and measures the
minimum value of the supply voltage at which the circuit will still function. This tech-
nique is referred to as VDDMin [64]. The reduction of the IC supply voltage decreases the
drive strength of the transistor gates, making them more sensitive to defects impacting
timing, such as resistive shorts or weak opens.
The VDDMin test increases the critical resistance of a bridge defect, and increases the
test efficiency of voltage-based tests. Example 10.5 analyzes this observation for one cir-
cuit example. Tseng et al. showed that the VDDMin value for weak chips was higher than
for the fault-free ones, and that this technique might detect bridging shorts, gate oxide
shorts, threshold voltage shifts, and tunneling opens [64]. An example follows that illus-
trates the change in Rcrit as VDD is lowered.
c10.qxd 2/7/2004 2:51 PM Page 319
왎 EXAMPLE 10.5
Calculate Rcrit in the bridging defect example (Figure 10.26) when the circuit is
tested at VDD = 1.5 V and then at 1.0 V. Kn = 100 ␮A/V2, W/L = 2, Vtn = 0.4 V, and
VTL = 0.5 VDD.
VDD
R
Vin Vout
Figure 10.26.
(a) VDD = 1.5 V and VTL = V0 = 0.75 V, so the n-channel transistor is in non-
saturation, and the p-channel transistor is off. Therefore,
IDn = (100 ␮A)(2)[2(1.5 – 0.4)0.75 – 0.752] = 217.5 ␮A

(1.5 – 0.75)V
Rcrit = ᎏᎏ = 3.45 k⍀
217.5 ␮A
(b) VDD = 1.0 V and VTL = V0 = 0.5 V, so the n-channel transistor is in nonsat-
uration, and the p-channel transistor is off. Therefore,
IDn = (100 ␮A)(2)[2(1.0 – 0.4)0.5 – 0.52] = 70 ␮A

(1.0 – 0.5)V
Rcrit = ᎏᎏ = 7.14 k⍀
70 ␮A
The increase in critical resistance at the lower VDD value approximately doubled,
and that is good for voltage-based testing. However, detection of bridge defects
by the voltage-based test is still not a target test. This detection relies on the
chance that a sensitized path exists, and that the defect resistance lies below Rcrit.
Nevertheless, increases in test efficiencies for advanced-technology ICs are a
trend reversal. 왎
The drawbacks of this technique for production testing relate to the increase in test time,
and the cost to do a search test for the minimum voltage at which the die still passes the
test [32]. To overcome the search-time penalty of the VDDMin test, a three-step process
was proposed based on VDDMin to detect outliers and a posterior statistical process for
outlier screening [35]. This technique uses a reduced vector set instead of the full vector
set to search the VDDMin value, and then applies the full set of test vectors to the die using
the minimum voltage found in the previous step. Depending on the fault coverage, out-
liers are screened using statistical postprocessing methods. Experimental results showed
that VDDMin yield fallout varied from 0.2–0.8%, depending on product complexity, and
c10.qxd 2/7/2004 2:51 PM Page 320
approximately 20% of the outlier dies showed a MinVDD positive or negative shifting.
Some specific defects were found during failure analysis, including a resistive via and a
tungsten stringer (bridge).
10.5.6 Multiparameter Testing

The test techniques discussed until now are based on monitoring one test observable and
applying data analysis to reduce variance and set an adjustable limit, as a method to bin
parts subjected to a spread of parameters. Another solution to distinguish good from bad
devices in a population with large variance is to exploit the correlation of different circuit
parameters owing to fundamental physical properties of devices and interconnects. These
techniques started by correlating two parameters, such as speed and leakage, to establish
the two-parameter techniques. This can be generalized to multiparameter techniques
where more than two variables are adjusted.
Fmax versus IDDQ Two-Parameter Testing. Keshavarzi et al. showed that outliers
could be pulled out of intrinsic variations by manipulating more than one variable to find
a sensitive limit [29]. Single-threshold IDDQ testing was based on setting a single pass/fail
threshold independent of other parameters of the circuit. For a given population of cir-
cuits, high-leakage parts are intrinsically faster since their transistors have smaller Vt’s and
shorter Leff’s. This does not necessarily correspond to a defective IC, but to a faster one,
since larger Ioff implies larger IDsat if the device is working properly. Keshavarzi et. al. ob-
served this property and plotted the static current leakage versus Fmax for a large number
of circuits, obtaining the graph shown in Figure 10.27. Data clearly show a trend in which
leaky parts run faster, whereas slower parts exhibit a smaller leakage. The technique of
combining two parameters to establish pass/fail criteria is a good solution to avoid yield
loss from valid parts. This test method is a low-cost alternative for saving fast, intrinsical-
ly leaky ICs while discriminating against defective ones.
Figure 10.27. IDDQ versus maximum frequency [29].

c10.qxd 2/7/2004 2:51 PM Page 321
(a)
(b)
Figure 10.28. (a) Leakage current versus frequency for six different temperatures. (b) Defect de-
tection using IDDQ at different temperatures [29].
Beyond Two-Parameter Testing. The distribution of two parameters can be altered

by a third or fourth parameter to extract outliers in the original distribution. Several vari-
ables can be considered for multiparameter testing, such as Fmax, VDD, VDDMin, tempera-
ture, reverse body bias, IDDQ, and ⌬IDDQ. Reverse body biasing (RBB) of the source and
body terminals increases the transistor threshold voltage, decreases intrinsic IDDQ, and
slows the chip. Keshavarzi et al. found that temperature was more effective than RBB for
distinguishing defects in a 180 nm technology [29].
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Figure 10.28(a) shows normalized IDDQ versus Fmax distributions for six temperatures
[29]. The normal variations at each temperature in the data do not overlap. Figure 10.28
shows the test discrimination in the presence of extrinsic leakage. A 1 M⍀ resistor was in-
serted to emulate a low-impact bridge defect between the power rails. Without this resis-
tance, the circled IC data point dropped 36× with temperature cooling from 110°C to
27.7°C. When the emulated defect was attached across the power lines, the drop in IDDQ
was only 1.6×. That value was well outside of the intrinsic distribution at room tempera-
ture, demonstrating a promising test approach to see through the terrible variance of the
intrinsic deep-submicron parameters.
10.6 CONCLUSIONS
Deep-submicron and nanometer technologies challenge several areas of test and diagno-
sis. The complex ATE digital testers are pressed to match the timing requirements, the I/O
pin counts, the high thermal environment, the power supply current demands, contain
costs, and make critical measurements in the face of widening statistical variation in the
normal population of ICs. Test development and actual IC test measurement costs drove
acceptance of design-for-test structures for the high-performance industry. Scan circuits
are mandatory to ease the pressures of the deep-submicron technologies. Defect-based
testing is a deterministic technique to analyze defect electronic behavior, and then use test
methods matched to those behaviors. DfT structures dictate a test pattern delivery style,
and defect-based testing dictates what specific tests to use. The test strategies are compro-
mised by the increase in transistor and part parameter variance with each technology
node. These are exciting times to push the technological and human limit of computing
circuits.
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EXERCISES
10.1. Example 10.1 uses a 1K memory to illustrate the futility of functional testing.
Therefore, should we eliminate functional testing from our IC test methods?
10.2. Can a functional test set replace a stuck-at-fault test set?
10.3. What does it mean to sensitize a logic signal path?
10.4. An exclusive OR gate (XOR) is shown in Figure 10.29. The output is a logic-1 only
when a single logic-1 exists in AB. XOR = logic-1 if AB = 10 or 01. Derive the
stuck-at-fault vectors to detect nodes x-SA0 and y-SA1.
A y
XOR (AB)
B
Figure 10.29.
10.5. The circuit in Figure 10.30 is a 2-bit input to 4-bit decoder. The four logic states of
A0A1 can activate the output of the four output lines with a logic-0. Derive the test
vectors that detect x-SA1 and y-SA0.
A0 x
A0
A0
y
A1
A1
A1
x0 x1 x2 x3
Figure 10.30.
10.6. List three advantages and three disadvantages of the stuck-at-fault test method.
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EXERCISES 327
10.7. Derive the delay fault vectors that detects nodes x slow to rise and y slow to fall
(Figure 10.31).
A
B
C x
D
E
F y
G
H
Figure 10.31.
10.8. Derive the delay fault vectors that detect nodes x slow to rise and y slow to fall (Fig-
ure 10.32).
y
A
B
C F
D x
E
Figure 10.32.
10.9. List three advantages and three disadvantages of the delay fault (DF) test method.
10.10. List four advantages and four disadvantages of the IDDQ test method.
10.11. Derive an IDDQ test vector to detect the transistor bridge defects in Gate–3 of Fig-
ure 10.33.
A
B
C (Gate-3)
D
Figure 10.33.
10.12. Derive an IDDQ test vector to detect a bridge defect across nodes x and y in Figure
10.34.
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A
B
C x
D
E
F
G
H y
I
Figure 10.34.
10.13. Scan DfT makes sequential circuit (flip-flop) testing simple; you simply send log-
ic ones and zeros through the chain, and measure the result. Describe the sequen-
tial test problem if scan DfT is not used.
10.14. A bridge defect may cause a DC leakage path from VDD to GND. The IDDQ going
through the bridge causes a current elevation. For this circuit, you measured an
IDDQ strongly in excess of the current in the bridge defect. Explain.
10.15. What is the thermal problem associated with testing ICs using scan circuits?
10.16. LBIST testing requires that all flip-flops in LFSR initially be set to logic zero.
Why?
10.17. If an LBIST LFSR generated all possible logic combinations driving a subcircuit,
describe the defects that can quantifiably be detected. Assume that the all-zeros
state of the LFSR is generated by a separate test structure, and that the circuit is
clocked at the operational speed of the IC.
10.18. Assume that an LFSR drives all inputs of the circuit in Figure 10.35.
(a) Is the probability high or low that a single random vector will detect node-A as
a stuck-at one?
(b) Is the probability high or low that a single random vector will detect node-A as
a stuck-at zero?
10.19. Table 10.4 lists an electromigration reliability open circuit as rarely causing stuck-
at-fault behavior. Is this conclusion a contradiction since we studied that hard open
circuit defects can cause stuck-at-fault behavior in two of the five combinational
logic defect classes?
10.20. The DC transfer curve and the timing results in Figure 10.18 should match node
voltages when the quiescent logic state is reached. Do they? Why?
10.21. Why does Figure 10.18(c) show a peak for a defect resistance between 1 k⍀ and 2
k⍀?
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EXERCISES 329
Figure 10.35.
10.22. Is there a single test method that can detect all open circuit defect behavior class-
es? Explain.
10.23. The Venn diagram in Figure 10.10(a) obtained by Maxwell et al. [39] was obtained
with a stuck-at fault coverage of 99%. The functional test set was fault-simulated
and had a 83.7% stuck-at-fault coverage. Why did the functional test set in Figure
10.10(a) detect more defects?
10.24. Resistive vias grew to be significant for IC test problems in the 1990s. Why is the
present test solution to resistive vias a near-perfect example of defect-based test-
ing?
10.25. The development of deep-submicron ICs introduced serious noise into the test
process that was insignificant in older technologies. Describe the noise that affects
test methods in deep-submicron technologies.
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APPENDIX A
SOLUTIONS TO SELF-EXERCISES
A.1 CHAPTER 1. ELECTRICAL CIRCUIT ANALYSIS
Self-Exercise 1.1
V0 = 1.65 V
VP = 52.33 V
Self-Exercise 1.2
Req = 1200 || 950 || R3
250 = [1/1200 + 1/950 + 1/R3]–1
1/R3 = 1/250 – 1/1200 – 1/950 ⇒ R3 = 473.0
Self-Exercise 1.3
Rin = 8 k
IBB = 1.25 mA
V0 = 7.5 V
Self-Exercise 1.4
(a) Rin = 667
(b) Rin = 2 k
(c) Rin = 990.1
(d) Rin = 999
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332 APPENDIX A SOLUTIONS TO SELF-EXERCISES
Self-Exercise 1.5
Rin = 11.5 k
IBB = 86.96 A
V0 = 652.2 mV
Self-Exercise 1.6
(a) I3 = 100 A – 50 A – 10 A = 40 A
(b) VR3 = 40 A × 50 k = 2.0 V, so that
R1 = 2.0 V/50 A = 40 k
R2 = 2.0 V/10 A = 200 k
Self-Exercise 1.7
VR3 = V0 = 200 A × 8 k = 1.6 V
R1 = [3.3 – 1.6]/650 A = 2.615 k
I2 = 650 A – 200 A = 450 A
R2 = 1.6/450 A = 3.556 k
Self-Exercise 1.8
R1 = 7.125 k
Self-Exercise 1.9
(a) Req = 1 M || 2.3 M; that is, Req = 697.0 k
(b) Req = 75 k || [150 k + 35 k]; that is, Req = 53.37 k
Self-Exercise 1.10
Req = R1 + R3 || (R2 + R4)
Req = R1 + R3 || (R2 + R4) + R5
Req = R1 || [R2 + R4 || (R3 + R5)]
Self-Exercise 1.11
(a) Req = 31.98 k
(b) Req = 36.98 k
(c) Req = 10.32 k
Self-Exercise 1.12
V0 = (12k || 20k)/[4k + (12k || 20k)] × 1 V = 0.652 V
V4k = (4k)/[4k + (12k || 20k)] × 1 V = 0.348 V
VBB = 0.652 + 0.348 = 1.00 V
Rin = 4k + (12k || 20k) = 11.5 k
IBB = VBB/Rin = 87.0 A
Self-Exercise 1.13
Rin = 45k||[8k + (18k||30k)] = 13.48 k
V0 = (18k||30k)/[8k + (18k||30k)] × 2.5 V = 1.461 V
IBB = 185.4 A
Self-Exercise 1.14
I12k = [20/(20 + 12)] × 87.0 A = 54.38 A
I20k = [12/(20 + 12)] × 87.0 A = 32.63 A
(Notice that the KCL is satisfied: 87.0 A = 54.38 A + 32.63 A.)
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A.1 CHAPTER 1. ELECTRICAL CIRCUIT ANALYSIS 333
Self-Exercise 1.15
I45k = [8k + (18k || 30k)]/[45k + 8k + (18k || 30k)] × 185.4 A = 55.55 A
I8k = (45k)/[45k + 8k + (18k || 30k)] × 185.4 A = 129.9 A
(Notice that I8k is more easily obtained from KCL, where I8k = 185.4 A – 55.55 A =
129.9 A.)
I18k = (30k)/(30k + 18k) × 129.9 A = 81.16 A
I30k = (18k)/(30k + 18k) × 129.9 A = 48.69 A
VBB = 2.5 V
Self-Exercise 1.16
(a) I10k = 46.15 A
I15k = 30.77 A
I20k = 23.08 A
(b) R20k ⇒ 114 k
Self-Exercise 1.17
(a) V0 = 3.60 mV
(b) I2 = 714.3 A, I9 = 400 A
Self-Exercise 1.18
Rin = 250 + [4k + (3k ||1k)] || [2k || (750 + 1.5k)] + 250 = 1.366 k
I1.5k = [5 V/Rin] × [2k || (4k +(3k 1k))]/[2k || (4k + (3k||1k) + (750 + 1.5k)]
= 1.409 mA
Self-Exercise 1.19
(a) Ceq = 38.1 nF
(b) Ceq = 25.9 fF
Self-Exercise 1.20
C2
V1 = × 100 mV
C1 + C2
75
= × 100 mV = 62.5 mV
45 + 75
45
V2 = × 100 mV = 37.5 mV
45 + 75
Self-Exercise 1.21
C1
V2 = × VD
C1 + C2
30
= × VD = 0.7 V
30 + 25
55
VD = × 0.7 V = 1.28 V
30
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Self-Exercise 1.22
86.17 eV/K
冢冣冢冣
200 nA
(a) VD = (298 K) ln + 1 = 136.2 mV
1 eV 1 nA
(b) ID = 1 nA(e400/26) = 4.80 mA
Self-Exercise 1.23
ID = 185 A
VD = 315.3 mV
Self-Exercise 1.24
(a) 5.179 V, –0.179 V
(b) 5 V
Self-Exercise 1.25
VD1 = 18.02 mV
V0 = 4.982 V
Self-Exercise 1.26
ID = 26 mV/1 A ⇒ 26 k
ID = 26 mV/100 A ⇒ 260
ID = 26 mV/1 mA ⇒ 26
ID = 26 mV/10 mA ⇒ 2.6
Dynamic diode resistance can vary over a wide range, depending upon the bias current.
A.2 CHAPTER 3. MOSFET TRANSISTORS
Self-Exercise 3.1
(a) Ohmic
(b) Ohmic
(c) Saturated
(Hint: watch your terminals.) The source terminal always has a lower or equal voltage
than the drain in a conducting nMOS transistor.
Self-Exercise 3.2
ID = 12.5 A using saturated state model.
VD = 9.375 V
Self-Exercise 3.3
ID = 184.8 A
VD = 0.761 V
Self-Exercise 3.4
VGS = 3.33 V
M1 in saturation
Self-Exercise 3.5
R1 = 180 k
Self-Exercise 3.6
R0 = 537.6
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A.3 CHAPTER 4. CMOS BASIC GATES 335
Self-Exercise 3.7
(a) Saturated state
(b) Ohmic state
(c) Boundary point of both saturated and ohmic state
Self-Exercise 3.8
ID = 29.4 A, V0 = 2.94 V
Self-Exercise 3.9
ID = 48.46 A, V0 = 4.846 V
Self-Exercise 3.10
ID = 153.6 A, V0 = –1.848 V
Self-Exercise 3.11
R = 239.0 k
Self-Exercise 3.12
W/L > 6024
Self-Exercise 3.13
ISAT = 6 mA
Self-Exercise 3.14
ISAT = 0.66 mA
A.3 CHAPTER 4. CMOS BASIC GATES
Self-Exercise 4.1
Wp/Wn = 3.36
Self-Exercise 4.2
(a) 61.4%
(b) 71.7%; you must derive the equation for this from the Vin equation in Example 4.2.
(c) 10.4%
Self-Exercise 4.3
Vout/Vin ⬇ –17
Self-Exercise 4.4
D = 103.1 ps at VDD = 2.5 V
D = 186.0 ps at VDD = 1.8 V
The extra delay is 83.0 ps, which represents an increase of 80.4%.
Self-Exercise 4.5
(a) I1I2I3I4 = 11X0
(b) I1I2I3I4 = 1X00
Self-Exercise 4.6
(a) I1I2I3I4 = 1100
(b) I1I2I4I5 = 1101
(c) I2I3I4I5 = 1001
c11.qxd 2/2/2004 12:40 PM Page 336
A.4 CHAPTER 5. CMOS BASIC CIRCUITS
Self-Exercise 5.1
x x
w t
y z
F
x y
x z
z
w
Self-Exercise 5.2
The gate level design of a D-latch shown in Figure 5.16(a) has four transistors in each
NOR gate (thus, a total of 16 devices), plus two transistors for the inverter, resulting in 18
transistors. A transistor-level design of the circuit in Figure 5.16(b) is
clk clk
D Q
clk clk
This design uses 10 transistors shown plus two more to invert the clock for a total of 12
transistors. The circuit loads data when clk is high, and holds that data to output Q when
the clk goes negative.
A.5 CHAPTER 6. FAILURE MECHANISMS IN CMOS ICs
Self-Exercise 6.1
(a) 29.7% Reduction in current density
(b) 50.7% Reduction in lifetime at the higher temperature
c11.qxd 2/2/2004 12:40 PM Page 337
A.8 CHAPTER 10. DEFECT BASED TESTING 337
Self-Exercise 6.2
(a) P = 1.2 W/cm2
(b) P = 12 kW/cm2. Since the passivation material is highly insulating, you can get a hot
region. 10 mA is typical for electromigration test structure experiments and 100 A is
typical for IC operation.
(c) The 100 A current drops 300 V and the 10 mA current drops 30 mV. These drops
would typically not alter logic function.
Self-Exercise 6.3
250 m
Self-Exercise 6.4
(a) 8.658 × 10–6 lb, 3.936 × 10–6 kg
(b) 0.1329 m = 132.9 nm
A.6 CHAPTER 7. BRIDGING DEFECTS
Self-Exercise 7.1
(a) Rcrit = 3.246 k
(b) Kp/Kn = 1 and both transistor drains are at the logic threshold voltage.
Self-Exercise 7.2
Rcrit = 1.433 k – 1.722 k
Self-Exercise 7.3
VG = 2.30 V, so gate passes function (barely).
A.7 CHAPTER 8. OPEN DEFECTS
Self-Exercise 8.1
(a) V2 = 1 V
(b) VDD = 2.513 V
A.8 CHAPTER 10. DEFECT BASED TESTING
Self-Exercise 10.1
Node-c SA1 has three possible test vectors:
01 11 11
01 11 10
01 11 01
Node-m SA0 has nine possible test vectors including:
11 00 10
11 00 01
11 00 11
index.qxd 2/2/2004 12:40 PM Page 339
INDEX
Acceptor atom, 44, 48 parasitic structure from gate-oxide short,

AHI (see Anode hole injection model) 211–212, 214
AHR (see Anode hydrogen release model) role in latchup, 145–146
Anode hole injection model (AHI), 182 BIST (see Built-in self test)
Anode hydrogen release model (AHR), 182 Bit line, 141, 142
Antennas, 191 Black’s law, 161, 162
Aspect ratio Blech Effect, 165–168, 176, 196
via, 177, 253–254, 306 Body effect (see also Transistor threshold
impact on gate threshold voltage, 102 voltage)
impact on parameter variations, 247 constant, 78, 93, 94, 97, 145
symmetric transfer characteristic, 103 Bohr, Neils, 37
ATE (see Automatic test equipment) Boltzmann constant, 24, 41, 158, 160, 162, 186
ATPG (see Automatic test pattern generation) Bounce (see Noise)
Automatic test equipment (ATE), 282, 296, Bridging defect
299, 310, 314–315, 322 control loops, 217–218
Automatic test pattern generation (ATPG) (see floating state, 217–218
also Test), 207, 214, 281, 284, 292, 296 forced state, 217
Avalanche voltage based testing of, 302
weak, 93 feedback, 214–215
inverted, 216
Band bending, 45 nonfeedback, 214
Band gap, 38 noninverted, 216
BCC (see Metal Body-centered cubic) Built-in electric field (see Diode and
Bi-directional (bipolar) current, 165–166 Transistor)
Bi-directional pin, 146, 147 Built-in self test (BIST), 293, 296
Bipolar current (see Bi-directional current) combinational logic test (LBIST), 209, 296,
Bipolar transistor, 53, 207 298, 328
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340 INDEX
Built-in self test (BIST) (continued) parametric failures, 243, 245–246

embedded core memory test (MBIST), 296 impact on delay, 259, 266–268
linear feedback shift register (LFSR), increase with interconnect scaling, 255
296–298, 328 Current based testing, 283, 289–293
multiple input shift register (MISR), of bridge defect, 301–302
296–298 current ratios test, 316
current signatures, 315–316
Capacitor voltage divider. 20–22, 224–226, 233 current-based test, 218, 283, 289–290, 293,
Capacitor 301–302, 304–305, 311, 315
parallel connection, 18, 19 delta-IDDQ, 316
series connection, 19, 21, 81, 225 IDDQ test (see IDDQ test)
Carrier transport, 44–46 of hard opens, 304–305
Catastrophic defect (see defect) of nanometer ICs, 311, 315–318
CD (see Critical dimension) of semiconductor memories, 218
Channel length (see Transistor Channel length) transient, 292
Channel length modulation, 83 transient current test, 283, 292
Channel width (see Transistor Channel width) Current divider, 14–15, 17
Charge based testing, 323 Current drive strength (see also Drive
Charge sharing, 134–35, 142 strength), 109, 142, 201, 249–250
Chemical mechanical planarization (CMP), impact on bridge critical resistance, 205, 214
177, 244, 259, 275 impact on inverter characteristics, 103
Chemical vapor deposition (CVD), 177 of memory transistors, 304
CMP (see Chemical mechanical planarization) of NAND gate, 120
Column decoder, 140, 296 Current leakage (see Transistor subthreshold
Comparative test methods, 292–293, 314 leakage and Diode)
Complementary static gates, 127–128, 133 Current source, 6–7, 12, 60, 110
Compound domino logic, 135, -137, 148 Current
Conduction band, 38–43, 44, 45 Conduction current, 18
Conduction channel (see Transistor) Displacement current, 18
Conduction, CVD (see Chemical vapor deposition)
diffusion, 45–47, 49
drift, 40, 45–46, 52 Damage
in diodes (see also Diode), 48–50 thermal current, 182, 270
in metal voids, 165 trap (see also Trap), 93, 129, 180, 182,
in solids (see also Semiconductor), 37–41 185–187, 191
in transistors (see also Transistor), 56, 60 Dangling bonds, 178–179
trap-assisted (see Trap), 181–182 DBT (see Defect-based testing)
tunneling, 229–230, 236–237 DCVS (see Differential cascode voltage
Conductivity, 37, 156, 254 switch)
Coulomb, 4, 18, 40 Defect activation, 201
Critical dimension (CD), 244, 310 Defect clustering, 317
Critical path, 265 Defect location, 107
global interconnect, 259 Defect
impact of noise on, 269–270 bridge (see Bridging defect),
timing test, 315, 318 catastrophic, 244
Vt adjustment of, 104 delay (see Parametric defects)
Critical resistance, 199–207, 284, 287, environmentally sensitive, 243
301–302 gate oxide short (see Gate oxide short)
impact of technology scaling on, 218 in crystals, 156
variation with VDD, 318–319 open (see Open defect)
Cross-talk (see also Noise), 17, 243, 253, 255, parametric (see Parametric defects)
308–309 random, 272, 282
in Cu-interconnect, 177 short (see Bridging defect)
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INDEX 341
Defect-based testing (DBT), 281 role in substrate noise, 264

Delay role in temperature variation, 255
impact of threshold voltage, 110, 112 Drain bias mobility reduction, 84
signal slow-down, 265–266, 268 Drain depletion region, 52, 59, 67, 79–81, 83,
signal speed-up, 255, 260, 268 107
Delay fault (DF), 305–306, 309, 312, 314–315, in gate oxide short, 210–211
327 reduction in short-channel transistors, 248
Delay fault test, 266, 283, 288 role in hot carrier injection, 185–189
comparative analysis, 292–293 Drain induced barrier lowering (DIBL), 82, 91,
in nanometer ICs, 314 93, 98, 248
pattern generation, 289, 296 DRAM (see Dynamic random access memory)
using Statistical timing analysis, 318 Drift current, 45
Depletion region, Drive strength (see also Current drive
diode, 47–50 strength), 103, 120, 214, 221, 318
in channel length modulation, 83 impact on bridge critical resistance, 199,
light emission from, 67 202, 204–205
transistor channel, 57 impact on IC performance, 252
transistor drain (see Drain depletion region) of transistor (K), 61
Depletion, transistor operation region (see variation with VDD lowering, 318
Weak inversion) Dual damascene process, 177–178, 196
Design for test (DfT) Duality property, 41, 229
scan design, 293 Duty cycle, 169, 190
Design verification, 281, 284 Dynamic logic, 127, 135, 147, 262
DF (see Delay fault) Dynamic power, 113, 131, 312
DfT (see Design for test) Dynamic random access memory (DRAM),
DIBL (see Drain induced barrier lowering) 142, 150, 218, 310
Die
identification code, 307 E–1 model, 185
per wafer, 81 E-model, 185
Differential cascode voltage switch (DCVS), Electrical overstress (EOS), 143, 150
136 Electromigration (EM), 159–161
Diffusion current, 46, 47, 49 failure process, 162–165
Diffusivity, 158, 160, 175, 177 failure time, 161–162
Diode resistor circuits, 25–28 flux, 177
Diode weak spot, 178
built-in electric field, 48–49, 51, 57 Electron, 37–38
depletion region (see Depletion region) Electron tunneling, 183, 229–230, 236
dynamic resistance, 28–29 Electron-hole pair creation, 40–41, 43–44, 52,
I-V characteristics, 24 93, 186
leakage current (see Diode reverse bias Electron-hole pair recombination, 40–41
saturated current) Electrostatic discharge (ESD), 143–144, 150
parasitics, 50–51 EM (see Electromigration)
reverse bias saturated current (Is), 24 Energy band model, 37, 44
under equilibrium, 46–48 Energy gap, 39, 41
under forward bias, 49 EOS (see Electrical overstress)
under reverse bias, 49 ESD (see Electrostatic discharge)
Displacement current, 18 ESD protection circuit, 143–144, 150
Domino logic, 135–136 Evaluation phase, 134
Domino logic, Self Resetting (SRCMOS), 135 Evaluation transistor, 134
Donor atom, 43, 47–48 Extrinsic failures, 223, 243–244, 271–272,
Doping, 42–44, 51 275, 322
in pn junction, 46–48, Extrinsic material, 154, 243
role in parameter variation, 247–248 Extrinsic semiconductor, 42
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342 INDEX
Farads (F), 18 IDL (see Interlayer dielectrics)

Fault (see Fault model) IEEE Test standard 1149.1, 299–300
Fault equivalence, 286 IEEE Test standard 1149.4, 299–300
Fault model IEEE Test standard 1149.5, 300
biased voting, 207–208 IEEE Test standard 1149.6, 300
delay (see Delay fault), IEEE Test standard 1450, 300
logic wired AND/OR, 207–208 IEEE Test standard 1532, 300
pseudo stuck-at, 207, 291 IEEE Test standard P1500, 300
stuck-at (see Stuck-at) IEEE Test standard P1581, 300
voting, 207–208 IEEE Test standards, 300
FCC (see Metal Face-centered cubic) Inductor, 3, 53, 262
Feedback transistor, 135 Input high voltage (VIH), 102, 123
Fermi–Dirac, 41 Input low voltage (VIL), 102, 123
Fick’s law, 46, 158 Insulator, 18, 37–39, 52, 54, 56–57, 79, 248,
Field emission, 185 261
Flip-flop, 137–139, 265, 302, 304 Interconnect line
bridges in, 217–218, capacitance model, 257
in scan design, 294–295 RC model, 258, 279
opens in, 239, RLC model, 258, 279
FMAX (see Maximum operating frequency) Interconnect wire
Forward bias, 25, 28, 49–52, 211 capacitive coupling, 261
Functional failure, 202 Copper reliability, 176–179
Functional test, 283 crystal structure, 154–158
defects (see Defects)
Gate bias mobility reduction, 85 delay variation, 266
Gate induced leakage current (GIDL), 186 electrical models, 257–259
Gate overdrive, 103, 115, 256 electromigration (see Electromigration)
Gate oxide short (GOS), 181, 183, 191, 199, inductive coupling, 261
208–214, 271, 301–302, 318 material in ICs, 154–155
in semiconductor memories, 218 parameter variation (see Parameter variation)
soft, 181, 213 resistance dependence with temperature,
Gate threshold voltage (Vthr or VTL), 101–103 256
GIDL (see Gate induced leakage current) via-structure, 163–164
GOS (see Gate oxide short) Interlayer dielectrics (IDL), 244
Ground, 4 Intrinsic failures, 243–246, 256, 270, 275, 311,
Ground bounce (see Noise) 314–316, 320, 322
Guardband, 188, 314 Intrinsic material, 154, 249–253
Intrinsic semiconductor, 42
Hard opens, 271–272, 275, 304, 306, 328 Inverter logic threshold (see Gate threshold
HBD (see Oxide Hard breakdown) voltage)
HCI (see Hot carrier injection)
High-Z, 131–132, 134, 224 KCL (see Kirchhoff Current law)
Hole, 39–49, 52, 57–58, 60, 70–71, 146, Kirchhoff Current law (KCL), 4, 7, 29
179–180, 186, 189, 191 Kirchhoff Voltage Law (KVL), 4, 5, 29
Horizontal mobility, 84, 93 KVL (see Kirchhoff Voltage Law)
Hot carrier effects, 82, 91, 93, 116
Hot carrier injection (HCI), 124, 178, 185, Latch, 135, 137–139, 147, 150, 238–239, 265,
188–189, 192, 196, 232, 262 314, 336
lifetime, 190 Latchup, 145–146, 150, 211–212,
Hot electrons, 146, 186 LBIST (see Built-in self test)
Leakage power, 312–313
IDDQ test, 283, 288, 290–292, 302, 304–305, LFSR (see Built-in Self test, Linear feedback
309, 311, 315, 320, 327 shift register)
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INDEX 343
Logic threshold voltage (see Gate threshold NBTI (see Negative bias temperature
voltage) instability)
Low VDD testing (see Voltage based testing) Nearest neighbor test, 317–318
Negative bias temperature instability (NBTI),
Master-slave flip flop (MSFF), 138–139 178, 191
Maximum operating frequency (FMAX), 186, NM (see Noise margin)
188, 245, 250, 264–266, 268–269, 280, NMH (see Noise margin high)
304–306, 312, 315, 317, 321–322 NML (see Noise margin low)
test, 288 Noise margin (NM), 100, 102, 127, 184, 232,
test in nanometer ICs, 315 247, 257, 259, 261, 264, 275,
MBIST (see Built-in Self test, Embedded core Noise margin high (NMH), 102, 123
memory test) Noise margin low (NML), 102, 123
MCM (see Multichip modules) Noise
Metal coupling noise, 259–260
bamboo grains, 157, 161, 176–177 crosstalk noise (see also Cross-talk),
body-centered cubic (BCC), 155 260–261, 279
Bravais lattices, 154 Delta-I noise, 259, 262, 264
close-packed plane, 155 ground bounce, 253, 263, 275, 279, 308
edge dislocation, 156–157 IR drop noise, 259, 261–262
face-centered cubic (FCC), 155 substrate noise, 64
flux divergence, 162–164 supply bounce, 253, 263, 308
grain boundaries, 154, 156–159, 161–162, switching noise, 243, 245, 253, 264
175, 195 Noncontrolling logic state, 118–121, 137, 237,
grains, 154, 161, 177 285, 287
interstitial, 156 NOR logic gate, 99, 120–121, 286–287
mousebites, 271–275, 282 path sensitization, 285
slip plane, 156–157
sliver defect, 199–200, 221 Off-state, 54–55
substitutionals, 156, 195 current (see Transistor subthreshold leakage)
triple point, 156–157 Ohm’s Law, 4–8, 28–29
vacancy, 156, 159 Ohm, 4
Min VDD (see Voltage based testing), 317–319, On-state, 54–55, 60, 262
321 OPC (see Optical proximity correction)
MISR (see Built-in self test, Multiple input Open defect class,
shift register) delay, 232, 236–237
Mobility, 45–46, 83 sequential, 232, 238–239
of electron, 61, 103 transistor pair-on, 232, 234–235
reduction, 84, 86 transistor pair-on/off, 232, 234–236
reduction, horizontal, 84, 93 transistor-off (memory), 232, 237–238
reduction, vertical, 85, 93 transistor-on, 232–234
of hole, 103 Open defect
MODL (see Multiple output domino logic) impact of surrounding lines, 226
Moore’s law, 309 large opens, 224–226
MSFF (see Master-slave flip flop) tunneling opens, 229
Multichip modules (MCM), 299 Optical proximity correction (OPC), 244
Multiparameter testing, 320–321 Outer energy band, 40
Multiple output domino logic (MODL), 135 Output high voltage (VOH), 102, 123, 314
Output low voltage (VOL), 102, 123, 315
n-type semiconductor, 42–43, 46 Overshoot, 107–110
NAND logic gate, 99, 118–120, 129, 227–228, Oxide hard breakdown (HBD), 181, 183–184,
237 213–214
path sensitization, 285 Oxide soft breakdown (SBD), 181, 183–184,
with input-output short, 302 213
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344 INDEX
Oxide ultrathin, 181–185, 213–214, 221, 248, POH (see Power-on hours)
271 Positive current convention, 4
Oxide wearout, 178–183, 185, 191–192, 213, Power consumption, 113
244, 301, 308, 312 leakage component, 113
shortcircuit component, 113
p-type semiconductor, 44, 47 transient component, 113
Parallel plate capacitor, 18, 50, 52, 79, 80, 258, Power grid, 262–264
275 Power-on hours (POH), 190–191
Parallel resistance, 8–11 Precharge, 134
Parameter variations Precharge transistor, 131–136, 141–142
channel length variation, 246–247, 250, 266 Printed circuit board (PCB), 142, 145
channel width variation, 246–247 Printed wire boards (PWB), 299
die to die, 244 Process corners, 253, 269
extrinsic, 243–244, 271–275 PSM (see Phase shift masks)
impact on delay, 265 Pull-down (see Transistor Pull-down)
in interconnect, 244, 252–255 Pull-down network, 128–131
intrinsic, 243–253, 257, 261, 264–266, 268, Pull-up (see Transistor Pull-up)
270, 275, 279–280, 288, 306, 308–309, Pull-up network, 128–131, 148
315 PVD (see Plasma vapor deposition)
lot to lot, 244 PWB (see Printed wire boards)
nMOS to pMOS length ratio, 244, 246–
247 Quic-Mon IDDQ circuit, 291
random, 245, 317–318
random doping fluctuation, 248318 RAM (see Random access memory)
systematic, 245, 317–318 Random access memory (RAM), 139
wafer to wafer, 244 RBB (see Reverse body biasing)
within die, 244 Redundant faults (nodes), 216, 287, 291
Parametric defects, (see also Parameter Register, 137, 139
variations) linear feedback shift register (LFSR),
delay, 264–270 296–297
extrinsic metal mousebites, 272 multiple input shift register (MISR), 298
extrinsic metal slivers, 275 scan, 294–296
extrinsic resistive vias/contacts, 271 Resistive contacts, 306
extrinsic weak opens, 271 Resistive via, Fmax testing of, 288
Parasitics (see Transistor Parasitic and Diode Resistive vias, 237, 271–272, 275, 288,
Parasitic) 305–307, 309, 320, 329
Pascal (Pa), 171 Reverse bias saturation current, 25, 27, 49–50,
Pass gate, 127, 132–133, 217 52, 103
Pass transistor logic, 127, 132 Reverse bias, 49–50, 52, 56–57, 79, 83, 191,
Pass transistor, 122, 127, 132–133, 141–142, 233
144, 147, 256 Reverse body biasing (RBB), 321
Pauli exclusion principle, 41 Ring oscillator, 187, 213
PCB (see Printed circuit board) Row decoder, 238
Percolation model, 182–183, 196, 214
Permittivity, 18, 79–80 Saddle point, 159
Phase shift masks (PSM), 244 SAF (see Stuck-at)
PICA (see Timing path analyzer) Sakurai model, 88
Pinchoff (see Transistor pinchoff), 59, 61, 83, Saturation current (see Transistor saturation
93 and Diode saturation)
Pitch, 244, 253, 310 SBD (see Oxide Soft breakdown)
Plasma vapor deposition (PVD), 177 Scan design for test, 293–296, 298–299,
pn junction, (see also Diode) 46, 50, 52, 56, 304–305, 309–310, 314, 322, 328
113, 177, 209, 212, 214, 248 Scan flip-flop, 295
index.qxd 2/2/2004 12:40 PM Page 345
INDEX 345
Schmitt trigger, 144, 150 delay fault (see Delay fault test)
SE (see Soft errors) functional (see Functional test)
Self-resetting domino logic (SRCMOS), 135 IDDQ (see IDDQ test)
Semiconductor stuck-at fault (see Stuck-at)
doping, 42–44 voltage-based (see Voltage based testing)
extrinsic, 42 weak defect (see Weak defects)
intrinsic, 42 Thermal coefficient of expansion (TCE), 169
pure, 39 Thermal voltage, 24
SER (see Soft error rates) Threshold voltage (see Transistor threshold
Series elements, 5 voltage, and/or Gate threshold voltage)
Series resistance, 6, 14 Timing path analyzer (PICA), 107
Shallow trench isolation (STI), 244, 247, 250 Transient faults, 313
Sheet resistivity, 273 Transistor lifetime (t), 190
Silicon (see also Semiconductor) Transistor pull-down (see also Evaluate
SIV (see Stress induced Voiding) transistor), 103
Smiconductor, conduction in, 44–46 Transistor pull-up (see also Precharge
Soft breakdown (see Gate oxide short) transistor), 103, 141
Soft error rates (SER), 313–314 Transistor threshold voltage (Vt), 54, 58
Soft errors (SE), 312 body effect, 77
Soft gate oxide rupture (see Gate oxide short) graphical determination, 105
Speed binning, 288 impact of technology scaling on, 93
SRAM (see Static random access memory) impact on delay, 110, 112
SRCMOS (see Self-Reseting CMOS) nmos (Vtn), 54, 58
Static random access memory (SRAM), 140 pMOS (Vtp), 54, 58
Statistical timing analysis, 315, 318 scaling, 92
STI (see Shallow trench isolation) variation with Vsb, 77
Stress gradient, 157, 160 zero bias (Vt0), 78
Stress induced Voiding (SIV), 169 Transistor
Stress voiding (SV), 157, 169–178 built in diodes, 56–57
Stuck-at bulk, 54–56
comparative analysis, 291–293, channel length, 56
fault (SAF), 207, 283, 284, 308 channel width, 56
test, 284 drain region, 54, 56
test for nanometer ICs, 314 drive strength (see Drive strength)
test Pattern Generation, 284–288 family of curves, 60, 70
weak, 234–235 gate oxide, 55
Stuck-open, fault, 237 internal diodes, 56–57
Subthreshold current, 92 inversion channel, 58
Subthreshold slope, 92 junction leakage current, 113
degradation, 186 linear operation region (see Transistor ohmic
Supply bounce (see Noise) operation region)
Supply nonsaturated operation region (see Transistor
current, 6 ohmic operation region)
voltage, 5 ohmic operation region, 59, 61–63, 70, 86,
SV (see Stress voiding) 89
Switching noise (see Noise) parasitic capacitors, 79–81
pinchoff, 59, 83
Tapered buffers, 117 pinchoff voltage, 61
TCE (see Thermal coefficient of expansion) saturation operation region, 59, 70, 86, 88
Test pattern, 282 source region, 54, 56
Test vector, 282 subthrehold leakage scaling with technology,
Test 312
current based (see Current based testing) subthreshold leakage (Ioff), 92, 252
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346 INDEX
Transistor (continued) Voltage divider, 14-16, 20–22

subthreshold leakage stress induced due to open defect, 224–226, 233
degradation, 188 Voltage source, 5–6
Transmission gate, 122 Voltage, 3–5
weak voltage in, 132 weak (see Weak voltage)
Transmission line effects, 259, 261 Vt (see Transistor threshold voltage)
Trap, 93, 179 Vthr (see Gate threshold voltage)
assisted conduction, 181 VTL (see Gate threshold voltage)
charge, 191, 232 Vtn (see Transistor threshold votlage)
damage, 182 Vt0 (see Transistor threshold voltage)
distribution, 183 Vtp (see Transistor threshold voltage)
interface, 180, 186
plasma-induced, 232 Wafer hot chuck, 307
state, 179 Wafer-level reliability (WLR), 189
Tri-state gate, 131 Wafer probing, 307, 310
Tri-state level, 122 Watt (W), 5
Weak bond
Undershoot, 107–108 in Cu, 177
Unipolar current, 165–166 in oxide, 179, 182
Weak defect
Vacancy bridge,
defect, 156 open, 223, 271–272, 304–306
of electron, 39–40, 44 test for, 318
Valence band, 38–40 Weak inversion, 79–80
Velocity saturation, 45–46, 83–85, 93 Weak logic gate, 264
with voltage scaling, 115–116 Weak logic value (see Weak voltage)
Vertical mobility reduction (see Mobility) Weak oxide, 181
VIH (see Input high voltage) defect due to, 210
VIL (see Input low voltage) Weak Stuck-at (see Stuck-at)
VOH (see Output high voltage) Weak transistor, 205
VOL (see Output low voltage) Weak voltage, 102, 107, 132, 144, 184, 201,
Voltage based testing (VBT), 282–283 202, 205, 211
critical path timing test (see Critical path) defect-induced, 213, 219, 239, 304
delay fault test (see Delay fault) Well, 77
FMAX test (see Maximum Operating single technology, 145–146, 211
Frequency) Wired logic, 208
for nanometerIC, 314
low VDD test (Min VDD), 318 XOR gate, 128, 132, 133, 297, 298, 326
of bridge defects (see Bridging defect) weak voltage in, 122
speed testing, 288
stuck-at fault test (see Stuck-at) Young’s modulus, 171, 176
index.qxd 2/2/2004 12:40 PM Page 347
ABOUT THE AUTHORS
Jaume Segura is an associate professor of Electronic Technology in the Electronic Tech-

nology Group at the Balearic Islands University, Spain. He teaches graduate courses in
microelectronic analog and digital design, microprocessor-based design, test engineering,
and reliability. He also teaches short courses on these topics in Europe, the United States,
and South America. Professor Segura has done research in these topics for more than 10
years, establishing research collaborations with several universities and companies. He
has been a visiting researcher at Philips Semiconductors in New Mexico and Intel Corpo-
ration in Oregon.
Dr. Segura has been a guest editor for the IEEE Design & Test of Computers and was
the general chair of the IEEE International On-Line Testing Workshop in 2000. Dr. Segu-
ra is a member of the executive committee of the Design Automation and Test in Europe
(DATE) conference and a member of the organizing committee of the IEEE VLSI Test
Symposium (VTS). He was director of the IEEE-TTTC Summer Courses on Design and
Test Topics from 1999–2002. He also served as program committee member for several
international conferences including the IEEE International Test Conference (ITC), IEEE
VLSI Test symposium (VTS), the IEEE International On-Line Testing Symposium
(IOLTS), the IEEE European Test Symposium (ETS), and the IEEE Workshop on Defect
Based Testing (DBT). He is the chairman of the IEEE-CAS Spanish Chapter. He received
his Ph.D. in Electronic Technology from the Polytechnic University of Catalonia in 1992,
and a Physics degree from the Balearic Islands University in 1989. In 1994, he was a vis-
iting researcher at the University of New Mexico.
Charles F. Hawkins is a professor in the Electrical and Computer Engineering Depart-

ment at the University of New Mexico, Albuquerque. He teaches graduate courses in Mi-
croelectronics Design, Reliability, Test Engineering, and Failure Analysis. For more than
index.qxd 2/2/2004 12:40 PM Page 348
348 ABOUT THE AUTHORS
20 years, Professor Hawkins has also taught industry short courses on these topics in the
United States, Canada, Europe, and Australia. His research in these topics includes a 20-
year research collaboration with the Microelectronics Group at Sandia National Laborato-
ries in Albuquerque, New Mexico; a four-year collaboration with the AMD Corporation
and Sandia Labs in failure analysis of timing paths in high-speed microprocessors; and a
four-month sabbatical with Intel Corporation in Rio Rancho, New Mexico.
He was the editor of the ASM Electron Device Failure Analysis Magazine (EDFA) from
1999–2003 and the general and program chair of the International Test Conference (ITC)
in 1996 and 1994, respectively. He co-shared eight Best or Outstanding Paper conference
awards with colleagues at Sandia Labs, Intel, and AMD Corp at ITC and at the Interna-
tional Symposium on Test & Failure Analysis (ISTFA). In addition to this book, he has co-
authored two books on electronics. He received his Ph.D. in Bioengineering from the Uni-
versity of Michigan, a Master degree in Electrical Engineering from Northeastern
University, and a BEE from the University of Florida. He was the associate dean of the
School of Engineering at the University of New Mexico from 1980–1982. He held sum-
mer faculty appointments at the University of the Balearic Islands, Spain from
1998–2002.

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qxd 5/10/2004 1:47 PM Page i

IEEE Press Editorial Board

M. Akay M. E. El-Hawary F. M. B. Periera

Kenneth Moore, Director of Book and Information Services (BIS)

IEEE Computer Society, Sponsor

IEEE Computer Society, Sponsor

A JOHN WILEY & SONS, INC., PUBLICATION

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

Library of Congress Cataloging-in-Publication Data is available.

Printed in the United States of America.

A Mumara, a la seva memòria, i al meu Pare.

To Jan, who has shared the mostly ups, the some-

PART I CMOS FUNDAMENTALS

1 Electrical Circuit Analysis 3

4 CMOS Basic Gates 99

5 CMOS Basic Circuits 127

PART II FAILURE MODES, DEFECTS, AND TESTING OF CMOS ICs

6 Failure Mechanisms in CMOS IC Materials 153

6.3 Metal Failure Modes 159

7 Bridging Defects 199

8 Open Defects 223

8.2.5 Other Effects 232

9 Parametric Failures 243

10 Defect-Based Testing 281

10.3.2 BIST 296

Appendix A Solutions to Self-Exercises 331

About the Authors 347

cur during characterization of a product? Is the symptom an outcome of random defects,

ELECTRICAL CIRCUIT ANALYSIS

1.2 VOLTAGE AND CURRENT LAWS

4 CHAPTER 1 ELECTRICAL CIRCUIT ANALYSIS

m/coulomb. Current is the movement of charged particles and is measured in coulombs

VBB = (10 nA)(1 M⍀) = 10 mV IBB = 3 V/6 k⍀ = 500 ␮A R = 100 mV/4 ␮A = 25 k⍀

1.2 VOLTAGE AND CURRENT LAWS 5

1.2.1 Kirchhoff’s Voltage Law (KVL)

VBB = R1IBB + R2IBB + R3IBB + R4IBB + R5IBB

Figure 1.2. KVL seen in series elements.

6 CHAPTER 1 ELECTRICAL CIRCUIT ANALYSIS

The voltage drop across RA is

The current in Figure 1.3(a) through the 12 k⍀ in series with a 20 k⍀ resistance is

1.2 VOLTAGE AND CURRENT LAWS 7

Figure 1.4. A current source driving a resistor load.

1.2.2 Kirchhoff’s Current Law (KCL)

Applying Equation (1.5), the total current delivered by the battery is

IBB = IA + IB = 25 ␮A + 16.67 ␮A = 41.67 ␮A (1.7)

Figure 1.5. KCL and its current summation at a node.

8 CHAPTER 1 ELECTRICAL CIRCUIT ANALYSIS

Figure 1.6. Parallel resistance example.

VBB VBB VBB

1.2 VOLTAGE AND CURRENT LAWS 9

500 µA 180 kΩ 3.3 kΩ

Calculate R3 in the circuit of Figure 1.8.

Req = 250 Ω 1200 Ω 950 Ω R3

Figure 1.8. Equivalent parallel resistance.

When the number of resistors in parallel is two, Equation (1.11) reduces to

10 CHAPTER 1 ELECTRICAL CIRCUIT ANALYSIS

Figure 1.9. Parallel resistance calculations and equivalent circuits.

The equivalent resistance at the network in Figure 1.9(b) is found by combining