Loops and Complexity in Digital Systems

Loops & Complexity
in
DIGITAL SYSTEMS
Lecture Notes on Digital Design

in
Giga-Gate per Chip Era
(work in never ending progress)
Gheorghe M. S
tefan
1st Loop

2nd Loop
GUESS
1st Loop
WHAT !
2011 version
Introduction
... theories become clear and reasonable only after incoherent parts of them have been used for a long time.
Paul Feyerabend1
The price for the clarity and simplicity of a reasonable

approach is its incompleteness.
Few legitimate questions about how to teach digital systems in Giga-Gate Per Chip Era
(G2CE) are waiting for an answer.
1. What means a complex digital system? How complex systems are designed using small
and simple circuits?
2. How a digital system expands its size, increasing in the same time its speed? Are there
simple mechanisms to be emphasized?
3. Is there a special mechanism allowing a hierarchical growing in a digital system? Or,
how new features can be added in a digital system?
The rst question occurs because already exist many dierent big systems which seem to have
dierent degree of complexity. For example: big memory circuits and big processors. Both are
implemented using a huge number of circuits, but the processors seem to be more complicated
than the memories. In almost all text books complexity is related only with the dimension of
the system. Complexity means currently only size, the concept being unable to make necessary
distinctions in G2CE. The last improvements of the microelectronic technologies allow us to put
on a Silicon die around a billion of gates, but the design tools are faced with more than the size
of the system to be realized in this way. The size and the complexity of a digital system must
be distinctly and carefully dened in order to have a more exible conceptual environment for
designing, implementing and testing systems in G2CE.
The second question rises in the same context of the big and the complex systems. Growing
a digital system means both increasing its size and its complexity. How are correlated these two
growing processes? The dynamic of adding circuits and of adding adding features seems to be
very dierent and governed by distinct mechanisms.
The third question occurs in the hierarchical contexts in which the computation is dened.
For example, Kleenes functional hierarchy or Chomskys grammatical hierarchy are dened to
1
Paul Feyerabend (b.1924, d.1994), having studied science at the University of Vienna, moved into philosophy
for his doctoral thesis. He became a critic of philosophy of science itself, particularly of rationalist attempts to
lay down or discover rules of scientic method. His rst book, Against Method (1975), sets out epistemological
anarchism, whose main thesis was that there is no such thing as the scientic method.
4
explain how computation or formal languages used in computation evolve from simple to complex. Is this hierarchy reected in a corresponding hierarchical organization of digital circuits?
It is obvious that a sort of similar hierarchy must be hidden in the multitude of features already
emphasized in the world of digital circuits. Let be the following list of usual terms: boolean
functions, storing elements, automata circuits, nite automata, memory functions, processing
functions, . . ., self-organizing processes, . . .. Is it possible to disclose in this list a hierarchy, and
more, is it possible to nd similarities with previously exemplied hierarchies?
The rst answer will be derived from the Kolmogorov-Chaitin algorithmic complexity: the
complexity of a circuit is related with the dimension of its shortest formal description. A big circuit (a circuit built using a big number o gates) can be simple or complex
depending on the possibility to emphasize repetitive patterns in its structure. A no pattern
circuit is a complex one because its description has the dimension proportional with its size.
Indeed, for a complex, no pattern circuit each gate must be explicitly specied.
The second answer associate the composition with sizing and the loop with featuring.
Composing circuits results biggest structures with the same kind of functionality, while closing
loops in a circuit new kind of behaviors are induced. Each new loop adds more autonomy to the
system, because increases the dependency of the output signals in the detriment of the input
signals. Shortly, appropriate loops means more autonomy that is equivalent sometimes with a
new level of functionality.
The third answer is given by proposing a taxonomy for digital systems based on the maximum number of included loops closed in a certain digital system. The old distinction between
combinational and sequential, applied only to circuits, is complemented with a classication
taking into the account the functional and structural diversity of the digital systems used in
the contemporary designs. More, the resulting classication provides classes of circuits having
direct correspondence with the levels belonging to Kleenes and Chomskys hierarchies.
The rst part of the book Digital Systems: a Birds-Eye View is a general introduction
in digital systems framing the digital domain in the larger context of the computational sciences,
introducing the main formal tool for describing, simulating and synthesizing digital systems, and
presenting the main mechanisms used to structure digital systems. The second part of the book
Looping in Digital Systems deals with the main eects of the loop: more autonomy and
segregation between the simple parts and the complex parts in digital systems. Both, autonomy
and segregation, are used to minimize size and complexity. The third part of the book Loop
Based Morphisms contains three attempts to make meaningful connections between the
domain of the digital systems, and the elds of recursive functions, of formal languages and of
information theories. The last chapter sums up the main ideas of the book making also some new
correlations permitted by its own nal position. The book ends with a lot of annexes containing
short reviews of the prerequisite knowledge (binary arithmetic, Boolean functions, elementary
digital circuits, automata theory), compact presentations of the formal tools used (pseudo-code
language, Verilog HDL), examples, useful data about real products (standard cell libraries).
PART I: Digital Systems: a Birds-Eye View
The rst chapter: Whats a Digital System? Few general questions are answered in this
chapter. One refers to the position of digital system domain in the larger class of the sciences of
computation. Another asks for presenting the ways we have to implement actual digital systems.
The importance is also to present the correlated techniques allowing to nalize a digital product.
The second chapter: Lets Talk Digital Circuits in Verilog The rst step in approaching
the digital domain is to become familiar with a Hardware Description Language (HDL) as the
5
main tool for mastering digital circuits and systems. The Verilog HDL is introduced and in the
same time used to present simple digital circuits. The distinction between behavioral descriptions
and structural descriptions is made when Verilog is used to describe and simulate combinational
and sequential circuits. The temporal behaviors are described, along with solutions to control
them.
The third chapter: Scaling & Speeding & Featuring The architecture and the organization of a digital system are complex objectives. We can not be successful in designing big
performance machine without strong tools helping us to design the architecture and the high
level organization of a desired complex system. These mechanisms are three. One helps us to
increase the brute force performance of the system. It is composition. The second is used to
compensate the slow-down of the system due to excessive serial composition. It is pipelining.
The last is used to add new features when they are asked by the application. It is about closing
loops inside the system in order to improve the autonomous behaviors.
The fourth chapter: The Taxonomy of Digital Systems A loop based taxonomy for
digital systems is proposed. It classies digital systems in orders, as follows:
0-OS: zero-order systems - no-loop circuits - containing the combinational circuits;
1-OS: 1-order systems - one-loop circuits - the memory circuits, with the autonomy of the
internal state; they are used mainly for storing
2-OS: 2-order systems - two-loop circuits - the automata, with the behavioral autonomy
in their own state space, performing mainly the function of sequencing
3-OS: 3-order systems - three-loop circuits - the processors, with the autonomy in interpreting their own internal states; they perform the function of controlling
4-OS: 4-order systems - four-loop circuits - the computers, which interpret autonomously
the programs according to the internal data
...
n-OS: n-order systems - n-loop circuits - systems in which the information is interpenetrated with the physical structures involved in processing it; the distinction between data
and programs is surpassed and the main novelty is the self-organizing behavior.
The fth chapter: Our Final Target A small and simple programmable machine, called
toyMachine is dened using a behavioral description. In the last chapter of the second part a
structural design of this machine will be provided using the main digital structure introduced
meantime.
PART II: Looping in Digital Domain
The sixth chapter: Gates The combinational circuits (0-OS) are introduced using a functional approach. We start with the simplest functions and, using dierent compositions, the
basic simple functional modules are introduced. The distinction between simple and complex
combinational circuits is emphasized, presenting specic technics to deal with complexity.
6
The seventh chapter: Memories There are two ways to close a loop over the simplest
functional combinational circuit: the one-input decoder. One of them oers the stable structure
on which we ground the class of memory circuits (1-OS) containing: the elementary latches,
the master-slave structures (the serial composition), the random access memory (the parallel
composition) and the register (the serial-parallel composition). Few applications of storing
circuits (pipeline connection, register le, content addressable memory, associative memory) are
described.
The eight chapter: Automata Automata (2-OS) are presented in the fourth chapter. Due
to the second loop the circuit is able to evolve, more or less, autonomously in its own state
space. This chapter begins presenting the simplest automata: the T ip-op and the JK ipop. Continues with composed congurations of these simple structures: counters and related
structures. Further, our approach makes distinction between the big sized, but simple functional
automata (with the loop closed through a simple, recursive dened combinational circuit that
can have any size) and the random, complex nite automata (with the loop closed through a
random combinational circuit having the size in the same order with the size of its denition).
The autonomy oered by the second loop is mainly used to generate or to recognize specic
sequences of binary congurations.
The ninth chapter: Processors The circuits having three loops (3-OS) are introduced. The
third loop may be closed in three ways: through a 0-OS, through an 1-OS or through a 2-OS,
each of them being meaningful in digital design. The rst, because of the segregation process
involved in designing automata using JK ip-ops or counters as state register. The size of
the random combinational circuits that compute the state transition function is reduced, in the
most of case, due to the increased autonomy of the device playing the role of the register. The
second type of loop, through a memory circuit, is also useful because it increases the autonomy
of the circuit so that the control exerted on it may be reduced (the circuit knows more about
itself). The third type of loop, that interconnects two automata (an functional automaton and
a control nite automaton), generates the most important digital circuits: the processor.
The tenth chapter: Computers The eects of the fourth loop are shortly enumerated in the
sixth chapter. The computer is the typical structure in 4-OS. It is also the support of the strongest
segregation between the simple physical structure of the machine and the complex structure of
the program (a symbolic structure). Starting from the fourth order the main functional up-dates
are made structuring the symbolic structures instead of restructuring circuits. Few new loops
are added in actual designs only for improving time or size performances, but not for adding
new basic functional capabilities. For this reason our systematic investigation concerning the
loop induced hierarchy stops with the fourth loop. The toyMachine behavioral description is
revisited and substituted with a pure structural description.
The eleventh chapter: Self-Organizing Structures ends the rst part of the book with
some special circuits which belongs to n-OSs. The cellular automata, the connex memory and
the eco-chip are n-loop structures that destroy the usual architectural thinking based on the
distinction between the physical support for symbolic structures and the circuits used for processing them. Each bit/byte has its own processing element in a system which performs the
nest grained parallelism.
The twelfth chapter: Global-Loop Systems Why not a hierarchy of hierarchies of loops?
Having an n-order system how new features can be added? A possible answer: adding a
7
global loop. Thus, a new hierarchy of super-loops starts. It is not about science ction.
ConnexArrayT M is an example. It is described, evaluated and some possible applications
are presented.
The main stream of this book deals with the simple and the complex in digital systems, emphasizing them in the segregation process that opposes simple structures of circuits to the complex
structures of symbols. The functional information oers the environment for segregating the
simple circuits from the complex binary congurations.
When the simple is mixed up with the complex, the apparent complexity of the system
increases over its actual complexity. We promote design methods which reduce the apparent
complexity by segregating the simple from the complex. The best way to substitute the apparent
complexity with the actual complexity is to drain out the chaos from order. One of the most
important conclusions of this book is that the main role of the loop in digital systems is to
segregate the simple from the complex, thus emphasizing and using the hidden resources of
autonomy.
In the digital systems domain prevails the art of disclosing the simplicity because there
exists the symbolic domain of functional information in which we may ostracize the complexity.
But, the complexity of the process of disclosing the simplicity exhausts huge resources of imagination. This book oers only the starting point for the architectural thinking: the art of nding
the right place of the interface between simple and complex in computing systems.
Acknowledgments
Contents
I
A BIRDS-EYE VIEW ON DIGITAL SYSTEMS
1 WHATS A DIGITAL SYSTEM?

1.1 Framing the digital design domain . . .
1.2 Simple introductory examples . . . . . .
1.3 Dierent embodiment of digital systems
1.4 Correlated domains . . . . . . . . . . . .
1.5 Problems . . . . . . . . . . . . . . . . .
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3
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2 LETS TALK IN VERILOG!

2.1 Pseudo-code languages & algorithms . . . . .
2.2 Finite input vs. innite input algorithms .
2.3 History free systems & combinational circuits
2.4 History sensitive systems & sequential circuits
2.5 Time restrictions in digital systems . . . . . .
2.5.1 Pipelined connections . . . . . . . . .
2.5.2 Fully buered connections . . . . . . .
2.6 Concluding about Verilog & digital systems .
2.7 Problems . . . . . . . . . . . . . . . . . . . .
2.8 Projects . . . . . . . . . . . . . . . . . . . . .
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3 GROWING & SPEEDING & FEATURING

3.1 Size vs. Complexity . . . . . . . . . . . . . . . . . .
3.2 Growing the size by composition . . . . . . . . . . .
3.3 Speeding by pipelining . . . . . . . . . . . . . . . . .
3.3.1 Register transfer level . . . . . . . . . . . . .
3.3.2 Pipeline structures . . . . . . . . . . . . . . .
3.3.3 Data parallelism vs. time parallelism . . . . .
3.4 Featuring by closing new loops . . . . . . . . . . . .
3.4.1 Data dependency . . . . . . . . . . . . . . .
3.4.2 Speculating to avoid limitations imposed by
3.5 Concluding about composing & pipelining & looping
3.6 Problems . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Projects . . . . . . . . . . . . . . . . . . . . . . . . .
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4 THE TAXONOMY OF DIGITAL SYSTEMS

4.1 Loops & Autonomy . . . . . . . . . . . . . . . .
4.2 Classifying Digital Systems . . . . . . . . . . .
4.3 # Digital Systems . . . . . . . . . . . . . . . .
4.4 Preliminary Remarks On Digital Systems . . .
4.5 Problems . . . . . . . . . . . . . . . . . . . . .
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10
CONTENTS
4.6
Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 OUR FINAL TARGET

5.1 toyMachine: a small & simple computing machine
5.2 How toyMachine works . . . . . . . . . . . . . . . .
5.3 Concluding about toyMachine . . . . . . . . . . . .
5.4 Problems . . . . . . . . . . . . . . . . . . . . . . .
5.5 Projects . . . . . . . . . . . . . . . . . . . . . . . .
II
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91
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. 103
. 104
. 104
LOOPING IN THE DIGITAL DOMAIN
6 GATES:
Zero order, no-loop digital systems
6.1 Simple, Recursive Dened Circuits . . . . . . . . . . . . . . .
6.1.1 Decoders . . . . . . . . . . . . . . . . . . . . . . . . .
Informal denition . . . . . . . . . . . . . . . . . . . .
Formal denition . . . . . . . . . . . . . . . . . . . . .
Recursive denition . . . . . . . . . . . . . . . . . . .
Structural description . . . . . . . . . . . . . . . . . .
Arithmetic interpretation . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Demultiplexors . . . . . . . . . . . . . . . . . . . . . .
Formal denition . . . . . . . . . . . . . . . . . . . . .
6.1.3 Multiplexors . . . . . . . . . . . . . . . . . . . . . . .
Formal denition . . . . . . . . . . . . . . . . . . . . .
Structural aspects . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . .
6.1.4 Shifters . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.5 Priority encoder . . . . . . . . . . . . . . . . . . . .
6.1.6 Increment circuit . . . . . . . . . . . . . . . . . . . . .
6.1.7 Adders . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carry-Look-Ahead Adder . . . . . . . . . . . . . . . .
Carry-Save Adder . . . . . . . . . . . . . . . . . . .
6.1.8 Combinational Multiplier . . . . . . . . . . . . . . .
6.1.9 Arithmetic and Logic Unit . . . . . . . . . . . . . . .
6.1.10 Comparator . . . . . . . . . . . . . . . . . . . . . . . .
6.1.11 Sorting network . . . . . . . . . . . . . . . . . . . .
Bathcers sorter . . . . . . . . . . . . . . . . . . . . . .
6.1.12 Prex computation network . . . . . . . . . . . . . .
6.1.13 First detection network . . . . . . . . . . . . . . . .
6.1.14 Spiras theorem . . . . . . . . . . . . . . . . . . . . .
6.2 Complex, Randomly Dened Circuits . . . . . . . . . . . . . .
6.2.1 An Universal circuit . . . . . . . . . . . . . . . . . . .
6.2.2 Using the Universal circuit . . . . . . . . . . . . . . .
6.2.3 The many-output random circuit: Read Only Memory
90
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107
108
109
109
109
110
111
112
112
113
113
113
114
115
115
115
116
116
117
118
120
122
122
124
125
128
129
132
133
134
135
137
139
139
139
142
144
CONTENTS
6.3
6.4
6.5
11
Concluding about combinational circuits . . . . . . . . . . . . . . . . . . . . . . . 149

Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7 MEMORIES:
First order, 1-loop digital systems
7.1 Stable/Unstable Loops . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Elementary Structures . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Elementary Latches . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Elementary Clocked Latches . . . . . . . . . . . . . . . . . .
7.2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 The Serial Composition: the Edge Triggered Flip-Flop . . . . . . . .
7.3.1 The Master-Slave Principle . . . . . . . . . . . . . . . . . . .
7.3.2 The D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3 The Serial Register . . . . . . . . . . . . . . . . . . . . . . . .
7.4 The Parallel Composition: the Random Access Memory . . . . . . .
7.4.1 The n-Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 Asynchronous Random Access Memory . . . . . . . . . . . .
Expanding the number of bits per word . . . . . . . . . . . .
Expanding the number of words by two dimension addressing
7.5 The Serial-Parallel Composition: the Register . . . . . . . . . . . . .
7.6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1 Synchronous RAM . . . . . . . . . . . . . . . . . . . . . . . .
7.6.2 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.3 Field Programmable Gate Array FPGA . . . . . . . . . . .
The system level organization of an FPGA . . . . . . . . . .
The IO interface . . . . . . . . . . . . . . . . . . . . . . . . .
The switch node . . . . . . . . . . . . . . . . . . . . . . . . .
The basic building block . . . . . . . . . . . . . . . . . . . . .
The congurable logic block . . . . . . . . . . . . . . . . . . .
7.6.4 Content Addressable Memory . . . . . . . . . . . . . . . . .
7.6.5 An Associative Memory . . . . . . . . . . . . . . . . . . . .
7.6.6 First-Order Systolic Systems . . . . . . . . . . . . . . . . .
7.7 Concluding About Memory Circuits . . . . . . . . . . . . . . . . . .
7.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 AUTOMATA:
Second order, 2-loop digital systems
8.1 Optimizing DFF with an asynchronous automaton
8.2 Two States Automata . . . . . . . . . . . . . . . .
8.2.1 The Smallest Automaton: the T Flip-Flop .
8.2.2 The JK Automaton: the Greatest Flip-Flop
8.2.3 Serial Arithmetic . . . . . . . . . . . . . .
8.2.4 Universal 2-input and 2-state automaton
8.3 Functional Automata: the Simple Automata . . . .
8.3.1 Counters . . . . . . . . . . . . . . . . . . .
8.3.2 Accumulator Automaton . . . . . . . . .
8.3.3 Bit-eater automaton . . . . . . . . . . .
8.4 Composing with simple automata . . . . . . . . .
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155
157
158
158
161
162
164
165
166
167
168
168
169
171
172
174
175
175
176
177
178
179
179
180
181
182
183
185
187
188
193
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197
199
201
201
202
202
203
204
204
206
207
208
12
CONTENTS
LIFO memory . . . . . . . . . . . . .
FIFO memory . . . . . . . . . . . . .
The Multiply-Accumulate Circuit . .
# With 2-radix multiplication . . . . .
# With 4-radix multiplication . . . . .
With bits eater automaton . . . . . .
8.5 Finite Automata: the Complex Automata . . .
8.5.1 Basic Congurations . . . . . . . . . . .
8.5.2 Designing Finite Automata . . . . . . .
8.5.3 Control Automata: the First Turning
Verilog descriptions for CROM . . . . .
Binary code generator . . . . . . . . . .
8.6 Automata vs. Combinational Circuits . . . .
8.7 The Circuit Complexity of a Binary String .
8.8 Concluding about automata . . . . . . . . . . .
8.9 Problems . . . . . . . . . . . . . . . . . . . . .
8.10 Projects . . . . . . . . . . . . . . . . . . . . . .
8.4.1
8.4.2
8.4.3
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208
210
212
212
212
212
213
213
214
221
226
228
230
233
235
236
241
9 PROCESSORS:
Third order, 3-loop digital systems
9.1 Implementing nite automata with intelligent registers . . . . . .
9.1.1 Automata with JK registers . . . . . . . . . . . . . . . .
9.1.2 Automata using counters as registers . . . . . . . . . . . .
9.2 Loops closed through memories . . . . . . . . . . . . . . . . . . . .
Version 1: the controlled Arithmetic & Logic Automaton .
Version 2: the commanded Arithmetic & Logic Automaton
9.3 Loop coupled automata: the second turning point . . . . . . . .
9.3.1 # Sequential divider . . . . . . . . . . . . . . . . . . . . .
9.3.2 Push-down automata . . . . . . . . . . . . . . . . . . . .
9.3.3 The elementary processor . . . . . . . . . . . . . . . . . . .
9.3.4 Executing instructions vs. interpreting instructions . . . . .
Von Neumann architecture / Harvard architecture . . . . .
9.3.5 An executing processor . . . . . . . . . . . . . . . . . . . .
The organization . . . . . . . . . . . . . . . . . . . . . . . .
The instruction set architecture . . . . . . . . . . . . . . . .
Implementing toyRISC . . . . . . . . . . . . . . . . . . . . .
The time performance . . . . . . . . . . . . . . . . . . . . .
9.3.6 An interpreting processor . . . . . . . . . . . . . . . . . .
The organization . . . . . . . . . . . . . . . . . . . . . . . .
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . .
Instruction set architecture (ISA) . . . . . . . . . . . . . . .
Implementing ISA . . . . . . . . . . . . . . . . . . . . . . .
Time performance . . . . . . . . . . . . . . . . . . . . . . .
Concluding about our CISC processor . . . . . . . . . . . .
9.4 The assembly language: the lowest programming level . . . . . .
9.5 Concluding about the third loop . . . . . . . . . . . . . . . . . . .
9.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.7 Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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243
245
245
248
250
251
251
252
252
252
254
258
260
261
261
262
264
264
264
264
269
269
270
278
279
279
279
280
280
CONTENTS
13
10 COMPUTING MACHINES:
4loop digital systems
10.1 Types of fourth order systems . . . . . . . . . . . . . . . . . . . .
10.1.1 The computer support for the strongest segregation . .
10.2 The stack processor a processor as 4-OS . . . . . . . . . . . .
10.2.1 The organization . . . . . . . . . . . . . . . . . . . . . .
10.2.2 The micro-architecture . . . . . . . . . . . . . . . . . . .
10.2.3 The instruction set architecture . . . . . . . . . . . . . .
10.2.4 Implementation: from micro-architecture to architecture
10.2.5 Time performances . . . . . . . . . . . . . . . . . . . . .
10.2.6 Concluding about our Stack Processor . . . . . . . . . .
10.3 Embedded computation . . . . . . . . . . . . . . . . . . . . . . .
10.3.1 The structural description of toyMachine . . . . . . . . .
The top module . . . . . . . . . . . . . . . . . . . . . . .
The interrupt unit . . . . . . . . . . . . . . . . . . . . . .
The control section . . . . . . . . . . . . . . . . . . . . . .
The data section . . . . . . . . . . . . . . . . . . . . . . .
Multiplexors . . . . . . . . . . . . . . . . . . . . . . . . .
Concluding about toyMachine . . . . . . . . . . . . . .
10.3.2 Interrupt automaton: the asynchronous version . . . . . .
10.4 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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281
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291
295
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296
296
296
299
299
301
304
305
305
308
308
11 # SELF-ORGANIZING STRUCTURES:
N-th order digital systems
11.1 Push-Down Stack as n-OS . . . . . . . . . . .
11.2 Cellular automata . . . . . . . . . . . . . . .
11.2.1 General denitions . . . . . . . . . . .
11.3 Systolic systems . . . . . . . . . . . . . . . . .
11.4 Fractal structures . . . . . . . . . . . . . . . .
11.5 Problems . . . . . . . . . . . . . . . . . . . .
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309
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12 # GLOBAL-LOOP SYSTEMS
First-order super-systems
319
T
M
12.1 ConnexArray
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12.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
III
ANNEXES
321
A Pseudo-code language
B Boolean functions
B.1 Short History . . . . . . . . . . . .
B.2 Elementary circuits: gates . . . . .
B.2.1 Zero-input logic circuits . .
B.2.2 One input logic circuits . .
B.2.3 Two inputs logic circuits . .
B.2.4 Many input logic circuits .
B.3 How to Deal with Logic Functions
B.4 Minimizing Boolean functions . . .
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14
CONTENTS
B.4.1 Canonical forms . . . . . . . . . . . . .
B.4.2 Algebraic minimization . . . . . . . . .
Minimal depth minimization . . . . . .
Multi-level minimization . . . . . . . . .
Many output circuit minimization . . .
B.4.3 Veitch-Karnaugh diagrams . . . . . . .
Minimizing with V-K diagrams . . . . .
Minimizing incomplete dened functions
V-K diagrams with included functions .
B.5 Problems . . . . . . . . . . . . . . . . . . . . .
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329
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D Standard cell libraries

D.1 Main parameters . . . . . . . . . . . . . . . . . .
D.2 Basic cells . . . . . . . . . . . . . . . . . . . . . .
D.2.1 Gates . . . . . . . . . . . . . . . . . . . .
Two input AND gate: AND2 . . . . . . .
Two input OR gate: OR2 . . . . . . . . .
Three input AND gate: AND3 . . . . . .
Three input OR gate: OR3 . . . . . . . .
Four input AND gate: AND4 . . . . . . .
Four input OR gate: OR4 . . . . . . . . .
Four input AND-OR gate: ANDOR22 . .
Invertor: NOT . . . . . . . . . . . . . . .
Two input NAND gate: NAND2 . . . . .
Two input NOR gate: NOR2 . . . . . . .
Three input NAND gate: NAND3 . . . .
Three input NOR gate: NOR3 . . . . . .
Four input NAND gate: NAND4 . . . . .
Four input NOR gate: NOR4 . . . . . . .
Two input multiplexer: MUX2 . . . . . .
Two input inverting multiplexer: NMUX2
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353
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C Basic circuits
C.1 Actual digital signals . . . . .
C.2 CMOS switches . . . . . . . .
C.3 The Inverter . . . . . . . . . .
C.3.1 The static behavior . .
C.3.2 Dynamic behavior . .
C.3.3 Buering . . . . . . .
C.3.4 Power dissipation . . .
C.4 NAND & NOR gates . . . . .
C.5 AND-NOR gates . . . . . . .
C.6 Many-Input Gates . . . . . .
C.7 The Tristate Buers . . . . .
C.8 The Transmission Gate . . .
C.9 # Memory Circuits . . . . . .
C.9.1 Flip-ops . . . . . . .
C.9.2 Static memory cell . .
C.9.3 Array of cells . . . . .
C.9.4 Dynamic memory cell
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CONTENTS
15
Two input XOR: XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

D.2.2 # Flip-ops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
E Finite Automata
E.1 Basic denitions in automata theory . . . . . . . . . . . . .
E.2 How behaves a nite automata . . . . . . . . . . . . . . . .
E.3 Representing nite automata . . . . . . . . . . . . . . . . .
E.3.1 Flow-charts . . . . . . . . . . . . . . . . . . . . . . .
The ow-chart for a half-automaton . . . . . . . . .
The ow-chart for a Moore automaton . . . . . . . .
The ow-chart for a Mealy automaton . . . . . . . .
E.3.2 Transition diagrams . . . . . . . . . . . . . . . . . .
Transition diagrams for half-automata . . . . . . . .
Transition diagrams Moore automata . . . . . . . .
Transition diagrams Mealy automata . . . . . . . . .
E.3.3 Procedures . . . . . . . . . . . . . . . . . . . . . . .
HDL representations for Moore automata . . . . . .
HDL representations for Mealy automata . . . . . .
E.4 State codding . . . . . . . . . . . . . . . . . . . . . . . . . .
E.4.1 Minimal variation encoding . . . . . . . . . . . . . .
E.4.2 Reduced dependency encoding . . . . . . . . . . . .
E.4.3 Incremental codding . . . . . . . . . . . . . . . . . .
E.4.4 One-hot state encoding . . . . . . . . . . . . . . . .
E.5 Minimizing nite automata . . . . . . . . . . . . . . . . . .
E.5.1 Minimizing the size by an appropriate state codding
E.5.2 Minimizing the complexity by one-hot encoding . . .
E.6 Parasitic eects in automata . . . . . . . . . . . . . . . . . .
E.6.1 Asynchronous inputs . . . . . . . . . . . . . . . . . .
E.6.2 The Hazard . . . . . . . . . . . . . . . . . . . . . . .
Hazard generated by asynchronous inputs . . . . . .
Propagation hazard . . . . . . . . . . . . . . . . . .
Dynamic hazard . . . . . . . . . . . . . . . . . . . .
E.7 Fundamental limits in implementing automata . . . . . . .
F # Meta-stability
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359
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16
CONTENTS
Part I
A BIRDS-EYE VIEW ON
DIGITAL SYSTEMS
Chapter 1
WHATS A DIGITAL SYSTEM?

In the previous chapter
we can not nd anything because it does not exist, but we suppose the reader is familiar
with:
fundamentals about what means computation
basics about Boolean algebra and basic digital circuits (see Annexes Boolean Functions and Basic circuits for a short refresh)
the usual functions supposed to be implemented by digital sub-systems in the current
audio, video, communication, gaming, ... market products
In this chapter
general denitions related with the digital domain are used to reach the following targets:
to frame the digital system domain in the larger area of the information technologies
to present dierent ways the digital approach is involved in the design of the real
market products
to enlist and shortly present the related domains, in order to integrate better the
knowledge and skills acquired by studying the digital system design domain
In the next chapter
is a friendly introduction in both, digital systems and a HDLs (Hardware Description
Languages) used to describe, simulate, and synthesized them. The HDL selected for this
book is called Verilog. The main topics are:
the distinction between combinational and sequential circuits
the two ways to describe a circuit: behavioral or structural
how digital circuits behave in time.
CHAPTER 1. WHATS A DIGITAL SYSTEM?
Talking about Apple, Steve said, The system

is there is no system. Then he added, that
doest mean we dont have a process. Making the distinction between process and system
allows for a certain amount of uidity, spontaneity, and risk, while in the same time it
acknowledges the importance of dened roles
and discipline.
J. Young & W. Simon1
A process is a strange mixture of rationally
established rules, of imaginary driven chaos,
and of integrative mystery.
A possible good start in teaching about a complex domain is an informal one. The main
problems are introduced friendly, using an easy approach. Then, little by little, a more rigorous
style will be able to consolidate the knowledge and to oer formally grounded techniques. The
digital domain will be disclosed here alternating informal plane views with simple, formalized
real stu. Rather than imperatively presenting the digital domain we intend to disclose it in
step by step using a project oriented approach.
1.1
Framing the digital design domain
The domain of digital systems is considered as part of computing science. This, possible view
point presents the digital systems as systems which compute their associated transfer functions.
A digital system is seen as a sort of electronic system because of the technology used now to
implement it. But, from a functional view point it is simply a computational system, because future technologies will impose maybe dierent physical ways to implement it (using, for example,
dierent kinds of nano-technologies, bio-technologies, photon-based devices, . . ..). Therefore,
we decided to start our approach using a functionally oriented introduction in digital systems,
considered as a sub-domain of computing science. Technology dependent knowledge is always
presented only as a supporting background for various design options.
Where can be framed the domain of digital systems in the larger context of computing
science? A simple, informal denition of computing science oers the appropriate context for
introducing digital systems.
Denition 1.1 Computer science (see also Figure 1.1) means to study:
algorithms,
their hardware embodiment
and their linguistic expression
with extensions toward
hardware technologies
and real applications.
1
They co-authored iCon. Steve Jobs. The Greatest Second Act in the History of Business, an unauthorized
portrait of the co-founder of Apple.
1.1. FRAMING THE DIGITAL DESIGN DOMAIN
ALGORITHMS
digital systems
HARDWARE

TECHNOLOGY
abstract
R
LANGUAGES
R
APPLICATIONS
?
actual
Figure 1.1: What is computer science? The domain of digital systems provides techniques for
designing the hardware involved in computation.
The initial and the most abstract level of computation is represented by the algorithmic level.
Algorithms specify what are the steps to be executed in order to perform a computation. The
most actual level consists in two realms: (1) the huge and complex domain of the application
software and (2) the very tangible domain of the real machines implemented in a certain technology. Both contribute to implement real functions (asked, or aggressively imposed, my the
so called free market). An intermediate level provides the means to be used for allowing an
algorithm to be embodied in a physical structure of a machine or in an informational structure
of a program. It is about (1) the domain of the formal programming languages, and (2) the
domain of hardware architecture. Both of them are described using specic and rigorous formal
tools.
The hardware embodiment of computations is done in digital systems. What kind of formal tools are used to describe, in the most exible and ecient way, a complex digital system?
Figure 1.2 presents the formal context in which the description tools are considered. Pseudocode language is an easy to understand and easy to use way to express algorithms. Anything
about computation can be expressed using this kind of languages. By the rule, in a pseudo-code
language we express, for our (human) mind, preliminary, not very well formally expressed, ideas
about an algorithm. The main user of this kind of language is only the human mind. But,
for building complex applications or for accessing advanced technologies involved in building big
digital systems, we need rened, rigorous formal languages and specic styles to express computation. More, for a rigorous formal language we must take into account that the main user is
a merciless machine, instead of a tolerant human mind. Elaborated programming languages
(such as C++, Java, Prolog, Lisp) are needed for developing complex contexts for computation
and to write using them real applications. Also, for complex hardware embodiments specic
hardware description languages, HDL, (such as Verilog, VHDL, SystemC) are proposed.
Both, general purpose programming languages and HDLs are designed to describe something
for another program, mainly for a compiler. Therefore, they are more complex and rigorous than
a simple pseudo-code language.
The starting point in designing a digital system is to describe it using what we call a specication, shortly, a spec. There are many ways to specify a digital system. In real life a
hierarchy of specs are used, starting from high-level informal specs, and going down until the
most detailed structural description is provided. In fact, de design process can be seen as a
stream of descriptions which starts from an idea about how the new object to be designed behaves, and continues with more detailed descriptions, in each stage more behavioral descriptions
PSEUDO-CODE
LANGUAGE

HARDWARE DESCRIPTION
LANGUAGES
R
PROGRAMMING
LANGUAGES
Figure 1.2: The linguistic context in computer science. Human mind uses pseudo-code
languages to express informally a computation. To describe the circuit associated with the computation
a rigorous HDL (hardware description language) is needed, and to describe the program executing the
computation rigorous programming languages are used.
being converted in structural descriptions. At the end of the process a full structural description
is provided. The design process is the long way from a spec about what we intend to do to
another spec describing how our intention can be fullled.
At one end of this process there are innovative minds driven by the will to change the world.
In these imaginative minds there is no knowledge about how, there is only willingness about
what. At the other end of this process there are very skilled entities knowing how to do very
eciently what the last description provides. They do not care to much about the functionality
they implement. Usually, they are machines driven by complex programs.
In between we need a mixture of skills provided by very well instructed and trained people.
The role of the imagination and of the very specic knowledge are equally important.
How can be organized optimally a designing system to manage the huge complexity of this
big chain, leading from an idea to a product? There is no system able to manage such a complex
process. No one can teach us about how to organize a company to be successful in introducing,
for example, a new processor on the real market. The real process of designing and imposing a
new product is trans-systemic. It is a rationally adjusted chaotic process for which no formal
rules can ever provided.
Designing a digital system means to be involved in the middle of this complex process,
usually far away from its ends. A digital system designer starts his involvement when the
specs start to be almost rigorously dened, and ends its contribution before the technological
borders are reached.
However, a digital designer is faced in his work with few level of descriptions during the
execution of a project. More, the number of descriptions increases with the complexity of the
project. For a very simple project, it is enough to start from a spec and the structural description
of the circuit can be immediately provided. But for a very complex project, the spec must be
split in specs for sub-systems, each sub-system must be described rst by its behavior. The
process continue until enough simple sub-systems are dened. For them structural descriptions
can be provided. The entire system is simulated and tested. If it works synthesisable descriptions
are provided for each sub-system.
A good digital designer must be well trained in providing various description using an HDL.
She/he must have the ability to make, both behavioral and structural descriptions for circuits
having any level of complexity. Playing with inspired partitioning of the system, a skilled
1.2. SIMPLE INTRODUCTORY EXAMPLES
designer is one who is able to use appropriate descriptions to manage the complexity of the
design.
1.2
Simple introductory examples
Digital systems belong to the wider class of the discrete systems (systems having a countable
number of states). Therefore, a general denition for digital system can be done as a special
case of discrete system.
Denition 1.2 A digital system, DS, in its most general form is dened by specifying the ve
components of the following quintuple:
DS = (X, Y, S, f, g)
where: X {0, 1}n is the input set of n-bit binary congurations, Y {0, 1}m is the output
set of m-bit binary congurations, S {0, 1}q is the set of internal states of q-bit binary
congurations,
f : (X S) S
is the state transition function, and
g : (X S) Y
is the output transition function.
A digital system has two simultaneous evolutions:
the evolution of its internal state which takes into account the current internal state and
the current input generating the next state of the system
the evolution of its output which takes into account the current internal state and the
current input generating the current output.
The internal state of the system determines the partial autonomy of the system. It responds on
its outputs to the input variations taking into account both, the current input and the internal
state.
Because all the sets involved in the previous denition have the form {0, 1}s , each of the
s one-bit input, output, or state evolves in time switching between two values: 0 and 1. The
previous denition denes a system having an n-bit input, an m-bit output and a q-bit internal
state. If xt X, yt Y , qt Q are values on input, output, and of state at the discrete moment
of time t, then the behavior of the system is described by:
qt = f (qt1 , xt1 )
yt = g(qt , xt )
While the current output is computed from the current input and the current state, the current state was computed using the previous input and the previous state. The two functions
describing a discrete system belong to two distinct class of functions:
sequential functions : used to generate a sequence of values each of them iterated from its
predecessor (an initial value is always provided, and the i-th value cannot be computed
without computing all the previous i 1 values)
non-sequential functions : used to compute an output value starting only from the current
values applied on its inputs.
Depending on how the functions f and g are dened results a hierarchy of digital systems.
More on this in the next chapters.
The variable time is essential for the sequential functions, but for the non-sequential ones
it is meaningless.
Results the following requests for implementing actual digital systems:
the binary values 0 and 1 must be codded by two electric levels; the current technologies
work with 0 Volts for the value 0, and with a tension level in the range of 1-2 Volts for the
value 1
physical modules to compute functions like yt = g(qt , xt ), which continuously follow by
their output values yt any change on the inputs qt and xt
a master of the discrete time must be provided, in order to make consistent the simple
ideas as was, previous, next; it is about a specic signal having the period T which
swings between 0 ad 1, called clock, used to tick the discrete time with its active edge
(see Figure 2.1 where a clock, active on its positive edge, is shown)
a storing support to memorize the state between two successive discrete moments of time
is required; it is the register used to register, synchronized with the active edge of the
clock signal, the state computed at the moment t 1 in order to be used at the moment t
to compute a new state and a new output.
Tclock
clock

6
time
ti2
ti1
ti
ti+1
ti+2
Figure 1.3: The clock. This clock signal is active on its positive edge (negative edge as active edge is
also possible). The time interval between two positive transitions is the period Tclock of the clock signal.
Each positive transition marks a discrete moment of time.
The most complex part of dening a digital system is the description of the two functions f
and g. The complexity of dening how the system behaves is managed by using various HDLs.
Its the time for few example using the simplest forms for the functions f and g. Let us
consider rst the simple case of a system with no internal state (S = ):
DS = (X, Y, g)
where: X {0, 1}n is the input set of n-bit binary congurations, Y {0, 1}m is the output
set of m-bit binary congurations
g:XY
is the output transition function. Because the function g has the general form yt = g(qt , xt ) the
time evolution is not important and the actual system will be a clockless one with no internal
registers to store the state. The following examples give us only a avor about what digital
design means.
Example 1.1 Let us use the Verilog HDL to describe an adder for 4-bit numbers (see Figure
1.4a). The description which follows is a behavioral one, because we know what we intend to
design, but we do not know yet how to design the internal structure of an adder.
in0
in1
in2
in0
in0
in1
adder
inAdder
in1
out
adder
in0
sum
outAdder
in1
adder
out
out
threeAdder
?
a.
out
b.
Figure 1.4: The rst examples of digital systems. a. The two 4-bit numbers adder, called
adder. b. The structure of an adder for 3 4-bit numbers, called threeAdder.
The Verilog code describing the module adder is:

module adder(out, in0, in1);
output [3:0] out ;
input [3:0] in0 ;
input [3:0] in1 ;
assign out = in0 + in1;
endmodule
The story just told by the previous Verilog module is: the 4-bit adder has two inputs, in0,
in1, one output, out, and its output is continuously assigned to the value obtained by adding
modulo 16 the two input numbers.
What we just learned from the previous rst simple example is summarized in the following
VerilogSummary.
VerilogSummary 1 :
module : keyword which indicates the beginning of the description of a circuit as a module
having the name which immediately follows (in our example, the name is: adder)
endmodule : keyword which indicates the end of the modules description which started with
the previous keyword module
output : keyword used to declare a terminal as an output (in our example the terminal out is
declared as output)
10
input : keyword used to declare the terminal as an input (in our example the terminals in0
and in1 are declared as inputs)
assign : keyword called the continuous assignment, used here to specify the function performed
by the module (the output out takes continuously the value computed by adding the two
input numbers)
(...) : delimiters used to delimit the list of terminals (external connections)
, : delimiter to separate each terminal within a list of terminals
; : delimiter for end of line
[ . . . ]: delimiters which contains the denition of the bits associated with a connection, for
example [3:0] dene the number of bits for the three connections in the previous example
+ : the operator add, the only one used in the previous example.
The description of a digital system is a hierarchical construct starting from a top module
populated by modules, which are similarly dened. The process continues until very simple
module are directly described. Thus, the functions f and g are specied by HDL programs (in
our case, in the previous example by a Verilog program).
The main characteristic of the digital design is modularity. A problem is decomposed in
many simpler problems, which are solved similarly, and so on until very simple problems are
identied. Modularity means also to dene as many as possible identical modules in each design.
This allow to replicate many times the same module, already designed and validated. Many &
simple modules! Is the main slogan of the digital designer. Lets take another example which
uses as module the one just dened in the previous example.
Example 1.2 The previously exemplied module (adder) will be used to design a modulo 16
3-number adder, called threeAdder (see Figure 1.4b). It adds 3 4-bit numbers providing a 4-bit
result (modulo 16 sum). Follows the structural description:
module threeAdder(output
input
input
input
wire [3:0] sum;
adder
[3:0]
[3:0]
[3:0]
[3:0]
out,
in0,
in1,
in2);
inAdder(.out(sum),
.in0(in1),
.in1(in2)),
outAdder(.out(out),
.in0(in0),
.in1(sum));
endmodule
Two modules of adder type (dened in the previous example) are instantiated as inAdder,
outAdder, they are interconnected using the wire sum, and are connected to the terminals of the
threeAdder module. The resulting structure computes the sum of three numbers.
VerilogSummary 2 :
Another way to specify the type of terminals, inside the list of terminals
11
A new keyword: wire used to specify internal connections inside the current module (in
our example: the 4-bit (numbered from 3 to 0) connection, sum, between the output of a
module and the input of another module (see also Figure 1.4b))
How a previously dened module (in our example: adder) is two times instantiated using
two dierent names (inAdder and outAdder in our example)
A safe way to allocate the terminals for a module previously dened and instantiated
inside the current module: each original terminal name is preceded by a dot, and followed
by a parenthesis containing the name of the wire or of the terminal where it is connected
(in our example, outAdder( ... .in1(sum)) means: the terminal in1 of the instance
outAdder is connected to the wire sum)
The successive instantiations of the same module can be separated by a ,.
While the module adder is a behavioral description, the module threeAdder is a structural
one. The rst tells us what is the function of the module, and the second tells us how its
functionality is performed by using a structure containing two instantiation of a previously
dened subsystems, and an internal connection.
Once the design completed we need to know if the resulting circuit works correctly. A simple
test must be provided in what we call a simulation environment. It is a Verilog module
which contains, besides the device under test (dut) a stimulus generator and an output
device used to monitor the behavior of dut. In Figure 1.5 this simple simulation environment
is presented.
dut
in0
STIMULUS
in1
&
in2
MONITOR
out
in0
in1
threeAdder
in2
out
threeAdderSim
Figure 1.5: Simulation environment: the module threeAdderSim. The device under test
threeAdder is interconnected with a module which provides the inputs and monitors the output.
Example 1.3 The simulation for the circuit designed in the previous example is done using
the following Verilog module.
module threeAdderSim;
// STIMULUS & MONITOR SECTION
reg
[3:0]
in0, in1, in2;
wire
[3:0]
out;
initial begin
in0 = 4b0011
in1 = 4b0100
;
;
12
#2
#2
#2
#2
in2 =
in0 =
in2 =
in1 =
$stop
4b1000
in0 + 1
in2 + in0
0
;
;
;
;
;
end
initial
$monitor
("time = %d, in0 = %d, in1 = %d, in2 = %d, out = %d, out = %b",
$time, in0, in1, in2, out, out);
// DEVICE UNDER TEST
threeAdder dut(out, in0, in1, in2);
endmodule
The module threeAdderSim includes the device under test threeAdder module , and a
module which provides the environment for the module to be tested. The environment-module
contains registers used to store the input variables in0, in1, in2, and a monitor used to
print the evolving values on the terminals of the device under test.
The rst initial block describes the evolution of the three input variables, starting from the
time 0 until the end of simulation specied by $stop
The second initial block displays the evolution on the terminals of dut. The output terminal
out is twice displayed, once in decimal form and another time in binary form.
The two initial blocks are executed in parallel starting from the time 0 of the simulation.
The simulation provides the following result:
#
#
#
#
time
time
time
time
=
=
=
=
0,
2,
4,
6,
in0
in0
in0
in0
=
=
=
=
3,
4,
4,
4,
in1
in1
in1
in1
=
=
=
=
4,
4,
4,
0,
in2
in2
in2
in2
= 8, out
= 8, out
= 12, out
= 12, out
= 15, out = 1111

= 0, out = 0000
= 4, out = 0100
= 0, out = 0000
VerilogSummary 3 :
reg[n-1:0 ]: is an n-bit register used to store an n-bit state variable; it is usually loaded using
as trigger the active edge of clock
test module is another circuit (usually without external connections), used to simulate the
behavior of a specic module, containing:
registers, or other circuits, for providing the input variables of the tested circuit
an instantiation of the tested circuit
a monitor to display the behavior of the outputs of the tested circuit (or a signal
inside the tested circuit)
initial : initializes a block of commands executed only once, starting at the time 0 of the
simulation
begin : used to delimit the beginning of a block of behavioral statements (equivalent with "{"
in C programming language)
end : used to delimit the end of a block of behavioral statements (equivalent with "}" in C
programming language)
13
#< number > : species a delay of < number > time units (a time unit is an arbitrary unit
of time), and is used in a description only for the purpose of simulating circuits, but not
for synthesizing them
$stop : stops the process of simulation
$monitor : starts the simulation task of monitoring the signals selected in the associated list
$time : specify the time variable
%d : the number is represented as a decimal one
%b : the number is represented as a binary one
// : it is used to delimit the comment, the text which follows until the end of the current line.
The previous three examples represent a simple bottom-up approach in digital design. The
rst example dened an elementary module, the adder. The second, uses the adder to build the
structure of a 3-number adder. The rst two examples oered a simple image about what a nostate circuit can be, and about what the simulation is and how it can be used for a preliminary
test for our design.
Next step is to consider a simple example of a digital system having an internal state. Let
us consider the case of adding numbers represented on multiple by 4 bits using circuits able to
perform only 4-bit addition. As we know from elementary arithmetic the carry generated by
each 4-bit adder can be used to add numbers bigger than 15. Let say two 12-bit numbers must
be added. First, the least signicant 4 bits are added resulting the least signicant 4 bits of the
result and a value for the one-bit signal carry. The next 4 signicant bits of the operands are
added and the result is added with the one bit number carry, resulting the next 4 signicant
bits of the result and a new value for carry. The last step adds the most signicant 4 bits and
the value of carry, resulting the most signicant bits of the result. If the last value of carry is
considered, then it is the 13th bit of the result. The digital engine able to perform the previously
described operations uses its internal state to store the value of the carry signal in order to be
considered in the next step of computation. It is described in the next example.
Example 1.4 The digital system for the sequential addition has two 4-bit data inputs, in0,
in1, one 2-bit command input, com, a clock input, clk, and the 4-bit output sum. The command
input tells the system what to do in each clock cycle: if com[1] = 0, then the state of the
system do not change, else the state of the system takes the value of the carry resulting from
adding the current values applied on the data inputs; if com[0] = 0, then the current addition
ignores the value of carry stored as the internal state of the system, else the addition takes
into account the state as the carry generated in the previous addition cycle. The Verilog code
describing the system is the following:
/*
com
com
com
com
=
=
=
=
00
01
10
11
:
:
:
:
sum = in1 + in0

sum = in1 + in0 + carry
{carry, sum} = in1 + in0
{carry, sum} = in1 + in0 + carry
*/
module sequentialAdder(output
input
input
[3:0]
[3:0]
[3:0]
sum,
in0,
in1,
;
;
;
;
14

input
[1:0]
com,
input
clk);
; // the state register of the system
;
;
reg carry
wire cryOut
wire cry
assign
assign
cry = com[0] ? carry : 0

;
{cryOut, sum} = in0 + in1 + cry ;
always @(posedge clk) if (com[1]) carry = cryOut;

endmodule
The way this module is used is explained in the folowing simulation:

module testSequentialAdder;
reg
[3:0] in0;
reg
[3:0] in1;
reg
[1:0] com;
reg
clk;
wire [3:0] sum;
initial begin
forever
#1
clk = 0
;
clk = ~clk;
end
initial begin
#2
#2
#2
#2
com =
in1 =
in0 =
com =
in1 =
in0 =
com =
in1 =
in0 =
com =
in1 =
in0 =
com =
$stop
2b10 ;
4b1000;
4b1001;
2b11 ;
4b0000;
4b0001;
2b11 ;
4b0010;
4b0011;
2b11 ;
4b0010;
4b0011;
2b00 ;
;
end
sequentialAdder dut( sum,
in0,
in1,
com,
clk);
initial $monitor("time = %d clk = %b in1 = %b in0 = %b com = %b sum = %b carry = %b",
$time, clk, in1, in0, com, sum, dut.carry);
endmodule
The result of simulation is:

#
#
#
#
#
time
time
time
time
time
=
=
=
=
=
0
1
2
3
4
clk
clk
clk
clk
clk
=
=
=
=
=
0
1
0
1
0
in1
in1
in1
in1
in1
=
=
=
=
=
1000
1000
0000
0000
0010
in0
in0
in0
in0
in0
=
=
=
=
=
1001
1001
0001
0001
0011
com
com
com
com
com
=
=
=
=
=
10
10
11
11
11
sum
sum
sum
sum
sum
=
=
=
=
=
0001
0001
0010
0001
0101
carry
carry
carry
carry
carry
=
=
=
=
=
x
1
1
0
0
15
# time = 5 clk = 1 in1 = 0010 in0 = 0011 com = 11 sum = 0101 carry = 0
The result of synthesis is presented in Figure 1.6, where:

the adder module adds two 4-bit numbers (in1[3:0], in2[3:0]) and the one-bit number
cin (carry-in) providing the 4-bit sum (out[3:0]) and the one bit number cout (carry-out)
the one-bit register carry is used to store, synchronized with the positive edge of the clock
signal clk, the value of the carry signal, cout generated by the adder, only when the input
ce (clock enable) is 1 (com[1] = 1) enabling the switch of the register
the 2-input AND gate applies the output of the register to the cin only when com[0] = 1;
when com[0] = 0, cin = 0
com[0]
in1[3:0] in0[3:0]
in1
clk
com[1] ce
1
one-bit register
cryOut
in
carry
out
adder
cout
out
in0
cin
cry
AND gate
sum[3:0]
carry
Figure 1.6: Sequential adder.

Both, simulation and synthesis are performed using specic software tools (for example: ModelSim for simulations and Xilinx ISE for synthesis)
VerilogSummary 4 :
cond ? a : b : is the well known a C construct which selects a if cond = 1, else selects b
{a, b} : represent the concatenation of a with b
always @( <activating condition> ) : is a Verilog construct activated whenever the condition <activating condition> is fullled
posedge : keyword used to specify the positive edge of the clock signal (negedge species the
negative edge of the clock signal)
always @(posedge clock) : each positive transition of clock will trigger the action described
inside the body of the construct always
if (cond) ... : used to specify the conditioned execution
forever : keyword indicating an unending repetition of the subsequent action
16
name1.name2 : selects the signal name2 from the module name1
The previous examples oered a avor about what the digital design is: using an HDL
(Verilog, for example) two kinds of descriptions can be provided behavioral and structural
both, being used to simulate and/or to synthesize a digital system. Shortly: describe,
simulate, synthesize is the main triad of the digital design.
1.3
Dierent embodiment of digital systems
The physical embodiment of a digital system evolved, in the second part of the previous century,
from circuits built using vacuum tubes to now a day complex systems implemented on a single
die of silicon containing billions of components. We are here interested only by the actual
stage of technology characterized by an evolutionary development and a possible revolutionary
transition.
The evolutionary development is from the multi-chip systems approach to the system on a
chip (SoC) implementations.
The revolutionary transition is from Application Specic Integrated Circuit (ASIC) approach
to the fully programmable solutions for SoC.
SoC means integrating on a die a big system which, sometimes, involve more than one technology. Multi-chip approach was, and it is in many cases, necessary because of two reasons: (1)
the big size of the system and, more important, (2) the need of use of few incompatible technologies. For example, there are big technological dierences in implementing analog or digital
circuits. If the circuit is analog, there is also a radio frequency sub-domain to be considered.
The digital domain has also its specic sub-domain of the dynamic memories. Accommodating
on the same silicon die dierent technologies is possible but the price is sometimes too big. The
good news is that there are continuous technological developments providing cheap solutions for
integrating previously incompatible technologies.
An ASIC provides very ecient solutions for well dened functions and for big markets.
The main concern with this approach is the lack of functional exibility on a very fast evolving
market. Another problem with the ASIC approach is related with the reusability of the silicon
area which is a very expensive resource in a digital system. For example, if the multiplication
function is used in few stages of the algorithm performed by an ASIC, then a multiplication
circuit must be designed and placed on silicon few times even if the circuits stay some- or manytimes unused. An alternative solution provides only one multiplier which is shared by dierent
stages of the algorithm, if possible.
There are dierent types of programmable digital systems:
recongurable systems: are physical structures, having a set of useful features, can
be congured, to perform a specic function, by the binary content of some specic storage registers called conguring registers; the exibility of this approach is limited to the
targeted application domain
programmable circuits: are general purpose structures whose interconnection and simple functionality are both programmed providing any big and complex systems; but, once
the functionality in place, the system performs a x function
programmable systems: are designed using one or many programmable computing
machines able to provide any transfer function between its inputs and outputs.
1.4. CORRELATED DOMAINS
17
All these solutions must be evaluated takeing into account their exibility, speed performance, complexity, power consumption, and price. The exibility is minimal for congurable
systems and maximal for programmable circuits. Speed performance is easiest to be obtained
with recongurable systems, while the programmable circuits are the laziest at big complexities.
Complexity is maximal for programmable circuits and limited for recongurable systems. Power
consumption is minimal for recongurable solutions, and maximal for programmable circuits.
Price is minimal for recongurable systems, and maximal for programmable circuits. In all the
previous evaluations programmable systems are avoided. Maybe this is the reason for which
they provide overall the best solution!
Designing digital circuits is about the hardware support of programmable systems. This book
provides knowledge on circuits, but the nal target is to teach how to build various programmable
structures. Optimizing a digital system means to have a good balance between the physical
structure of circuits and the informational structure of programs running on them. Because the
future of complex systems belongs to the programmable systems, the hardware support oered
by circuits must be oriented toward programmable structures, whose functionality is actualized
by the embedded information (program).
Focusing on programmable structures does not mean we ignore the skills involved in designing
ASICs or recongurable systems. All we discuss about programmable structures applies also to
any kind of digital structure. What will happen will be that at a certain level in the development
of digital systems features for accepting program control will be added.
1.4
Correlated domains
Digital design must be preceded and followed by other disciplines. There are various prerequisites
for attending a digital design course. These disciplines are requested for two reasons:
the student must be prepared with an appropriate pool of knowledge
the student must be motivated to acquire a new skill.
In an ideal world, a student is prepared to attend digital design classes by having knowledge
about: Boolean algebra (logic functions, canonic forms, minimizing logic expressions), Automata
theory (formal languages, nite automata, . . . Turing Machine), Electronic devices (MOS transistor, switching theory), Switching circuits (CMOS structure, basic gates, transmission gate,
static & dynamic behavior of the basic structures).
In the same ideal world, a student can be motivated to approach the digital design domain if
he payed attention to Theory of computation, Microprocessor architecture, Assembly languages.
Attending the classes of Digital Systems is only a very important step on a long journey
which suppose to attend a lot of other equally important disciplines. The most important are
listed bellow.
Verication & testing For complex digital system verication and testing become very important tasks. The design must be veried to be sure that the intended functionality is in
place. Then in each stage, on the way from the initial design to the fabrication of the actual
chip, various tests are performed. Specic techniques are developed for verication and testing
depending on the complexity of the design. Specic design techniques are used to increase the
eciency of testing. Design for testability is a well developed sub-domain which helps us with
design tricks for increasing the accuracy and speed of testing.
18
Physical design The digital system designer provides only a description. It is a program
written in a HDL. This description must be used to build accurately an actual chip containing
many hundred of million of circuits. It is a multi-stage process where after circuit design,
simulation, synthesis, and functional verication, done by the digital design team, follow layout
design & verication, mask preparation, wafer fabrication, die test. During this long
process a lot of additional technical problem must be solved. A partial enumeration of them
follows.
Clock distribution: The clock signal is a pulse signal distributed almost uniformly on the
whole area of the chip. For a big circuit the clock distribution is a critical problem because
of the power involved and because of the accuracy of the temporal relation imposed for it.
Signal propagation: Besides clock there are a lot of other signals which can be critical
if they spread on big parts of the circuit area. The relation between these signals makes
the problem harder.
Chip interface circuits: The electrical charge of an interface circuit is much bigger than
for the internal one. The capacitance load on pins being hundred times bigger the usual
internal load, the output current for pin driver must be correspondingly.
Powering: The switching energy is provided from a DC power supply. The main problem
is to have enough energy right in time at the power connections of each circuit form the
chip. Power distribution is made dicult by the inductive eect of the power connections.
Cooling: The electrical energy introduced in circuit, through the power system, must be
then, unfortunately, extracted as caloric energy (heat) by cooling it.
Packaging: The silicon die is mounted in a package which must full a lot of criteria. It
must allow powering and cooling the die it contains. Also, it must provide hundreds or
even thousands external connections. Not to mention protection to cosmic rays, . . ..
Board design: The chips are designed to be mounted on boards where they are interconnected with other electronic components. Because of the very high density of connections,
designing a board is a very complex job involving knowledge from a lot of related domains
(electromagnetism, mechanics, chemistry, . . .).
System design: Actual applications are nalized as packaged systems containing one or
many boards, sometimes interconnected with electro-mechanical devices. Putting together
many components, powering them, cooling them, protecting them from disturbing external
(electromagnetic, chemical, mechanical, . . .) factors, adding esthetic qualities require multidisciplinary skills.
For all these problems specic knowledge must be acquired attending special classes, course
modules, or full courses.
Computer architecture Architectural thinking is a major tendency in the contemporary
word. It is a way to discuss about the functionality of an object ignoring its future actual
implementation. The architectural approach helps us to clarify rst what we intend to build,
unrestricted by the implementation issues. Computer architecture is a very important subdomain of computer science. It allow us to develop independently the hardware domain and the
software domain maintaining in the same time a high communicating channel between the two
technologies: one referring to the physical structures and another involving the informational
structure of programs.
1.5. PROBLEMS
19
Embedded systems In an advanced stage of development of digital system the physical

structure of the circuits start to be interleaved with the informational structure of programs.
Thus, the functional exibility of the system and its eciency is maximized. A digital system
tend to be more and more a computational system. The computation become embedded into
the core of a digital system. The discipline of embedded system or embedded computation2
starts to be a nis coronat opus of digital domain.
Project management Digital systems are complex systems. In order to nalize a real product a lot of activities must be correlated. Therefore, an ecient management is mandatory for a
successful project. More, the management of the digital system project has some specic aspects
to be taken into account.
Business & Marketing & Sales Digital systems are produced to be useful. Then, they must
spread in our human community in the most appropriate way. Additional, but very related skills
are needed to enforce on the market a new digital system. The knowledge about business, about
marketing and sales is crucial for imposing a new design. A good, even revolutionary idea is
necessary, but absolutely insucient. The pure technical skills must be complemented by skills
helping the access on the market, the only place where a design receives authentic recognition.
1.5
Problems
Problem 1.1 Let be the full 4-bit adder described in the following Verilog module:
module fullAdder(
output [3:0]
output
input [3:0]
input [3:0]
input
out
crOut
in0
in1
crIn
wire
[4:0]
sum ;
assign
assign
assign
sum
out
crOut
= in0 + in1 + crIn

= sum[3:0]
= sum[4]
,
,
,
,
);
// carry output
// carry input
;
;
;
endmodule
Use the module fullAdder to design the following 16-bit full adder:
module bigAdder(
output [15:0]
output
input [15:0]
input [15:0]
input
out
crOut
in0
in1
crIn
,
,
,
,
);
// carry output
// carry input
// ???
endmodule
The resulting project will be simulated designing the appropriate test module.
2
In DCAE chair of the Electronics Faculty, in Politehnica University of Bucharest this topics is taught as
Functional Electronics, a course introduced in late 70s by the Professor Mihai Draganescu.
20
Problem 1.2 Draw the block schematic of the following design:

module topModule(
wire
output [7:0]
input
[7:0]
input
[7:0]
input
[7:0]
wire1, wire2;
[7:0]
bottomModule
mod1(
out,
in1,
in2,
in3);
.out(wire1
.in1(in1
.in2(in2
.out(wire2
.in1(wire1
.in2(in3
.out(out
.in1(in3
.in2(wire2
mod2(
mod3(
),
),
)),
),
),
)),
),
),
));
endmodule
module bottomModule(
output
input
input
[7:0]
[7:0]
[7:0]
out,
in1,
in2);
// ...
endmodule
Synthesize it to test your solution.

Problem 1.3 Let be the schematic representation of the design topSyst in Figure 1.7. Write
the Verilog description of what is described in Figure 1.7. Test the result by synthesizing it.
in2
8
in3
in1
syst2
in2
in1
in1
in2
in1
?
in
in2
syst3
syst1
syst1
out
out
out
8
8
topSyst
in1
?
in2
syst2
a.
in2
in2
syst4
out
out
8
out2
in1
syst4
out2
?
in1
out1
out1
8
out1
out2
?
b.
Figure 1.7: The schematic of the design topSyst. a. The top module topSyst b. The structure
of the module syst2.
Chapter 2
LETS TALK IN VERILOG!

a general introduction in digital systems is done with the following emphasis:
the digital domain is part of the computer science, providing the physical support for
all the technologies involved in information processing
a digital system has many ways and levels of implementation, starting from pure
circuits and ending with fully programmable systems
there are a lot of related activities supporting the actual implementation of a digital
system; the digital design is only one important stage on the way leading to real
market products performing useful functions
In this chapter
a friendly introduction in Verilog HDL is provided. Meantime, generalities about digital
circuits (not systems) are introduced discussing the following topics:
how an algorithm can be converted into a digital circuit
the distinction between combinational (history free) and sequential (history sensitive)
circuits
time aware design in order to reach the expected performance.
In the next chapter
a preliminary discussion about how a big, fast and featured digital system can be dened and implemented, starting from small and simple digital circuits is presented. The
following mechanisms are introduced:
the composition mechanism to show how a digital system scales
the pipeline trick used to increase the speed of the system
the loop closed inside a digital circuit or system which acts adding new functional
features if it is appropriately used.
21
22
CHAPTER 2. LETS TALK IN VERILOG!
When we gain the ability to share our understanding of experiences with others, we are in
danger of losing contact with direct experience.
Arnold Mindell1
Using a formal language the eort of designing digital circuits is shared with formal tools,
but we face in the same time the danger of
less experiencing deep thoughts about digital
systems.
The HDL already adopted for this book is Verilog. It will be used to express rigorously our
thought about digital systems. Its similarity with the C language, one of the most common used
language, recommends it for this purpose. Both, C and Verilog borrow from the pseudo-code
language the main mechanisms to express an algorithm.
2.1
Pseudo-code languages & algorithms
An algorithm can be expressed in many forms. Currently a pseudo-code language can be used as
a primary form to manipulate ideas about a certain computation. Pseudo-code is any notation
that captures the ow of the circuit or of the program you are designing. It has its value in
providing a transition language situated between your ideas about how to solve a problem and
the corresponding program written in a programming language the machines can understand.
It outlines the general ow of what you want to do and how you want to do it, but it wont
run on a computer. The idea of algorithm expressed in pseudo-code is a non-formal concept.
Denition 2.1 Informally, an algorithm is:
a syntactic correct sequence
of eectively computable operations
which produces a result in a nite amount of time.
A rough idea about what a pseudo-language is can be obtained visiting Appendix Pseudocode language, where we can learn how an algorithm, or a pseudo-program, is expressed as a
procedure having a name and acting on few variables using a nite sequence of operations.
There are few kinds of operations. The input operations set the initial value of variables. The
output operation print, prints the value of the certain variables as intermediate or nal results
of computation. The same operation can be used to print certain messages about the evolution of
the computational process. There are simple operations used to modify the value of a variable
according to a logic or arithmetic operation applied to one or many variables. Because the
sequence of operations to be applied in a certain stage of computation depends, sometimes, by
a partial result of the current computation, the conditional execution allows to apply a string
of operations or another, according to the value of a tested condition. Other times, the same
sequence of operations must be executed a number of times given by the value of a variable
(can be an input variable or a variable computed at a certain stage of the current computation).
There are two kind of iterative executions. The rst tests the ending condition at the end of
the sequence, and the second tests the condition before executing the sequence.
1
From [Mindell 00] pag. 41
2.2. FINITE INPUT VS. INFINITE INPUT ALGORITHMS
23
A pseudo-program is a procedure and it can calls other procedures. Thus, an algorithm is

expressed by one procedure or many hierarchical dened procedures.
Example 2.1 The Euclids algorithms for computing the greatest common divider of two numbers is:
procedure gcd(a, b);
v = a;
w = b;
r = 0
// reminder
loop
r = v - (int(v/w) * w); // int(x) is integer part of x
v = w;
w = r;
until (r = 0)
print(v);
end
The previous algorithm is described in pseudo-code language only for the use of our mind,
as an intermediary step for two dierent possible purposes. One can be to write a program in
a formal programming language to be sent as input for a compiler which will generate code for
a specic machine. Another can be to write the description of a circuit, using a HDL language,
to be sent as input for a synthesis program which will generate a more or less detailed circuit
representation.
Neither the computer program nor the circuit will behave performing exactly the operations
used in the previous description. For example, in a high level programming language or in a HDL
the reminder will be determined using a simpler operations than a division. The translation of
a pseudo-code procedure is always a creative process taking into account the specic features
oered by the targeted language.
2.2
Finite input vs. innite input algorithms
Data used as input for an algorithm can be constant dimensioned or can have a undened dimension. Depending on how the input variables are dimensioned there are two kind of algorithms:
nite input algorithms: the input consists in a constant number of constant dimensioned
variables,
innite input algorithms: the input consists in a stream of variables with unknown,
usually big, length.
For example, a nite input algorithm is the algorithm for computing ab where a and b are 4-bit
signed integers:
procedure exp(a[3:0], b[3:0]);
...
end
The examples 2.1 (gcd(a,b)) and 2.2 (binary(x)) represent also nite input algorithms.
An example of innite input algorithm is the algorithm to search the occurrence of a
pattern (an m-symbol stream of ASCII characters) in a text (an n-symbol stream of ASCII
characters), where the length of the pattern and of the text are both unknown:
24

procedure search(
pattern_1[7:0], ... , pattern_m[7:0],

text_1[7:0], ... , text_n[7:0]
);
...
end
The exp procedure can be dened as a x length sequence of operations. But, for the
procedure search must be dened a family of mn sequences of operations in order to specify the
algorithm, because for each pair (m, n) another nite sequence of operations must be specied.
In order to avoid the use of a family of algorithms for the procedure search, it is reformulated
as the procedure sequential search dened as follows:
receive and memorize symbol by symbol a stream of symbols representing
the pattern, and search this pattern against the stream of symbols received and
memorized symbol by symbol as text.
Here the algorithm is transformed into a nite input algorithm. Now in each moment the
algorithm receives only one symbol and some additional information referring to how the symbol
must be interpreted (as belonging to text or to pattern or having no meaning, in our example).
The associated procedure is:
procedure sequential_search(symbol[7:0],
type[1:0] ,
clock
);
...
end
Now we have three kinds of input variables:

symbol: it belongs sometimes to the text stream, other times to the pattern stream, or
has no meaning
type: is the word indicating what kind of symbol is applied on the input symbol, i.e.,
whether symbol belongs to the text stream, to the pattern stream, or has no meaning for
the process we describe
clock: an one bit signal used to validate the occurrence of the pairs (symbol, type); it
indicates: now a new pair of data is stable on the other two inputs
Very important warning: the inputs symbol and text are allowed to change only when the
clock input is non active.
But, what means clock is active? Because the clock is used to indicate the moment
when for sure the other inputs are stable and meaningful, its active part must be as short as
possible. Thus, the variable clock is a digital periodic signal used to validate by its active
transition the other variables.
The clock is used to say when other events are for sure all stabilized at the new correlated
values. This very special signal is used to avoid the misinterpretation of the changing inputs.
For example, in the procedure sequential search the clock allows us avoiding to take many
times the same symbol, or to interpret a new symbol with an old type. Thus, the clock
signal is used to synchronize the evolution of the algorithm or of the associated machine
(digital circuit). It acts sampling the interrelated inputs only when they are both for sure stable,
i.e., far from the last change (the set-up time tsu ) and far from the next change (the hold
time tsu ). See Figure 2.1, where are represented the two time intervals, tsu and th , associated
to the input type. Actually, the clock is a periodic signal with the frequency: fclock = 1/Tclock
(see also Figure 2.1).
25
As a physical process the clock is a one-bit signal. Its behavior is presented in Figure 2.1
in the context of the sequential search algorithm. The moments of the truth, separated
from the previous transition by the set-up time (tsu ) and from the next transition by the hold
time (th ), are marked by the dashed lines in Figure 2.1. For each input the minimal values of
tsu and of th must be specied. Results the time interval (tsu min + th min ) as the moment in
which the other inputs (symbol and type) must be stable in order to have a clearly dened
meaning. In each clocked system the active edge of the clock must be dened. In Figure 2.1 the
active edge of clock is the positive edge. In this early stage of our approach we will approximate
the transition time of the clock to zero. (In actual systems the edge transition of the clock takes
no zero time.)
Tclock
clock
time
type[1:0]
su-
6
pattern
pattern
no meaning
text
th
text
text
time
symbol[7:0]
6
c
time
Figure 2.1: The clock signal. The variables type and symbol in procedure sequential search
have for sure a well dened meaning only at the positive transition of the signal clock. The set-up time
(tsu ) and the hold time (th ) are marked for the input type.
In the system dened by the procedure sequential search the order in which the inputs
symbol and type switch is not important, but the relation between these inputs and the clock
input is very important. Instead of correlating two complex signals, one having 8 bits and
another having 2 bits, we must solve a simplest problem: to correlate independently the two
signals with an 1-bit, very predictable (because it is periodic) signal.
Going back to our example, the procedure (or the associated machine it describes) receives
in each clock cycle, at the positive (or negative) transition of the periodic signal called clock,
a pair of data (symbol, type). Reformulating the problem in this way the algorithm starts to
look like a nite input one. It depends, in each moment, on a nite number of input variable,
but it is fundamentally dierent because when we say symbol by symbol the sequentially
evolving time comes into being and manifests embodied as the periodic clock signal. The
nite described algorithm has a very specic additional feature: it is able to work for a stream
of variables having any length. Therefore, it remains actually an innite input algorithm
which can be specied by a single nite sequence of operations.
Depending on the problem, the symbol streams are stored fully or partially into the ma-
26
chine associated to the algorithm as a more or less complex set of internal state values. These
state values help to determine the specic conditions involved in each step of computation.
The procedure sequential search has now, indeed in each moment a nite input, and it
is dened by one nite sequence of operations working for any pair (n, m). The associated
meanings for each input variable deserve additional comments.
About simultaneity The variable type has tree meaningful values indicating how to interpret
the variable symbol, as belonging to pattern, to text, or having no meaning for computation.
When type and symbol change they can not change simultaneously (for the simple reason that
in the actual world strict simultaneity does not exists, and engineering refers to actual
systems not to theoretically ideal ones). In our example, if type changes rst there is a time
interval when type and symbol belongs to dierent pairs (symbol, type), and they can not
interpreted as a well formed pair by the algorithm. Similarly, for the case when symbol changes
rst. If, hypothetically, they changes synchronously, then for sure no real system will be able to
be sensitive to this synchronicity. The time interval when the two input variables change must
by avoided, the algorithm and the associated machine ignoring the value of the two inputs in a
comfortable time neighborhood around the switches. These two interrelated inputs are correctly
sampled only using the third one-bit signal we already called clock.
The semantic dimension Receiving synchronously two or many input variables implies the
meaning of a variable depends at least on the value of the another one. (In our example: symbol
is interpreted according to the value of type.)
The internal state The complex behavior of the signals applied as inputs to an algorithm
(digital system) is mirrored by a similarly internal behavior of the algorithm/system. The
internal behavior manifests by changing in each clock cycle the internal state of the algorithm/system. The internal state is stored inside the system or in the values of variables inside an algorithm. The output provided by the computation belongs also to the overall state of
the algorithm/system. For the algorithm they are output variables, while for the machine they
are stored in output registers.
Let us have an example of an innite input machine. The full pseudo-code description will
be provided.
Example 2.2 The problem to be solved is to add a stream of maximum n m-bit numbers. The
innite input form of the algorithm has the form, leading to a family of algorithms:
procedure accumulate(number_1[m-1:0], ... number_n[m-1:0]);
...
end
The associated nite input algorithm is:

procedure accumulate(number[m-1:0],
com[1:0]
,
clock
);
acc = 0;
forever if (clock & (com = 01))
acc = 0
;
else if (clock & (com = 10)) acc = acc + number ;
endforever
end
27
The commands are codded with 2 bits, because they are 3 : noOperation (00), init (01)
and accumulate (10). The fourth binary conguration (11) is not used.
In the previous example the variable acc is the internal variable whose evolution stores the
partial sum of the already received numbers. This variable works like the internal state of the
algorithm.
We can state that the price for converting an innite input algorithm to a nite input
algorithm materializes in the following general feature of a digital system:
the semantic dimension: the meanings associated to dierent input of the system are
correlated (in the previous example, only when the command takes the value 10 the input
number is considered)
the clock controlled temporal behavior allowing:
to synchronize many-input algorithm/systems
to sequence the process of computation described by the algorithm for an actual
machine.
the evolving internal state which keeps the trace of the computational process.
The previous description is very good to oer a rough, not quite exact, image about the
function performed by the system which it describes. Our adaptive mind is able to understand
what is about, but the rigorous mind of a machine is not. A more rigorous description can
be oered using a HDL. A following Verilog description of the associated circuit is done for the
very rigorous tools like a compiler, a simulator or a synthesizer.
Example 2.3 Let us implement the accumulator circuit dened in the previous example. Let
be 256 the biggest value allowed for n, and m = 16. For a real circuit we can not avoid to dene
the actual dimensions associated with its physical resources.
module accumulator(output [23:0] out
,
input [15:0] number,
input [1:0] com
,
input
clock );
reg [23:0] acc;
// the function f
always @(posedge clock) if (com == 2b01)
acc = 0
;
else if (com == 2b10) acc = acc + number;
// the function g
assign out = acc;
endmodule
The internal state register acc has the capacity of storing 24 bits, because it must be able to
store the biggest number resulting from adding 256 16-bit numbers.
The state transition function f in this system is expressed by the always construct. The
function g is the simple identity function expressed by the assign construct.
A more compact representation of the circuit is:
28
module accumulator(output reg [23:0] acc

,
input
[15:0] number,
input
[1:0] com
,
input
clock );
always @(posedge clock) if (com == 2b01)
acc = 0
;
else if (com == 2b10) acc = acc + number;
endmodule
In this simple circuit the state and the output are identical.
Any design must be accompanied by the test module used to validate the project.
Example 2.4 The Verilog test module for accumulator module is:
module testAccumulator;
// INPUTS FOR DUT
reg [15:0] number;
reg [1:0] com
;
reg
clock ;
// OUTPUT OF DUT
wire [23:0] acc
;
// THE CLOCK GENERATOR
initial begin
clock = 0
;
forever #1 clock = ~clock;
end
// THE STIMULI GENERATOR
initial begin
com
= 2b00
;
#2 com
= 2b01
;
#2 com
= 2b10
;
number = 16b0000_1001;
#2 number = 16b0000_0001;
#2 number = 16b0000_0011;
#2 number = 16b0000_0010;
#2 number = 16b0000_0001;
#2 number = 16b0000_0001;
#2 com
= 2b01
;
#2 com
= 2b10
;
number = 16b0000_0001;
#2 number = 16b0000_1001;
#2 number = 16b0000_0001;
#2 number = 16b0000_0001;
#2 com
= 2b00
;
#2 $stop
;
end
// THE DEVICE UNDER TEST (DUT)
accumulator dut(acc
,
number,
com
,
clock );
// THE MONITOR
initial
$monitor("time = %d clock = %b com = %b number = %b number = %d acc = %b acc = %d",
$time, clock, com, number, number, acc, acc);
endmodule
29
The next step is the synthesis which provides a stream of implementations depending on the
targeted technology. A rst one is always a gate/cell level representation. It uses logic gates
and/or standard cells with currently used functionalities (adders, multipliers, registers, ...).
An algorithm working on stream of data (on innite input) has the history sensitive behavior allowed by the internal state which changes with each active edge of clock. Unlike the
history sensitive algorithms, a history free algorithm does not need internal variables and clock
control (see Example 2.1, and Example 2.2). From the previous discussion results that there are
two kinds of digital systems, one can be associated with the nite input algorithms, and another
which must be associated with innite input sequential algorithms. They are:
x
assign f comb = ... ;
6
x1
x2
fcomb (x)
always @(x) begin ...
...
end
time
f(x)
fcomb (x)
tf f (x1 )
f (x2 )
time
Figure 2.2: Combinational circuit. The output is continuously re-assigned, with a delay of tf , to
the value of the function f according to the current value of x.
clock
?
clock
fseq (x)
6
-
time
x
tsu

-
time
g(x, time)
g(x,time)
always @(posedge clock) ... ;
tg-
time
Figure 2.3: Sequential circuit. The output is actualized always at (@) positive edge of clock.
The input must be stable tsu before the active edge of clock. The output is actualized with a delay of ts
after the active edge of clock.
history free systems, implemented using combinational circuits: circuits whose outputs
depend continuously by the evolution of the inputs, because they results as a combination
determined only by the actual value of the inputs (see Figure 2.2)
30

history sensitive systems implemented using sequential circuits: circuits having an internal state which, in order to compute each output, memorizes what is necessary, and
how it is necessary, from its own history: the previously received sub-streams of data
(see Figure 2.3).
For eciency reasons, sometimes combinational circuits are transformed in equivalent sequential circuits. Results much smaller systems, and sometimes the speed is not dramatically
reduced, remaining in the same magnitude order.
2.3
History free systems & combinational circuits
Figure 1.2 tells us about the three formal representation of a computation. One for helping our
mind with a half-rigorous primary description of a computation. The other two are used to make
rigorous descriptions for the use of dierent kind of machines (compilers, simulators, synthesizers). Lets take a simple computation: the absolute dierence of two integers, abs dif(a,b).
The algorithm will be presented rst in pseudo-code. Follows a rigorous expression in C language
and another rigorous description of the associated hardware (circuit) in Verilog HDL.
Example 2.5 The algorithm for computing the absolute dierence of two integers,
abs dif(a,b), is expressed, in the previously dened pseudo-code language, as follows:
procedure abs_dif(a,b)
v1 = a;
v2 = b;
v0 = v1 - v2;
if (v0 < 0)
v0 = 0 - v0;
endif
print(v0);
end
//
//
//
//
//
//
//
//
name: abs_dif, variables: a and b

input the first value
input the second value
compute the difference
test if v0 is negative
change sign if negative
no action if sign is positive
print the result
Example 2.6 The C program for computing the absolute dierence of two integers is:
int myAbsDiff(int n1, int n2) {
int D;
D = n1 - n2;
if (D >= 0) return D;
else return -D;
}
The circuit performing the absolute dierence can be described in a variety of ways, delimited
at one end by a pure behavioral description (telling us what does the circuit) and at the other
end by a pure structural description (telling us how looks the actual circuit). Both kinds of
describing circuits can be mingled with dierent weight in order to obtain the desired degree of
structural or behavioral description. All are of interest depending by the context.
Example 2.7 The circuit for computing the absolute dierence of two integers, abs dif(a,b),
has two 32-bit inputs and one 32-bit output (see Figure 2.4). In 4 time units (#4) it provides
on its output the absolute dierence of the two numbers applied on its inputs.
The behavior of this circuit is described in Verilog, as follows:
2.3. HISTORY FREE SYSTEMS & COMBINATIONAL CIRCUITS
32
32
in1
31
in2
abs dif
out
32
Figure 2.4: The circuit for computing the absolute dierence. In 4 time units, say 4ns, the
output of this circuit takes the value of the absolute dierence of two 32-bit signed integers.
module abs_dif(output [31:0] out,
input
[31:0] in1,
input
[31:0] in2);
assign #4 out = (in1 < in2) ? in2 - in1 : in1 - in2;
endmodule
Example 2.8 The Arithmetic & Logic Unit (ALU) is a multi-functional module designed
to perform usually 1-ary and binary functions. It has three kinds of connections:
data connections:
two 32-bit data inputs receiving the two operands: left and right
one 32-bit data outputs out generating the result of the current computed function
extension connections used to support extended arithmetic operations:
carryOut it is the 33-th bit of the current result if an arithmetic operation is
performed
carryIn it can be used to add/subtract the carryOut signal provided by a previous
arithmetic operation
command connections func selects the function performed by the circuit.
The Verilog description of a simple ALU follows:
module ALU(input
carryIn
,
input
[2:0]
func
,
input
[31:0] left, right ,
output reg
carryOut
,
output reg [31:0] out
);
always @(left or right or func or carryIn)
case (func)
3b000: {carryOut, out} = left + right + carryIn;
3b001: {carryOut, out} = left - right - carryIn;
3b010: {carryOut, out} = {1b0, left & right};
3b011: {carryOut, out} = {1b0, left | right};
3b100: {carryOut, out} = {1b0, left ^ right};
3b101: {carryOut, out} = {1b0, ~left};
3b110: {carryOut, out} = {1b0, left};
3b111: {carryOut, out} = {1b0, left >> 1};
endcase
endmodule
//add
//sub
//and
//or
//xor
//not
//left
//shr
32
func
left
right
Arithmetic & Logic Unit
carryOut
carryIn
?
out
Figure 2.5: The block schematic of an arithmetic and logic unit. ALU has inputs for
data (left, right, carryIn), for the operation to be performed (func) and for bits to characterize the
current result (here only carryOut).
These previous two descriptions are a pure behavioral, because they describe only how behave
the output according to the values applied on inputs. For example, in the circuit abs dif, with
a delay of 4 time units (lets say 4 nano-seconds) from the last change on inputs, the output is
assigned to the value of in2 - in1 if in1 < in2, else the output is assigned to the value of
in1 - in2. It is a functional description saying nothing about how looks inside the described
circuit. It says only about when (#4) and about what (assign ...) the circuit does perform.
VerilogSummary 5 :
An output can be also an internal register declared as reg in the connection list (see the
example of the accumulator circuit)
the behavior can be expressed, in our examples, in two ways:
assigning (assign) for the output a function depending by the input variables
using an always construct
the always construct is activated only when at least one component from its sensitivity
list changes (in our last example it is about left, right, func, or carryIn)
the always construct changes the value of some variables (carryOut and out in our last
example) stored in the associated registers, but these registers are used only by the simulator, they are not actual registers in the simulated circuit
The similarities between the three previous descriptions, in pseudo-code, in C++, in Verilog,
are obvious: an operation, a decision according to a condition, and a nal operation.
What is specic for Verilog is the possibility to make also structural descriptions. Instead
of describing only the desired behavior, Verilog language is able to describe also the physical
2.3. HISTORY FREE SYSTEMS & COMBINATIONAL CIRCUITS
33
structure having the desired behavior. While any behavioral description has few circuit implementation, a structural description has only one circuit implementation. Thus, a structural
description is more imperative.
Circuit simulation ts better with behavioral descriptions, while circuit synthesis (implementation) asks, mainly for high accuracy, structural descriptions. Follows two examples dealing
with two distinct structural implementation of the circuit abs dif whose behavior was previously
described.
Example 2.9 The circuit for computing the absolute dierence of two integers, abs dif(a,b),
has the structure described by module abs dif() in Verilog. The module instantiated inside
module abs dif() are dened in this stage using behavioral descriptions in Verilog.
in1
in2
in1
in2
sub
out
dif[31:0]
dif[31]
in
comp2
out
compl
dif[31:0]
?
- sel
in0
?
mux2 32
out
in1
?
out
Figure 2.6: The circuit for absolute dierence. Two signed integers, in1 and in2 are applied
to the input of a subtract circuit. The most signicant bit (the sign bit) of the dierence is used to select
as output the result of subtraction (if the sign bit is 0) or its 2s complement (if the sign bit is 1).
module abs_dif(output [31:0] out,

input
[31:0] in1,
input
[31:0] in2);
wire
[31:0]
dif
,
compl
;
sub
sub1(
.out
(dif),
.in1
(in1),
.in2
(in2)); // computes difference between inputs
compl2 compl2( .out
(compl),
.in
(dif)); // complements the difference
mux2_32 sel(.out
(out),
.in0
(dif),
.in1
(compl),
34

.sel
(dif[31])); // selects the result according to sign
endmodule
module sub(output
input
input
assign #3 out
endmodule
[31:0]
[31:0]
[31:0]
= in1 -
out,
in1,
in2);
in2;
module compl2( output [31:0]

input
[31:0]
assign #2 out = ~in + 1;
endmodule
module mux2_32(
assign
endmodule
#1
output
input
input
input
out = sel ?
// 32-bit subtractor
out ,
in );
// 32-bit 2s complementer
[31:0]
[31:0]
[31:0]
out,
in0,
in1,
sel);
in1 : in0;
// 32-bit multiplexor
Now, at the rst level of the description an actual structure is presented (see Figure 2.6).
Indeed, the circuit abs dif looks as being built using three circuits:
sub instantiated as sub1 which outputs, according to the description provided in module
sub(out, in1, in2), the dierence between the two signed number applied on its inputs,
compl2 instantiated as compl2 which outputs, according to the description provided in
module compl2(out, in), the 2s complement of the signed number applied on its input
mux2 32 instantiated as sel which outputs, according to the description provided in module
mux2 32(out, in0, in1, sel), the value applied on the input in1 if sel = 1 or the value
applied on the input in0 if sel = 0
and two internal connections as 32-bit wires:
dif used to connect the output of the module sub to the input of the module compl2 and
to the input in1 of the module mux2 32
compl used to connect the output of the module compl2 to the other input of the multiplexer
mux2 32.
For the sake of simplicity and because our knowledge about real circuits are yet week the three
internal module are presented using a behavioral description only.
Example 2.10 A faster version for the circuit abs dif(a,b) can be redesigned using a little
bigger circuit. It is a speculative version because the circuit compute all the possible versions
(in our case both in1 - in2 and in2 - in1) and selects one of them ignoring the other(s).
Figure 2.7 shows our solution.
The Verilog code describing the proposed structure is:
module fast_abs_dif(output[31:0] out, input[31:0] in1, input[31:0] in2);
wire
[31:0]
dif, rev_dif ;
sub
sub1(.out(dif), .in1(in1), .in2(in2)),

sub2(.out(rev_dif), .in1(in2), .in2(in1));
mux2_32 sel(.out(out), .in0(dif), .in1(rev_dif), .sel(dif[31]));
endmodule
2.4. HISTORY SENSITIVE SYSTEMS & SEQUENTIAL CIRCUITS
in1
35
in2
in1
in2
in1
sub
out
in2
sub
out
dif[31:0]
rev dif[31:0]
?
dif[31]
- sel
in0
?
mux2 32
out
in1
?
out
Figure 2.7: The speculative circuit version for absolute dierence. Both dierences, in1
- in2 and in2 - in1, are computed, but only one selected as result using dif[31], the sign of the rst
dierence.
For sub and mux2 32 the behavioral description from the previous example are used.
The propagation time for the rst version of the absolute dierence circuit, abs dif, is
#6, because the longest path from input to output goes through all the three circuits when the
dierence is negative. Indeed, if dif in negative (dif[31] = 1) the result is selected from the
output of the comparator.
The propagation time for the fast version is only #4. The propagation involves always a sub
circuit and the output selector.
The price for the speed-up is payed by the fact that a sub circuit is bigger then a comp2
circuit.
Learning more about digital systems in the following chapters the modules sub, compl2 and
mux2 32 will get also structural descriptions.
2.4
History sensitive systems & sequential circuits
The specic structure in history sensitive systems is the device used to memorize the history:
the storing register, or simply the register. The state of a register, i.e., its content, changes
only synchronously with the active (positive or negative) edge of the clock signal. There are
specic Verilog features to deal with the specic aspects of the register behaviors related with
its synchronicity.
Actually, the register is the simplest sequential circuit. It is a sequential circuit which
does perform sequentially the identity function (f (x) = x). In real applications a register has
some specic features, such as enable (execute the identity function) and reset (execute the
function f (x) = 0). Follows the Verilog code describing a resetable and enabled register.
module register #(parameter n = 8)( output
input
input
input
reg [n-1:0] out

[n-1:0] in
reset
enable
,
,
,
,
36
clock
my in
clk
my reg
in
enable
register
reset
out
1
rst
time
in
my out
6
a
time
register my reg( .out

.in
.enable
.reset
.clock
(my out ),
(my in ),
(1b1 ),
(rst
),
(clk
));
out
6
a
time
Figure 2.8: Register. At each active edge of clock (in this example it is the positive edge) the registers
output takes the value applied on its inputs if reset = 0 and enable = 1.
input
always
@(posedge clock) #2 if(reset)

else if(enable)
else
clock
out = 0
out = in
out = out
);
;
;
;
endmodule
The moment of the transition of the active edge of the clock signal is in fact a time interval.
In Figure 2.9 the moment of transition is magnied to emphasize some signicant details.
the transition from 0 to 1 of the clock, the edge time, is done in the time interval t+ ,
measured between the moment when clock reaches 0.1 from its nal value and the moment
when clock reaches 0.9 from its nal value
the set-up time, tsu , the time before the active clock transition when data input must
be stable for an accurate load
the hold time, th , the time after the clock transition when the data must remain stable
for an accurate load.
Thus the moment of transition is in fact the time interval: tsu + t+ + th .
The register is used at least for the following purposes: to store, to buer, to synchronize,
to delay, to loop, . . ..
Storing The enable input allows us to determine when (i.e., in what clock cycle) the input is
loaded into a register. If enable = 0, the registers stores the data loaded in the last clock cycle
when the condition enable = 1 was fullled. This means we can keep the content once stored
into the register as much time as it is needed for the application purposes.
37
100%
90%
clock
10%
time
in
- -tsu
t+
time
th
Figure 2.9: Magnifying the transition of the active edge of the clock signal. The input
data must be sable around the active transition of the clock tsu (set-up time) before the beginning of the
clock transition, during the transition of the clock, t+ (active transition time), and th (hold time) after
the end of the active edge.
Buering The registers can be used to buer (to isolate, to separate) two distinct blocks so
as some behaviors are not transmitted through the register. For example, in Figure 2.8 the
transitions from c to d and from d to e at the input of the register are not transmitted to the
output.
Synchronizing For various reasons the digital signals are generated unaligned in time to
the inputs of a system, but they are needed to be received very well controlled in time. We
say usually, the signals are applied asynchronously but they must be received synchronously.
For example, in Figure 2.8 the input of the register changes somehow chaotically related to the
active edge of the clock, but the output of the register switches with a constant delay after the
positive edge of clock. We say the inputs are synchronized to the output of the register. Their
behavior is time tempered.
Delaying The input value applied in the clock cycle n to the input of a register is generated
to the output of the register in the clock cycle n+1. In other words, the input of a register is
delayed one clock cycle to its output. See in Figure 2.8 how the occurrence of a value in one
clock cycle to the registers input is followed in the next clock cycle by the occurrence of the
same value to the registers output.
Looping Structuring a digital system means to make dierent kind of connections. One of
the most special, as we see in what follows, is a connection from some outputs to certain inputs
in a digital subsystem. This kind of connections are called loops. The register is an important
structural element in closing controllable loops inside a complex system.
We will present some typical applications of the register using simple examples.
Example 2.11 Let be the following circuit: its output is identical with its internal state, its state
can take the value received on its data input, its internal state can be modied incrementing the
38
number which represents its state or can stay unchanged. Let us call this circuit: presetable
counter. Its Verilog description, for an 8-bit state, is:
module counter(
output reg [7:0]

input
[7:0]
input
input
input
always @(posedge clock)
if (init)
out = in;
else if (count) out = out +
endmodule
out
,
in
,
init
, // initialize with in
count
, // increment state
clock
);
// always at the positive edge of clock
1;
The init input has priority to the input count, if it is active (init = 1) the value of count
is ignored and the value of state is initialized to in. If init in not activated, then if count = 1
then the value of counter is incremented modulo 256. Note: a circuit is an actual nite entity.
For this reason its dimension and its function must specied accordingly.
in
in
inc
out
inc en
1
?
init
in1
sel
count
inc out ?
in
in0
mux2 8
out
our inc
*
reg in
sel
clock
clock
in
register8
out
reset
enable
i
our reg
counter
?
out
Figure 2.10: The internal structure of a counter. If init = 0 each active edge of clock loads in
register its incremented value, else, if init = 1 the value of the register is initialized to in.
Example 2.12 Lets generate the Verilog structural description for the presetable counter behaviorally described in the previous example.
module counter(
wire
[7:0]
output [7:0]
input
[7:0]
input
input
input
inc_out,
out,
in,
init,
count,
clock);
39
clock
6
6
time
init
6
time
count
6
time
t
- reg
out[0]
t
- reg
6
time
t
- reg
out[1]
t
- reg
6
time
tinc
-
inc out[0]
6
time
tinc
-
inc out[1]
6
time
tmux
reg in[0]
-tmux

time
-tmux

reg in[1]
6
time
Figure 2.11: The wave forms explaining how the counter works. It is supposed in[1:0] =
2b01. If init is active (init = 1), then the value of count does not matter and the counter is initialized
to in[1:0] = 2b01 at the positive edge of clock with treg delay. In the next three clock cycles the value
of counter is incremented modulo 4.
40
inc
mux2_8
register8
reg_in;
our_inc(
.out
(inc_out),
.in
(out),
.inc_en (count));
sel( .out
(reg_in),
.in0
(inc_out),
.in1
(in),
.sel
(init));
our_reg(
.out
(out),
.in
(reg_in),
.enable (1b1),
.reset (1b0),
.clock (clock));
endmodule
module inc(
assign
endmodule
output [7:0]
out,
input
[7:0]
in,
input
inc_en);
#1 out = in + inc_en;
module mux2_8(
output [7:0]
out,
input
[7:0]
in0,
input
[7:0]
in1,
input
sel);
assign #1 out = sel ? in1 : in0;
endmodule
module
register8(
output reg [7:0]

out,
input
[7:0]
in,
input
enable,
input
reset,
input
clock);
always @(posedge clock) if (reset)
out = #2 0;
else if (enable)
out = #2 in;
endmodule
Figure 2.10 represents the resulting counter. Figure 2.11 represents the wave forms showing
the behavior of two bits of the counter. The wave forms are drown taking into account the delays
introduced by each components of the design. The vertical dashed lines are used to mark the
time: between two dashed lines one time unit ows. The input has a constant value: in[1:0] =
2b01. Only a short comment about the 1-time unit spike on the wave inc out[0]: it occurs
because the behavior of the module inc. The spike does not aect the external behavior of the
system because its eect, to the output of multiplexer, ends before the next positive edge of clock.
Example 2.13 The simplest way to use an ALU is to connect it in a loop with an accumulator
register (see Figure 2.12). In each clock cycle the left operand is received on the input in, and
the right operand is the content of the accumulator register acc reg. The structural description
of the top level of this system follows:
module alu_acc( output
input
input
input
output
reg [31:0]
[31:0]
[2:0]
acc_reg
in
func
cin
cout
,
,
,
,
,
41
in
?
-
func
right
left
func
ALU
carryIn
carryOut
cout
out
cin
?
acc reg
clock
acc reg
Figure 2.12: ALU with Accumulator. The ALUs output is accumulated in a clocked register
and used as right operand.
input
wire
[31:0] out;
ALU alu(.out
(out)
.carryOut
(cout)
.carryIn
(cin)
.left
(in)
.right
(acc_reg)
.func
(func)
always @(posedge clock) acc_reg
endmodule
clock
);
,
,
,
,
,
);
= out;
The module ALU is dened in Example 1.7.

An example of how to use this simple system is described by the following sequence of command applied to its inputs:
{func, in, cin} = {3b000, 31b101, 1bx}
{func, in, cin} = {3b010, 31b010, 1b0}
{func, in, cin} = {3b011, 31b011, 1b1}
// acc_reg = 31b101
// acc_reg = acc_reg + 31b10 + 0
// acc_reg = acc_reg - 31b11 - 1
The nal value to the output of the system is acc reg = 31b011.
Example 2.14 Sometimes we need to make evident the moment when a binary signal switches
from 0 to 1, or from 1 to 0, or both, from 0 to 1 and from 1 to 0. The circuit which solves this
problem is a sort of derivative circuit used to discern the transitory moments. The schematic of
the circuit is presented in Figure 2.13. The idea of the circuit is to delay the input wave, in,
with one clock cycle using a one-bit register. The delayed input, dIn, is combined with the input
wave, in, using few gates.
Let us use the wave forms from Figure 2.14 in order to understand how the circuit works.
We assume that the input in is synchronized to the input of our circuit by the same clock. The
beginning of an input pulse is characterized in the rst clock cycle by the fact that in = 1 and
dIn = 0. Only in the rst clock cycle after the occurrence of an input pulse in & !dIn = 1.
Similarly, in the rst clock cycle after the end of an input pulse the following logical condition
42
in
first
-D
both
REG
last
clock
dIn
Figure 2.13: The derivative circuit.

is fullled: !in & dIn = 1. If both, the occurrence and the end of a pulse must be marked, the
previous two conditions must be ORed: in & !dIn | !in & dIn = 1
clock
time
in
time
in
time
dIn
time
dIn
time
first
time
last
time
both
time
Figure 2.14: Wave forms for the derivative circuit.

The Verilog module for derivative circuit is:
module derivative( output
output
output
input
input
reg dIn ;
first
last
both
in
clock
,
,
,
,
);
always @(posedge clock) dIn = in;

and firstAnd(first, in, ~dIn)
lastAnd(last, ~in, dIn)
or bothOr(both, first, last)
endmodule
,
;
;
The circuit is simulated using the following test module which generate the input wave in,
and the clock signal (see Figure 2.14).
module testDerivative;
reg
in
;
2.5. TIME RESTRICTIONS IN DIGITAL SYSTEMS

reg
wire
wire
wire
clock
first
last
both
initial begin
43
;
;
;
;
clock = 1
forever #10 clock = ~clock
end
initial begin
#41
#120
#60
#60
#60
in = 0
in = 1
in = 0
in = 1
in = 0
$stop
;
;
;
;
;
;
;
;
end
derivative dut( first
last
both
in
clock
endmodule
,
,
,
,
);
VerilogSummary 6 :
A structural description is more complex than a functional one (indeed, is easies to describe
what must be done than how it can be done); but, if the circuit is complex, then it
is synthesized with more accuracy starting from a structural description than from a
functional description
a history sensitive circuit contains a loop and this is expressed:
using expressions in which the left part occurs in the right part, as in the the behavioral descriptions (see out = out + 1 the behavioral description for counter)
using a connection which takes the output (or a part of it) and connects it to the
input of sub-circuits used to compute the output, as in the structural descriptions
(see out back connected to the input of inc circuit in the structural description of
counter).
Key words, like not, and, or are used to specify simple typical logic circuits
The clock input has no a functional role, it is used only to emulate the ow of time.
The smallest dimension of a behavioral description ts with the common use of such a description for simulation. Indeed, big circuits can be faster simulated using behavioral description
than structural descriptions.
2.5
Time restrictions in digital systems
The most general form of a digital circuit (see Figure 2.15) includes both combinational and
sequential behaviors. It includes two combinational circuits (comb circ 1 and comb circ 2)
and register. There are four critical propagation paths in this digital circuit:
44
input
comb circ 1
tin
reg
treg
reg
clock
?
register
?
treg
out
comb circ 2
tin
out
?output
Figure 2.15: The four critical propagation paths in digital circuits. Input-to-register time
(tin reg ) is recommended to be as small as possible in order to reduce the time dependency from the
previous sub-system. Register-to-register time (Tmin ) must be minimal to allow a high frequency for the
clock signal. Input-to-output time (tin out ) is good to be undened to avoid hard to manage sub-systems
interdependencies. Register-to-output time (treg out ) must be minimal to reduce the time dependency for
the next sub-system
1. form input to register through comb circ 1, which determines minimum input arrival
time before clock: tin reg
2. from register to register through comb circ 1, which determines minimum period of
clock: treg reg = Tmin , or maximum frequency of clock: fmax = 1/T
3. from input to output through comb circ 2, which determines maximum combinational
path delay: tin out
4. from register to output through comb circ 2, which determines maximum output required time after clock: treg out .
If the active transition of clock takes place at t0 and the input signal changes after t0 tin reg ,
then the eect of the input change will be not registered correctly at t0 in register. The input
must be stable in the time interval from t0 tin reg to t0 in order to have a predictable behavior
of the circuit.
The loop is properly closed only if Tmin > treg + tcc2 + tsu and th < treg + tcc2 , where: treg
is the propagation time through register from active edge of clock to output, and tcc2 is the
propagation time through comb circ 1 on the path 2.
45
If the system works with the same clock, then tin out < Tmin , preferably tin out << Tmin .
Similar conditions are imposed for tin reg and treg out , because we suppose there are additional
combinational delays in the circuits connected to the inputs and to the outputs of this circuit,
or at least a propagation time through a register or set-up time to the input of a register.
Example 2.15 Let us compute the propagation times for the four critical propagation paths of
the counter circuit represented in Figure 2.10. If we consider #1 = 100ps results:
tin reg = tp (mux2 8) = 0.1ns
(the set-up time for the register is considered too small to be considered)
fmax = 1/T = 1/(tp (reg) + tp (inc) + tp (mux2 8)) = 1/(0.2 + 0.1 + 0.1)ns = 2.5 GHz
tin
treg
out
out
is not dened
= tp (reg) = 0.2ns
Example 2.16 Let be the circuit from Figure 2.16, where:

register is characterized by: tp (register) = 150ps, tsu (register) = 35ps, th = 27ps
adder with tp (adder) = 550ps
selector with tp (selector) = 85ps
comparator with tp (comparator) = 300ps
The circuit is used to accumulate a stream of numbers applied on the input data, and to compare
it against a threshold applied on the input thr. The accumulation process is initialized by the
signal reset, and is controlled by the signal acc.
thr
data
?
b
adder
550ps a+b
selector
85ps out
35ps
in
register
sel
rst
acc
reset
clock
150ps out
a
b
comparator
300ps a<b
?
over
?sum
Figure 2.16: Accumulate & compare circuit. In the left-down corner of each rectangle
is written the propagation time of each module. If acc = 1 the circuit accumulates, else the
content of register does not change.
The propagation time for the four critical propagation path of this circuit are:
46

tin
reg
= tp (adder) + tp (selector) + tsu (register) = (550 + 85 + 35)ps = 670ps
fmax = 1/T = 1/(tp (register) + tp (adder) + tp (selector) + tsu (register)) =

1/(150 + 550 + 85 + 35)ps = 1.21GHz
tin
out
treg
= tp (comparator) = 300ps
out
= tp (register) + tp (comparator) = 450ps
While at the level of small and simple circuits no additional restriction are imposed, for
complex digital systems there are mandatory rules to be followed for an accurate design. Two
main restrictions occur:
1. the combinational path through the entire system must be completely avoided,
2. the combinational, usually called asynchronous, input and output path must be avoided
as much as possible if not completely omitted.
Combinational paths belonging to distinct modules are thus avoided. The main advantage
is given by the fact that design restrictions imposed in one module do not aect time restriction
imposed in another module. There are two ways to consider these restrictions, a weak one and a
strong one. The rst refers to the pipeline connections, while the second to the fully buered
connections.
2.5.1
Pipelined connections
For the pipelined connection between two complex modules the timing restrictions are the following:
1. from input to output through: it is not dened
2. from register to output through: treg out = treg it does not depend by the internal
combinational structure of the module, i.e., the outputs are synchronous, because they
are generated directly from registers.
in2
out2
comb1
in1
pr1
out1
sr1
in1
pr2
out1
sr2
nextState
sys1
in2
out2
comb2

nextState
sys2
clock
Figure 2.17: Pipelined connections.
47
Only two combinational paths are accepted: (1) from register to register, and (2) form input
to register. In Figure 2.17 a generic conguration is presented. It is about two systems, sys1 and
sys2, pipeline connected using the output pipeline registers (pr1 between sys1 and sys2, and
pr2 between sys2 and an external system). For the internal state are used the state registers
sr1 and sr2. The timing restrictions for the two combinational circuits comb1 and comb2 are not
correlated. The maximum clock speed for each system does not depend by the design restrictions
imposed for the other system.
The pipeline connection works well only if the two systems are interconnected
with short wires, i.e., the two systems are implemented on adjacent areas on the silicon die.
No additional time must be considered on connections because they a very short.
The system from Figure 2.17 is descried by the following code.
module pipelineConnection( output [15:0]
input
[15:0]
input
wire
[15:0] pipeConnect ;
sys sys1(
.pr
(pipeConnect),
.in
(in
),
.clock (clock
)),
sys2(
.pr
(out
),
.in
(pipeConnect),
.clock (clock
));
endmodule
module sys(output reg [15:0] pr
input
[15:0] in
input
clock
reg
[7:0]
sr
;
wire
[7:0]
nextState
;
wire
[15:0] out
;
comb myComb(.out1
(nextState ),
.out2
(out
),
.in1
(sr
),
.in2
(in
));
always @ (posedge clock)
begin
out
in
clock
,
,
);
,
,
);
pr <= out
;
sr <= nextState ;
end
endmodule
module comb(
output
output
input
input
[7:0]
[15:0]
[7:0]
[15:0]
out1,
out2,
in1 ,
in2 );
// ...
endmodule
Something very important is introduced by the last Verilog code: the distinction between
blocking and non-blocking assignment:
the blocking assignment, = : the whole statement is done before control passes to the
next
the non-blocking assignment, <= : evaluate all the right-hand sides in the project for
the current time unit and assign the left-hand sides only at the end of the time unit.
Let us use the following simulation to explain the very important dierence between the two
kinds of assignment.
48
VeriSim 2.1 The following simulation used 6 clocked registers. All of them switch on the
positive edge. But, the code is written for three of them using the blocking assignment, while
for the other three using the non-blocking assignment. The resulting behavior show us the
dierence between the two clock triggered assignment. The blocking assignment seems to be
useless, because propagates the input through all the three registers in one clock cycle. The nonblocking assignment shifts the input along the three serially connected registers clock by clock.
This second behavior can be used in real application to obtain clock controlled delays.
module blockingNonBlocking(output
output
input
input
reg [1:0]
reg [1:0]
reg [1:0]
[1:0]
blockingOut
nonBlockingOut
in
clock
,
,
,
);
reg1
reg2
blockingOut
= in
= reg1
= reg2
;
;
;
end
reg3
reg4
nonBlockingOut
<= in
;
<= reg3 ;
<= reg4 ;
end
reg1, reg2, reg3, reg4;
always @(posedge clock) begin
endmodule
module blockingNonBlockingSimulation;
reg
clock
;
reg
[1:0]
in
;
wire
[1:0]
blockingOut, nonBlockingOut ;
initial begin
clock = 0
;
forever #1 clock = ~clock ;
end
initial begin
in = 2b01 ;
#2 in = 2b10 ;
#2 in = 2b11 ;
#2 in = 2b00 ;
#7 $stop
;
end
blockingNonBlocking dut(blockingOut
,
nonBlockingOut ,
in
,
clock
);
initial
$monitor
("clock=%b in=%b reg1=%b reg2=%b blockingOut=%b reg3=%b reg4=%b nonBlockingOut=%b",
clock, in, dut.reg1, dut.reg2, blockingOut, dut.reg3, dut.reg4, nonBlockingOut);
endmodule
/*
clock=0 in=01 reg1=xx reg2=xx blockingOut=xx
reg3=xx reg4=xx nonBlockingOut=xx
clock=1 in=01 reg1=01 reg2=01 blockingOut=01
reg3=01 reg4=xx nonBlockingOut=xx
reg3=01 reg4=xx nonBlockingOut=xx
reg3=10 reg4=01 nonBlockingOut=xx
reg3=10 reg4=01 nonBlockingOut=xx
reg3=11 reg4=10 nonBlockingOut=01

clock=1 in=00
clock=0 in=00
*/
reg1=00 reg2=00 blockingOut=00

reg1=00 reg2=00 blockingOut=00
49

It is obvious that the registers reg1 and reg2 are useless because they are somehow transparent.
The non-blocking version of assigning the content of a register will provide a clock controlled
delay. Anytime in a design there are more than one registers the non-blocking assignment must
be used.
VerilogSummary 7 :
= : blocking assignment the whole statement is done before control passes to the next
<= : non-blocking assignment evaluate all the right-hand sides in the project for the current time unit and assign the left-hand sides only at the end of the time unit.
2.5.2
Fully buered connections
The most safe approach, the synchronous one, supposes fully registered inputs and outputs
(see Figure 2.18 where the functionality is implemented using combinatorial circuits and registers
and the interface with the rest of the system is implemented using only input register and
output register).
The modular synchronous design of a big and complex system is the best approach for a
robust design, and the maximum modularity is achieved removing all possible time dependency
between the modules. Then, take care about the module partitioning in a complex system
design!
Two fully buered modules can be placed on the silicon die with less restrictions, because even
if the resulting wires are long the signals have time to propagate because no gates are connected
between the output register of the sender system and the input register of the receiver system..
For the synchronously interfaced module represented in Figure 2.18 the timing restrictions
are the following:
1. form input to register: tin
module
reg
= tsu it does not depend by the internal structure of the
2. from register to register: Tmin , and fmax = 1/T it is a system parameter

3. from input to output through: it is not dened
4. from register to output through: treg
structure of the module.
out
= treg it does not depend by the internal
Results a very well encapsuled module easy to be integrate in a complex system. The price
of this approach consists in an increasing number of circuits (the interface registers) and some
restrictions in timing imposed by the additional pipeline stages introduced by the interface
registers. These costs can be reduced by a good system level module partitioning.
50
clock
input
?
input register
comb circuits & registers
?
output register
?output
Figure 2.18: The general structure of a module in a complex digital system. If any big
module in a complex design is buered with input and output registers, then we are in the ideal situation
when: tin reg and treg out are minimized and tin out is not dened.
2.6
Concluding about Verilog & digital systems
The main concepts and facts introduced in this chapter are:

to describe, to simulate and to design digital systems the most useful tool is a hardware
description language, and we selected the Verilog HDL because of its simplicity and its
familiar syntax
there are two classes of digital systems:
history free systems whose outputs follow continuously any input changing, called
combinational systems
history sensitive systems called sequential systems whose outputs depends by
the current inputs and by the previously applied inputs whose eect is stored inside
the system as what we call the internal state of the system, or simply state
a combinational circuit is a physical device performing a function in a nite time, called
propagation time, tcircuit
the internal state of a sequential system evolves in discrete time2 controlled by a special
signal called clock, which is a periodic signal having assigned an active edge (the positive
edge or the negative edge)
a sequential system changes its output synchronized by the active edge of clock with a
delay tcircuit
2
The usual embodiment of history sensitive systems are synchronous. The asynchronous version without
clock synchronization is possible, but our approach is limited to the synchronous systems.
2.7. PROBLEMS
51
the specic circuit in sequential systems is the register, a storing device changing its state
synchronously with the active edge of clock if its input evolves respecting the following
conditions:
the set-up time condition: tsu > tsu
before the active edge of clock
min
the hold time condition: th > th

after the active edge of clock
- the input remains unchanged enough time
min
- the input value is stable enough time
the timing associated with a digital system is characterized by: tin

the modular approach in digital design asks for: tin
undef ined
reg
reg ,
= tsu , treg
Tmin , tin
out
out , treg out
= treg , tin
out
there are two extreme ways to encode a circuit using the Verilog language:
generating a behavioral pure functional description, used mainly in description,
simulation and testing
generating a structural description imposed by the necessity of an accurate formal
synthesis followed by the physical implementation
the second must be a synthesisable code, while the rst sometimes is not synthesisable by
the existing tools
the introductory features of the Verilog HDL are:
each system or sub-system is described by a module, having a name and a list of
input or output connections, which starts with module and end with endmodule
the continuous assignment, assign, is used to specify combinational functions; optionally the propagation time is associated (example: #3)
the pure structural elements are the wires, wire[dim-1:0], and instantiated modules
using the local names:
mux2 my mux(.out (our in), ...);
the state variables have associated registers, reg[dim-1:0], synchronized by posedge
or negedge of the clock signal
usually a behavioral description is shorter (simpler) than a corresponding structural one
specifying a digital system means usually: (1) to express the desired functionality in
pseudo-code language, (2) to write a behavioral description is a HDL (for example, Verilog), (3) to write a structural description in the same HDL (both Verilog descriptions are
necessary in the process of designing the circuit)
the functional description oers an image about the complexity of the system, while the
corresponding structural description says something about the size of the system.
2.7
Problems
Algorithms & Pseudo-code language

Problem 2.1 In Example 1.3 the unary represented numbers are supposed to be separated by
one 0 only. Modify the algorithm to allow between the unary represented numbers any number
of 0s.
52
Problem 2.2 Design an algorithm to convert positive fractionary numbers into binary representation.
Problem 2.3 Describe in the pseudo-code language the algorithm for counting the number of
1s in a binary string, while the 1-bit enable signal is active (en = 1).
Problem 2.4 Describe in the pseudo-code language the algorithm for adding bit by bit two n-bit
numbers for any n. The result is delivered also bit by bit. Using it write a Verilog description
for the associated machine. The module will have the following header:
module serial_addition(output
input
input
input
input
input
...
endmodule
out
in1
in2
init
enable
clock
, //
, //
, //
, //
, //
);
result
first operand
second operand
reset the system
enable operation
Innite input algorithms

Problem 2.5 Redesign the electronic key adding the programmability feature.
Problem 2.6 Design the algorithm and describe the associated circuit for a system which compare two n-bit numbers received serially, bit by bit, for any n. The result is delivered on two
outputs: eq, active if the two numbers are equal, and lt, active if rst operand is less than the
second operand. Version 1: the numbers are received with the most signicant bit rst. Version
2: the numbers are received with the the least signicant bit rst. The resulting system has an
init input and an enable input.
Problem 2.7 Design the algorithm and describe the associated circuit for a system which detects
into a serially received stream of bits a sub-stream of identical bits longer than n. Version 1:
the machine stops outputing the value 1. Version 2: the machine switch its output on 1, during
one clock cycle at the end of each detected sequence.
Describing history free combinational circuits

Problem 2.8 Revisit the structural description of the circuit computing the absolute dierence,
abs dif(a,b), having in mind that the following circuit, called enabled complement, exists:
module en_compl(
assign
endmodule
#2
output
input
input
[n-1:0] out,
[n-1:0] in,
enable
);
out = enable ? (~in - 1) : in;
The enabled complement circuit computes, conditioned by the input enable, the 2s complement of the signed integer applied on the input in.
Problem 2.9 Find the execution time for the module abs dif(a,b) described in Example 1.6
and for the same module solved in the previous problem.
Problem 2.10 Design a combinational circuit for comparing two 8-bit numbers. The output
has three bits, eq, gt, lt, indicating equal, greater, less.
2.7. PROBLEMS
53
Problem 2.11 Write the behavioral and the structural description for a combinational circuit
which computes the arithmetic mean value of two 16-bit positive integers. Write a test program
to check if the two description work identical.
Problem 2.12 Specify the time behavior of the counter represented in Figure 2.10.
Problem 2.13 Design in Verilog a two input combinational circuit for computing c = a 2b ,
where: a is a 16-bit number and b is a 4-bit number. The module is dened as follows:
module exp(
output
input
input
[31:0]
[15:0]
[3:0]
c,
a,
b);
...
endmodule
Problem 2.14 Design in Verilog a combinational circuit for computing b = 2a , where: b is a

32-bit number and a is a 5-bit number. The module is dened as follows:
module exp(
output
input
[31:0]
[3:0]
b,
a);
...
endmodule
Describing history sensitive, sequential circuits

Problem 2.15 The serial to parallel converter is a circuit which receives binary streams and
converts it into an 8-bit word stream. Its function is:
procedure serial_to_parallel(validIn
forever
if
(reset)
else if
(validIn & ~reg[7])
else if (validIn & reg[7])
, serialIn, reset);
reg =
reg =
print
print
reg =
1;
2*reg + serialIn;
"newOut:";
({reg[6:0], serialIn});
1;
endif
endif
endif
endforever
end
Successive 8 bits received whenever validIn = 1 are converted in 8-bit words and sent out by
activating the output signal validOut. The process is restarted after each activation of reset.
Design the corresponding Verilog description:
module serial_to_parallel(output
valid_out
,
output [7:0] parallel_out,
input
valid_in
,
input
serial_in
,
input
reset
,
input
clock
);
...
endmodule
Only in the clock cycle when valid out = 1 the output parallel out can be read by an
external circuit.
54
Problem 2.16 Write a test module for the pipelined inner prod module and run it for testing
the circuit.
Problem 2.17 Design the behavioral model and the structural model for multiply and accumulate circuit, MACC, for n-bit signed integers, and the input sequences no longer than m
numbers. The circuit will compute:
c=
m1
ai bi
i=0
The module has the following connections:

module macc(
output
output
input
input
input
input
input
[n-1:0] out
ovf
[n-1:0] in1
[n-1:0] in2
reset
run
clock);
,
,
,
,
,
,
//
//
//
//
//
//
n-bit output
overflow signal
n-bit input data
n-bit input data
set output to zero
multiply & accumulate
...
endmodule
Problem 2.18 Using modules like adder, left shift, right shift, register design in
Verilog a sequential multiplier for n-bit positive integers which perform the multiplication in
(n + const) clock cycles. Make an appropriate tester for the design.
Hint: look for algorithms on web.
Problem 2.19 The same for n-bit signed integers.
Problem 2.20 Repeat the previous two problems for division.
Hint: An additional loop is compulsory.
Problem 2.21 Use the accumulator circuit designed in Example 1.11 to design a resetable
counter, dened as follows:
module res_count(
out
reset
count
clock
,
,
,
);
// the n-bit output

// reset signal
// enable counting
...
endmodule
Design two versions. One with reset having priority against count, and another with count
having priority against reset. What is the solution do you prefer?
Problem 2.22 Design a serial-parallel register dened as follows:
module sp_reg( output [n-1:0] out,
input
[n-1:0] in,
input
serial_in, /* bit to be loaded in
the least significant position when shift is performed */
input
load,
// load the output with in
input
shift, /* load the output with
out one position left shifted and serial_in as the bit 0 */
input
clock);
...
endmodule
2.7. PROBLEMS
55
Problem 2.23 Design a circuit for computing in O(n) time fib(n) (the n-th element of Fibbonacci sequence) with a circuit having the following external connections:
module fib(
output
output
input
input
input
[n-1:0] out
eoc
[m-1:0] in
start
clock
,
,
,
,
);
//
//
//
//
output for fib(n)

end of computation
input for n
start of computation
...
endmodule
An appropriate relation between n and m must be established.

Problem 2.24 Find a solution for fib(n) which solve the problem in O(log n). Compare the
size of the resulting circuit with the solution of the previous problem.
Hint: see the last point in the last chapter.
Problem 2.25 Let be the circuit described by the following Verilog code:
module circuit(output out
,
input
in
,
input
clock
);
reg
delay;
always @(posedge clock) delay <= in;
assign out = delay ? ~in: in;
endmodule
Note: in means in inverted (if in=0 then in=1; if in=1 then in=0).
Suppose the input of the circuit receives a string of bits. How is modied the received string?
Timing issues
Problem 2.26 Let be two systems, S1 and S2, containing each 3 subsystems connected as in
Figure 2.19a and as in Figure 2.19b. The time behavior of each subsystem is the following:
SS1: tin
reg
= 1ns, fmax = 250M Hz, tin
out
= , treg
SS2: tin
reg
out
= 2ns, treg
out
= 1ns
SS3: tin
reg
= 2.5ns, fmax = 250M Hz, tin
= , treg
out
= 1.5ns
out
out
= 2ns
Determine the time behavior of the two systems S1 and S2.

Problem 2.27 Let be a system containing 4 subsystems connected as in the following Verilog
module.
module system_3(out, in, clock);
input
clock;
input
[n-1:0] in;
output [m-1:0] out;
wire
[p-1:0] out1, out2, out3;
sub_system1
sub_system2
sub_system3
sub_system4
endmodule
ss1(out1, in, clock);

ss2(out2, out1, clock);
ss3(out3, out1, clock);
ss4(out, {out2, out3}, clock);
56
clock input
input
clock
SS1
SS1
SS2
SS2
?
-
SS3
S2
SS3
S1
output1
a.
output
output2
b.
Figure 2.19: Interconnecting digital subsystems. a. System S1. b. System S2.

The time behavior of each subsystem is the following:
ss1: tin
reg
out
= , treg
ss2: tin
reg
out
= 3ns, treg
out
= 3ns
ss3: tin
reg
out
= 5ns, treg
out
= 2ns
ss4: tin
reg
out
= , treg
out
out
= 4ns
= 1ns
Make a plan of reducing propagation times to obtain the better improvement of the frequency at
system level. Is there a propagation time which can be improved without aecting the overall
time performance of the system?
2.8
Projects
Use Appendix How to make a project to learn how to proceed in implementing a project.
Project 2.1 Design a combinational oating point single precision (32 bit) adder according
to the ANSI/IEEE Standard 754-1985, Standard for Binary Floating Point Arithmetic. Only a
block level design is required. Use Verilog to describe structurally at system level and functionally
at the level of the internal functional block level as deep as possible.
Project 2.2 Design a rasterization circuit used to ll-up triangles in graphics machines. Start
the project searching on internet documentation explaining what means rasterization in graphic
domain. Use Verilog to describe structurally at system level and functionally at the level of the
internal functional block level as deep as possible.
Chapter 3
GROWING & SPEEDING &

FEATURING
starting from simple algorithms small combinational and sequential circuits were designed,
using the Verilog HDL as tool to describe and simulate. From the rst chapter is ggod to
remember:
Verilog can be used for both behavioral (what does the circuit?) and structural (how
looks the circuit?) descriptions
the outputs of a combinational circuits follow continuously (with as small as possible
delay) any change of its inputs, while a sequential one takes into account a shorter
or a longer history of the input behavior
the external time dependencies must be minimized if not avoided; each circuit must
have its own and independent time behavior in order to allow global optimizations
In this chapter
the three main mechanisms used to generate a digital system are introduced:
composition: the mechanism allowing a digital circuit to increase its size and its
computational power
pipeline: is the way of interconnecting circuits to avoid the increase of the delays
generated by too many serial compositions
loop: is a kind of connection responsible for adding new type of behaviors, mainly by
increasing the autonomy of the system
In the next chapter
a taxonomy based on the number of loops closed inside a digital system is proposed. Each
digital order, starting from 0, is characterized by the degree of the autonomy its behavior
develops. While digital circuits are combinational or sequential, digital systems will be:
0 order, no-loop circuits (the combinational circuits)
rst order, 1-loop circuits (simple ip-ops, ...)
second order, 2-loop circuits (nite automata, ...)
third order, 3-loop circuits (processors, ...)
...
57
58
CHAPTER 3. GROWING & SPEEDING & FEATURING
... there is no scientic theory about what can

and cant be built.
David Deutsch1
Engineering only uses theories, but it is art.
In this section we talk about simple things which have multiple, sometime spectacular,
followings. What can be more obvious than that a system is composed by many subsystems and
some special behaviors are reached only using appropriate connections.
Starting from the ways of composing big and complex digital systems by appropriately interconnecting simple and small digital circuits, this book introduces a more detailed classication
of digital systems. The new taxonomy classies digital systems in orders, based on the maximum number of included loops closed inside each digital system. We start from the basic idea
that a new loop closed in a digital system adds new functional features in it. By composition,
the system grows only by forwarded connections, but by appropriately closed backward connections it gains new functional capabilities. Therefore, we will be able to dene many
functional levels, starting with time independent combinational functions and continuing with
memory functions, sequencing functions, control functions and interpreting functions. Basically,
each new loop manifests itself by increasing the degree of autonomy of the system.
Therefore, the main goal of this section is to emphasize the fundamental developing mechanisms in digital systems which consist in compositions & loops by which digital systems gain
in size and in functional complexity.
In order to better understand the correlation between functional aspects and structural aspect
in digital systems we need a suggestive image about how these systems grow in size and how
they gain new functional capabilities. The oldest distinction between combinational circuits and
sequential circuits is now obsolete because of the diversity of circuits and the diversity of their
applications. In this section we present a new idea about a mechanism which emphasizes a
hierarchy in the world of digital system. This world will be hierarchically organized in orders
counted from 0 to n. At each new level a functional gain is obtained as a consequence of the
increased autonomy of the system.
Two are the mechanisms involved in the process of building digital systems. The rst allows
of system to grow in size. It is the composition, which help us to put together, using only
forward connections, many subsystems in order to have a bigger system. The second mechanism
is a special connection that provides new functional features. It is the loop connection, simply
the loop. Where a new loop is closed, a new kind of behavior is expected. To behave means,
mainly, to have autonomy. If a system use a part of own outputs to drive some of its inputs,
then he drives himself and an outsider receives this fact as an autonomous process.
Let us present in a systematic way, in the following subsections, the two mechanisms. Both
are very simple, but our goal is to emphasize, in the same time, some specic side eects as
consequences of composing & looping, like the pipeline connection used to accelerate the speed
of the too deep circuits or the speculative mechanisms used to allow loops to be closed in
pipelined structures.
Building a real circuit means mainly to interconnect simple and small components in order
to grow an enough fast system appropriately featured. But, growing is a concept with no precise
meaning. Many people do not make distinction between growing the size and growing the
complexity of a system, for example. We will start making the necessary distinctions between
size and complexity in the process of growing a digital system.
1
David Deutchs work on quantum computation laid the foundation for that eld, grounding new approaches
in both physics and the theory of computation. He is the author of The Fabric of Reality.
3.1. SIZE VS. COMPLEXITY
3.1
59
Size vs. Complexity
The huge size of the actual circuits implemented on a single chip imposes a more precise distinction between simple circuits and complex circuits. When we can integrated on a single chip
more than 109 components, the size of the circuits becomes less important than their complexity.
Unfortunately we dont make a clear distinction between size and complexity. We say usually:
the complexity of a computation is given by the size of memory and by the CPU time. But, if
we have to design a circuit of 100 million transistors it is very important to distinguish between
a circuit having an uniform structure and a randomly structured ones. In the rst case the
circuit can be easy specied, easy described in an HDL, easy tested and so on. Otherwise, if the
structure is completely random, without any repetitive substructure inside, it can be described
using only a description having a similar dimension with the circuit size. When the circuit is
small, it is not a problem, but for million of components the problem has no solution. Therefore,
if the circuit is very big, it is not enough to deal only with its size, the most important becomes
also the degree of uniformity of the circuit. This degree of uniformity, the degree of order inside
the circuit can be specied by its complexity.
As a consequence we must distinguish more carefully the concept of size by the concept of
complexity. Follow the denitions of these terms with the meanings we will use in this book.
Denition 3.1 The size of a digital circuit, Sdigital circuit , is given by the dimension of the
physical resources used to implement it.
In order to provide a numerical expression for size we need a more detailed denition which
takes into account technological aspects. In the 40s we counted electronic bulbs, in the 50s we
counted transistors, in the 60s we counted SSI2 and MSI3 packages. In the 70s we started to
use two measures: sometimes the number of transistors or the number of 2-input gates on the
Silicon die and other times the Silicon die area. Thus, we propose two numerical measures for
the size.
Denition 3.2 The gate size of a digital circuit, GSdigital circuit , is given by the total number
of CMOS pairs of transistors used for building the gates (see the appendix Basic circuits) used
to implement it4 .
This denition of size oers an almost accurate image about the Silicon area used to implement the circuit, but the eects of lay-out, of fan-out and of speed are not catched by this
denition.
Denition 3.3 The area size of a digital circuit, ASdigital circuit , is given by the dimension of
the area on Silicon used to implement it.
The area size is useful to compute the price of the implementation because when a circuit
is produced we pay for the number of wafers. If the circuit has a big area, the number of the
circuits per wafer is small and the yield is low5 .
Denition 3.4 The algorithmic complexity of a digital circuit, simply the complexity,
Cdigital circuit , has the magnitude order given by the minimal number of symbols needed to express
its denition.
2
Small Size Integrated circuits

Medium Size Integrated circuits
4
Sometimes gate size is expressed in the total number of 2-input gates necessary to implement the circuit.
We prefer to count CMOS pairs of transistors (almost identical with the number of inputs) instead of equivalent
2-input gates because is simplest. Anyway, both ways are partially inaccurate because, for various reasons, the
transistors used in implementing a gate have dierent areas.
5
The same number of errors make useless a bigger area of the wafer containing large circuits.
3
60
Denition 2.2 is inspired by Gregory Chaitins denition for the algorithmic complexity of a
string of symbols [Chaitin 77]. The algorithmic complexity of a string is related to the dimension
of the smallest program that generates it. The program is interpreted by a machine (more in
Chapter 12). Our Cdigital circuit can be associated to the shortest unambiguous circuit description
in a certain HDL (in the most of cases it is about a structural description).
Denition 3.5 A simple circuit is a circuit having the complexity much smaller than its size:
Csimple circuit << Ssimple circuit .
Usually the complexity of a simple circuit is constant: Csimple circuit O(1).
Denition 3.6 A complex circuit is a circuit having the complexity in the same magnitude
order with its size:
Ccomplex circuit Scomplex circuit .
Example 3.1 The following Verilog program describes a complex circuit, because the size of its
denition (the program) is
Sdef. of random
module random_circ(output
wire
w1, w2;
and and1(w1, a, b),
and2(w2, c, d);
or
or1(f, w1, c),
or2(g, w1, w2);
endmodule
circ
= k1 + k2 Srandom
f, g, input
circ
O(Srandom
circ ).
a, b, c, d, e);
Example 3.2 The following Verilog program describes a simple circuit, because the program
that dene completely the circuit is the same for any value of n.
module or_prefixes #(parameter n = 256)(output reg [0:n-1] out, input [0:n-1] in);
integer k;
always @(in) for (k=1; k<n; k=k+1) begin
out[0] = in[0];
out[k] = in[k] | out[k-1];
end
endmodule
The prexes of OR circuit consists in n OR2 gates connected in a very regular form. The
denition is the same for any value of n6 .
Composing circuits generate not only biggest structures, but also deepest ones. The depth
of the circuit is related with the associated propagation time.
Denition 3.7 The depth of a combinational circuit is equal with the total number of serially
connected constant input gates (usually 2-input gates) on the longest path from inputs to the
outputs of the circuit.
6
A short discussion occurs when the dimension of the input is specied. To be extremely rigorous, the parameter
n is expressed using a string o symbols in O(log n). But usually this aspect can be ignored.
3.2. GROWING THE SIZE BY COMPOSITION
61
The previous denition oers also only an approximate image about the propagation time
through a combinational circuit. Inspecting the parameters of the gates listed in Appendix
Standard cell libraries you will see more complex dependence contributing to the delay introduced
by a certain circuit. Also, the contribution of the interconnecting wires must be considered when
the actual propagation time in a combinational circuit is evaluated.
Some digital functions can be described starting from the elementary circuit which performs
them, adding a recursive rule for building a circuit that executes the same function for any size
of the input. For the rest of the circuits, which dont have such type of denitions, we must
use a denition that describes in detail the entire circuit. This description will be non-recursive
and thus complex, because its dimension is proportional with the size of circuit (each part of
the circuit must be explicitly specied in this kind of denition). We shall call random circuit a
complex circuit, because there is no (simple) rule for describing it.
The rst type of circuits, having recursive denitions, are simple circuits. Indeed, the elementary circuit has a constant (usually small) size and the recursive rule can be expressed using
a constant number of signs (symbolic expressions or drawings). Therefore, the dimension of
the denition remains constant, independent by n, for this kind of circuits. In this book, this
distinction, between simple and complex, will be exemplied and will be used to promote useful
distinctions between dierent solutions.
At the current technological level the size becomes less important than the complexity,
because we can produce circuits having an increasing number of components, but we can describe
only circuits having the range of complexity limited by our mental capacity to deal eciently
with complex representations. The rst step to have a circuit is to express what it must do in
a behavioral description written in a certain HDL. If this denition is too large, having the
magnitude order of a huge multi-billion-transistor circuit, we dont have the possibility to write
the program expressing our desire.
In the domain of circuit design we passed long ago beyond the stage of minimizing the number
of gates in a few gates circuit. Now, the most important thing, in the multi-billion-transistor
circuit era, is the ability to describe, by recursive denitions, simple (because we cant write
huge programs), big (because we can produce more circuits on the same area) sized circuits. We
must take into consideration that the Moores Law applies to size not to complexity.
3.2
Growing the size by composition
The mechanism of composition is well known to everyone who worked at least a little in mathematics. We use forms like:
f (x) = g(h1 (x), . . . , hm (x))
to express the fact that computing the function f requests to compute rst all the functions hi (x)
and after that the m-variable function g. We say: the function g is composed with the functions
hi in order to have computed the function f . In the domain digital systems a similar formalism
is used to compose big circuits from many smaller ones. We will dene the composition
mechanism in digital domain using a Verilog-like formalism.
Denition 3.8 The composition (see Figure 3.1) is a two level construct, which performs the
function f using on the second level the m-ary function g and on the rst level the functions
h 1, h 2, ... h m, described by the following, incompletely dened, but synthesisable, Verilog
modules.
module f #(include "parameters.v")(
wire
[size_1-1:0]
out_1;
output
input
[sizeOut-1:0]
[sizeIn-1:0]
out ,
in );
62
in
h 1
out 1
h 2
h m
out m
out 2
? ?
?
g
? out
= f(in)
Figure 3.1: The circuit performing composition. The function g is composed with the functions
h 1, ... h m using a two level circuit. The rst level contains m circuits computing in parallel the
functions h i, and on the second level there is the circuit computing the reduction-like function g.
wire
[size_2-1:0] out_2;
// ...
wire
[size_m-1:0] out_
g
second_level(
.out
(out
),
.in_1
(out_1 ),
.in_2
(out_2 ),
// ...
.in_m
(out_m ));
h_1 first_level_1(.out(out_1), .in(in));
// ...
h_m first_level_m(.out(out_m), .in(in));
endmodule
module g #(include "parameters.v")(
output
input
input
// ...
input
[sizeOut-1:0]
[size_1-1:0]
[size_2-1:0]
out ,
in_1,
in_2,
[size_m-1:0]
in_m);
// ...
endmodule
module h_1 #(include "parameters.v")( output [size_1-1:0] out ,
input [sizeIn-1:0] in );
// ...
endmodule
// ...
endmodule
// ...
module h_m #(include "parameters.v")( output [size_m-1:0] out ,
// ...
63
endmodule
The content of the le parameters.v is:

parameter
sizeOut
sizeIn
size_1
size_2
// ...
size_m
=
=
=
=
32,
8 ,
12,
16,
= 8
The general form of the composition, previously dened, can be called the serial-parallel
composition, because the modules h 1, ... h m compute in parallel m functions, and all are
serial connected with the module g (we can call it reduction type function, because it reduces the
vector generated by the previous level to a value). There are two limit cases. One is the serial
composition and another is the parallel composition. Both are structurally trivial, but represent
essential limit aspects regarding the resources of parallelism in a digital system.
Denition 3.9 The serial composition (see Figure 3.2a) is the composition with m = 1.
Results the Verilog description:
output
input
[sizeOut-1:0]
[sizeIn-1:0]
out ,
in );
[sizeOut-1:0]
[size_1-1:0]
out ,
in_1);
wire
[size_1-1:0] out_1;
g
second_level(
.out
(out
),
.in_1
(out_1 ));
endmodule
module g #(include "parameters.v")(
output
input
// ...
endmodule
// ...
endmodule
Denition 3.10 The parallel composition (see Figure 3.2b) is the composition in the particular case when g is the identity function. Results the following Verilog description:
wire
wire
// ...
wire
[size_1-1:0]
[size_2-1:0]
out_1;
out_2;
[size_m-1:0]
out_m;
assign out = {
out_m,
// ...
out_2,
output
input
[sizeOut-1:0]
[sizeIn-1:0]
out ,
in );
64
in
in
?
h1
?
h1
?
g
?
b.
?
h2
out 1
?
hm
out 2
out m
out
a.
Figure 3.2: The two limit forms of composition. a. The serial composition, for m = 1, imposing an inherent sequential computation. b. The parallel composition, with no reduction-like function,
performing data parallel computation.
out_1}; // g is identity function
// ...
h_m first_level_m(.out(out_m), .in(in));
endmodule
// ...
endmodule
// ...
endmodule
// ...
module h_m #(include "parameters.v")( output [size_m-1:0] out ,
// ...
endmodule
The content of the le parameters.v is now:

parameter
sizeIn
size_1
size_2
// ...
size_m
sizeOut
=
=
=
8
12
16
,
,
,
=
=
8
,
size_1 +
size_2 +
// ...
size_m
Example 3.3 Using the mechanism described in Denition 1.3 the circuit computing the scalar
product between two 4-component vectors will be dened, now in true Verilog. The test module
for n = 8 is also dened allowing to test the design.
65
module inner_prod #(include "parameter.v")

(output [((2*n+2)-1):0] out, input [n-1:0] a3, a2, a1, a0, b3, b2, b1, b0);
wire[2*n-1:0] p3, p2, p1, p0;
mult m3(p3, a3, b3),
m2(p2, a2, b2),
m1(p1, a1, b1),
m0(p0, a0, b0);
add4 add(out, p3, p2, p1, p0);
endmodule
module mult #(include "parameter.v")
(output [(2*n-1):0] out, input [n-1:0]
assign out = m1 * m0;
endmodule
m1, m0);
module add4 #(include "parameter.v")

(output [((2*n+2)-1):0] out, input [(2*n-1):0] t3, t2, t1, t0);
assign out = t3 + t2 + t1 + t0;
endmodule
a3
b3
a2
? ?
a1
? ?
m3
p3
b2
b1
? ?
m2
m1
p2
a0
b0
? ?
m0
p1
p0
????
add
out = a3*b3 + a2*b2 + a1*b1 + a0*b0
Figure 3.3: An example of composition. The circuit performs the scalar vector product for
4-element vectors. The rst level compute in parallel 4 multiplications generating the vectorial product,
and the second level reduces the resulting vector of products to a scalar.
The content of the le parameter.v is:

parameter n = 8
The simulation is done by running the module:

module test_inner_prod;
reg[7:0] a3, a2, a1, a0, b3, b2, b1, b0;
wire[17:0] out;
initial
begin
{a3, a2, a1, a0} = {8d1, 8d2, 8d3, 8d4};

{b3, b2, b1, b0} = {8d5, 8d6, 8d7, 8d8};
end
inner_prod dut(out, a3, a2, a1, a0, b3, b2, b1, b0);
initial $monitor("out=%0d", out);
endmodule
The test outputs: out = 70
66
The description is structural at the top level and behavioral for the internal sub-modules
(corresponding to our level of understanding digital systems). The resulting circuit is represented
in Figure 3.3.
VerilogSummary 8 :
The directive include is used to add in any place inside a module the content of the le
xxx.v writing: include "xxx.v"
We just learned how to concatenate many variables to obtain a bigger one (in the denition
of the parallel composition the output of the system results as a concatenation of the
outputs of the sub-systems it contains)
Is good to know there is also a risky way to specify the connections when a module is
instantiated into another: to put the name of connections in the appropriate positions in
the connection list (in the last example)
By composition we add new modules in the system, but we dont change the class to which
the system belongs. The system gains the behaviors of the added modules but nothing more.
By composition we sum behaviors only, but we can not introduce in this way a new kind of
behavior in the world of digital machines. What we cant do using new modules we can do with
an appropriate connection: the loop.
3.3
Speeding by pipelining
One of the main limitation in applying the composition is due to the increased propagation time
associated to the serially connected circuits. Indeed, the time for computing the function f is:
tf = max(th 1 , . . . , th
m)
+ tg
In the last example, the inner product is computed in:

tinner
product
= tmultiplication + t4
number add
If the 4-number add is also composed using 2-number add (as in usual systems) results:
tinner
product
= tmultiplication + 2 taddition
For the general case of n-components vectors the inner product will be computed, using a similar
approach, in:
tinner
product (n)
= tmultiplication + taddition log2 n O(log n)
For this simple example, of computing the inner product of two vectors, results for n n0 a
computational time bigger than can be accepted in some applications. Having enough multipliers, the multiplication will not limit the speed of computation, but even if we have innite
2-input adders the computing time will remain dependent by n.
The typical case is given by the serial composition (see Figure 3.2a), where the function
out = f (in) = g(h 1(in)) must be computed using 2 serial connected circuits, h 1(in) and
g(int out), in time:
tf = th 1 + tg .
3.3. SPEEDING BY PIPELINING
67
A solution must be nd to deal with the too deep circuits resulting from composing to many
or to lazy circuits.
First of all we must state that fast circuits are needed only when a lot of data is waiting to
be computed. If the function f (in) is rarely computed, then we do not care to much about the
speed of the associated circuit. But, if there is an application supposing a huge stream of data
to be successively submitted to the input of the circuit f , then it is very important to design a
fast version of it.
Golden rule: only what is frequently computed must be accelerated!
3.3.1
Register transfer level
The good practice in a digital system is: any stream of data is received synchronously and it is
sent out synchronously. Any digital system can be reduced to a synchronous machine receiving
a stream of input data and generating another stream of output results. As we already stated,
a robust digital design is a fully buered one because it provides a system interfaced to the
external world with registers.
The general structure of a system performing the function f (x) is shown in Figure 3.4a,
where it is presented in the fully buered version. This kind of approach is called register
transfer level (RTL) because data is transferred, modied by the function f , from a register,
input reg, to another register, output reg. If f = g(h 1(x)), then the clock frequency is limited
to:
fclock
max
1
1
=
treg + tf + tsu
treg + th 1 + tg + tsu
The serial connection of the module computing h 1 and g is a fundamental limit. If f

computation is not critical for the system including the module f , then this solution is very
good, else you must read and assimilate the next, very important, paragraph.
3.3.2
Pipeline structures
To increase the processing speed of a long stream of data the clock frequency must be increased.
If the stream has the length n, then the processing time is:
Tstream (n) =
1
fclock
(n + 2) = (treg + th
+ tg + tsu ) (n + 2)
The only way to increase the clock rate is to divide the circuit designed for f in two serially
connected circuits, one for h 1 and another for g, and to introduce between them a new register.
Results the system represented in Figure 3.4b. Its clock frequency is:
fclock
max
1
max(th 1 , tg ) + treg + tsu
and the processing time for the same string is:

Tstream (n) = (max(th 1 , tg ) + treg + tsu ) (n + 3)
The two systems represented in Figure 3.4 are equivalent. The only dierence between them
is that the second performs the processing in n + 3 clock cycles instead of n + 2 clock cycles
for the rst version. For big n, the current case, this dierence is a negligible quantity. We call
latency the number of the additional clock cycle. In this rst example latency is: = 1.
68
clock
in
in
clock
input reg
input reg
sync in
sync in
h 1(x)
f(x) = g(h 1(x))
int out
pipeline reg
out
sync int out
output reg
g(z)
sync out
out
output reg
sync out
a.
b.
Figure 3.4: Pipelined computation. a. A typical Register Transfer Logic (RTL) conguration.
Usually it is supposed a deep combinational circuit computes f (x). b. The pipeline structure splits the
combinational circuit associated with function f (x) in two less deep circuits and inserts the pipeline
register in between.
This procedure can be applied many times, resulting a processing pipe with a latency
equal with the number of the inserted register added to the initial system. The resulting system
is called a pipelined system. The additional registers are called pipeline registers.
The maximum eciency of a pipeline system is obtained in the ideal case when, for an
(m + 1)-stage pipeline, realized inserting m pipeline registers:
max(tstage 0 , tstage 1 , . . . , tstage
m)
tstage
max(tstage 0 , tstage 1 , . . . , tstage
+ tstage 1 + . . . + tstage
m+1
m)
>> treg + tsu
= m << n
In this ideal case the speed is increased almost m times. Obviously, no one of these condition
can be fully accomplished, but there are a lot of real applications in which adding an appropriate
number of pipeline stages allows to reach the desired speed performance.
Example 3.4 The pseudo-Verilog code for the 2-stage pipeline system represented in Figure 3.4
is:
module pipelined_f(
output reg [size_in-1:0]

input
[size_out-1:0]
reg
[size_in-1:0]
sync_in;
wire
[size_int-1:0] int_out,
reg
[size_int-1:0] sync_int_out;
wire
[size_out-1:0] out;
h_1 this_h_1(
.out
(int_out),
.in
(sync_in));
g
this_g( .out
(out),
.in
(sync_int_out));
sync_in
sync_out,
in);
<= #2 in;
3.3. SPEEDING BY PIPELINING
69
sync_int_out
sync_out
<= #2 int_out;
<= #2 out;
end
endmodule
module h_1(
output [size_int-1:0]
input
[size_in-1:0]
assign #15 out = ...;
endmodule
module g(
output [size_out-1:0]
input
[size_int-1:0]
assign #18 out = ...;
endmodule
out,
in);
out,
in);
Suppose, the unit time is 1ns. The maximum clock frequency for the pipeline version is:
fclock =
1
GHz = 50M Hz
max(15, 18) + 2
This value must be compared with the frequency of the non-pipelined version, which is:
fclock =
1
GHz = 28.57M Hz
15 + 18 + 2
Adding only a simple register and accepting a minimal latency ( = 1), the speed of the system
increased with 75%.
3.3.3
Data parallelism vs. time parallelism
The two limit cases of composition correspond to the two extreme cases of parallelism in digital
systems:
the serial composition will allow the pipeline mechanism which is a sort of parallelism
which could be called diachronic parallelism or time parallelism
the parallel composition is an obvious form of parallelism, which could be called synchronic
parallelism or data parallelism.
The data parallelism is more obvious: m functions, h 1, . . . , h m, are performed in parallel
by m circuits (see Figure 3.2b). But, time parallelism is not so obvious. It acts only in a
pipelined serial composition, where the rst stage is involved in computing the most recently
received data, the second stage is involved in computing the previously received data, and so
on. In an (m + 1)-stage pipeline structure m + 1 elements of the input stream are in dierent
stages of computation, and at each clock cycle one result is provided. We can claim that in such
a pipeline structure m + 1 computations are done in parallel with the price of a latency = m.
The previous example of a 2-stage pipeline accelerated the computation because of the time
parallelism which allows to work simultaneously on two input data, on one applying the function
h 1 and in another applying the function g. Both being simpler than the global function f , the
increase of clock frequency is possible allowing the system to deliver results at a higher rate.
Computer scientists stress on both type of parallelism, each having its own fundamental
limitations. More, each form of parallelism bounds the possibility of the other, so as the parallel
processes are strictly limited in now a day computation. But, for us it is very important to
emphasize in this stage of the approach that:
70

a3
a2
b3
a1
b2
? ?
DATA PARALLELISM
register
register
b0
register
register
? ?
a0
b1
register
TIME PARALLELISM
register
clock
register
Figure 3.5: The pipelined inner product circuit for 4-component vectors. Each multiplier
and each adder send its result in a pipeline register. For this application results a three level pipeline
structure with dierent degree of parallelism. The two kind of parallelism are exemplied. Data parallel
has the maximum degree on the rst level. The degree of time parallelism is three: in each clock cycle
three pairs of 4-element vectors are processed. One pair in the rst stage of multiplications, another pair
is the second stage of performing two additions, and one in the nal stage of making the last addition.
circuits are essentially parallel structures with both the possibilities and
the limits given by the mechanism of composition.
The parallel resources of circuits will be limited also, as we will see, in the process of closing
loops one after another with the hope to deal better with complexity.
Example 3.5 Let us revisit the problem of computing the scalar product. We redesign the circuit
in a pipelined version using only binary functions.
module pipelined_inner_prod(
output
input
input
[17:0]
[7:0]
out,
a3, a2, a1, a0, b3, b2, b1, b0,
clock);
wire[15:0] p3, p2, p1, p0;

wire[17:0] s1, s0;
mult
mult3(p3, a3, b3, clock),
mult0(p0, a0, b0, clock);
add
add11(s1, {1b0, p3}, {1b0, p2}, clock),
add10(s0, {1b0, p1}, {1b0, p0}, clock),
add0(out, s1[16:0], s0[16:0], clock);
endmodule
module mult(
output reg [15:0]

input
[7:0]
input
out
endmodule
out,
m1, m0,
clock);
<= m1 * m0;
3.4. FEATURING BY CLOSING NEW LOOPS
module add(output reg [17:0]

input
[16:0]
input
endmodule
71
out,
t1, t0,
clock);
out <= t1 + t0;
The structure of the pipelined inner product (dot product) circuit is represented in Figure
3.5. It shows us the two dimensions of the parallel computation. The horizontal dimension
is associated with data parallelism, the vertical dimension is associated with time parallelism.
The rst stage allows 4 parallel computation, the second allows 2 parallel computation, and the
last consists only in a single addition. The mean value of the degree of data parallelism is
2.33. The system has latency 2, allowing 7 computations in parallel. The peak performance
of this system is the whole degree of parallelism which is 7. The peak performance is the
performance obtained if the input stream of data is uninterrupted. If it is interrupted because
of the lack of data, or for another reason, the latency will act reducing the peak performance,
because some or all pipeline stages will be inactive.
3.4
Featuring by closing new loops
A loop connection is a very simple thing, but the eects introduced in the system in which it is
closed are sometimes surprising. All the time are beyond the evolutionary facts. The reason for
these facts is the spectacular eect of the autonomy whenever it manifests. The output of the
system starts to behave less conditioned by the evolution of inputs. The external behavior of the
system starts to depend more and more by something like an internal state continuing with
a dependency by an internal behavior. In the system starts to manifest internal processes
seem to be only partially under the external control. Because the loop allows of system to act
on itself, the autonomy is the rst and the main eect of the mechanism of closing loops. But,
the autonomy is only a rst and most obvious eect. There are others, more subtle and hidden
consequences of this apparent simple and silent mechanism. This book is devoted to emphasize
deep but not so obvious correlations between loops and complexity. Lets start with the denition
and a simple example.
in
in1
in0
out1
out0
Y
the loop
loop
?out
Figure 3.6: The loop closed into a digital system. The initial system has two inputs, in1 and
in0, and two outputs, out1 and out0. Connecting out0 to in0 results a new system with in and out
only.
Denition 3.11 The loop consists in connecting some outputs of a system to some of its inputs
(see Figure 3.6), as in the pseudo-Verilog description that follows:
72
module loop_system #(include "parameters.v")( output

input
wire
[loop_dim-1:0]
the_loop;
no_loop_system our_module( .out1
(out)
,
.out0
(the_loop) ,
.in1
(in)
,
.in0
(the_loop) );
endmodule
module no_loop_system #(include "parameters.v")(
[out_dim-1:0]
[in_dim-1:0]
output
output
input
input
out ,
in );
[out_dim-1:0]
[loop_dim-1:0]
[in_dim-1:0]
[loop_dim-1:0]
out1
out0
in1
in0
,
,
,
);
/* The description of no_loop_system module */

endmodule
The most interesting thing in the previous denition is a hidden variable occurred in
module loop system(). The wire called the loop carries the non-apparent values of a variable
evolving inside the system. This is the variable which evolves only internally, generating the
autonomous behavior of the system. The explicit aspect of this behavior is hidden, justifying
the generic name of the internal state evolution.
The previous denition dont introduce any restriction about how the loop must be closed. In
order to obtain desired eects the loop will be closed keeping into account restrictions depending
by each actual situation. There also are many technological restrictions that impose specic
modalities to close loops at dierent level in a complex digital system. Most of them will be
discussed later in the next chapters.
Example 3.6 Let be a synchronous adder. It has the outputs synchronized with an positive
edge clocked register (see Figure 3.7a). If the output is connected back to one of its input, then
results the structure of an accumulator (see Figure 3.7b). The Verilog description follows.
module acc(output[19:0] out, input[15:0] in, input clock, reset);
sync_add our_add(out, in, out, clock, reset);
endmodule
module sync_add(
output reg [19:0]

input
[15:0]
input
[19:0]
input
else
endmodule
out
,
in1
,
in2
,
clock
, reset );
out = 0;
out = in1 + in2;
In order to make a simulation the next test acc module is written:

module test_acc;
reg clock, reset;
reg[15:0] in;
wire[19:0] out;
initial begin
clock = 0;
end // the clock
initial begin
reset = 1;
#2 reset = 0;
#10 $stop;
in1
73
in
in2
adder
reset
clock
register
adder
reset
? ?
clock
register
?out
a.
? out
b.
Figure 3.7: Example of loop closed over an adder with synchronized output. If the
output becomes one of the inputs, results a circuit that accumulates at each clock cycle. a. The initial
circuit: the synchronized adder. b. The resulting circuit: the accumulator.
end
in = 0;
else
in = in + 1;
acc dut(out, in, clock, reset);
initial $monitor("time=%0d clock=%b in=%d out=%d",
$time, clock, in, dut.out);
endmodule
By simulation results the following behavior:

#
#
#
#
#
#
#
#
#
#
#
#
time=0 clock=0 in=

time=1 clock=1 in=
time=2 clock=0 in=
time=3 clock=1 in=
time=4 clock=0 in=
time=5 clock=1 in=
time=6 clock=0 in=
time=7 clock=1 in=
time=8 clock=0 in=
time=9 clock=1 in=
time=10 clock=0 in=
time=11 clock=1 in=
x
0
0
1
1
2
2
3
3
4
out=
out=
out=
out=
out=
out=
out=
out=
out=
out=
4 out=
5 out=
x
0
0
1
1
3
3
6
6
10
10
15
The adder becomes an accumulator. What is spectacular in this fact? The step made by
closing the loop is important because an obedient circuit, whose outputs followed strictly
the evolution of its inputs, becomes a circuit with the output depending only partially by the
evolution of its inputs. Indeed, the the output of the circuit depends by the current input but,
in the same time, depends by the content of the register, i.e., by the history accumulated in
it. The output of adder can be predicted starting from the current inputs, but the output of
the accumulator supplementary depends by the state of circuit (the content of the register). It
was only a simple example, but I hope, useful to pay more attention to loop.
3.4.1
Data dependency
The good news about loop is its ability to add new features. But any good news is accompanied by its
own bad news. In this case is about the limiting of the degree of parallelism allowed in a system with a
74
just added loop. It is mainly about the necessity to stop sometimes the input stream of data in order to
decide, inspecting an output, how to continue the computation. The input data waits for data arriving
from an output a number of clock cycles related with the system latency. To do something special the
system must be allowed to accomplish certain internal processes.
Both, data parallelism and time parallelism are possible because when the data arrive the system
knows what to do with them. But sometimes the function to be applied on certain input data is decided
by processing previously received data. If the decision process is to complex, then new data can not be
processed even if the circuits to do it are there.
Example 3.7 Let be the system performing the following function:
procedure cond_acc(a,b, cond);
out = 0;
end = 0;
loop
if (cond = 1)
out = out + (a + b);
else
out = out + (a - b);
until (end = 1) // the loop is unending
end
For each pair of input data the function is decided according to a condition input.
The Verilog code describing an associated circuit is:
module cond_acc0(
output reg [15:0] out,

input
[15:0] a, b,
input
cond, reset, clock);
if (reset)
out <= 0;
else if (cond)
out <= out + (a + b);
else
out <= out + (a - b);
endmodule
In order to increase the speed of the circuit a pipeline register is added with the penalty of = 1.
Results:
module cond_acc1(
output
input
input
reg [15:0]
[15:0]
out,
a, b,
cond, reset, clock);
reg[15:0] pipe;
if (reset)
begin
out <= 0;
pipe <= 0;
end
else begin
if (cond)
pipe <= a + b;
else
pipe <= a - b;
out <= out + pipe;
end
endmodule
Now let us close a loop
input takes the value of the
on each pair of input data
the computation performed
addapt acc.
in the rst version of the system (without pipeline register). The condition
sign of the output. The loop is: cond = out[15]. The function performed
in each clock cycle is determined by the sign of the output resulted from
with the previously received pairs of data. The resulting system is called
module addapt_acc0(output [15:0] out,

input
[15:0] a, b,
input
reset, clock);
cond_acc0 cont_acc0( .out
(out),
75
cond
a
+/-
- ? ?
cond
- ? ?
?
+/-
pipe reg
? ?
? ?
clock
out reg
out reg
clock
out
?
out
?
a.
b.
a
- ? ?
a
+/-
- ? ?
+/-
pipe reg
? ?
? ?
clock
out reg
out reg
clock
out[15]
out[15]
out
c.
out
?
d.
Figure 3.8: Data dependency when a loop is closed in a pipelined structure. a. The
non-pipelined version. b. The pipelined version. c. Adding a loop to the non-pipelined version. d.
To the pipelined version the loop can not be added without supplementary precautions because data
dependency change the overall behavior. The selection between add and sub, performed by the looped
signal comes too late.
.a
.b
.cond
.reset
.clock
(a),
(b),
(out[15]),
(reset),
(clock));
// the loop
endmodule
Figure 3.8a represents the rst implementation of the cond acc circuit, characterized by a low clock
frequency because both the adder and the adder/subtracter contribute to limiting the clock frequency:
fclock =
1
t+/ + t+ + treg
Figure 3.8b represents the pipelined version of the same circuit working faster because only one from
adder and the adder/subtracter contributes to limiting the clock frequency:
fclock =
A small price is paid by = 1.
1
max(t+/ , t+ ) + treg
76
The 1-bit loop closed from the output out[15] to cond input (see Figure 3.8c) allows the circuit to
decide itself if the sum or the dierence is accumulated. Its speed is identical with the initial, no-loop,
circuit.
Figure 3.8d warns us against the expected damages of closing a loop in a pipelined system. Because
of the latency the decision comes to late and the functionality is altered.
In the system from Figure 3.8a the degree of parallelism is 1, and in Figure 3.8b the system has the
degree of parallelism 2, because of the pipeline execution. When we closed the loop we where obliged to
renounce to the bigger degree of parallelism because of the latency associated with the pipe. We have a
new functionality the circuit decides itself regarding the function executed in each clock cycle but we
must pay the price of reducing the speed of the system.
According to the algorithm the function performed by the block +/- depends on data received in the
previous clock cycles. Indeed, the sign of the number stored in the output register depends on the data
stream applied on the inputs of the system. We call this eect data dependency. It is responsible for
limiting the degree of parallelism in digital circuits.
The circuit from Figure 3.8d is not a solution for our problem because the condition cond comes to
late. It corresponds to the operation executed on the input stream excepting the most recently received
pair of data. The condition comes too late, with a delay equal with the latency introduced by the pipeline
execution.
3.4.2
Speculating to avoid limitations imposed by data dependency
How can we avoid the speed limitation imposed by a new loop introduced in a pipelined execution? It is
possible, but we must pay a price enlarging the structure of the circuit.
If the circuit does not know what to do, addition or subtract in our previous example, then in it will be
compute both in the rst stage of pipeline and will delay the decision for the next stage so compensating
the latency. We use the same example to be more clear.
Example 3.8 The pipelined version of the circuit addapt acc is provided by the following Verilog code:
b
a
? ?
? ?
-
??
??
pipe1
reset
pipe0
clock
? ?
1
0
mux2 16
? ?
+
??
out
out[15]
?
out
Figure 3.9: The speculating solution to avoid data dependency. In order to delay the
moment of decision both addition and subtract are computed on the rst stage of pipeline. Speculating
means instead to decide what to do, addition or subtract, we decide what to consider after doing both.
module addapt_acc1(output
reg [15:0]
out,
3.5. CONCLUDING ABOUT COMPOSING & PIPELINING & LOOPING

input
[15:0]
input
reg
[15:0] pipe1, pipe0;
if (reset) begin
out <= 0;
pipe1 <= 0;
pipe0 <= 0;
end
else
begin
pipe1 <= a + b;
pipe0 <= a - b;
if (out[15])
out
else
out
end
endmodule
77
a, b,
reset, clock);
<= out + pipe1;

<= out + pipe0;
The execution time for this circuit is limited by the following clock frequency:
fclock =
1
1
max(t+ , t , (t+ + tmux )) + treg

t + treg
The resulting frequency is very near to the frequency for the pipeline version of the circuit designed in the
previous example.
Roughly speaking, the price for the speed is: an adder & two registers & a multiplexer (see for
comparing Figure 3.8c and Figure 3.9). Sometimes it deserves!
The procedure applied to design addapr acc1 involves the multiplication of the physical resources.
We speculated, computing on the rst level of pipe both the sum and the dierence of the input values.
On the second state of pipe the multiplexer is used to select the appropriate value to be added to out.
We call this kind of computation speculative evaluation or simply speculation. It is used to accelerate
complex (i.e., under the sign of a loop) computation. The price to be paid is an increased dimension
of the circuit.
3.5
Concluding about composing & pipelining & looping
The basic ideas exposed in this section are:

a digital system develops applying two mechanisms: composing functional modules and
closing new loops
by composing the system grows in size improving its functionality with the composed
functions
by closing loops the system gains new features which are dierent from the previous
functionality
the composition generates the conditions for two kinds of parallel computation:
data parallel computation
time parallel computation (in pipeline structures)
the loop limits the possibility to use the time parallel resources of a system because of
data dependency
a speculative approach can be used to accelerate data dependent computation in pipeline
systems; it means the execution of operation whose result may not actually be needed; it
is an useful optimization when early execution accelerates computation justifying for the
wasted eort of computing a value which is never used
78

circuits are mainly parallel systems because of composition (some restriction may apply
because of loops).
Related with the computing machines Flynn [Flynn 72] introduced three kind of parallel
machines:
MIMD (multiple-instructions-multiple data), which means mainly having dierent programs working on dierent data
SIMD (single-instructions-multiple-data), which means having one program working on
dierent data,
MISD (multiple-instructions-single-data), which means having dierent programs working
on the same data.
Related with the computing a certain function also three kind of almost the same parallelism
can be emphasized:
time parallelism, which is somehow related with MIMD execution, because in each temporal
stage a dierent operation (instruction) can be performed
data parallelism, which is identic with SIMD execution
speculative parallelism, which is a sort of MISD execution.
Thus, the germs of parallel processes, developed at the computing machine level, occur, at an
early stage, at the circuit level.
3.6
Problems
Speculative circuits
Problem 3.1 Let be the circuit described by the following Verilog module:
module xxx( output
input
input
input
input
input
reg [31:0]
[31:0]
[31:0]
[31:0]
a
x1
x2
x3
clock
reset
,
,
,
,
,
);
always @(posedge clock) if (reset) a <= 0;

else if (a > x3)
else
endmodule
a <= a + (x1 + x2);

a <= a + (x1 - x2);
The maximum frequency of clock is limited by the propagation time through the internal loop
(tregr eg ) or by tin reg . To maximize the frequency a speculative solution is asked.
Problem 3.2 Provide the speculative solution for the next circuit.
module yyy( output
output
input
input
input
input
reg [31:0]
reg [31:0]
[31:0]
[31:0]
a
b
x1
x2
clock
reset
,
,
,
,
,
);
3.7. PROJECTS
79

if (reset) begin
a <= 0;
b <= 0;
end
else
case({a + b > 8b101, a - b < 8b111})
2b00: {a,b} <= {a + (x1-x2),
2b01: {a,b} <= {a + (8b10 * x1+x2),
2b10: {a,b} <= {a + (8b100 * x1-x2),
2b11: {a,b} <= {a + (x2-x1),
endcase
endmodule
b
b
b
b
+
+
+
+
(x1+x2)
};
(x1+8b10 * x2) };
(8b100 * x2)
};
(8b100 * x1+x2)};
Problem 3.3 The following circuit has two included loops. The speculation will increase the
dimension of the circuit accordingly. Provide the speculative version of the circuit.
module zzz( output
input
input
input
input
input
reg
[15:0]
reg [31:0]
[15:0]
[15:0]
[15:0]
out,
x1,
x2,
x3,
clock,
reset);
acc;

if (reset)
begin
out <= 0;
acc <= 0;
end
else
begin
out <= acc * x3;
if (out[15])
acc <= acc + x1 + x2 + out[31:0];
else
acc <= acc + x1 - x2 + out[15:0];
end
endmodule
3.7
Projects
Project 3.1
80
Chapter 4
THE TAXONOMY OF DIGITAL

SYSTEMS
the basic mechanisms involved in dening the architecture of a digital system were
introduced:
the parallel composing and the serial composing are the mechanism allowing two kind
of parallelism in digital systems data parallelism & time parallelism both involved
in increasing the brute force of a computing machine
the pipeline connection supports the time parallelism, accelerating the inherent serial
computation
closing loops new kinds of functionality are allowed (storing, behaving, interpreting,
... self-organizing)
speculating is the third type of parallelism introduced to compensate the limitations
generated by loops closed in pipelined systems
In this chapter
loops are used to classify digital systems in orders, takeing into account the increased
degree of autonomy generated by each new added loop. The main topics are:
the autonomy of a digital system depends on the number of embedded loops closed
inside
the loop based taxonomy of digital systems developed to match the huge diversity of
the systems currently developed
some preliminary remarks before starting to describe in detail digital circuits and
how they can be used to design digital systems
In the next chapter
the nal target of our lessons on digital design is dened as the structure of the simplest
machine able to process a stream of input data providing another stream of output data.
The functional description of the machine is provided emphasizing:
the external connections and how they are managed
the internal control functions of the machine
the internal operations performed on the received and internally stored data.
81
82
CHAPTER 4. THE TAXONOMY OF DIGITAL SYSTEMS
A theory is a compression of data; comprehension is compression.

Gregory Chaitin1
Any taxonomy is a compressed theory, i.e., a
compression of a compression. It contains,
thus, illuminating beauties and dangerous insights for our way to comprehend a technical
domain. How can we escape from this attractive trap? Trying to comprehend beyond what
the compressed data oers.
4.1
Loops & Autonomy
The main and the obvious eect of the loop is the autonomy it can generate in a digital system.
Indeed, the rst things we observe in a circuit in which a new loop is introduced are new and
independent behaviors. Starting with a simple example the things will become more clear in an
easy way. We use an example with a system initially dened by a transition table. Each output
corresponds to an input with a certain delay (one time unit, #1, in our example). After closing
the loop, starts a sequential process, each sequence taking time corresponding with the delay
introduced by the initial system.
Example 4.1 Let be the digital system initSyst from Figure 4.1a, with two inputs, in, lp,
and one output, out. What hapend when is closed the loop from the output out to the input lp?
Lets make it. The following Verilog modules describe the behavior of the resulting circuit.
module loopSyst(
output [1:0]
out,
input
in);
initSyst noLoopSyst(.out(out), .in(in), .loop(out));
endmodule
module initSyst(
output
input
input
reg [1:0]
[1:0]
out ,
in ,
loop);
initial out = 2b11; // only for simulation purpose

always @(in or loop) #1 case ({in, loop})
3b000: out
3b001: out
3b010: out
3b011: out
3b100: out
3b101: out
3b110: out
3b111: out
endcase
endmodule
1
From [Chaitin 06]
=
=
=
=
=
=
=
=
2b01;
2b00;
2b00;
2b10;
2b01;
2b10;
2b11;
2b01;
4.1. LOOPS & AUTONOMY
83
In order to see how behave loopSyst we will use the following test module which initialize
(for this example in a non-orthodox fashion because we dont know nothing about the internal
structure of initSyst) the output of initSyst in 11 and put on the input in for 10 unit time
the value 0 and for the next 10 unit time the value 1.
module test;
reg in;
wire[1:0] out;
initial begin
in = 0;
#10
in = 1;
#10
$stop;
end
loopSyst dut(out, in);
initial $monitor(
"time=%0d in=%b out=%b",
$time, in, dut.out);
endmodule
{in, lp} out
in
lp
?
Y
initSyst
loopSyst
?out
a.
b.
?
00
01
00
6o
01
00
00
10
01
10
11
01
00
01
10
11
00
01
10
11
?
01
10
10
11
c.
0
0
0
0
1
1
1
1
11
d.
Figure 4.1: Example illustrating the autonomy. a. A system obtained from an initial system
in which a loop is closed from output to one of its input. b. The transition table of the initial system
where each output strict corresponds to the input value. c. The output evolution for constant input: in
= 0. d. The output evolution for a dierent constant input: in = 1.
The simulation oers us the following behavior:

#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
time=0
time=1
time=2
time=3
time=4
time=5
time=6
time=7
time=8
time=9
time=10
time=11
time=12
time=13
time=14
time=15
in=0
in=0
in=0
in=0
in=0
in=0
in=0
in=0
in=0
in=0
in=1
in=1
in=1
in=1
in=1
in=1
out=11
out=10
out=00
out=01
out=00
out=01
out=00
out=01
out=00
out=01
out=00
out=01
out=10
out=11
out=01
out=10
84

#
#
#
#
time=16
time=17
time=18
time=19
in=1
in=1
in=1
in=1
out=11
out=01
out=10
out=11
The main eect we want to emphasize is the evolution of the output under no variation of
the input in. The initial system, dened in the previous case, has an output that switches only
responding to the input changing (see also the table from Figure 4.1b). The system which results
closing the loop has its own behavior. This behavior depends by the input value, but is triggered
by the events coming through the loop. Figure 4.1c shows the output evolution for in = 0 and
Figure 4.1d represents the evolution for in = 1.
VerilogSummary 9 :
the register reg[1:0] out dened in the module initSyst is nor a register, it is a Verilog
variable, whose value is computed by a case procedure anytime at least one of the two
inputs change (always @(in or lp))
a register which changes its state ignoring a clock edge is not a register, it is a variable
evolving like the output of a combinational circuit
what is the dierence between an assign and an always (a or b or ...)? The body
of assign is continuously evaluated, rather than the body of always which is evaluated
only if at least an element of the list of sensitivity ((a or b or ...)) changes
in running a simulation an assign is more computationally costly in time than an always
which is more costly in memory resources.
Until now we used in a non-rigorous manner the concept of autonomy. It is necessary for
our next step to dene more clearly this concept in the digital system domain.
Denition 4.1 In a digital system a behavior is called autonomous i for the same input
dynamic there are dened more than one distinct output transitions, which manifest in distinct
moments.
If we take again the previous example we can see in the result of the simulation that in the
moment time = 2 the input switches from 0 to 0 and the output from 10 to 00. In the next
moment input switches the same, but output switches from 00 to 10. The input of the system
remains the same, but the output behaves distinctly. The explanations is for us obvious because
we have access to the denition of the initial system and in the transition table we look for the
rst transition in the line 010 and we nd the output 00 and for the second in the line 000
nding there 00. The input of the initial system is changed because of the loop that generates
a distinct response.
In our example the input dynamic is null for a certain output dynamic. There are example
when the output dynamic is null for some input transitions (will be found such examples when
we talk about memories).
Theorem 4.1 In the respect of the previous denition for autonomy, closing an internal loop
generates autonomous behaviors.
Proof
Let be The description of no loop system module from Denition 3.4 described, in the general form, by the following pseudo-Verilog construct:
4.2. CLASSIFYING DIGITAL SYSTEMS

always @(in1 or in0) #1
case (in1)
... :
case (in0)
... : {out1,
...
... : {out1,
endcase
...
... :
case (in0)
... : {out1,
...
... : {out1,
endcase
endcase
85
out0} = f_00(in1, in0);

out0} = f_0p(in1, in0);
out0} = f_q0(in1, in0);

out0} = f_qp(in1, in0);
The various occurrences of {out1, out2} are given by the functions f ij(in1, in2) dened
in Verilog.
When the loop is closed, in0 = out0 = state, the in1 remains the single input of the
resulting system, but the internal structure of the system continue to receive both variable, in1
and in0. Thus, for a certain value of in1 there are more Verilog functions describing the next
value of {out1, out0}. If in1 = const, then the previous description is reduced to:
always @(state) #1 case (state)
... : {out1, state} = f_i0(const, state);
...
... : {out1, state} = f_ip(const, state};
endcase
The output of the system, out1, will be computed for each change of the variable state,
using the function f ji selected by the new value of state, which function depends by state.
For each constant value of in1 another set of functions is selected. In the two-level case, which
describe no loop system, this second level is responsible for the autonomous behavior.
4.2
Classifying Digital Systems
The two mechanisms, of composing and of looping, give us a very good instrument for a
new classication of digital systems. If the system grows by dierent compositions, then it
allows various kinds of connections. In this context the loops are dicult to be avoided. They
occur sometimes in large systems without the explicit knowledge of the designer, disturbing
the design process. But, usually we design being aware of the eect introduced by this special
connection the loop. This mechanism leads us to design a complex network of loops which
include each other. Thus, in order to avoid ambiguities in using the loops we must dene what
means included loop. We shall use frequently in the next pages this expression for describing
how digital systems are built.
Denition 4.2 A loop includes another loop only when it is closed over a serial or a serialparallel composition which have at least one subsystem containing an internal loop, called an
included loop.
Attention! In a parallel composition a loop going through one of the parallel connected
subsystem does not include a loop closed over another parallel connected subsystem. A new
loop of the kind grows only a certain previously closed loop, but does not add a new one.
86
Example 4.2 In Figure 4.2 the loop (1) is included by the loop (2). In a serial composition
built with S1 and S2 interconnected by (3), we use the connection (2) to add a new loop.
?
*
the loop which includes
(2)
?
S1
1 (3)
?
? i
the serial connection

S2
(1)
the included loop
Y
?
Figure 4.2: Included loops. The loop (2) includes loop (1), closed over the subsystem S2 , because
S2 is serially connected with the subsystem S1 and loop (2) includes both S1 and S2 .
Now we can use the next recursive denition for a new classication of digital systems. The
classication contains orders, from 0 to n.
Denition 4.3 Let be a n-order system, n-OS. A (n+1)-OS can be built only adding a new loop
which includes the rst n loops. The 0-OS contains only combinational circuits (the loop-less
circuits).
This classication in orders is very consistent with the nowadays technological reality for
n < 5. Over this order the functions of digital systems are imposed mainly by information, this
strange ingredient who blinks in 2-OS, is born in 3-OS and grows in 4-OS monopolizing the
functional control in digital systems (see Chapter 16 in this book). But obviously, a function
of a circuit belonging of certain order can be performed also by circuits from any higher ones.
For this reason we use currently circuits with more than 4 loops only for they allow us to apply
dierent kind of optimizations. Even if a new loop is not imposed by the desired functionality,
we will use it sometimes because of its eect on the system complexity. As will be exemplied,
a good tted loop allows the segregation of the simple part from an apparent complex system,
having as main eect a reduced complexity.
Our intention in the second part of this book is to propose and to show how works the
following classication:
0-OS - combinational circuits, with no autonomy
1-OS - memories, having the autonomy of internal state
2-OS - automata, with the autonomy to sequence
3-OS - processors, with the autonomy to control
4-OS - computers, with the autonomy to interpret
...
n-OS - systems with the highest autonomy: to self-organize.
This new classication can be exemplied2 (see also Figure 4.3) as follows:
2
For almost all the readers the following enumeration is now meaningless. They are kindly invited to revisit
this end of chapter after assimilating the rst 7 chapter of this book.
4.2. CLASSIFYING DIGITAL SYSTEMS
87
? ?
CLC
?
0-OS: Combinational Circuit
1-OS: Memory Circuit
commands
clock
CLC
Register
state
6 ?
2-OS: Automaton
Eecrory
Automaton
?
Controll
Automaton
6 ?
ags
3-OS: Processor
6
6
6
?
?
?
Memory
Processor
66
address
666
data
controll
6
6
6
?
?
?
6
6
6
?
?
?
6
?
4-OS: Computer
6
?
6
?
n-OS: Cellular Automaton
Figure 4.3: Examples of circuits belonging to dierent orders. A combinational circuit

is in 0-OS class because has no loops. A memory circuit contains one-loop circuits and therefore it is
in 1-OS class. Because the register belongs to 1-OS class, closing a loop containing a register and a
combinational circuit (which is in 0-OS class) results an automaton: a circuit in 2-OS class. Two loop
connected automata a circuit in 3-OS class can work as a processor. An example of 4-OS is a simple
computer obtained loop connecting a processor with a memory. Cellular automata contains a number of
loops related with the number of automata it contains.
0-OS: gate, elementary decoder (as the simplest parallel composition), buered elementary
decoder (the simplest serial-parallel composition), multiplexer, adder, priority encoder, ...
1-OS: elementary latch, master-slave ip-op (serial composition), random access memory
(parallel composition), register (serial-parallel composition), ...
2-OS: T ip-op (the simplest two states automaton), J-K ip-op (the simplest two input
automaton), counters, automata, nite automata, ...
3-OS: automaton using loop closed through K-J ip-ops or counters, stack-automata,
elementary processors, ...
4-OS: micro-controller, computer (as Processor & RAM loop connected), stack processor,
co-processor
...
n-OS: cellular automaton.
88
The second part of this book is devoted to sketch a digital system theory based on these
two-mechanism principle of evolving in digital circuits: composing & looping. Starting with
combinational, loop-less circuits with no autonomy, the theory can be developed following the
idea of the increasing system autonomy with each additional loop. Our approach will be a
functional one. We will start with simple functions and we will end with complex structures
with emphasis on the relation between loops and complexity.
4.3
# Digital Systems
When a global loop is introduced in an n-order system results a super digital system (SDS).
4.4
Preliminary Remarks On Digital Systems
The purpose of this rst part of the book is to run over the general characteristics of digital
systems using an informal high level approach. If the reader become accustomed with the basic
mechanisms already described, then in the second part of this book he will nd the necessary
details to make useful the just acquired knowledge. In the following paragraphs the governing
ideas about digital systems are summed up.
Combinational circuits vs. sequential circuits Digital systems receive symbols or stream
of symbols on their inputs and generate other symbols or stream of symbols on their outputs
by computation. For combinational systems each generated symbol depends only by the last
recently received symbol. For sequential systems at least certain output symbols are generated
taking into account, instead of only one input symbol, a stream of more than one input symbols.
Thus, a sequential system is history sensitive, memorizing the meaningful events for its own
evolution in special circuits called registers using a special synchronization signal the clock.
Composing circuits & closing loops A big circuit results composing many small ones. A
new kind of feature can be added only closing a new loop. The structural composing corresponds
the the mathematical concept of composition. The loop corresponds somehow to the formal
mechanism of recursion. Composing is an additive process which means to put together
dierent simple function to obtain a bigger or a more complex one. Closing a loop new behaviors
occur. Indeed, when a snake eats a mouse nothing special happens, but if the Orouboros3 serpent
bits its own tail something very special must be expected.
Composition allows data parallelism and time parallelism Digital systems perform
in a natural way parallel computation. The composition mechanism generate the context
for the most frequent forms of parallelism: data parallelism (in parallel composition) and time
parallelism (in serial composition). Time parallel computation is performed in pipeline systems,
where the only limitation is the latency, which means we must avoid to stop the ow of data
through the pipe. The simplest data parallel systems can be implemented as combinational
circuits. The simplest time parallel systems must be implemented as sequential circuits.
3
This symbol appears usually among the Gnostics and is depicted as a dragon, snake or serpent biting its own
tail. In the broadest sense, it is symbolic of time and the continuity of life. The Orouboros biting its own tail
is symbolic of self-fecundation, or the primitive idea of a self-sucient Nature - a Nature, that is continually
returning, within a cyclic pattern, to its own beginning.
4.5. PROBLEMS
89
Closing loops disturbs time parallelism The price we pay for the additional features we
get when a new loop is closed is, sometimes, the necessity to stop the data ow through the
pipelined circuits. The stop is imposed by the latency and the eect can be loosing, totaly or
partially, the benet of the existing time parallelism. Pipelines & loops is a bad mixture, because
the pipe delays the data coming back from the output of the system to its own input.
Speculation can restore time parallelism If the data used to decide comes back to late,
the only solution is to delay also the decision. Follows, instead of selecting what to do, the
need to perform all the computations envisaged by the decision and to select later only the
desired result according to the decision. To do all the computations means to perform speculative
parallel computation. The structure imposed for this mechanism is a MISD (multiple instruction
single data) parallel computation on certain pipeline stage(s). Concluding, three kind of parallel
processes can be stated in a digital system: data parallelism, time parallelism and speculative
parallelism.
Closed loops increase system autonomy The features added by a loop closed in a digital
system refer mainly to dierent kinds of autonomy. The loop uses the just computed data to
determine how the computation must be continued. It is like an internal decision is partially
driven by the system behavior. Not all sort of autonomy is useful. Some times the increased
autonomy makes the system too stubborn, unable to react to external control signals. For this
reason, only an appropriately closed loop generates an useful autonomy, that autonomy which
can be used to minimize the externally exercised control. More about how to close proper loops
in the next chapters.
Closing loops induces a functional hierarchy in digital systems The degree of autonomy is a good criteria to classify digital systems. The proposed taxonomy establishes the degree
of autonomy counting the number of the included loops closed inside a system. Digital system
are classied in orders: the 0-order systems contain no loop circuits, and n-order systems contain
at least one circuit with n included loops. This taxonomy corresponds with the structural and
functional diversity of the circuits used in the actual digital systems.
The top view of the digital circuits domain is almost completely characterized by the previous
features. Almost all of them are not technology dependent. In the following, the physical
embodiment of these concepts will be done using CMOS technology. The main assumptions
grounding this approach may change in time, but now they are enough robust and are simply
stated as follows: computation is an eective formally dened process, specied using nite
descriptions, i.e., the length of the description is not related with the dimension of the processed
data, with the amount of time and of physical resources involved.
Important question: What are the rules for using composition and looping? No rules restrict
us to compose or to loop. The only restrictions come from our limited imagination.
4.5
Problems
Autonomous circuits
Problem 4.1 Prove the reciprocal of Theorem 1.1.
90
Problem 4.2 Let be the circuit from Problem 1.25. Use the Verilog simulator to prove its
autonomous behavior. After a starting sequence applied on its inputs, keep a constant set of
values on the input and see if the output is evolving.
Can be dened an input sequence which brings the circuit in a state from which the autonomous behavior is the longest (maybe unending)? Find it if it exists.
Problem 4.3 Design a circuit which after the reset generates in each clock cycle the next Fibbonaci number starting from zero, until the biggest Fibbonaci number smaller than 232 . When
the biggest number is generated the machine will start in the next clock cycle from the beginning
with 0. It is supposed the biggest Fibbonaci number smaller than 232 in unknown at the design
time.
Problem 4.4 To the previously designed machine add a new feature: an additional output
generating the index of the current Fibbonaci number.
4.6
Projects
Project 4.1
Chapter 5
OUR FINAL TARGET

a new, loop based taxonomy was introduced. Because each newly added loop increases the autonomy of
the system, results a functional circuit hierarchy:
history free, no-loop, combinational circuits performing logic and arithmetic functions (decoders,
multiplexors, adders, comparators, ...)
one-loop circuits used mainly as storage support (registers, random access memories, register les,
shift registers, ...)
two-loop, automata circuits used for recognition, generation, control, in simple (counters, ...) or
complex (nite automata) embodiments
three-loop, processors systems: the simplest information & circuit entanglement used to perform
complex functions
four-loop, computing machines: the simplest digital systems able to perform complex programmable
functions, because of the segregation between the simple structure of the circuit and the complex
content of the program memory
...
In this chapter
a very simple programmable circuit, called toyMachine, is described using the shortest
Verilog description which can be synthesized using the current tools. It is used to delimit
the list of circuits that must be taught for undergraduates students. This version of a
programmable circuit is selected because:
its physical implementation contains only the basic structures involved in dening a
digital system
it is a very small & simple entangler structure of circuits & information used for
dening, designing and building a digital system with a given transfer function
it has a well weighted complexity so as, after describing all the basic circuits, an
enough meaningful structure can be synthesized.
In the next chapter
starts the second part of this book which describes digital circuits closing a new loop after each chapter.
It starts with the chapter about no-loop digital circuits, discussing about:
simple (and large sized) uniform combinational circuits, easy to be described using a recursive pattern
complex and size limited random combinational circuits, whose descriptions size is in the same range
with their size
91
92
CHAPTER 5. OUR FINAL TARGET
We must do away with all explanation, and description alone must take its place. . . . The problems are
solved, not by giving new information, but by arranging what we have always known.
Ludwig Wittgenstein
Before proceeding to accomplish our targeted project

we must describe it using what we have always
known.
Our nal target, for these lessons on Digital Design, is described in this chapter as an
architecture. The term is borrowed from builders. They use it to dene the external view and
the functionality of a building. Similarly, in computer science the term of architecture denotes
the external connections and the functions performed by a computing machine. The architecture
does not tell anything about how the dened functionality is actually implemented inside the
system. Usually there are multiple possible solutions for a given architecture.
The way from what to how is the content of the next part of this book. The architecture
we will describe here states what we intend to do, while for learning how to do, we must know a
lot about simple circuits and the way they can be put together in order to obtain more complex
functions.
5.1
toyMachine: a small & simple computing machine
The architecture of one of the simplest meaningful machine will be dened by (1) its external
connections, (2) its internal state and (3) its transition functions. The transition functions
refer to how both, the internal state (the function f from the general denition) and the outputs
(the function g from the general denition) switch.
Let us call the proposed system toyMachine. It has 16 1-bit general purpose inputs,
gpi[15:0], and 16 1-bit general purpose outputs, gpo[15:0]. The interrupt input, int, is
an intrusive signal used to trigger a special event; it is acknowledged by activating the
output inta. The input reset is activated to initialize the system.
The transition function is given by the program stored in a x (read only) memory called
Program Memory (reg[15:0] programMemory[0:1023]). In each clock cycle toyMachine
receives the values applied on gpi. The program decides when (1) a new state of the machine is
computed and, if needed, (2) the outputs are actualized. Thus, the outputs gpo evolve according
to the inputs of the machine and according to the history stored in its internal state.
The internal state of the machine is stored in the following storage subsystems:
program counter (reg[9:0] pc) points in the program memory to the currently executed instruction; the reset signal sets its value to zero; during the execution of each
instruction its content is modied in order to read the next instruction
register le (reg[15:0] regFile[0:7]) contains a small number of register used to store
the most frequently used variables involved in each stage of the computation
1
From Witgensteins Philosophical Investigation (#109). His own very original approach looked for an alternative way to the two main streams of the 20th Century philosophy: one originated in Freges formal positivism,
and another in Husserls phenomenology. Wittgenstein can be considered as a forerunner of the architectural
approach, his vision being far beyond his contemporary fellows were able to understand.
5.1. TOYMACHINE: A SMALL & SIMPLE COMPUTING MACHINE
93
interrupt enable register (intEnable) is a 1-bit register used to enable the interrupt
signal to do its job; the reset signal sets it on 0, disabling the interrupt signal.
The content of the above listed storage devices is processed using combinational circuits, whose
functionality will be specied in this section using a Verilog behavioral description. At the end
of the next part of this book we will be able to synthesize the overall system using a Verilog
structural description. The image of the machine in this stage is represented in Figure 5.1.
gpi[15:0]
int
clock
reset
?
?
syncGpi
regFile
gpo
gpo[15:0]
- progCounter

Combinational Logic
I-
- programMemory
intEnable
inta
Figure 5.1: The internal state of toyMachine.

Each location in the program memory contains one 16-bit instruction organized in three
formats, as follows:
instruction =
where:
{opCode[4:0], op2[2:0], 2bxx, op1[2:0], op0[2:0]} |

{opCode[4:0], value[7:0], op0[2:0]}
|
{opCode[4:0], condSel[3:0], jmpAddr[6:0]}
;
opCode[4:0] :
op0[2:0]
:
op1[2:0]
:
op2[2:0]
:
value[7:0] :
cond[3:0]
:
jmpAddr[6:0]:
operation code
selects the destination in the register file
selects the left operand from the register file
selects the right operand from the register file
immediate value
selects the jump condition
signed jump for conditioned relative jump
The actual content of the rst eld pCode[4:0] determines how the rest of the instruction
is interpreted, i.e., what kind of instruction format has the current instruction. The rst format
applies the operation coded by opCode to the values selected by op1 and op2 from the le
register; the result is stored in le register to the location selected by op0. The second format
stores the value at op0 in dierent forms. The third format performs conditioned (by the
condition selected with cond) jumps relative to pc with the signed value jmpAddr.
The signal int acts, only if intEnable = 1, as follows:
begin
end
regFile[6]
pc
<= {6b0, pc}

; // one-level stack
<= regFile[7][9:0];
94
The location regFile[6] is loaded with the current value of pc when the interrupt is acknowledged, and the content of regFile[7] is loaded as the next program counter, i.e., the
register 7 contains the address of the routine started by the occurrence of the interrupt when it
is acknowledged. The content of regFile[6] will be used to restore the state of the machine
when the program started by the acknowledged signal int ends.
parameter
nop
jmp
zjmp
nzjmp
bjmp
nbjmp
ei
di
halt
add
sub
ashr
neg
bwand
bwor
bwxor
val
hval
get
send
= 5b00000, //
//
= 5b00001, //
= 5b00010, //
//
= 5b00011, //
//
= 5b00100, //
//
= 5b00101, //
//
= 5b00110, //
= 5b00111, //
= 5b01000, //
//
//
= 5b10000, //
= 5b10001, //
= 5b10010, //
= 5b10100, //
= 5b10101, //
= 5b10110, //
= 5b10111, //
= 5b11000, //
= 5b11001, //
//
= 5b11011, //
= 5b11100; //
pc = pc + 1
CONTROL INSTRUCTIONS
pc = rf[op1]
if (rf[cond[3:1]] = 0) pc = pc + jmpAddr[6:0]
else
pc = pc + 1
if (rf[cond[3:1]] != 0) pc = pc + jmpAddr[6:0]
else
pc = pc + 1
if (syncGpi[cond] = 0) pc = pc + jmpAddr[6:0]
else
pc = pc + 1
if (syncGpi[cond] != 0) pc = pc + jmpAddr[6:0]
else
pc = pc + 1
pc = pc + 1, intEnable = 1
pc = pc + 1, intEnable = 0
pc = pc
DATA INSTRUCTIONS: pc = pc + 1
Arithmetic & logic instructions
rf[op0] = rf[op1] + rf[op2]
rf[op0] = rf[op1] - rf[op2]
rf[op0] = {rf[op1][15], rf[op1][15:1]}
rf[op0] = ~rf[op1]
rf[op0] = rf[op1] & rf[op2]
rf[op0] = rf[op1] | rf[op2]
rf[op0] = rf[op1] ^ rf[op2]
rf[op0] = {8*value[7], value}
rf[op0] = {value, 8b0000_0000}
Input output instructions
rf[op0] = syncGpi
gpo = rf[op1]
Figure 5.2: toyMachines ISA dened by the le 0 toyMachineArchitecture.v.

The Instruction Set Architecture (ISA) of toyMachine is described in Figure 5.2 (it is
the executable part of the le toyMachineArchitecture.v), where there are listed two subset
of instructions:
control instructions: used to control the program ow by dierent kinds of jumps performed
conditioned, unconditioned or triggered by an interrupt
data instructions: used to modify the content of the le register, or to exchange data with
the external systems (each execution is accompanied with pc = pc + 1).
The le is manly used to specify opCode, the binary codes associated with each instruction.
The detailed description of each instruction is given by the Verilog behavioral description of
toyMachine (see Figure 5.3).
The description of toyMachine starts with a structural detail: the input register, syncGpi,
used to synchronize the inputs gpi.
The initial in Figure 5.3 is used to initialize the content of the program memory with the
program stored in binary form in the le 0 programMemory.v (an example for the content of
this le is given in Figure 5.10).
95
The rst include includes the binary codes dened in 0 toyMachineArchitecture.v (see
Figure 5.2) for each instruction executed by our simple machine.
module toyMachine( input
output
input
output
input
input
reg
reg
reg
reg
reg
[15:0]
[9:0]
[15:0]
[15:0]
[15:0]
reg [15:0]
programMemory[0:1023];
pc
;
regFile[0:7]
;
intEnable
;
syncGpi
;
int
inta
gpi
gpo
reset
clock
//
//
//
//
//
,
,
,
,
,
);
//
//
//
//
interrupt
interrupt acknowledge
general purpose inputs
general purpose outputs
program read only memory

program counter: points in programMemory
contains the most used varaibles
interrupt enable one-bit register
synchronized gpi
always @(posedge clock) syncGpi <= gpi; // syncronizing the gpi inputs
initial $readmemb("0_programMemory.v", programMemory);
include "0_toyMachineArchitecture.v"
include "instructionStructure.v"
include "controlFunction.v"
include "dataFunction.v"
endmodule
Figure 5.3: The le toyMachine.v containing the toyMachines behavioral description.

The second include includes the le used to describe how the instruction elds are structured.
The last two include lines include the behavioral description for the two subset of instructions performed by our simple machine. These last two les reect the ignorance of the reader
in the domain of digital circuits. They are designed to express only what the designer intent to
build, but she/he doesnt know yet how to do what must be done. The good news: the resulting description can be synthesized. The bad news: the resulting structure is very big (far from
optimal) and has a very complex form, i.e., no pattern can be emphasized. In order to provide
a small & simple circuit, in the next part of this book we will learn how to segregate the simple
part from the complex part of the circuits used to provide an optimal actual structure. Then,
we will learn how to optimize both, the simple, pattern-dominated circuits and the complex,
pattern-less ones.
The le instructionStructure.v denes the elds of the instruction. For all the three
form of the instruction appropriate elds are provided, i.e., the instruction content is divided in
many forms, thus allowing dierent interpretation of it.
In Figure 5.4 the rst assign teaches us about how the instruction code is accessed in
the program memory using as pointer the value contained in the program counter register, pc.
The following lines dene the meaning of each elds of the instruction. For example, the most
signicant 5 bits are used to code the operation performed by the instruction. Some bits have
many meanings. Their meaning depends on the operation performed by the given instruction.
The le controlFunction.v (see Figure 5.5) describes the behavior of the control instructions.The control of toyMachine refers to both, interrupt mechanism and program ow mechanism.
The interrupt signal int is acknowledged, activating the signal inta if intEnable = 1 (see
the assign on the rst line in Figure 5.5). Initially, the interrupt is not allowed to act: reset
96

wire
wire
wire
wire
wire
wire
wire
wire
[15:0]
[4:0]
[2:0]
[2:0]
[2:0]
[7:0]
[6:0]
[3:0]
instruction;
opCode
;
op0
;
op1
;
op2
;
value
;
jmpAddr
;
bitSel
;
assign instruction
opCode
op0
op1
op2
value
jmpAddr
cond
=
=
=
=
=
=
=
=
//
//
//
//
//
//
//
//
the instruction code

operation code
the address of the operand 0 (destination)
the address of the operand 1 (left operand)
the address of the operand 2 (right operand)
the immediate value
the signed jump address
the selection code for testing the state
programMemory[pc] ,
instruction[15:11],
instruction[2:0] ,
instruction[5:3] ,
instruction[10:8] ,
instruction[10:3] ,
instruction[6:0] ,
instruction[10:7] ;
Figure 5.4: The le instructionStructure.v.

signal forces intEnable = 0. The program decides when the system is prepared to accept
interrupts. Then, the instruction ei (enable interrupt) is programmed and intEnable = 0.
When an interrupt is acknowledged, the interrupt is disabled, letting the program decide when
another interrupt is welcomed. The interrupt is disabled by executing the instruction di
disable interrupt.
The program ow is controlled mainly by unconditioned and conditioned jump instructions.
The value of the program counter, pc, is by default incremented with 1, but when a control
instruction is executed its value can be incremented with a signed integer. If the jump is
conditioned, then the condition is selected by the cond code from the syncGpi register or from
the register le. The program control instructions are:
jmp : absolute jump with the value selected from the register le by the eld op1; the register
pc takes the value contained in the selected register
zjmp : relative jump with the signed value jmpAddr[6:0] if the content of the register selected
by cond[3:1] from the register le is 0, else pc = + 1
nzjmp : relative jump with the signed value jmpAddr[6:0] if the content of the register selected
by cond[3:1] from the register le is not 0, else pc = + 1
bjmp : relative jump with the signed value jmpAddr[6:0] if the the value selected by cond
from syncGpi is 1, else pc = + 1
nbjmp : relative jump with the signed value jmpAddr[6:0] if the the value selected by cond
from syncGpi is 0, else pc = + 1
halt : the program execution halts, pc = pc (it is a sort of nop instruction without incrementing
the register pc).
Warning! If intEnable = 0 when the instruction halt is executed, then the overall system
is blocked. The only way to turn it back to life is to activate the reset signal.
The le dataFunction.v (see Figure 5.6) describes the behavior of the data instructions. The
signal inta has the highest priority. It forces the register 6 of the register le to store the current
state of the register pc. It will be used to continue the program, interrupted by the acknowledged
interrupt signal int, by executing a jmp instruction with the content of regFile[6].
The following data instructions are described in this le:

assign inta = intEnable & int;
else if (inta)
else if (opCode == ei)
else if (opCode == di)
if (reset)pc <= 0;
else if (inta)
pc <= regFile[7][9:0]
else case(opCode)
jmp :
pc <= regFile[op2][9:0]
zjmp : if (regFile[cond[3:1] == 0)
pc <= pc + {{3{jmpAddr[6]}},
else pc <= pc + 1
nzjmp: if (regFile[cond[3:1] !== 0)
pc <= pc + {{3{jmpAddr[6]}},
else pc <= pc + 1
bjmp : if (syncGpi[cond] == 1)
pc <= pc + {{3{jmpAddr[6]}},
else pc <= pc + 1
nbjmp: if (syncGpi[cond] == 0)
pc <= pc + {{3{jmpAddr[6]}},
else pc <= pc + 1
halt :
pc <= pc
default
pc <= pc + 1
endcase
97
intEnable
intEnable
intEnable
intEnable
<=
<=
<=
<=
0;
0;
1;
0;
;
;
jmpAddr};
;
jmpAddr};
;
jmpAddr};
;
jmpAddr};
;
;
;
Figure 5.5: The le controlFunction.v.

add : the content of the registers selected by op1 and op2 is added, the result is stored in the
register selected by op0
sub : the content of the register selected by op2 is subtracted form the content of the register
selected by op2, the result is stored in the register selected by op0
ashr : the content of the register selected by op1 is arithmetically shifted right one position
and stored in the register selected by op0
neg : every bit contained in the register selected by op1 are inverted and the result is stored in
the register selected by op0
bwand : the content of the register selected by op2 is AND-ed bit-by-bit with the content of
the register selected by op2 and the result is stored in the register selected by op0
bwor : the content of the register selected by op2 is OR-ed bit-by-bit with the content of the
register selected by op2 and the result is stored in the register selected by op0
bwxor : the content of the register selected by op2 is XOR-ed bit-by-bit with the content of
the register selected by op2 and the result is stored in the register selected by op0
val : the register selected by op0 is loaded with the signed integer specied in the eld value
of the current instruction
hval : the signed integer specied in the eld value of the current instruction multiplied with
28 is stored in the register selected by op0
get : the register selected by op0 are loaded with the gpi bits
send : the gpo register is loaded with the content of the register selected by op1
98

if (inta)
regFile[6]
else
case(opCode)
add : regFile[op0]
sub : regFile[op0]
ashr : regFile[op0]
neg : regFile[op0]
bwand: regFile[op0]
bwor : regFile[op0]
bwxor: regFile[op0]
val : regFile[op0]
hval : regFile[op0]
get : regFile[op0]
send : gpo
default regFile[0]
endcase
<= {6b00, pc}
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
regFile[op1] + regFile[op2]
;
regFile[op1] - regFile[op2]
;
{regFile[op1][15], regFile[op1][15:1]};
~regFile[op1]
;
regFile[op1] & regFile[op2]
;
regFile[op1] | regFile[op2]
;
regFile[op1] ^ regFile[op2]
;
{{8{value[7]}}, value}
;
{value, 8b00000000}
;
syncGpi
;
regFile[op1]
;
regFile[0]
;
Figure 5.6: The le dataFunction.v.
5.2
How toyMachine works
The simplest, but not the easiest way to use toyMachine is to program it in machine language2 , i.e., to write programs as sequence of binary coded instructions stored in programMemory
starting from the address 0.
The general way to solve digital problems using toyMachine, or a similar device, is (1)
to dene the input stream, (2) the output stream, and (3) the program which transforms the
input stream into the corresponding output stream. Usually, we suppose an input signal which
is sampled at a program controlled rate, and the results is an output stream of samples which
is interpreted as the output signal. The transfer function of the system is programmed in the
binary sequence of instructions stored in the program memory.
The above described method to implement a digital system is called programmed logic,
because a general purpose programmable machine is used to implement a certain function which
generate an output stream of data starting from an input stream of data. The main advantage
of this method is its exibility, while the main disadvantages are the reduced speed and the
increased size. If the complexity, price and time to market issue are important, then it can be
the best solution.
Example 5.1 Using toyMachine is provided a programmed logic implementation for the function called delayAdd.
The function delayedAdd(< X >) =< Y > receives as input signal a stream of 8-bit positive
integers < X >=< x0 , x1 , x2 , . . . , xi , . . . > and sends out another stream of 9-bit positive integers
< Y >=< y0 , y1 , y2 , . . . , yi , . . . >, where yi = xi + xi+1 , for i = 0, 1, 2, . . .. In Figure 5.7a the
circuit version is represented, while in Figure 5.7b the system connections allowing toyMachine
to perform delayAdd are presented.
The input must be sampled at the maximum rate, allowed by the fastest program designed for
the requested function. The input will be connected to receive on the 8 least signicant bits the
value x (an element of the input stream < X >), and the most signicant 8 bits are connected
to 0. Therefore: gpi[15:0] = {8b0, x[7:0]}. The output values will be sent on the 9 least
signicant bits of gpo. Therefore: y[8:0] = gpo[8:0].
2
The next levels are to use an assembly language or a high level language (for example: C), but these
approaches are beyond our goal.
5.2. HOW TOYMACHINE WORKS
99
clock
clock
rIn
reg
rOut
toyMachine
8
adder
6 -
gpo
gpi
int
inta
no use
reset
a.
no use
-
reset
reset
b.
Figure 5.7: Two implementations for the delayAdd function. a. Direct, circuit implementation. b. Programmed logic implementation using toyMachine.
The logic of the program for delayAdd function suppose to have stored inside the machine two
successive input values, to add them and to send out the result. The logic version of the program
is in Figure 5.8. The program has two sections: (1) an initial linear sequence of instructions
used to start the process (instructions from lines 0 2), and (2) the unending loop used to
provide a new output value (instructions from lines 3 9). The rst section gets two values in
the registers 0 and 1, and adds them in the register 2. The loop starts sending out the content
of the register 2, which is used to store the sum of the last two received input values. Then the
oldest value, stored in reg0, is substituted with a new one, the contents of reg0 and reg1 are
summed in reg2. The content of reg2 is sent out as result. And so on: the oldest value, now
contained in reg1, is refreshed getting a new input value, ... .
0
1
2
3
4
5
6
7
8
9
loop
get 0;
get 1;
add 2, 0,
send 2;
get 0;
add 2, 0,
send 2;
get 1;
add 2, 0,
nbjmp 11,
1;
//
//
//
//
//
get first
get second
add
send
get odd sample
// STARTS LOOP
// UNENDING LOOP
1;
// get even sample
1;
loop;
Figure 5.8: Machine language program for delayAdd: the logic version.
The just described program has a problem. Logically it is correct. But, its temporal behavior
is wrong.
If the clock frequency is fclock , then its period is T = 1/fclock . Then, the program gets each
even sample at 3T after an odd one, and each odd sample at 4T after an even one. Similarly
behaves the output. In order to equalize the time interval between receiving and sending data,
nop instructions must be added.
The actual program stored in the internal read only memory is represented in Figure 5.9.
Few nop instruction are inserted (on lines: 01, 02, 03, 06, 10) in order to equalize both, the
input sampling interval to 4 cycles, and the output rate to the same value. For the ISA of our
machine the number 4 is dictated by the sequence of instructions stored in the lines from 11 to
14 (see Figure 5.9). Therefore, the highest sampling frequency is fsample = fclock /4.
The binary form of the program is in Figure 5.10.
100
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
loop
get 0;
nop;
nop;
nop;
get 1;
add 2, 0, 1;
nop;
send 2;
get 0;
add 2, 0, 1;
nop;
send 2;
get 1;
add 2, 0, 1;
nbmp 11, loop;
// get first
// STARTS LOOP
// get second
// add
// send
// get odd sample
// UNENDING LOOP
// get even sample
Figure 5.9: Machine language program for delayAdd. Improved version to meet the
temporal requirement.
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
11011_000_00_000_000
00000_000_00_000_000
00000_000_00_000_000
00000_000_00_000_000
11011_000_00_000_001
10000_001_00_000_010
00000_000_00_000_000
11100_000_00_010_000
11011_000_00_000_000
10000_001_00_000_010
00000_000_00_000_000
11100_000_00_010_000
11011_000_00_000_001
10000_001_00_000_010
00100_0000_1111001
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
loop
get 0;
nop;
nop;
nop;
get 1;
add 2, 0,
nop;
send 2;
get 0;
add 2, 0,
nop;
send 2;
get 1;
add 2, 0,
nbjmp 11,
1;
1;
1;
loop; // loop = 7 - 14 = -7
Figure 5.10: The binary form of the program for delayAdd.

In order to improve the speed performance of the solution provided in the previous example
the ISA must be improved. Will result a more powerful machine, but also a more expensive one.
Example 5.2 The video-sensor chips are huge circuits with millions of sensors. The weight of chips
with no errors is very low. In order to increase the yield, chips with a small number of isolated defective
sensors are still used in conjunction with a correction mechanism.
Let say that data provided by a defective sensor takes the value 0. When in the stream of data provided
by an 8-bit video-sensor chip the value 0 occurs, then the correction mechanism implemented as a specic
circuit, let us call it interpol, can be used to substitute the supposed wrong values with values obtained
from interpolating in a small neighborhood. The simplest interpolation is to provide in the position of the
erroneous data a value computed as the arithmetic mean between the previous value and the next value.
Therefore, if the value of pi is 0, then it is substituted by (pi1 + pi+1 )/2.
The input stream and the output stream are controlled by special signals allowing a exible ow of
data trough the correction system. Thus, the signal connections of toyMachine (see Figure 5.11) are
the following:
gpi[7:0] = inputPixel[7:0]: 8-bit input receiving the stream of pixel values (the rst value is a
dummy one having the value 8b0111 1111)
gpo[7:0] = outputPixel[7:0]: 8-bit output generating the stream of the corrected pixels.
5.2. HOW TOYMACHINE WORKS
101
clock
outputGet
inputGet
Sub-system
generating
validInput
pixels
inputPixel
no use
gpo[15:10]
gpi[15:10]
Sub-system
using
gpo[9]
gpi[9]
toyMachine
validOutput
gpi[8]
gpo[8]
gpi[7:0]
gpo[7:0]
int
inta reset
no use
outputPixel
pixels
6
reset
Figure 5.11: Programmed logic implementation for the interpol circuit.

gpi[9] = validInput: the value applied on inputPixel is valid; the signal must be acknowledged
by activating inputGet
gpo[9] = inputGet: the current input value is stored inside toyMachine and the input value can
change
gpo[8] = validOutput: the value on outputPixel is a valid one; the signal must be acknowledged
by activating oututGet
gpi[8] = outputGet: the current value on outputPixel was received at its destination
gpi[15:10] = 6b0, gpo[15:10] are unused outputs, int = 0, and inta is unused.
The program is structured to use three sequences of instructions called pseudo-macros3 . The rst,
called input, reads the input dealing with the dialog signals, validInput and inputGet. The second,
called output, controls the output stream dealing with the signals validOutput and outputGet. The
third pseudo-macro tests if the correction is needed, and apply it if necessary.
The pseudo-macro input: The registers 0, 1, and 2 are used to store three successive values of
pixels from the input stream. Then, before receiving a new value, the content of reg1 is moved in reg2
(lines 0 and 1), and the content of reg0 is moved in reg1 (lines 2 and 3). (Two steps are needed to
move data from one register to another, because a move instruction is missing from our ISA.) Now reg0
is ready to receive a new value. On line 4 the program waits the occurrence of validInput. When
validInput = 1, then the input is loaded in reg0 (line 5). The next four instructions are needed to
generate a one clock period pulse on the output inputGet. The last three instructions are used to clean
up the just received data of the 9-th bit which is the ag validInput. Lines 10 and 11 generates reg3 =
16b0000 0000 1111 1111, which ANDed with reg0 (line 12) will let in reg0 only the pixels value.
The pseudo-macro output: The value to be sent as the next pixel is stored in reg1. The gpo
must be loaded with outputPixel and 1 in the 8-th position in order to activate the signal validOutput.
Therefore, line 0 loads in reg3 the value 16b0000 0001 0000 0000, and line 1 adds in the same
register the value of outputPixel. The resulting mixture {flag, value} is sent out in gpo (line 2). In
reg5 is prepared a 16-bit 0 to be used for clearing gpo after receiving outputGet from the destination
sub-system. On line 4 the program waits outputGet = 1, then clears the output register (line 5).
The pseudo-macro compute: This pseudo-macro has two sections: the rst perform the test on
the content of reg1, while the second make the correction if necessary.
On the rst line is tested the value of the register 1. If it is not-zero, then the program jumps to end
because correction is needed no correction. The second part of this pseudo-macro adds in reg1 the values
3
The true macros are used in assembly languages. For this level of machine language a more rudimentary form
of macro is used.
102
// THE PROGRAM
//
0
1
2
3
4
5
6
7
8
9
10
11
12
//
0
1
2
3
4
5
//
0
1
2
3
insert
input
//
insert
input
//
loop
insert
input
//
insert
compute //
insert
output //
zjmp 11, loop;
//
PSEUDO-MACRO: input
define
input
neg 2, 1;
neg 2, 2;
neg 1, 0;
neg 1, 1;
wait1
nbjmp 9, wait1;
get 0;
hval 4, 8b10;
hval 5, 8b0;
send 4;
send 5;
hval 3, 8b1111_1111;
neg 3, 3;
bwand 0, 0, 3;
PSEUDO-MACRO: output
define
output
hval 3, 8b1;
bwor 3, 1, 3;
send 3;
hval 5, 8b0;
wait2
nbjmp 8, wait2;
send 5;
PSEUDO-MACRO: compute
define
compute
nzjmp 1, end;
add 1, 0, 2;
shr 1, 1;
end
nop;
//
receive a dummy pixel

receive the first pixel
receive the current pixel
make the correction if necessary
emit the current pixel
unconditioned jump to loop
for modularity purpose
Figure 5.12: Machine language program for interpol.

from reg0 and reg2 and divides the result by 2. The last nop instruction is imposed by the modularity
of our pour macro-like mechanism.
The actual program stored in the internal program memory (see // THE PROGRAM in Figure 5.12) has
a starting part receiving two input values, followed by an unending (because gpi[11] = 0) loop which
receives a new value, compute the value to be sent out and sends it.
The last example involves the use of interrupt as an independent process involved in transferring data
between two subsystems.
Example 5.3 The 10-bit output of an AD converter is sampled at each nT ns (T is the clock period
expressed in nano-seconds). The number n is a number which changes randomly each time a completely
independent external signal is activated. The circuit performs a randomly timed data transfer. Let us call
it randTrans.
The solution is to use a toyMachine connected as follows:
the 10-bit output of the AD converter is connected to the inputs gpi[9:0]; gpi[11] are connected
to 0
5.3. CONCLUDING ABOUT TOYMACHINE
103
the outputs gpo[9:0] contain the last sampled data

the output gpo[10], called newOut, is activated on 1 for one clock cycle anytime the outputs
gpo[9:0] change
on int is applied the independent signal used to change randomly the value of n
the input int holds until it is acknowledged by activating the output inta on 1 for one clock cycle.
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
time
count
inter
val 5, 8b1;
hval 4, 8b100;
val 7, inter;
val 3, 8b0111_1111;
ei;
neg 2, 3;
neg 2, 2;
sub 2, 2, 5;
nzjmp 2, count;
get 0;
bwor 1, 0, 4;
send 1;
send 0;
nbjmp 11, time;
get 3;
setst, 6;
jmp 6;
//
//
//
//
//
for decrement
// INITALIZE
for newOut
for the interrupt routine
initial constant for counter
enable interrupt
// COUNTING
// TRANSFER
// unending loop because gpi[11] = 0

// INTERRUPT
Figure 5.13: The program for the circuit randTrans.

The program is in Figure 5.13. It has four sections:
INITIALIZE: is the section (from 00 to 03) the register reg5 is set on 1, to be used for decrement
function (decrement function is not included in our too simple ISA); the register reg4 is prepared
to generate the signal newOut by setting only the bit reg4[10] on 1; reg7 is loaded with the absolute
address where the interrupt routine starts (inter = 16); reg3 is loaded with the initial value of
8b0111 1111
COUNTING: loads in reg2 the value of m (lines 04 and 05) and decrement it until reg2 = 0 (lines
06 and 07);
TRANSFER: the input is read in reg0; in reg1 to the read data is OR-ed the newOut bit; the received
data is sent out accompanied by the newOut bit, then next clock cycle only the read data is sent on
output connections; the program jumps to the counting section
INTERRUPT: the routine (lines 13 to 16) is executed only when an interrupt is acknowledged; the
value in reg3 is updated using the value found on the input; the interrupt is enabled and the control
of the program is sent back to the instruction accessed when the interrupt occurred (line 16).
Because, the interrupt signal is independent from the evolution of the input signal generated by the AD
converter, the value received on line 14 could be considered a random one.
5.3
Concluding about toyMachine
Our nal target is to be able to describe the actual structure of toyMachine using as much
as possible simple circuits. Maybe we just catched a glimpse about the circuits we must learn how
to design. It is almost obvious that the following circuits are useful for building toyMachine:
adders, subtractors, increment circuits, selection circuits, various logic circuits, registers, leregisters, memories, read-only memories (for x program memory). The next chapters present
detailed descriptions of all above circuits, and a little more.
104
The behavioral description of toyMachine is synthesisable, but the resulting structure

is too big and has a completely unstructured shape. The size increases the price, and the lack
of structure make impossible any optimization of area, of speed or of the energy consumption.
The main advantages of the just presented behavioral description is its simplicity, and the
possibility to use it as a more credible witness when the structural description will be veried.
Pros & cons for programmed logic
it is a very exible tool, but can not provide hi-performance solutions

very good time to market, but not for mass production
good for simple one chip solution, but not to be integrated as an IP on a complex SoC
solution
5.4
Problems
Problem 5.1 Write for toyMachine the program which follows-up as fast as possible by the
value on gpo[4:0] the number of 1s on the inputs gpi.
Problem 5.2 Redesign the interpol circuit for the interpolation rule:
pi = 0.2 pi2 + 0.3 pi1 + 0.3 pi+1 + 0.2 pi+2
Problem 5.3 Add a new instruction to the ISA of toyMachine in order to increase the frequency of the sampling rate for the circuit delayAdd.
5.5
Projects
Project 5.1 Design the test environment for toyMachine, and use it to test the examples from
this chapter.
Part II
LOOPING IN THE DIGITAL

DOMAIN
105
Chapter 6
GATES:
Zero order, no-loop digital systems
ended the rst part of this book, where we learned to talk in the Verilog HDL about
how to build big systems composing circuits and smaller systems, how to accelerate the
computation in a lazy system, and how to increase the autonomy of a system closing
appropriate loops. Where introduced the following basic concepts:
serial, parallel, and serial-parallel compositions used to increase the size of a digital
system, maintaining the functional capabilities at the same level
data (synchronic) parallelism and time (diachronic) parallelism (the pipeline connection) as the basic mechanism to improve the speed of processing in digital systems
included loops, whose eect of limiting the time parallelism is avoided by speculating
the third form of parallelism, usually ignored in the development of the parallel
architectures
classifying digital circuits in orders, the n-th order containing circuits with n levels
of embedded loops
The last chapter of the rst part denes the architecture of the machine whose components
will be described in the second part of this book.
In this chapter
the zero order, no-loop circuits are presented with emphasis on:
how to expand the size of a basic combinational circuit
the distinction between simple and complex combinatorial circuits
how to deal with the complexity of combinatorial circuits using programmable
devices
In the next chapter
the rst order, memory circuits are introduced presenting
how a simple loop allows the occurrence of the memory function
the basic memory circuits: elementary lathes, clocked latches, master-slave ip-ops
memories and registers as basic systems composed using the basic memory circuits
107
108
CHAPTER 6. GATES:
ZERO ORDER, NO-LOOP DIGITAL SYSTEMS
Belief #5: That qualitative as well as quantitative aspects of information systems will be
accelerated by Moores Law. . . . In the minds
of some of my colleagues, all you have to do
is identify one layer in a cybernetic system
thats capable of fast change and then wait for
Moores Law to work its magic.
Jaron Lanier1
The Moores Law applies to size not to complexity.
In this chapter we will forget for the moment about loops. Composition is the only mechanism
involved in building a combinational digital system. No-loop circuits generate the class of history
free digital systems whose outputs depend only by the current input variables, and are reassigned
continuously at each change of inputs. Anytime the output results as a specic combination
of inputs. No autonomy in combinational circuits, whose outputs obey not to say a word to
inputs.
The combinational functions with n 1-bit inputs and m 1-bit outputs are called Boolean
function and they have the following form:
f : {0, 1}n {0, 1}m .
For n = 1 only the NOT function is meaningful in the set of the 4 one-input Boolean functions.
For n = 2 from the set of 16 dierent functions only few functions are currently used: AND, OR,
XOR, NAND, NOR, NXOR. Starting with n = 3 the functions are dened only by composing
2-input functions. (For a short refresh see Appendix Boolean functions.)
Composing small gates results big systems. The growing process was governed in the last
40 years by Moores Law2 . For a few more decades maybe the same growing law will act.
But, starting from millions of gates per chip, it is very important what kind of circuits grow
exponentially!
Composing gates results two kinds of big circuits. Some of them are structured following
some repetitive patterns, thus providing simple circuits. Others grow patternless, providing
complex circuits.
6.1
Simple, Recursive Dened Circuits
The rst circuits used by designers were small and simple. When they were grew a little they
were called big or complex. But, now when they are huge we must talk, more carefully, about
big sized simple circuits or about big sized complex circuits. In this section we will talk about
simple circuits which can be actualized at any size, i.e., their denitions dont depend by the
number, n, of their inputs.
n
In the class of n-inputs circuits there are 22 distinct circuits. From this tremendous huge
number of logical function we use currently an insignicant small number of simple functions.
What is strange is that these functions are sucient for almost all the problem which we are
confronted (or we are limited to be confronted).
1
2
Jaron Lanier coined the term virtual reality. He is a computer scientist and a musician.
The Moores Law says the physical performances in microelectronics improve exponentially in time.
6.1. SIMPLE, RECURSIVE DEFINED CIRCUITS
109
One fact is clear: we can not design very big complex circuits because we can not specify
them. The complexity must get away in another place (we will see that this place is the world
of symbols). If we need big circuit they must remain simple.
In this section we deal with simple, if needed big, circuits and in the next with the complex
circuits, but only with ones having small size.
From the class of the simple circuits we will present only some very usual such as decoders,
demultiplexors, multiplexors, adders and arithmetic-logic units. There are many other interesting
and useful functions. Many of them are proposed as problems at the end of this chapter.
6.1.1
Decoders
The simplest problem to be solved with a combinational logic circuit (CLC) is to answer the
question: what is the value applied to the input of this one-input circuit?. The circuit which
solves this problem is an elementary decoder (EDCD). It is a decoder because decodes its onebit input value by activating distinct outputs for the two possible input values. It is elementary
because does this for the smallest input word: the one-bit word. By decoding, the value applied
to the input of the circuit is emphasized activating distinct signals (like lighting only one of n
bulbs). This is one of the main functions in a digital system. Before generating an answer to
the applied signal, the circuit must know what signal arrived on its inputs.
Informal denition
The n-input decoder circuit DCDn (see Figure 6.1) performs one of the basic function in
digital systems: with one of its m one-bit outputs species the binary conguration applied
on its inputs. The binary number applied on the inputs of DCDn takes values in the set
X = {0, 1, ...2n 1}. For each of these values there is one output y0 , y1 , ...ym1 which is
activated on 1 if its index corresponds with the current input value. If, for example, the input
of a DCD4 takes value 1010, then y10 = 1 and the rest 15 one-bit outputs take the value 0.
- x0
- x1
...
- xn1
DCDn
y0 y1
? ?
...
ym1
Figure 6.1: The n-input decoder (DCDn ).
Formal denition
In order to rigorously describe and to synthesize a decoder circuit a formal denition is requested.
Using Verilog HDL, such a denition is very compact certifying the non-complexity of this circuit.
Denition 6.1 DCDn is a combinational circuit with the n-bit input X, xn1 , . . . , x0 , and the
m-bit output Y , ym1 , . . . , y0 , where: m = 2n , with the behavioral Verilog description:
module dec #(parameter inDim = n)(input [inDim - 1:0]
sel,
output [(1 << inDim) - 1:0] out);
assign out = 1 << sel;
endmodule
110
CHAPTER 6. GATES:
The previous Verilog description is synthesisable by the current software tools which provide
an ecient solution. It happens because this function is simple and it is frequently used in
designing digital systems.
Recursive denition
The decoder circuit DCDn for any n can be dened recursively in two steps:
dening the elementary decoder circuit (EDCD = DCD1 ) as the smallest circuit performing the decode function
applying the divide & impera rule in order to provide the DCDn circuit using DCDn/2
circuits.
For the rst step EDCD is dened as one of the simplest and smallest logical circuits.
Two one-input logical function are used to perform the decoding. Indeed, parallel composing
(see Figure 6.2a) the circuits performing the simplest functions: f21 (x0 ) = y1 = x0 (identity
function) and f11 (x0 ) = y0 = x0 (NOT function), we obtain an (EDCD). If the output y0 is
active, it means the input is zero. If the output y1 is active, then the input has the value 1.
x0
x0
y1
y0
y1
y0
EDCD
a.
b.
Figure 6.2: The elementary decoder (EDCD). a. The basic circuit. b. Buered EDCD, a
serial-parallel composition.
In order to isolate the output from the input the buered EDCD version is considered serial
composing an additional inverter with the previous circuit (see Figure 6.2b). Hence, the fan-out
of EDCD does not depend on the fan-out of the circuit that drives the input.
y0
y0
y1
yp1
y1
DCDn/2
yp
yp1
6
ym1
n/2
n
n/2
y0
yp1
y1
DCDn/2
xn1 . . . x0
Figure 6.3: The recursive denition of n-inputs decoder (DCDn ). Two DCDn/2 are used
to drive a two dimension array of AN D2 gates. The same rule is applied for the two DCDn/2 , and so on
until DCD1 = EDCD is needed.
The second step is to answer the question about how can be build a (DCDn ) for decoding
an n-bit input word.
111
Denition 6.2 The structure of DCDn is recursive dened by the rule represented in Figure
6.3. The DCD1 is an EDCD (see Figure 6.2b).
The previous denition is a constructive one, because provide an algorithm to construct a
decoder for any n. It falls into the class of the divide & impera algorithms which reduce the
solution of the problem for n to the solution of the same problem for n/2.
The quantitative evaluation of DCDn oers the following results:
Size: GSDCD (n) = 2n GSAN D (2) + 2GSDCD (n/2) = 2(2n + GSDCD (n/2))
GSDCD (1) = GSEDCD = 2
GSDCD (n) O(2n )
Depth: DDCD (n) = DAN D (2) + DDCD (n/2) = 1 + DDCD (n/2) O(log n)
DDCD (1) = DEDCD = 2
Complexity: CDCD O(1) because the denition occupies a constant drown area (Figure 6.3)
or a constant number of symbols in the Verilog description for any n.
The size, the complexity and the depth of this version of decoder is out of discussion because
the order of the size can not be reduced under the number of outputs (m = 2n ), for complexity
O(1) is the minimal order of magnitude, and for depth O(log n) is optimal takeing into account
we applied the divide & impera rule to build the structure of the decoder.
Structural description
The current HDLs, such as VHDL and Verilog, do not support recursive descriptions. Therefore,
for structural descriptions, when the behavioral ones do not provide an appropriate solution,
the recursive denition must be translated into an iterative one.
x0
x1
xn1
...
y0
...
y1
...
ym1
Figure 6.4: Constant depth DCD Applying the associative rule into the hierarchical network of
AN D2 gates results the one level AN Dn gates circuit driven by n EDCDs.
An iterative structural version of the previous recursive constructive denition is possible,
because the outputs of the two DCDn/2 from Figure 6.3 are also 2-input AND circuits, the same
as the circuits on the output level. In this case we can apply the associative rule, implementing
the last two levels by only one level of 4-input ANDs. And so on, until the output level of the
2n n-input ANDs is driven by n EDCDs. Now we have the decoder represented in Figure 6.4).
Apparently it is a constant depth circuit, but if we take into account that the number of inputs
in the AND gates is not constant, then the depth is given by the depth of an n-input gate which
is in O(log n). Indeed, an n-input AND has an ecient implementation as as a binary tree of
2-input ANDs.
This constant depth DCD version CDDCD is faster than the previous for small values
of n (usually for n < 6; for more details see Appendix Basic circuits), but the size becomes
112
CHAPTER 6. GATES:
SCDDCD (n) = n 2n + 2n O(n2n ). The price is over-dimensioned related to the gain, but for
small circuits sometimes it can be accepted.
The pure structural description for DCD3 is:
module dec3(output [7:0] out,
input [2:0] in );
// internal connections
wire in0, nin0, in1, nin1, in2, nin2;
// EDCD for in[0]
not not00(nin0, in[0]);
not not01(in0, nin0) ;
// EDCD for in[1]
// EDCD for in[2]
// the second level
and and0(out[0], nin2, nin1, nin0); //
and and1(out[1], nin2, nin1, in0 ); //
and and2(out[2], nin2, in1, nin0); //
and and3(out[3], nin2, in1, in0 ); //
and and4(out[4], in2, nin1, nin0); //
and and5(out[5], in2, nin1, in0 ); //
and and6(out[6], in2, in1, nin0); //
and and7(out[7], in2, in1, in0 ); //
endmodule
output
output
output
output
output
output
output
output
0
1
2
3
4
5
6
7
For n = 3 the size of this iterative version is identical with the size which results from the
recursive denition. There are meaningful dierences only for big n. In real designs we do not
need this kind of pure structural descriptions because the current synthesis tools manage very
well even pure behavioral descriptions such that from the formal denition of the decoder.
Arithmetic interpretation
The decoder circuit is also an arithmetic circuit. It computes the numerical function of exponentiation: Y = 2X . Indeed, for n = i only the output yi takes the value 1 and the rest of the
outputs take the value 0. Then, the number represented by the binary conguration Y is 2i .
Application
Because the expressions describing the m outputs of DCDn are:
y0 = xn1 xn2 . . . x1 x0
y1 = xn1 xn2 . . . x1 x0
y2 = xn1 xn2 . . . x1 x0
...
ym2 = xn1 xn2 . . . x1 x0
ym1 = xn1 xn2 . . . x1 x0
the logic interpretation of these outputs is that they represent all the min-terms for an n-input
function. Therefore, any n-input logic function can be implemented using a DCDn and an OR
with maximum m 1 inputs.
113
Example 6.1 Let be the 3-input 2-output function dened in the table from Figure 6.5. A
DCD3 is used to compute all the min-terms of the 3 variables a, b, and c. A 3-input OR is used
to add the min-terms for the function X, and a 4-input OR is used to add the min-terms
for the function Y.
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
0
X
0
1
0
0
0
1
1
0
Y
1
1
0
1
0
0
1
0
c
b
a
- x0
- x1
- x2
DCD3
y0 y1 y2 y3 y4 y5 y6 y7
X
Figure 6.5:
Each min-term is computed only once, but it can be used as many times as the implemented
functions suppose.
6.1.2
Demultiplexors
The structure of the decoder is included in the structure of the other usual circuits. Two of them
are the demultiplexor circuit and the multiplexer circuit. These complementary functions are
very important in digital systems because of their ability to perform communication functions.
Indeed, demultiplexing means to spread a signal from a source to many destinations, selected
by a binary code and multiplexing means the reverse operation to catch signals from distinct
sources also selected using a selection code. Inside of both circuits there is a decoder used to
identify the source of the signal or the destination of the signal by decoding the selection code.
Informal denition
The rst informally described solution for implementing the function of an n-input demultiplexor
is to use a decoder with the same number of inputs and m 2-input NAND connected as in Figure
6.6. The value of the input E is generated to the output of the gate opened by the activated
output of the decoder DCDn . It is obvious that an inverted outputs DCDn is a DM U Xn with
E = 0. Therefore, the size, depth of DMUXs are the same as for DCDs, because the depth is
incremented by 1 and to the size is added a value which is in O(2n ).
For example, if on the selection input X = s, then the outputs yi take the value 1 for i = s
and ys = E . The inactive value on the inverted outputs of this DMEX is 1.
Formal denition
Denition 6.3 The n-input demultiplexor DM U Xn is a combinational circuit which transfers the 1-bit signal from the input E to the one of the outputs ym1 , . . . , y0 selected by the n-bit
selection code X = xn1 , . . . , x0 , where m = 2n . It has the following behavioral Verilog description:
module dmux #(parameter inDim = n)(input [inDim - 1:0]
sel
,
input
enable,
output [(1 << inDim) - 1:0] out
);
assign out = enable << sel;
114
CHAPTER 6. GATES:
DCDn
y0
ym1
...
y1
...
ym1
y1
y0
Figure 6.6: Demultiplexor. The n-input demultiplexor (DM U Xn ) includes a DCDn and 2n AN D2
gates used to distribute the input E in 2n dierent places according to the n-bit selection code.
endmodule
The version presented in Figure 6.6, with active on zero enable input and outputs, has the
following description for n = 4:
module dmux #(parameter inDim = 4)(input [inDim - 1:0]
input
output [(1 << inDim) - 1:0]
assign notOut = ~({((1 << inDim) - 1){1b0}}, ~notEnable} <<
endmodule
sel
,
notEnable,
notOut
);
sel);
Recursive denition
The DMUX circuit has also a recursive denition. The smallest DMUX, the elementary DMUX
EDMUX , is a 2-output one, with a one-bit selection input. EDMUX is represented in Figure
6.7. It consists of an EDCD used to select, with its two outputs, the way for the signal E .
Thus, the EDMUX is a circuit that oers the possibility to transfer the same signal (E ) in two
places (y0 and y1 ), according with the selection input (x0 ) (see Figure 6.7.
?
EDCD
x0
y0
y0
a.
x0 EDMUX
y1
y1
b.
Figure 6.7: The elementary demultiplexor. a. The internal structure of an elementary demultiplexor (EDMUX) consists in an elementary decoder, 2 N AN D2 gates, and an inverter circuit as input
buer. b. The logic symbol.
The same rule divide & impera is used to dene an n-input demultiplexor, as follows:
xn1
115
x0
E
EDMUX
y0
y1
xn2 , . . . , x0
n1
E
DM U Xn1
y m
y0
y0
DM U Xn1
y m
y0
...
...
y m
2
y m
2
ym1
Figure 6.8: The recursive denition of DM U Xn . Applying the same rule for the two DM U Xn1
a new level of 2 EDMUXs is added, and the output level is implemented using 4 DM U Xn2 .
And so on until the output level is implemented using 2n1 EDMUXs. The resulting circuit
contains 2n 1 EDMUXs.
Denition 6.4 DM U Xn is dened as the structure represented in Figure 6.8, where the two
DM U Xn1 are used to select the outputs of an EDMUX.
If the recursive rule is applied until the end the resulting circuit is a binary tree of EDMUXs.
It has SDM U X (N ) O(2n ) and DDM U X (n) O(n). If this depth is considered too big for the
current application, the recursive process can be stopped at a convenient level and that level is
implemented with a constant depth DMUXs made using constant depth DCDs. The mixed
procedures are always the best. The previous denition is a suggestion for how to use small
DMUXs to build bigger ones.
6.1.3
Multiplexors
Now about the inverse function of demultiplexing: the multiplexing, i.e., to take a bit of information from a selected place and to send in one place. Instead of spreading by demultiplexing,
now the multiplexing function gathers from many places in one place. Therefore, this function is
also a communication function, allowing the interconnecting between distinct places in a digital
system. In the same time, this circuit is very useful for implementing random, i.e. complex,
logical functions, as we will see at the end of this chapter. More, in the next chapter we will see
that the smallest multiplexor is used to build the basic memory circuits. Looks like this circuit
is one of the most important basic circuit, and we must pay a lot of attention to it.
Informal denition
The direct intuitive implementation of a multiplexor with n selection bits M U Xn starts also
from a DCDn which is now serially connected with an AND-OR structure (see Figure 6.9). The
outputs of the decoder open, for a given input code, only one AND gate that transfers to the
output the corresponding selected input which, by turn, is OR-ed to the output y.
Applying in this structure the associativity rule, for the AND gates to the output of the
decoder and the supplementary added ANDs, results the actual structure of MUX. The structure
AND-OR maintains the size and the depth of MUX in the same orders as for DCD.
Formal denition
As for the previous two circuits DCD and DMUX , we can dene the multiplexer using a
behavioral (functional) description.
116
CHAPTER 6. GATES:
ym1
DCDn
y1
y0
i0
im1
i1
...
6
n
...
xn1 , . . . , x0
...
Figure 6.9: Multiplexer. The n selection inputs multiplexer M U Xn is made serial connecting a
DCDn with an AND-OR structure.
Denition 6.5 A multiplexer M U Xn is a combinational circuit having n selection inputs
xn1 , . . . , x0 that selects to the output y one input from the m = 2n selectable inputs, im1 , . . . , i0 .
The Verilog description is:
module mux #(parameter inDim = n)(input [inDim-1:0]
sel, // selection inputs
input [(1<<inDim)-1:0] in , // selected inputs
output
out);
assign out = in[sel];
endmodule
The MUX is obviously a simple function. Its formal description, for any number of inputs has
a constant size. The previous behavioral description is synthesisable eciently by the current
software tools.
Recursive denition
There is also a rule for composing large MUSs from the smaller ones. As usual, we start from
an elementary structure. The elementary MUX EMUX is a selector that connects the signal
i1 or i0 in y according to the value of the selection signal x0 . The circuit is presented in Figure
6.10a, where an EDCD with the input x0 opens only one of the two ANDs added by the OR
circuit in y. Another version for EMUX uses tristate inverting drivers (see Figure 6.10c).
The denition of M U Xn starts from EMUX, in a recursive manner. This denition will
show us that MUX is also a simple circuit (CM U X (n) O(1)). In the same time this recursive
denition will be a suggestion for the rule that composes big MUXs from the smaller ones.
Denition 6.6 M U Xn can be made by serial connecting two parallel connected M U Xn/2 with
an EMUX (see Figure 6.11 that is part of the denition), and M U X1 = EM U X.
Structural aspects
This denition leads us to a circuit having the size in O(2n ) (very good, because we have m = 2n
inputs to be selected in y) and the depth in O(n). In order to reduce the depth we can apply
i0
117
i1
i0
x0
- x0
i0
i1
i1
EMUX
a.
x0
b.
c.
Figure 6.10: The elementary multiplexer (EMUX). a. The structure of EMUX containing an
EDCD and the smallest AND-OR structure. b. The logic symbol of EMUX. c. A version of EMUX
using transmission gates (see section Basic circuits).
i0
...
im
i m 1
...
i0
i m 1
2
M U Xn1
y
i0
...
im1
...
i m 1
M U Xn1
y
xn2 , . . . , x0
xn1
? ?
i
x0 0
i1
EMUX
y
?y
Figure 6.11: The recursive denition of M U Xn . Each M U Xn1 has a similar denition (two
M U Xn2 and one EMUX), until the entire structure contains EMUXs. The resulting circuit is a binary
tree of 2n 1 EMUXs.
step by step the next procedure: for the rst two levels in the tree of EMUXs we can write the
equation
y = x1 (x0 i3 + x0 i2 ) + x1 (x0 i1 + x0 i0 )
that becomes
y = x1 x0 i3 + x1 x0 i2 + x1 x0 i1 + x1 x0 i0 .
Using this procedure two or more levels (but not too many) of gates can be reduced to one.
Carefully applied this procedure accelerate the speed of the circuit.
Application
Because the logic expression of a n selection inputs multiplexor is:
y = xn1 . . . x1 x0 im1 + . . . + xn1 . . . x1 x0 i1 + xn1 . . . x1 x0 i0
any n-input logic function is specied by the binary vector {im1 , . . . i1 , i0 }. Thus any n input
logic function can be implemented with a M U Xn having on its selected inputs the binary vector
dening it.
118
CHAPTER 6. GATES:
Example 6.2 Let be function X dened in Figure 6.12 by its truth table. The implementation
with a M U X3 means to use the right side of the table as the dening binary vector.
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
0 1 0 0 0 1 1 0
X
0
1
0
0
0
1
1
0
????????
c
b
a
- x0
- x1
- x2
i0 i1 i2 i3 i4 i5 i6 i7
M U X3
y
Figure 6.12:
6.1.4
Shifters
One of the simplest arithmetic circuit is a circuit able to multiply or to divided with a number equal
with a power of 2. The circuit is called also shifter because these operations do not change the relations
between the bits of the number, they change only the position of the bits. The bits are shifted a number
of positions to the left, for multiplication, or to the right for division.
The circuit used for implementing a shifter for n-bit numbers with m 1 positions is an m-input
multiplexor having the selected inputs dened on n bits.
In the previous subsection were dened multiplexors having 1-bit selected inputs. How can be expanded the number of bits of the selected inputs? An elementary multiplexor for p-bit words, pEMUX,
is made using p EMUXs connected in parallel. If the two words to be multiplexed are ap1 , . . . a0 and
bp1 , . . . b0 , then each EMUX is used to multiplex a pair of bits (ai , bi ). The one-bit selection signal is
shared by the p EMUXs. nEMUX is a parallel extension of EMUX.
ap1
bp1
ap2
bp2
a0
b0
yp1
yp2
y0
Figure 6.13: The structure of pEMUX. Because the selection bit is the same for all EMUXs one
EDCD is shared by all of them.
Using pEMUXs an pM U Xn can be designed using the same recursive procedure as for designing
M U Xn starting from EMUXs.
An 2n 1 positions left shifter for p-bit numbers, pLSHIF Tn , is designed connecting the selected
inputs of an pEMUX, i0 , . . . im1 where m = 2n , to the number to be shifted N = {an1 , an2 , . . . a0 }
(ai {0.1} for i = 0, 1, . . . (m 1)) in 2n 1 ways, according to the following rule:
ij = {{anj1 , anj2 , . . . a0 }, {j{0}}}
for: j = 0, 1, . . . (m 1).
119
Example 6.3 For 4LSHIF T2 an 4M U X2 is used. The binary code specifying the shift dimension is
shiftDim[1:0], the number to be shifted is in[3:0], and the ways the selected inputs, in0, in1, in2,
in3, are connected to the number to be shifted are:
in0
in1
in2
in3
=
=
=
=
{in[3],
{in[2],
{in[1],
{in[0],
in[2],
in[1],
in[0],
0
,
in[1],
in[0],
0
,
0
,
in[0]}
0
}
0
}
0
}
Figure 6.14 represents the circuit.

The Verilog description of the shifter is done by instantiating a 4-way 4-bit multiplexor with its inputs
connected according to the previously described rule.
module leftShifter(output [3:0] out
,
input [3:0] in
,
input [1:0] shiftDim);
mux4_4 shiftMux(.out(out
),
.in0(in
),
.in1({in[2:0], 1b0}),
.in2({in[1:0], 2b0}),
.in3({in[0] , 3b0}),
.sel(shiftDim
));
endmodule
in[0]
in[1]
in[2]
in[3]
? ? ? ?
shiftDim
in0
sel
in1 in2
mux4
in3
mux3
out[3]
? ? ? ?
in0
sel
in1 in2
mux4
in3
mux2
out[2]
? ? ? ?
in0
sel
in1 in2
mux4
in3
mux1
out[1]
? ? ? ?
in0
sel
in1 in2
mux4
in3
mux0
out[0]
Figure 6.14: The structure of 4LSHIF T2 , a maximum 3-position, 4-bit number left
shifter.
The multiplexor used in the previous module is built using 3 instantiations of an elementary 4-bit
multiplexors. Results the two level tree of elementary multiplexors interconnected as the following Verilog
code describes.
module mux4_4(output [3:0] out,
input [3:0] in0, in1, in2, in3,
input [1:0] sel); // 4-way 4-bit multiplexor (4MUX_2)
wire[3:0]
out1, out0;
// internal connections between the two levels
mux2_4 mux(out, out0, out1, sel[1]), // output multiplexor
mux1(out1, in2, in3, sel[0]), // input multiplexor for in3 and in2
mux0(out0, in0, in1, sel[0]); // input multiplexor for in1 and in0
endmodule
Any n-bit elementary multiplexer is described by the following parameterized module:
module mux2_4 #(parameter n = 4)(output [n-1:0] out,
input [n-1:0] in0, in1,
input
sel); // 2-way 4-bit mux: 4EMUX
assign out = sel ? in1 : in0; // if (sel) then in1, else in0
endmodule
120
CHAPTER 6. GATES:
The same idea helps us to design a special kind of shifter, called barrel shifter which performs a
rotate operation described by the following rule: if the input number is N = {an1 , an2 , . . . a0 }
(ai {0.1} for i = 0, 1, . . . (m 1)), then rotating it with i positions will provide:
ii = {ani1 , ani2 , . . . a0 , an1 , an2 , . . . ani }
for: i = 0, 1, . . . (m 1). This rst solution for the rotate circuit is very similar with the shift circuit.
The only dierence is: all the inputs of the multiplexor are connected to an input value. No 0s on any
inputs of the multiplexor.
A second solution uses only elementary multiplexors. A version for 8-bit numbers is presented in the
following Verilog code.
module leftRotate(output [7:0] out
,
input [7:0] in
,
input [2:0] rotateDim);
wire [7:0] out0, out1;
mux2_8
level0(.out(out0), .in0(in ), .in1({in[6:0], in[7]} ),
.sel(rotateDim[0])),
level1(.out(out1), .in0(out0), .in1({out0[5:0], out0[7:6]}), .sel(rotateDim[1])),
level2(.out(out ), .in0(out1), .in1({out1[3:0], out1[7:4]}), .sel(rotateDim[2]));
endmodule
module mux2_8(output [7:0] out,
input [7:0] in0, in1,
input
sel);
assign out = sel ? in1 : in0;
endmodule
While the rst solution uses for n bit numbers n M U Xlog2 (rotateDim) , the second solution uses
log2 (rotateDim) nEM U Xs. Results:
Sf irstSolutionOf Lef tRotate = (n (rotateDim 1)) SEM U X
SsecondSolutionOf Lef tRotate = (n log2 (rotateDim)) SEM U X
6.1.5
Priority encoder
An encoder is a circuit which connected to the outputs of a decoder provides the value applied on the
input of the decoder. As we know only one output of a decoder is active at a time. Therefore, the encoder
compute the index of the activated output. But, a real application of an encoder is to encode binary
congurations provided by any kind of circuits. In this case, more than one input can be active and the
encoder must have a well dened behavior. One of this behavior is to encode the most signicant bit and
to ignore the rest of bits. For this reason the encoder is a priority encoder.
The n-bit input, enabled priority encoder circuit, P E(n), receives xn1 , xn2 , . . . x0 and, if the enable
input is activated, en = 1, it generates the number Y = ym1 , ym2 , . . . y0 , with n = 2m , where Y is
the biggest index associated with xi = 1 if any, else zero output is activated. (For example: if en = 1,
for n = 8, and x7 , x6 , . . . x0 = 00110001, then y2 , y1 , y0 = 101 and zero = 0) The following Verilog code
describe the behavior of P E(n).
module priority_encoder #(parameter m = 3)(input
[(1b1<<m)-1:0] in
input
enable
output reg [m-1:0]
out
output reg
zero
integer i;
always @(*) if (enable) begin
out = 0;
for(i=(1b1 << m)-1; i>=0; i=i-1)
if ((out == 0) && in[i]) out = i;
,
,
,
);
121
if (in == 0)
else
end
begin
else
zero = 1;
zero = 0;
out = 0;
zero = 1;
end
endmodule
For testing the previous description the following test module is used:
module test_priority_encoder #(parameter
m = 3);
reg
[(1b1<<m)-1:0]
in
;
reg
enable ;
wire
[m-1:0]
out
;
wire
zero
;
initial
begin
enable = 0;
in = 8b11111111;
#1 enable = 1;
#1 in = 8b00000001;
#1 in = 8b0000001x;
#1 in = 8b000001xx;
#1 in = 8b00001xxx;
#1 in = 8b0001xxxx;
#1 in = 8b001xxxxx;
#1 in = 8b01xxxxxx;
#1 in = 8b1xxxxxxx;
#1 in = 8b110;
#1 $stop;
end
priority_encoder
dut(in
,
enable ,
out
,
zero
);
initial $monitor
($time, "enable=%b in=%b out=%b zero=%b",
enable, in, out, zero);
endmodule
Running the previous code the simulation provides the following result:
time
time
time
time
time
time
time
time
time
time
time
= 0
= 1
= 2
= 3
= 4
= 5
= 6
= 7
= 8
= 9
=10
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
=
=
=
=
=
=
=
=
=
=
=
0
1
1
1
1
1
1
1
1
1
1
in
in
in
in
in
in
in
in
in
in
in
=
=
=
=
=
=
=
=
=
=
=
11111111
11111111
00000001
0000001x
000001xx
00001xxx
0001xxxx
001xxxxx
01xxxxxx
1xxxxxxx
00000110
out
out
out
out
out
out
out
out
out
out
out
=
=
=
=
=
=
=
=
=
=
=
000
111
000
001
010
011
100
101
110
111
010
zero
zero
zero
zero
zero
zero
zero
zero
zero
zero
zero
=
=
=
=
=
=
=
=
=
=
=
1
0
0
0
0
0
0
0
0
0
0
It is obvious that this circuit computes the integer part of the base 2 logarithm. The output zero is
used to notify that the input value is unappropriate for computing the logarithm, and prevent us from
takeing into account the output value.
122
CHAPTER 6. GATES:
6.1.6
Increment circuit
The simplest arithmetic operation is the increment. The combinational circuit performing this
function receives an n-bit number, xn1 , . . . x0 , and a one-bit command, inc, enabling the operation. The outputs, yn1 , . . . y0 , and crn1 behaves according to the value of the command:
If inc = 1, then
{crn1 , yn1 , . . . y0 } = {xn1 , . . . x0 } + 1
else
{crn1 , yn1 , . . . y0 } = {0, xn1 , . . . x0 }.
in
xn1
xn2
cr
inc
crn1
in
cr
EINC inc
?

out
EINC
yn1
out
a.
x0
crn2
?

INCn1
inc
INCn
yn2
y0
b.
Figure 6.15: Increment circuit. a. The elementary increment circuit (called also half adder). b.
The recursive denition for an n-bit increment circuit.
The increment circuit is built using as brick the elementary increment circuit, EINC,
represented in Figure 6.15a, where the XOR circuit generate the increment of the input if inc = 1
(the current bit is complemented), and the circuit AND generate the carry for the the next binary
order (if the current bit is incremented and it has the value 1). An n-bit increment circuit, IN Cn
is recursively dened in Figure 6.15b: IN Cn is composed using an IN Cn1 serially connected
with an EINC, where IN C0 = EIN C.
6.1.7
Adders
Another usual digital functions is the sum. The circuit associated to this function can be also
made starting from a small elementary circuits, which adds two one-bit numbers, and looking
for a simple recursive denitions for n-bit numbers.
The elementary structure is the well known full adder which consists in two half adders and
an OR2 . An n-bit adder could be done in a recursive manner as the following denition says.
Denition 6.7 The full adder, FA, is a circuit which adds three 1-bit numbers generating a
2-bit result:
F A(in1, in2, in3) = {out1, out0}
FA is used to build n-bit adders. For this purpose its connections are interpreted as follows:
in1, in2 represent the i-th bits if two numbers
in3 represents the carry signal generated by the i 1 stage of the addition process
out0 represents the i-th bit of the result
123
out1 represents the carry generated for the i + 1-th stage of the addition process
Follows the Verilog description:
module full_adder(output sum, carry_out, input in1, in2, carry_in);
half_adder ha1(sum1, carry1, in1, in2),
ha2(sum, carry2, sum1, carry_in);
assign carry_out = carry1 | carry2;
endmodule
module half_adder(output sum, carry, input
assign sum = in1 ^ in2,
carry = in1 & in2;
endmodule
in1, in2);
Note: The half adder circuit is also an elementary increment circuit (see Figure 6.15a).
Denition 6.8 The n-bits ripple carry adder, (ADDn ), is made by serial connecting on the
carry chain an ADDn1 with a FA (see Figure 6.16). ADD1 is a full adder.
module
adder( output [n-1:0] sum

,
output
carry_out
,
input
[n-1:0] in1, in2
,
input
carry_in
);
full_adder fa(sum[n-1], carry_out, in1[n-1], in2[n-1], carry);
adder
adder(sum[n-2:0], carry,
{1b0, in1[n-2:0]}, {1b0, in2[n-2:0]}, carry_in);
endmodule
An1 Bn1
Cn
FA
C+
An2
Sn1
...
B0
A0 Bn2
...
??
ADDn1
C+
Sn2
...
C0
S0
Figure 6.16: The recursive dened n-bit ripple-carry adder (ADDn ). ADDn is simply
designed adding to an ADDn1 a full adder (FA), so as the carry signal ripples from one FA to the next.
Unfortunately the Verilog code from the previous denition is nor simulable neither synthesisable. It can be used only as denition. The iterative structural description for such a circuit
can be done using the generate mechanism provided by Verilog.
Example 6.4 Generated n-bit adder:
module add #(parameter n=8)(
input
input
output
output
[n-1:0] in1, in2,

cIn
,
[n-1:0] out
,
cOut
);
124
CHAPTER 6. GATES:
wire
[n:0]
cr ;
assign cr[0] = cIn ;
assign cOut = cr[n] ;
genvar i
;
generate for (i=0; i<n;
fa adder(
.in1
.in2
.cIn
.out
.cOut
end
endgenerate
endmodule
module fa( input
output
wire
xr ;
i=i+1) begin: S
(in1[i] ),
(in2[i] ),
(cr[i] ),
(out[i] ),
(cr[i+1]));
in1, in2, cIn

out, cOut
assign xr
= in1 ^ in2
assign out = xr ^ cIn
assign cOut = in1 & in2
endmodule
,
);
| cIn
;
;
& xr ;
Carry-Look-Ahead Adder
The size of ADDn is in O(n) and the depth is unfortunately in the same order of magnitude.
For improving the speed of this very important circuit there was found a way for accelerating
the computation of the carry: the carry-look-ahead adder (CLAn ). The fast carry-look-ahead
adder can be made using a carry-look-ahead (CL) circuit for fast computing all the carry signals
Ci and for each bit an half adder and a XOR (the modulo two adder)(see Figure 6.17). The half
adder has two roles in the structure:
Ai
Bi
A
...
S
Pi
...
HA
CR
Gn1
G0
...
Pn1
P0
...
?
Gi
Ci
?
C0
Carry-Lookahead Circuit
??
Si
CnCn1
...
C1
Figure 6.17: The fast n-bit adder. The n-bit Carry-Lookahead Adder (CLAn ) consists in n HAs,
n 2-input XORs and the Carry-Lookahead Circuit used to compute faster the n Ci , for i = 1, 2, . . . n.
sums the bits Ai and Bi on the output S
125
computes the signals Gi (that generates carry as a local eect) and Pi (that allows the
propagation of the carry signal through the binary level i) on the outputs CR and P .
The XOR gate adds modulo 2 the value of the carry signal Ci to the sum S.
In order to compute the carry input for each binary order an additional fast circuit must
be build: the carry-look-ahead circuit. The equations describing it start from the next rule: the
carry toward the level (i + 1) is generated if both Ai and Bi inputs are 1 or is propagated
from the previous level if only one of Ai or Bi are 1. Results:
Ci+1 = Ai Bi + (Ai + Bi )Ci = Ai Bi + (Ai Bi )Ci = Gi + Pi Ci .
Applying the previous rule we obtain the general form of Ci+1 :
Ci+1 = Gi + Pi Gi1 + Pi Pi1 Gi2 + Pi Pi1 Pi2 Gi3 + . . . + Pi Pi1 . . . P1 C0
for i = 0, . . . , n.
Computing the size of the carry-look-ahead circuit results SCL (n) O(n3 ), and the theoretical depth is only 2. But, for real circuits an n-input gates can not be considered as a one-level
circuit. In Basic circuits appendix (see section Many-Input Gates) is shown that an optimal
implementation of an n-input simple gate is realized as a binary tree of 2-input gates having the
depth in O(log n). Therefore, in a real implementation the depth of a carry-look ahead circuit
has DCLA O(log n).
For small n the solution with carry-look-ahead circuit works very good. But for larger n
the two solutions, without carry-look-ahead circuit and with carry-look-ahead circuit, must be
combined in many fashions in order to obtain a good price/performance ratio. For example, the
ripple carry version of ADDn is divided in two equal sections and two carry look-ahead circuits
are built for each, resulting two serial connected CLAn/2 . The state of the art in this domain is
presented in [Omondi 94].
It is obvious that the adder is a simple circuit. There exist constant sized denition for all
the variants of adders.
Carry-Save Adder
For adding m n-bit numbers there is a faster solution than the one which supposes to use the direct
circuit build as a tree of m 1 2-number adders. The depth and the size of the circuit is reduced using
a carry-save adder circuit.
The carry save adder receives three n-bit numbers:
x = {xn1 , xn2 , . . . x1 , x0 }
y = {yn1 , yn2 , . . . y1 , y0 }
z = {zn1 , zn2 , . . . z1 , z0 }
and generate two (n + 1)-bit numbers:
c = {cn1 , cn2 , . . . c1 , c0 , 0}
s = {0, sn1 , sn2 , . . . s1 , s0 }
where:
c + s = x + y + z.
The function of the circuit is described by the following transfer function applied for i = 0, . . . n 1:
xi + yi + zi = {ci , si }.
126
CHAPTER 6. GATES:
z = {zn1 , . . . z0 }
y = {yn1 , . . . y0 }
x = {xn1 , . . . x0 }
x[i]
y[i]
z[i]
??? ???
B
C
S
ECSA
c[i]
s[i]
ECSA0
b.
n0 n1 n2
???
x
ECSAn2
c = {cn1 , . . . c0 , 0}
a.
ECSAn1
FA
C+
?
3CSAn
s = {0, sn1 , . . . s0 }
n3
???
y
3CSAn
c
???
y
????
{0, n3}
n0 n1 n2 n3
4REDAn
3CSAn+1
c
??
4CSAn
n0 + n1 + n2 + n3
d.
ADDn+1
?n0 + n1 + n2 + n3
c.
Figure 6.18: Carry-Save Adder. a. The elementary carry-save adder. b. CSA for 3 n-bit numbers:
3CSAn . c. How to use carry-save adders to add 4 n-bit numbers. d. The logic symbol for a 4 n-bit
inputs reduction adder (4REDAn ) implemented with two 3CSAn and a (n + 1)-bit adder.
The internal structure of the carry-save adders contains n circuits performing the previous function which
is the function of a full adder. Indeed, the binary variables xi and yi are applied on the two inputs of the
FA, zi is applied on the carry input of the same FA, and the two inputs ci , si are the carry-out and the
sum outputs. Therefore, an elementary carry-save adder, ECSA, has the structure of a FA (see Figure
6.18a).
To prove for the functionality of CSA we write for each ECSA:
{cn1 , sn1 } = xn1 + yn1 + zn1
{cn2 , sn2 } = xn2 + yn2 + zn2
...
{c1 , s1 } = x1 + y1 + z1
{c0 , s0 } = x0 + y0 + z0
from which results that:
x + y + z = {cn1 , sn1 } 2n1 + {cn2 , sn2 } 2n2 + . . . {c1 , s1 } 21 + {c0 , s0 } 20 =
{cn1 , cn2 , . . . c1 , c0 } 2 + {sn1 , sn2 , . . . s1 , s0 } = {cn1 , cn2 , . . . c1 , c0 , 0} + {0, sn1 , sn2 , . . . s1 , s0 }.
Figure 6.18c shows a 4-number adder for n-bit numbers. Instead of 3 adders, 2 3CSAn circuits and
a (n + 1)-bit adder are used. The logic symbol for the resulting 4-input reduction adder 4REDAn
127
is represented in Figure 6.18d. The depth of the circuit is of 2 FAs and an (n + 1)-bit adder, instead of
the depth associated with one n-bit adder and an (n + 1)-bit adder. The size is also minimized if in the
standard solution carry-look-ahead adders are used.
Example 6.5 The module 3CSAm is generated using the following template:
module csa3_m #(parameter n=m)(input
output
wire
[n-1:0] out ;
wire
[n-1:0] cr ;
[n-1:0] in0, in1, in2

[n:0]
sOut, cOut
,
);
genvar i
;
generate for (i=0; i<n; i=i+1) begin: S
fa adder(in0[i], in1[i], out[i], cr[i]);
end
endgenerate
assign sOut = {1b0, out}
assign cOut = {cr, 1b0}
endmodule
;
;
where: (1) an actual value for m must be provided and (2) the module fa is dened in the previous
example.
Example 6.6 For the design of a 8 1-bit input adder (8REDA1 ) the following modules are used:
module reda8_1(
output [3:0]
out ,
input
[7:0]
in );
wire
[2:0]
sout, cout ;
csa8_1 csa( in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7],cout,sout);
assign out = cout + sout
;
endmodule
module csa8_1( input
in0, in1, in2, in3, in4, in5, in6, in7,
output [2:0]
cout, sout
);
wire
[1:0]
sout0, cout0, sout1, cout1;
csa4_1 csa0(in0, in1, in2, in3, sout0, cout0),
csa1(in4, in5, in6, in7, sout1, cout1);
csa4_2 csa2(sout0, cout0, sout1, cout1, cout, sout);
endmodule
where csa4 1 and csa4 2 are instances of the following generic module:
module csa4_p( input
[1:0]
in0, in1, in2, in3
output [2:0]
sout, cout
wire
[2:0]
s1, c1 ;
wire
[3:0]
s2, c2 ;
csa3_p csa0(in0, in1, in2, s1, c1);
csa3_q csa1(s1, c1, {1b0, in3}, s2, c2);
assign sout = s2[2:0], cout = c2[2:0];
endmodule
,
);
for p = 1 and p = 2, while q = p + 1. The module csa3 m is dened in the previous example.
The eciency of this method to add many numbers increases, compared to the standard solution,
with the number of operands.
128
CHAPTER 6. GATES:
6.1.8
Combinational Multiplier
One of the most important application of the CSAs circuits is the ecient implementation of a combinational multiplier. Because multiplying n-bit numbers means to add n 2n 1-bit partial products, a
nCSA2n1 circuit provides the best solution. Adding n n-bit numbers using standard carry-adders is
done, in the best case, in time belonging to O(n log n) on a huge area we can not aord. The proposed
solution provides a linear time.
In Figure 6.19 is an example for how for the binary multiplication for n = 4 works. Thus, the
combinational multiplication is done in the following three stages:
a3 a2 a1 a0
b3 b2 b1 b0
p23
p33 p32
p03 p02 p01 p00

p13 p12 p11 p10
p22 p21 p20
p31 p30
p7 p6 p5 p4 p3 p2 p1 p0
1 0 1 1
1 1 0 1
multiplicand: a
multiplier: b
partial
partial
partial
partial
product:
product:
product:
product:
pp0
pp1
pp2
pp3
nal product: p
1 0 1 1
0 0 0 0
1 0 1 1
1 0 1 1
1 0 0 0 1 1 1 1
Figure 6.19: Multiplying 4-bit numbers.

1. compute n partial products pp0 , . . . ppn1 using a two-dimension array of n n AN D2 circuits
(see in Figure 6.20 the partial products computation dashed box); for n = 4 the following
relations describe this stage:
pp0 = {a3 b0 , a2 b0 , a1 b0 , a0 b0 }
pp1 = {a3 b1 , a2 b1 , a1 b1 , a0 b0 }
pp2 = {a3 b2 , a2 b2 , a1 b2 , a0 b0 }
pp3 = {a3 b3 , a2 b3 , a1 b3 , a0 b0 }
2. shift each partial product ppi i binary positions left; results n (2n 1)-bit numbers; for n = 4:
n0 = pp0 << 0 = {0, 0, 0, pp0 }
n1 = pp1 << 1 = {0, 0, pp1 , 0}
n2 = pp2 << 2 = {0, pp2 , 0, 0}
n3 = pp3 << 3 = {pp3 , 0, 0, 0}
easy to be done, with no circuits, by an appropriate connection of the AND array outputs to the
next circuit level (see in Figure 6.20 the hardware-less shifter dashed box)
3. add the resulting n numbers using a nCSA2n1 ; for n = 4:
p = {0, 0, 0, pp0 }plus{0, 0, pp1 , 0}plus{0, pp2 , 0, 0}plus{pp3 , 0, 0, 0}
The combinational multiplier circuit is presented in Figure 6.20 for the small case of n = 4. The rst
stage partial products computation generate the partial products ppi using 2-input ANDs as one
bit multipliers. The second stage of the computation request a hardware-less shifter circuit, because the
multiplying n-bit numbers with a power of 2 no bigger than n 1 is done by an appropriate connection
of each ppi to the (2n 1)-bit inputs of the next stage, lling up the unused positions with zeroes. The
third stage consists of a carry-save adder nCSA2n1 which receives, as 2n 1-bit numbers, the partial
products ppi , each multiplied with 2i .
The circuit represented in Figure 6.20 for n = 4, has in the general case the size in O(n2 ) and the
depth in O(n). But, the actual size and depth of the circuit is established by the 0s applied to the input
of the nCSA2n1 circuit, because some full-adders are removed from design and others are reduced to
a3
a2
a1
129
a0
b0
pp0 = {a3 b0 , a2 b0 , a1 b0 , a0 b0 }
b1
b2
b3
pp1
pp2
pp3
4

rst stage: partial products computation
3
n3
n2
n1
3
n0
4CSA7
second stage: hardware-less shifter
s = n0 + n1 + n2 + n3
8
?p = a b
Figure 6.20: 4-bit combinational multiplier. .

half-adders. The actual size of nCSA2n1 results to be very well approximated with the actual size of
a nCSAn . The actual depth of the combinational multiplier is well approximated with the depth of a
2.5n-bit adder.
The decision to use a combinational multiplier must be done takeing into account (1) its area, (2) the
acceleration provided for the function it performs and (3) the frequency of the multiplication operation
in the application.
6.1.9
Arithmetic and Logic Unit
All the before presented circuits have had associated only one logic or one arithmetic function.
Now is the time to design the internal structure of a previously dened circuit having many
functions, which can be selected using a selection code: the arithmetic and logic unit ALU
(for the functional description see Example 2.8). ALU is the main circuit in any computational
device, such as processors, controllers or embedded computation structures.
The ALU circuit can be implemented in many forms. One of them is the speculative version
(see Figure 6.21) well described by the Verilog module from Example 2.8, where the case structure describes, in fact, an 8-input multiplexor for 33-bit words. We call this version speculative
because all the possible functions are computed in order to be all available to be select when the
function code arrives to the func input of ALU. This approach is ecient when the operands are
available quickly and the function to be performed arrives lately (because it is usually decoded
from the instruction fetched from a program memory). The circuit speculates computing all
the dened functions oering 8 results from which the func code selects one. (This approach
will be useful for the ALU designed for the stack processor described in Chapter 10.)
The speculative version provides a fast version in some specic designs. The price is the
big size of the resulting circuit (mainly because the arithmetic section contains and adder and
an subtractor, instead a smaller circuit performing add or subtract according to a bit used to
complement the right operand and the carryIn signal).
An area optimized solution is provided in the next example.
Example 6.7 Let be the 32-bit ALU with 8 functions described in Example 2.8. The imple-
130
CHAPTER 6. GATES:
right[n-1:0]
{2b0, left[n-1:1]}
left[n-1:0]
carryIn
??
??
ab
a+b
n AN D2
n OR2
?
n
n XOR2
func
N OT
- sel
????????
01234567
(n + 1) M U X8
{carryOut, out[n-1:0]}
Figure 6.21: The internal structure of the speculative version of an arithmetic and
logic unit. Each function is performed by a specic circuit and the output multiplexer selects the
desired result.
mentation will be done using an adder-subtractor circuit and a 1-bit slice for the logic functions.
Results the following Verilog description:
module structuralAlu(output [31:0] out
,
output
carryOut,
input
carryIn ,
input
[31:0] left
, right
input
[2:0]
func
);
wire
[31:0] shift, add_sub, arith, logic;
addSub addSub(.out
(add_sub ),
.cout
(carryOut),
.left
(left
),
.right (right
),
.cin
(carryIn ),
.sub
(func[0] ));
logic log( .out
(logic
),
.left
(left
),
.right (right
),
.op
(func[1:0]));
mux2
shiftMux(.out(shift
),
.in0(left
),
.in1({1b0, left[31:1]}),
.sel(func[0]
)),
arithMux(.out(arith ),
.in0(shift ),
.in1(add_sub),
.sel(func[1])),
outMux(.out(out
),
.in0(arith ),
.in1(logic ),
.sel(func[2]));
endmodule
module mux2(input
input
[31:0]
sel
,
in0, in1,
assign
endmodule
output [31:0] out

out = sel ? in1 : in0;
module addSub(output [31:0]

output
input [31:0]
input
assign {cout, out} = left
endmodule
131
);
out
,
cout
,
left, right ,
cin, sub
);
+ (right ^ {32{sub}}) + (cin ^ sub);
module logic(output reg [31:0] out

,
input
[31:0] left, right ,
input
[1:0] op
);
integer i;
wire [3:0] f;
assign f = {op[0], ~(~op[1] & op[0]), op[1], ~|op};
always @(left or right or f)
for(i=0; i<32; i=i+1) logicSlice(out[i], left[i], right[i], f);
task
logicSlice;
output
o;
input
l, r;
input
[3:0]
f;
o = f[{l,r}];
endtask
endmodule
The resulting circuit is represented in Figure 6.22. This version can be synthesized on a
smaller area, because the number of EM U Xs is smaller, instead of an adder and a subtractor
an adder/subtractor is used. The price for this improvement is a smaller speed. Indeed, the
add sub module starts to compute the addition or the subtract only when the signal sub =
func[0] is received. Usually, the code func results from the decoding of the current operation
to be performed, and, consequently, comes later.
right
left
n M U XE
sub
add sub
carryOut
logic
carryIn
func[0]
n M U XE
func[1]
func[2]
n M U XE
?out
Figure 6.22: The internal structure of an area optimized version of an ALU. The add sub
module is smaller than an adder and a subtractor, but the operation starts only when func[0] is valid.
132
CHAPTER 6. GATES:
We just learned a new feature of the Verilog language: how to use a task to describe a
circuit used many times in implementing a simple, repetitive structure.
The internal structure of ALU consists mainly in n slices, one for each input pair left[i],
rught[i] and a carry-look-ahead circuit(s) used for the arithmetic section. It is obvious that
ALU is also a simple circuit. The magnitude order of the size of ALU is given by the size of the
carry-look-ahead circuit because each slice has only a constant dimension and a constant depth.
Therefore, the fastest version implies a size in O(n3 ) because of the carry-look-ahead circuit.
But, lets remind: the price for the fastest solution is always too big! For optimal solutions see
[Omondi 94].
6.1.10
Comparator
Comparing functions are used in decisions. Numbers are compared to decide if they are equal
or to indicate the biggest one. The n-bit comparator, COM Pn , is represented in Figure 6.23a.
The numbers to be compared are the n-bit positive integers a and b. Three are the outputs of
the circuit: lt out, indicating by 1 that a < b, eq out, indicating by 1 that a = b, and gt out,
indicating by 1 that a > b. Three additional inputs are used as expanding connections. On
these inputs is provided information about the comparison done on the higher range, if needed.
If no higher ranges of the number under comparison, then these thre inputs must be connected
as follows: lt in = 0, eq in = 1, gt in = 0.
a[n-1:0]
lt in
eq in
gt in
b[n-1:0]
a[i]
COMP
lt out
lt in
eq out
eq in
gt out
gt in
a.
b[i]
ECOMP
lt out
eq out
gt out
b.
a[n-1] b[n-1]
lt in
eq in
gt in
ECOMP
a[n-2]
b[n-2]
COM Pn1
lt out
eq out
gt out
c.
Figure 6.23: The n-bit comparator, COM Pn . a. The n-bit comparator. b. The elementary
comparator. c. A recursive rule to built an COM Pn , serially connecting an ECOM P with a COM Pn1
The comparison is a numerical operation which starts inspecting the most signicant bits
of the numbers to be compared. If a[n 1] = b[n 2], then the result of the comparison is
given by comparing a[n 2 : 0] with b[n 1 : 0], else, the decision can be done comparing
only a[n 1] with b[n 1] (using an elementary comparator, ECOM P = COM P1 (see Figure
6.23b)), ignoring a[n 2 : 0] and b[n 2 : 0]. Results a recursive denition for the comparator
circuit.
Denition 6.9 An n-bit comparator, COM Pn , is obtained serially connecting an COM P1 with
a COM Pn1 . The Verilog code describing COM P1 (ECOMP) follows:
module e_comp( input
a
b
,
,
assign
lt_in
,
eq_in
,
gt_in
,
output lt_out ,
eq_out ,
gt_out );
lt_out = lt_in | eq_in
eq_out = eq_in & ~(a ^
gt_out = gt_in | eq_in
133
// the previous e_comp decided lt

// the previous e_comp decided eq
// the previous e_comp decided gt
// a < b
// a = b
// a > b);
& ~a & b,
b),
& a & ~b;
endmodule
The size and the depth of the circuit resulting from the previous denition are in O(n). The
size is very good, but the depth is too big for a high speed application.
An optimal comparator is dened using another recursive denition based on the divide et
impera principle.
Denition 6.10 An n-bit comparator, COM Pn , is obtained using two COM Pn/2 , to compare the higher and the lower half of the numbers (resulting {lt out high, eq out high,
gt out high} and {lt out low, eq out low, gt out low}), and a COM P1 to compare
gt out low with lt out low in the context of {lt out high, eq out high, gt out high}. The
resulting circuit is represented in Figure 6.24.
a[n-1:n/2]
b[n-1:n/2]
a[n/2-1:0]
?
1
COM Pn/2
ECOMP
b[n/2-1:0]
?
COM Pn/2
?
-
lt out
eq out
gt out
Figure 6.24: The optimal n-bit comparator. Applying the divide et impera principle a COM Pn
is built using two COM Pn/2 and an ECOM P . Results a log-depth circuit with the size in O(n).
The resulting circuit is a log-level binary tree of ECOMPs. The size remains in the same
order3 , but now the depth is in O(log n).
The bad news is: the HDL languages we have are unable to handle safely recursive denitions.
The good news is: the synthesis tools provide good solutions for the comparison functions
starting from a very simple behavioral description.
6.1.11
Sorting network
In the most of the cases numbers are compared in order to be sorted. There are a lot of algorithms for
sorting numbers. They are currently used to write programs for computers. But, in G2CE the sorting
function will migrate into circuits, providing specic accelerators for general purpose computing machines.
3
The actual size of the circuit can be minimized takeing into account that: (1) the compared input of ECOMP
cannot be both 1, (2) the output eq out of one COM Pn/2 is unused, and (3) the expansion inputs of both
COM Pn/2 are all connected to x values.
134
CHAPTER 6. GATES:
To solve in circuits the problem of sorting numbers we start again from an elementary module: the
elementary sorter (ESORT).
Denition 6.11 An elementary sorter (ESORT) is a combinational circuit which receives two n-bit
integers, a and b and generate outputs them as min(a,b) and max(a,b). The logic symbol of ESORT is
represented in Figure 6.25b.
The internal organization of an ESORT is represented in Figure 6.25a. If COM Pn is implemented
in an optimal version, then this circuit is optimal because its size is linear and its depth is logarithmic.
n EM U X
n EM U X
COM Pn
min(a,b) max(a,b)
min(a,b)
max(a,b)
a.
b.
Figure 6.25: The elementary sorter. a. The internal structure of an elementary sorter. The
output lt out of the comparator is used to select the input values to output in the received order (if
lt out = 1) or in the crossed order (if lt out = 0). b. The logic symbol of an elementary sorter.
stage 1
d
stage 2
stage 3
max(max(a,b), max(c,d))
max(min(max(a,b)max(cd),max(min(a,b), min(c,d)))
min(min(max(a,b)max(cd),max(min(a,b), min(c,d)))
min(min(a,b), min(c,d))
Figure 6.26: The 4-input sorter. The 4-input sorter is a three-stage combinational circuit built by
5 elementary sorters.
The circuit for sorting a vector of n numbers is build by ESORTs organized on many stages. The resulting combinational circuit receives the input vector (x1 , x2 , x3 , . . . xn ) and generates the sorted version
of it. In Figure 6.26 is represented a small network of ESORTs able to sort the vector of integers (a, b, c, d).
The sorted is organized on three stages. On the rst stage two ESORTs are used sort separately the
sub-vectors (a, b) and (c, d). On the second stage, the minimal values and the maximal values obtained
from the previous stage are sorted, resulting the the smallest value (the minimal of the minimals), the
biggest value (the maximal of the maximal) and the two intermediate values. For the last two the third
level contains the last ESORT which sorts the middle values.
The resulting 4-input sorting circuit has the depth Dsort (4) = 3 Desort (n) and the size Ssort (4) =
5 Sesort (n), where n is the number of bits used to represent the sorted integers.
Bathcers sorter
What is the rule to design an 8-number sorter? This topic will pe presented using [Batcher 68], [Knuth
73] or [Parberry 87].
135
Theorem 6.1 An n-input comparator network is a sorting network i it works as sorter for all sequences
of n symbols of zeroes and ones.
The previous theorem is known as Zero-One Principle.
x0
x1
x2
x3
a0
a1
a2
a3
Sn/2
xn/22
xn/21
xn/2
xn/2+1
xn/2+2
xn/2+3
an/22
an/21
b0
b1
b2
b3
Sn/2
xn2
xn1
bn/22
bn/21
Mn/2
m0 m1 m2
Mn/2
Mn
mn/21
m0 m1
y1
y0
y2
y3
y4
yn3
yn2
yn1
Figure 6.27: Batchers sorter. The n-input sorter, Sn , is dened by a double-recursive construct:
Sn = 2 Sn/2 + Mn , where the merger Mn consists of Mn = 2 Mn/2 + (n/2 1)S2 .
6.1.12
Prex computation network
There is a class of circuits, called prex computation networks, P CNf unc (n), dened for n inputs and
having the characteristic function f unc. If f unc is expressed using the operation , then the function of
P CN (n) is performed by a circuit having the inputs x0 , . . . xn1 and the outputs y0 , . . . yn1 related as
follows:
y0 = x0
y1 = x0 x1
y2 = x0 x1 x2
136
CHAPTER 6. GATES:

...
yn1 = x0 x1 . . . xn1
where the operation is an associative and commutative operation. For example, can be the arithmetic operation add, or the logic operation AND. In the rst case xi is an m-bit binary number, and in
the second case it is a 1-bit Boolean variable.
Example 6.8 If is the Boolean function AND, then P CNAN D (n) is described by the following behavioral description:
module and_prefixes #(parameter n = 64)(input
[0:n-1] in ,
output reg [0:n-1] out);
integer k;
always @(in) begin out[0] = in[0];
for (k=1; k<n; k=k+1) out[k] = in[k] & out[k-1];
end
endmodule
There are many solutions for implementing P CNAN D (n). If we use AND gates with up to n inputs,
then there is a rst direct solution for P CNAN D starting from the dening equations (it consists in
one 2-input gate, plus one 3-input gate, . . . plus one (n-1)-input gate). A very large high-speed circuit
is obtained. Indeed, this direct solution oers a circuit with the size S(n) O(n2 ) and the depth
D(n) O(1). We are very happy about the speed (depth), but the price paid for this is too high: the
squared size. In the same time our design experience tells us that this speed is not useful in current
applications because of the time correlations with other subsystems. (There is also a discussion about
gate having n inputs. These kind of gates are not realistic.)
A second solution oers a very good size but a too slow circuit. If we use only 2-input AND gates,
then the denition becomes:
y0 = x0
y1 = y0 & x1
y2 = y1 & x2
...
yn1 = yn2 & xn1
A direct solution starting from this new form of the equations (as a degenerated binary tree of ANDs)
has S(n) O(n) and D(n) O(n). This second solution is also very inecient, now because of the speed
which is too low.
The third implementation is a optimal one. For P CNAN D (n) is used the recursive dened network
represented in Figure 6.28 [Ladner 80], where in each node, for our application, there is a 2-inputs
AN D gate. If P CNAN D (n/2) is a well-functioning prex network, then all the structure works as a
prex network. Indeed, P CNAN D (n/2) computes all even outputs because of the n/2 input circuits that
perform the y2 function between successive pairs of inputs. On the output level the odd outputs are
computed using even outputs and odd inputs. The P CNAN D (n/2) structure is built upon the same rule
and so on until P CNAN D (1) that is a system without any circuit. The previous recursive denition is
applied for n = 16 in Figure 6.29.
The size of P CNAN D (n), S(n) (with n a power of 2), is evaluated starting from: S(1) = 0, S(n) =
S(n/2) + (n 1)Sy1 where Sy1 is the size of the elementary circuit that denes the network (in our case
is a 2-inputs AND gate). The next steps leads to:
S(n) = S(n/2i ) + (n/2i1 + . . . + n/20 i)Sy1
and ends, for i = log2 n (the rule is recursively applied log n times), with:
S(n) = (2n 2 log2 n)Sy1 O(n).
x0
x1
x2
x3
x4
137
xn2 xn1
x5
P CNAN D (n/2)
y0
y1
y2
y3
y4
yn3 yn2 yn1
Figure 6.28: The internal structure of P CNAN D (n). It is recursively dened: if P CNAN D (n/2)
is a prex computation network, then the entire structure is P CNn .
(The network consists in two binary trees of elementary circuits. The rst with the bottom root having
n/2 leaves on the rst level. The second with the top root having n/2 1 leaves on the rst level.
Therefore, the rst tree has n 1 elementary circuits and the second tree has n 1 log n elementary
circuits.) The depth is D(n) = 2Dy2 log2 n O(log n) because D(n) = D(n/2) + 2 (at each step two
levels are added to the system).
6.1.13
First detection network
Let be the vector of Boolean variable: inVector = {x0, x1, ...

outputs three vectors of the same size:
x(n-1)}. The function firstDetect
first
= {0, 0, ... 0, 1, 0, 0, ... 0}
beforeFirst = {1, 1, ... 1, 0, 0, 0, ... 0}
afterFirst = {0, 0, ... 0, 0, 1, 1, ... 1}
indicating, by turn, the position of the rst 1 in inVector, all the positions before the rst 1, and all the
positions after the rst 1.
Example 6.9 Let be a 16-bit input circuit performing the function firstDetect.
inVector
= {0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1}
first
= {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
beforeFirst = {1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
afterFirst = {0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
The circuit performing the function firstDetect is described by the following Verilog program:
module firstDetect #(parameter n =4)( input
output
output
output
wire [0:n-1] orPrefixes;
[0:n-1]
[0:n-1]
[0:n-1]
[0:n-1]
in
,
first
,
beforeFirst,
afterFirst );
138
CHAPTER 6. GATES:
x0
x1
x2
x3
x4
x5
x6
x7
x8
x9 x10 x11 x12 x13 x14 x15
M
EP Nand
P Nand (4)
P Nand (8)
y0
y1
y2
y3
y4
y5
y6
y7
y8
y9 y10 y11 y12 y13 y14 y15
P Nand (16)
Figure 6.29: P CNAN D (16)
or_prefixes prefixNetwork(.in (in

),
.out(orPrefixes));
assign first
= orPrefixes & ~(orPrefixes >> 1),
beforeFirst = ~orPrefixes
,
afterFirst = (orPrefixes >> 1)
;
endmodule
module or_prefixes #(parameter n =4)(input
[0:n-1] in ,
output reg [0:n-1] out);
integer k;
always @(in) begin out[0] = in[0];
for (k=1; k<n; k=k+1) out[k] = in[k] | out[k-1];
end
endmodule
The function firstDetect classies each component of a Boolean vector related to the rst occurrence
of the value 14 .
6.2. COMPLEX, RANDOMLY DEFINED CIRCUITS
x0
x1
x0
??
f1
y1
y2
??
f1
x2
y1
??
f2
x1
y2
xn/2+1
??
x2
??
fn/2+1
xn/2+1
??
xn/2+2
??
fn/2+1
xn/2+2
??
f2
fn/2+2
fn/2+2
x3
??
139
f3
y3
xn/2
??
fn/2
xn
??
fn
fn
??
fn
xn
??
fn/2
??
yn
xn
1 0
emux
s
yn
a.
?
b.
Figure 6.30:
6.1.14
6.2
6.2.1
Spiras theorem
Complex, Randomly Dened Circuits

An Universal circuit
Besides the simple, recursively dened circuits there is the huge class of the complex or random
circuits. Is there a general solution for these category of circuits? A general solution asks a
general circuit and this circuit surprisingly exists. Now rises the problem of how to catch the
huge diversity of random in this approach. The following theorem will be the rst step in solving
the problem.
Theorem 6.2 For any n, all the functions of n binary-variables have a solution with a combinational logic circuit.
Proof Any Boolean function of n variables can be written as:
f (xn1 , . . . , x0 ) = xn1 g(xn2 , . . . , x0 ) + xn1 h(xn2 , . . . x0 ).
where:
g(xn2 , . . . , x0 ) = f (0, xn2 , . . . , x0 )
h(xn2 , . . . , x0 ) = f (1, xn2 , . . . , x0 )
Therefore, the computation of any n-variable function can be reduced to the computation
of two other (n 1)-variables functions and an EMUX. The circuit, and in the same time the
algorithm, is represented in Figure 6.32. For the functions g and h the same rule may applies.
4
The function firstDetect becomes very meaningful related to the minimalization rule in Kleenes computational model [Kleene 36].
140
CHAPTER 6. GATES:
x0 x1
x0 x1
1 x2
0 x2
x2
x3
x0 x1
x2
x2
x3
x3
x3
x3
1 0
emux
1 0
emux
a.
x0 x1
c.
b.
x2 x3
x2 x3
x0 x1
x2 x3
x0 x1
x2 x3
XOR
1 0
emux
1 0
emux
s
e.
d.
f.
Figure 6.31:
And so on until the two zero-variable functions: the value 0 and the value 1. The solution is an
n-level binary tree of EMUXs having applied to the last level zero-variable functions. Therefore,
solution is a M U Xn and a binary string applied on the 2n selected inputs. The binary sting has
n
the length 2n . Thus, for each of the 22 functions there is a distinct string dening it.
The universal circuit is indeed the best example of a big simple circuit, because it is described
by the following code:
module nU_circuit #(include "parameter.v")(
assign
endmodule
output
input
input
[(1b1 << n)-1:0]

[n-1:0]
out ,
func,
in );
out = func[in];
The le parameter.v contains the value for n. But, attention! The size of the circuit is:
SnUc ircuit (n) O(2n ).
Thus, circuits are more powerful than Turing Machine (TM), because TM solve only problem
having the solution algorithmically expressed with a sequence of symbols that does not depend
by n. Beyond the Turing-computable function there are many functions for which the solution
is a family of circuits.
141
xn2 , . . . , x0
n1
CLCg
g(xn2 , . . . , x0 )
CLCh
h(xn2 , . . . , x0 )
i0
i1
x0 emux
xn1
y
?f (xn1 , . . . , x0 )
Figure 6.32: The universal circuit. For any CLCf (n), where f (xn1 , . . . , x0 ) this recursively
dened structure is a solution. EMUX behaves as an elementary universal circuit.
The solution imposed by the previous theorem is an universal circuit for computing the n
binary variable functions. Let us call it nU-circuit (see Figure 6.33). The size of this circuit is
Suniversal (n) O(2n ) and its complexity is Cuniversal (n) O(1). The functions is specied by
the program P = mp1 , mp2 , . . . m0 which is applied on the selected inputs of the n-input
multiplexer M U Xn . It is about a huge simple circuit. The functional complexity is associated
with the program P , which is a binary string.
mp1 mp2 mp3 mp4 mp5 mp6 mp7 mp8
x0
??
1 0
emux
1 0
emux
x1
??
1 0
emux
??
1 0
emux
1 0
emux
??
x2
xn1
??
1 0
emux
m3 m2
??
m1 m0
??
1 0
emux
1 0
emux
??
1 0
emux
??
??
1 0
emux
??
1 0
emux
nU-circuit
f (xn1 , xn2 , . . . x0 )
Figure 6.33: The Universal Circuit as a tree of EMUXs. The depth of the circuit is equal
with the number, n, of binary input variables. The size of the circuit increases exponentially with n.
This universal solution represents the strongest segregation between a simple physical structure - the n-input MUX - and a complex symbolic structure - the string of 2n bits applied on
the selected inputs which works like a program. Therefore, this is THE SOLUTION, MUX is
THE CIRCUIT and we can stop here our discussion about digital circuits!? ... But, no! There
are obvious reasons to continue our walk in the world of digital circuits:
rst: the exponential size of the resulting physical structure
second: the huge size of the programs which are in a tremendous majority represented
142
CHAPTER 6. GATES:
by random, uncompressible, strings (hard or impossible to be specied).

The strongest segregation between simple and complex is not productive
in no-loop circuits. Both resulting structure, the simple circuit and the
complex binary string, grow exponentially.
6.2.2
Using the Universal circuit
We have a chance to use M U Xn to implement f (xn1 , . . . , x0 ) only if one of the following

conditions is fullled:
1. n is small enough resulting realizable and ecient circuits
2. the program is a string with useful regularities (patterns) allowing strong minimization
of the resulting circuit
Follows few well selected examples. First is about an application with n enough small to provide
an useful circuit (it is used in Connection Machine as an universal circuit performing anyone
of the 3-input logic function [Hillis 85]).
Example 6.10 Let be the following Verilog code:
module three_input_functions(
assign
endmodule
output
input
[7:0]
input
out = func[{in0, in1, in2}];
out
func
in0, in1, in2
,
,
);
The circuit three input functions can be programmed, using the 8-bit string func as program, to perform anyone 3-input Boolean function. It is obviously a M U X3 performing
out = f (in0, in1, in2)
where the function f is specied (programmed) by an 8-bit word (program).
The programmable circuit for any 4-input Boolean function is obviously M U X4 :
out = f (in0, in1, in2, in3)
where f is programmed by a 16-bit word applied on the selected inputs of the multiplexer.
The bad news is: we can not go to far on this way because the size of the resulting universal
circuits increases exponentially. The good news is: usually we do not need universal but particular solution. The circuits are, in most of cases, specic not universal. They execute a specic
program. But, when a specic binary word is applied on the selected inputs of a multiplexer,
the actual circuit is minimized using the following removing rules and reduction rules.
An EMUX dened by:
out = x ? in1 : in0;
can be removed, if on its selected inputs specic 2-bit binary words are applied, according to the
following rules:
if {in1, in0} = 00 then out = 0
if {in1, in0} = 01 then out = x
143
if {in1, in0} = 10 then out = x

if {in1, in0} = 11 then out = 1
or, if the same variable, y, is applied on both selected inputs:
if {in1, in0} = yy then out = y
An EMUX can be reduced, if on one its selected inputs a 1-bit binary word are applied, being
substituted with a simpler circuit according to the following rules:
if {in1, in0} = y0 then out = xy
if {in1, in0} = y1 then out = y + x
if {in1, in0} = 0y then out = x y
if {in1, in0} = 1y then out = x + y
Results: the rst level of 2n1 EMUXs of a M U Xn is reduced, and on the inputs of the
second level (of nn2 EMUXs) is applied a word containing binary values (0s and 1s) and binary
variables (x0 s and x0 s). For the next levels the removing rules or the reducing rules are applied.
the program
input variables
1 1
x0
??
1 0
emux
1 0
emux
x1
x2
1 0
1 0
??
1 0
emux
??
1 0
emux
1 0
emux
??
0 0
??
1 0
emux
??
??
1 0
emux
m3 (x2 , x1 , x0 )
Figure 6.34: The majority function. The majority function for 3 binary variables is solved by a
3-level binary tree of EMUXs. The actual program applied on the leafs will allow to minimize the
tree.
Example 6.11 Let us solve the problem of majority function for three Boolean variable. The
function maj(x2 , x1 , x0 ) returns 1 if the majority of inputs are 1, and 0 if not. In Figure 6.34
a programmable circuit is used to solve the problem.
Because we intend to use the circuit only for the function maj(x2 , x1 , x0 ) the rst layer of
EMUXs can be removed resulting the circuit represented in Figure 6.35a.
On the resulting circuit the reduction rules are applied. The result is presented in Figure
6.35b.
The next examples refer to big n, but program containing repetitive patterns.
144
CHAPTER 6. GATES:
x0
x0
1
x1
x2
??
1 0
emux
x1
??
1 0
emux
??
1 0
emux
x2
1 0
emux
m3 (x2 , x1 , x0 )
m3 (x2 , x1 , x0 )
a.
b.
Figure 6.35: The reduction process. a. For any function the rst level of EMUSs is reduced to a
binary vector ((1, 0) in this example). b. For the actual program of the 3-input majority function the
second level is supplementary reduced to simple gates (an AN D2 and an OR2 ).
Example 6.12 If the program is 128-bit string i127 . . . i0 = (10)64 , it corresponds to a function
of form:
f (x6 , . . . , x0 )
where: the rst bit, i0 is the value associated to the input conguration x6 , . . . , x0 = 0000000 and
the last bit i127 is the value associated to input conguration x6 , . . . , x0 = 1111111 (according
with the representation from Figure 6.11 which is equivalent with Figure 6.32).
The obvious regularities of the program leads our mind to see what happened with the
resulting tree of EMUXs. Indeed, the structure collapses under this specic program. The
upper layer of 64 EMUXs are selected by x0 and each have on their inputs i0 = 1 and i1 = 0,
generating x0 on their outputs. Therefore, the second layer of EMUXs receive on all selected
inputs the value x0 , and so on until the output generates x0 . Therefore, the circuit performs the
function f (x0 ) = x0 and the structure is reduced to a simple inverter.
In the same way the program (0011)32 programs the 7-input MUX to perform the function
f (x1 ) = x1 and the structure of EMUXs disappears.
For the function f (x1 , x0 ) = x1 x0 the program is (0010)32 .
For a 7-input AND theprogram is 0127 1, and the tree of MUXs degenerates in 7 EMUXs
serially connected each having the input i0 connected to 0. Therefore, each EMUX become an
AN D2 and applying the associativity principle results an AN D7 .
In a similar way, the same structure become an OR7 if it is programmed with 01127 .
It is obvious that if the program has some uniformities, these uniformities allow to minimize
the size of the circuit in polynomial limits using removing and reduction rules. The simple
programs lead toward small circuits.
6.2.3
The many-output random circuit: Read Only Memory
The simple solution for the following many-output random circuits having the same inputs:
f (xn1 , . . . x0 )
g(xn1 , . . . x0 )
...
145
s(xn1 , . . . x0 )
is to connect in parallel many one-output circuits. The ineciency of the solution become
obvious when the structure of the MUX presented in Figure 6.9 is considered. Indeed, if we
implement many MUXs with the same selection inputs, then the decoder DCDn is replicated
many time. One DCD is enough for many MUXs if the structure from Figure 6.36a is adopted.
The DCD circuit is shared for implementing the functions f, g, . . . s. The shared DCD is used
to compute all possible minterms (see Appendix C.4) needed to compute an n-variable Boolean
function.
fm1 fm2
f0
gm1 gm2
g0
sm1 sm2
s0
O0
DCD
Om2
Om1
n
xn1 , . . . x0
f (xn1 , . . . x0 )
a.
g(xn1 , . . . x0 )
s(xn1 , . . . x0 )
O0
DCD
Om2
Om1
n
xn1 , . . . x0
b.
f (xn1 , . . . x0 )
g(xn1 , . . . x0 )
s(xn1 , . . . x0 )
f (xn1 , . . . x0 )
g(xn1 , . . . x0 )
s(xn1 , . . . x0 )
O0
DCD
Om2
Om1
n
xn1 , . . . x0
c.
Figure 6.36: Many-output random circuit. a. One DCD and many AND-OR circuits. b. An
example. c. The version using programmable connections.
Figure 6.36b is an example of using the generic structure from Figure 6.36a to implement a
specic many-output function. Each output is dened by a dierent binary string. A 0 removes
the associated AND, connecting the corresponding OR input to 0, and an 1 connects to the
corresponding i-th input of each OR to the i-th DCD output. The equivalent resulting circuit is
represented in Figure 6.36c, where some OR inputs are connected to ground and other directly
146
CHAPTER 6. GATES:
to the DCDs output. Therefore, we use a technology allowing us to make programmable

connections of some wires to other (each vertical line must be connected to one horizontal line).
The uniform structure is programmed with a more or less random distribution of connections.
VDD
O0
O0
DCD
DCD
Om1
Om1
Om1
Om1
xn1 , . . . x0
a.
xn1 , . . . x0
f
??
b.
Figure 6.37: The internal structure of a Read Only Memory used as trans-coder. a.
The internal structure. b. The simplied logic symbol where a thick vertical line is used to represent an
m-input NAND gate.
If De Morgan transformation is applied, the circuit from Figure 6.36c is transformed in the
circuit represented in Figure 6.37a, where instead of an active high outputs DCD an active low
outputs DCD is considered and the OR gates are substituted with NAND gates. The DCDs
outputs are generated using NAND gates to decode the input binary word, the same as the gates
used to encode the output binary word. Thus, a multi-output Boolean function works like a
trans-coder. A trans-coder works translating all the binary input words into output binary
words. The list of input words can by represented as an ordered list of sorted binary numbers
starting with 0 and ending with 2n 1. The table from Figure 6.38 represents the truth table
for the multi-output function used to exemplify our approach. The left column contains all
binary numbers from 0 (on the rst line) until 2n 1 = 11 . . . 1 (on the last line). In the right
column the desired function is dened associating to each input an output. If the left column is
an ordered list, the right column has a more or less random content (preferably more random
for this type of solution).
Input
00 ... 00
...
11 ... 10
11 ... 11
Output
11 ... 0
...
10 ... 0
01 ... 1
Figure 6.38: The truth table for a multi-output Boolean function. The input columns can
be seen as addresses, from 00 . . . 0 to 11 . . . 1 and the output columns as the content stored at the
corresponding addresses.
The trans-coder circuit can be interpreted as a x content memory. Indeed, it works like a
memory containing at the location 00...00 the word 11...0, ... at the location 11...10 the word
10...0, and at the last location the word 01...1. The name of this kind of programmable device
is read only memory, ROM.
Example 6.13 The trans-coder from the binary coded decimal numbers to 7 segments display is
a combinational circuit with 4 inputs, a, b, c, d, and 7 outputs A, B, C, D, E, F, G, each associated
147
to one of the seven segments. Therefore we have to solve 7 functions of 4 variables (see the truth
table from Figure 6.40).
The Verilog code describing the circuit is:
module seven_segments( output reg [6:0]
out ,
input
[3:0]
in );
always @(in) case(in)
4b0000: out = 7b0000001;
4b0001: out = 7b1001111;
4b0010: out = 7b0010010;
4b0011: out = 7b0000110;
4b0100: out = 7b1001100;
4b0101: out = 7b0100100;
4b0110: out = 7b0100000;
4b0111: out = 7b0001111;
4b1000: out = 7b0000000;
4b1001: out = 7b0000100;
default out = 7bxxxxxxx;
endcase
endmodule
The rst solution is a 16-location of 7-bit words ROM (see Figure 6.39a. If inverted outputs
are needed results the circuit from Figure 6.39b.
0
DCD4
DCD4
15
x3 x2 x1 x0
6666
6b c d
15
x3 x2 x1 x0
6666
??????
6b c d A?
B CD E F G
???????
A B C D E F G
a.
b.
Figure 6.39: The CLC as trans-coder designed serially connecting a DCD with an
encoder. Example: BCD to 7-segment trans-coder. a. The solution for non-inverting functions. b.
The solution for inverting functions.
Programmable Logic Array In the previous example each output of DCD compute the inverted
value of a minterm. But our applications do not need all the possible minterms, for two reasons:
the function is not dened for all possible input binary congurations (only the input codes representing numbers from 0 to 9 dene the output behavior of the circuit)
in the version with inverted outputs the minterm corresponding for the input 1000 (the number 8)
is not used.
148
CHAPTER 6. GATES:

abcd
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
....
1111
ABCDEFG
1111110
0110000
1101101
1111001
0110011
1011011
1011111
1110000
1111111
1111011
------.......
-------
Figure 6.40: The truth table for the 7 segment trans-coder. Each binary represented decimal
(in the left columns of inputs) has associated a 7-bit command (in the right columns of outputs) for the
segments used for display. For unused input codes the output is dont care.
A more exible solution is needed. ROM consists in two arrays of NANDs, one x and another congurable (programmable). What if also the rst array is congurable, i.e., the DCD circuit is programmed
to compute only some minterms? More, what if instead of computing only minterms (logic products
containing all the input variable) we compute also some, or only, terms (logic products containing only a
part of input variable)? As we know a term corresponds to a logic sum of minterms. Computing a term
in a programmable array of NANDs two or more NANDs with n inputs are substituted with a NAND
with n 1 or less inputs. Applying these ideas results another frequently used programmable circuit: the
famous PLA (programmable logic array).
Example 6.14 Lets revisit the problem of 7 segment trans-coder. The solution is to use a PLA. Because
now the minimal form of equations is important the version with inverted outputs is considered. Results
the circuit represented in Figure 6.41, where a similar convention for representing NANDs as a thick line
is used.
a
b
c
d
- A
- B
- C
- D
- E
- F
- G
bcd
bcd
d
bcd
abcd
bcd
cd
bcd
abc
Figure 6.41: Programmable Logic Array (PLA). Example: BCD to 7-segment trans-coder.
Both, decoder and encoders are programmable structures.
When PLA are used as hardware support the minimized form of Boolean functions (see Appendix C.4
for a short refresh) are needed. In the previous example for each inverted output its minimized Boolean
expression was computed.
The main eect of substituting, whenever is possible, ROMs with PLAs are:
6.3. CONCLUDING ABOUT COMBINATIONAL CIRCUITS
149
the number of decoder outputs decreases

the size of circuits that implements the decoder decreases (some or all minterms are substituted
with less terms)
the number of inputs of the NANds on the output level also decreases.
There are applications supposing ROMs with a very random content, so as the equivalent PLA has
the same ar almost the same size and the eort to translate the ROM into a PLA does not deserve. A
typical case is when we store into a ROM a program executed by a computing machine. No regularities
are expected in such an applications.
It is also surprising the eciency of a PLA in solving pure Boolean problems which occur in current
digital designs. A standard PLA circuit, with 16 inputs, 8 outputs and only 48 programmable (min)terms
on the rst decoding level, is able to solve a huge amount of pure logic (non-arithmetic) applications. A
full decoder in a ROM circuit computes 66536 minterms, and the previous PLA is designed to support
no more than 48 terms!
Warning! For arithmetic applications PLA are extremely inecient. Short explanation: a 16-input
XOR supposes 32768 minterms to be implemented, but a 16-input AND can be computed using one
minterm. The behavioral diversity to the output of an adder is similar with the behavioral diversity on
its inputs. But the diversity on the output of 8-input NAND is almost null. The probability of 1 on the
output of 16-input AND is 1/216 = 0.000015.
6.3
Concluding about combinational circuits
The goal of this chapter was to introduce the main type of combinational circuits. Each presented
circuit is important rst, for its specic function and second, as a suggestion for how to build
similar ones. There are a lot of important circuits undiscussed in this chapter. Some of them
are introduced as problems at the end of this chapter.
Simple circuits vs. complex circuits Two very distinct class of combinational circuits
are emphasized. The rst contains simple circuits, the second contains complex circuits. The
complexity of a circuit is distinct from the size of a circuit. Complexity of a circuit is given by
the size of the denition used to specify that circuit. Simple circuits can achieve big sizes because
they are dened using a repetitive pattern. A complex circuit can not be very big because its
denition is dimensioned related with its size.
Simple circuits have recursive denitions Each simple circuit is dened initially as an
elementary module performing the needed function on the smallest input. Follows a recursive
denition about how can be used the elementary circuit to dene a circuit working for any
input dimension. Therefore, any big simple circuit is a network of elementary modules which
expands according to a specic rule. Unfortunately, the actual HDL, Verilog included, are not
able to manage without (strong) restrictions recursive denitions neither in simulation nor in
synthesis. The recursiveness is a property of simple circuits to be fully used only for our mental
experiences.
Speeding circuits means increase their size Depth and size evolve in opposite directions.
If the speed increases, the pay is done in size, which also increases. We agree to pay, but in
digital systems the pay is not fair. We conjecture the bigger is performance the bigger is the
unit price. Therefore, the pay increases more than the units we buy. It is like paying urgency
tax. If the speed increases n times, then the size of the circuit increases more than n times,
which is not fair but it is real life and we must obey.
150
CHAPTER 6. GATES:
Big sized complex circuits require programmable circuits There are software tolls for
simulating and synthesizing complex circuits, but the control on what they generate is very low.
A higher level of control we have using programmable circuits such as ROMs or PLA. PLA are
ecient only if non-arithmetic functions are implemented. For arithmetic functions there are a
lot of simple circuits to be used. ROM are ecient only if the randomness of the function is
very high.
Circuits represent a strong but ineective computational model Combinational circuits represent a theoretical solution for any Boolean function, but not an eective one. Circuits
can do more than algorithms can describe. The price for their universal completeness is their
ineectiveness. In the general case, both the needed physical structure (a tree of EMUXs) and
the symbolic specication (a binary string) increase exponentially with n (the number of binary
input variables). More, in the general case only a family of circuits represents the solution.
To provide an eective computational tool new features must be added to a digital machine and some restrictions must be imposed on what is to be computable. The next chapters
will propose improvements induced by successively closing appropriate loops inside the digital
systems.
6.4
Problems
Gates
Problem 6.1 Determine the relation between the total number, N , of n-input m-output Boolean
functions (f : {0, 1}n {0, 1}m ) and the numbers n and m.
Problem 6.2 Let be a circuit implemented using 32 3-input AND gates. Using the appendix
evaluate the area if 3-input gates are used and compare with a solution using 2-input gates.
Analyze two cases: (1) the fan-out of each gate is 1, (2) the fan-out of each gate is 4.
Decoders
Problem 6.3 Draw DCD4 according to Denition 2.9. Evaluate the area of the circuit, using
the cell library from Appendis E, with the placement eciency5 70%. Estimate the maximum
propagation time. The wires are considered enough short to be ignored their contribution in
delaying signals.
Problem 6.4 Design a constant depth DCD4 . Draw it. Evaluate the area and the maximum
propagation time using the cell library from Appendix E. Compare the results with the results of
the previous problem.
Problem 6.5 Propose a recursive denition for DCDn using EDMUXs. Evaluate the size and
the depth of the resulting structure.
Multiplexors
Problem 6.6 Draw M U X4 using EMUX. Make the structural Verilog design for the resulting
circuit. Organize the Verilog modules as hierarchical as possible. Design a tester and use it to
test the circuit.
5
For various reason the area used to place gates on Silicon can not completely used. Some unused spaces
remain between gates. Area eciency measures the degree of area use.
6.4. PROBLEMS
151
Problem 6.7 Dene the 2-input XOR circuit using an EDCD and an EMUX.
Problem 6.8 Make the Verilog behavioral description for a constant depth left shifter by maximum m 1 positions for m-bit numbers, where m = 2n . The header of the project is:
module left_shift( output
input
input
...
endmodule
[2m-2:0]
[m-1:0]
[n-1:0]
out
in
shift
,
,
);
Problem 6.9 Make the Verilog structural description of a log-depth (the depth is log2 16 = 4)
left shifter by 16 positions for 16-bit numbers. Draw the resulting circuit. Estimate the size and
the depth comparing the results with a similar shifter designed using the solution of the previous
problem.
Problem 6.10 Draw the circuit described by the Verilog module leftRotate in the subsection
Shifters.
Problem 6.11 A barrel shifter for m-bit numbers is a circuit which rotate the bits the input
word a number of positions indicated by the shift code. The header of the project is:
module barrel_shift(
output
input
input
[m-1:0] out
[m-1:0] in
[n-1:0] shift
,
,
);
...
endmodule
Write a behavioral code and a minimal structural version in Verilog.
Prex network
Problem 6.12 A prex network for a certain associative function f ,
Pf (x0 , x1 , . . . xn1 ) = {y0 , y1 , . . . yn1 }
receives n inputs and generate n outputs dened as follows:
y0 = f (x0 )
y1 = f (x0 , x1 )
y2 = f (x0 , x1 , x2 )
...
yn1 = f (x0 , x1 , . . . xn1 ).
Design the circuit POR (n) for n = 16 in two versions: (1) with the smallest size, (2) with
the smallest depth.
Problem 6.13 Design POR (n) for n = 8 and the best product size depth.
Problem 6.14 Design Paddition (n) for n = 4. The inputs are 8-bit numbers. The addition is a
mod256 addition.
152
CHAPTER 6. GATES:
Recursive circuits
Problem 6.15 A comparator is circuit designed to compare two n-bit positive integers. Its
denition is:
module comparator( input
input
output
output
output
...
endmodule
[n-1:0] in1 ,
[n-1:0] in2 ,
eq ,
lt ,
gt );
//
//
//
//
//
first operand
second operand
in1 = in2
in1 < in2
in1 > in2
1. write the behavioral description in Verilog

2. write a structural description optimized for size
3. design a tester which compare the results of the simulations of the two descriptions: the
behavioral description and the structural description
4. design a version optimized for depth
5. dene an expandable structure to be used in designing comparators for bigger numbers in
two versions: (1) optimized for depth, (2) optimized for size.
Problem 6.16 Design a comparator for signed integers in two versions: (1) for negative numbers represented in 2s complement, (2) for negative numbers represented a sign and number.
Problem 6.17 Design an expandable priority encoder with minimal size starting from an elementary priority encoder, EPE, dened for n = 2. Evaluate its depth.
Problem 6.18 Design an expandable priority encoder, P E(n), with minimal depth.
Problem 6.19 What is the numerical function executed by a priority encoder circuit if the input
is interpreted as an n-bit integer, the output is an m-bit integer and n ones is a specic warning
signal?
Problem 6.20 Design the Verilog structural descriptions for an 8-input adder in two versions:
(1) using 8 FAs and a ripple carry connection, (2) using 8 HAs and a carry look ahead circuit.
Evaluate both solutions using the cell library from Appendix E.
Problem 6.21 Design an expandable carry look-ahead adder starting from an elementary circuit.
Problem 6.22 Design an enabled incrementer/decrementer circuit for n-bit numbers. If en =
1, then the circuit increments the input value if inc = 1 or decrements the input value if inc = 0,
else, if en = 0, the output value is equal with the input value.
Problem 6.23 Design an expandable adder/subtracter circuit for 16-bit numbers. The circuit
has a carry input and a carry output to allow expandability. The 1-bit command input is sub. For
sub = 0 the circuit performs addition, else it subtracts. Evaluate the area and the propagation
time of the resulting circuit using the cell library from Appendix E.
Problem 6.24 Provide a divide et impera solution for the circuit performing firstDetect
function.
6.4. PROBLEMS
153
Random circuits
Problem 6.25 The Gray counting means to count, starting from 0, so as at each step only one
bit is changed. Example: the three-bit counting means 000, 001, 011, 010, 110, 111, 101, 100,
000, ... Design a circuit to convert the binary counting into the Gray counting for 8-bit numbers.
Problem 6.26 Design a converter from Gray counting to binary counting for n-bit numbers.
Problem 6.27 Write a Verilog structural description for ALU described in Example 2.3. Identify the longest path in the resulting circuit. Draw the circuit for n = 8.
Problem 6.28 Design a 8-bit combinational multiplier for a7 , . . . a0 and b7 , . . . b0 , using as basic
brick the following elementary multiplier, containing a FA and an AND:
module em(carry_out, sum_out, a, b, carry, sum);
input
a, b, carry, sum;
output carry_out, sum_out;
assign {carry_out, sum_out} = (a & b) + sum + carry;
endmodule
Problem 6.29 Design an adder for 32 1-bit numbers using the carry save adder approach.
Hint: instead of using the direct solution of a binary tree of adders a more ecient way (from
the point of view of both size and depth) is to use circuits to compact the numbers. The
rst step is presented in Figure 6.42, where 4 1-bit numbers are transformed in two numbers,
a 1-bit number and a 2-bit number. The process is similar in Figure 6.43 where 4 numbers, 2
1-bit numbers and 2 2-bit numbers are compacted as 2 numbers, one 2-bit number and one 3-bit
number. The result is a smaller and a faster circuit than a circuit realized using adders.
in[3:0]
???
????
210
FA
3210
csa4
xx
0x
?? ??
a.
?? ??
out1[1:0]out0[1:0]
b.
Figure 6.42: 4-bit compacter.

Compare the size and depth of the resulting circuit with a version using adders.
Problem 6.30 Design in Verilog the behavioral and the structural description of a multiply
and accumulate circuit, MACC, performing the function: (a b) + c, where a and b are 16-bit
numbers and c is a 24-bit number.
Problem 6.31 Design the combinational circuit for computing
c=
ai bi
i=0
where: ai , bi are 16-bit numbers. Optimize the size and the depth of the 8-number adder using a
technique learned in one of the previous problem.
154
CHAPTER 6. GATES:
csa4
0x xx
7 654
3 210
FA
FA
HA
FA
csa4
0x xx
HA
0 (3)
x
- x0 csa4 +
0 0 xx
x (3)
x
- xx csa4
0x xx
out0
3
a.
xxx
?
out0
3
0xx
out1
out1
b.
Figure 6.43: 8-bit compacter.

Problem 6.32 Exemplify the serial composition, the parallel composition and the serial-parallel
composition in 0 order systems.
Problem 6.33 Write the logic equations for the BCD to 7-segment trans-coder circuit in both
high active outputs version and low active outputs version. Minimize each of them individually.
Minimize all of them globally.
Problem 6.34 Applying removing rules and reduction rules nd the functions performed by
5-level universal circuit programmed by the following binary strings:
1. (0100)8
2. (01000010)4
3. (0100001011001010)2
4. 024 (01000010)
5. 00000001001001001111000011000011
Problem 6.35 Compute the biggest size and the biggest depth of an n-input, 1-output circuit
implemented using the universal circuit.
Problem 6.36 Provide the prof for Zero-One Principle.
6.5
Projects
Project 6.1 Finalize Project 1.1 using the knowledge acquired about the combinational structures in this chapter.
Project 6.2 Design a combinational oating point single precision (32 bit) multiplier according
to the ANSI/IEEE Standard 754-1985, Standard for Binary Floating Point Arithmetic.
Chapter 7
MEMORIES:
First order, 1-loop digital systems
the main combinational, no-loop circuits were presented with emphasis on
the simple, pattern-based basic combinational circuits performing functions like: decode using demultiplexors, selection using multiplexors, increment, add, various selectable functions using arithmetic
and logic units, compare, shift, priority encoding, ...
the dierence between the simple circuits, which grow according to recursive rules, and the complex,
pattern-less circuits whose complexity must be kept at lowest possible level
the compromise between area and speed, i.e., how to save area accepting to give up the speed, or
how can be increased the speed accepting to enlarge the circuits area.
In this chapter
the rst order, one-loop circuits are introduced studying
how to close the rst loop inside a combinational circuit in order to obtain a stable
and useful behavior
the elementary storage support the latch and the way to expand it using the
serial, parallel, and serial-parallel compositions leading to the basic memory circuits,
such as: the master-slave ip-op, the random access memory and the register
how to use rst order circuits to design basic circuits for real applications, such as
register les, content addressable memories, associative memories or systolic systems.
In the next chapter
the second order, automata circuits are described. While the rst order circuits have the smallest degree of
autonomy they are able only to maintain a certain state the second order circuits have an autonomous
behavior induced by the loop just added. The following circuits will be described:
the simplest and smallest elementary, two-state automata: the T ip-op and JK ip-op, which
besides the storing function allow an autonomous behavior under a less restrictive external command
simple automata performing recursive functions, generated by expanding the function of the simplest
two-state automata (example: n-bit counters)
the complex, nite automata used for control or for recognition and generation of regular streams of
symbols.
155
156
CHAPTER 7. MEMORIES:
FIRST ORDER, 1-LOOP DIGITAL SYSTEMS
The magic images were placed on the wheel of the memory system to which correspondent other wheels on which
were remembered all the physical contents of the terrestrial
world elements, stones, metals, herbs, and plants, animals, birds, and so on and the whole sum of the human
knowledge accumulated through the centuries through the
images of one hundred and fty great men and inventors.
The possessor of this system thus rose above time and reected the whole universe of nature and of man in his mind.
Frances A. Yates1
A true memory is an associative one. Please do not confuse
the physical support the random access memory with the
function the associative memory.
According to the mechanisms described in Chapter 3 of this book, the step toward a new
class of circuits means to close a new loop. This will be the rst loop which closed over the
combinational circuits already presented. Thus, a rst degree of autonomy will be reached in
digital systems: the autonomy of the state of the circuit. Indeed, the state of the circuit will be
partially independent by the input signals, i.e., the output of the circuits do not depend on or
not respond to certain input switching.
In this chapter we introduce some of the most important circuits used for building digital
systems. The basic function in which they are involved is the memory function. Some events
on the input of a memory circuit are signicant for the state of the circuits and some are not.
Thus, the circuit memorizes, by the state it reaches, the signicant events and ignores the
rest. The possibility to have an attitude against the input signals is given to the circuit by the
autonomy induced by its internal loop. In fact, this rst loop closed over a simple combinational
circuit makes insignicant some input signals because the circuit is able to compensate their
eect using the signals received back from its output.
The main circuits with one internal loop are:
the elementary latch - the basic circuit in 1-OS, containing two appropriately loopcoupled gates; the circuit has two stable states being able to store 1 bit of information
the clocked latch - the rst digital circuit which accepts the clock signal as an input
distinct from data inputs; the clock signal determines by its active level when the latch is
triggered, while the data input determines how the latch switches
the master-slave ip-op - the serial composition in 1-OS, built by two clocked latches
serially connected; results a circuit triggered by the active transition of clock
the random access memory (RAM) - the parallel composition in 1-OS, containing a
set of n clocked elementary latches accessed with a DM U Xlog2 n and a M U Xlog2 n
the register - the serial-parallel composition in 1-OS, made by parallel connecting masterslave ip-ops.
These rst order circuits dont have a direct computational functionality, but are involved
in supporting the following main processes in a computational machine:
1
She was Reader in the History of the Renaissance at the University of London. The quote is from Giordano
Bruno and the Hermetic Tradition. Her other books include The Art of Memory.
7.1. STABLE/UNSTABLE LOOPS
157
oer the storage support for implementing various memory functions (register les, stacks,
queues, content addressable memories, associative memories, ...)
are used for synchronizing dierent subsystems in a complex system (supports the pipeline
mechanism, implements delay lines, stores the state of automata circuits).
7.1
Stable/Unstable Loops
There are two main types of loops closed over a combinational logic circuit: loops generating a
stable behavior and loops generating an unstable behavior. We are interested in the rst kind
of loop that generates a stable state inside the circuit. The other loop cannot be used to build
anything useful for computational purposes, except some low performance signal generators.
The distinction between the two types of loops is easy exemplied closing loops over the
simplest circuit presented in the previous chapter, the elementary decoder (see Figure 7.1a).
The unstable loop is closed connecting the output y0 of the elementary decoder to its input
x0 (see Figure 7.1b). Suppose that y0 = 0 = x0. After the time interval equal with tpLH 2 the
output y0 becomes 1. After another time interval equal with tpHL the output y0 becomes again
0. And so on, the two outputs of the decoder are unstable oscillating between 0 and 1 with a
period of time Tosc = tpLH + tpHL , or the frequency fosc = 1/(tpLH + tpHL ).
y1
x0
y0
a.
y1
x0
out1
y1
x0
EDCD
EDCD
y0
b.
y0
out2
c.
Figure 7.1: The two loops closed over an elementary decoder. a. The simplest combinational circuit: the one-input, elementary decoder. b. The unstable, inverting loop containing one (odd)
inverting logic level(s). c. The stable, non-inverting loop containing two (even) inverting levels.
The stable loop is obtained connecting the output y1 of the elementary decoder to the input
x0 (see Figure 7.1c). If y1 = 0 = x0, then y0 = 1 xing again the value 0 to the output y1.
If y1 = 1 = x0, then y0 = 0 xing again the value 1 to the output y1. Therefore, the circuit
has two stable states. (For the moment we dont know how to switch from one state to another
state, because the circuit has no input to command the switching from 0 to 1 or conversely. The
solution comes soon.)
What is the main structural distinction between the two loops?
The unstable loop has an odd number of inverting levels, thus the signal comes back to
the output having the complementary value.
The stable loop has an even number of inverting levels, thus the signal comes back to the
output having the same value.
2
the propagation time through the inverter when the output switches from the low logic level to the high level.
158
Example 7.1 Let be the circuit from Figure 7.2a, with 3 inverting levels on its internal loop.
If the command input C is 0, then the loop is opened, i.e., the ow of the signal through the
circular way is interrupted. If C switches in 1, then the behavior of the circuit is described by the
wave forms represented in Figure 7.2b. The circuit generates a periodic signal with the period
Tosc = 3(tpLH + tpHL ) and frequency fosc = 1/3(tpLH + tpHL ). (To keep the example simple we
consider that tpLH and tpHL have the same value for the three circuits.)
C
C
6
-
l1
l1
out
l2
- tpHL
6
out
-
6
l2
a.
tpLH
b.
Figure 7.2: The unstable loop. The circuit version used for a low-cost and low-performance clock
generator. a. The circuit with a three (odd) inverting circuits loop coupled. b. The wave forms drawn
takeing into account the propagation times associated to the low-high transitions (tpLH ) and to the
high-low transitions (tpHL ).
In order to be useful in digital applications, a loop closed over a combinational logic circuit
must contain an even number of inverting levels for all binary combinations applied to its inputs.
Else, for certain or for all input binary congurations, the circuit becomes unstable, unuseful
for implementing computational functions. In the following, only even (in most of cases two)
number of inverting levels are used for building the circuits belonging to 1-OS.
7.2
7.2.1
Elementary Structures
Elementary Latches
This chapter is devoted to introduce the elementary structure used to build memory systems:
ip-ops, registers and random access memories. In order to be stable, all these elementary
circuits have one loops with even (zero or two) inverting levels.
The reset-only latch is the AND loop circuit represented in Figure 7.3a. The passive input
value forAND loop is 1 ((Reset) = 1), while the active input value is 0 ((Reset) = 0). If
the passive input value is applied, then the output of the circuits is not aected (the output
depends only by the other input of the AND circuit). It can be 0 or 1, depending by the previous
values applied on the input. When the active value is temporary applied, then the state of the
circuit (the value of its output) switches in 0 and remains forever in this state, independent on
the input value. We conclude that the circuit is sensitive to the signal 0 temporarily applied on
its input, i.e., it is able to memorize forever the event 0.
7.2. ELEMENTARY STRUCTURES
159
The set-only latch is the OR loop circuit represented in Figure 7.3b. The passive value for
OR loop is 0 (Set = 0) while the active input value is 1 (Set = 1). If the passive input value
is applied, then the output of the circuits is not aected (the output depends only by the other
input of the OR circuit). It can be 0 or 1, depending by the previous values applied on the
input. When the active value is temporary applied, then the state of the circuit (the value of
its output) switches in 1 and remains forever in this state, independent on the input value. We
conclude that the circuit is sensitive to the signal 1 temporarily applied on its input, i.e., it is
able to memorize forever the event 1.
R
Set
(Reset)
out
out
a.
out
c.
b.
Q
Q
d.
e.
Figure 7.3: The elementary latches. Using the stable non-inverting loop (even inverting levels)
elementary storage elements are built. a. AND loop provides a reset-only latch. b. OR loop provides the
set-only version of a storage element. c. The heterogeneous elementary set-reset latch results combining
the reset-only latch with the set-only latch. d. Symmetric elementary NAND latch with low-active
commands S and R. e. Symmetric elementary NOR latch with high-active commands S and R.
The heterogenous set-reset latch results by combining the previous two latches (see Figure
7.3c). The circuit has zero inverting levels on the loop and two inputs: one active-low (active
on 0) input, R, to reset the circuit (out = 0) and another active-high (active on 1) input, S, to
set the circuit (out = 0). The value 0 must remain to the input R at least 2tpHL for a stable
switching of the circuit into the state 0, because the loop depth in the state 1 is given by the
propagation time through both gates that switch from high to low. For a similar reason, the
value 1 must remain to the input S at least 2tpLH when the circuit must switch in 1.
The symmetric set-reset latch is obtained by applying De Morgans law to the heterogenous elementary latch. In the rst version, the OR circuit is transformed by De Morgans law
resulting the circuit from Figure 7.3d. The second version (see Figure 7.3e) is obtained applying
the same law to the AND circuit. The passive input value for the NAND elementary latch is 1,
while for the NOR elementary latch it is 0. The avtive input value for the NAND elementary
latch is 0, while for the NOR elementary latch it is 1. The symmetric structure of these latches
have two outputs, Q and Q.
VeriSim 7.1 The Verilog description of NAND latch is:
module elementary_latch(output out, not_out,
input not_set, not_reset);
nand
#2 nand0(out, not_out, not_set);
160
nand
endmodule
#2
nand1(not_out, out, not_reset);
For testing the behavior of the NAND latch just described, the following module is used:
module test_shortest_input;
reg
not_set, not_reset;
initial begin
not_set
not_reset
#10 not_reset
#10 not_reset
#10 not_set
#10 not_set
//#1 not_set
//#2 not_set
//#3 not_set
#10 not_set
#10 not_set
#10 not_reset
#10 not_reset
#10 $stop;
=
=
=
=
=
=
=
=
=
=
=
=
=
1;
1;
0;
1;
0;
1;
1;
1;
1;
0;
1;
0;
1;
// reset
//
//
//
//
//
//
set
1-st experiment
2-nd experiment
3-rd experiment
4-th experiment
another set
// reset
end
elementary_latch
endmodule
dut(out, not_out, not_set, not_reset);
In the rst experiment the set signal is activated on 0 during 10ut (ut stands for unit time).
In the second experiment (comment the line 9 and de-comment the line 10 of the test module),
a set signal of 1ut is unable to switch the circuit. The third experiment, with 2ut set signal,
generate an unstable simulated, but non-actual, behavior (to be explained by the reader). The
fourth experiment, with 3ut set signal, determines the shortest set signal able to switch the latch
(to be explained by the reader).
In order to use these latches in more complex applications we must solve two problems.
The rst latch problem : the inputs for indicating how the latch switches are the same as
the inputs for indicating when the latch switches; we must nd a solution for declutching the
two actions building a version with distinct inputs for specifying how and when
The second latch problem : if we apply synchronously S=0 and R=0 on the inputs of
NAND latch (or S=1 and R=1 on the inputs of OR latch), i.e., the latch is commanded to
switch in both states simultaneously, then we can not predict what is the state of the latch
after the ending of these two active signals.
The rst latch problem will be partially solved in the next paragraph introducing the clocked
latch, but the problem will be completely solved only by introducing the master-slave structure.
The second latch problem will be solved only in the next chapter with the JK ip-op, because
the circuit needs more autonomy to solve the contradictory command that says him to
switch in both states simultaneously. And, as we already know, more autonomy means at least
a new loop.
161
Application: debouncing circuit Interfacing digital systems with the real world involves
sometimes the use of mechanical switching contacts. The bad news is that this kind of contact
does not provide an accurate transition. Usually when it closes, a lot of parasitic bounces come
with the main transition (see wave forms S and R in Figure 7.4).
VDD
6
-
time
Q
Q
...
...
...
.
.....
.......
.
time
R
6
-
VDD
time
Figure 7.4: The debouncing circuit.

The debouncing circuit provide clean transitions when digital signals must generated by
electro-mechanical switches. In Figure 7.4 an RS latch is used to clear up the bounces generated
by a two-position electro-mechanical switch. The elementary latch latches the rst transition
from VDD to 0. The bounces that follow have no eect on the output Q because the latch is
already switched by the rst transition in the state they intend to lead the circuit.
7.2.2
Elementary Clocked Latches
In order to start solving the rst latch problem the elementary latch is supplemented with two
gates used to validate the data inputs only during the active level of clock. Thus the clocked
elementary latch is provided.
active level
CK
S
? ? ?
CK
RSL
Q
a.
b.
Figure 7.5: Elementary clocked latch. The transparent RS clocked latch is sensitive (transparent)
to the input signals during the active level of the clock (the high level in this example). a. The internal
structure. b. The logic symbol.
The NAND latch is used to exemplify (see Figure 7.5a) the partial separation between how
and when. The signals R and S for the NAND latch are generated using two 2-input NAND
gates. If the latch must be set, then on the input S we apply 1, R is maintained in 0 and, only
162
after that, the clock is applied, i.e., the clock input CK switches temporary in 1. In this case
the active level of the clock is the high level. For reset, the procedure is similar: the input R is
activated, the input S is inactivated, and then the clock is applied.
We said that this approach allows only a partial declutching of how by when because on the
active level of CK the latch is transparent, i.e., any change on the inputs S and R can modify
the state of the circuit. Indeed, if CK = 1 and S or R is activated the latch is set or reset, and
in this case how and when are given only by the transition of these two signals, S for set or R
for reset. The transparency will be avoided only when, in the next subsection, the transition of
the output will be triggered by the active edge of clock.
The clocked latch does not solve the second latch problem, because for R = S = 1 the end of
the active level of CK switches the latch in an unpredictable state.
VeriSim 7.2 The following Verilog code can be used to understand how the elementary clocked
latch works.
module clocked_nand_latch(output
out, not_out,
input
set, reset, clock);
elementary_latch the_latch(out, not_out, not_set, not_reset);
nand
#2 nand2(not_set, set, clock);
nand
#2 nand3(not_reset, reset, clock);
endmodule
7.2.3
Data Latch
In the rst order circuits class the second latch problem can be only avoided, not removed,
dening a restriction on the input of the clocked latch. Indeed, introducing an inverter between
the inputs of the RS clocked latch, as is shown in Figure 7.6a, the ambiguous command (simultaneous set and reset) can not be applied. We name the new input D (from Data). Now, the
situation R = S = 1 is avoided. The output is synchronized with the clock only if on the active
level of CK the input D is stable.
D
CK
D
S
RSL
Q
a.
CK
DL
b.
c.
Figure 7.6: The data latch. Imposing the restriction R = S to an RS latch results the D latch
without non-predictable transitions (R = S = 1 is not anymore possible). a. The structure. b. The
logic symbol. c. An improved version for the data latch internal structure.
The output of this new circuit, called D latch, follows all the time the input D. Therefore,
the autonomy of this circuit is questionable because act only in the time when the clock is
inactive (on the inactive level of the clock). We say D latch is transparent on the active level of
the clock signal, i.e, the output is sensitive to any input change during the active level of clock.
VeriSim 7.3 The following Verilog code can be used to describe the behavior of a D latch.
163
module data_latch( output reg out,

output
not_out,
input
data, clock);
always @(data or clock) if (clock) out = data;
assign not_out = ~out;
endmodule
The main problem when data input D is separated by the timing input CK is the correlation
between them. When this two inputs change in the same time, or, more precisely, during the
same small time interval, some behavioral problems occur. In order to obtain a predictable
behavior we must obey two important time restrictions: the set-up time and the hold time.
In Figure 7.6c an improved version of the circuit is presented. The number of components
are minimized, the maximum depth of the circuit is maintained and the fan-in for the input D
is reduced from 2 to 1.
VeriSim 7.4 The following Verilog code can be used to understand how a D latch works.
module test_data_latch;
reg
data, clock;
initial begin
end
initial begin
clock = 0;
data = 0;
#25 data = 1;
#10 data = 0;
#20 $stop;
end
data_latch dut(out, not_out, data, clock);
endmodule
module data_latch(output
input
not #2
out, not_out,
data, clock);
data_inverter(not_data, data);
clocked_nand_latch
endmodule
rs_latch(out, not_out, data, not_data, clock);
The second initial construct from test data latch module can be used to apply data in
dierent relation with the clock.
The internal structure of the data latch (4 2-input NANDs and an inverter in Figure 7.6a)
can be minimized opening the loop by disconnecting the output Q from the input of the gate
generating Q , and renaming it C. The resulting circuit is described by the following equation:
Q = ((D CK) (C(D CK) ) )
which can be successively transformed as follows:
Q = ((D CK) + (C(D CK) )
Q = ((D CK) + (C(D + CK ))
Q = D CK + C D + C CK (anti hasard redundancy)
164
D
CK
in1
in0
CK
sel
EMUX
out
Q
Q
a.
b.
Figure 7.7: The optimized data latch. An optimized version is implemented closing the loop over
an elementary multiplexer, EMUX. a. The resulting minimized structure for the circuit represented in
Figure 7.6a. b. Implementing the minimized form using only inverting circuits.
Q = D CK + C CK
The resulting circuit is an elementary multiplexor (the selection input is CK and the selected
inputs are D, by CK = 1, and C, by CK = 0. Closing back the loop, by connecting Q to C,
results the circuit represented in Figure 7.7a. The actual circuit has also the inverted output
Q and is implemented using only inverted gates as in Figure 7.7b. The circuit from Figure
7.6a (using the RSL circuit from Figure 7.5a) is implemented with 18 transistors, instead of 12
transistors supposed by the minimized form Figure 7.7b.
VeriSim 7.5 The following Verilog code can be used as one of the shortest description for a D
latch represented in Figure 7.7a.
module mux_latch(
assign
endmodule
output q
input
d, ck
q = ck ? d : q;
,
);
In the previous module the assign statement, describing an elementary multiplexer, contains
the loop. The variable q depends by itself. The code is synthesisable.
The elementary decoder was used to start the discussion about latches (see Figure 7.1). We
ended using the elementary multiplexer to describe the most complex latch.
7.3
The Serial Composition: the Edge Triggered Flip-Flop
The rst composition in 1-order systems is the serial composition, represented mainly by:
the master-slave structure as the main mechanism that avoids the transparency of the
storage structures
the delay ip-op, the basic storage circuit that allows to close the second loop in the
synchronous digital systems
the serial register, the st big and simple memory circuit having a recursive denition.
7.3. THE SERIAL COMPOSITION: THE EDGE TRIGGERED FLIP-FLOP
165
This class of circuits allows us to design synchronous digital systems. Starting from this
point the inputs in a digital system are divided in two categories:
clock inputs for synchronizing dierent parts of a digital system
data and control inputs that receive the informational ow inside a digital system.
7.3.1
The Master-Slave Principle
In order to remove the transparency of the clocked latches, disconnecting completely the how
from the when, the master-slave principle was introduced. This principle allows us to build a
two state circuit named ip-op that switches synchronized with the rising or falling edge of the
clock signal.
S
active edge
?
9
???
CK
S CK R
RSL
Q
Q
RSF-F
S CK R
RSL
Q
Q
a.
Q
b.
Figure 7.8: The master-slave principle. Serially connecting two RS latches, activated with
dierent levels of the clock signal, results a non-transparent storage element. a. The structure of a
RS master-slave ip-op, active on the falling edge of the clock signal. b. The logic symbol of the RS
ip-op.
The principle consists in serially connecting two clocked latches and in applying the clock
signal in opposite on the two latches (see Figure 7.8). In the exemplied embodiment the rst
latch is transparent on the high level of clock and the second latch is transparent on the low
level of clock. (The symmetric situation is also possible: the rst latch is transparent of the
low level value of clock and the second no the high value of clock.) Therefore, there is no time
interval in which the entire structure is transparent. In the rst phase, CK = 1, the rst latch
is transparent - we call it the master latch - and it switches according to the inputs S and R.
In the second phase CK = 0 the second latch - the slave latch - is transparent and it switches
copying the state of the master latch. Thus the output of the entire structure is modied only
synchronized with the negative transition of CK. We say the RS master-slave ip-op switches
with the falling (negative) edge of the clock. (The version triggered by the positive edge of clock
is also possible.)
The switching moment of a master-slave structure is determined exclusively by the active
edge of clock signal. Unlike the RS latch or data latch, which can sometimes be triggered (in the
transparency time interval) by the transitions of the input data (R, S or D), the master-slave
ip-op ips only at the positive edge of clock (always @(posedge clock)) or at the negative
edge of clock (always @(negedge clock)) edge of clock, according with the values applied on
the inputs R and S. The how is now completely separated from the when. The rst latch problem
is nally solved.
VeriSim 7.6 The following Verilog code can be used to understand how a master-slave ip-op
works.
166
module master_slave(output out, not_out, input set, reset, clock);

wire
master_out, not_master_out;
clocked_nand_latch
master_latch(
slave_latch(
.out
(master_out
.not_out(not_master_out
.set
(set
.reset (reset
.clock (clock
.out
(out
.not_out(not_out
.set
(master_out
.reset (not_master_out
.clock (~clock
),
),
),
),
)),
),
),
),
),
));
endmodule
There are some other embodiments of the master-slave principle, but all suppose to connect
latches serially.
Three very important time intervals must catch our attention in designing digital systems
with edge triggered ip-ops:
set-up time (tSU ) the time interval before the active edge of clock in which the inputs R
and S must stay unmodied allowing the correct switch of the ip-op
edge transition time (t+ or t ) the positive or negative time transition of the clock signal
(see Figure 2.9)
hold time (tH ) the time interval after the active edge of CK in which the inputs R and S
must be stable (even if this time is zero or negative).
In the switching moment, that is approximated by the time interval tSU +t+ +tH or tSU +t +tH
centered on the active edge (+ or ), the data inputs must evidently be stable, because
otherwise the ip-op does not know what is the state in which he must switch.
Now, the problem of decoupling the how by the when is better solved. Although, this solution
is not perfect, because the moment of the switch is approximated by the short time interval
tSU + t+/ + tH . But the moment does not exist for a digital designer. Always it must be a
time interval, enough over-estimated for an accurate work of the designed machine.
7.3.2
The D Flip-Flop
Another tentative to remove the second latch problem leads to a solution that again avoids
only the problem. Now the RS master-slave ip-op is restricted to R = S (see Figure 7.9a).
The new input is named also D, but now D means delay. Indeed, the ip-op resulting by
this restriction, besides avoiding the unforeseeable transition of the ip-op, gains a very useful
function: the output of the D ip-op follows the D input with a delay of one clock cycle.
Figure 7.9c illustrates the delay eect of this kind of ip-op.
Warrning! D latch is a transparent circuit during the active level of the clock, unlike the
D ip-op which is no time transparent and switches only on the active edge of the clock.
VeriSim 7.7 The structural Verilog description of a D ip-op, provided only for simulation
purpose, follows.
7.3. THE SERIAL COMPOSITION: THE EDGE TRIGGERED FLIP-FLOP

module dff(output
input
wire
not_d;
not #2
167
out, not_out,
d, clock
);
data_inverter(not_d, d);
master_slave
endmodule
rs_ff(out, not_out, d, not_d, clock);
CK
R
RSF-F
Q
Q
a.
?
-
DF-F
b.
c.
Figure 7.9: The delay (D) ip-op. Restricting the two inputs of an RS ip-op to D = S = R ,
results an FF with predictable transitions. a. The structure. b. The logic symbol. c. The wave forms
proving the delay eect of the D ip-op.
The functional description currently used for a D ip-op active on the negative edge of clock
is:
module dff(output
input
reg out
,
d, clock);
always @(negedge clock) out <= d;

endmodule
The main dierence between latches and ip-ops is that over the D ip-op we can close
a new loop in a very controllable fashion, unlike the D latch which allows a new loop, but the
resulting behavior is not so controllable because of its transparency. Closing loops over D ipops result in synchronous systems. Closing loops over D latches result asynchronous systems.
Both are useful, but in the rst kind of systems the complexity is easiest manageable.
7.3.3
The Serial Register
Starting from the delay function of the last presented circuit (see Figure 7.9) a very important
function and the associated structure can be dened: the serial register. It is very easy to give
a recursive denition to this simple circuit.
Denition 7.1 An n-bit serial register, SRn , is made by serially connecting a D ip-op with
an SRn1 . SR1 is a D ip-op.
In Figure 7.10 is shown a SRn . It is obvious that SRn introduces a n clock cycle delay
between its input and its output. The current application is for building digital controlled
delay lines.
168
IN
-D
DF-F
Q
...
RSF-F
-R
CK
OUT
RSF-F
...
-R
...
Figure 7.10: The n-bit serial register (SRn ). Triggered by the active edge of the clock, the
content of each RSF-F is loaded with the content of the previous RSF-F.
We hope that now it is very clear what is the role of the master-slave structure. Let us
imagine a serial register built with D latches! The transparency of each element generates
the strange situation in which at each clock cycle the input is loaded in a number of latches
that depends by the length of the active level of the clock signal and by the propagation time
through each latch. Results an uncontrolled system, useless for any application. Therefore, for
controlling the propagation with the clock signal we must use the master-slave, non-transparent
structure of D ip-op that switches on the positive or negative edge of clock.
VeriSim 7.8 The functional description currently used for an n-bit serial register active on the
positive edge of clock is:
module serial_register #(parameter
reg[0:n-1]
n = 1024)(output out
,
input in, enable, clock);
serial_reg;
assign out = serial_reg[n-1];

if (enable) serial_reg = {in, serial_reg[0:n-2]};
endmodule
7.4
The Parallel Composition: the Random Access Memory
The parallel composition in 1-OS provides the random access memory (RAM), which is the main
storage support in digital systems. Both, data and programs are stored on this physical support
in dierent forms. Usually we call these circuits improperly memories, even if the memory
function is something more complex, which suppose besides a storage device a specic access
mechanism for the stored information. A true memory is, for example, an associative memory
(see the next subchapters about applications), or a stack memory (see next chapter).
This subchapter introduces two structures:
a trivial composition, but a very useful circuit: the n-bit latch
the asynchronous random access memory (RAM),
both involved in building big but simple recursive structures.
7.4.1
The n-Bit Latch
The n-bit latch, Ln , is made by parallel connecting n data latches clocked by the same CK. The
system has n inputs and n outputs and stores an n-bit word. Ln is a transparent structure on
the active level of the CK signal. The n-bit latch must be distinguished by the n-bit register
7.4. THE PARALLEL COMPOSITION: THE RANDOM ACCESS MEMORY
169
(see the next section) that switches on the edge of the clock. In a synchronous digital system is
forbidden to close a combinational loop over Ln .
VeriSim 7.9 A 16-bit latch is described in Verilog as follows:
module
n_latch #(parameter n = 16)(output reg [n-1:0] out

input
[n-1:0] in
input
clock
always @(in or clock)
if (clock == 1)
// the active-high clock version
//if (clock == 0)
// the active-low clock version
out = in;
endmodule
,
,
);
The n-bit latch works like a memory, storing n bits. The only deciency of this circuit is
due to the access mechanism. We must control the value applied on all n inputs when the latch
changes its content. More, we can not use selectively the content of the latch. The two problems
are solved adding some combinational circuits to limit both the changes and the use of the stored
bits.
7.4.2
Asynchronous Random Access Memory
Adding combinational circuits for accessing in a more exible way an m-bit latch for write and
read operations, results one of the most important circuits in digital systems: the random
access memory. This circuit is the biggest and simplest digital circuit. And we can say it can
be the biggest because it is the simplest.
-
WE
Om1
.
.
DM U Xp
O1
O0
Ap1 . . . A0
6
?
i0
i1
DOUT
? ?
CK
DL
Q
? ?
CK
DL
Q
...
DIN
? ?
CK
...
DL
Q

.
M U Xp
.
.
im1
Figure 7.11: The principle of the random access memory (RAM). The clock is distributed
by a DMUX to one of m = 2p DLs, and the data is selected by a MUX from one of the m DLs. Both,
DMUX and MUX use as selection code a p-bit address. The one-bit data DIN can be stored in the
clocked DL.
Denition 7.2 The m-bit random access memory, RAMm , is a linear collection of m D (data)
latches parallel connected, with the 1-bit common data inputs, DIN. Each latch receives the clock
signal distributed by a DM U Xlog2 m . Each latch is accessed for reading through a M U Xlog2 m .
170
The selection code is common for DMUX and MUX and is represented by the p-bit address code:
Ap1 , . . . , A0 , where p = log2 m.
The logic diagram associated with the previous denition is shown in Figure 7.11. Because
no one of the input signal is clock related, this version of RAM is considered an asynchronous
one. The signal W E is the low-active write enable signal. For W E = 0 the write operation is
performed in the memory cell selected by the address An1 , . . . , A0 .3 The wave forme describing
the relation between the input and output signals of a RAM are represented in Figure 7.12,
where the main time restrictions are the followings:
An1 . . . A0
6
a1
a2
a3
WE
tASU-
tDSU tDH

--
DIN
tW
-
tAH
6
data in
DOU T
-

-
tACC
d(a1)
d(a2)
d(a3)
data in
Figure 7.12: Read and write cycles for an asynchronous RAM. Reading is a combinational
process of selecting. The access time, tACC , is given by the propagation through a big MUX. The write
enable signal must be strictly included in the time interval when the address is stable (see tASU and tAH ).
Data must be stable related to the positive transition of W E (see tDSU and tDH ).
tACC : access time - the propagation time from address input to data output when the
read operation is performed; it is dened as a minimal value
tW : write signal width - the length of active level of the write enable signal; it is dened
as the shortest time interval for a secure writing
tASU : address set-up time related to the occurrence of the write enable signal; it is dened
as a minimal value for avoiding to disturb the content of other than the storing cell selected
by the current address applied on the address inputs
tAH : address hold time related to the end transition of the write enable signal; it is dened
as a minimal value for similar reasons
tDSU : data set-up time related to the end transition of the write enable signal; it is dened
as a minimal value that ensure a proper writing
tDH : data hold time related to the end transition of the write enable signal; it is dened
as a minimal value for similar reasons.
3
The actual implementation of this system uses optimized circuits for each 1-bit storage element and for the
access circuits. See Appendix C for more details.)
171
The just described version of a RAM represents only the asynchronous core of a memory
subsystem, which must have a synchronous behavior in order to be easy integrated in a robust
design. In Figure 7.11 there is no clock signal applied to the inputs of the RAM. In order to
synchronize the behavior of this circuit with the external world, additional circuits must be
added (see the rst application in the next subchapter: Synchronous RAM).
The actual organization of an asynchronous RAM is more elaborated in order to provide the
storage support for a big number of m-bit words.
VeriSim 7.10 The functional description of a asynchronous n = 2p m-bit words RAM follows:
module ram(input
[m-1:0]
din ,
// data input
input
[p-1:0]
addr,
// address
input
we ,
// write enable
output [m-1:0]
dout); // data out
reg
[m-1:0]
mem[(1b1<<p)-1:0];
assign
dout = mem[addr];
always @(din or addr or we) if (we) mem[addr] = din;

endmodule
// the memory
// reading memory
// writing memory
The real structural version of the storage array will be presented in two stages. First the
number of bits per word will be expanded, then the e solution for a big number of words number
of words will be presented.
Expanding the number of bits per word
The pure logic description oered in Figure 7.11 must be reconsidered in order (1) to optimize it
and (2) to show how the principle it describe can be used for designing a many-bit word RAM.
The circuit structure from Figure 7.13 represents the m-bit word RAM. The circuit is organized
in m columns, one for each bit of the m-bit word. The DMUX structure is shared all by the m
columns, while each column has it own MUX structure. Let us remember that both, the DMUX
and MUX circuits are structured around a DCD. See Figure 6.6 and 6.9, where the rst level
in both circuits is a decoder, followed by a linear network of 2-input ANDs for DMUX, and by
an AND-OR circuit for MUX. Then, only one decoder, DCDp , must be provided for the entire
memory. It is shared by the demultiplexing function and by the m multiplexors. Indeed, the
outputs of the decoder, LINEn1 , ... LINE1 , LINE0 , are used to drive:
one AND2 gate associate cu each line in the array, whose output clocks the DL latches
associated to one word; with these gates the decoder forms the demultimplexing circuit
used to clock, when WE = 1, the latches selected (addressed) by the current value of the
address: Ap1 , . . . A0
m AND2 gates, one in each column, selecting the read word to be ORed to the outputs
DOUTm1 , DOUTm2 , ... DOUT0 ; with the AND-OR circuit from each COLUMN the
decoder forms the multiplexor circuit associated to each output bit of the memory.
The array of lathes is organized in n and m columns. Each line is driven for write by the
output of a demultiplexer, while for the read function the addressed line (word) is selected by
the output of a decoder. The output value is gathered from the array using m multiplexors.
The reading process is a pure combinational one, while the writing mechanism is an asynchronous sequential one. The relation between the WE signal and the address bits is very
172
sensitive. Due to the combinational hazard to the output of DCD, the WE signal must be
activated only when the DCDs outputs are stabilized to the nal value, i.e., tASU before the
fall edge of WE or tH after the rise edge of WE.
On1
m-COLUMN BLOCK
LINEn1
CK
DL
Q
D
COLU M Nm1
DCDp
O1
O0
ADDR
COLU M Nm2
COLU M N0
LINE1
CK
DL
Q
D
LINE0
6
CK
DL
Q
D
Ap1 . . . A0
...
6
WE
DINm1
DOU Tm1
DINm2 DOU Tm2
6
DIN0
DOU T0
Figure 7.13: The asynchronous m-bit word RAM. Expanding the number of bits per word
means to connect in parallel one-bit word memories which share the same decoder. Each COLUMN
contains the storing latches and the AND-OR circuits for one bit.
Expanding the number of words by two dimension addressing

The factor form on silicon of the memory described in Figure 7.13 is very unbalanced for n >>>
m. Expanding the number of words for the a RAM in the previous, one block version is not
ecient because request a complex lay-out involving very long wires. We are looking for a more
squarish version of the lay-out for a big memory. The solution is to connect in parallel many
m-column blocks, thus dening a many-word from which to select one word using another level
of multiplexing. The reading process selects the many-word containing the requested word from
which the requested word is selected.
The internal organization of memory is now a two dimension array of rows and columns.
Each row contains a many-word of 2q words. Each column contains a number of 2r words. The
memory is addressed using the (p = r + q)-bit address:
addr[p-1:0] = {rowAddr[r-1:0], colAddr[q-1:0]}
The row address rowAddr[r-1:0] selects a many-word, while from the selected many-word,
173
the column address colAddr[q-1:0] selects the word addressed by the address addr[p-1:0].
Playing with the values of r and q an appropriate lay-out of the memory array can be designed.
In Figure 7.14 the block schematic for the resulting memory is presented. The second decoder
COLUMN DECODE selects from the s m-bit words provided by the s COLUMN BLOCKs
the word addressed by addr[p-1:0].
While the size decoder for a one block memory version is in the same order with the number
of words (SDCDp 2p ), the sum of the sizes of the two decoders in the two dimension version
is much smaller, because usually 2p >> 2r + 2q , for p = r + q. Thus, the area of the memory
circuit is dominated only by the storage elements.
-
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
ROW
DECODE
m-COLUMN
BLOCK (s-1)
m-COLUMN
BLOCK (s-2)
.
.
.
.
.
.
.
.
.
.
.
.
.
WE DOUT DIN
m-COLUMN
BLOCK (0)
WE DOUT DIN
WE DOUT DIN
rowAddr[r-1:0]
din[m-1:0]
.........
s-input DMUX
we
COLUMN
DECODE
.
.
.
.
.
.
.
6
colAddr[q-1:0]
m 2-input
ANDs
m 2-input
ANDs
m 2-input
ANDs
.......
m s-input
ORs
m q-input MUXs
addr[n-1:0]
dout[m-1;0]
Figure 7.14: RAM version with two dimension storage array. A number of m-bit blocks
are parallel connected and driven by the same row decoder. The column decoder selects to outoput an
m-bit word from the (s m)-bit row.
The second level of selection is based also on a shared decoder COLUMN DECODER. It
forms, with the s two-input ANDs a DM U Xq the q-input DMUX in Figure 7.14 which
distributes the write enable signals, we, to the selected m-column block. The same decoder is
174
shared by the m s-input MUXs used to select the output word from the many-word selected by
ROW DECODE.
The well known principle of divide et impera (divide and conquer) is applied when the
address is divided in two parts, one for selecting a row and another for selecting a column. The
access circuits is thus minimized.
Unfortunately, RAM has not the function of memorizing. It is only a storage support.
Indeed, if we want to memorize the number 13, for example, we must store it to the address
131313, for example, and to keep in mind (to memorize) the value 131313, the place where the
number is stored. And than, whats the help provided us by a the famous RAM memory? No
one. Because RAM is not a memory, it becomes a memory only if the associated processor runs
an appropriate procedure which allows us to forget about the address 131313. Another solution
is provided by additional circuits used to improve the functionality (see the subsection about
Associative Memories.)
7.5
The Serial-Parallel Composition: the Register
The last composition in 1-OS is the serial-parallel composition. The most representative circuit
of this class is the register. The main application of register is to support the synchronous
processes in a digital system. There are two typical use of the register:
provides the pipeline connection between subsystems (see the subsections 2.5.1 Pipelined
connections, and 3.3.2 Pipeline structures).
stores the internal state of an automata (see the next chapter); the register is used to close
of the second loop in a digital system.
Unlike the parallel compositions that store asynchronously, the circuits resulting from the
serial-parallel compositions store synchronously the value applied on their inputs. The parallel
compositions are used for designing memory systems, instead of the serial-parallel compositions,
used to support the designing of the control structures in a digital system.
The skeleton of any contemporary digital design is based on registers, used to store, synchronously with the system clock, the overall state of the system. The Verilog (or VHDL)
description of a structured digital design starts by dening the registers, and provides, usually,
an Register Transfer Logic (RTL) description. An RTL code describe a set of registers interconnected through (simple uniform or complex random) combinational blocks. For a register is a
non-transparent structure any loop congurations are supported. Therefore, the design is freed
by the care of the unstable loops.
In1
DF-F
Q
a.
?
On1
In2
I0
...
DF-F
...
?
On2
DF-F
CK
?
CK
?O
Q
...
?
O0
Rn
b.
Figure 7.15: The n-bit register. a. The structure: a bunch of DF-F connected in parallel. b. The
logic symbol.
7.6. APPLICATIONS
175
Denition 7.3 An n-bit register, Rn , is made by parallel connecting a Rn1 with a D (masterslave) ip-op. R1 is a D ip-op.
The register Rn , represented in Figure 7.15, is a serial-parallel composition in 1-OS because
its elementary component, the D ip-ops, are serial compositions in 1-OS. Another possible
denition is to build the register by serially connecting two n-bit latches. We know that the
n-bit latch is a parallel extension in 1-OS. The clock must be applied to the two n-bit latches
avoiding the simultaneous transparency.
VeriSim 7.11 An 8-bit enabled and resetable register with 2 unit time delay is described by the
following Verilog module:
module register #(parameter n = 8)(output
input
input
always
reg [n-1:0] out

[n-1:0] in
reset, enable, clock)
@(posedge clock) #2 if (reset)

else if (enable)
else
out = 0
out = in
out = out
,
,
;
;
;
;
endmodule
The time behavior specied by #2 is added only for simulation purpose. The synthesizable
version must avoid this unsinthesizable representation.
The main feature of the register assures its non-transparency, excepting an undecided transparency during a short time interval, tSU + tH , centered on the active edge of the clock signal.
Thus, a new loop can be closed carelessly over a structure containing a register. Due to its
non-transparency the register will be properly loaded with any value, even with a value depending on its own current content. This last feature is the main condition to close the loop of a
synchronous automata - the structure presented in the next chapter.
7.6
Applications
Composing basic memory circuits with combinational structures result typical system congurations or typical functions to be used in structuring digital machines. The pipeline connection, for
example, is a system conguration for speeding up a digital system using a sort of parallelism.
This mechanism is already described in the subsections 2.5.1 Pipelined connections, and 3.3.2
Pipeline structures. Few other applications of the circuits belonging to 1-OS are described in this
section. The rst is a frequent application of 1-OS: the synchronous memory, obtained adding
clock triggered structures to an asynchronous memory. The next is the le register a typical
storage subsystem used in the kernel of the almost all computational structures. The basic
building block in one of the most popular digital device, the Field Programmable Gate Array,
is also SRAM based structure. Follows the content addressable memory which is a hardware
mechanism useful in controlling complex digital systems or for designing genuine memory
structures: the associative memories.
7.6.1
Synchronous RAM
It is very hard to consider the time restriction imposed by the wave forms presented in Figure
7.12 when the system is requested to work at high speed. The system designer will be more
comfortable with a memory circuit having all the time restrictions dened related only to the
active edge of the system clock. The synchronous RAM (SRAM) is conceived to have all time
176
CLOCK
An1 . . . A0
6
a1
a2
a3
a4

W E

-
-
DIN
data in
DOU T
d(a1)
d(a2)
d(a4)
data in
Figure 7.16: Read and write cycles for SRAM. For the ow-through version of a SRAM the
time behavior is similar to a register. The set-up and hold time are dened related to the active edge of
clock for all the input connections: data, write-enable, and address. The data output is also related to
the same edge.
relations dened related to the active edge of the clock signal. SRAM is the preferred embodiment of a storage circuit in the contemporary designs. It performs write and read operations
synchronized with the active edge of the clock signal (see Figure 7.16).
VeriSim 7.12 The functional description of a synchronous RAM (0.5K of 64-bit words) follows:
module sram(
input
input
input
output
[63:0]
[8:0]
reg [63:0]
din
addr
we, clk
dout
,
,
,
);
//
//
//
//
data input
address
write enable & clock signal
data out
reg
[63:0]
mem[511:0];
always
@(posedge clk)
if (we) dout <= din

else
dout <= mem[addr]
;
;
always
endmodule
@(posedge clk)
if (we) mem[addr] <= din
The previously described SRAM is the ow-through version of a SRAM. A pipelined version
is also possible. It introduces another clock cycle delay for the output data.
7.6.2
Register File
The most accessible data in a computational system is stored in a small and fast memory whose
locations are usually called machine registers or simply registers. In most usual embodiment
they have actually the physical structure of a register. The machine registers of a computational
7.6. APPLICATIONS
177
(processing) element are organized in what is called register le. Because computation supposes
two operands and one result in most of cases, two read ports and one write port are currently
provided to the small memory used as register le (see Figure 7.17).
write enable
right addr[n-1:0]
dest addr[n-1:0]
result[m-1:0]
left addr[n-1:0]
clock
?
-
right operand[m-1:0]
left operand[m-1:0]
register file m n
Figure 7.17: Register le. In this example it contains 2n m-bit registers. In each clock cycle any two
registers can be read and writing can be performed in anyone.
VeriSim 7.13 Follows the Verilog description of a register le containing 32 32-bit registers.
In each clock cycle any two pair of registers can be accessed to be used as operands and a result
can be stored in any one register.
module register_file(
reg [31:0]
assign
output
output
input
input
input
input
input
input
file[0:31];
left_operand
right_operand
[31:0]
[31:0]
[31:0]
[4:0]
[4:0]
[4:0]
left_operand
right_operand
result
left_addr
right_addr
dest_addr
write_enable
clock
= file[left_addr]
= file[right_addr]
,
,
,
,
,
,
,
);
,
;
always @(posedge clock) if (write_enable) file[dest_addr] <= result;

endmodule
The internal structure of a register le can be optimized using m 2n 1-bit clocked latches
to store data and 2 m-bit clocked latches to implement the master-slave mechanism.
7.6.3
Field Programmable Gate Array FPGA
Few decades ago the prototype of a digital system was realized in a technology very similar with
the one used for the nal form of the product. Dierent types of standard integrated circuits
where connected according to the design on boards using a more or less exible interconnection
technique. Now we do not have anymore standard integrated circuits, and making an Application
Specic Integrated Circuit (ASIC) is a very expensive adventure. Fortunately, now there is a
wonderful technology for prototyping (which can be used also for small production chains). It
is based on a one-chip system called Field Programmable Gate Array FPGA. The name
178
comes from its exibility to be congured by the user after manufacturing, i.e., in the eld.
This generic circuit can be programmed to perform any digital function.
In this subsection the basic conguration of an FPGA circuit will be described4 . The internal
cellular structure of the system is described for the simplest implementation, letting aside details
and improvements used by dierent producer on this very diverse market (each new generation
of FPGA integrates dierent usual digital blocks in order to help ecient implementations; for
example: multipliers, block RAMs, ...; learn more about this from the on-line documentation
provided by the FPGA producers).
I/O
I/O
I/O
Switch matrix
=
I/O
CLB
Long connection
CLB

I/O
CLB
CLB
Local connection
)
I/O
Figure 7.18: Top level organization of FPGA.
The system level organization of an FPGA

The FPGA chip has a cellular structure with three main programmable components, whose
function is dened by setting on 0 or on 1 control bits stored in memory elements. An FPGA
can be seen as a big structured memory containing million of bits used to control the state of
million of switches. The main type of cells are:
Congurable Logic Blocks (CLB) used to perform a programmable combinational
and/or sequential function
Switch Nodes which interconnect in the most exible way the CLB modules and some
of them to the IO pins, using a matrix of programmed switches
Input-Output Interfaces are two-direction programmable interfaces, each one associated with an IO pin.
4
The terminology introduced in this section follows the Xlilinx style in order to support the associated lab
work.
7.6. APPLICATIONS
179
Figure 7.18 provides a simplied representation of the internal structure of an FPGA at the top
level. The area of the chip is lled up with two interleaved arrays. One of the CLBs and another
of the Switch Nodes. The chip is boarded by IO interfaces.
The entire functionality of the system can be programmed by an appropriate binary conguration distributed in all the cells. For each IO pin is enough one bit to dene if the pin is an
input or an output. For a Switch Node more bits are needed because each switch asks for 6 bits
to be congured. But, most of bits (in some implementations more than 100 per CLB) are used
to program the functions of the combinational and sequential circuits in each node containing a
CLB.
The IO interface
Each signal pin of the FPGA chip can be assigned to be an input or an output. The simplest
form of the interface associated to each IO pin is presented in Figure 7.19, where:
D-FF0: is the D master-slave ip-op which synchronously receives the value of the I/O
pin through the associated input non-inverting buer
m: the storage element which contains the 1-bit program for the input interface used to
command the tristate buer; if m = 1 then the tristate buer is enabled and interface is
in the output mode, else the tristate buer is disabled and interface is in the input mode
D-FF1: is the ip-op loaded synchronously with the output bit to be sent to the I/O
pin if m = 1.
Programmable memory element
+
m
-D
D-FF1
clock

D-FF0
Q
D
I
I/O pin
Figure 7.19: Input-Output interface.

The storage element m is part of the big distributed RAM containing all the storage elements
used to program the FPGA.
The switch node
The switch node (Figure 7.20a) consists of a number of programmable switches (4 in our description). Each switch (Figure 7.20b) manages 4 wires, connection them in dierent congurations
using 6 nMOS transistors, each commanded by the state of 1-bit memory (Figure 7.20c). If mi
= 1 then the associated nMOS transistor is on and between its drain end source the resistor
has a small value. If mi = 0 then the associated nMOS transistor is o and the two ends of the
switch are not connected.
For example, the conguration shown in Figure 7.20d is programmed as follows:
180
6 6 6 6
-
m2
3
2

1
0
? ? ?
a.
b.
c.
d.
Figure 7.20: The structure of a Switch Node. a. A Switch Node with 4 switches. b. The
organization of a switch. c. A line switch. d. An example of actual connections.
switch 0 : {m0, m1, m2, m3, m4, m5} = 011010;

switch 1 : {m0, m1, m2, m3, m4, m5} = 101000;
switch 2 : {m0, m1, m2, m3, m4, m5} = 000001;
switch 3 : {m0, m1, m2, m3, m4, m5} = 010000;
Any connection is a two-direction connection.
The basic building block
Because any digital circuit can be composed by properly interconnected gates and ip-ops, each
CLB contains a number of basic building blocks, called bit slices (BSs), each able to provide
at least an n-input, 1-output programmable combinational circuit and an 1-bit register.
In the previous chapter was presented an Universal combinational circuit: the n-input multiplexer able to perform any n-variable Boolean function. It was programmed applying on its
selected inputs an m-bit binary conguration (where m = 2n ). Thereby, an M U Xn and a memory for storing the m-bit program provide the structure able to be programmed to perform any
n-input 1-output combinational circuit. In Figure 7.21 it is represented, for n = 4, by the multiplexer MUX and the 16 memory elements m0, m1, ... m15. The entire sub-module is called
LUT (from look-up table). The memory elements m0, m1, ... m15, being part of the big
distributed RAM of the FPGA chip, can be loaded with any out of 65536 binary conguration
used to dene the same number of 4-input Boolean function.
Because the arithmetic operations are very frequently used the BS contains a specic circuit
for any arithmetic operation: the circuit computing the value of the carry signal. The module
carry Figure 7.21 has also its specic propagation path dened by a specic input, carryIn,
and a specic output carryOut.
The BS module contains also the one-bit register D-FF. Its contribution can be considered
in the current design if the memory element md is programmed appropriately. Indeed, if md =
1, then the output of the BS comes form the output of D-FF, else the output of the BS is a
combinational one, the ip-op being shortcut.
The memory element mc is used to program the selection of the LUT output or of the Carry
output to be considered as the programmable combinational function of this BS.
The total number of bits used to program the function of the BS previously described is 18.
Real FPGA circuits are now featured with much more complex BSs (please search on their web
pages for details).
7.6. APPLICATIONS
181
carryOut
6
mc
md
LUT
m15
- 15
-
MUX
m1
?
m0
-D
EMUX
EMUX
out
D-FF
Carry
0
6666
6 6
carryIn
in[3:0]
clock
Figure 7.21: The basic building block: the bit slice (BS).
There are two kinds of BS: logic type and memory type. The logic type uses LUT to
implement combinational functions. The memory type uses LUT for implementing both, combinatorial functions and memory function (RAM or serial shift register).
The congurable logic block
The main cell used to build an FPGA, CLB (see Figure 7.18) contains many BSs organized in
slices. The most frequent organization is of 2 slices, each having 4 BSs (see Figure 7.22). There
are slices containing logic type BSs (usually called SLICEL), or slices containing memory type
BSs (usually called SLICEM). Some CLBs are composed by two SLICEL, others are composed
by one SLICEL and one SLICEM.
Carry chain
Configurable Logic Block
Slice 2
BS3
W

BS2
BS1
BS0
Slice 1
BS3
BS2
BS1
BS0
Figure 7.22: Congurable logic block.

A slice has some x connections between its BSs. In our simple description, the x connections refers to the carry chain connections. Obviously, we can aord to make x connections for
circuits having specic function.
182
7.6.4
Content Addressable Memory
A normal way to question a memory circuit is to ask for:

Q1: the value of the property A of the object B
For example: How old is George? The age is the property and the object is George. The rst step to
design an appropriate device to be questioned as previously is exemplied is to dene a circuit able to
answer the question:
Q2: where is the object B?
with two possible answers:
1. the object B is not in the searched space
2. the object B is stored in the cell indexed by X.
The circuit for answering Q2-type questions is called Content Addressable Memory, shortly: CAM. (About
the question Q1 in the next subsection.)
The basic cell of a CAM is consists of:
the storage elements for binary objects
the questioning circuits for searching the value applied to the input of the cell.
In Figure 7.23 there are 4 D latches as storage elements and four XORs connected to a 4-input NAND
used as comparator. The cell has two functions:
to store: the active level of the clock modify the content of the cell storing the 4-bit input data
into the four D latches
to search: the input data is continuously compared with the content of the cell generating the
signal AO = 0 if the input matches the content.
D3
clock
? ?
D6
? ?
CK
D2
CK
D1
? ?
CK
D0
? ?
CK
AO
a.
D3 , . . . , D0
clock
- CK
cam cell
AO
b.
Figure 7.23: The Content Addressable Cell. a. The structure: data latches whose content is
compared against the input data using 4 XORs and one NAND. Write is performed applying the clock
with stable data input. b. The logic symbol.
The cell is written as an m-bit latch and is continuously interrogated using a combinational circuit
as comparator. The resulting circuit is an 1-OS because results serially connecting a memory, one-loop
circuit with a combinational, no-loop circuit. No additional loop is involved.
An n-word CAM contains n CAM cells and some additional combinational circuits for distributing
the clock to the selected cell and for generating the global signal M, activated for signaling a successful
match between the input value and one or more cell contents. In Figure 7.24a a 4-word of 4 bits each is
7.6. APPLICATIONS
183
represented. The write enable, W E, signal is demultiplexed as clock to the appropriate cell, according to
the address codded by A1 A0 . The 4-input NAND generate the signal M . If, at least one address output,
AOi is zero, indicating match in the corresponding cell, then M = 1 indicating a successful search.
A1 A0
WE
???
DMUX
3 2 1 0
a.
D3 , . . . , D0
- CK cam cell 0
- CK cam cell 1
- CK cam cell 2
- CK cam cell 3
AO0
AO1
AO2
AO3
Dm1 , . . . , D0
WE
Ap1 , . . . , A0
?
-
CAMmn
AOn1
, . . . , AO0
?
M
b.
Figure 7.24: The Content Addressable Memory (CAM). a. A 4-word CAM is built using 4
content addressable cells, a demultiplexor to distribute the write enable (WE) signal, and a N AN D4 to
generate the match signal (M). b. The logic symbol.
The input address Ap1 , . . . , A0 is binary codded on p = log2 n bits. The output address
AOn1 , . . . , AO0 is an unary code indicating the place or the places where the data input Dm1 , . . . , D0
matches the content of the cell. The output address must be unary codded because there is the possibility
of match in more than one cell.
Figure 7.24b represents the logic symbol for a CAM with n m-bit words. The input W E indicate the
function performed by CAM. Be very careful with the set-up time and hold time of data related to the
W E signal!
The CAM device is used to locate an object (to answer the question Q2). Dealing with the properties
of an object (answering Q1-type questions) means to use o more complex devices which associate one or
more properties to an object. Thus, the associative memory will be introduced adding some circuits to
CAM.
7.6.5
An Associative Memory
A partially used RAM can be an associative memory, but a very inecient one. Indeed, let be a RAM
addressed by An1 . . . A0 containing 2-eld words {V, Dm1 . . . D0 }. The objects are codded using the
address, the values of the unique property P are codded by the data eld Dm1 . . . D0 . The one-bit eld
V is used as a validation ag. If V = 1 in a certain location, then there is a match between the object
designated by the corresponding address and the value of property P designated by the associated data
eld.
Example 7.2 Let be the 1Mword RAM addressed by A19 . . . A0 containing 2-eld 17-bit words
{V, D15 . . . D0 }. The set of objects, OBJ, are codded using 20-bit words, the property P associated
to OBJ is codded using 16-bit words. If
RAM [11110000111100001111] = 1 0011001111110000
RAM [11110000111100001010] = 0 0011001111110000
then:
184
for the object 11110000111100001111 the property P is dened (V = 1) and has the value
0011001111110000
for the object 11110000111100001010 the property P is not dened (V = 0) and the data eld is
meaningless.
Now, let us consider the 20-bit address codes four-letter names using for each letter a 5-bit code. How
many locations in this memory will contain the eld V instantiated to 1? Unfortunately, only extremely
few of them, because:
only 24 from 32 binary congurations of 5 bits will be used to code the 24 letters of Latin alphabet
(244 < 220 )
but more important: how many dierent name expressed by 4 letters can be involved in a real
application? Usually no more than few hundred, meaning almost nothing related to 220 .
The previous example teaches us that a RAM used as associative memory is a very inecient solution.
In real applications are used names codded very ineciently:
number of possible names >>> number of actual names.
In fact, the natural memory function means almost the same: to remember about something immersed
in a huge set of possibilities.
One way to implement an ecient associative memory is to take a CAM and to use it as a programmable decoder for a RAM. The (extremely) limited subset of the actual objects are stored into a
CAM, and the address outputs of the CAM are used instead of the output of a combinational decoder to
select the accessed location of a RAM containing the value of the property P . In Figure 7.25 this version
of an associative memory is presented. CAMmn is usually dimensioned with 2m >>> n working as a
decoder programmed to decode any very small subset of n addresses expressed by m bits.
wa
sel
address
din
?
we
AOn1
we
wd
A
CAMmn
Array of Lq
(prog dcd)
M
AO0
valide dout
dout
Figure 7.25: An associative memory (AM). The structure of an AM can be seen as a RAM with
a programmable decoder implemented with a CAM. The decoder is programmed loading CAM with the
considered addresses.
Here are the three working mode of the previously described associative memory:
dene object : write the name of an object to the selected location in CAM
wa = 0, address = name of object, sel = cam address
wd = 1, din = dont care
associate value : write the associated value in the randomly accessed array to the location selected by
the active address output of CAM
wa = 1, address = name of object, sel = dont care
wd = 0, din = value
search : search for the value associated with the name of the object applied to the address input
wa = 1, address = name of object, sel = dont care
wd = 1, din = dont care
dout is valid only if valide dout = 1.
7.6. APPLICATIONS
185
This associative memory will be dimensioned according to the dimension of the actual subset of
names, which is signicantly smaller than the virtual set of the possible names (2p <<< 2m ). Thus, for
a searching space with the size in O(2m ) a device having the size in O(2p ) is used.
7.6.6
First-Order Systolic Systems
When a very intense computational function is requested for an Application Specic Integrated Circuit
(ASIC) systolic systems represent an appropriate solution. In a systolic system data are inserted and/or
extracted rhythmically in/from a uniform modular structure. H. T. Kung and Charles E. Leiserson
published the rst paper describing a systolic system in 1978 [Kung 79] (however, the rst machine
known to use a a systolic approach was the Colossus Mark II in 1944). The following example of systolic
system is taken from this paper.
Let us design the circuit which multiplies a band matrix with a vector as follows:

a11 a12 0
0
0
y1
x1
a21 a22 a23 0
0 x2 y2

a31 a32 a33 a34 0
y
x3
= 3
0 a42 a43 a44 a45
x
y
4
..
..
..
..
x
y5
5
.
.
.
.
0
0
..
..
..
..
..
.
.
.
.
.
0
0
0
The main operation executed for matrix-vector operations is multiply and accumulate (MACC):
Z =AB+C
for which a specic combinational module is designed. Interleaving MACCs with memory circuits is
provided a structure able to compute and to control the ow of data in the same time. The systolic
vector-matrix multiplier is represented in Figure 7.26.
The systolic module is represented in Figure 7.26a, where a combinational multiplier (M = A B)
is serially connected with an combinational adder (M + C). The result of MACC operation is latched in
the output latch which latches besides the result of the computation, the two input value A and B. The
latch is transparent on the high level of the clock. It is used to buer intermediary results and to control
the data propagation through the system.
The system is congured using pairs of modules to generate a master-slave structures, where one
module receives ck and another ck. The resulting structure is a non-transparent one ready to be used
in a pipelined connection.
For a band matrix having the width 4, two non-transparent structures are used (see Figure 7.26c).
Data is inserted in each phase of the clock (correlate data insertion with the phase of clock represented
in Figure 7.26b) as follows:
The result of the computation is generated sequentially to the output yi of the circuit from Figure
7.26c, as follows:
y1 = a11 x1 + a12 x2
y2 = a21 x1 + a22 x2 + a23 x3
y3 = a31 x1 + a32 x2 + a33 x3 + a34 x4
y4 = a42 x2 + a43 x3 + a44 x4 + a45 x5
y5 = . . .
...
The output X of the module is not used in this application (it is considered for matrix matrix
multiplication only). The state of the system in each phase of the clock (see Figure 7.26b) is represented
by two quadruples:
(Y1 , Y2 , Y3 , Y4 )
(Z1 , Z2 , Z3 , Z4 )
If the initial state of the system is unknown,
(Y1 , Y2 , Y3 , Y4 ) = (, , , )
186
(Z1 , Z2 , Z3 , Z4 ) = (, , , )
then the state of the system in the rst 10 phases of the clock, numbered in Figure 7.26c, are the following:
Phase: (1)
(Y1 , Y2 , Y3 , Y4 ) = (, , , )
(Z1 , Z2 , Z3 , Z4 ) = (, , , 0)
Phase: (2)
(Y1 , Y2 , Y3 , Y4 ) = (0, , , )
(Z1 , Z2 , Z3 , Z4 ) = (, , 0, 0)
?
-
+
ck
- ck
ck
9 10
Latch
?
X
?
Y
?
Z
a.
b.
...
...
...
...
(9)
a33
a42
(8)
a23
a32
(7)
a22
a31
(6)
a12
a21
(5)
a11
? (1 - 4)
(1) (2)
...
(10)
0
0 y1 y1 y2 y2 y3
x4 x3 x3 x2 x2 x1 x1
(10)
- (2) (1)
A1
A2
A3
A4
Z1 C1 Z2 C2 Z3 C3 Z4 C4
- B1 1 Y1 - B2 2 Y2 - B3 3 Y3 - B4 4 Y4
ck
ck
ck
ck
ck
ck
c.
Figure 7.26: Systolic vector-matrix multiplier. a. The module. b. The clock signal with
indexed half periods. c. How the modular structure is fed with the data in each half period of the clock
signal.
Phase: (3)
(Y1 , Y2 , Y3 , Y4 ) = (0, 0, , )
(Z1 , Z2 , Z3 , Z4 ) = (, 0, 0, 0)
Phase: (4)
(Y1 , Y2 , Y3 , Y4 ) = (x1 , 0, 0, )
(Z1 , Z2 , Z3 , Z4 ) = (0, 0, 0, 0)
7.7. CONCLUDING ABOUT MEMORY CIRCUITS
187
(5)
(Y1 , Y2 , Y3 , Y4 ) = (x1 , x1 , 0, 0)
(Z1 , Z2 , Z3 , Z4 ) = (0, a11 x1 , 0, 0)
(6)
(Y1 , Y2 , Y3 , Y4 ) = (x2 , x1 , x1 , 0)
(Z1 , Z2 , Z3 , Z4 ) = (a11 x1 + a12 x2 , a11 x1 , a21 x1 , 0)
(7)
(Y1 , Y2 , Y3 , Y4 ) = (x2 , x2 , x1 , x1 )
(Z1 , Z2 , Z3 , Z4 ) = (y1 , a21 x1 + a22 x2 , a21 x1 , a31 x1 )
(8)
(Y1 , Y2 , Y3 , Y4 ) = (x3 , x2 , x2 , x1 )
(Z1 , Z2 , Z3 , Z4 ) = (a21 x1 + a22 x2 + a23 x3 , a21 x1 + a22 x2 , a31 x1 + a32 x2 , a31 x1 )
(9)
(Y1 , Y2 , Y3 , Y4 ) = (x3 , x3 , x2 , x2 )
(Z1 , Z2 , Z3 , Z4 ) = (y2 , a31 x1 + a32 x2 + a33 x3 , a31 x1 + a32 x2 , a42 x2 )
(10)
(Y1 , Y2 , Y3 , Y4 ) = (x4 , x3 , x3 , x2 )
(Z1 , Z2 , Z3 , Z4 ) = (a31 x1 + a32 x2 + a33 x3 + a34 x4 , a31 x1 + a32 x2 + a33 x3 , a42 x2 + a43 x3 , a42 x2 )
(11)
(Y1 , Y2 , Y3 , Y4 ) = (x4 , x4 , x3 , x3 )
(Z1 , Z2 , Z3 , Z4 ) = (y3 , . . .)
...
In each clock cycle 4 multiplications and 4 additions are performed. The pipeline connections allow the
synchronous insertion and extraction of data. The maximum width of the matrix band determines the
number of modules used to design the systolic system.
7.7
Concluding About Memory Circuits
For the rst time, in this chapter, both composition and loop are used to construct digital
systems. The loop adds a new feature and the composition expands it. The chapter introduced
only the basic concepts and the main ways to use them in implementing actual digital systems.
The rst closed loop in digital circuits latches events Closing properly simple loops in
small combinational circuits vey useful eects are obtained. The most useful is the latch eect
allowing to store certain temporal events. An internal loop is able to determine an internal
state of the circuit which is independent in some extent from the input signals (the circuit
controls a part of its inputs using its own outputs). Associating dierent internal states to
dierent input events the circuit is able to store the input event in its internal states. The rst
loop introduces the rst degree of autonomy in a digital system: the autonomy of the internal
state. The resulting basic circuit for building memory systems is the elementary latch.
Meaningful circuits occur by composing latches The elementary latches are composed
in dierent modes to obtain the main memory systems. The serial composition generates the
master-slave ip-op which is triggered by the active edge of the clock signal. The parallel composition introduces the concept of random access memory. The serial-parallel composition
denes the concept of register.
Distinguishing between how? and when? At the level of the rst order systems
occurs a very special signal called clock. The clock signal becomes responsible for the history
sensitive processes in a digital system. Each clocked system has inputs receiving information
about how to switch and another special input the clock input acting on one of its edge called
the active edge of clock and another special input indicating when the system switches. We
188
call this kind of digital systems synchronous systems, because any change inside the system is
triggered synchronously by the same edge (positive or negative) of the clock signal.
Registers and RAMs are basic structures First order systems provide few of the most
important type of digital circuits used to support the future developments when new loops will
be closed. The register is a synchronous subsystem which, because of its non-transparency,
allows closing the next loop leading to the second order digital systems. Registers are used also
for accelerating the processing by designing pipelined systems. The random access memory
will be used as storage element in developing systems for processing a big amount of data or
systems performing very complex computations. Both, data and programs are stored in RAMs.
RAM is not a memory, it is only a physical support Unfortunately RAM has not the
function of memorizing. It is only a storage element. Indeed, when the word W is stored at the
address A we must memorize the address A in order to be able to retrieve the word W . Thus,
instead of memorizing W we must memorize A, or, as usual, we must have a mechanism to
regenerate the address A. In conjunction with other circuits RAM can be used to build systems
having the function of memorizing. Any memory system contains a RAM but not only a RAM,
because memorizing means more than storing.
Memorizing means to associate Memorizing means both to store data and to retrieve it.
The most natural way to design a memory system is to provide a mechanism able to associate
the stored data with its location. In an associative memory to read means to nd, and to write
means to nd a free location. The associative memory is the most perfect way of designing
a memory, even if it is not always the most optimal as area (price), time and power.
To solve ambiguities a new loop is needed At the level of the rst order systems the
second latch problem can not be solved. The system must be more intelligent to solve the
ambiguity of receiving synchronously contradictory commands. The system must know more
about itself in order to be able to behave under ambiguous circumstances. Only a new loop
will help the system to behave coherently. The next chapter, dealing with the second level of
loops, will oer a robust solution to the second latch problem.
The storing and memory functions, typical for the rst order systems, are not true computational features. We will see that they are only useful ingredients allowing to make digital
computational systems ecient.
7.8
Problems
Stable/unstable loops
Problem 7.1 Simulate in Verilog the unstable circuit described in Example 3.1. Use 2 unit
time (#2) delay for each circuit and measure the frequency of the output signal.
Problem 7.2 Draw the circuits described by the following expressions and analyze their stability
taking into account all the possible combinations applied on their inputs:
d = b(ad) + c
d = (b(ad) + c)
c = (ac + bc)
c = (a c) b.
7.8. PROBLEMS
189
Simple latches
Problem 7.3 Illustrate the second latch problem with a Verilog simulation. Use also versions
of the elementary latch with the two gates having distinct propagation times.
Problem 7.4 Design and simulate an elementary clocked latch using a NOR latch as elementary
latch.
Problem 7.5 Let be the circuit from Figure 7.27. Indicate the functionality and explain it.
Hint: emphasize the structure of an elementary multiplexer.
d
c
c
c
ck
Figure 7.27: ?
Problem 7.6 Explain how it works and nd an application for the circuit represented in Figure
7.28.
Hint: Imagine the tristate drivers are parts of two big multiplexors.
out1
out2
in
Figure 7.28: ?
Master-slave ip-ops
Problem 7.7 Design an asynchronously presetable master-slave ip-op.
Hint: to the slave latch must be added asynchronous set and reset inputs (S and R in the
NAND latch version, or S and R in the NOR latch version).
Problem 7.8 Design and simulate in Verilog a positive edge triggered master-slave structure.
Problem 7.9 Design a positive edge triggered master slave structure without the clock inverter.
Hint: use an appropriate combination of latches, one transparent on the low level of the clock
and another transparent on the high level of the clock.
190
Problem 7.10 Design the simulation environment for illustrating the master-slave principle
with emphasis on the set-up time and the hold time.
Modify the circuit to be triggered by the other edge of the clock.
Hint: emphasize the structures of two clocked latches and explain how they interact.
d
c
ck
Figure 7.29: ?
Assign a name for the questioned input. What happens if the NANDs are substituted with NORs.
Rename the questioned input. Combine both functionality designing a more complex structure.
Hint: go back to Figure 7.3c.
q
c
c
?
c
ck
Figure 7.30: ?
Enabled circuits
Problem 7.13 An n-bit latch stores the n-bit value applied on its inputs. It is transparent on
the low level of the clock. Design an enabled n-bit latch which stores only in the clock cycle in
which the enable input, en, take the value 1 synchronized with the positive edge of the clock.
Dene the set-up time and the hold time related to the appropriate clock edge for data input and
for the enable signal.
Problem 7.14 Provide a recursive Verilog description for an n-bit enabled latch.
7.8. PROBLEMS
191
RAMs
Problem 7.15 Explain the reason for tASU and for tAH in terms of the combinational hazard.
Problem 7.16 Explain the reason for tDSU and for tDH .
Problem 7.17 Provide a structural description of the RAM circuit represented in Figure 7.11
for m = 256. Compute the size of the circuit emphasizing both the weight of storing circuits and
the weight of the access circuits.
Problem 7.18 Design a 256-bit RAM using a two-dimensional array of 1616 latches in order
to balance the weight of the storing circuits with the weight of the accessing circuits.
Problem 7.19 Design the ow-through version of SRAM dened in Figure 7.16.
Hint: use additional storage circuits for address and input data, and relate the W E signal with
the clock signal.
Problem 7.20 Design the register to latch version of SRAM dened in Figure 7.31.
Hint: the write process is identical with the ow-through version.
CLOCK
-
ADDRESS
6
-
addr
DOU T
Register to Latch
data(addr)
DOU T
Pipeline
data(addr)
Figure 7.31: Read cycles. Read cycle for the register to latch version and for the pipeline version of
SRAM .
Problem 7.21 Design the pipeline version of SRAM dened in Figure 7.31.
Hint: only the output storage device must be adapted.
Registers
Problem 7.22 Provide a recursive description of an n-bit register. Prove that the (algorithmic)
complexity of the concept of register is in O(n) and the complexity of a ceratin register is in
O(log n).
192
Problem 7.23 Draw the schematic for an 8-bit enabled and resetable register. Provide the
Verilog environment for testing the resulting circuit. Main restriction: the clock signal must be
applied only directly to each D ip-op.
Hint: an enabled device performs its function only if the enable signal is active; to reset a
register means to load it with the value 0.
Problem 7.24 Add to the register designed in the previous problem the following feature: the
content of the register is shifted one binary position right (the content is divided by two neglecting
the reminder) and on most signicant bit (MSB) position is loaded the value of the one input
bit called SI (serial input). The resulting circuit will be commanded with a 2-bit code having the
following meanings:
nop : the content of the register remains unchanged (the circuit is disabled)
reset : the content of the register becomes zero
load : the register takes the value applied on its data inputs
shift : the content of the register is shifted.
Problem 7.25 Design a serial-parallel register which shifts 16 16-bit numbers.
Definition 7.4 The serial-parallel register, SP Rnm , is made by a SP R(n1)m serial connected with a Rm . The SP R1m is Rm .
Hint: the serial-parallel register, SP Rnm can be seen in two manners. SP Rnm consists in
m parallel connected serial registers SRn , or SP Rnm consists in n serially connected registers
Rm . We prefer usually the second approach. In Figure 7.32 is shown the serial-parallel SP Rnm .
IN
Rm
Rm
CK
...
Rm
OUT
-
...
a.
IN
b.
SP Rnm
OUT
-
CK
Figure 7.32: The serial-parallel register. a. The structure. b. The logic symbol.
Problem 7.26 Let be tSU , tH , tp , for a register and tpCLC the propagation time associated with
the CLC loop connected with the register. The maximal and minimal value of each is provided.
Write the relations governing these time intervals which must be fullled for a proper functioning
of the loop.
Pipeline systems
Problem 7.27 Explain what is wrong in the following always construct used to describe a
pipelined system.
7.9. PROJECTS
module pipeline
193
#(parameter
n = 8, m = 16, p = 20)
(output
reg[m-1:]
output_reg,
input
wire[n-1:0] in,
clock);
reg[n-1:0]
input_reg;
reg[p-1:0]
pipeline_reg;
wire[p-1:0]
out1;
wire[m-1:0]
out2;
clc1
first_clc(out1, input_reg);
clc2
second_clc(out2, pipeline_reg);
input_reg = in;
pipeline_reg = out1;
output_reg = out2;
end
endmodule
module clc1(out1, in1);
// ...
endmodule
module clc2(out2, in2);
// ...
endmodule
Hint: revisit the explanation about blocking and nonblocking evaluation in Verilog.
Register le
Problem 7.28 Draw register file 16 4 at the level of registers, multiplexors and decoders.
Problem 7.29 Evaluate for register file 32 5 minimum input arrival time before clock
(tin reg ), minimum period of clock (Tmin ), maximum combinational path delay (tin out ) and
maximum output required time after clock (treg out ) using circuit timing from Appendix Standard cell libraries.
CAMs
Problem 7.30 Design a CAM with binary codded output address, which provides as output
address the rst location containing the searched binary conguration, if any.
Problem 7.31 Design an associative memory, AM , implemented as a maskable and readable
CAM. A CAM is maskable if any of the m input bits can be masked using an m-bit mask word.
The masked bit is ignored during the comparison process. A CAM is readable if the full content
of the rst matched location in sent to the data output.
Problem 7.32 Find examples for the inequality
number of possible names >>> number of actual names
which justify the use of the associative memory concept in digital systems.
7.9
Projects
Project 7.1 Let be the module system containing system1 and system2 interconnected through
the two-direction memory buer module bufferMemory. The signal mode controls the sense of
194
the transfer: for mode = 0 system1 is in read mode and system2 in write mode, while for
mode = 1 system2 is in read mode and system1 in write mode. The module library provide the
memory block described by the module memory.
module system( input
[m-1:0] in1
,
input
[n-1:0] in2
,
output [p-1:0] out1
,
output [q-1:0] out2
,
input
clock
);
wire
[63:0] memOut1 ;
wire
[63:0] memIn1 ;
wire
[13:0]] addr1
;
wire
we1
;
wire
[255:0] memOut2 ;
wire
[255:0] memIn2 ;
wire
[11:0] addr2
;
wire
we2
;
wire
mode
; // mode = 0: system1 reads, system2 writes
// mode = 1: system2 reads, system1 writes
wire
[1:0]
com12, com21
;
system1 system1(in1, out1, com12, com21,
memOut1 ,
memIn1 ,
addr1
,
we1
,
mode
,
clock
);
system2 system2(in2, out2, com12, com21,
memOut2 ,
memIn2 ,
addr2
,
we2
,
clock
);
bufferMemory
bufferMemory(
memOut1 ,
memIn1 ,
addr1
,
we1
,
memOut2 ,
memIn2 ,
addr2
,
we2
,
mode
,
clock
);
endmodule
module memory #(parameter n=32, m=10)
(
output reg [n-1:0] dataOut
input
[n-1:0] dataIn
input
[m-1:0] readAddr
input
[m-1:0] writeAddr
input
we
input
enable
input
clock
,
,
,
,
,
,
);
reg [n-1:0] memory[0:(1 << m)-1];

always @(posedge clock) if (enable) begin
//
//
//
//
//
//
data output
data input
read address
write address
write enable
module enable
7.9. PROJECTS
195
if (we) memory[writeAddr] <= dataIn ;
dataOut <= memory[readAddr]
;
end
endmodule
Design the module bufferMemory.

Project 7.2 Design a systolic system for multiplying a band matrix of maximum width 16 with
a vector. The operands are stored in serial registers.
196
Chapter 8
AUTOMATA:
Second order, 2-loop digital systems
the memory circuit were described discussing about
how is built an elementary memory cell
how applying all type of compositions the basic memory structures (ip-ops, registers, RAMs) can be obtained
how the basic memory structures are in used real applications
In this chapter
the second order, two-loop circuits are presented with emphasis on
dening what is an automaton
the smallest 2-state automata, such as T ip-op and JK ip-op
big and simple automata exemplied by the binary counters
small and complex nite automata exemplied by the control automata
In the next chapter
the third order, three-loop systems are described taking into account the type of system
through which the third loop is closed:
combinational circuit - resulting optimized design procedures for automata
memory systems - supposing simplied control
automata - with the processor as typical structure.
197
198
CHAPTER 8. AUTOMATA:
SECOND ORDER, 2-LOOP DIGITAL SYSTEMS
The Tao of heaven is impartial.

If you perpetuate it, it perpetuates you.
Lao Tzu1
Perpetuating the inner behavior is the
magic of the second loop.
The next step in building digital systems is to add a new loop over systems containing 1-OS.
This new loop must be introduced carefully so as the system remains stable and controllable.
One of the most reliable ways is to build synchronous structures, that means to close the loop
through a way containing a register. The non-transparency of registers allows us to separate
with great accuracy the current state of the machine from the next state of the same machine.
This second loop increases the autonomous behavior of the system including it. As we shall
see, in 2-OS each system has the autonomy of evolving in the state space, partially independent
from the input dynamics, rather than in 1-OS in which the system has only the autonomy of
preserving a certain state.
The basic structure in 2-OS is the automaton, a digital system with outputs evolving according to two variables: the input variable and a hidden internal variable named the internal
state variable, simply the em state. The autonomy is given by the internal eect of the state.
The behavior of the circuit output can not be explained only by the evolution of the input,
the circuit has an internal autonomous evolution that memorizes previous events. Thus the
response of the circuit to the actual input takes into account the more or less recent history. The
state space is the space of the internal state and its dimension is responsible for the behavioral
complexity. Thus, the degree of autonomy depends on the dimension of the state space.
register
?
Uncloked Lathes
Unclocked Latch
1-OS
Cloked Lathes
clock
1-OS
1-OS
clock
1-OS
CLC
Cloked Lathes
clock
1-OS
CLC
0-OS
6
a.
0-OS
0/1-OS
b.
1-OS
Figure 8.1: The two type of 2-OS. a. The asynchronous automata with a hazardous loop over
a transparent latch. b. The synchronous automata with a edge clock controlled loop closed over a
non-transparent register.
An automaton is built closing a loop over a 1-OS represented by a collection of latches. The
loop can be structured using the previous two type of systems. Thus, there are two type of
automata:
asynchronous automata, for which the loop is closed over unclocked latches, through
combinational circuit and/or unclocked latches as in Figure 8.1a
1
Quote from Tao Te King of Lao Tzu translated by Brian Browne Walker.
8.1. OPTIMIZING DFF WITH AN ASYNCHRONOUS AUTOMATON
199
synchronous automata, having the loop closed through an 1-OS and all latches are clocked
latches connected on the loop in master-slave congurations (see Figure 8.1b).
Our approach will be focused on the synchronous automata, after considering only in the rst
subchapter an asynchronous automaton used to optimize the internal structure of the widely
used ip-op: DFF.
Denition 8.1 Formally, a nite automaton is an automaton (see Appendix G) having a nite
set of states.
Actually, all implementable automata are nite. Traditionally, this term is used to distinguish
a subset of automata whose behavior is described using a constant number of states. Even if
the input string is innite, the behavior of the automaton is limited to a trajectory traversing a
constant (nite) number of states. A nite automaton will be an automaton having a random
combinational function for computing the next state. Therefore, a nite automaton is a complex
structure.
A non-nite automaton that is an automaton designed to evolve in a state space proportional with the length of the input string. Now, if the input string is innite the number of
states must be also innite. Such an automaton can be dened only if its transition function is
simple. Its combinational loop is a simple circuit even if it can be a big one. The non-nite
automaton has a number of states that does not aect the denition (see the following examples
of counters, for sum prex automaton, ...). We classify the automata in two categories:
non-nite, recursive dened, simple automata, called functional automata, or simply
automata
non-recursive dened, complex automata, called nite automata.
We start this chapter with an example of asynchronous circuit, because of its utility and
because we intend to show how complex is the management of its behavior. We will continue
presenting only synchronous automata, starting with small automata having only two states
(the smallest state space). We will continue with simple, recursive dened automata and we will
end with nite automata, that are the most complex automata.
8.1
Optimizing DFF with an asynchronous automaton
The very important feature added by the master-slave conguration that of edge triggering
the ip-op was paid by increasing two times the size of the structure. An improvement is
possible for DFF (the master-slave D ip-op) using the structure presented in Figure 8.2, where
instead of 8 2-input NANDs and 2 invertors only 6 2-input gates are used. The circuit contains
three elementary unclocked latches: the output latch, with the inputs R and S commanded by
the outputs of the other two latches, L1 and L2. L1 and L2 are loop connected building up a
very simple asynchronous automaton with two inputs D and CK and two outputs R and
S.
The explanation of how this DFF, designed as a 2-OS, works uses the static values on the
inputs of the latches. For describing the process of switching in 1 the triplets (x,y,z) are used,
while for switching in 0 are used [x,y,z], where:
x : is the stable value in the set-up time interval (in a time interval, equal with tsu , before
the positive transition of CK)
y : is the stable value in the hold time interval (in a time interval of th , after the positive
transition of CK; the transition time, t+ is considered very small and is neglected)
200
z : is a possible value after the hold time interval (after th measured from the positive
transition of CK)
For the process of transition in 1 we follow the triplets (x,y,z) in Figure 8.2:
in set-up time interval : CK = 0 forces the values R and S to 1, does not matter what is
the value on D. Thus, the output latch receives passive values on both of its inputs.
in hold time interval : CK = 1 frees L1 and L2 to follow the signals they receive on their
inputs. The rst order and the second order loops are now closed. L2 switches to S =
0, because of the 0 received from L1, which maintains its state because D and CK have
passive values and the output S of L2 reinforces its state to R = 1. The output latch is
then set because of S = 0.
after the hold time interval : the possible transition in 0 of D after the hold time does not
aect the output of the circuit, because the second loop, from L2 to L1, forces the output
R to 1, while L2 is not aected by the transition of its input to the passive value because
of D = 0. Now, the second loop allow the system to ignore the switch of D after the hold
time.
(0,0,1)
(1,1,1)
[1,1,1]
[0,0,0]
Async. Automaton
(1,1,0)
L1
D
L2
[0,0,1]
(0,1,1)
CK
[0,1,1]
(1,1,1) R
S (1,0,0)
[1,0,0]
[1,1,1]
Figure 8.2: The D ip-op implemented as a 2-OS system. The asynchronous automaton
built up loop connecting two unclocked latches allows to trigger the output latch according to the input
data value available at the positive transition of clock.
For the process of transition in 0 we follow the triplets [x,y,z] in Figure 8.2:
in set-up time interval : CK = 0 forces the values R and S to 1, does not matter what is
the value on D. Thus, the output latch receives passive values on both of its inputs. The
output of L1 applied to L2 is also forced to 1, because of the input D = 0.
in hold time interval : CK = 1 frees L1 and L2 to follow the signals they receive on their
inputs. The rst order and the second order loops are now closed. L1 switches to R = 0,
because of the 0 maintained on D. L2 does not change its state because the input received
from L1 has the passive value and the CK input switches also in the passive value. The
output latch is then reset because of R = 0.
8.2. TWO STATES AUTOMATA
201
after the hold time interval : the possible transition in 1 of D after the hold time does not
aect the state of the circuit, because 1 is a passive value for a NAND elementary latch.
The eect of the second order loop is to inform the circuit that the set signal was, and still
is, activated by the positive transition of CK and any possible transition on the input D must be
ignored. The asynchronous automaton L1 & L2 behaves as an autonomous agent who knows
what to do in the critical situation when the input D takes an active value in an unappropriate
time interval.
8.2
Two States Automata
The smallest two-state half-automata can be explored almost systematically. Indeed, there are
only 16 one-input two-state half-automata and 256 with two inputs. We choose only two of
them: the T ip-op, the JK ip-op, which are automata with Q = Y and f = g. For simple
2-operand computations 2-input automata can be used. One of them is the adder automaton.
This section ends with a small and simple universal automaton having 2 inputs and 2 states.
8.2.1
The Smallest Automaton: the T Flip-Flop
The size and the complexity of an automaton depends at least on the dimension of the sets
dening it. Thus, the smallest (and also the simplest) automaton has two states, Q = {0, 1}
(represented with one bit), one-bit input, T = {0, 1}, and Q = Y . The associated structure in
represented in Figure 8.3, where is represented a circuit with one-bit input, T, having a one-bit
register, a D ip-op, for storing the 1-bit coded state, and a combinational logic circuit, CLC,
for computing the function f .
What can be the meaning of an one-bit message, received on the input T, by a machine
having only two states? We can express with the two values of T only the following things:
no op : T = 0 - the state of the automaton remains the same
switch : T = 1 - the state of the automaton switches.
??
CLC
CK
CK
DF-F
DF-F
Q
a.
CK
?
Q
TF-F
Q
b.
?
Q
?
c.
Figure 8.3: The T ip-op. a. It is the simplest automaton because: has 1-bit state register (a
DF-F), a 2-input loop circuit (one as automaton input and another to close the loop), and direct output
from the state register. b. The structure of the T ip-op: the XOR2 circuits complements the state is
T = 1. c. The logic symbol.
The resulting automaton is the well known T ip-op. The actual structure of a T ip-op
is obtained connecting on the loop a commanded invertor, i.e., a XOR gate (see Figure 8.3b).
The command input is T and the value to be inverted is Q, the state and the output of the
circuit.
202
This small and simple circuit can be seen as a 2-modulo counter because for T = 1 the output
says: 01010101... Another interpretation of this circuit is: the T ip-op is a frequency divider.
Indeed, if the clock frequency is fCK , then the frequency of the signal received to the output Q
is fCK /2 (after each clock cycle the circuit comes back in the same state).
8.2.2
The JK Automaton: the Greatest Flip-Flop
The next automaton in an imaginary hierarchy is one having two inputs. Lets call them J
and K. Thus, we can dene the famous JK ip-op. Also, the function of this automaton results
univocally. For an automaton having only two states the four input messages coded with J and
K will be compulsory:
no op : J = K = 0 - the ip-op output does not change (the same as T = 0 for T ip-op)
reset : J = 0, K = 1 - the ip-op output takes the value 0 (specic for D ip-op)
set : J = 1, K = 0 - the ip-op output takes the value 1 (specic for D ip-op)
switch : J = K = 1 - the ip-op output switches in the complementary state (the same as
T = 1 for T ip-op)
Only for the last function the loop acts specic for a second order circuit. The ip-op
must tell to itself what is its own state in order to knows how to switch in the other state.
Executing this command the circuit asserts its own autonomy. The vagueness of the command
switch imposes a sort of autonomy to determine a precise behavior. The loop that assures
this needed autonomy is closed through two AND gates (see Figure 8.4a).
J
CK
J
S
a.
?
Q
?
Q
JKF-F
R
RSF-F
6
?
Q
b.
Figure 8.4: The JK ip-op. It is the simplest two-input automaton. a. The structure: the loop is
closed over a master-slave RSF-F using only two AN D2 . b. The logic symbol.
Finally, we solved the second latch problem. We have a two state machine with two command
inputs and for each input conguration the circuit has a predictable behavior. The JK ip-op is
the best ip-op ever dened. All the previous ones can be reduced to this circuit with minimal
modications (J = K = T for T ip-op or K = J = D for D ip-op).
8.2.3
Serial Arithmetic
As we know the ripple carry adder has the size in O(n) and the depth also in O(n) (remember Figure
6.16). If we agree with the time in this magnitude order, then there is a better solution where a second
order circuit is used.
The best solution for the n-bit adder is a solution involving a small and simple automaton. Instead
of storing the two numbers to be added in (parallel) registers, as in the pure combinational solution, the
sequential solutions needs serial registers for storing the operands. The system is presented in Figure 8.5,
containing three serial registers (two for the operands and one for the result) and the adder automaton.
8.2. TWO STATES AUTOMATA
IN
203
SRn
-A
-B
-C
OUT
CK
S
FA
C+
Q
IN
SRn
OUT
DF-F
Adder automaton
OUT
SRn
IN
Figure 8.5: Serial n-bit adder. The state of the adder automaton has the value of the carry generated
adding the previous 2 bits received from the output of the two serial registers containing the operands.
The adder automaton is a two states automaton having in the loop the carry circuit of a full adder
(FA). The one-bit state register contains the carry bit from the previous cycle. The inputs A and B of
FA receive synchronously, at each clock cycle, bits having the same binary range from the serial registers.
First, LSBs are read from the serial registers. Initially, the automaton is in the state 0, that means
CR = 0. The output S is stored bit by bit in the third serial register during n clock cycles. The nal
(n + 1)-bit result is contained in the output serial register and in the state register.
The operation time remains in the order of O(n), but the structure involved in computation becomes
the constant structure of the adder automaton. The product of the size, SADD (n), into the time, TADD (n)
is in O(n) for this sequential solution. Again, Conjecture 2.1 acts emphasizing the slowest solution as
optimal. Let us remember that for a carry-look-ahead adder, the fastest O(1) variant, the same product
was in O(n3 ). The price for the constant execution time is, in this example, in O(n2 ). I believe it is too
much. We will prefer architectural solutions which allow us to avoid the structural necessity to perform
the addition in constant time.
8.2.4
Universal 2-input and 2-state automaton
Any binary (two-operand) simple operation on n-bit operands can be performed serially using a 2state automaton. The internal state of the automaton stores the carry information from one stage of
processing to another. In the adder automaton, just presented, the internal state is used to store the
carry bit generated adding the i-th bits of a number. It is used in the next stage for adding the (i + 1)-th
bits. This mechanism can be generalized, resulting an universal 2-input (for binary operation), 2-state
automaton (for carry bit).
Denition 8.2 An Universal 2-input (in1, in2), 2-state (codded by state[0]) automaton is a programmable structure using a 16-bit program word, {next state f unc[7 : 0], out f unc[7 : 0]}. It is dened
by the following Verilog code:
module univ_aut(
output
input
input
input
reg
assign
[7:0]
out
in1
in2
next_state_func
out_func
reset
clock
state;
out = out_func[{state, in2, in1}];
,
,
,
,
,
,
);
//
//
//
//
//
the
the
the
the
the
output
first operand
second operand
program for loop
program for output
204
if (reset)
else
endmodule
state <= 0;
state <= next_state_func[{state, in2, in1}];
The universal programmable automaton is implemented using two 3-input universal combinational
circuits, one for the output function and another for the loop function. The total number of automata
can be programmed on this structure is 216 (the total number of 16-bit programs). Most of them are
meaningless, but the simplicity of solution deserves our attention.2
8.3
Functional Automata: the Simple Automata
The smallest automata before presented are used in recursively extended conguration to perform similar functions for any n. From this category of circuits we will present in this section
only the binary counters. The next circuit will be also a simple one, having the denition independent by size. It is a sum-prex automaton. The last subject will be a multiply-accumulate
circuit built with two simple automata serially connected.
8.3.1
Counters
The rst simple automaton is a composition starting from one of the function of T ip-op: the
counting. If one T ip-op counts modulo-21 , maybe two T ip-ops will count modulo-22 and
so on. Seems to be right, but we must nd the way for connecting many T ip-ops to perform
the counter function.
For the synchronous counter3 built with n T ip-ops, Tn1 , . . . , T0 , the formal rule is very
simple: if IN C0 , then the rst ip-op, T0 , switches, and the i-th ip-op, for i = 1, . . . , n 1,
switches only if all the previous ip-ops are in the state 1. Therefore, in order to detect the
switch condition for i-th ip-op an AN Di+1 must be used.
Denition 8.3 The n-bit synchronous counter, COU N Tn , has a clock input, CK, a command
input, IN C0 , an n-bit data output, Qn1 , . . . Q0 , and an expansion output, IN Cn . If IN C0 = 1,
the active edge of clock increments the value on the data output (see Figure 8.6).
There is also a recursive, constructive, denition for COU N Tn .
Denition 8.4 An n-bit synchronous counter, COU N Tn is made by expanding a COU N Tn1
with a T ip-op with the output Qn1 , and an AN Dn+1 , with the inputs IN C0 , Qn1 , . . . , Q0 ,
which computes IN Cn (see Figure 8.6). COU N T1 is a T ip-op and an AN D2 with the inputs
Q0 and IN C0 which generates IN C1 .
Example 8.1
The Verilog description of a synchronous counter follows:
module sync_counter #(parameter n = 8)(output

output
input
t_reg
2
3
t_reg(
.out
.in
[n-1:0] out
inc_n
inc_0
reset
clock
(out)
,
(prefix_out[n-1:0]) ,
,
,
,
,
);
The processing element in Connection Machine [Hillis 85] used a similar simple and small machine.
There exist also asinchronous counters. They are simpler but less performant.
8.3. FUNCTIONAL AUTOMATA: THE SIMPLE AUTOMATA
205
CK
IN C0
T
Tn1
IN Cn1
COU N Tn1
Qn2
...
Q0
...
...
IN C0
IN Cn
?
Qn1
?
Qn2
?
Q0
...
Figure 8.6: The synchronous counter. The recursive denition of a synchronous counter has
SCOU N T (n) O(n2 ) and TCOU N T (n) O(log n), because for the i-th range one TF-F and one AN Di
are added.
.reset
.clock
and_prefix
assign
endmodule
(reset)
(clock)
and_prefix( .out
.in
,
);
(prefix_out)
({out, inc_0})
,
);
inc_n = prefix_out[n];
module t_reg #(parameter n = 8)(
output
input
input

else
endmodule
reg [n-1:0] out

[n-1:0] in
reset
clock
out <= 0;
out <= out ^ in;
,
,
,
);
The reset input is added because it is used in real applications. Also, a reset input is good in simulation
because makes the simulation possible allowing an initial value for the ip-ops (reg[n-1:0] out in
module t reg) used in design.
It is obvious that CCOU N T (n) O(1) because the denition for any n has the same, constant
size (in number of symbols used to write the Verilog description for it or in the area occupied
by the drawing of COU N Tn ). The size of COU N Tn , according to the Denition 4.4, can be
computed starting from the following iterative form:
SCOU N T (n) = SCOU N T (n 1) + (n + 1) + ST
and results:
SCOU N T (n) O(n2 )
because of the AND gates network used to command the T ip-op. The counting time is the
clock period. The minimal clock period is limited by the propagation time inside the structure.
It is computed as follows:
TCOU N T (n) = tpT + tpAN Dn + tSU O(log n)
where: tpT O(1) is the propagation time through the T ip-op, tpAN Dn O(log n) is the
propagation time through the AN Dn (in the fastest version it is implemented using a tree of
AN D2 gates) gate and tSU O(1) is the set-up time at the input of T ip-op.
206
In order to reduce the size of the counter we must nd another way to solve the function
performed by the network of ANDs. Obviously, the network of ANDs is an AND prex-network.
Thus, the problem could be reduced to the problem of the general form of prex-network. The
optimal solution exists and has the size in O(n) and the time in O(log n) (see in this respect
the section 8.2).
Finishing this short discussion about counters must be emphasized the autonomy of this
circuit which consists in switching in the next state according to the current state. We tell
simply to the circuit please count, and the circuit know what to do. The loop allow him to
know how to behave.
Real applications uses more complex counters able to be initialized in any states or the count
in both ways, up and down. Such a counter is described by the following code:
module full_counter #(parameter n = 4)(output
input
input

if (reset)
else if (load)
else if (count) if (down)
else
else
endmodule
reg [n-1:0] out

[n-1:0] in
reset
load
down
count
clock
out
out
out
out
out
<=
<=
<=
<=
<=
0
in
out - 1
out + 1
out
,
,
,
,
,
,
);
;
;
;
;
;
The reset operation has the highest priority, and the counting operations have the lowest
priority.
8.3.2
Accumulator Automaton
The accumulator automaton is a generalization of the counter automaton. A counter can add 1 to the
value of its state in each clock cycle. An accumulator automaton can add in each clock cycle any value
applied on its inputs.
Many applications require the accumulator function performed by a system which adds a string of
numbers returning the nal sum and all partial results the prexes. Let be p numbers x1 , . . . , xp . The
sum-prexes are:
y1 = x1
y2 = x1 + x2
y3 = x1 + x2 + x3
...
yp = x1 + x2 + . . . + xp .
This example of arithmetic automata generates at each clock cycle one prex starting with y1 . The
initial value in the register Rm+n is zero. The structure is presented in Figure 8.7 and consists in an
adder, ADDm+n , two multiplexors and a state register, Rm+n . This automaton has 2m+n states and
computes sum prexes for p = 2m numbers, each represented with n bits. The supplementary m bits are
needed because in the worst case adding two numbers of n bits results a number of n + 1 bits, and so
on, ... adding 2m n-bit numbers results, in the worst case, a n + m-bit number. The automaton must
be dimensioned such as in the worst case the resulting prex can be stored in the state register. The
two multiplexors are used to initialize the system clearing the register (for acc = 0 and clear = 1), to
maintain unchanged the accumulated value (for acc = 0 and clear = 0), or to accumulate the n-bit
input value (for acc = 1 and clear = 0). It is obvious the accumulate function has priority: for acc =
1 and clear = 1 the automaton accumulates ignoring the clear command.
8.3. FUNCTIONAL AUTOMATA: THE SIMPLE AUTOMATA
207
in
m
Am+n1
...
? ?
m+n
...
Bm+n1
A0
B0
ADDm+n
Sm+n1
...
S0
(m + n) EM U X
(m + n) EM U X
clear
acc
?
Rm+n
clock
?
out
Figure 8.7: Accumulator automaton. It can be used as sum prex automaton because in each
clock cycle outputs a new value as a result of a sequential addition of a stream of signed integers.
The size of the systems depends on the speed of adder and can be found between O(m + n) (for ripple
carry adder) and O((m + n)3 ) (for carry-look-ahead adder).
It is evident that this automaton is a simple one, having a constant sized denition. The four
components are all simple recursive dened circuits. This automaton can be build for any number of
states using the same denition. In this respect this automaton is a non-nite, functional automaton.
8.3.3
Bit-eater automaton
A very useful function is to search the bits of a binary word in order to nd the positions occupied by the
1s. For example, inspecting the number 00100100 we nd in 2 steps a 1 on the 5-th position and another
on the 2-nd position. A simple automaton does this operation in a number of clock cycles equal with the
number of 1s contained in its initial state. In Figure 8.8 is represented The bit-eater automaton which
is a simple machine containing:
in
next state
n
S0
1
0
n EM U X
load
n XOR
2
Rn
clock
state
eat
?
enable
out
DM U Xlog2 n
in
P En
out
zero
log2 n
?
out
in
?
n bit
Figure 8.8: Bit-eater automaton. Priority encoder outputs the index of the most signicant 1
in register, and the loop switches it into 0 using the demultiplexer to point it and a XOR to invert it.
208
an n-bit state register

a multiplexer used to initialize the automaton with the number to be inspected, if load = 1, then
the register takes the input value, else the automatons loop is closed
a priority encoder circuit which computes the index of the most signicant bit of the state and
activates the demultiplexer (E = 0), if its enable input is activated, (eat = 1)
an enabled decoder (or a demultiplexor) which decodes the value generated by the priority encoder
applying 1 only to the input of one XOR circuit if zero = 0 indicating at least one bit of the state
word is 1
n 2-input XORs used to complement the most signicant 1 of the state.
In each clock cycle after the initialization cycle the output takes the value of the index of the most
signicant bit of state having the value 1, and the next state is computed clearing the pointed bit.
Another, numerical interpretation is: while state = 0, the output of the automaton takes the integer
value of the base 2 logarithm of the state value, |log2 (state)|, and the next state will be next state =
state |log2 (state)|. If state = 0, then n bit = 1, the output takes the value 0, and the state remains in
0.
8.4
Composing with simple automata
Using previously dened simple automata some very useful subsystem can be designed. In this section are
presented some subsystems currently used to provide solutions for real applications: Last-In First-Out
memory (LIFO), First-In-First-Out memory (FIFO), and a version of the multiply accumulate circuit
(MACC). All are simple circuits because result as simple compositions of simple circuits, and all are
expandable for any n . . . m, where n . . . m are a parameters dening dierent part of the circuit. For
example, the memory size and the word size are independent parameters is a FIFO implementation.
8.4.1
LIFO memory
The LIFO memory or the stack memory has many applications in structuring the processing systems. It
is used both for building the control part of the system, or for designing the data section of a processing
system.
Denition 8.5 LIFO memory implements a data structure which consists in a string of maximum 2m
n-bit recordings accessed for write, called push, and read, called pop, at the same end called top of
stack (tos).
A possible implementation of a LIFO is presented in Figure 11.1, where:
RAM is an asynchronous random access memory organized in 2m n-bit words
Up/Down Counter which is a simple automaton composed by:
REG, an m-bit register
INC/DEC is a combinational circuit whose output provides:
REG if {push, pop} = 00
REG + 1 if {push, pop} = 10
REG 1 if {push, pop} = 01
the NOR gate generate the we signal for RAM when push is executed.
The Up/Down Counter circuit works like a pointer into a RAM. The pointer moves up or down
according with the current operation.
Example 8.2 A Verilog description of the previously dened LIFO (stack), for n = 8 and m = 6, is:
8.4. COMPOSING WITH SIMPLE AUTOMATA
out
in
n
209
- in
out
addr
RAM
Up/Down Counter
m
?
we
REG
INC/DEC
dec
inc

push
clock
pop
Figure 8.9: LIFO memory. The up/downn counter is used as stack pointer to organize in a RAM a
LIFO (stack) memory. Each push increments the pointer and each pop decrement it. The top of stack
(tos) is continuously accessible on out.
module simple_stack(
reg
reg
wire
[7:0]
[5:0]
[5:0]
output
input
input
[7:0]
[7:0]
top_of_stack,
in
,
push
,
pop
,
reset
,
clock
);
ram[0:63];
stack_pointer;
ram_addr;

if (reset) stack_pointer <= 0; // for simulation reasons only
else
stack_pointer <= ram_addr;
assign
ram_addr = stack_pointer + push + {6{pop}},

top_of_stack = ram[ram_addr];
always @(ram_addr or push or clock) if (~clock & push) ram[ram_addr] = in;

endmodule
The previous solution has some weaknesses. The rst weakness is the dependency by the duty cycle
of the clock signal. The position and the length of the active level of the we signal (see Figure 11.1) is
critical if the system is designed to run fast. The second weakness is due to the hold times for both, data
and address related to the last edge of the we signal. The two problems are solved using a synchronous
RAM instead of an asynchronous one.
Example 8.3 An improved version of stack for high speed applications means to substitute the last two
lines in the previous Verilog module with:
...
always @(posedge clock) if (push) ram[ram_addr] = in;
endmodule
210
Faster implementations can be done using registers instead of dierent kind of RAMs and counters.
For big stacks, optimized solutions are obtained combining a small register implemented stack with a big
RAM based implementation.
In real applications more complex stacks are used. For example, in certain actual machines the rst
two recordings, the top of stack and the previously pushed data, are both accessible to operate on.
8.4.2
FIFO memory
The FIFO memory, or the queue memory is used to interconnect subsystems working logical, or both
logical and electrical, asynchronously.x
Denition 8.6 FIFO memory implements a data structure which consists in a string of maximum 2m nbit recordings accessed for write and read, at its two ends. Full and empty signals are provided indicating
the write operation or the read operation are not allowed.
in
we
write counter
up
rst
out
out
in
RAM
- w addr[n-1:0]
r addr[n-1:0]
clock
read counter
up
rst
reset
write
- w addr[n-1:0] eq r addr[n-1:0]
w addr[n]
full
read
r addr[n]
empty
Figure 8.10: FIFO memory. Two pointers, evolving in the same direction, and a two-port RAM
implement a LIFO (queue) memory. The limit ags are computed combinational from the addresses used
to write and to read the memory.
A FIFO is considered synchronous if both read and write signals are synchronized with the same clock
signal. If the two commands, read and write, are synchronized with dierent clock signals, then the FIFO
memory is called asynchronous.
In Figure 8.10 is presented a solution for the synchronous version, where:
RAM is a 2n m-bit words two-port asynchronous random access memory, one port for write to
the address w addr and another for read form the address r addr
write counter is an (n + 1)-bit resetable counter incremented each time a write is executed; its
output is w addr[n:0], initially it is reset
read counter is an (n + 1)-bit resetable counter incremented each time a read is executed; its
output is r addr[n:0], initially it is reset
eq is a comparator activating its output when the least signicant n bits of the two counters are
identical.
8.4. COMPOSING WITH SIMPLE AUTOMATA
211
FIFO works like a circular memory addressed by two pointers (w addr[n-1:0] and r addr[n-1:0])
running on the same direction. If the write pointer after a write operation becomes equal with the read
pointer, then the memory is full and the full signal is 1. If the read pointer after a read operation becomes
equal with the write pointer, then the memory is empty and the empty signal is 1. The n + 1-th bit in
each counter is used to dierentiate between empty and full when w addr[n-1:0] and r addr[n-1:0]
are the same. If w addr[n] and r addr[n] are dierent, then w addr[n-1:0] = r addr[n-1:0] means
full, else it means empty.
The circuit used to compare the two addresses is a combinational one. Therefore, its output has a
hazardous behavior which aects the outputs full and empty. These two outputs must be used carefully
in designing the system which includes this FIFO memory. The problem can be managed because the
system works in the same clock domain (clock is the same for both ends of FIFO and for the entire
system). We call this kind of FIFO synchronous FIFO.
VeriSim 8.1 A Verilog synthesisable description of a synchronous FIFO follows:
module simple_fifo(output [31:0] out
output
empty
output
full
input
[31:0] in
input
write
input
read
input
reset
input
clock
wire
[9:0]
write_addr, read_addr;
counter write_counter(
read_counter(
.out
.reset
.count_up
.clock
.out
.reset
.count_up
.clock
dual_ram memory(.out
.in
.read_addr
.write_addr
.we
.clock
assign
eq
phase
empty
full
=
=
=
=
,
,
,
,
,
,
,
);
(write_addr
(reset
(write
(clock
(read_addr
(reset
(read
(clock
),
),
),
)),
),
),
),
));
(out
),
(in
),
(read_addr[8:0] ),
(write_addr[8:0]),
(write
),
(clock
));
read_addr[8:0] == write_addr[8:0] ,
~(read_addr[9] == write_addr[9]) ,
eq & phase
,
eq & ~phase
;
endmodule
module counter(output
input
input
input
reg [9:0]
out
,
reset
,
count_up,
clock
);

out <= 0;
else if (count_up) out <= out + 1;
endmodule
module dual_ram(
output
[31:0]
out
212
input
[31:0] in
input
[8:0]
read_addr
input
[8:0]
write_addr
input
we
input
clock
reg
[63:0] mem[511:0];
assign
out = mem[read_addr]
;
always @(posedge clock) if (we) mem[write_addr]
endmodule
,
,
,
,
);
<= in
An asynchronous FIFO uses two independent clocks, one for write counter and another for read
counter. This type of FIFO is used to interconnect subsystems working in dierent clock domains. The
previously described circuit is unable to work as an asynchronous FIFO. The signals empty and full
are meaningless, being generated in two clock domains. Indeed, write counter and read counter are
triggered by dierent clocks generating the signal eq with hazardous transitions related to two dierent
clocks: write clock and read clock. This signal can not be used neither in the system working with write
clock nor in the system working with read clock. Read clock is unable to avoid the hazard generated by
write clock, and write clock is unable to avoid the hazard generated by read clock. Special tricks must be
used.
8.4.3
The Multiply-Accumulate Circuit
The functional automata can be composed in order to perform useful functions in a digital system.
Otherwise, we can say that a function can be decomposed in many functional units, some of them
being functional automata, in order to implement it eciently. Lets take the example of the MultiplyAccumulate Circuit (MACC) and implement it in few versions. It is mainly used to implement one of the
most important numerical functions performed in our digital machines, the scalar product of two vectors:
a1 b1 + . . . + an bn . The MACC circuit is implemented in the next paragraphs in three dierent ways.
# With 2-radix multiplication

# With 4-radix multiplication
With bits eater automaton
We will oer in the following a solution involving two serially connected functional automata: an accumulator automaton and bits eater automaton.
The starting idea is that the multiplication is also an accumulation. Thus we use an accumulator
automaton for implementing both operations, the multiplication and the sum of products, without any
loss in the execution time.
The structure of the multiply-accumulate circuit is presented in Figure 8.12 and consists in:
bits eater automaton used to indicates successively the positions of the bits having the value 1
from the rst operand ai ; it also points out the end of the multiplication (see Figure 8.8)
combinational shifter shifts the second operand, bi , with a number of positions indicated by the
previous automaton
accumulate automaton performs the partial sums for each multiplication step and accumulate the
sum of products, if it is not cleared after each multiplication (see Figure 8.7).
In order to execute a multiplication only we must execute the following steps:
load the beat-eater automaton with the rst operand and clear the content of the output register
in accumulator automaton
select to the input the second operand which remains applied to the input of the shifter circuit
during the operation
wait for the end of operation indicated by the done output.
8.5. FINITE AUTOMATA: THE COMPLEX AUTOMATA
in1
213
in0
??
load
??
reg1
reg0
selects the number with less 1s
mux
mux
REDA1
?
REDA0
COMP
?

SHIFTER
start
BIT EATER
AUTOMATON
ADDER
?
outReg

done
readOut
?out
Figure 8.11:
The operation is performed in a number of clock cycles equal with the number of 1s of the rst operand.
Thus, the mean execution time is proportional with n/2. To understand better how this machine works
the next example will be an automaton which controls it.
If a MACC function is performed the clear of the state register of the accumulator automaton is
avoided after each multiplication. Thus, the register accumulates the results of the successive multiplications.
8.5
Finite Automata: the Complex Automata
After presenting the elementary small automata and the large and simple functional automata
it is the time to discuss about the complex automata. The main property of these automata
is to use a random combinational circuit, CLC, for computing the state transition function and
the output transition function. Designing a nite automaton means mainly to design two CLC:
the loop CLC (associated to the state transition function f ) and the output CLC (associated to
the output transition function g).
8.5.1
Basic Congurations
The half automaton is an automaton without the output function (see Figure 8.13a,b) dened
only for theoretical reasons (see Appendix G). The utility of this concept is due to the fact
that many optimization techniques are related only with the loop circuits of the automaton.
The main feature of the automaton is the autonomy and the half-automaton concept describes
especially this type of behavior.
All kind of automata can be described starting from a half-automaton, adding only combinational (no loops) circuits and/or memory (one loop) circuits. In Figure 8.13 are presented all
214
clock
in
load
?
in
?
load
nop
Bit-Eater Automaton
data in
SHIFTER shift
out
out
eat
n bit
2n
done
in
Accumulate Automaton
clear
acc
clear
out
2n+m
?
out
Figure 8.12: A multiply-accumulate circuit (MAC). A sequential version of MAC results

serially connecting an automaton, generating by turn the indexes of the binary ranges equal with 1 in
multiplier, with a combinational shifter and an accumulator.
the four types of automata:

Mealy automaton : results connecting to the output of an A1/2 the output CLC that receives also the input X (Figure 8.13c) and computes the output function g; a combinational
way occurs between the input and the output of this automaton allowing a fast response,
in the same clock cycle, to the input variation
Moore automaton : results connecting to the output of an A1/2 the output CLC (Figure
8.13d) that computes the output function g; this automaton reacts to the input signal in
the next clock cycle
delayed Mealy automaton : results serially connecting a register, R, to the output of the
Mealy automaton (Figure 8.13e); this automaton reacts also to the input signal in the
next clock cycle, but the output is hazard free because it is registered
delayed Moore automaton : results serially connecting a register, R, to the output of the
Moore automaton (Figure 8.13f); this automaton reacts to the input signal with a two
clock cycles delay.
Real applications use all the previous type of automata, because they react with dierent
delay to the input change. The registered outputs are preferred if possible.
8.5.2
Designing Finite Automata
The behavior of a nite automaton can be dened in many ways. Graphs, transition tables, owcharts, transition V/K diagrams or HDL description are very good for dening the transition
functions f and g. All this forms provide non-recursive denitions. Thus, the resulting automata
has the size of the denition in the same order with the size of the structure. Therefore, the
nite automata are complex structures even when they have small size.
215
? ?
loopCLC
halfAut
?
CK
a.
?
b.
halfAut
X
CK
stateReg
halfAut
CK
CK
?
-
outCLC
outCLC
c.
?
Y
d.
halfAut
X
halfAut
CK
CK
?
-
outCLC
outCLC
outReg
outReg
?
e.
?
f.
Figure 8.13: Automata types. a. The structure of the half-automaton (A1/2 ), the no-output
automaton: the state is generated by the previous state and the previous input. b. The logic symbol
of half-automaton. c. Immediate Mealy automaton: the output is generated by the current state and
the current input. d. Immediate Moore automaton: the output is generated by the current state. e.
Delayed Mealy automaton: the output is generated by the previous state and the previous input. f.
Delayed Moore automaton: the output is generated by the previous state.
In order to exemplify the design procedure for a nite automaton let be two examples, one
dealing with a 1-bit input string and another related with a system built around the multiplyaccumulate circuit (MAC) previously described.
Example 8.4 The binary strings 1n 0m , for n 1 and m 1, are recognized by a nite halfautomaton by its internal states. Lets dene and design it. The transition diagram dening the
behavior of the half-automaton is presented in Figure 8.14, where:
q0 - is the initial state in which 1 must be received, if not the the half-automaton switches
in q3 , the error state
q1 - in this state at least one 1 was received and the rst 0 will switch the machine in q2
q2 - this state acknowledges a well formed string: one or more 1s and at least one 0 are
already received
q3 - the error state: an incorrect string was received.
216
reset
w
q0
^
q1
[10]
[11]
U
q3
[00]
[01]
q2
}
0
Figure 8.14: Transition diagram. The transition diagram for the half-automaton which recognizes
strings of form 1n 0m , for n 1 and m 1. Each circle represent a state, each (marked) arrow represent
a (conditioned) transition.
Q1
Q0
Q1
Q0
X0 1
X0 X0 0
*+
Q1 , Q+
0
f (Q1 , Q0 , X0 ) = {Q+
, Q+
}
1
0
Q1 , Q0
a.
Q1
Q0
0 X0
Q1
X0
X0
Q0
Q+
1
X0
X0
Q+
0
c.
b.
Figure 8.15: VK transition maps. The VK transition map for the half-automaton used to recognize
1n 0m , for n 1 and m 1. a. The state transition function f . b. The VK diagram for the next most
signicant state bit, extracted from the previous full diagram. c. The VK diagram for the next least
signicant state bit.
The rst step in implementing the structure of the just dened half-automaton is to assign
binary codes to each state.
In this stage we have the absolute freedom. Any assignment can be used. The only dierence
will be in the resulting structure but not in the resulting behavior.
For a rst version let be the codes assigned int square brackets in Figure 8.14. Results the
transition diagram presented in Figure 8.15. The resulting transition functions are:

Q+
1 = Q1 X0 = ((Q1 X0 ) )

Q+
0 = Q1 X0 + Q0 X0 = ((Q1 X0 ) (Q0 X0 ))
(The 1 from q0+ map is double covered. Therefore, it is taken into consideration as a dont
care.) The circuit is represented in Figure 8.16 in a version using inverted gated only. The
2-bit state register is designed by 2 D ip-ops. The reset input is applied on the set input of
D-FF1 and on the reset input of D-FF0.
The Verilog behavioral description of the automaton is:
module rec_aut( output
input
reg [1:0]
state
in
,
,
X0 reset
clock
Q+
1
217
D
D-FF1
Q+
0
- R
D
D-FF0
Q1
Q
Q0
Figure 8.16: A 4-state nite half-automaton. The structure of the nite half-automaton used
to recognize binary string belonging to the 1n 0m set of strings.
input
reset
,
input
clock
);
if (reset) state <= 2b10;
else
case(state)
2b00: state <= 2b00
2b01: state <= {1b0, ~in}
2b10: state <= {in, in}
2b11: state <= {in, 1b1}
endcase
endmodule
;
;
;
;
Example 8.5 The execution time of the MAC circuit is data dependent, depends on how many 1s contains the multiplicand. Therefore, the data ow through it has no a x rate. The best way to interconnect
this version of MAC circuit supposes two FIFOs, one to its input and another to its output. Thus, a
exible buered way to interconnect MAC is provided.
reset
clock
(end)
reset
IN FIFO
read
empty
in
MAC
clear
load
nop
done

?
-
Finite Automaton
reset
out
full
write
OUT FIFO
reset
Figure 8.17: The Multiply-Accumulate System. The system consists in a multiply-accumulate

circuit (MAC), two FIFOs and a nite automaton (FA) controlling all of them.
218
A complex nite automaton must be added to manage the signals and the commands associated
with the three simple subsystems: IN FIFO, OUT FIFO, and MAC (see Figure 8.17). The ow-chart
describing the version for performing multiplications is presented in Figure 8.18, where:
q0 : wait first state the system waits to have at least one operand in IN FIFO, clearing in the same
time the output register of the accumulator automaton, when empty = 0 reads the rst operand
from IN FIFO and loads it in MAC
q1 : wait second state if IN FIFO is empty, the system waits for the second operand
q2 : multiply state the system perform multiplication while done = 0
q3 : write state the system writes the result in OUT FIFO and read the second operand from IN FIFO
if full = 0 to access the rst operand for the next operation, else waits while full = 1.
reset
q0
00
(00)
clear, nop
1
empty
load, read
q1
empty
01
(01)
0
q2
nop
q3
full
done
11
(10)
0
10
(11)
0
write, read
Figure 8.18: Flow chart describing a Mealy nite automaton. The ow-chart describes the
nite automaton FA from Figure 8.17, which controls MAC and the two FIFOs in MAC system. (The
state coding shown in parenthesis will be used in the next chapter.)
The ow chart can be translated into VK transition maps (see Figure 8.19) or in a Verilog description.
From the VK transition maps result the following equations describing the combinational circuits for the
loop (q1+ , q0+ ) and for the outputs.
Q+
1 = Q1 Q0 + Q0 empty + Q1 f ull
Q+
0 = Q1 Q0 + Q0 done + Q1 empty
clear = Q1 Q0
nop = Q1 Q0 + Q1 empty
load = Q1 Q0 empty
read = Q1 Q0 f ull + Q1 Q0 empty
Q1
Q0
Q1
11
01
10
00
Q0
Q1
Q0
empty
done
Q1
Q1
Q0
Q+
0
nop
clear
Q1
Q1
Q0
Q1
Q0
Q0
empty
full empty
load
empty
Q0
empty
full
Q+
1
1
empty
Q+
, Q+
1
0
Q1
1
done empty
1
full
reference
Q0
219
full
write
read
Figure 8.19: Veitch-Karnaugh transition diagrams. The transition VK diagrams for FA (see
+
Figure 8.17). The reference diagram has a box for each state. The state transition diagram, Q+
1 Q1 ,
contains in the same positions the description of the next state. For each output a diagram describe the
outputs behavior in the corresponding state.
write = Q1 Q0 f ull
The resulting circuit is represented in Figure 8.20, where the state register is implemented using 2 D
ip-ops and the combinational circuits are implemented using a PLA.
If we intend to use a software tool to implement the circuit the following Verilog description is a must.
module macc_control(read
write
load
clear
nop
empty
full
done
reset
clock
input
output
,
,
,
,
,
,
,
,
,
);
//
//
//
//
//
//
//
//
read from IN FIFO

write in OUT FIFO
load the multiplier in MAC
reset the output of MAC
stops the multiplication
IN FIFO is empty
OUT FIFO is full
the multiplication is concluded
empty, full, done, reset, clock;

read, write, load, clear, nop;
reg [1:0]
reg
state;
parameter
wait_first
wait_second
multiply
write_result
=
=
=
=
// as variables
2b00,
2b01,
2b11,
2b10;
// THE STATE TRANSITION FUNCTION

if (reset) state <= wait_first;
else
case(state)
wait_first : if (empty)
else
wait_second : if (empty)
else
multiply
: if (done)
state
state
state
state
state
<=
<=
<=
<=
<=
wait_first;
wait_second;
wait_second;
multiply;
write_result;
220
empty
full
done
+
q0
Q
q0
D
DF-F
read
write
load
Q
q1
clear
+
q1
D
nop
DF-F
Q
Half-automaton
clock
Figure 8.20: FAs structure. The FA is implemented with a two-bit register and a PLA with 5 input
variables (2 for state bits, and 3 for the input sibnals), 7 outputs and 10 products.
else
write_result: if (full)
else
endcase
state <= multiply;

state <= write_result;
state <= wait_first;
// THE OUTPUT TRANSITION FUNCTION (MEALY IMMEDIATE)

always @(state or empty or full or done)
case(state)
wait_first :
if (empty)
{read, write, load, clear, nop}
else
wait_second :
if (empty)
else
multiply
:
write_result:
if (full)
else
endcase
endmodule
= 5b00011;
= 5b10111;
= 5b00001;
= 5b00000;
= 5b00000;
= 5b00000;
= 5b11000;
The resulting circuit will depend by the synthesis tool used because the previous description is too
behavioral. There are tools which will synthesize the circuit codding the four states using four bits ....!!!!!.
If we intend to impose a certain solution, then a more structural description is needed. For example,
the following very structural code which translate directly the transition equations extracted from VK
transition maps.
module macc_control(read
write
,
,
// read from IN FIFO

// write in OUT FIFO

load
clear
nop
empty
full
done
reset
clock
input
output
,
,
,
,
,
,
,
);
//
//
//
//
//
//
221
load the multiplier in MAC

reset the output of MAC
stops the multiplication
IN FIFO is empty
OUT FIFO is full
the multiplication is concluded
empty, full, done, reset, clock;

reg [1:0]
state;
// as an actual register
// THE STATE TRANSITION FUNCTION

if (reset) state <= 2b00;
else state <= {(state[1] & state[0] | state[0] & ~empty |
state[1] & full),
(~state[1] & state[0] | state[0] & ~done |
~state[1] & ~empty)};
assign
read
write
load
clear
nop
= ~state[1] & ~state[0] & ~empty |

state[1] & ~state[0] & ~full,
= state[1] & ~state[0] & ~full,
= ~state[1] & ~state[0] & ~empty,
= ~state[1] & ~state[0],
= ~state[1] & ~state[0] | ~state[1] & empty;
endmodule
The resulting circuit will be eventually an optimized form of the version represented in Figure 8.20
because instead a PLA, the current tools use an minimized network of gates.
The nite automaton has two distinct parts:

the simple, recursive dened part, that consists in the state register; it can be minimized
only by minimizing the denition of the automaton
the complex part, that consists in the PLA that computes functions f and g and this is
the part submitted to the main minimization process.
Our main goal in designing nite automaton is to reduce the random part of the automaton,
even if the price is to enlarge the recursive dened part. In the current VLSI technologies we
prefer big size instead of big complexity. A big sized circuit has now a technological solution,
but for describing very complex circuits we have not yet ecient solutions (maybe never).
8.5.3
Control Automata: the First Turning Point
A very important class of nite automata is the class of control automata. A control automaton is
embedded in a system using three main connections (see Figure 8.21):
the p-bit input operation[p-1:0] selects the control sequence to be executed by the control
automaton (it receives the information about what to do); it is used to part the ROM in 2p
parts, each having the same dimension; in each part a sequence of maximum 2n operation can be
stored for execution
the m-bit command output, command[m-1:0], the control automaton uses to generate the command toward the controlled subsystem
222
the n-bit input flags[q-1:0] the control automaton uses to receive information, represented by
some independent bits, about what happens in the controlled subsystems commanded by the
output command[m-1:0].

flags[q-1:0]
What happens
operation[p-1:0]
What to do
CLC(ROM)

?
?Q
state[n-1:0]
command[m-1:0]
The command
Figure 8.21: Control Automaton. The functional denition of control automaton. Control means
to issue commands and to receive back signals (ags) characterizing the eect of the command.
The size and the complexity of the control sequence asks the replacement of the PLA with a ROM,
at least for the designing and testing stages in implementing the application. The size of the ROM has
the magnitude order:
SROM (n, p, q) O(2n+p+q ).
In order to reduce the ROMs size we start from the actual applications which emphasize two very
important facts:
1. the automaton can store the information about what to do in the state space, i.e., each current
state belongs to a path through the state space, started in one initial state given by the code used
to specify the operation
2. in most of the states the automaton tests only one bit from the flags[q-1:0] input and if not, a
few additional states in the ow-chart solve the problem in most of the cases.
nEM U X
S0
CLC(ROM)
operation[n-1:0]

?
MOD
command[m-1:0]
flags[q-1:0]
.
.
.
TEST
NEXT
M U Xq
Figure 8.22: Optimized version of control automata. The ags received from the controlled
system have independent meaning considered in distinct cycles. The ag selected by the code TEST, T,
decides from what half of ROM the next state and output will be read.
223
Starting from these remarks the structure of the control automaton can be modied (see Figure 8.22).
Because the sequence is only initialized using the code operation[n-1:0], this code is used only for
addressing the rst command line from ROM in a single state in which M OD = 1. For this feature we
must add n EMUXs and a new output to the ROM to generate the signal M OD. This change allows
us to use in a more exible way the storing space of ROM. Because a control sequence can have the
dimension very dierent from the dimension of the other control sequence it is not ecient to allocate x
size part of ROM for each sequence as in we did in the initial solution. The version presented in Figure
8.22 uses for each control sequence only as much of space as needed to store all lines of command.
The second modication refers to the input flags[q-1:0]. Because the bits associated with this
input are tested in dierent states, M U Xq selects in each state the appropriate bit using the t-bit eld
TEST. Thus, the q 1 bits associated to the input flags[q-1:0] are removed from the input of the
ROM, adding only t output bits to ROM. Instead of around q bits we connect only one, T, to the input
of ROM.
This new structure works almost the same as the initial structure but the size of ROM is very strongly
minimized. Now the size of the ROM is estimated as being:
SROM (2n ).
Working with the control automaton in this new version we will make another remark: the most part
of the sequence generated is organized in a linear sequence. Therefore, the commands associated to the
linear sequences can be stored in ROM at the successive addresses, i.e., the next address for ROM can be
obtained incrementing the current address stored in the register R. The structure represented in Figure
8.23 results. What is new in this structure is an increment circuit connected to the output of the state
register and a small combinational circuit that transcodes the bits M1 , M0 , T into S1 and S0 . There are
4 transition modes coded by M1 , M0 :

n
CLC(ROM)
nM U X4
S1 S0
2
1
0

operation[n-1:0]
66
command[m-1:0]
INC
MOD
TEST
flags[q-1:0]
.
.
.
?
MUXT
JUMP
?
TC
Figure 8.23: The simplest Controller with ROM (CROM). The Moore form of control
automaton is optimized using an incremented circuit (INC) to compute the most frequent next address
for ROM.
inc, codded by M1 M0 = 00: the next address for ROM results by incrementing the current address;
the selection code must be S1 S0 = 00
jmp, codded by M1 , M0 = 01: the next address for ROM is given by the content of the one eld to
the output of ROM; the selection code must be S1 S0 = 01
cjmp, codded by M1 , M0 = 10: if the value of the selected ag, T, is 1, then the next address
for ROM is given by the content of the one eld to the output of ROM, else the next address for
ROM results by incrementing the current address; the selection code must be S1 S0 = 0T
init, codded by M1 , M0 = 11: the next address for ROM is selected by nM U X4 from the initialization input operation; the selection code must be S1 S0 = 1
224
Results the following logic functions for the transcoder TC: S1 = M1 M0 , S0 = M1 T + M0 .

The output of ROM can be seen as a microinstruction dened as follows:
<microinstruction>::= <setLabel> <Command> <Mod> <Test> <useLabel>;
<command>::= <to be defined when use>;
<mod>::= jmp | cjmp | init | inc ;
<test>::= <to be defined when use>;
<setLabel>::= setLabel(<number>);
<useLabel>::= useLabel(<number>);
<number>::= 0 | 1 | ... | 9 | <number><number>;
This last version will be called CROM (Controller with ROM) and will be considered, in the present
approach, to have enough functional features to be used as controller for the most complex structures
described in this book.
Very important comment! The previous version of the control automatons structure is characterized by two processes:
the rst is the increasing of the structural complexity.
the second is the decreasing of the dimension and of the complexity of the binary conguration
stored in ROM.
In this third step both, the size and the complexity of the system grows without any functional improvement. The only eect is reducing the (algorithmic) complexity of ROMs content.
We are in a very important moment of digital system development, in which the physical complexity
starts to compensate the symbolic complexity of ROMs content. Both, circuits and symbols, are
structures but there is a big dierence between them. The physical structures have simple recursive
denitions. The symbolic content of ROM is (almost) random and has no simple denition.
We agree to grow a little the complexity of the physical structure, even the size, in order to create the
condition to reduce the eort to set up the complex symbolic content of ROM.
This is the rst main turning point in the development of digital systems. We have here the rst
sign about the higher complexity of symbolic structures. Using recursive dened objects the physical
structures are maintained at smaller complexity, rather than the symbolic structures, that must assume
the complexity of the actual problems to be solved with the digital machines. The previous dened
CROM structure is so thought as the content of ROM to be easy designed, easy tested and easy maintained
because it is complex. This is the rst moment, in our approach, when the symbolic structure has more
importance than the physical structure of a digital machine.
Example 8.6 Lets revisit the automaton used to control the MAC system. Now, because a more powerful
tool is available, the control automaton will perform three functions, multiply, multiply and accumulate,
no operation, codded as follows:
mult: op = 01,
macc: op = 11,
noop: op = 00.
The CROM circuit is actualized in Figure 8.24 with the word of ROM organized as follows:
<microinstruction>::= <setLabel><Command> <Mod> <Test> <useLabel>
<command>::= <c1> <c2> <c3> <c4> <c5>
<c1> ::= nop | <c2> ::= clear | <c3> ::= load | <c4> ::= read | <c5> ::= write | <mod>::= jmp | cjmp | init | inc
<test>::= empty | full | done | stop | n_done | n_empty
<setLabel>::= setLabel(<number>);
<useLabel>::= useLabel(<number>);
<number>::= 0 | 1 | ... | 9 | <number><number>;
225
clock
3
ROM
MUX
S1 S0
nop
clear
load
read
write

1
0
6 6
5
4
3 MUXT
2
1
0
reset
INC
5
jumpAddr
?
-
2
mode
test
n empty
n done
empty
full
done
stop
{0, 0, op[1], op[1], op[0]}
?2
- TC
T
Figure 8.24: Using a CROM. A more complex control can be done for Multiply Accumulate System
using a CROM instead of a standard nite automaton.
The elds <c1> ... <c5> are one-bit elds takeing the value 0 for -. When nothing is specied,
then in the corresponding position is 0. The bit end is used to end the accumulation. If stop = 0 the macc
operation does not end, the system waits for a new pairs of numbers to be multiplied and accumulated.
The result is sent out only when stop = 1.
The function mult is dened in the owchart from Figure 8.20 as a Mealy automaton. Because the
CROM automaton is dened as a Moore automaton the code sequence will be dened takeing into account
the Moore version of the control multiply-accumulate automaton. The function macc is dened in Figure
8.25 as a Moore automaton. The function nop consist in looping in the reset state waiting for a command
dierent from nop. The content of ROM has the following symbolic denition:
// no operation
setLabel(0)
// multiplication
setLabel(1)
setLabel(2)
setLabel(3)
setLabel(4)
// multiply and
setLabel(5)
setLabel(8)
setLabel(6)
setLabel(7)
setLabel(9)
init;
nop
nop
nop
cjmp
cjmp
read
accumulate
nop
nop
nop
cjmp
read
cjmp
cjmp
cjmp
// 00000
clear
load
cjmp
done
full
write
cjmp
read
empty
setLabel(3);
setLabel(4);
jmp
empty
setLabel(1);
inc;
setLabel(2);
clear
load
cjmp
n_done
inc;
n_empty
stop
empty
cjmp
read
empty
setLabel(7);
empty
setLabel(5);
inc;
setLabel(6);
setLabel(8);
setLabel(10);
setLabel(9);
setLabel(0);
//
//
//
//
//
//
//
//
q0
q1
q2
q3
q4
q5
q6
q9
226
init
clear, nop
empty
q0
0000
load, read, nop
q1
0001
nop
q2
0010
empty
q3
0011
0
1
done
q4
0100
read
q5
0101
1
empty
q6
0110
1
stop
q7
0111
1
q9
1001
1
full
write
empty
q8
1000
Figure 8.25: Control owchart. The control owchart for the function macc.
setLabel(10)
jmp
cjmp
write
loop8;
full
jmp
setLabel(10);
setLabel(0);
// q10!
// q7
// q8
The binary sequence is stored in ROM starting from the address zero with the line labelled as
setLabel(0). The sequence associated to the function mult has 6 lines because a Moore automaton
has usually more states when the equivalent Mealy version. For macc function the correspondence with
the state are included in commentaries on each line. An additional state (q10) occurs also here, because
this version of CROM can not consider jump addresses depending on the tested bits; only one jump
address per line is available.
The binary image of the previous code asks codes for the elds acting on the loop.
Verilog descriptions for CROM

The most complex part in dening a CROM unit is the specication of the ROMs content. There are
few versions to be used. One is to provide the bits using a binary le, another is to generate the bits
using a Verilog program. Let us start with the rst version.
The description of the unit CROM implies the specication of the following parameters used for
dimensioning the ROM:
comDim: the number of bits used to encode the command(s) generated by the control automaton;
it depends by the system under control
227
adrDim: the number of bits used to encode the address for ROM; it depends on the number of
state of the control automaton
testDim: the number of bits used to select one of the ags coming back from the controlled system;
it depends by the functionality performed by the entire system.
The following description refers to the CROM represented in Figure 8.23. It is dimensioned to generate
a 5-bit command, to have maximum 32 internal states, and to evolve according to maximum 8 ags
(the dimensioning ts with the simple application presented in the previous example). Adjusting these
parameters, the same design can by reused in dierent projects. Depending on the resulting size of the
ROM, its content is specied in various ways. For small sizes the ROM content can be specied by a
hand written le of bits, while for big sizes it must be generated automatically starting from a friendly
denition.
A generic Verilog description of the simple CROM already introduced follows:
module crom #(include "0_parameter.v")(output [comDim - 1:0]
command ,
input [addrDim - 1:0]
operation,
input [(1 << testDim) - 1:0] flags
,
input
reset
,
input
clock
);
reg [addrDim - 1:0] stateRegister;
wire
wire
wire
wire
wire
wire
[comDim + testDim + addrDim + 1:0] romOut ;

flag
;
[testDim - 1:0]
test
;
[1:0]
mode
;
[addrDim - 1:0]
nextAddr;
[addrDim - 1:0]
jumpAddr;
rom rom(.address (stateRegister),

.data
(romOut
));
assign {command, test, jumpAddr, mode} = romOut,
flag = flags[test];
mux4 addrSelMux(.out(nextAddr
),
.in0(stateRegister + 1
),
.in1(jumpAddr
),
.in2(operation
),
.in3(operation
),
.sel({&mode, (mode[1] & flag | mode[0])}));
always @(posedge clock) if (reset) stateRegister <= 0
;
else
stateRegister <= nextAddr;
endmodule
The simple uniform part of the previous module consists in two multiplexer, an increment circuit,
and a register. The complex part of the module is formed by a very small one (the transcoder) and a big
one the ROM.
From the simple only the addrSelMux multiplexor asks for a distinct module. It follows:
module mux4 #(include "0_parameter.v")(out, in0, in1, in2, in3, sel);
input [1:0]
sel
;
input [addrDim - 1:0] in0, in1, in2, in3;
output [addrDim - 1:0] out
;
reg
[addrDim - 1:0] out
;
always @(in0 or in1 or in2 or in3 or sel)
228
case(sel)
2b00:
2b01:
2b10:
2b11:
endcase
endmodule
out
out
out
out
=
=
=
=
in0;
in1;
in2;
in3;
The big complex part has a rst version described by the following Verilog module:
module rom #(include "0_parameter.v")
(input [addrDim - 1:0]
address,
output [comDim + testDim + addrDim + 1:0] data
);
reg [comDim + testDim + addrDim + 1:0] mem [0:(1 << addrDim) - 1];
initial $readmemb("0_romContent.v", mem); // the fix content of the memory
assign data = mem[address]; // it is a read only memory
endmodule
The le 0 parameter.v denes the dimensions used in the project crom. It must be placed in the
same folder with the rest of the les dening the project. For our example its content is:
parameter comDim = 5,
addrDim = 5,
testDim = 3
The initial line loads in background, in a transparent mode, the memory module mem. The module
rom does not have explicit writing capabilities, behaving like a read only device. The synthesis tools
are able to infer from the previous description that it is about a ROM combinational circuit.
The content of the le 0 romContent.v is lled up according to the micro-code generated in Example
7.6. Obviously, after the rst 4 line the our drive to continue is completely lost.
/*
/*
/*
/*
//
/*
/*
00
01
02
03
*/
*/
*/
*/
30 */
31 */
00000_000_00000_11
11000_011_00001_10
10100_000_00000_00
10000_011_00011_10
...
00000_000_00000_00
00000_000_00000_00
Obviously, after lling up the rst 4 lines our internal drive to continue is completely lost. The full
solution asks for 270 bits free of error bits. Another way to generate them must be found!
Binary code generator

Instead of dening and writing bit by bit the content of the ROM, using a hand written le (in our
example 0 romContent.v), is easiest to design a Verilog description for a machine which takes a le
containing lines of microinstructions and translate it into the corresponding binary representation. Then,
in the module rom the line initial ...; must be substituted with the following line:
include "codeGenerator.v" // generates ROMs content using to theDefinition.v
which will act by including the the description of a loading mechanism for the memory mem. The
code generating machine is a program which has as input a le describing the behavior of the automaton.
Considering the same example of the control automaton for MAC system, the le theDefinition is a
possible input for our code generator. It has the following form:

// MAC control automaton
setLabel(0); init;
// multiplication
setLabel(1); nop;
clear;
nop;
load;
setLabel(2); nop;
cjmp;
setLabel(3); cjpm; done;
setLabel(4); cjmp; full;
read; write;
// multiply & accumulate
setLabel(5); nop;
clear;
setLabel(8); nop;
load;
setLabel(7); cjmp; notDone;
read; inc;
cjmp; notEmpty;
cjmp; stop;
setLabel(9); cjmp; empty
jmp;
useLabel(8);
setLabel(10); cjmp; full;
write; jmp;
cjmp;
read;
empty;
useLabel(3);
useLabel(4);
jmp;
229
empty;
useLabel(1);
inc;
useLabel(2);
useLabel(0);
cjmp;
empty;
read;
inc;
useLabel(7);
useLabel(5);
useLabel(8);
useLabel(10);
useLabel(9);
useLabel(10);
useLabel(0);
The theDefinition le consist in a stream of Verilog tasks. The execution of these tasks generate
the ROMa content.
The le codeGenerator.v understand and use the le theDefinition, whose content follows:
// Generate the binary content of the ROM
reg
nopReg
;
reg
clearReg
;
reg
loadReg
;
reg
readReg
;
reg
writeReg
;
reg [1:0] mode
;
reg [2:0] test
;
reg [4:0] address
;
reg [4:0] counter
;
reg [4:0] labelTab[0:31];
task endLine;
begin
mem[counter] =
{nopReg, clearReg, loadReg, readReg, writeReg, mode, test, address};
nopReg
= 1b0;
clearReg = 1b0;
loadReg = 1b0;
readReg = 1b0;
writeReg = 1b0;
counter = counter + 1;
end
endtask
// sets labelTab in the first pass associating counter with labelIndex
task setLabel; input [4:0] labelIndex; labelTab[labelIndex] = counter; endtask
// uses the content of labelTab in the second pass
task useLabel; input [4:0] labelIndex; begin address = labelTab[labelIndex];
endLine;
end
endtask
230
// external commands
task nop ; nopReg
= 1b1; endtask
task clear; clearReg = 1b1; endtask
task load ; loadReg = 1b1; endtask
task read ; readReg = 1b1; endtask
task write; writeReg = 1b1; endtask
// transition mode
task inc ; begin mode = 2b00; endLine; end endtask
task jmp ; mode = 2b01; endtask
task cjmp; mode = 2b10; endtask
task init; begin mode = 2b11; endLine; end endtask
// flag selection
task empty ; test = 3b000; endtask
task full
; test = 3b001; endtask
task done
task stop
task notDone; test = 3b100; endtask
task notEmpt; test = 3b101; endtask
initial begin counter
nopReg
clearReg
loadReg
readReg
writeReg
include
include
end
= 0;
= 0;
= 0;
= 0;
= 0;
= 0;
"theDefinition.v"; // first pass
"theDefinition.v"; // second pass
The le theDefinition is included twice because if a label is used before it is dened, only at the
second pass in the memory labelTab the right value of a label will be found when the task useLabel is
executad.
8.6
Automata vs. Combinational Circuits
As we saw, both combinational circuits (0-OS) and automata (2-OS) execute digital functions. Indeed,
there are combinational circuits performing addition or multiplication, but there are also sequential circuits performing the same functions. What is the correlation between a gates network and an automaton
executing the same function? What are the conditions in which we can transform a combinational circuit
in an automaton or conversely? The answer to this question will be given in this last section.
Let be a Mealy automaton, his two CLCs (LOOP CLC and OU T CLC), the initial state of the
automaton, q(t0 ) and the input sequence for the rst n clock cycle: x(t0 ), . . . , x(tn1 ). The combinational
circuit that generates the corresponding output sequence y(t0 ), . . . , y(tn1 ) is represented in Figure 8.26.
Indeed, the rst pair LOOP CLC, OU T CLC computes the rst output, y(t0 ), and the next state, q(t1 )
to be used by the second pair of CLCs to compute the second output and the next state, and so on.
Example 8.7 The ripple carry adder (Figure 6.16) has as correspondent automaton the adder automaton
from the serial adder (Figure 8.5).
Should be very interesting to see how a complex problem having associated a nite automaton can
be solved starting from a combinational circuit and reducing it to a nite automaton. Let us revisit in
the next example the problem of recognizing strings from the set 1a 0b , for a, b > 0.
Example 8.8 The universal combinational circuit (see 2.3.1) is used to recognize all the strings having
the form:
x0 , x1 , . . . xi , . . . xn1 1a 0b
8.6. AUTOMATA VS. COMBINATIONAL CIRCUITS
231
initial state
q(t0 )
x(t0 )
LOOP CLC
q(t1 )
x(t1 )
x(t2 )
LOOP CLC
q(t2 )
LOOP CLC
OUT CLC
OUT CLC
OUT CLC
y(t0 )
y(t1 )
y(t2 )
.
.
.
q(tn )
x(tn )
LOOP CLC
OUT CLC
y(tn )
6
?
Figure 8.26: Converting an automata into a combinational circuit. The conversion rule
from the nite (Mealy) automaton into a combinational logic circuit means to use a pair of circuits (LOOP
CLC, OUTPUT CLC) for each clock cycle. The time dimension is transformed in space dimension.
for a, b > 0, and a + b = n. The function performed by the circuit will be:
f (xn1 , . . . , x0 )
which takes value 1 for the following inputs:
xn1 , . . . , x0 = 0000 . . . 01
xn1 , . . . , x0 = 000 . . . 011
xn1 , . . . , x0 = 00 . . . 0111
...
xn1 , . . . , x0 = 00011 . . . 1
xn1 , . . . , x0 = 0011 . . . 11
xn1 , . . . , x0 = 011 . . . 111
Any function f (xn1 , . . . , x0 ) of n variables can be expressed using certain minterms from the set of
2n minterms of n variables. Our functions uses only n 1 minterms from the total number of 2n . They
are:
m2i 1
for i = 1, . . . (n 1), i.e., the functions takes the value 1 for m1 or m3 or m7 or m15 or . . ..
Figure 8.27 represents the universal circuits receiving as program the string:
. . . 001000000010001010
where 1s corresponds to minterms having the value 1, and 0s to the minterms having the value 0.
Initially the size of the resulting circuit is too big. For an n-bit input string from x0 to xn1 the circuits
contains 2n 1 elementary multiplexors. But, a lot of EMUXs have applied 0 on both selected inputs.
They will generate 0 on their outputs. If the multiplexors generating 0 are removed and substituted with
connections to 0, then the resulting circuit containing only n(n 1)/2 EMUXs is represented in Figure
8.28a.
The circuit can be more reduced if we take into account that some of them are identical. Indeed, on
the rst line all EMUXs are identical an the third (from left to right) can do the job of the rst tree
232
x0
x2
00
10
00
00
00
10
00
10
10
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
x1
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
x3
x4
s1w0
s1w0
xi
Figure 8.27: The Universal Circuit programmed to recognize 1a 0b . A full tree of 2n

EMUXs are used to recognize the strings belonging to 1a 0b . The program is applied on the selected
inputs of the rst level of EMUXs.
x0
10
10
10
s1w0
s1w0
s1w0
0
s1w0
x1
0
s1w0
0
s1w0
x2
s1w0
s1w0
s1w0
x3
x4
10
s1w0
s1w0
xi
a.
x0
0
s1w0
x1
0
s1w0
x2
x3
x4
0
s1w0
10
10
s1w0
s1w0
s1w0
s1w0
s1w0
s1w0
xi
b.
Figure 8.28: Minimizing the Universal Circuit programmed to recognize 1a 0b . a. The

rst step of minimizing the full tree of 2n 1 EMUXs to a tree containing 0.5n(n + 1) EMUXs. Each
EMUX selecting between 0 and 0 is substituted with a connection to 0. b. The minimal combinational
network of EMUXs obtained removing the duplicated circuits. The resulting network is a linear stream
of identical CLCs.
8.7. THE CIRCUIT COMPLEXITY OF A BINARY STRING
233
circuits. Therefore, the output of the third circuit from the rst line will be connected to the input of all
the circuits from the second line. Similarly, on the second line we will maintain only two EMUXs, and
so on on each line. Results the circuit from Figure 8.28b containing (2n 1) EMUXs.
This last form consists in a serial composition made using the same combinational circuit: an EMUX
and an 2-input AND (the EMUX with the input 0 connected to 0). Each stage of the circuit receives one
input value starting with x0 . The initial circuit receives on the selected inputs a x binary conguration
(see Figure 8.28b). It can be considered as the initial state of the automaton. Now we are in the position
to transform the circuit in a nite half-automaton connecting the emphasized module in the loop with a
2-bit state register (see Figure 8.29a).
The resulting half-automaton can be compared with the half-automaton from Figure 8.16, reproduced
in Figure 8.29b. Not-surprisingly they are identical.
xi reset
clock
reset
xi
clock
a.
?0
1 0
s
w
?
S - R
??
1 0
w
D-FF1
D-FF0
q1
+
q1
q0
D
D-FF1
Q
b.
+
q0
- R
D
D-FF0
q1
Q
q0
Figure 8.29: From a big and simple CLC to a small and complex nite automata.
a. The resulting half-automaton obtained collapsing the stream of identical circuits. b. Minimizing the
structure of the two EMUXs results a circuit identical with the solution provided in Figure 8.16 for the
same problem.
To transform a combinational circuit in a (nite) automaton the associated tree (or trees) of EMUXs
must degenerate into a linear graph of identical modules. An interesting problem is: how many of
programs, P = mp1 , mp2 , . . . m0 , applied as leaves of Universal Circuit allows the tree of EMUXs
to be reduced to a linear graph of identical modules?
8.7
The Circuit Complexity of a Binary String
Greg Chaitin taught us that simplicity means the possibility to compress. He expressed the complexity of
a binary string as being the length of the shortest program used to generate that string. An alternative
form to express the complexity of a binary string is to use the size of the smallest circuit used to generate
it.
Denition 8.7 The circuit complexity of a binary string P of length p, CCP (p), is the size of the
minimized circuit used to generate it.
Denition 8.8 The universal circuit used to generate any p-bit sting, pU-Generator, consists in a nUCircuit programmed with the string to be generated and triggered by a resetable counter (see Figure 8.30).
According to the actual content of the program P = mp1 . . . m0 the nU-Circuit can be reduced to
a minimal size using techniques previously described in the section 2.3. The minimal size of the counter
is in O(log p) (the rst proposal for an actual value is 11(1 + log2 p) + 5). Therefore, the minimal size
of pU-Generator, used to generate an actual string of p bits is the very precisely dened number CCP (p).
234
mp1 mp2
reset
start
m0
? ?
counter
nU-Circuit
clock
n = log2 p
pU-Generator
?
valid out
?
out
Figure 8.30: The universal string generator. The counter, starting from zero, selects to the
output out the bits of the program one by one starting with m0 .
Example 8.9 Let us compute the circuit size of the following 16-bit strings:
P 1 = 0000000000000000
P 2 = 1111111111111111
P 3 = 0101000001010000
P 4 = 0110100110110001
For both, P1 and P2 the nU-Circuit is reduced to circuits containing no gates. Therefore, CC(P 1) =
CC(P 2) = 11(1 + log2 16) + 5 + 0 = 60.
For P3, applying the removing rules the rst level of EMUXs in nU-Circuitis is removed and to the
inputs of the second level the following string is applied:
x0 , x0 , 0, 0, x0 , x0 , 0, 0
We continue applying removing and reducing rules. Results the inputs of the third level:
x0 x2 , x0 x2
The last level is removed because its inputs are identic. The resulting circuit is: x0 x2 . It has the size 3.
Therefore CC(P 3) = 60 + 3 = 63.
For P4, applying the removing rules results the following string for the second level of EMUXs:
x0 , x0 , x0 , x0 , x0 , 1, 0, x0
No removing or reducing rule apply for the next level. Therefore, the size of the resulting circuit is:
CC(P 4) = 1 + 7SEM U X + 88 = 103.
The main problem in computing the circuit complexity of a string is to nd the minimal form
of a Boolean function. Fortunately, there are rigorous formal procedures to minimize logic functions
(see Appendix C.4 for some of them). (Important note: the entire structure of pU-Generator can be
designed composing and closing loops in a structure containing only elementary multiplexors and inverters.
In the langauge of the partial recursive functions these circuits perform the elementary selection and the
elementary increment. Programming uses only the function zero and the elementary increment. No
restrictions imposed by primitive recursiveness or minimalization are applied!)
An important problem rises: how many of the n-bit variable function are simple? The answer comes
from the next theorem.
8.8. CONCLUDING ABOUT AUTOMATA
235
Theorem 8.1 The weight, w, of Turing-computable functions, of n binary variables, in the set of the
formal functions decreases twice exponentially with n.
n
Proof Let be a given n. The number of formal n-input function is N = 22 , because the denition
are expressed with 2n bits. Some of this functions are Turing-computable. Let be these functions dened
by the compressed m-bit strings. The value of m depends on the actual function, but is realized the
condition that max(m) < 2n and m does not depends by n. Each compressed form of m bits corresponds
only to one 2n -bit uncompressed form. Thus, the ratio between the Turing-computable function of and
the formal function, both of n variables, is smaller than
max(w) = 2(2
max(m))
And, because max(m) does not depends by n, the ratio has the same form for no matter how big becomes
n. Results:
n
max(w) = const/22 .
A big question arises: how could be combinational circuits useful with this huge ratio between complex
circuits and simple circuits? An answer could be: potentially this ratio is very high, but actually, in the
real world of problems this ratio is very small. It is small because we do not need to compute too many
complex functions. Our mind is usually attracted by simple functions in a strange manner for which we
do not have (yet?) a simple explanation.
The Turing machine is limited to perform only partial recursive functions (see Chapter 9 in this
book). The halting problem is an example of a problem that has no solutions on a Turing machine (see
subsection 9.3.5???? in this book). Circuits are more powerful but they are not so easyprogrammed
as the Turing Machine, and the related systems. We are in a paradoxical situation: the circuit does not
need algorithms and Turing Machine is limited only to the problems that have an algorithm. But without
algorithms many solutions exist and we do not know the way to nd them. The complexity of the
way to nd of a solution becomes more and more important.
The working hypothesis will be that at the level of combinational (without autonomy) circuits the
segregation between simple circuits and complex programs is not productive. In most of cases the digital
system grows toward higher orders where the autonomy of the structures allow an ecient segregation
between simple and complex.
8.8
Concluding about automata
A new step is made in this chapter in order to increase the autonomous behavior of digital
systems. The second loop looks justied by new useful behaviors.
Synchronous automata need non-transparent state registers The rst loop, closed for
gain the storing function, is applied carefully to obtain stable circuits. Tough restrictions can be
applied (even number of inverting levels on the loop) because of the functional simplicity. The
functional complexity of automata rejects any functional restrictions applied for the transfer
function associated to loop circuits. The unstable behavior is avoided using non-transparent
memories (registers) to store the state4 . Thus, the state switches synchronized by clock. The
output switches synchronously for delayed version of the implementation. The output is asynchronous for the immediate versions.
The second loop means the behaviors autonomy Using the rst loop to store the state
and the second to compute any transition function, a half-automaton is able to evolve in the
state space. The evolution depends by state and by input. The state dependence allows an
evolution even if the input is constant. Therefore, the automaton manifests its autonomy being
4
Asynchronous automata are possible but their design is restricted by to complex additional criteria. Therefore,
asynchronous design is avoided until stronger reason will force us to use it.
236
able to behave, evolving in the state space, under constant input. An automaton can be used
as pure generator of more or less complex sequence of binary conguration. the complexity
of the sequence depends by the complexity of the state transition function. A simple function
on the second loop determine a simple behavior (a simple increment circuit on the second loop
transforms a register in a counter which generate the simple sequence of numbers in the strict
increasing order).
Simple automata can have n states When we say n states, this means n can be very big,
it is not limited by our ability to dene the automaton, it is limited only by the possibility to
implement it using the accessible technologies. A simple automata can have n states because the
state register contains log n ip-ops, and its second loop contains a simple (constant dened)
circuit having the size in O(f (log n)). The simple automata can be big because they can be
specied easy, and they can be generated automatically using the current software tools.
Complex automata have only nite number of states Finite number of states means:
a number of states unrelated with the length (theoretically accepted as innite) of the input
sequence, i.e., the number of states is constant. The denition must describe the specic behavior
of the automaton in each state. Therefore, the denition is complex having the size (at least)
linearly related with the number of states. Complex automata must be small because they
suppose combinational loops closed through complex circuits having the description in the same
magnitude order with their size.
Control automata suggest the third loop Control automata evolve according to their
state and they take into account the signals received from the controlled system. Because the
controlled system receives commands from the same control automaton a third loop pregures.
Usually nite automata are used as control automata. Only the simple automata are involved
directly in processing data.
An important nal question: adding new loops the functional power of digital systems is
expanded or only helpful features are added? And, if indeed new helpful features occur, who is
helped by these additional features?
8.9
Problems
Problem 8.1 Draw the JK ip-op structure (see Figure 8.4) at the gate level. Analyze the
set-up time related to both edges of the clock.
Problem 8.2 Design a JK FF using a D ip-op by closing the appropriate combinational loop.
Compare the set-up time of this implementation with the set-up time of the version resulting in
the previous problem.
Problem 8.3 Design the sequential version for the circuit which computes the n-bit AND prexes. Follow the approach used to design the serial n-bit adder (see Figure 8.5).
Problem 8.4 Write the Verilog structural description for the universal 2-input, 2-state programmable automaton.
Problem 8.5 Draw at the gate level the universal 2-input, 2-state programmable automaton.
Problem 8.6 Use the universal 2-input, 2-state automaton to implement the following circuits:
8.9. PROBLEMS
237
n-bit serial adder

n-bit serial subtractor
n-bit serial comparator for equality
n-bit serial comparator for inequality
n-bit serial parity generator (returns 1 if odd)
Problem 8.7 Dene the synchronous n-bit counter as a simple n-bit Increment Automaton.
Problem 8.8 Design a Verilog tester for the resetable synchronous counter from Example 4.1.
Problem 8.9 Evaluate the size and the speed of the counter dened in Example 4.1.
Problem 8.10 Improve the speed of the counter designed in Example 4.1 designing an improved
version for the module and prefix.
Problem 8.11 Design a reversible counter dened as follows:
module smartest_counter
(
output [n-1:0]
input
[n-1:0]
input
input
input
input
input
endmodule
#(parameter
out
,
in
,
reset
,
load
,
down
,
count
,
clock
);
n = 16)
//
//
//
//
//
preset value
reset counter to zero
load counter with in
counts down if (count)
counts up or down
Problem 8.12 Simulate a 3-bit counter with dierent delay on its outputs. It is the case in
real world because the op-ops can not be identical and their load could be dierent. Use it as
input for a three input decoder implemented in two versions. One without delays and another
assigning delays to the inverters and the the gates used to implement the decoder. Visualize the
outputs of the decoder in both cases and interpret what you will nd.
Solution:
module dec_spyke;
reg
clock,
enable;
reg [2:0]
counter;
wire
out0, out1, out2, out3, out4, out5, out6, out7;
initial begin
clock = 0;
enable = 1;
counter = 0;
end
initial #400 $stop;
begin
counter[0] <= #3 ~counter[0];
238
if (counter[0])
if (&counter[1:0])

.out0
.out1
.out2
.out3
.out4
.out5
.out6
.out7
.in
.enable
,
,
,
,
,
,
,
,
,
);
end
dmux dmux(
(out0)
(out1)
(out2)
(out3)
(out4)
(out5)
(out6)
(out7)
(counter)
(enable)
initial $vw_dumpvars;
endmodule
module dmux(out0, out1, out2, out3, out4, out5, out6, out7, in, enable);
input
input
output
[2:0]
enable;
in;
out0, out1, out2, out3, out4, out5, out6, out7;
assign {out0, out1, out2, out3, out4, out5, out6, out7} = 1b1 << in;
/*
not
#1 not0(nin2, in[2]);
not
#1 not1(nin1, in[1]);
not
#1 not2(nin0, in[0]);
not
#1 not3(in2, nin2);
not
#1 not4(in1, nin1);
not
#1 not5(in0, nin0);
nand
nand
nand
nand
nand
nand
nand
nand
*/
endmodule
#2
#2
#2
#2
#2
#2
#2
#2
nand0(out0,
nand1(out1,
nand2(out2,
nand3(out3,
nand4(out4,
nand5(out5,
nand6(out6,
nand7(out7,
nin2,
nin2,
nin2,
nin2,
in2,
in2,
in2,
in2,
nin1,
nin1,
in1,
in1,
nin1,
nin1,
in1,
in1,
nin0,
in0,
nin0,
in0,
nin0,
in0,
nin0,
in0,
enable);
enable);
enable);
enable);
enable);
enable);
enable);
enable);
Problem 8.13 Justify the reason for which the LIFO circuit works properly without a reset
input, i.e., the initial state of the address counter does not matter.
Problem 8.14 How behaves simple stack .
Problem 8.15 Design a LIFO memory using a synchronous RAM (SRAM) instead of an asynchronous one as in the embodiment represented in Figure 11.1.
8.9. PROBLEMS
239
Problem 8.16 Some applications ask the access to the last two data stored into the LIFO. Call
them tos, for the last pushed data, and prev tos for the previously pushed data. Both accessed
data can be popped from stack. Double push is allowed. The accessed data can be rearranged
swapping their position. Both, tos and prev tos can be pushed again in the top of stack. Design
such a LIFO dened as follows:
module two_head_lifo(
output [31:0] tos

,
output [31:0] prev_tos
,
input
[31:0] in
,
input
[31:0] second_in
,
input
[2:0]
com
, // the operation
input
clock
);
// the semantics of com
parameter
nop
= 3b000, // no operation
swap
= 3b001, // swap the first two
pop
= 3b010, // pop tos
pop2
= 3b011, // pop tos and prev_tos
push
= 3b100, // push in as new tos
push2
= 3b101, // push in and second_in
push_tos
= 3110b, // push tos (double tos)
push_prev
= 3b111; // push prev_tos
endmodule
Problem 8.17 Write the Verilog description of the FIFO memory represented in Figure 8.10.
Problem 8.18 Redesign the FIFO memory represented in Figure 8.10 using a synchronous
RAM (SRAM) instead of the asynchronous RAM.
Problem 8.19 There are application asking for a warning signal before the FIFO memory is
full or empty. Sometimes full and empty come to late for the system using the FIFO memory.
For example, no more then 3 write operation are allowed, or no more than 7 read operation
are allowed are very useful in systems designed using pipeline techniques. The threshold for this
warning signals is good to be programmable. Design a 256 8-bit entries FIFO with warnings
activated using a programmable threshold. The interconnection of this design are:
module th_fifo(output
input
input
input
input
input
output
output
output
output
input
input
endmodule
[7:0]
[7:0]
[3:0]
[3:0]
out
,
in
,
write_th, //
read_th , //
write
,
read
,
w_warn , //
r_warn , //
full
,
empty
,
reset
,
clock
);
write threshold
read threshold
write warning
read warning
Problem 8.20 A synchronous FIFO memory is written or read using the same clock signal.
There are many applications which use a FIFO to interconnect two subsystems working with
dierent clock signals. In this cases the FIFO memory has an additional role: to cross from
the clock domain clock in into another clock domain, clock out. Design an asynchronous
FIFO using a synchronous RAM.
Problem 8.21 A serial memory implements the data structure of a x length circular list. The
rst location is accessed, for write or read operation, activating the input init. Each read or
write operation move the access point one position right. Design an 8-bit word serial memory
using a synchronous RAM as follows:
240
module serial_memory(
output
input
input
input
input
input
[7:0]
[7:0]

out
in
init
write
read
clock
,
,
,
,
,
);
endmodule
Problem 8.22 A list memory is a circuit in which a list can be constructed by insert, can be
accessed by read forward, read back, and modied by insert, delete. Design such a circuit
using two LIFOs.
Problem 8.23 Design a sequential multiplier using as combinational resources only an adder,
a multiplexors.
Problem 8.24 Write the behavioral and the structural Verilog description for the MAC circuit
represented in Figure 8.12. Test it using a special test module.
Problem 8.25 Redesign the MAC circuit represented in Figure 8.12 adding pipeline register(s)
to improve the execution time. Evaluate the resulting speed performance using the parameters
form Appendix E.
Problem 8.26 How many 2-bit code assignment for the half-automaton from Example 4.2 exist? Revisit the implementation of the half-automaton for four of them dierent from the one
already used. Compare the resulting circuits and try to explain the dierences.
Problem 8.27 Ad to the denition of the half-automaton from Example 4.2 the output circuits
for: (1) error, a bit indicating the detection of an incorrectly formed string, (2)ack, another
bit indicating the acknowledge of a well formed sting.
Problem 8.28 Multiplier control automaton can be dened testing more than one input variable
in some states. The number of states will be reduced and the behavior of the entire system will
change. Design this version of the multiply automaton and compare it with the circuit resulted
in Example 4.3. Reevaluate also the execution time for the multiply operation.
Problem 8.29 Revisit the system described in Example 4.3 and design the nite automaton for
multiply and accumulate (MACC) function. The system perform MACC until the input FIFO
is empty and end = 1.
Problem 8.30 Design the structure of TC in the CROM dened in 4.4.3 (see Figure 8.23).
Dene the codes associated to the four modes of transition (jmp, cjmp, init, inc) so as to
minimize the number of gates.
Problem 8.31 Design an easy to actualize Verilog description for the CROM unit represented
in Figure 8.23.
Problem 8.32 Generate the binary code for the ROM described using the symbolic denition
in Example 4.4.
Problem 8.33 Design a fast multiplier converting a sequential multiplier into a combinational
circuit.
8.10. PROJECTS
8.10
241
Projects
Project 8.1 Finalize Project 1.2 using the knowledge acquired about the combinational and
sequential structures in this chapter and in the previous two.
Project 8.2 The idea of simple FIFO presented in this chapter can be used to design an actual
block having the following additional features:
fully buered inputs and outputs
programmable thresholds for generating the empty and full signals
asynchronous clock signals for input and for output (the design must take into consideration
that the two clocks clockIn, clockOut are considered completely asynchronous)
the read or write commands are executed only if the it is possible (reads only if not-empty,
or writes only if not-full).
The module header is the following:
module asyncFIFO #(include "fifoParameters.v")
(
output reg [n-1:0] out
,
output reg
empty
,
output reg
full
,
input
[n-1:0] in
,
input
write
,
input
read
,
input
[m-1:0] inTh
, // input threshold
input
[m-1:0] outTh
, // output threshold
input
reset
,
input
clockIn ,
input
clockOut);
// ...
endmodule
The le fifoParameters.v has the content:
parameter
n = 16
m = 8
// word size
// number of levels
Project 8.3 Design a stack execution unit with a 32-bit ALU. The stack is 16-level depth
(stack0, stack1, ... stack15) with stack0 assigned as the top of stack. ALU has the
following functions:
add: addition
{stack0, stack1, stack2, ...} <= {(stack0 + stack1), stack2, stack3,...}
sub: subtract
{stack0, stack1, stack2, ...} <= {(stack0 - stack1), stack2, stack3,...}
inc: increment
{stack0, stack1, stack2, ...} <= {(stack0 + 1), stack1, stack2, ...}
dec: decrement
{stack0, stack1, stack2, ...} <= {(stack0 - 1), stack1, stack2, ...},
242
and: bitwise AND

{stack0, stack1, stack2, ...} <= {(stack0 & stack1), stack2, stack3,...}
or: bitwise OR
{stack0, stack1, stack2, ...} <= {(stack0 | stack1), stack2, stack3,...}
xor: bitwise XOR
{stack0, stack1, stack2, ...} <= {(stack0 stack1), stack2, stack3,...}
not: bitwise NOT
{stack0, stack1, stack2, ...} <= {(stack0), stack1, stack2, ...}
over:
{stack0, stack1, stack2, ...} <= {stack1, stack0, stack1, stack2, ...}
dup: duplicate
{stack0, stack1, stack2, ...} <= {stack0, stack0, stack1, stack2, ...}
rightShift: right shift one position (integer division)
{stack0, stack1, ...} <= {({1b0, stack0[31:1]}), stack1, ...}
arithShift: arithmetic right shift one position
{stack0, stack1, ...} <= {({stack0[31], stack0[31:1]}), stack1, ...}
get: push dataIn in top of stack
{stack0, stack1, stack2, ...} <= {dataIn, stack0, stack1, ...},
acc: accumulate dataIn
{stack0, stack1, stack2, ...} <= {(stack0 + dataIn), stack1, stack2, ...},
swp: swap the last two recordings in stack
{stack0, stack1, stack2, ...} <= {stack1, stack0, stack2, ...}
nop: no operation
{stack0, stack1, stack2, ...} <= {stack0, stack1, stack2, ...}.
All the register buered external connections are the following:
dataIn[31:0] : data input provided by the external subsystem
dataOut[31:0] : data output sent from the top of stack to the external subsystem
aluCom[3:0] : command code executed by the unit
carryIn : carry input
carryOut : carry output
eqFlag : is one if (stack0 == stack1)
ltFlag : is one if (stack0 stack1)
zeroFlag : is one if (stack0 == 0)
Project 8.4
Chapter 9
PROCESSORS:
Third order, 3-loop digital systems
the circuits having an autonomous behavior were introduced pointing on
how the increased autonomy adds new functional features in digital systems
the distinction between nite automata and uniform automata
the segregation mechanism used to reduce the complexity
In this chapter
the third order, three-loop systems are studied presenting
how a smart register can reduce the complexity of a nite automaton

how an additional memory helps for designing easy controllable systems
how the general processing functions can be performed loop connecting two appropriate automata forming a processor
In the next chapter

the fourth order, four-loop systems are suggested with emphasis on
the four types of loops used for generating dierent kind of computational structures
the strongest segregation which occurs between the simple circuits and the complex
programs
243
244
CHAPTER 9. PROCESSORS:
THIRD ORDER, 3-LOOP DIGITAL SYSTEMS
The soft overcomes the hard in the world

as a gentle rider controls a galloping horse.
Lao Tzu1
The third loop allows the softness of symbols to act
imposing the systems function.
In order to add more autonomy in digital systems the third loop must be closed. Thus,
new eects of the autonomy are used in order to reduce the complexity of the system. One of
them will allow us to reduce the apparent complexity of an automaton, another, to reduce the
complexity of the sequence of commands, but, the main form of manifesting of this third loop
will be the control process.
?
?
simpler (& smalleer)
Automaton
CLC
2-OS
a.
0-OS
?
1-OS
?
Automaton
2-OS
automaton
Automaton
c.
easier to control
Memory
2-OS
b.
Automaton
automaton
Processor
2-OS
Figure 9.1: The three types of 3-OS machines. a. The third loop is closed through a combinational circuit resulting less complex, sometimes smaller, nite automaton. b. The third loop is closed
through memories allowing a simplest control. c. The third loop is closed through another automaton
resulting the Processor: the most complex and powerful circuit.
The third loop can be closed in three manners, using the three types of circuits presented in
the previous chapters.
The rst 3-OS type system is a system having the third loop closed through a combinational
circuit, i.e., over an automaton or a network of automata the loop is closed through a 0-OS
(see Figure 9.1a).
The second type (see Figure 9.1b) has on the loop a memory circuit (1-OS).
The third type connects in a loop two automata (see Figure 9.1c). This last type is typical
for 3-OS, having the processor as the main component.
1
Quote from Tao Te King of Lao Tzu translated by Brian Browne Walker.
9.1. IMPLEMENTING FINITE AUTOMATA WITH INTELLIGENT REGISTERS
245
All these types of loops will be exemplied emphasizing a new and very important process
appearing at the level of the third order system: the segregation of the simple from the
complex in order to reduce the global (apparent) complexity.
9.1
Implementing nite automata with intelligent registers
The automaton function rises at the second order level, but this function can be better implemented using the facilities oered by the systems having a higher order. Thus, in this section
we resume a previous example using the feature oered by 3-OS. The main eect of these new
approaches: the ratio between the simple circuits and the complex circuits grows, without spectacular changes in the size of circuits. The main conclusion of this section: more autonomy
means less complexity.
9.1.1
Automata with JK registers
In the rst example we will substitute the state register with a more autonomous device: a
register made by JK ip-ops. The JK register is not a register, it is a network of parallel
connected simple automata. We shall prove that, using this more complicated ip-op, the
random part of the system will be reduced and in most of big sized cases the entire size of the
system could be also reduced. Thus, both the size and the complexity diminishes when we work
with autonomous (smart) components.
But lets start to disclose the promised magic method which, using ip-ops having two
inputs instead of one, oers a minimized solution for the combinational circuit performing the
loops function f . The main step is to oer a simple rule to substitute a D ip-op with a JK
ip-op in the structure of the automaton.
The JK ip-op has more autonomy than the D ip-op. The rst is an automaton and
the second is only a storage element used to delay. The JK ip-op has one more loop than
the D ip-op. Therefore, for switching from a state to another the input signals of a JK ipop accepts more ambiguity than the signal to the input of a D ip-op. The JK ip-op
transition can be commanded as follows:
for 0 0 transition, JK can be 00 or 01, i.e., JK=0 ( means dont care value)
for 0 1 transition, JK can be 11 or 10, i.e., JK=1
From the previous rule results the following rule:
for 0 A, JK=A
for 1 A, JK=A.
Using these rules, each transition diagram for Q+
i can be translated in two transition diagrams
for Ji and Ki . Results: twice numbers of equations. But surprisingly, the entire size of the
random circuit which computes the state transition will diminish.
Example 9.1 The half-automaton designed in Example 8.4 is reconsidered in order to be designed using JK ip-ops instead of D ip-ops. The transition map from Figure 8.15 (reproduces in Figure 9.2a) is translated in JK transition maps in Figure 9.2b. The resulting circuit
is represented in Figure 9.2c.
246
Q1
Q0
Q1
Q0
X0 1
0 X0
X0 X0 0
X0
Q+
, Q+
1
0
Q1 , Q0
a.
clock
Q1
Q0
Q0
X0
X0
Q1
R
JK-FF1
K1 = X0
J1 = 0
Q0
reset
Q1
-
R
JK-FF0
Q
Q1
X0
Q0
X0
Q1
J0 = Q1 X0 = (Q1 + X0 )
Q0
K0 = Q1 X0 = (Q1 + X0 )
c.
b.
Figure 9.2: Translating D transition diagrams in the corresponding JK transition

diagrams. The transition VK diagrams for the JK implementation of the nite half-automaton used
to recognize binary string belonging to the 1n 0m set of strings.
The size of the random circuit which computes the state transition function is now smaller
(from the size 8 for DFF to size 5 for JKFF). The increased autonomy of the now used
ip-ops allows a smaller eort for the same functionality.
Example 9.2 Lets revisit also Example 8.5. Applying the transformation rules results the VK diagrams from Figure 9.3 from which we extract:
Q1
Q0
Q1
11
01
10
00
Q0
Q1
-
Q0
J1
Q+
0
Q1
empty
full
K1
done
empty
Q+
1
Q1
-
Q1
Q0
empty
full
reference
Q0
Q0
Q1
-
Q0
done
-
empty
J0
K0
Figure 9.3: Translating D transition diagrams in the corresponding JK transition

diagrams. The transition VK diagrams for the JK implementation of the nite automaton used to
control MAC circuit (see Example 4.3).
J1 = Q0 empty
K1 = Q0 f ull
J0 = Q1 empty
K0 = Q1 done
If we compare with the previous D ip-op solution where the loop circuit is dened by
Q+
1 = Q1 Q0 + Q0 empty + Q1 f ull
247
Q+
0 = Q1 Q0 + Q0 done + Q1 empty
results a big reduction of complexity.
empty
full
done
write
Q
Q0
J
JKF-F
read
K
load
clear
Q
Q1
J
nop
JKF-F
Q
K
Half-automaton
clock
Figure 9.4: Finite automaton with smart JK register. The new implementation of FA
from Figure 8.17 using a JK register as a state register. The associated half-automaton is simpler (the
corresponding PLA is smaller).
In this new approach, using a smart register, a part of loopCLC from the automaton built
with a true register was segregated in the uniform structure of the JK register. Indeed, the
size of loopCLC decreases, but the size of each ip-op increases with 3 units (instead of an
inverter between S and R in D ip-op, there are two AN D2 in JK ip-op). Thus, in this new
variant the size of loopCLC decreases on the account of the size of the JK register.
This method acts as a mechanism that emphasizes more uniformities in the designing process
and allows to build for the same function a less complex and, only sometimes, a smaller circuit.
The eciency of this method increases with the complexity and the size of the system.
We can say that loopCLC of the rst versions has only an apparent complexity, because of
a certain quantity of order distributed, maybe hidden, among the eective random parts of
it. Because the order sunken in disorder can not be easy recognized we say that disorder
+ order means disorder. In this respect, the apparent complexity must be dened. The
apparent complexity of a circuit is reduced segregating the hidden order, until the circuit
remains really random. The rst step is done. The next step, in the following subsection.
What is the explanation for this segregation that implies the above presented minimization
in the random part of the system? Shortly: because the JK register is a smart register
having more autonomy than the true register built by D ip-ops. A D ip-op has only the
partial autonomy of staying in a certain state, instead of the JK ip-op that has the autonomy
to evolve in the state space. Indeed, for a D ip-op we must all the time say on the input
what will be the next state, 0 or 1, but for a JK ip-op we have the vague, almost evasive,
command J = K = 1 that says: switch in the other state, without indicating precisely, as
for D ip-op, the next state, because the JK knows, aided by the second loop, what is its
present state.
248
Because of the second loop, that informs the JK ip-op about its own state,
the expressions for Ji and Ki do not depend by Qi , rather than Q+
i that depends on Qi .
Thus, Ji and Ki are simplied. More autonomy means less control. For this reason the PLA
that closes the third loop over a JK register is smaller than a PLA that closes the second loop
over a true register.
9.1.2
Automata using counters as registers
Are there ways to extract more simplicity by segregation from the PLA associated to an automaton?
For some particular problems there is at least one more solution: to use a synchronous setable counter,
SCOU N Tn . The synchronous setable counter is a circuit that combines two functions, it is a register
(loaded on the command L) and in the same time it is a counter (counting up under the command U).
The load has priority before the count.
Instead of using few one-bit counters, i.e. JK ip-ops, one few-bit counter is used to store the state
and to simplify, if possible, the control of the state transition. The coding style used is the incremental
encoding (see E.4.3), which provides the possibility that some state transitions to be performed by
counting (increment).
Warning: using setable counters is not always an ecient solution!
Follows two example. One is extremely encouraging, and another is more realistic.
Example 9.3 The half-automaton associated to the codes assignment written in parenthesis in Figure
8.18 is implemented using an SCOU N Tn with n = 2. Because the states are codded using increment
encoding, the state transitions in the ow-chart can be interpreted as follows:
in the state q0 if empty = 0, then the state code is incremented, else it remains the same
in the state q1 if empty = 0, then the state code is incremented, else it remains the same
in the state q2 if done = 1, then the state code is incremented, else it remains the same
in the state q3 if f ull = 0, then the state code is incremented, else it remains the same
Half-automaton
empty
load
full
0
1
MUX w
I1
up
I0
reset
SCOU N T2
reseet
load
3
S0 S1
66
O1
Q1
O0
clock
Q0
Figure 9.5: Finite half-automaton implemented with a setable counter. The last implementation of the half-automaton associated with FA from Figure 8.17 (with the function dened in Figure
8.18 where the states coded in parenthesis). A synchronous two-bit counter is used as state register. The
simple four-input MUX commands the counter.
Results the very simple (not necessarily very small) implementation represented in Figure 9.5, where
a 4-input multiplexer selects according to the state the way the counter switches: by increment (up = 1)
or by loading (load = 1).
Comparing with the half-automaton part in the circuit represented in Figure 9.4, the version with
counter is simpler, eventually smaller. But, the most important eect is the reducing complexity.
Example 9.4 This example is also a remake. The half-automaton of the automaton which controls the
operation macc in Example 4.6 will be implemented using a presetable counter as register. See Figure
249
empty
done
empty
end
full
-0
-1
-2
-3
-4
-5
-6
-7
-8
-9
- 10
- 11
- 12
- 13
- 14
- 15
M U X4
U
L
I3 I2 I1 I0
SCOU N T4
R
Q3 Q2 Q1 Q0
clock
reset
S3 S2 S1 S0
6666
empty
Figure 9.6: Finite half-automaton for controlling the function macc. The function was
previously implemented using a CROM in Example 4.6.
8.25 for the state encoding. The idea is to have in the ow-chart as many as possible transitions by
incrementing.
Building the solution starts from a SCOU N T4 and a M U X4 connected as in Figure 9.6. The multiplexer selects the counters operation (load or up-increment) in each state according to the ow-chart
description. For example in the state 0000 the transition is made by counting if empty = 0, else the state
remains the same. Therefore, the multiplexer selects the value of empty to the input U of the counter.
The main idea is that the loading inputs I3 , I2 , I1 and I0 must have correct values only if in the
current state the transition can be made by loading a certain value in the counter. Thus, in the denition
of the logical functions associated with these inputs we have many dont cares. Results the circuit
represented in Figure 9.6. The random part of the circuit is designed using the transition diagrams from
Figure 9.7.
The resulting structure has a minimized random part. We assumed even the risk of increasing the
recursive dened part of the circuit in order to reduce the random part of it.
Now, the autonomous device that allows reducing the randomness is the counter used as state register.
An adequate state assignment implies many transitions by incrementing the state code. Thus, the basic
function of the counter is many times involved in the state transition. Therefore, the second loop of the
system, the simple dened loop that counts, is frequently used by the third loop, the random loop.
The simple command UP, on the third loop, is like a complex macro executed by the second loop using
simple circuits. This hierarchy of autonomies simplies the system, because at the higher level the loop
uses simple commands for complex actions. Let us remember:
the loop over a true register (in 2-OS) uses the simple commands for the simplest actions: load 0
in D ip-op and load 1 in D ip-op
the loop over a JK register (in 3-OS) uses beside the previous commands the following: no op
(remain in the same state!) and switch (switch in the complementary state!)
the loop over a SCOU N Tn substitutes the command switch with the same simple expressed, but
more powerful, command increment.
250
q3
q2
- - - -
- - - -
1001
- - - -
- - - -
- - - -
0111
0001
001
- - - -
0011
- - - -
0000
- - - -
0010
0000
empty
q1
+
+
q3
, . . . q0
q3
q3
q2
q2
q0
+
q3
q1
+
q2
q0
q3
-
1
q1
q2
q0
+
q1
q3
-
1
1
q2
q0
q0
1
q1
+
q0
q1
Figure 9.7: Transition diagrams for the presetable counter used as state register.
The complex (random) part of the automaton is represented by the loop closed to the load input of the
presetable counter.
The architecture used on the third loop is more powerful than the two previous. Therefore, the eort
of this loop to implement the same function is smaller, having the simpler expression: a reduced random
circuit.
The segregation process is more deep, thus we imply in the designing process more simple, recursive
dened, circuits. The apparent complexity of the previous solution is reduced towards, maybe on, the
actual complexity. The complexity of the simple part is a little increased in order to pay the price for a
strong minimization of the random part of the system. The quantitative aspects of our small example are
not very signicant. Only the design of the actual large systems oers a meaningful example concerning
the quantitative eects.
9.2
Loops closed through memories
Because the storage elements do not perform logical or arithmetical functions - they only store
- a loop closed through the 1-OS seems to be unuseful or at least strange. But a selective
memorizing action is used sometimes to optimize the computational process! The key is to
know what can be useful in the next steps.
The previous two examples of the third order systems belongs to the subclass having a
combinational loop. The function performed remains the same, only the eciency is aected.
In this section, because automata having the loop closed through a memory is presented, we
expect the occurrence of some supplementary eects.
In order to exemplify how a trough memory loop works an Arithmetic & Logic Automaton
ALA will be used (see Figure 9.8a). This circuit performs logic and arithmetic functions
on data stored in its own state register called accumulator ACC , used as left operand and
on the data received on its input in, used as right operand. A rst version uses a control
automaton to send commands to ALA, receiving back one ag: crout.
A second version of the system contains an additional D ip-op used to store the value of
the CRout signal, in each clock cycle when it is enabled (E = 1), in order to be applied on the
CRin input of ALU. The control automaton is now substituted with a command automaton,
used only to issue commands, without receiving back any ag.
Follow two example of using this ALA, one without an additional loop and another with the
third loop closed trough a simple D ip-op.
9.2. LOOPS CLOSED THROUGH MEMORIES
251
out
in
6
The second
loop

CRin
Right
ALU
CRout
ACC
clock
Left
<func>
<carry>
crout
Arithmetic & Logic Automaton
CONTROL
AUTOMATON
a.
out
in
6
The second
loop

CRin
Right
ALU
CRout
ACC
clock
Left
<func>
<carry>
COMMAND
AUTOMATON
6
1
Arithmetic & Logic Automaton
-D
Q
D-FF
The third loop

clock
R E
66<enable>
<reset>
b.
Figure 9.8: The third loop closed over an arithmetic and logic automaton. a. The basic
structure: a simple automaton (its loop is closed through a simple combinational circuit: ALU) working
under the supervision of a control automaton. b. The improved version, with an additional 1-bit state
register to store the carry signal. The control is simpler if the third loop tells back to the arithmetic
automaton the value of the carry signal in the previous cycle.
Version 1: the controlled Arithmetic & Logic Automaton

In the rst case ALA is controlled (see Figure 9.8a) using the following denition for the
undened elds of < microinstruction> specied in 8.4.3:
<command> ::= <func> <carry>;
<func> ::= and | or | xor | add | sub | inc | shl | right;
<test> ::= crout | -;
Let be the sequence of commands that controls the increment of a double-length number:
bubu
cucu
inc cjmp crout bubu // ACC = in + 1

right jmp cucu
// ACC = in
inc
// ACC = in + 1
...
The rst increment command is followed by dierent operarion according to the value of
crout. If crout = 1 then the next command is an increment, else the next command is a
simple load of the upper bits of the double-length operand into the accumulator. The control
automaton decides according to the result of the rst increment and behaves accordingly.
Version 2: the commanded Arithmetic & Logic Automaton
The second version of Arithmetic & Logic Automaton is a 3-OS because of the additional loop
closed through the D ip-op. The role of this new loop is to reduce, to simplify and to speed up
the routine that performs the same operation. Now the microinstruction is actualized dierently:
252
<command> ::= <func>;

<func> ::= and | or | xor | add | sub | inc | addcr | shl;
<test> ::= - ;
The eld <test> is not used, and the control automaton can be substituted by a command
automaton. The eld <func> is codded so as one of its bit is 1 for all arithmetic functions. This
bit is used to enable the switch of D-FF. A new function is added: addcr. The instruction add
the value of carry to the input in.
The resulting dierence in how the system works is that in each clock cycle CRin is given by
the content of the D ip-op. Thus, the sequence of commands that performs the same action
becomes:
inc
// ACC = in + 1
addcr // ACC = in + Q
In the two previous use of the arithmetic and logic automaton the execution time remains
the same, but the expression used to command the structure in the second version is shorter
and simpler. The explanation for this eect is the improved autonomy of the second version of
the ALA. The rst version was a 2-OS but the second version is a 3-OS. A signicant part of
the random content of the ROM from CROM can be removed by this simple new loop. Again,
more autonomy means less control. A small circuit added as a new loop can save much
from the random part of the structure. Therefore, this kind of loop acts as a segregation method.
Specic for this type of loop is that adding simple circuits we save random, i.e., complex,
structured symbolic structures. The circuits grow by simple physical structure and the complex
symbolic structures are partially avoided.
In the rst version the sequence of commands are executed by the automaton all the time
in the same manner. In the second version, a simpler sequence of commands are executed
dierent, according to the processed data that impose dierent values in the carry op-op.
This dierent execution can be thought as an interpretation.
In fact, the execution is substituted by the interpretation, so as the apparent complexity of the
symbolic structure is reduced based on the additional autonomy due to the third structural loop.
The autonomy introduced by the new loop through the D ip-op allowed the interpretation of
the commands received from the sequencer, according to the value of CR.
The third loop allows the simplest form of interpretation, we will call it static interpretation.
The fourth loop allows a dynamic interpretation, as we will see in the next chapter.
9.3
Loop coupled automata: the second turning point
This last step in building 3-OS stresses specically on the maximal segregation between the
simple physical structure and the complex symbolic structures. The third loop allows
us to make a deeper segregation between simple and complex.
We are in the point where the process of segregation between simple and complex physical
structures ends. The physical structures reach the stage from which the evolution can be done
only coupled with the symbolic structures. From this point a machine means: circuits that
execute or interpret bit congurations structured under restrictions imposed by the formal
languages used to describe the functionality to be performed.
9.3.1
# Sequential divider
9.3.2
Push-down automata
The rst example of loop coupled automata uses a nite automaton and a functional automaton: the stack
(LIFO memory). A nite complex structure is interconnected with an innite but simple structure.
9.3. LOOP COUPLED AUTOMATA: THE SECOND TURNING POINT
253
The simple and the complex are thus perfectly segregated. This approach has the role of minimizing
the size of the random part. More, this loop aects the magnitude order of the randomness, instead of
the previous examples (Arithmetic & Logic Automaton) in which the size of randomness is reduced only
by a constant. The proposed structure is a well known system having many theoretical and practical
applications: the push-down automaton.
X
?
FA
DIN
LIFO
DOUT
{P U SH, P OP, }
Figure 9.9: The push-down automaton (PDA). A nite (random) automaton loop-coupled with
an innite stack (a simple automaton) is an enhanced toll for dealing with formal languages.
Denition 9.1 The push-down automaton, PDA, (see Figure 9.9) built by a nite automaton loop
connected with a push-down stack (LIFO), is dened by the six-tuple:
P DA = (X X , Y Y X, Q, f, g, z0 )
where:
X : is the nite alphabet of the machine; the input string is in X
X : is the nite alphabet of the stack, X = X {z0 }
Y : is the nite output set of the machine
Y : is the set of commands issued by the nite automaton toward LIFO, {P U SH, P OP, }
Q : is the nite set of the automaton states (i.e., |Q| = h(max l(s)), where s X is received on the
input of the machine)
f : is the state transition function of the machine
f : X X Q Q X Y
(i.e., depending on the received symbol, by the value of the top of stack (TOS) and by the automatons state, the automaton switches in a new state, a new value can be sent to the stack and the
stack receives a new command (PUSH, POP or NOP))
g : is the output transition function of the automaton - g : Q Y
z0 : is the initial value of TOS.
Example 9.5 The problem to be solved is designing a machine that recognizes strings having the form
$x&y$, where $, & X and x, y X , X being a nite alphabet and y is the antisymmetric version of x.
The solution is to use a PDA with f and g described by the ow-chart given in Figure 9.10. Results
a ve state, initial (in q0 ) automaton, each state having the following meaning and role:
q0 : is the initial state in which the machine is waiting for the rst $
q1 : in this state the received symbols are pushed into the stack, excepting & that switches the automaton
in the next state
q2 : in this state, each received symbol is compared with T OS, that is poped on, while the received symbol
is not $; when the input is $ and T OS = z0 the automaton switches in q3 , else, if the received
symbols do not correspond with the successive value of the T OS or the nal value of TOS diers
from z0 , the automaton switches in q4
254
q0
1
X =$
q1
0
X =&
PUSH X
q2
1
X =$
X = T OS
T OS = Z0
POP
q3
q4
OK
WRONG
Figure 9.10: Dening the behavior of a PDA. The algorithm detecting the antisymmetrical
sequences of symbols.
q3 : if the automaton is in this state the received string was recognized as a well formed string
q4 : if the automaton is in this state the received string was wrong.
The reader can try to solve the problem using only an automaton. For a given X set, especially for
a small set, the solution is possible and small, but the LOOP PLA of the resulting automaton will be a
circuit with the size and the form depending by the dimension and by the content of the set X. If only
one symbol is added or at least is changed, then the entire design process must be restarted from scratch.
The automaton imposes a solution in which the simple, recursive part of the solution is mixed up with
the random part, thus all the system has a very large apparent complexity. The automaton must store
in the state space what PDA stores in stack. You imagine how huge become the state set in a such crazy
solution. Both, the size and the complexity of the solution become unacceptable.
The solution with PDA, just presented, does not depend by the content and by the dimension of the
set X. In this solution the simple is well segregated from the complex. The simple part is the innite
stack and the complex part is a small, ve-state nite automaton.
9.3.3
The elementary processor
The most representative circuit in the class of 3-OS is the processor. The processor is maybe the
most important digital circuit because of its exibility to compute any computable function.
Denition 9.2 The processor, P, is a circuit realized loop connecting a functional automaton
with a nite (control) automaton.
The function of a processor P is specied by the sequences of commands stored in the
loopCLC of the nite automaton used for control. (In a microprogrammed processor each sequence represents a microprogram. A microprogram consists in a sequence of microinstructions
255
each containing the commands executed by the functional automaton and elds that allow to
select the next microinstruction.)
In order to understand the main mechanisms involved by the third loop closed in digital
systems we will present initially only how an elementary processor works.
Denition 9.3 The elementary processor, EP, is a processor executing only one control sequence, i.e., the associated nite automaton is a strict initial automaton.
An EP performs only one function. It is a structure having a x, nonprogrammable function.
The two parts of an EP are very dierent. One, the control automaton, is a complex structure,
while another, the functional automaton, is a simple circuit assembled from few recursively dened circuits (registers, ALU, le registers, multiplexors, and the kind). This strong segregation
between the simple part and the complex part of a circuit is the key idea on which the eciency
of this approach is based.
Even on this basic level the main aspect of computation manifest. It is about control and
execution. The nite automaton performs the control, while the functional automaton executes
the logic or arithmetic operations on data. The control depends on the function to be computed
(the 2nd level loop at the level of the automaton) and on the actual data received by the system
(the 3rd level loop at the system level).
Example 9.6 Lets revisit Example 5.2 in order to implement the function interpol using an
EP. The organization of the EP intepolEP is presented in Figure 9.11.
reset
asndAck
send
DFF
DFF
DFF
DFF
The functional automaton RALU

inR
in
8xEMUX
get
6
???

Regiser File
ALU
out
outR
-getAck
FA
6

2nd
Loop
3rd Loop

2nd
Loop
zero
interpolEP
Figure 9.11: The elementary processor interpolEP.

The functional automaton consists of a register le, an Arithmetic and Logic Unit and a 2way multiplexer. Such a simple functional automaton can be called RALU (Registers & ALU).
In each clock cycle two operands are read from the register le, they are operated in ALU, and
the result is stored back at destination register in the register le. The multiplexor is used to
256
load the register le with data. The loop closed from the ALUs output to the MUXs input is a
2nd level loop, because each register in the le register contains a rst level loop.
The system has fully buered connections. Synchronization signals (send, get, sendAck,
getAck) are connected through DFFs (one-bit registers) and data through two 8-bit registers:
inR and outR.
The control of the system is performed by the nite automaton FA. It is initialized by the
reset signal, and evolve by testing three independent 1-bit signals: send (the sending external
subsystem provides a new input byte), get (the receiving external subsystem is getting the data
provided by the EP), zero (means the current output of ALU has the value 0). The last 1-bit
signal closes the third loop of the system. The transition function is described in the following
lines:
STATE
FUNCTION
TEST
EXT. SIGNAL
NEXT STATE
waitSend
reg0 <= inReg,
sendAck,
test
reg1 <= reg1,
waitGet
outReg <= reg1,
if (send)
else
if (zero)
else
if (get)
else
move1
move0
add
divide
reg2
reg1
reg1
reg1
next
next
next
next
next
next
next
next
next
next
<=
<=
<=
<=
getAck,
reg1,
reg0,
reg0 + reg2,
reg1 >> 1,
=
=
=
=
=
=
=
=
=
=
test;
waitSend;
add;
waitGet;
move1;
waitGet;
move0;
waitSend;
divide;
waitGet;
The outputs of the automaton provide the command for the acknowledge signals for the
external subsystems, and the internal command signals for RALU and output register outR.
Example 9.7 The EP structure is exemplied framed inside the simple system represented in Figure
9.12, where:
reset
read
inFIFO
empty
stack com
in2
in1
?
LIFO
?
mux
Elementary Processor
right
left
alu
?

Control
Automaton
6
6
acc reg
out
write outFIFO
full
the third loop
Figure 9.12: An example of elementary processor (EP). The third loop is closed between a
simple execution automaton (alu & acc reg) and a complex control automaton used to generate the
sequence of operations to be performed by alu and to control the data ow between EP and the associated
memory resources: LIFO, inFIFO, outFIFO.
inFIFO : provides the input data for EP when read = 1 if empty = 0
257
outFIFO : receives the output data generated by EP when write = 1 if full = 0

LIFO : stores intermediary data for EP if push = 1 and send back the last sent data if pop
Elementary Processor : is one of the simplest embodiment of an EP containing:
Control Automaton : a strict initial control automaton (see CROM from Figure 8.23)
alu : an Arithmeetic & Logic Unit
acc reg : an accumulator register, used as state register for Arithmetic & Logic Automaton which
is a functional automaton
mux : is the multiplexer for select the left operand from inFIFO or from LIFO.
The control automaton is a one function CROM that commands the functional automaton, receiving from
it only the carry output, cr, of the adder embedded in ALU.
The description of PE must be supplemented with the associated microprogramming language, as
follows:
<microinstruction> ::= <label> <command> <mod> <test> <next>;
<label> ::= <any string having maximum 6 symbols>;
<command> ::= <func> <inout>;
<mod> ::= jmp | cjmp | - ;
<test> ::= zero | notzero | cr | notcr | empty | nempty | full | nfull;
<next> ::= <label>;
<func> ::= left | add | half0 | half1 | - ;
<inout> ::= read | write | push | pop ;
where:
notcr: inverted cr
nempty: inverted empty
nfull: inverted full
left: acc_reg <= left
add: acc_reg <= left + acc_reg
half0: acc_reg <= {0, acc_reg[n-1:1]}
half1: acc_reg <= {1, acc_reg[n-1:1]}
left = read ? out(inFIFO) : out(LIFO)
and by default command are:
inc for <mode>
right: acc_reg <= acc_reg
The only microprogram executed by the previous described EP receives a string of numbers and generates another string of numbers representing the mean values of the successive two received numbers.
The numbers are positive integers. Using the previous dened microprogramming language results the
following microprogram:
microprogram mean;
bubu
read,
cucu
cjmp,
read,
half0;
out
write,
jmp,
one
half1,
endmicroprogram
cjmp,
empty,
add,
empty,
cucu;
cjmp,
bubu,
left;
cr,
one;
cjmp,
bubu;
jmp,
full,
out;
out;
258
On the rst line PE waits for non-empty inFIFO; when empty becomes inactive the last left command
puts in the accumulator register the correct value. The second microinstruction PE waits for the second
number, when the number arrives the microprogram goes to the next line. The third line adds the content
of the register with the just read number from inFIFO. If cr = 1, the next microinstruction will be one,
else the next will be the following microinstruction. The fourth and the last microinstructions performs
the right shift setting the most signicant bit on 0, i.e., the division for nishing to compute the mean
between the two received numbers. The line out send out the result when full = 0. The jump to bubu
restart again the procedure, and so on unending. The line one performs a right shift setting the most
signicant bit on 1.
The entire physical structure of EP is not relevant for the actual function it performs. The
function is dened only by the loopCLC of the nite automaton. The control performed by the
nite automaton combines the simple functional facilities of the functional automaton that is
a simple logic-arithmetic automaton. The randomness is now concentrated in the structure of
loopCLC which is the single complex structure in the system. If loopCLC is implemented as a
ROM, then its internal structure is a symbolic one. As we said at the beginning of this section,
at the level of 3-OS the complexity is segregated in the symbolic domain. The complexity is
driven away from the circuits being lodged inside the symbolic structures supported by ROM.
The complexity can not be avoided, it can be only transferred in the more controllable space of
the symbolic structures.
9.3.4
Executing instructions vs. interpreting instructions
A processor is a machine which composes & loops functions performed by elementary

processors. Let us call them elementary computations or, simply, instructions. But now it
is not about composing circuits. The big dierence from a physical composition or a physical
looping, already discussed, is that now the composition and looping are done in the symbolic
domain.
As we know, an EP computes a function of variables received from an external sub-system
(in the previous example from inFIFO), and sends the result to an external sub-system (in the
previous example to outFIFO). Besides input variables a processor receives also functions. The
results are stored sometimes internally or in specic external resources (for example a LIFO
memory), and only at the end of a complex computation a result or a partial result is outputed.
The symbolic composition is performed applying the computation g on the results of computations hm , . . . h0 . Lets call now g, hi , or other similar simple computations, instructions.
The symbolic looping means to apply the same string of instructions to the same variables
as many time as needed.
Any processor is characterized by its instruction set architecture (ISA). As we mentioned,
an instruction is equivalent with an elementary computation performed by an EP, and its code
is used to specify:
the operation to be performed (<op code>)
sometimes an immediate operand, i.e., a value known at the moment the computation is
dened (<value>),
therefore, in the simplest cases instruction ::= <op code> <value>
A program is a sequence of instructions allowing to compose and to loop more or less complex
computations.
There are two ways to perform an instruction:
to execute it: to transcode op code in one or many elementary operations executed in one
clock cycle
259
to interpret it: to expand op code is a sequence of operations performed in many clock

cycles.
Accordingly, two kind of processors are dened:
executing processors
interpreting processors.
elementary functions
w
storage elements
VARIABLES
composing & looping
storage elements
PROCESSOR
PROGRAM
COUNTER
DATA
&
PROGRAMS
ALU
NEXT PC
EXECUTION UNIT
or
INTERPRETATION UNIT
decoding or -composing & -looping
Figure 9.13: The processor (P) in its environment. P works loop connected with an external
memory containing data and programs. Inside P elementary function, applied to a small set of very
accessible variables, are composed in linear or looped sequences. The instructions read from the external
memory are executed in one (constant) clock cycle(s) or they are interpreted by a sequence of elementary
functions.
In Figure 9.13 the processing module is framed in a typical context. The data to be computed
and the instructions to be used perform the computation are stored in a RAM module (see in
Figure 9.13 DATA & PROGRAMS). PROCESSOR is a separate unit used to compose and to
loop strings of instructions. The internal resources of a processor consists, usually, in:
a block to perform elementary computations, containing:
an ALU performing at least simple arithmetic operations and the basic logic operations
a memory support for storing the most used variable
the block used to transform each instruction in an executable internal mico-code, with two
possible versions:
a simple decoder allowing the execution of each instruction in one clock cycle
a microprogrammed unit used to expand each instruction in a microprogram, thus
allowing the interpretation of each instruction in a sequence of actions
the block used to compose and to loop by:
reading the successive instructions organized as a program (by incrementing the PROGRAM COUNTER register) from the external memory devices, here grouped under
the name DATA & PROGRAMS
260
jumping in the program space (by adding signed value to PROGRAM COUNTER)
In this section we introduce only the executing processors (in Chapter 11 the interpreting
processor will be used to exemplify how the functional information works).
Informally, the processor architecture consists in two main components:
the internal organization of the processor at the top level used to specify:
how are interconnected the top levels blocks of processor
the micro-architecture: the set of operations performed by each top level block
the instruction set architecture (ISA) associated to the top level internal organization.
Von Neumann architecture / Harvard architecture
When the instruction must be executed (in one clock cycle) two distinct memories are mandatory,
one for programs and one for data, because in each cycle a new instruction must be fetched and
sometimes data must be exchanged between the external memory and the processor. But,
when an instructions is interpreted in many clock cycles it is possible to have only one external
memory, because, if a data transfer is needed, then it can be performed adding one or few extra
cycles to the process of interpretation.
DATA
PROGRAM
DATA & PROGRAM
MEMORY
MEMORY
MEMORY
6
?
6
?
6
?
PROCESSOR
a.
PROCESSOR
b.
Figure 9.14: The two main computer architectures. a. Harvard Architecture: data and
programs are stored in two dierent memories. b. Von Neumann Architecture: both data and programs
are stored in the same memory.
Two kind of computer architecture where imposed from the beginning of the history of
computers:
Harvard architecture with two external memories, one for data and another for programs (see Figure 10.6a)
von Neumann architecture with only one external memory used for storing both data
and programs (see Figure 10.6b).
The preferred embodiment for an executing processor is a Hardvare architecture, and the
preferred embodiment for an interpreting processor is a von Neumann architecture. For technological reasons in the rst few decades of development of computing the von Neumann architecture was more taken into account. Now the technology being freed by a lot of restriction, we
pay attention to both kind of architectures.
In the next two subsections both, executing processor (commercially called Reduced Instruction Set Computer RISC processors) and interpreting processor (commercially called
Complex Instruction Set Computer CISC processors) are exemplied by implementing
very simple versions.
9.3.5
261
An executing processor
The executing processor is simpler than an interpreting processor. The complexity of computation moves almost completely from the physical structure of the processor into the programs
executed by the processor, because a RISC processor has an organization containing mainly
simple, recursively dened circuits.
The organization
The Harvard architecture of a RISC executing machine (see Figure 10.6a) determine the internal
structure of the processor to have mechanisms allowing in each clock cycle cu address both, the
program memory and the data memory. Thus, the RALU-type functional automaton, directly
interfaced with the data memory, is loop-connected with a control automaton designed to fetch
in each clock cycle a new instruction from the program memory. The control automaton does
not know the function to be performed, as it does for the elementary processor, rather he
knows how to fetch the function from an external storage support, the program memory2 .
Program Memory
addr
Data Memory
instruction
dataOut
dataIn
addr
toyRISC processor
jmpAddr
value
Decode
R

- MUX

?
PC
pc + 1
2nd
Loop
?
Next PC
3rd Loop
RALU
File Register
ALU
2nd
Loop
leftOp
rightOp
Control
Figure 9.15: The organization of toyRISC processor.

The organization of the simple executive processortoyRISC is given in Figure 9.15, where
the RALU subsystem is connected with the Control subsystem, thus closing a 3rd loop.
Control section is simple functional automaton whose state, stored in the register called Program Counter (PC), is used to compute in each clock cycle the address from where the next
instruction is fetched. There are two modes to compute the next address: incrementing, with
1 or signed number the current address. The next address can be set, independently from the
current value of PC, using a value fetched from an internal register or a value generated by
the currently executed instruction. The way the address is computed can be determined by the
value, 0 or dierent from 0, of a selected register. More, the current pc+1 can be stored in an
internal register when the control of the program call a new function and a return is needed.
For all the previously described behaviors the combinational circuit NextPC is designed. It
contains outCLC and loopCLC of the automaton whose state is stored in PC.
2
The relation between an elementary processor and a processor is somehow similar with the relation between
a Turing Machine and an Universal Turing Machine.
262
RALU section accepts data coming form data memory, from the currently executed instruction, or from the Control automaton, thus closing the 3dr loop.
Both, the Control automaton and the RALU automaton are simple, recursively dened
automata. The computational complexity is completely moved in the code stored inside the
program memory.
The instruction set architecture
The architecture of toyRISC processor is described in Figure 9.16.
/**********************************************************************************
INSTRUCTION SET ARCHITECTURE
reg
[15:0] pc; // program counter
reg
[31:0] programMemory[0:65535];
reg
[31:0] dataMemory[0:n-1];
instruction[31:0] = {opCode[5:0], dest[4:0], left[4:0], value[15:0]} |
{opCode[5:0], dest[4:0], left[4:0], right[4:0], noUse[10:0]};
**********************************************************************************/
parameter
// CONTROL
nop
= 6b00_0000,
// no operation: pc = pc+1;
zjpm
= 6b00_0010,
// cond jump: pc = (rf[left] = 0) ? pc + value : pc+1
nzjmp = 6b00_0011,
// !cond jump: pc = !(rf[left] = 0) ? pc + value : pc+1
rjmp
= 6b00_0100,
// relative jump: pc = pc + value;
ret
= 6b00_0101,
// return from subroutine: pc = rf[left][15:0];
ajmp
= 6b00_0110,
// absolute jump: pc = value;
call
= 6b00_0111,
// subroutine call: pc = value; rf[dest] = pc+1;
// ARITHMETIC & LOGIC
inc
= 6b11_0000,
// rf[dest] = rf[left] + 1; pc = pc+1;
dec
= 6b11_0001,
// rf[dest] = rf[left] - 1; pc = pc+1;
add
= 6b11_0010,
// rf[dest] = rf[left] + rf[right]; pc = pc+1;
sub
= 6b11_0011,
// rf[dest] = rf[left] - rf[right]; pc = pc+1;
inccr = 6b11_0100,
// rf[dest] = (rf[left] + 1)[32]; pc = pc+1;
deccr = 6b11_0101,
// rf[dest] = (rf[left] - 1)[32]; pc = pc+1;
addcr = 6b11_0110,
// rf[dest] = (rf[left] + rf[right])[32]; pc = pc+1;
subcr = 6b11_0111,
// rf[dest] = (rf[left] - rf[right])[32]; pc = pc+1;
lsh
= 6b11_1000,
// rf[dest] = rf[left] >> 1; pc = pc+1;
ash
= 6b11_1001,
// rf[dest] = {rf[left][31], rf[left][31:1]}; pc = pc+1;
move
= 6b11_1010,
// rf[dest] = rf[left]; pc = pc+1;
swap
= 6b11_1011,
// rf[dest] = {rf[left][15:0], rf[left][31:16]} pc = pc+1;
neg
= 6b11_1100,
// rf[dest] = ~rf[left]; pc = pc+1;
bwand = 6b11_1101,
// rf[dest] = rf[left] & rf[right]; pc = pc+1;
bwor
= 6b11_1110,
// rf[dest] = rf[left] | rf[right]; pc = pc+1;
bwxor = 6b11_1111,
// rf[dest] = rf[left] ^ rf[right]; pc = pc+1;
// MEMORY
read
= 6b10_0000,
// read from dataMemory[rf[right]]; pc = pc+1;
load
= 6b10_0111,
// rf[dest] = dataOut; pc = pc+1;
store = 6b10_1000,
// dataMemory[rf[right]] = rf[left]; pc = pc+1;
val
= 6b01_0111;
// rf[dest] = {{16*{value[15]}}, value}; pc = pc+1;
Figure 9.16: The architecture of toyRISC processor.

The 32-bit instruction has two forms: (1) control form, and (2) arithmetic-logic & memory
form. The rst eld, opCode, is used to determine what is the form of the current instruction.
Each instruction is executed in one clock cycle.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
module toyRISC(output
input
output
output
input
output
input
input
reg
wire
wire
wire
wire
wire
[15:0]
[31:0]
[31:0]
[31:0]
[31:0]
[15:0]
[15:0]
[31:0]
[31:0]
[31:0]
[31:0]
pc
aluOut
leftOp
rightOp
regFileIn
incPc
instrAddr
instruction
dataAddr
dataOut
dataIn
we
reset
clock
, //
, //
, //
, //
, //
, //
,
);
263
program memory address

instruction from program memory
data memory address
data send to data memory
data received from data memory
write enable for data memory
;
;
;
;
;
;
assign we = instruction[31:26] == 6b101000 ;

assign dataAddr = rightOp
assign dataOut = leftOp
;
;
always @(posedge clock) if (reset) pc <=0; else pc <= instrAddr;

nextPc nextPc(
.addr
.incPc
.pc
.jmpVal
.leftOp
.enable
(instrAddr
(incPc
(pc
(instruction[15:0]
(leftOp
(~|instruction[31:30]
),
),
),
),
),
));
fileReg fileReg(.leftOut
(leftOp
.rightOut
(rightOp
.in
(regFileIn
.leftAddr
(instruction[15:11]
.rightAddr (instruction[20:16]
.destAddr
(instruction[25:21]
.writeEnable(&instruction[31:30] | &instruction[28:26]
),
),
),
),
),
),
));
mux4_32 mux(.out(regFileIn
),
.in0({16b0, incPc}
),
.in1({{16{instruction[15]}}, instruction[15:0]} ),
.in2(dataIn
),
.in3(aluOut
),
.sel(instruction[31:30]
));
alu alu(.out
(aluOut
.leftIn (leftOp
.rightIn(rightOp
.func
(instruction[29:26]
),
),
),
));
endmodule
Figure 9.17: The top module of toyRISC processor. The four module of the design are all
simple circuits with no meaningful random glue logic used to interconnect them.
264
Implementing toyRISC
The structure of toyRISC will be implemented as part of a bigger project realized for a SoC,
where the program memory and data memory are on the same chip, tightly coupled with our
design. Therefore, the connections of the module are not very rigorously buered.
The Figure 9.17 describe the structure of the top level of our design, which is composed by
simple modules. Because the glue logic is minimal (see lines 17, 29 and 37), the overall structure
could be considered also a very simple one.
The time performance
The longest combinational path in a system using our toyRISC, which imposes the minimum
clock period, is:
Tclock = tclock
to instruction
+ tlef tAddr
to lef tOp
+ tthroughALU + tthroughM U X + tf ileRegSU
Because the system is not buered the clock frequency depends also by the time behavior of
the system directly connected with toyRISC. In this case tclock to instruction the access time
of the program memory, related to the active edge of the clock is an extra-system parameter
limiting the speed of our design. The internal propagation time to be considered are: the read
time from the le register (tlef tAddr to lef tOp or trightAddr to rightOp ), the maximum propagation
time through ALU (dominated by the time for an 32-bit arithmetic operation), the propagation
time through a 4-way 32-bit multiplexer, and the set-up time on the le registers data inputs.
The way from the output of the le register through Next PC circuit is shorter because it
contains a 16-bit adder, comparing with the 32-bit one of the ALU.
9.3.6
An interpreting processor
The interpreting processor are known also as processors having a Complex Instruction Set Computer
(CISC) architecture, or simply as CISC Processors. The interpreting approach allows us to design complex
instructions which are transformed at the hardware level in a sequence of operations. Lets remember
that an executing (RISC) processor has almost all instructions implemented in one clock cycle. It is not
decided what style of designing an architecture is the best. Depending on the application sometimes a
RISC approach is mode ecient, sometimes a CISC approach is preferred.
The organization
Our CISC Processor is a machine characterized by using a register le to store the internal (the most
frequently used) variables. The top level view of this version of processor is represented in Figure 9.18.
It contains the following blocks:
REGISTER & ALU RALU 32 32-bit registers organized in a register le, and an ALU; the
registers are used also for control purposes (program counter, return address, stack pointer in the
external memory, ...)
INPUT & OUTPUT BUFFER REGISTERS used to provide full synchronous connections with the
external world, minimizing tin reg , treg out , maximizing fmax , and avoiding tin out (see subsection
1.1.5); the registers are the following:
COM REG : sends out the 2-bit read or write command for the external data & program memory
ADDR REG : sends out the 32-bit address for the external data & program memory
OUT REG : sends out the 32-bit data for the external memory
DATA REG : receives back, with one clock cycle delay related to the command loaded in COM
REG, 32-bit data from the external data & program memory
INST REG : receives back, with one clock cycle delay related to the command loaded in COM
REG, 32-bit instruction from the external data & program memory
265
in
data
mem addr
instruction
REG
- enINST
inst
DATA REG
clock
?

addr
ADDR

W
inst[15:0]

dest addr
left addr
right addr
result
write enable
REG
REGISTER FILE
inst[31:11]
?
CONTROL
right out
left out
AUTOMATON
(CROM)
OUT
out
data out
REG
value
data in
1
0
LEFT MUX
????
left sel

0
1
2
3
RIGHT MUX
6
reset
right sel
command

com
COM
mem com
REG
?
right
left
ALU
alu com
flags
alu out
RALU
I
the second loop
the third loop
Figure 9.18: An interpreting processor. The organization is simpler because only one external
memory is used.
CONTROL AUTOMATON used to control the fetch and the interpretation of the instructions
stored in the external memory; it is an initial automaton initialized, for each new instruction, by
the operation code (inst[31:26] received from INST REG)
The instruction of our CISC Processor has two formats. The rst format is:
{
opcode[5:0]
dest_addr[4:0]
left_addr[4:0]
right_addr[4:0]
rel_addr[10:0]
= instr[31:0];
,
,
,
,
}
//
//
//
//
//
operation code
selects the destination
selects the left operand
selects the right operand
small signed jump for program address
The relative address allows a positive or a negative jump of 1023 instructions in the program space. It is
sucient for almost all jumps in a program. If not, special absolute jump instruction can solve this very
rare cases.
The second format is used when the right operand is a constant value generated at the compiling
time in the instruction body. It is:
{
opcode[5:0]
dest_addr[4:0]
,
,
266
left_addr[4:0]
value[15:0]
= instr[31:0];
,
}
// signed integer
When the instruction is fetched from the external memory it is memorized in INST REG because its
content will be used in dierent stages of the interpretation, as follows:
inst[31:26] = opcode[5:0] to initialize CONTROL AUTOMATON in the state from which
ows the sequence of commands used to interpret the current instruction
inst[29:26] = opcode[3:0] to command the function performed by ALU in the step associated
to perform the main operation associated with the current instruction (for example, if the instruction is add 12, 3, 7, then the bits opcode[3:0] are used to command the ALU to do the addition
of registers 3 and 7 in the appropriate step of interpretation)
inst[25:11] = {dest addr, left addr, right addr} is used to address the REGISTER FILE
unit when the main operation associated with the current instruction is performed
inst[15:0] = value is selected to form the right operand when an instruction operating with
immediate value is interpreted
inst[10:0] = rel addr is used in jump instructions, in the appropriate clock cycle, to compute
the next program address.
The REGISTER FILE unit contains 32 32-bit registers. In each clock cycle, any ordered pair of
registers can be selected as operands, and the result can be stored back in any of them. They have the
following use:
r0, r1, ...
r29 are general purpose registers;
r31 is used as Program Counter (PC);

r30 is used to store the Return Address (RA) when the call instruction is interpreted (no embedded
calls are allowed for this simple processor3 ).
CONTROL AUTOMATON has the structure presented in Figure 9.19. In the fetch cycle init =
1 allows the automaton to jump into the state codded by opcode, from which a sequence of operations
ows with init = 0, ignoring the initialization input. This is the simplest way to associate for each
instruction the interpreting sequence of elementary operation.
The output of CONTROL AUTOMATON commands all the top level blocks of our CISC Processor
using the following elds:
{en_inst
,
write_enable
,
dest_addr[4:0] ,
left_addr[4:0] ,
alu_com[3:0]
,
right_addr[4:0],
left_sel
,
right_sel[1:0] ,
mem_com[1:0]
}
= command
//
//
//
//
//
//
//
//
//
write enable for the instruction register

write back enable for the register file
destination address in file register
left operand address in file register
alu functions
right operand address in file register
left operand selection
right operand selection
memory command
The elds dest addr, left addr, right addr, alu com are sometimes selected from INST REG
(see ADDR MUX and FUNC MUX in Figure 9.19) and sometimes their value is generated by CONTROL
AUTOMATON according to the operation to be executed in the current clock cycle. The other command
elds are generated by CONTROL AUTOMATON in each clock cycle.
3
If embedded calls are needed, then this register contains the stack pointer into a stack organized in the
external memory. We are not interested in adding the feature of embedded calls, because in this digital system
lessons we intend to keep the examples small and simple.
inst[31:11]
267
inst[31:26]
inst[25:11]
inst[29:26]
1
0
INIT MUX
init
next state
reset
STATE REG
clock
state
?
?
1
0
ADDR MUX
0
1
FUNC MUX
RANDOM CLC

6
{dest addr, left addr, right addr}
flag
alu com
{en instr, write enable, left sel, right sel, mem com}
Figure 9.19: The control automaton for our CISC Processor. It is a more compact version
of CROM (see Figure 8.23). Instead of a CLC used for the complex part of executing processor, for an
interpreting processor a sequential machine is used to solve the problem of complexity.
CONTROL AUTOMATON receives back from ALU only one ag: the least signicant bit of ALU,
alu out[0]; thus closing the third loop4 .
In each clock cycle the content of two registers can be operated in ALU and the result stored in a
third register.
The left operand can be sometimes data in if left sel = 1. It must be addressed two clock cycles
before use, because the external memory is supposed to be a synchronous one, and the input register
introduces another one cycle delay. The sequence generated by CONTROL AUTOMATON takes care
by this synchronization.
The right operand can be sometimes value = instr reg[15:0] if right sel = 2b1x. If right sel
= 2b01 the right operand is the 11-bit signed integer rel addr = instr reg[10:0]
The external memory is addressed with a delay of one clock cycle using the value of left out. We
are not very happy about this additional delay, but this is the price for a robust design. What we loose
in number of clock cycles used to perform some instructions is, at least partially, recuperated by the
possibility to increase the frequency of the system clock.
Data to be written in the external memory is loaded into OUT REG from the right output of FILE
REG. It is synchronous with the address.
The command for the external memory is also delayed one cycle by the synchronization register COM
REG. It is generated by CONTROL AUTOMATON.
Data and instructions are received back from the external memory with two clock cycle delay, one
because of we have an external synchronous memory, and another because of the input re-synchronization
done by DATA REG and INST REG.
The structural Verilog description of the top level of our CISC Processor is in Figure 9.20.
The second loop is closed once in the big & simple automaton RALU, and another in the complex nite
automaton CONTROL AUTOMATON. The rst loop is closed in each ip-op used to build the registers.
268
module cisc_processor(input
clock
,
input
reset
,
output
reg [31:0] addr_reg,
// memory address
output
reg [1:0]
com_reg ,
// memory command
output
reg [31:0] out_reg ,
// data output
input
[31:0] in
); // data/inst input
// INTERNAL CONNECTIONS
wire
[25:0] command;
wire
flag;
wire
[31:0] alu_out, left, right, left_out, right_out;
// INPUT & OUTPUT BUFFER REGISTERS
reg [31:0] data_reg, inst_reg;
if (command[25]) inst_reg <= in ;
data_reg <= in
;
addr_reg <= left_out
;
out_reg <= right_out
;
com_reg <= command[1:0]
;
end
// CONTROL AUTOMATON
control_automaton control_automaton(.clock (clock
),
.reset (reset
),
.inst
(inst_reg[31:11]),
.command(command
),
.flag
(alu_out[0]
));
// REGISTER FILE
register_file register_file(.left_out
(left_out
),
.right_out
(right_out
),
.result
(alu_out
),
.left_addr
(command[18:14] ),
.right_addr
(command[9:5]
),
.dest_addr
(command[23:19] ),
.write_enable
(command[24]
),
.clock
(clock
));
// MULTIPLEXERS
mux2 left_mux( .out(left
),
.in0(left_out
),
.in1(data_reg
),
.sel(command[4]));
mux4 right_mux( .out(right
),
.in0(right_out
),
.in1({{21{inst_reg[10]}}, inst_reg[10:0]}
),
.in2({16b0, inst_reg[15:0]}
),
.in3({inst_reg[15:0], 16b0}
),
.sel(command[3:2]
));
// ARITHMETIC & LOGIC UNIT
cisc_alu alu(
.alu_out(alu_out
),
.left
(left
),
.right (right
),
.alu_com(command[13:10] ));
endmodule
Figure 9.20: The top module of our CISC Processor.
269
Microarchitecture
The complex part of our CISC Processor is located in the block called CONTROL AUTOMATON. More
precisely, the only complex circuit in this design is the loop of the automaton called RANDOM CLC
(see Figure 9.19). The Verilog module describing CONTROL AUTOMATON is represented in Figure
9.21.
The micro-architecture denes all the elds used to command the simple parts of this processor.
Some of them are used inside the control automaton module, while others command the top modules
of the processor.
The inside used elds command are the following:
init : allows the jump of the automaton into the initial state associated with each instruction when
init = new seq
addr sel : the three 5-bit addresses for FILE REGISTER are considered only if the eld addr sel takes
the value from inst, else three special combinations of addresses are generated by the control
automaton
func sel : the eld alu com is considered only if the eld func sel takes the value from out, else the
code opcode[3:0] selects the ALUs function
The rest of elds command the function performed in each clock cycle by the top modules of our
CISC Processor. They are:
en inst : enables the load of data received from the external memory only when it represents the next
instruction to be interpreted
write enable : enables write back into FILE REGISTER the result from the output of ALU
alu com : is a 4-bit eld used to command ALUs function for the specic purpose of the interpretation
process (it is considered only if func sel = from aut)
left sel : is the selection code for LEFT MUX (see Figure 9.18)
right sel : is the selection code for RIGHT MUX (see Figure 9.18)
mem com : generated the commands for the external memory containing both data and programs.
The micro-architecture (see Figure 9.22) is subject of possible changes during the denition of the
transition function of CONTROL AUTOMATON.
Instruction set architecture (ISA)

There is a big exibility in dening the ISA for a CISC machine, because we accepted to interpret
each instruction using a sequence of micro-operations. The control automaton is used as sequencer for
implementing instructions beyond what can be simply envisaged inspecting the organization of our simple
CISC processor.
An executing (RISC) processor displays its architecture in its organization, because the control is very
simple (the decoder is a combinational circuit used to trans-code only). The complexity of the control
of an interpreting processor hides the architecture in the complex denition of the control automaton
(which can have a strong generative power).
In Figure 9.23 is sketched a possible instruction set for our CISC processor. There are at least the
following classes of instructions:
Arithmetic & Logic Instructions: the destination register takes the value resulted from operating
any two registers (unary operations, such as increment, are also allowed)
Data Move Instructions: data exchange between the external memory and the le register are
performed
Control Instructions: the ow of instruction is controlled according to the x or data dependent
patterns
...
We limit our discussion to few and small classes of instructions because our goal is to oer only a structural
image about what an interpretative processor is. An exhaustive approach is an architectural one, which
is far beyond out intention in these lessons about digital systems, not about computational systems.
270
module control_automaton(
input
input
input
output
input
[20:0]
[25:0]
[3:0]

clock
reset
inst
command
flags
,
,
,
,
);
include "micro_architecture.v"
include "instruction_set_architecture.v"
// THE STRUCTURE OF inst
wire
[5:0]
opcode ;
//
wire
[4:0]
dest
,
//
left_op ,
//
right_op;
//
assign {opcode, dest, left_op,
operation code
selects destination register
selects left operand register
selects right operand register
right_op} = inst;
// THE STRUCTURE OF command

reg
en_inst
; // enable load a new instruction in inst_reg
reg
write_enable; // writes the output of alu at dest_addr
reg
[4:0]
dest_addr
; // selects the destination register
reg
[4:0]
left_addr
; // selects the left operand in file register
reg
[3:0]
alu_com
; // selects the operation performed by the alu
reg
[4:0]
right_addr ; // selects the right operand in file register
reg
left_sel
; // selects the source of the left operand
reg
[1:0]
right_sel
; // selects the source of the right operand
reg
[1:0]
mem_com
; // generates the command for memory
assign command = {en_inst, write_enable, dest_addr, left_addr, alu_com,
right_addr, left_sel, right_sel, mem_com};
// THE STATE REGISTER
reg
[5:0]
state_reg
; // the state register
reg
[5:0]
next_state ; // a "register" used as variable
always @(posedge clock) if (reset) state_reg <= 0
;
else
state_reg <= next_state ;
include "the_control_automatons_loop.v"
endmodule
Figure 9.21: Verilog code for control automaton.

Implementing ISA
Implementing a certain Instruction Set Architecture means to dene the transition functions of the control
automaton:
the output transition function, in our case to specify for each state the value of the command code
(see Figure 9.21)
the state transition function, which species the value of next state
The content of the le the control automatons loop.v contains the description of the combinational
circuit associated to the control automaton. It generates both the 26-bit command code and the 6-bit
next state code. The following Verilog code is the most compact way to explain how the control
automaton works. Please read the next always as the single way to explain rigorously how out CISC
machine works.
// THE CONTROL AUTOMATONS LOOP
always @(state_reg or opcode or dest or left_op or right_op or flag)
begin
en_inst
= 1bx
;

// MICRO-ARCHITECTURE
// en_inst
parameter
no_load
load_inst
// write_enable
parameter
no_write
write_back
// alu_func
parameter
alu_left
alu_right
alu_inc
alu_dec
alu_add
alu_sub
alu_shl
alu_half
alu_zero
alu_equal
alu_less
alu_carry
alu_borrow
alu_and
alu_or
alu_xor
// left_sel
parameter
left_out
from_mem
// right_sel
parameter
right_out
jmp_addr
low_value
high_value
// mem_com
parameter
mem_nop
read
write
= 1b0, // disable instruction register

= 1b1; // enable instruction register
= 1b0,
= 1b1; // write back the current ALU output
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
4b0000,
4b0001,
4b0010,
4b0011,
4b0100,
4b0101,
4b0110,
4b0111,
4b1000,
4b1001,
4b1010,
4b1011,
4b1100,
4b1101,
4b1110,
4b1111,
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
left
right
left + 1
left - 1
left + right
left - right
{1b0, left[31:1]}
{left[31], left[31:1]}
{31b0, (left == 0)}
{31b0, (left == right)}
{31b0, (left < right)}
{31b0, add[32]}
{31b0, sub[32]}
left & right
left | right
left ^ right
= 1b0, // left out of the reg file as left op

= 1b1; // data from memory as left op
=
=
=
=
2b00,
2b01,
2b10,
2b11;
//
//
//
//
right
right
right
right
out of the reg file as right op

op = {{22{inst[10]}}, inst[9:0]}
op = {{16{inst[15]}}, inst[15:0]}
op = {inst[15:0], 16b0}
= 2b00,
= 2b10, // read from memory
= 2b11; // write to memory
Figure 9.22: The micro-architecture of our CISC Processor.
write_enable = 1bx
;
dest_addr
= 5bxxxxx ;
left_addr
= 5bxxxxx ;
alu_com
= 4bxxxx ;
right_addr
= 5bxxxxx ;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= 2bxx
;
next_state
= 6bxxxxxx;
// INITIALIZE THE PROCESSOR
if (state_reg == 6b00_0000)
// pc = 0
begin
en_inst
= no_load
write_enable = write_back
dest_addr
= 5b11111
left_addr
= 5b11111
;
;
;
;
271
272
// INSTRUCTION SET ARCHITECTURE (only samples)

// arithmetic & logic instructions & pc = pc + 1
parameter
move
= 6b10_0000, // dest_reg = left_out
inc
= 6b10_0010, // dest_reg = left_out + 1
dec
= 6b10_0011, // dest_reg = left_out - 1
add
= 6b10_0100, // dest_reg = left_out + right_out
sub
= 6b10_0101, // dest_reg = left_out - right_out
bwxor
= 6b10_1111; // dest_reg = left_out ^ right_out
// ...
// data move instructions & pc = pc + 1
parameter
read
= 6b01_0000, // dest_reg = mem(left_out)
rdinc
= 6b01_0001, // dest_reg = mem(left_out + value)
write
= 6b01_1000, // mem(left_out) = right_out
wrinc
= 6b01_1001; // mem(left_out + value) = right_out
// ...
// control instructions
parameter
nop
= 6b11_0000, // pc = pc + 1
jmp
= 6b11_0001, // pc = pc + value
call
= 6b11_0010, // pc = value, ra = pc + 1
ret
= 6b11_0011, // pc = ra
jzero
= 6b11_0100, // if (left_out = 0) pc = pc + value;
// else pc = pc + 1
jnzero = 6b11_0101; // if (left_out != 0) pc = pc + value;
// else pc = pc + 1
// ...
Figure 9.23: The instruction set architecture of our CISC Processor. The partial denition
of the le instruction set architecture.v included in the conttrol automaton.v le.
alu_com
right_addr
left_sel
right_sel
mem_com
next_state
=
=
=
=
=
=
alu_xor
;
5b11111
;
left_out
;
right_out
;
mem_nop
;
state_reg + 1;
end
// INSTRUCTION FETCH
// rquest for a new instruction & increment pc
begin
en_inst
= no_load
;
;
dest_addr
= 5b11111
;
left_addr
= 5b11111
;
alu_com
= alu_inc
;
right_addr
= 5bxxxxx
;
left_sel
= left_out
;
right_sel
= 2bxx
;
mem_com
= mem_read
;
next_state
= state_reg + 1;
end

// wait for memory to read doing nothing (synchronous memory)
begin
en_inst
= no_load
;
write_enable = no_write
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= state_reg + 1;
end
// load the new instruction in instr_reg
begin
en_inst
= load_inst
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= state_reg + 1;
end
// initialize the control automaton
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= opcode[5:0] ;
end
// EXECUTE THE ONE CYCLE FUNCTIONAL INSTRUCTIONS
if (state_reg[5:4] == 2b10)
// dest = left_op OPERATION right_op
begin
en_inst
= no_load
;
;
dest_addr
= dest
;
left_addr
= left_op
;
alu_com
= opcode[3:0] ;
right_addr
= right_op
;
left_sel
= left_out
;
right_sel
= right_out
;
mem_com
= mem_nop
;
next_state
= 6b00_0001
;
end
273
274
// EXECUTE MEMORY READ INSTRUCTIONS

// read from left_reg in dest_reg
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= left_op
;
alu_com
= alu_left
;
right_addr
= 5bxxxxx
;
left_sel
= left_out
;
right_sel
= 2bxx
;
mem_com
= mem_read
;
next_state
= 6b01_0010
;
end
// read from left_reg + <value> in dest_reg
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= left_op
;
alu_com
= alu_add
;
right_addr
= 5bxxxxx
;
left_sel
= left_out
;
right_sel
= low_value
;
mem_com
= mem_read
;
next_state
= 6b01_0010
;
end
// wait for memory to read doing nothing
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= state_reg + 1;
end
// the data from memory is loaded in data_reg
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= state_reg + 1;

end
// data_reg is loaded in dest_reg & go to fetch
begin
en_inst
= no_load
;
;
dest_addr
= dest
;
left_addr
= 5bxxxxx
;
alu_com
= alu_left
;
right_addr
= 5bxxxxx
;
left_sel
= from_mem
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= 6b00_0001
;
end
// EXECUTE MEMORY WRITE INSTRUCTIONS
// write right_op to left_op & go to fetch
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= left_op
;
alu_com
= alu_left
;
right_addr
= right_op
;
left_sel
= left_out
;
right_sel
= 2bxx
;
mem_com
= mem_write
;
next_state
= 6b00_0001
;
end
// write right_op to left_op + <value> & go to fetch
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= left_op
;
alu_com
= alu_add
;
right_addr
= right_op
;
left_sel
= left_out
;
right_sel
= low_value
;
mem_com
= mem_write
;
next_state
= 6b00_0001
;
end
// CONTROL INSTRUCTIONS
// no operation & go to fetch
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
275
276
mem_com
next_state
= mem_nop
= 6b00_0001
end
// jump to (pc + <value>) & go to fetch
begin
en_inst
= no_load
dest_addr
= 5b11111
left_addr
= 5b11111
alu_com
= alu_add
right_addr
= 5bxxxxx
left_sel
= left_out
right_sel
= low_value
mem_com
= mem_nop
next_state
= 6b00_0001
end
// call: first step: ra = pc + 1
begin
en_inst
= no_load
dest_addr
= 5b11110
left_addr
= 5b11111
alu_com
= alu_left
right_addr
= 5bxxxxx
left_sel
= left_out
right_sel
= 2bxx
mem_com
= mem_nop
next_state
= 6b11_0110;
end
if (state_reg == 8b0011_0110)
// call: second step: pc = value
begin
en_inst
= no_load
dest_addr
= 5b11111
left_addr
= 5bxxxxx
alu_com
= alu_right
right_addr
= 5bxxxxx
left_sel
= 1bx
right_sel
= jmp_addr
mem_com
= mem_nop
next_state
= 6b00_0001
end
// ret: pc = ra
begin
en_inst
= no_load
dest_addr
= 5b11111
left_addr
= 5b11110
alu_com
= alu_left
right_addr
= 5bxxxxx
left_sel
= left_out
right_sel
= 2bxx
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

mem_com
next_state
= mem_nop
= 6b00_0001
;
;
end
if ((state_reg == 6b11_0100) && flag)
// jzero: if (left_out = 0) pc = pc + value;
begin
en_inst
= no_load
;
;
dest_addr
= 5b11111
;
left_addr
= 5b11111
;
alu_com
= alu_add
;
right_addr
= 5bxxxxx
;
left_sel
= left_out
;
right_sel
= low_value
;
mem_com
= mem_nop
;
next_state
= 6b00_0001
;
end
if ((state_reg == 6b11_0100) && ~flag)
// jzero: if (left_out = 1) pc = pc + 1;
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
mem_com
= mem_nop
;
next_state
= 6b00_0001
;
end
if ((state_reg == 6b11_0100) && ~flag)
// jnzero: if (left_out = 1) pc = pc + value;
begin
en_inst
= no_load
;
;
dest_addr
= 5b11111
;
left_addr
= 5b11111
;
alu_com
= alu_add
;
right_addr
= 5bxxxxx
;
left_sel
= left_out
;
right_sel
= low_value
;
mem_com
= mem_nop
;
next_state
= 6b00_0001
;
end
if ((state_reg == 6b11_0100) && flag)
// jnzero: if (left_out = 0) pc = pc + 1;
begin
en_inst
= no_load
;
;
dest_addr
= 5bxxxxx
;
left_addr
= 5bxxxxx
;
alu_com
= 4bxxxx
;
right_addr
= 5bxxxxx
;
left_sel
= 1bx
;
right_sel
= 2bxx
;
277
278
mem_com
next_state
= mem_nop
= 6b00_0001
;
;
end
end
The automaton described by the previous code has 36 states for the 25 instructions implemented
(see Figure 9.23). More instructions can added if new state are described in the previous always.
Obviously, the most complex part of the processor is this combinational circuit associated to the control
automaton.
Time performance
The representation from Figure 9.24 is used to evaluate the time restrictions imposed by our CISC
processor.
from the external memory
clock
?
INPUT REGISTERS
?

CONTROL
RALU
-
AUTOMATON
OUTPUT REGISTERS
?
to the external memory
Figure 9.24: The simple block diagram of our CISC processor. The fully buered solution
imposed for designing this interpretative processor minimizes the depth of signal path entering and
emerging in/from the circuit, and avoid a going through combinational path.
The full registered external connections of the circuit allows us to provide the smallest possible values
for minimum input arrival time before clock, tin reg , maximum output required time after clock, treg out ,
and no path for maximum combinational path delay, tin out . The maximum clock frequency is fully
determined by the internal structure of the processor, by the path on the loop closed inside RALU or
between RALU and CONTROL AUTOMATON. The actual time characterization is:
tin
reg
treg
= tsu the set-up time for the input registers
out
= treg the propagation time for the output registers
Tmin = max(tRALU
tRALU
tprocessor
loop
loop , tprocessor loop ),

loop
= tstate
= tstate
reg
reg
+ taut
where:
+ taut
out clc
out clc
+ treg
+ treg
f ile
f ile
+ tmux + talu + treg
+ tmux + talu
f lag
+ taut
f ile su
in clc
+ tstate
reg su
9.4. THE ASSEMBLY LANGUAGE: THE LOWEST PROGRAMMING LEVEL
279
This well packed version of a simple processor is very well characterized as time behavior. The
price for this is the increasing number of clock cycle used for executing an instruction. The eect of
the increased number of clock cycles is sometimes compensated by the possibility to use a higher clock
frequency. But, all the time the modularity is the main benet.
Concluding about our CISC processor

A CISC processor is more complex than a stack processor because for each instruction the operands must
be selected from the le register. The architecture is more exible, but the loop closed in RALU is longer
than the loop closed in SALU.
A CISC approach allows more complex operations performed during an instruction because it is
interpreted, not simply executed in one clock cycle.
Interpretation allows a single memory for both data and programs with all the resulting advantages
and disadvantages.
An interpreting processor contains a simple automaton RALU and a complex one Control
Automaton because its complex behavior.
Both, Stack Processor and CISC Processor are only simple exercises designed for presenting the
circuit aspects of the closing of hte third loop. The real and complex architectural aspects are minimally
presented because this text book is about circuits not abut computation.
9.4
The assembly language: the lowest programming level
The instruction set represent the machine language: the lowest programming level in a computation
machine. The programming is very dicult at this level because of the concreteness of the process.
Too many details must be known by the programmer. The main improvement added by a higher level
language is the level of abstraction used to present the computational resources. Writing a program
in machine language we must have in mind a lot of physical details of the machine. Therefore, a real
application must be developed in a higher level language.
The machine language can be used only for some very critical section of the algorithms. The automatic
translation done by a compiler from a high level language into the machine language is some times
unsatisfactory for high performance application. Only in this cases small part of the code must be
generated manually using the machine language.
9.5
Concluding about the third loop
The third loop is closed through simple automata avoiding the fast increasing of the
complexity in digital circuit domain. It allows the autonomy of the control mechanism.
Intelligent registers ask less structural control maintaining the complexity of a nite
automaton at the smallest possible level. Intelligent, loop driven circuits can be controlled using
smaller complex circuits.
The loop through a storage element ask less symbolic control at the microarchitectural level. Less symbols are used to determine the same behavior because the local
loop through a memory element generates additional information about the recent history.
Looping through a memory circuit allows a more complex understanding because
the controlled circuits knows more about its behavior in the previous clock cycle. The circuit is
somehow conscious about what it did before, thus being more responsible for the operation
it performs now.
280
Looping through an automaton allows any eective computation. Using the theory
of computation (see chapter Recursive Functions & Loops in this book) can be proved that any
eective computation can be done using a three loop digital system. More than three loops are
needed only for improving the eciency of the computational structures.
The third loop allows the symbolic functional control using the arbitrary meaning
associated to the binary codes embodied in instructions or micro-instructions. Both, the coding
and the decoding process being controlled at the design level, the binary symbols act actualizing
the potential structure of a programmable machine.
Real processors use circuit level parallelism discussed in the rst chapter of this book.
They are: data parallelism, time parallelism and speculative parallelism. How all these kind of
parallelism are used is a computer architecture topic, beyond the goal of these lecture notes.
9.6
Problems
Problem 9.1 Interrupt automaton with asynchronous input.

Problem 9.2 Solving the second degree equations with an elementary processor.
Problem 9.3 Compute y if x, m and n is given with an elementary processor..
Problem 9.4 Modify the unending loop of the processor to avoid spending time in testing if a
new instruction is in inFIFO when it is there.
Problem 9.5 Dene an instruction set for the processor described in this chapter using its
microarchitecture.
Problem 9.6 Is it closed another loop in our Stack Processor connecting tos to the input of
DECODE unit?
Problem 9.7 Our CISC Processor: how must be codded the instruction set to avoid FUNC
MUX?
9.7
Projects
Project 9.1 Design a specialized elementary processor for rasterization function.

Project 9.2 Design a system integrating in a parallel computational structure 8 rasterization
processors designed in the previous project.
Project 9.3 Design a oating point arithmetic coprocessor.
Project 9.4 Design the RISC processor dened by the following Verilog behavioral description:
module risc_processor(
);
endmodule
Project 9.5 Design a version of Stack Processor modifying SALU as follows: move MUX4 to
the output of ALU and the input of STACK.
Chapter 10
COMPUTING MACHINES:
4loop digital systems
was introduced the main digital system - the processor - and we discussed how works the
third loop in a digital system emphasizing
eects on the size of digital circuits
eects on the complexity of digital systems
how the apparent complexity can be reduced to the actual complexity in a digital
system
In this chapter
a very short introduction in the systems having more than three internal loops is provided,
talking abut
how are dened the basic computational structures: microcontrollers, computers,
stack machines, co-processors
how the classication in orders starts to become obsolete with the fourth order systems
the concept of embedded computation
In the next chapter
some futuristic systems are described as N-th order systems having the following features:
they can behave as self-organizing systems
they are cellular systems easy to be expanded in very large and simple powerful
computational systems
281
282
CHAPTER 10. COMPUTING MACHINES:
4LOOP DIGITAL SYSTEMS
Software is getting slower more rapidly than hardware becomes faster.

Wirths law1
To compensate the eects of the bad behavior of software guys, besides the job done by the Moore law a
lot of architectural work must be added.
The last examples of the previous chapter emphasized a process that appears as a turning
point in 3-OS: the function of the system becomes lesser and lesser dependent on the physical
structure and the function is more and more assumed by a symbolic structure (the program
or the microprogram). The physical structure (the circuit) remains simple, rather than the
symbolic structure, stored in program memory of in a ROM, that establishes the functional
complexity. The fourth loop creates the condition for a total functional dependence on the
symbolic structure. By the rule, at this level an universal circuit - the processor - executes (in
RISC machines) or interprets (in CISC machines) symbolic structures stored in an additional
device: the program memory.
10.1
Types of fourth order systems
There are four main types of fourth order systems (see Figure 10.1) depending on the order of
the system through which the loop is closed:
1. P & ROM is a 4-OS with loop closed through a 0-OS - in Figure 10.1a the combinational
circuit is a ROM containing only the programs executed or interpreted by the processor
2. P & RAM is a 4-OS with loop closed through a 1-OS - is the computer, the most
representative structure in this order, having on the loop a RAM (see Figure 10.1b) that
stores both data and programs
3. P & LIFO is a 4-OS with loop closed through a 2-OS - in Figure 10.1c the automaton is
represented by a push-down stack containing, by the rule, data (or sequences in which the
distinction between data and programs does not make sense, as in the Lisp programming
language, for example)
4. P & CO-P is a 4-OS with loop closed through a 3-OS - in Figure 10.1d COPROCESSOR
is also a processor but a specialized one executing eciently critical functions in the system
(in most of cases the coprocessor is a oating point arithmetic processor).
The representative system in the class of P & ROM is the microcontroller the most successful circuit in 4-OS. The microcontroller is a best seller circuit realized as a one-chip computer.
The core of a microcontroller is a processor executing/interpreting the programs stored in a
ROM.
The representative structure in the class of P & RAM is the computer. More precisely, the
structure Processor - Channel - Memory represents the physical support for the well known von
Neumann architecture. Almost all present-day computers are based on this architecture.
1
Niklaus Wirth is an already legendary Swiss born computer scientist with many contributions in developing
various programming languages. The best known is Pascal. Wirths law is a sentence which Wirth made popular,
but he attributed it to Martin Reiser.
10.1. TYPES OF FOURTH ORDER SYSTEMS
283
The third type of system seems to be strange, but a recent developed architecture is a stack
oriented architecture dened for the successful Java language. Naturally, a real Java machine is
endowed also with the program memory.
The third and the fourth types are machines in which the segregation process emphasized
physical structures, a stack or a coprocessor. In both cases the segregated structures are also
simple. The consequence is that the whole system is also a simple system. But, the rst two
systems are very complex systems in which the simple is net segregated by the random. The
support of the random part is the ROM physical structure in the rst case and the symbolic
content of the RAM memory in the second.
Programs
)
PROCESSOR
ROM
3-OS
0-OS
66
DATA
ADDRESS
READ
WAIT
a.
Data & Programs
)
PROCESSOR
RAM
3-OS
1-OS
DATA
66
2
ADDRESS
{READ, W RIT E, }
WAIT
b.
Data
)
PROCESSOR
LIFO
2-OS
3-OS
DATA
6
2
{P U SH, P OP, }
WAIT
c.
Functions
)
PROCESSOR
CO-PROCESSOR
3-OS
3-OS
DATA
COMMANDS
d.
WAIT
Figure 10.1: The four types of 4-OS machines. a. Fix program computers usual in embedded
computation. b. General purpose computer. c. Specialized computer working working on a restricted
data structure. d. Accelerated computation supported by a specialized co-processor.
The actual computing machines have currently more than order 4, because the processors
involved in the applications have additional features. Many of these features are introduced by
new loops that increase the autonomy of certain subsystems. But theoretically, the computer
function asks at least four loops.
284
10.1.1
The computer support for the strongest segregation
The ROM content is dened symbolically and after that it is converted in the actual physical
structure of ROM. Instead, the RAM content remains in symbolic form and has, in consequence, more exibility. This is the main reason for considering the PROCESSOR & RAM =
COMPUTER as the most representative in 4-OS.
The computer is not a circuit. It is a new entity with a special functional denition, currently
called computer architecture. Mainly, the computer architecture is given by the machine language. A program written in this language is interpreted or executed by the processor. The
program is stored in the RAM memory. In the same subsystem are stored data on which the
program acts. Each architecture can have many associated computer structures (organizations).
Starting from the level of four order systems the behavior of the system is controlled mainly
by the symbolic structure of programs. The architectural approach settles the distinction between the physical structures and the symbolic structures. Therefore, any computing machine
supposes the following triadic denition (suggested by [Milutinovic 89]):
the machine language (usually called architecture)
the storage containing programs written in the machine language
the machine that interprets the programs, containing:
the machine language ...
the storage ...
the machine ... containing:
...
and so on until the machine executes the programs.
Does it make any sense to add new loops? Yes, but not too much! It can be justied to
add loops inside the processor structure to improve its capacity to interpret fast the machine
language by using simple circuits. Another way is to see PROCESSOR & COPROCESSOR or
PROCESSOR & LIFO as performant processors and to add over them the loop through RAM.
But, mainly these machines remain structures having the computer function. The computer
needs at least four loops to be competent, but currently it is implemented on system having
more loops in order to become performant.
10.2
The stack processor a processor as 4-OS
The best way to explain how to use the concept of architecture to design an executive processor is to
use an example having an appropriate complexity. One of the simplest model of computing machine is
the stack machine. A stack machine nds always its operands in the rst two stages of a stack (LIFO)
memory. The last two pushed data are the operands involved in the current operation. The computation
must be managed to have accessible the current operand(s) in the data stack. The stack used in a stack
processor have some additional features allowing an ecient data management. For example: double
pop, swap, . . ..
The high level description of a stack processor follows. The purpose of this description is to oer an
example of how starts the design of a processor. Once the functionality of the machine is established at
the higher level of the architecture, there are many ways to implement it.
10.2. THE STACK PROCESSOR A PROCESSOR AS 4-OS
10.2.1
285
The organization
Our Stack Processor is a sort of simple processing element characterized by using a stack memory
(LIFO) for storing the internal variables. The top level internal organization of a version of Stack
Processor (see Figure 10.2) contains the following blocks:
STACK & ALU SALU is the unit performing the elementary computations; it contains:
a two-output stack; the top of stack (stack0 or tos) and the previous recording (stack1)
are accessible
an ALU with the operands from the top of stack (left op = stack0 and right io =
stack1)
a selector for the input of stack grabbing data from: (0) the output of ALU, (1) external data
memory, (2) the value provided by the instruction, or (3) the value of pc +1 to be used as
return address
PROGRAM FETCH a unit used to generate in each clock cycle a new address for fetching from
the external program memory the next instruction to be executed
DECODER is a combinational circuit used to trans-code the operation code op code into
commands executed by each internal block or sub-block.
the fourth loop

data out
data addr
instr addr
ret addr
SALU
STACK
stack com
pc com
MUX4
2
6 6 6 6
NEXT PC
stack1
stack0
data sel
1
left
?
PC
ALU
data in
right
PROGRAM
FETCH

<value>
alu com
instruction
data mem com

mem ready
DECODER
<op code>
Figure 10.2: An executing Stack Processor. Elementary functions are performed by ALU
on variables stored in a stack (LIFO) memory. The decoder supports the one-cycle execution of the
instructions fetched from the external memory.
Figure 10.3 represents the Verilog top module for our Stack Processor (stack processor).
The two loop connected automata are SALU and PROGRAM FETCH. Both are simple, recursive
dened structures. The complexity of the Stack Processor is given by the DECODE unit: a combinational circuit used to trans-code op code providing 5 small command words to specify how behaves
286
module stack_processor(input
clock
,
input
reset
,
output [31:0] instr_addr ,
// instruction address
output [31:0] data_addr
,
// data address
output [1:0]
data_mem_com,
// data memory command
output [31:0] data_out
,
// data output
input
[23:0] instruction ,
// instruction input
input
[31:0] data_in
,
// data input
input
mem_ready
); // data memory is ready
wire
[2:0]
stack_com
;
// stack command
wire
[3:0]
alu_com
;
// alu command
wire
[1:0]
data_sel
;
// data selection for SALU
wire
[2:0]
pc_com
;
// program counter command
wire
[31:0] tos
,
// top of stack
ret_addr
;
// return from subroutine address
// INSTRUCTION DECODER UNIT
decode decode( .op_code
(instruction[23:16]) ,
.test_in
(tos)
,
.mem_ready
(mem_ready)
,
.stack_com
(stack_com)
,
.alu_com
(alu_com)
,
.data_sel
(data_sel)
,
.pc_com
(pc_com)
,
.data_mem_com
(data_mem_com)
);
// SALU: STACK WITH ARITHMETIC & LOGIC UNIT
salu
salu(
.stack0
(tos)
,
.stack1
(data_out)
,
.in1
(data_in)
,
.in2
({16b0, instruction[15:0]}),
.in3
(ret_addr)
,
.s_com
(stack_com)
,
.data_sel
(data_sel)
,
.alu_com
(alu_com)
,
.reset
(reset)
,
.clock
(clock)
);
assign data_addr = tos;
// PROGRAM COUNTER UNIT
program_counter pc( .clock
(clock)
,
.reset
(reset)
,
.addr
(instr_addr)
,
.inc_pc
(ret_addr)
,
.value
(instruction[15:0]) ,
.tos
(tos)
,
.pc_com
(pc_com)
);
endmodule
Figure 10.3: The top level structural description of a Stack Processor. The Verilog code
associated to the circuit represented in Figure 10.2.
287
each component of the system. The Verilog decode module uses test in = tos and mem ready to make
decisions. The value of tos can be tested (if it is zero or not, for example) to decide a conditional jump
in program (on this way only PROGRAM FETCH module is aected). The mem ready input received
from data memory allows the processor to adapt itself to external memories having dierent access time.
The external data and program memories are both synchronous: the content addressed in the current
clock cycle is received back in the next clock cycle. Therefore, instruction received in each clock cycle
corresponds to instr addr generated in the previous cycle. Thus, the fetch mechanism ts perfect with
the behavior of the synchronous memory. For data memory mem ready ag is used to inform the decode
module to delay one clock cycle the use of the data received from the external data memory.
In each clock cycle ALU unit from SALU receives on its data inputs the two outputs of the stack,
and generates the result of the operation selected by the alu com code. If MUX4 has the input 0 selected
by the data sel code, then the result is applied to the input of stack. The result is written back in
tos if a unary operation (increment, for example) is performed (write the result of increment in tos is
equivalent with the sequence pop, increment & push). If a binary operation (addition, for example) is
performed, then the rst operand is popped from stack and the result is written back over the the new
tos (double pop & push involved in a binary operation is equivalent with pop & write).
MUX4 selects for the stack input, according to the command data sel, besides the output of ALU,
data received back from the external data memory, the value carried by the currently executed instruction,
or the value pc+1 (to be used as return address).
module decode( input
input
input
output
output
output
output
output
[7:0]
[31:0]
[2:0]
[3:0]
[1:0]
[2:0]
[1:0]
op_code
,
test_in
,
mem_ready
,
stack_com
,
alu_com
,
data_sel
,
pc_com
,
data_mem_com);
include "micro_architecture.v"
include "instruction_set_architecture.v"
include "decoder_implementation.v"
endmodule
Figure 10.4: The decode module. It contains the three complex components of the description of
Stack Processor.
The unit PC generates in each clock cycle the address for program memory. It uses mainly the
value from the register PC, which contains the last used address, to fetch an instruction. The content of
tos or the value contained in the current instruction are also used to compute dierent conditioned or
unconditioned jumps.
To keep this example simple, the program memory is a synchronous one and it contains anytime the
addressed instruction (no misses in this memory).
Because our Stack Processor is designed to be an executing machine, besides the block associated
with the elementary functions (SALU) and the block used to compose & and loop them (PC) there is only
a decoder used as execution unit (see Figure 9.13. The decoder module decode is the most complex
module of Stack Processor (see Figure 10.4). It contains three sections:
micro-architecture: it describes the micro-operations performed by each top level block listing
the meaning of all binary codes used to command them
instruction set architecture: describe each instruction performed by Stack Processor
decoder implementation: describe how the micro-architecture is used to implement the instruction set architecture.
10.2.2
The micro-architecture
Any architecture can be implemented using various micro-architectures. For our Stack Processor one of
them is presented in Figure 10.5.
288
// MICROARCHITECTURE
// pc_com
parameter
stop
=
next
=
small_jmp
=
big_jmp
=
abs_jmp
=
ret_jmp
=
// alu_com
parameter
alu_left
=
alu_right
=
alu_inc
=
alu_dec
=
alu_add
=
alu_sub
=
alu_shl
=
alu_half
=
alu_zero
=
alu_equal
=
alu_less
=
alu_carry
=
alu_borrow =
alu_and
=
alu_or
=
alu_xor
=
// data_sel
parameter
alu
=
mem
=
val
=
return
=
// stack_com
parameter
s_nop
=
s_swap
=
s_push
=
s_write
=
s_pop
=
s_popwr
=
s_pop2
=
// data_mem_com
parameter
mem_nop
=
read
=
write
=
Figure 10.5:
3b000,
3b001,
3b010,
3b011,
3b100,
3b101;
//
//
//
//
//
//
pc
pc
pc
pc
pc
pc
=
=
=
=
=
=
pc
pc + 1
pc + value
pc + tos
value
tos
4b0000,
4b0001,
4b0010,
4b0011,
4b0100,
4b0101,
4b0110,
4b0111,
4b1000,
4b1001,
4b1010,
4b1011,
4b1100,
4b1101,
4b1110,
4b1111;
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
alu_out
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
left
right
left + 1
left - 1
left + right = add[32:0]
left - right = sub[32:0]
{1b0, left[31:1]}
{left[31], left[31:1]}
{31b0, (left == 0)}
{31b0, (left == right)}
{31b0, (left < right)}
{31b0, add[32]}
{31b0, sub[32]}
left & right
left | right
left ^ right
2b00,
2b01,
2b10,
2b11;
//
//
//
//
stack_input
stack_input
stack_input
stack_input
3b000,
3b001,
3b010,
3b100,
3b101,
3b110,
3b111;
//
//
//
//
//
//
//
no operation
swap the content of the first two
push
write in tos
pop
pop2 & push
pops two values
2b00,
2b01,
2b10;
// no data memory command

// read from data memory
// write to data memory
=
=
=
=
alu_out
data_in
value
ret_addr
The micro-architecture of our Stack Processor. The content of le

micro architecture.v denes each command word generated by the decoder describing the associated
micro-commands and their binary codes.
289
The decoder unit generates in each clock cycle a command word having the following 5-eld structure:
{alu com, data sel, stack com data mem com, pc com} = command
where:
alu com: is a 4-bit code used to select the arithmetic or logic operation performed by ALU in the
current cycle; it species:
well known binary operations such as: add, subtract, and, or, xor
usual unary operations such as: increment, shifts
test operations indicating by alu out[0] the result of testing, for example: if an input is zero
or if an input is less than another input
data sel: is a 2-bit code used to select the value applied on the input of the stack for the current
cycle as one from the following:
the output of ALU
data received from data memory addressed by tos (with a delay of one clock cycle controlled
by mem ready signal because the external data memory is synchronous)
the 16-bit integer selected from the current instruction
pc+1, generated by the PROGRAM FETCH module, to be pushed in stack when the a call
instruction is executed
stack com: is a 3-bit code used to select the operation performed by the stack unit in the current
cycle (it is correlated with the ALU operation selected by alu com); the following micro-operations
are codded:
push: it is the well known standard writing operation into a stack memory
pop: it is the well known standard reading operation into a stack memory
write: it writes in top of stack, which is equivalent with popping an operand and pushing
back the result of operation performed on it (used mainly in performing unary operations)
pop & write: it is equivalent with popping two operands from stack and pushing back the
result of operation performed on them (used mainly in performing binary operations)
double pop: it is equivalent with two successive pops, but is performed in one clock cycle;
some instructions need to remove both the content of stack0 and of stack1 (for example,
after a data write into the external data memory)
swap: it exchange the content of stack0 and of stack1; it is useful, for example to make a
subtract in the desired order.
data mem com: is a 2-bit command for the external data memory; it has three instantiations:
memory nop: keep memory doing nothing is a very important command
read: commands the read operation from data memory with the address from tos; the data
will be returned in the next clock cycle; in the current cycle mem read is activated to allow
stoping the processor one clock cycle (the associated read instruction will be executed in two
clock cycles)
write: the data contained in stack1 is written to the address contained in stack0 (both,
address and data will be popped from stack)
pc com: is a 3-bit code used to command how is computed the address for the fetching of the next
instruction; 6 modes are used:
stop: program counter is not incremented (the processor halts or is waiting for a condition
to be fullled)
next: it is the most frequent mode to compute the program counter by incrementing it
290
small jump: compute the next program counter adding to it the value contained in the
current instruction (instruction[15:0]) interpreted as a 16-bit signed integer; a relative
jump in program is performed
big jump: compute the next program counter adding to it the value contained in tos interpreted as a 32-bit signed integer; a relative big jump in program is performed
absolute jump: the program counter takes the value of instruction[15:0]; thhe processor
performs an absolute jump in program
return jump: is an absolute jump performed using the content of tos (usually performs a
return from a subroutine, or is used to call a subroutine in a big addressing space)
The 5-eld just explained can not be lled up without inter-restrictions imposed by the meaning of the
micro-operations. There exist inter-correlations between the micro-operations assembled in a command.
For example, if ALU performs an addition, then the stack must perform mandatory pop & poop& &
push == pop write. If the ALU operation is increment, then the stack must perform write. Some elds
are sometimes meaningless. For example, when an unconditioned small jump is performed the elds
alu com and data sel can take dont care values. But, for obvious reasons, no times stack com and
data mem com can take dont care values.
Each unconditioned instruction has associated one 5-eld commands, and each conditioned instructions is dened using two 5-eld commands.
10.2.3
The instruction set architecture
Instruction set architecture is the interface between the hardware and the software part of a computing
machine. It grounds the denition of the lowest level programming language: the assembly language.
It is an interface because allows the parallel work of two teams once its denitions is frozen. One is the
hardware team which starts to design the physical structure, and the other is the software team which
starts to grow the symbolic structure of the hierarchy of programs. Each architecture can be embodied
in many forms according to the technological restrictions or to the imposed performances. The main
benet of this concept is the possibility to change the hardware without throwing out the work done by
the software team.
The implementation of our Stack Processor has, as the majority of the currently produced processors,
an instruction set architecture containing the following class of instructions:
arithmetic and logic instructions having the form:
[stack0, stack1, s2, ...] = [op(stack0, stack1), s2, ...]
where: stack0 is the top of stack, stack1 is the next recording in stack, and op is an arithmetic
or logic binary operation
[stack0, stack1, s2, ...]
if the operation op is unary
= [(op(stack0), stack1, s2, ...]
input-output instructions which uses stack0 as data addr and stack1 as data out
stack instructions (only for stack processors) used to immediate load the stack or to change the content
in the rst two recordings (stack0 and stack1)
test instructions used to test the content of stack putting the result of the test back into the stack
control instructions used to execute unconditioned or conditioned jumps in the instruction stream by
modifying the variable program counter used to address in the program space.
The instruction set architecture is given as part of the Verilog code describing the module
decode: the content of the le instruction set architecture.v (a more complete stage of this
module in Appendix: Designing a stack processor). Figure 10.6 contains an incipient form of le
instruction set architecture.v. From each class of instructions only few examples are shown. Each
instruction is performed in one clock cycle, except load whose execution can be delayed if data ready
= 0.
291
// INSTRUCTION SET ARCHITECTURE

// arithmetic & logic instructions (pc <= pc + 1)
parameter
nop
= 8b0000_0000, // s0, s1, s2 ... <= s0, s1, s2, ...
add
= 8b0000_0001, // s0, s1, s2 ... <= s0 + s1, s2, ...
inc
= 8b0000_0010, // s0, s1, s2 ... <= s0 + 1, s1, s2, ...
half
= 8b0000_0011; // s0, s1, s2 ... <= s0/2, s1, s2, ...
// ...
// input output instructions (pc <= pc + 1)
parameter
load
= 8b0001_0000, // s0, s1, s2 ... <= data_mem[s0], s1, s2, ...
store
= 8b0001_0001; // s0, s1, s2 ... <= s2, s3, ...; data_mem[s0] = s1
// stack instructions (pc <= pc + 1)
parameter
push
= 8b0010_0000, // s0, s1, s2 ... <= value, s0, s1, ...
pop
= 8b0010_0010, // s0, s1, s2 ... <= s1, s2, ...
dup
= 8b0010_0011, // s0, s1, s2 ... <= s0, s0, s1, s2, ...
swap
= 8b0010_0100, // s0, s1, s2 ... <= s1, s0, s2, ...
over
= 8b0010_0101; // s0, s1, s2 ... <= s1, s0, s1, s2, ...
// ...
// test instructions (pc <= pc + 1)
parameter
zero
= 8b0100_0000, // s0, s1, s2 ... <= (s0 == 0), s1, s2, ...
eq
= 8b0100_0001; // s0, s1, s2 ... <= (s0 == s1), s2, ...
// ...
// control instructions
parameter
jmp
= 8b0011_0000, // pc = pc + value
call
= 8b0011_0001, // pc = s0; s0, s1, ... <= pc + 1, s1, ...
cjmpz
= 8b0011_0010, // if (s0 == 0) pc <= pc + value, else pc <= pc + 1
cjmpnz = 8b0011_0011, // if (s0 == 0) pc <= pc + 1, else pc <= pc + value
ret
= 8b0011_0111; // pc = s0; s0, s1, ... <= s1, s2, ...
// ...
Figure 10.6: Instruction set architecture of our Stack Processor. From each subset few
typical example are shown. The content of data stack is represented by: s0, s1, s2, ....
10.2.4
Implementation: from micro-architecture to architecture
Designing a processor (in our case designing the Stack Processor) means to use the micro-architecture
to implement the instruction set architecture. For an executing processor the connection between
micro-architecture and architecture is done by the decoder which is a combinational structure.
The main body of the decode module decoder implementation.v contains the description of
the Stack Processors instruction set architecture in term of micro-architecture.
The structure of the le decoder implementation.v is suggested in Figure 10.7, where the output
variables are the 5 command elds (declared as registers) and the input variables are: the operation code
from instruction, the value of tos received as test in and the ag received from the external memory:
mem ready.
The main body of this vile consists in a big case structure with an entry for each instruction. In
Figure 10.7 only few instructions are implemented (nop, add, load) to show how an unconditioned
instruction nop, add or a conditioned instruction load is executed.
Instruction nop does not aect the state of stack and PC is incremented. Wemust take care only
about three command elds. PC must be incremented (next, and the elds commanding memory resources (stack, external data memory) must be set on no operation (s nop, mem nop. The operation
performed by ALU and data selected as right operand have no meaning for this instruction.
292
Instruction add pops the two last recordings in stack, adds them, pushes back the result in tos, and
increments PC. Meantime the data memory receives no active command.
Instruction load is executed in two clock cycles. In the rst cycle, when mem ready = 0, the command read is sent to the external data memory, and the PC is maintained unchanged. The operation
performed by ALU does not matter. The selection code for MUX4 does not matter. In the next clock
cycle data memory sets it ag on 1 (mem ready = 1 means the requested data is available), data selected
is from memory mem), and the output of MUX4 is pushed in stack ((s push).
By default the decoder generates dontcare commands. Another possibility is to have nop instruction
the by default instruction. Or by default to have a halt instruction which stops the processor. The
rst version is good as a nal solution because generates a minimal solution. The last version is preferred
in the initial stage of development because provides an easy testing and debugging solution.
Follows the description of some typical instructions from a possible instruction set executed by our
Stack Processor.
Instruction inc increments the top of stack, and increments also PC. The right operand of ALU
does not matter. The code describing this instruction, to be inserted into the big case sketched in Figure
10.7, is the following:
inc
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
next
alu_inc
alu
s_write
m_nop
;
;
;
;
;
end
Instruction store stores the value contained in stack1 at the address from stack0 in external data
memory. Both, data and address are popped from stack. The associated code is:
store
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
next ;
4bx ;
2bx ;
s_pop2;
write ;
end
Instruction push pushes {16b0, instruction[15:0]} in in stack. The code is:

push
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
next
4bx
val
s_push
m_nop
;
;
;
;
;
end
Instruction dup pushes in stack the top of stack, thus duplicating it. ALU performs alu left, the
right operand does not matter, and in the stack is pusher the output of ALU. The code is:
dup
begin
end
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
next
alu_left
alu
s_push
m_nop
;
;
;
;
;
293
// THE IMPLEMENTATION
reg
reg
reg
[3:0]
[2:0]
[1:0]
alu_com
pc_com, stack_com
data_sel, data_mem_com
;
;
;
always @(op_code or test_in or mem_ready

)
case(op_code)
// arithmetic & logic instructions
nop :
begin
pc_com
= next
;
alu_com
= 4bx
;
data_sel
= 2bx
;
stack_com
= s_nop
;
data_mem_com
= mem_nop
;
end
add :
begin
pc_com
= next
;
alu_com
= alu_add
;
data_sel
= alu
;
stack_com
= s_popwr
;
data_mem_com
= mem_nop
;
end
// ...
// input output instructions
load
:
if (mem_ready)
begin
pc_com
= next
alu_com
= 4bx
data_sel
= mem
stack_com
= s_write
data_mem_com
= mem_nop
end
else
begin
pc_com
= stop ;
alu_com
= 4bx ;
data_sel
= 2bx ;
stack_com
= s_nop ;
data_mem_com
= read ;
end
// ...
// ...
default
begin
pc_com
= 3bx ;
alu_com
= 4bx ;
data_sel
= 2bx ;
stack_com
= 3bx ;
data_mem_com
= 2bx ;
end
endcase
;
;
;
;
;
Figure 10.7: Sample from the le decoder implementation.v. Implementation consists in a

big case form with an entry for each instruction.
294
Instruction over pushes stack1 in stack, thus duplicating the second stage of stack. ALU performs
alu right, and in the stack is pusher the output of ALU.
over
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
next
alu_right
alu
s_push
m_nop
;
;
;
;
;
end
The sequence of instructions:
over;
over;
duplicates the rst two recordings in stack to be reused later in another stage of computation.
Instruction zero substitute the top of stack with 1, if its content is 0, or with 0 if the content is
dierent from 0.
zero
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
next
alu_zero
alu
s_write
m_nop
;
;
;
;
;
end
This instruction is used in conjunction with a conditioned jump (cjmpz or cjmpnz) to decide according
to the value of stack0.
Instruction jmp adds to PS the signed value instruction[15:0].

jmp
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
rel_jmp
4bx
2bx
s_nop
m_nop
;
;
;
;
;
end
This instruction is expressed as follows:
jmp <value>
where, <value> is expressed sometimes as an explicit signed integer, but usually as a label which takes
a numerical value only when the program is assembled. For example:
jmp loop1;
Instruction
call performs an absolute jump to the subroutine placed at the address

instruction[15:0], and saves in tos the return address (ret addr) which is pc + 1. The address
saved in stack will be used by ret instruction to return the processor from the subroutine into the main
program.
call
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
end
The instruction is used, for example, as follows:
jmp subrt5;
where subrt5 is the label of a certain subroutine.
abs_jmp
4bx
return
s_write
m_nop
;
;
;
;
;
295
Instruction cjmpz performs a relative jump if the content of tos is zero; else PC is incremented.
The content of stack is unchanged. (A possible version of this instruction pops the tested value from the
stack.)
cjmpz
if (test_in == 32b0)
begin
pc_com
alu_com
data_sel
stack_com
data_mem
end
else
begin
pc_com
alu_com
data_sel
stack_com
data_mem
end
=
=
=
=
=
small_jmp
4bx
2bx
s_nop
m_nop
=
=
=
=
=
next
4bx
2bx
s_nop
m_nop
;
;
;
;
;
;
;
;
;
;
The instruction is used, for example, as follows:

jmp george;
where george is a label to be converted in a signed 16-bit integer in the assembly process.
Instruction ret performs a jump from subroutine back into the main program using the address
popped from tos.
ret
begin
pc_com
alu_com
data_sel
stack_com
data_mem
=
=
=
=
=
ret_jmp
4bx
2bx
s_pop
m_nop
;
;
;
;
;
end
The hardware resources of this Stack Processor permits up to 256 instructions to be dened. For
this simple machine we do not need to dene too many instructions. Therefore, a smart codding of
instructions will allow minimizing the size of decoder. More, for some critical paths the depth of decoder
can be also minimized, eventually reduced to zero. For example, maybe it is possible to set
alu com = instruction[19:16]
data sel = instruction[21:20]
allowing the critical loop to be closed faster.
10.2.5
Time performances
Evaluating the time behavior of the just designed machine does not make us too happy. The main reason
is provided by the fact that all the external connections are unbuered.
All the three inputs, instruction, data in, mem ready must be received long time before the
active edge of clock because their combinational path inside the Stack Processor are too deep. More,
these paths are shared partially with the internal loops responsible for the maximum clock frequency.
Therefore, optimizing the clock interferes with optimizing tin reg .
Similar comments apply to the output combinational paths.
The most disturbing propagation path is the combinational path going from inputs to outputs (for
example: from instruction to data mem com). The impossibility to avoid tin out make this design very
unfriendly at the system level. Connecting this module together with a data memory a program memory
and some input-output circuits will generate too many (restrictive) time dependencies.
296
This kind of approach can be useful only if it is strongly integrated with the design of the associated
memories and interfaces in a module having all inputs and outputs strictly registered.
The previously described Stack Processor remains to be a very good bad example of a pure functionally
centered design which ignores the basic electrical restrictions.
10.2.6
Concluding about our Stack Processor
The simple processor exemplied by Stack Processor is typical for a computational engine: it contains an
simple working 3loop system SALU and another simple automaton Program Fetch both driven
by a decoder to execute what is codded in each fetched instruction. Therefore, the resulting system is
a 4th order one. This is not the solution! A lot of improvement are possible, and a lot of new features
can be added. But it is very useful to exemplify one of the main virtue of the fourth loop: the 4-loop
processing. A processor with more than the minimal 3 loops is easiest to be controlled. In our cases the
operands are automatically selected by the stack mechanism. Results a lot of advantages in control and
some performance loss. But, the analysis of pros & cons is not a circuit design problem. It is a topics to
be investigated in the computer architecture domain.
The main advantages of a stack machine is its simplicity. The operands are in each cycle already
selected, because they are the rst to recording in the top of stack. Results a simple instruction containing
only two elds: op code[7:0] and value[15:0].
The loop inside SALU is very short allowing a high clock frequency (if other loop do not impose a
smaller one).
The main disadvantage of a stack machine is the stack discipline which sometimes adds new instructions in the code generated by the compiler.
Writing a compiler for this kind of machine is simple because the discipline in selecting the operands
is high. The eciency of the resulting code is debatable. Sometimes a longer sequence of operation is
compensated by the higher frequency allowed by a stack architecture.
A real machine can adopt a more sophisticated stack in order to remove some limitation imposed by
the restricted access imposed by the discipline.
10.3
Embedded computation
Now we are prepared to revisit the Chapter OUR FINAL TARGET in order to oer an optimal
implementation for the small & simple system toyMachine. The main application for such
a machine is in the domain of the embedded computation. The technology of embedded
computation uses programmable machines of various complexity to implement by programming
functions formerly implemented by big & complex circuits.
Instead of the behavioral description by the module toyMachine (see Figure 5.3) we are
able to provide now a structural description. Even if the behavioral description oered by the
module toyMachine is synthesisable will we see that the following structural version provides a
half sized circuit.
10.3.1
The structural description of toyMachine
A structural description is supposed to be a detailed description which provide a hierarchical

description of the design using on the leafs of the tree simple and optimal circuits. A structural
description answers the question of how.
The top module
In the top module of the design toyMachineStructure there are four structures (see also
Figure 10.8):
syncGpi : the 16-bit input register is used to synchronize individually each of the 16 input
signals; note that the 16 bits as a whole binary conguration can not be synchronized
using a simple register, because each ip-op has its own set-up time and hold time
10.3. EMBEDDED COMPUTATION
297
interruptUnit : the module manages the interrupt signal (which is supposed to be synchronous
with the system clock), execute the two instructions which control the interrupt acknowledge process, and generates the inta signal
controlSection : manages the instruction ow read from the program memory and executed,
one per clock cycle, by the entire system; the specic control instructions are executed by
this module using data, when needed, provided by the other modules (bits from syncGpi,
values from controlSection); the asyncInta signal constrains the specic action of jumping to the instruction addressed with the content of rf[7]
dataSection : performs the functional aspect of computation, operating on data internally
stored by the register le, or received from the external world; it generate also the output
signals loading the output register gpo with the results of the internal computation.
gpi
syncGpi
[10:7]
10b1
? ???

loopSel
loopMux
[6:0]
??
Decode
theInc
?

fileMux
?
in
? ? ? ? insSel

mux2
pc
bitSel
adder
?

op0
op1
regFile
op2
leftOp
rightOp
fileEnable
[2:0]
[5:3]
[10:8]
?

mux1
Data
Section
ALU
aluOut
[13:11]
zero
- Decode
?

?
gpo
Control
Section
Program
?
tMux
nextSel
nextPc
Memory
gpoEnable
bit
6 6
Instruction
gpo
[15:11]
instruction
?
asyncInta
intAut
[15:11]
6
int
?
inta
Figure 10.8: The block schematic of the toyMachine design.

The block Data Section is a second order (2-loop) digital system having the second loop
closed over the Register File through ALU, loopMux and leMux. The rst loop in this
section is closed in the latches used to build the module Register File.
The block Control Section is a third order (3-loop) digital system, because the rst loop
is closed in the master-slave ip-ops of the program counter (pc, the second loop is closed over
pc through adder and mux1, and the third loop is closed through the synchronous Program
Memory.
Because intAut is a second order system, it forms with Control Section a fourth order
system. Thus, the toyMachine system is a fth order digital system, the last loop being closed
298
through Data Section module which receives pc, instruction, asyncInta and sends back
rightOp.
See in Figure 10.9 the code describing the top module. If the content of the two dash boxes
is ignored, the Figure 10.8 represents the interconnections between the four modules dened at
the top level of the structural description of toyMachine.
module toyMachineStructure(input
int , // interrupt
output
inta , // interrupt acknowledge
input [15:0] gpi , // general purpose inputs
output [15:0] gpo , // general purpose outputs
input
reset,
input
clock);
wire [15:0] instruction; // the instruction code
wire [9:0] pc
; // program counter
wire [15:0] rightOp
; // the right operand for controlSection from dataSection
wire
asyncInta ; // internal asynchronous interrupt acknowledge
reg [15:0] syncGpi
; // synchronized gpi
always @(posedge clock) syncGpi <= gpi;
interruptUnit interruptUnit(
inta
int
// EXTERNAL CONNECTIONS
,
,
asyncInta , // to controlSection
instruction, // from controlSection
reset
,
clock
);
controlSection controlSection(
syncGpi
, // synchronized gpi
instruction, // to interruptUnit & dataSection
asyncInta , // from interruptUnit
pc
, // to dataSection
rightOp
, // from dataSection
reset
,
clock
);
dataSection dataSection(
gpo
,
syncGpi
, // synchronized gpi
rightOp
, // to controlSection
pc
, // from controlSection
instruction, // from controlSection
asyncInta , // from interruptUnit
clock
);
endmodule
Figure 10.9: The top module which describes the toyMachine structure. design.
Unlike the module toyMachine (see Chapter OUR FINAL TARGET), which describe on one
level design the behavior of toyMachine, the module toyMachineStucture is a pure structural
description providing only the top level description of the same digital system. It contains three
modules, one for each main sub-system of or design, and the input register.
299
The interrupt unit

There are many ways to solve the problem of the interrupt signal in a computing machine.
The solutions are dierent depending on the way the signals int and inta are connected to
the external systems. The solution provided here is the simplest one. It is supposed that both
signals are synchronous with the toyMachine structure. This simple solution consists of a
2-state automaton described in the module interruptUnit (see Figure 10.10.
module interruptUnit(output reg
inta
,
input
int
,
output
asyncInta , // to controlSection
input
[15:0] instruction, // from controlSection
input
reset
,
input
clock
);
reg intEnable; // interrupt enable one-bit register
assign asyncInta = intEnable & int;
always @(posedge clock) inta <= asyncInta;
if (reset | inta | (instruction[15:11] == di)) intEnable <= 0;
else if (instruction[15:11] == ei)
intEnable <= 1;
endmodule
Figure 10.10: The module interruptUnit.

Because the input int is considered synchronously generated with the system clock, the
signal asyncIna is combinational generated. In order to avoid uncontrolled combinational loops
(we do not know how the signal inta is used by the system which receives it), the output signal
inta is generated synchronizing the signal asyncInta.
The next subsection provides an enhanced version of this module which is able to manage
asynchronous int signal.
The control section
This unit fetches in each clock cycle a new instruction from the program memory. The instruction
is decoded locally for its use and is also sent for the use of the data unit and interrupt unit. For
each instruction there is a specic way to use the content of the program counter pc in order
to compute the address of the next instruction. For data and interrupt instructions (see Figure
5.2) the next instruction is always fetched form the address pc + 1. For the control instructions
(see Figure 5.2) there are dierent modes for each instruction. The internal structure of the
module controlSection is designed to provide the specic modes of computing the next value
for the program counter.
The two multiplexors mux1 and mux2 from the control section (see Figure 10.8) are used
to select the next value of the program counter, providing the value of nextPc. The program
counter register is set to the value read from the le register on the output rightOp) or is
incremented, according to the selection made by mux1. The value of the increment theInc is
selected by mux2. The selection bits for mux1 and mux2 are generated by the Decode module from
control section (described by the Verilog module controlTransCoder). It uses for generating
the selections for the two multiplexors: opCode from instruction, asyncInta, and the content
300
of syncGpi and of the register selected by op2 from the register le. Two simple circuits are
used to provide the condition bits for decoder. One is the 16 one-bit input multiplexor tMux
which selects the condition bit bit from syncGpi, and the other is the circuit called zero which
provide condition bit zero comparing to zero the rightOp signal received from Data Section.
module controlSection(input
[15:0] syncGpi
,
output reg [15:0] instruction,
input
asyncInta ,
output reg [9:0] pc
,
input
[15:0] rightOp
,
input
reset
,
input
clock
);
reg [15:0] programMemory[0:1023]; // program read only memory
initial $readmemb("0_programMemory.v", programMemory);
wire [9:0] nextPc
;
wire [9:0] theInc
;
wire
nextSel ;
wire [1:0] theIncSel;
if (reset) begin pc
<= 10b1111111111;
instruction <= 0
;
end
else
begin pc
<= nextPc
;
instruction <= programMemory[nextPc];
end
mux2_10 mux1(.out(nextPc
),
.in0(theInc + pc ),
.in1(rightOp[9:0]),
.sel(nextSel
));
mux4_10 mux2(.out(theInc
),
.in0(10b0
),
.in1(10b1
),
.in2(10b0
),
.in3({{3{instruction[6]}}, instruction[6:0]}),
.sel(theIncSel
));
controlTransCoder controlTransCoder(.nextSel (nextSel
),
),
.theIncSel(theIncSel
.asyncInta(asyncInta
),
.opCode
(instruction[15:11]
),
.zero
(rightOp == 0
),
.bit
(syncGpi[instruction[10:7]]));
endmodule
Figure 10.11: The module controlSection.

The only complex module in the control section is Decode described by the Verilog module
controlTransCoder (see Figure 10.12). The circuit is a combinational circuit which receives as
inputs the operation code and three independent bits: asyncInta, zero, and bit. Because the
event asyncInta = 1 has priority against opCode it generates the selections for an unconditional
jump to the address provided by the rightOp output of the register le (which is selected in the
module Data Section to the value 7 by the same asyncInta). Results: nextSel = 1 and the
value of theIncSel does not matter. For each program control instruction a specic selection
301
is made, and for the rest (by default) program counter is incremented by 1. For the four
conditioned jump instructions the bits bit and zero are tested.
module controlTransCoder(output reg
nextSel ,
output reg [1:0] theIncSel,
input
asyncInta,
input
[4:0] opCode
,
input
zero
,
input
bit
);
always @(asyncInta or opCode or zero or
if (asyncInta)
{nextSel,
else case(opCode)
jmp :
{nextSel,
zjmp : if (zero) {nextSel,
else
{nextSel,
nzjmp: if (~zero) {nextSel,
else
{nextSel,
bjmp : if (bit)
{nextSel,
else
{nextSel,
nbjmp: if (~bit) {nextSel,
else
{nextSel,
halt:
{nextSel,
default
{nextSel,
endcase
endmodule
bit)
theIncSel} = {1b1, 2bxx};
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
theIncSel}
=
=
=
=
=
=
=
=
=
=
=
{1b1,
{1b0,
{1b0,
{1b0,
{1b0,
{1b0,
{1b0,
{1b0,
{1b0,
{1b0,
{1b0,
2bxx};
2b11};
2b01};
2b11};
2b01};
2b11};
2b01};
2b11};
2b01};
2b00};
2b01};
Figure 10.12: The module controlTransCoder.

The type reg in this description must be understood as a variable. The actual structure of
a register is not generated.
The data section
The module dataSection includes mainly the data storage resources and the combinational
circuits allowing the execution of each data instruction in one clock cycle.
Data is stored in the register le, regFile, which allows to read two variable as operands for
the current instruction, selected by instruction[5:3] and instruction[10:8], and to store
the result of the current instruction to the location selected by instruction[2:0] (except the
case when asyncInta = 1 forces reading rightOp form the location 111, to be used as absolute
jump address, and loading the location 110 with the current value of pc).
The arithmetic-logic unit, alu, operate in each clock cycle on the operands received from
the two outputs of the register le: leftOp and rightOp. The operation code is given directly
from instruction (instruction[13:11]).
The input of the register le is provided from the alu output and from other three sources:
syncGpi: because the input bits can be submitted to arithmetic and logic processing only
if they are stored in the register le rst
value = instruction[10:3]: is used to generate immediate values for the purpose of
the program
302
module dataSection(output reg [15:0] gpo

,
input
[15:0] syncGpi
,
output
[15:0] rightOp
, //
input
[9:0] pc
, //
input
[15:0] instruction, //
input
asyncInta , //
input
clock
);
wire
wire
wire
wire
wire
wire
wire
[1:0]
[15:0]
[15:0]
[15:0]
[15:0]
to controlSection
from controlSection
from controlSection
from interruptUnit
fileEnable;
gpoEnable ;
loopSel
;
dataLoop ;
aluOut
;
fileIn
;
leftOp
;
mux4_16 loopMux(.out(dataLoop
),
.in0(aluOut
),
.in1(syncGpi
),
.in2({{8{instruction[10]}}, instruction[10:3]}),
.in3({instruction[10:3], 8b0}
),
.sel(loopSel
));
mux2_16 fileMux(.out(fileIn
),
.in0(dataLoop
),
.in1({6b00, pc}),
.sel(asyncInta ));
regFile regFile(.leftOut (leftOp
),
.rightOut (rightOp
),
.leftAddr (instruction[5:3]
),
.rightAddr(instruction[10:8] | {3{asyncInta}}
),
.destAddr (asyncInta ? 3b011 : instruction[2:0]),
.we
(fileEnable
),
.in
(fileIn
),
.clock
(clock
));
always @(posedge clock) if (gpoEnable) gpo <= leftOp;
alu alu(.aluOut (aluOut
),
.leftOp (leftOp
),
.rightOp(rightOp
),
.aluFunc(instruction[13:11]));
dataTransCoder dataTransCoder(.inta
(asyncInta
),
.opCode
(instruction[15:11]),
.fileEnable(fileEnable
),
.gpoEnable (gpoEnable
),
.loopSel
(loopSel
));
endmodule
Figure 10.13: The module dataSection.
303
pc: is saved as the return address after running the program started by the acknowledged
interrupt.
The rst two of these inputs are selected according to the current instructions by the selection
code loopSel generated by the module dataTransCoder for the multiplexor loopMux. The last
one is forced at the input of the register le by the occurrence of the signal asyncInt used as
the selection bit for the multiplexor fileMux.
The register le description uses the code presented in the subsection Register le. Only
the sizes are adapted to our design (see Figure 10.14.
module regFile(output [15:0] leftOut ,
output [15:0] rightOut ,
input [2:0] leftAddr ,
input [2:0] rightAddr,
input [2:0] destAddr ,
input
we
,
input [15:0] in
,
input
clock
);
reg [15:0] file[0:7];
assign leftOut = file[leftAddr] ,
rightOut = file[rightAddr];
always @(posedge clock) if (we) file[destAddr] <= in;
endmodule
Figure 10.14: The module regFile.

The module called alu (see Figure 10.15) performs the 7 arithmetic-logic functions of our
small instruction set. Because the current synthesis tools are able to synthesize very eciently
uniform arithmetic and logic circuits, this Verilog contains a behavioral description.
module alu(output reg [15:0] aluOut ,
input
[15:0] leftOp , rightOp,
input
[2:0] aluFunc);
always @(leftOp or rightOp or aluFunc)
case(aluFunc)
3b000: aluOut = ~leftOp
;
3b001: aluOut = leftOp & rightOp
;
3b010: aluOut = leftOp | rightOp
;
3b011: aluOut = leftOp ^ rightOp
;
3b100: aluOut = leftOp + rightOp
;
3b101: aluOut = leftOp - rightOp
;
3b110: aluOut = {leftOp[15], leftOp[15:1]};
default aluOut = 16bx
;
endmodule
endcase
Figure 10.15: The module alu.

The Decode block, described in our design by the Verilog moduledataTransCoder, takes the
opCode = instruction[15:11] eld from instruction and asyncInta and trans-codes them
into the control signals used to enable the storage resources of dataSection fileReg, gpo
and to generate the selection code for the multiplexor loopMux. This is the only complex module
from the data section.
304
module dataTransCoder(input
inta
,
input
[4:0] opCode
,
output reg
fileEnable,
output reg
gpoEnable ,
output reg [1:0] loopSel
);
always @(inta or opCode)
if (inta)
{fileEnable, gpoEnable, loopSel}
else case(opCode)
add
: {fileEnable, gpoEnable, loopSel}
sub
ashr : {fileEnable, gpoEnable, loopSel}
neg
bwand : {fileEnable, gpoEnable, loopSel}
bwor : {fileEnable, gpoEnable, loopSel}
bwxor : {fileEnable, gpoEnable, loopSel}
val
hval : {fileEnable, gpoEnable, loopSel}
get
send : {fileEnable, gpoEnable, loopSel}
default {fileEnable, gpoEnable, loopSel}
endmodule
= 8b10_xx;
=
=
=
=
=
=
=
=
=
=
=
=
8b10_00;
8b10_00;
8b10_00;
8b10_00;
8b10_00;
8b10_00;
8b10_00;
8b10_10;
8b10_11;
8b10_01;
8b01_xx;
8b00_00;
endcase
Figure 10.16: The module dataTransCoder.
Multiplexors
The design of toyMachine uses a lot of multiplexors. Their description is part of the project.
module mux2_10 #(parameter n = 10)(output [n-1:0] out,
input [n-1:0] in0, in1,
input
sel);
assign out = sel ? in1 : in0;
endmodule
module mux4_10 #(parameter n = 10)(output reg [n-1:0] out,
input
[n-1:0] in0, in1, in2, in3,
input
[1:0]
sel);
always @(in0 or in1 or in2 or in3 or sel) case(sel)
3b000: out = in0;
3b001: out = in1;
3b010: out = in2;
3b011: out = in3; endcase
endmodule
Figure 10.17: The module multiplexors.
As for the usual functions from an ALU, or small combinational circuits, for multiplexors
behavioral descriptions work very well because the software synthesis tools are enough smart
to know how to provide optimal solutions.
305
Concluding about toyMachine

For the same system toyMachine we have now two distinct descriptions: toyMachine,
the initial behavioral description (see Chapter OUR FINAL TARGET), and the structural
description toyMachineStructure just laid down in this subsection. Both descriptions, the
structural and the behavioral, are synthesisable, but the resulting structures are very dierent.
The synthesis of toyMachine design provides a number of components 2.09 times bigger than
the synthesis of the module toyMachineStructure. A detailed description provided a smallest
structure.
The actual structure generated by the behavioral description is not only bigger, but it is
completely unstructured. The structured version provided by the alternative design is easy to
understand, to debug and to optimize.
10.3.2
Interrupt automaton: the asynchronous version
Sometimes for the interrupt automaton a more rigorous solution is requested. In the already
provided solution the int signal must be stable until inta is activated. In many systems this is
an unacceptable restriction. Another restriction is the synchronous switch of int.
This new version for the interrupt automaton accepts an asynchronous int signal having any
width exceeding the period of the clock. The ow chart describing the automaton is in Figure
10.18. It has 4 states:
dis : the initial state of the automaton when the interrupt action is disabled
en : the state when the interrupt action is enabled
mem : is the state memorizing the occurrence of an interrupt when interrupt is disabled
inta : is the acknowledge state.
The input signals are:
int : is the asynchronous interrupt signal
ei : is a synchronous bit resulting from the decode of the instruction ei (enable interrupt)
di : is a synchronous bit resulting from the decode of the instruction di (disable interrupt)
The output signal is asyncInta. It is in fact a synchronous hazardous signal which will be
synchronized using a DFF.
Because int is asynchronous it must be used to switch the automaton in another state in
which asyncInta will be eventually generated.
The state codding style applied for this automaton is imposed by a asynchronous int signal.
It will be of the reduced dependency by the asynchronous input variable int. Let us try rst the
following binary codes (see the codes in square brackets in Figure 10.18) for the four states of
the automaton:
dis : Q1 Q0 = 00
en : Q1 Q0 = 11
mem : Q1 Q0 = 01
inta : Q1 Q0 = 10
The critical transitions are from the states dis and en, where the asynchronous input int is
tested. Therefore, the transitions from these two states takes place as follows:
306
+
+
+
from state dis = 00: if (ei = 0) then {Q+

1 , Q0 } = {0, int}; else {Q1 , Q0 } = {1, int };
+
+
therefore: {Q1 , Q0 } = {ei, ei int}
+
+
+
from state en = 11: if (di = 0) then {Q+

1 , Q0 } = {1, int }; else {Q1 , Q0 } = {0, int};
+
+
therefore: {Q1 , Q0 } = {di , di int}
Therefore, the transitions triggered by the asynchronous input int inuence always only one
state bit.
reset
00 [00]
dis
int
ei
ei
11 [10]
10 [11]
inta
01 [01]
en
mem
asyncInta
0
1
ei
1
di
int
asyncInta
di
Figure 10.18: Interrupt automaton for a limited width and an asynchronous int signal.
For an implementation with registers results the following equations for the state transition
and output functions:

Q+
1 = Q1 Q0 di + Q1 Q0 ei

Q+
0 = Q1 Q0 (di int) + Q1 Q0 ei + Q1 Q0 (ei int)
asyncInta = Q1 Q0 + Q1 Q0 ei
We are not very happy about the resulting circuits because the size is too big to my taste.
Deserve to try another equivalent state coding, preserving the condition that the transitions
depending on the int input are reduced dependency type. The second coding proposal is (see
the un-bracketed codes in Figure 10.18):
dis : Q1 Q0 = 00
en : Q1 Q0 = 10
mem : Q1 Q0 = 01
inta : Q1 Q0 = 11

module interruptAutomaton(input
input
input
output
input
input
307
int
,
ei
,
di
,
regasyncInt,
reset
,
clock
);
reg [1:0] state

;
reg [1:0] nextState;
always @(posedge clock) if (reset) state <= 0
;
else
state <= nextState;
always @(int or ei or di or state)
case(state)
2b00: if (int) if (ei) {nextState,
else
{nextState,
else if (ei)
{nextState,
else
{nextState,
2b01: if (ei)
{nextState,
else
{nextState,
2b10: if (int) if (di) {nextState,
else
{nextState,
else if (di)
{nextState,
else
{nextState,
2b11:
{nextState,
endcase
endmodule
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
asyncInt}
=
=
=
=
=
=
=
=
=
=
=
3b11_0;
3b01_0;
3b10_0;
3b00_0;
3b00_1;
3b01_0;
3b01_0;
3b11_0;
3b00_0;
3b10_0;
3b00_1;
Figure 10.19: The module interruptAutomaton.

The new state transition functions are:

Q+
1 = Q1 Q0 di + Q1 Q0 ei
Q+
0 = Q0 int + Q1 Q0 ei
The Verilog behavioral description for this version is presented in Figure 10.19.
If we make another step re-designing the loop for an intelligent JK register, then results
for the loop the following expressions:
J1 = Q0 ei
K1 = di + Q0
J0 = int
K0 = Q1 + ei
and for the output transition:
asyncInta = Q0 (Q1 + ei) = Q0 K0
A total of 4 2-input gates for the complex part of the automaton. The nal count: 2 JK-FFs, 2
ANDs, 2 ORs. Not bad! The structural description for this version is presented in Figure 10.20
and in Figure 10.21
The synthesis process will provide a very small circuit with the complex part implemented
using only 4 gates. The module interruptUnit in the toyMachine design must be redesigned
308
module interruptAutomaton(input int

,
input ei
, di,
output asyncInta,
input reset
,
input clock
);
wire q1, q0, notq1, notq0;
JKflipFlop ff1(.Q
(q1
),
.notQ (notq1
),
.J
(notq0 & ei),
.K
(di | q0
),
.reset(reset
),
.clock(clock
));
JKflipFlop ff0(.Q(q0),
.notQ (notq0 ),
.J
(int
),
.K
(q1 | ei),
.reset(reset ),
.clock(clock ));
assign asyncInta = q0 & (q1 | ei);
endmodule
Figure 10.20: The structural description of the module interruptAutomaton implemented using JK-FFs..
module JKflipFlop(output reg Q
,
output
notQ ,
input
J
, K,
input
reset,
input
clock);
assign notQ = ~Q;
always @(posedge clock) if (reset) Q <= 0
;
else
Q <= J & notQ | ~K & Q;
endmodule
Figure 10.21: The module JKflipFlop.

including the just presented module interruptAutomaton. The size of the overall project will
increase, but the interrupt mechanism will work with less electrical restrictions imposed to the
external connections.
10.4
Problems
Problem 10.1 Interpretative processor with distinct program counter block.
10.5
Projects
Project 10.1
Chapter 11
# SELF-ORGANIZING
STRUCTURES:
N-th order digital systems
the concept of computer, as at least four-loop system, was introduced. The basic part of
the section is contained in the Problems section. Adding few loops the functionality of the
system remains the same - basic computation - the only eect is optimizing area, power,
speed.
In this chapter
the self-organizing systems are supported by a cellular approach consisting in n-loop
systems. The main structure discussed are:
the stack memory, as the simplest n-loop system

the cellular automata, as the simplest self-organizing system
fractal structures, as non-uniform network of processors
In the next chapter

we make only the rst step in closing a new kind of loops over an n-order system, thus
introducing the new category of systems with global loops.
309
310CHAPTER 11. # SELF-ORGANIZING STRUCTURES:N-TH ORDER DIGITAL SYSTEMS

Von Neumanns architecture is supported by a structure which consists of two distinct subsystems. The rst is a processor and the second is a memory that stores the bits to be processed.
In order to be processed a bit must be carried from the memory to the processor and many times
back, from the processor to the memory. Too much time is wasted and many structures are
involved only to move bits inside the computing machine. The functional development in the
physical part of a digital systems stopped when this universal model was adopted. In the same
time the performances of the computation process are theoretically limited. All the sort of
parallelism pay tribute to this style that is sequentially founded. We have only one machine,
each bit must be accessed, processed and after that restored. This ritual stopped the growing
process of digital machines around the fth order. There are a small number of useful systems
having more than ve loops.
The number of loops can become very large if we give up this model and we have the nerve
to store each bit near its own processor. A strange, but maybe a winning solution is to
interleave the processing elements with the storage circuits [Moto-Oka 82]. Many of us believe
that this is a more natural solution. Until now this way is only a beautiful promise, but this
way deserves more attention.
Denition 11.1 A digital system, DS, belongs to n-OS if having the size in O(f (n)) contains
a number of internal loop in O(n).
A paradigmatic example of n-loop digital system is the cellular automaton (CA). Many
applications of CA model self-organizing systems.
For the beginning, as a simple introduction, the stack memory is presented in a version
belonging to n-OS. The next subject will be a new type of memory which tightly interleaves
the storage elements with processing circuits: the connex memory. This kind of memory
allows ne grain deep paralel processes in computation. We end with the eco-chip, a spectacular application of the two-dimensional cellular automata enhanced with the connex memorys
functions.
The systems belonging to n-OS support eciently dierent mechanisms related to some
parallel computation models. Thus, there are many chances to ground true parallel computing
architecture using such kind of circuits.
11.1
Push-Down Stack as n-OS
There are only a few exotic structures that are implemented as digital systems with a great
number of loops. One of these is the stack function that needs at least two loops to be realized, as
a system in 2-OS (reversible counter & RAM serially composed). There is another, more uniform
solution for implementing the push-down stack function or LIFO (last-in rst-out) memory. This
solution uses a simple, i.e., recursive dened, structure.
Denition 11.2 The n-level push-down stack, LIF On , is built serial connecting a LIF On1
with a LIF O1 as in Figure 11.1. The one level push-down stack is a register, Rm , loop connected
with m M U X2 , so as:
S1 S0 = 00 means: no op - the content of the register does not change
S1 S0 = 01 means: push - the register is loaded with the input value, IN
S1 S0 = 10 means: pop - the register is loaded with the extension input value, EXTIN.
It is evident that LIF On is a bi-directional serial-parallel shift register. Because the content
of the serial-parallel register shifts in both directions each Rm is contained in two kind of loops:
11.2. CELLULAR AUTOMATA
311
LIF O1
IN
IN
EXTOUT
LIFO (n-1)
OUT
OUT
EXTIN
-0
- 1 MUX - R m
-2
S1
S0
{P U SH, P OP, }
Figure 11.1: The LIFO structure as n OS

through its own MUX for no op function
through two successive LIF O1
Thus, LIF O1 is a 2-OS, LIF O2 is a 3-OS, LIF O3 is a 4-OS, . . ., LIF Oi is a (i + 1)OS, . . ..
The push-down stack implemented as a bi-directional serial-parallel register is an example
of digital system having the order related with the size. Indeed: LIF On1 is a n OS.
11.2
Cellular automata
11.2.1
General denitions
module eCell #(parameter n

(
output reg [n-1:0]
input
[n-1:0]
input
[n-1:0]
input
[n-1:0]
input
[n-1:0]
input
[n-1:0]
input
input
always @(posedge clk)
= 8)
out ,
in ,
in0 ,
in1 ,
in2 ,
in3 ,
rst ,
clk );
if (rst)
else
out <= 0
out <= in0
in1
in2
in3
in
endmodule
module cellAut #(parameter n =
(
input
[n-1:0] in
output reg [n-1:0] out
input
rst
input
clk
wire
reg
8, l = 6, c = 4)
,
,
,
);
[n-1:0] cellOut[0:l*c-1];
[n-1:0]
inReg
;
genvar i;
//* // Linear cellular automaton
;
|
|
|
|
;
-
-
-
-
6
?
6
?
6
?
6
6
-
a.
6
?
6
?
6
?
-
I
6
-
-
R
-
6I
? R
-
6
?
-
I
R
-
6
6I
? R
-
6
6I
? R
-
6
6I
? R
6
6I
? R
c.
b.
?
6
?
6
6
6
?
6
?
6
6

?
6
?
6
6
6
?
6
?
6

6

6
e.
d.
Figure 11.2: Cellular automaton. a. One-dimension cellular automaton. b. Two-dimension

cellular automaton with von Neumann neighborhood. c. Two-dimension cellular automaton with Moore
neighborhood. d. Two-dimension cellular automaton with toroidal shape. e. Two-dimension cellular
automaton with rotated toroidal shape.
generate for (i=0; i<l*c; i=i+1) begin: C

eCell eCell(.out(cellOut[i]
.in ((i==0) ? inReg : {n{1b0}}
.in0(cellOut[(i+l*c-1)%(l*c)]
.in1(cellOut[(i+1)%(l*c)]
.in2({n{1b0}}
.in3({n{1b0}}
.rst(rst
.clk(clk
end
endgenerate
//*/
/* // Two-dimension linearly connected cells
.in ((i==0) ? inReg : {n{1b0}}
.in0(cellOut[(i+l*c-1)%(l*c)]
),
),
),
),
),
),
),
));
),
),
),
11.2. CELLULAR AUTOMATA
313
.in1(cellOut[(i+1)%(l*c)]
.in2(cellOut[(i+l*c-l)%(l*c)]
.in3(cellOut[(i+l)%(l*c)]
.rst(rst
.clk(clk
),
),
),
),
));
end
endgenerate
*/
/*
// Two-dimension cellular automaton

.in ((i==0) ? inReg : {n{1b0}}
.in0(cellOut[((i/c)%c)*c+(i-(((i/c)%c)*c)+c-1)%c]
.in1(cellOut[((i/c)%c)*c+(i-(((i/c)%c)*c)+1)%c]
.in2(cellOut[(i+l*c-l)%(l*c)]
.in3(cellOut[(i+l)%(l*c)]
.rst(rst
.clk(clk
end
endgenerate
),
),
),
),
),
),
),
));
*/
always @(posedge clk) if (rst)
else
begin
end
begin
out
inReg
<= 0
<= 0
;
;
out
inReg
<= cellOut[l*c-1]
<= in
;
end
endmodule
module cellAutSim
reg
reg
reg
wire
#(parameter n = 8) ;
[n-1:0] in
rst
clk
[n-1:0] out
initial begin
;
;
;
;
clk = 0 ;
forever #1 clk = ~clk
end
initial begin
rst = 1 ;
#10 rst = 0 ;
in = 8b1;
//#2
in = 8b0101;
#40 $stop
;
end
cellAut dut(in
out
rst
clk
,
,
,
);
initial $monitor("time= %d clk = %b %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d",

$time, clk, dut.cellOut[15],
dut.cellOut[14],
dut.cellOut[13],
dut.cellOut[12],

dut.cellOut[11],
dut.cellOut[10],
dut.cellOut[9] ,
dut.cellOut[8] ,
dut.cellOut[7] ,
dut.cellOut[6] ,
dut.cellOut[5] ,
dut.cellOut[4] ,
dut.cellOut[3] ,
dut.cellOut[2] ,
dut.cellOut[1] ,
dut.cellOut[0] );
endmodule
11.3
Systolic systems
Leisersons systolic sorter. The initial state: in each cell = . For no operation: in1 =
+, in2 = . To insert the value v: in1 = v, in2 = . For extract: in1 = in2 = +.
A
ck
-A
-B
-C
Latch
a.
Y
Z
ck
min(A,B,C)
out
med(A,B,C)
in1
max(A,B,C)
in2
? ? ?
X
X
-B
-C
Y
Z
ck
ck
X
-B
-C
A
Y
Z
ck
X
-B
-C
A
Y
Z
ck
X
-B
-C
A
Y
Z
ck

-
ck
c.
b.
Figure 11.3: Systolic sorter. a. The internal structure of cell. b. The logic symbol of cell. c. The
organization of the systolic sorter.
module systolicSorterCell #(parameter n=8)(input

[n-1:0] a, b, c,
output reg [n-1:0] x, y, z,
input
rst, ck);
wire
[n-1:0] a1, b1 ; // sorters first level outputs
wire
[n-1:0] a2, c2 ; // sorters second level outputs
wire
[n-1:0] b3, c3 ; // sorters third level outputs
assign
assign
assign
assign
assign
assign
a1
b1
a2
c2
b3
c3
=
=
=
=
=
=
(a < b) ? a : b ;
(a < b) ? b : a ;
(a1 < c) ? a1 : c
(a1 < c) ? c : a1
(b1 < c2) ? b1 : c2
(b1 < c2) ? c2 : b1
;
;
;
;
always @(ck or rst or a2 or b3 or c3)

if (rst & ck)
begin
x = {n{1b1}}
y = {n{1b1}}
z = {n{1b1}}
end
;
;
;
11.3. SYSTOLIC SYSTEMS

else if (ck)
315
begin
x = a2
y = b3
z = c3
;
;
;
end
endmodule
module systolicSorter #(parameter n=8, m=7)(
wire
wire
wire
assign
assign
assign
assign
output
input
input
[n-1:0] out,
[n-1:0] in1, in2,
rst, ck1, ck2);
[n-1:0] x[0:m];
[n-1:0] y[0:m-1];
[n-1:0] z[0:m-1];
y[0]
z[0]
out
x[m]
=
=
=
=
in1
in2
x[1]
{n{1b1}}
;
;
;
;
genvar i;
generate for(i=1; i<m; i=i+1)
begin: C
systolicSorterCell systolicCell(
.a (x[i+1]),
.b (y[i-1]),
.c (z[i-1]),
.x (x[i]),
.y (y[i]),
.z (z[i]),
.rst(rst),
.ck (((i/2)*2 == i) ? ck2 : ck1));
end
endgenerate
endmodule
module systolicSorterSim #(parameter n=8);
reg
ck1, ck2, rst
;
reg
[n-1:0] in1, in2;
wire
[n-1:0] out ;
initial begin
ck1 = 0 ;
forever begin
#3 ck1 = 1
#1 ck1 = 0
;
;
#3 ck2 = 1
#1 ck2 = 0
;
;
end
end
initial begin
ck2 = 0 ;
#2 ck2 = 0 ;
forever begin
end
end
initial begin
#8
#4
#4
#4
#4
rst
in2
in1
rst
in1
in1
in1
in1
=
=
=
=
=
=
=
=
1 ;
0 ;
8b1000;
0 ;
8b0010;
8b0100;
8b0010;
8b0001;

#4
in1 = 8b11111111;
in2 = 8b11111111;
#30 $stop;
end
systolicSorter dut( out,
in1, in2,
rst, ck1, ck2);
initial
$monitor("time = %d ck1 = %b ck2 = %b rst = %b in1 = %d in2 = %d out = %d ",
$time, ck1, ck2, rst, in1, in2, out);
endmodule
The result of simulation is:

#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
time
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0
3
4
5
6
7
8
9
10
11
12
13
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15
16
17
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22
23
24
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30
31
32
33
34
35
36
37
38
39
40
41
42
ck1
ck1
ck1
ck1
ck1
ck1
ck1
ck1
ck1
ck1
ck1
ck1
ck1
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11.4. FRACTAL STRUCTURES

#
#
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time
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11.4
Fractal structures
11.5
Problems
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Problem 11.1 Design a stack with the rst two recordings accessible.
Problem 11.2 Design a stack with the following features in reorganizing the rst recordings.
Problem 11.3 Design a stack with controlled deep access.
Problem 11.4 Design an expandable stack.
Problem 11.5 The global loop on a linear cellular automata providing a pseudo-noise generator.
Problem 11.6
Problem 11.7
Problem 11.8
Chapter 12
# GLOBAL-LOOP SYSTEMS
First-order super-systems
we ended to discuss about closing local loops in digital systems introducing the n-th order
systems.
In this chapter
a new kind of loop will be introduced: the global loop. This loop has the following
characteristics:
it is closed over an n order system

usually carries only control information about the state of the entire system
the feedback introduced classies each subsystems in the context of the entire system
In the next chapter

the second part of this book starts, with a discussion about recursive functions and their
circuit implementations.
The computation model of partial functions is presented.

To each level (basic functions, composition, primitive recursiveness and minimalization) an digital order is associated.
Conclusion: computation means at least 3-loop circuits.
319
320
CHAPTER 12. # GLOBAL-LOOP SYSTEMS
12.1
FIRST-ORDER SUPER-SYSTEMS
ConnexArrayT M
Scalars & Boolean
Log-depth reduction network

Flags
666Log-depth global loop

666
j
???
66
66
??
Linear Cellular Array of EUs | PUs
666
PU
66
IO Plane
6 6
? ?
?
IO Control System
Log-depth distribution network
6
?
IO Data
6
Instruction & Scalar & Address
Figure 12.1: ConnexArrayT M . The global loop is a rst detection network, while the Reduction/Distribution network is used to control the entire system.
12.2
Problems
Problem 12.1
Problem 12.2
Problem 12.3
Part III
ANNEXES
321
Appendix A
Pseudo-code language
The pseudo-code is an outline of a program, written in a form that can easily be converted into
real programming statements. For example, the pseudo-code for a bubble sort routine might be
written:
00
01
02
03
04
05
06
while not at end of list

compare adjacent elements
if second is greater than first
switch them
get next two elements
if elements were switched
repeat for entire list
Pseudo-code cannot be compiled nor executed, and there are no real formatting or syntax
rules. It is simply one step - an important one - in producing the nal code. The benet
of pseudo-code is that it enables the programmer to concentrate on the algorithms without
worrying about all the syntactic details of a particular programming language. In fact, you can
write pseudo-code without even knowing what programming language you will use for the nal
implementation.1
Pseudo-code is a generic way of describing an algorithm using the conventions of programming languages, without using language-specic syntax.
As the name suggests, pseudo-code generally does not actually use the syntax of any particular language; there is no systematic standard form, although any particular writer will generally
borrow the appearance of a particular language. Popular sources include ALGOL, C, and Lisp.
Details not relevant to the algorithm (such as memory management code) are usually omitted, and the programming language will be augmented with natural language where convenient
(for example, for trivial operations such as swapping two variables). Depending on the writer,
pseudo-code may therefore vary widely in style, from a near-exact imitation of a real programming language at one extreme, to a description approaching formatted prose at the other.2
A pseudo-code language is an almost formal rigorous way to express algorithms. It uses
the main construct of the current programming languages.
Example A.1 A summary and informal description of a simple pseudo-code language follows, describing the basic operations:
<pseudo_prog>
1
2
procedure <name>(<variable>, ... , <variable>);

<operation>;
Excerpt from: http://www.webopedia.com/TERM/P/pseudocode.html

Excerpt from: Wikipedia. The Free Encyclopedia
323
324
APPENDIX A. PSEUDO-CODE LANGUAGE

...
<operation>;
<name>
<character>
<variable>
<operation>
<expression>
:
:
:
:
:
<value>
<digit>
<binary_op>
<unary_op>
<cond_op>
:
:
:
:
:
<condition>
:
<cond>
:
<iterative_op> :
<input_op>
<output_op>
<item>
<message>
:
:
:
:
end
<character> | <character> <name>;
a | b | c | ... | z;
<name>;
<variable> = <expression> | <cond_op> | <iterative_op>;
<variable> <binary_op> (<variable> | <value>)
|
<unary_op> (<variable> | <value>);
<digit> | <digit> <value>;
0 | 1 | 2 | ... | 9;
+ | - | * | / | and | or | xor | ... ;
not | inc | dec | compl2 | ... ;
if (<condition>)
<operation>;
...
<operation>;
else
<operation>;
...
<operation>;
endif
<variable> <cond> (<variable> | <value>)
= | < | > | =< | ... ;
loop
<operation>;
...
<operation>;
until (<condition>)
|
while (<condition>)
<operation>;
...
<operation>;
repeat
|
forever <operation>;
...
<operation>;
endforever
input(<variable>, ... <variable>);
print(<variable>, ... <variable>) | <message>;
<variable> | <message> | <<item> <variable>>
"...";
Appendix B
Boolean functions
Searching the truth, dealing with numbers and behaving automatically are all based on logic.
Starting from the very elementary level we will see that logic can be interpreted arithmetically.
We intend to oer a physical support for both the numerical functions and logical mechanisms.
The logic circuit is the fundamental brick used to build the physical computational structures.
B.1
Short History
There are some signicant historical steps on the way from logic to numerical circuits. In the following
some of them are pointed.
Aristotle of Stagira (382-322) a Greek philosopher considered as founder for many scientic domains. Among them logics. All his writings in logic are grouped under the name Organon, that means
instrument of scientic investigation. He worked with two logic values: true and false.
George Boole (1815-1864) is an English mathematician who formalized the Aristotelian logic like an
algebra. The algebraic logic he proposed in 1854, now called Boolean logic, deals with the truth and the
false of complex expressions of binary variables.
Claude Elwood Shannon (1916-2001) obtained a master degree in electrical engineering and PhD
in mathematics at MIT. His Masters thesis, A Symbolic Analysis of Relay and Switching Circuits [Shannon 38], used Boolean logic to establish a theoretical background of digital circuits.
B.2
Elementary circuits: gates
Denition B.1 A binary variable takes values in the set {0, 1}. We call it bit.
The set of numbers {0, 1} is interpreted in logic using the correspondences: 0 f alse, 1
true in what is called positive logic, or 1 f alse, 0 true in what is called negative logic. In
the following we use positive logic.
Denition B.2 We call n-bit binary variable an element of the set {0, 1}n .
Denition B.3 A logic function is a function having the form f : {0, 1}n {0, 1}m with n 0
and m > 0.
In the following we will deal with m = 1. The parallel composition will provide the possibility
to build systems with m > 1.
325
326
APPENDIX B. BOOLEAN FUNCTIONS
B.2.1
Zero-input logic circuits
Denition B.4 The 0-bit logic function are f00 = 0 (the false-function) which generates the
one bit coded 0, and f10 = 1 (the true-function) which generate the one bit coded 1.
They are useful for generating initial values in computation (see the zero function as basic
function in partial recursivity).
B.2.2
One input logic circuits
Denition B.5 The 1-bit logic functions, represented by true-tables in Figure B.1, are:
f01 (x) = 0 the false function
f11 (x) = x the invert (not) function
f21 (x) = x the driver or identity function
f31 (x) = 1 the true function
x
0
1
f01
0
0
f11
1
0
f21
0
1
f31
1
1
a.
1 = VDD
x
b.
c.
x
d.
e.
Figure B.1: One-bit logic functions. a. The truth table for 1-variable logic functions. b. The
circuit for 0 (false) by connecting to the ground potential. c. The logic symbol for the inverter circuit.
d. The logic symbol for driver function. e. The circuit for 1 (true) by connecting to the high potential.
Numerical interpretation of the NOT circuit: one-bit incrementer. Indeed, the output
represents the modulo 2 increment of the inputs.
B.2.3
Two inputs logic circuits
Denition B.6 The 2-bit logic functions are represented by true-tables in Figure B.2.
Interpretations for some of 2-input logic circuits:
f82 : AND function is:
a multiplier for 1-bit numbers
a gate, because x opens the gate for y:
if (x = 1) output = y; else output = 0;
f62 : XOR (exclusiv OR) is:
the 2-modulo adder
NEQ (not-equal) circuit, a comparator pointing out when the two 1-bit numbers on
the input are inequal
an enabled inverter:
if x = 1 output is y ; else output is y;
B.3. HOW TO DEAL WITH LOGIC FUNCTIONS

x
0
0
1
1
y
0
1
0
1
f02
0
0
0
0
f12
1
0
0
0
f22
0
1
0
0
f32
1
1
0
0
f42
0
0
1
0
f52
1
0
1
0
f62
0
1
1
0
f72
1
1
1
0
f82
0
0
0
1
327
f92
1
0
0
1
2
fA
0
1
0
1
2
fB
1
1
0
1
2
fC
0
0
1
1
2
fD
1
0
1
1
2
fE
0
1
1
1
2
fF
1
1
1
1
a.
x
f82 = xy
f72 = (xy)
y
c.
b.
x
2
fE
=x+y
f12 = (x + y)
y
e.
d.
x
f62 = x y
f92 = (x y)
y
f.
g.
Figure B.2: Two-bit logic functions. a. The table of all two-bit logic functions. b. AND gate
the original gate. c. NAND gate the most used gate. d. OR gate. e. NOR gate. f. XOR gate
modulo2 adder. g. NXOR gate coincidence circuit.
a modulo 2 incrementer.
fB2 : the logic implication is also used to compare 1-bit numbers because the output is 1
for y < x
f12 : NOR function detects when 2-bit numbers have the value zero.
All logic circuits are gates, even if a true gate is only the AND gate.
B.2.4
Many input logic circuits
For enumerating the 3-input function a table with 8 line is needed. On the left side there are 3
columns and on the right side 256 columns (one for each 8-bit binary conguration dening a
logic function).
n
Theorem B.1 The number of n-input one output logic (Boolean) functions is N = 22 .
Enumerating is not a solution starting with n = 3. Maybe the 3-input function can be
dened using the 2-input functions.
B.3
How to Deal with Logic Functions
The systematic and formal development of the theory of logical functions means: (1) a set of
elementary functions, (2) a minimal set of axioms (of formulas considered true), and (3) some
rule of deduction.
Because our approach is a pragmatic one: (1) we use an extended (non-minimal) set of
elementary functions containing: NOT, AND, OR, XOR (a minimal one contains only NAND,
or only NOR), and (2) we will list a set of useful principles, i.e., a set of equivalences.
Identity principle Even if the natural tendency of existence is becoming, we stone the value
a to be identical with itself: a = a. Here is one of the fundamental limits of digital systems and
of computation based on them.
328
Double negation principle The negation is a reversible function, i.e., if we know the
output we can deduce the input (it is a very rare, somehow unique, feature in the world of
logical function): (a ) ) = a. Actually, we can not found the reversibility in existence. There are
logics that dont accept this principle (see the intuitionist logic of Heyting & Brower).
Associativity Having 2-input gates, how can be built gates with much more inputs? For
some functions the associativity helps us.
a + (b + c) = (a + b) + c = a + b + c
a(bc) = (ab)c = abc
a (b c) = (a b) c = a b c.
Commutativity
in any order.
a+b=b+a
ab = ba
ab=ba
Commutativity allows us to connect to the inputs of some gates the variable
Distributivity Distributivity oers the possibility to dene all logical functions as sum of
products or as product of sums.
a(b + c) = ab + ac
a + bc = (a + b)(a + c)
a(b c) = ab ac.
Not all distributions are possible. For example:
a bc = (a b)(b c).
The table in Figure B.3 can be used to prove the previous inequality.
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
bc
0
0
0
1
0
0
0
1
a bc
0
0
0
1
1
1
1
0
ab
0
0
1
1
1
1
0
0
ac
0
1
0
1
1
0
1
0
(ab)(ac)
0
0
0
1
1
0
0
0
Figure B.3: Proving by tables. Proof of inequality a bc = (a b)(b c).
Absorbtion Absorbtion simplify the logic expression.

a + a = 1
a+a=a
aa = 0
aa = a
a + ab = a
a(a + b) = a
Tertium non datur: a + a = 1.
B.4. MINIMIZING BOOLEAN FUNCTIONS

Half-absorbtion
tion.
a + a b = a + b
a(a + b) = ab.
Substitution
with a value.
a+0=a
a+1=1
a0 = 0
a1 = a
a0=a
a 1 = a .
329
The half-absorbtion allows only a smaller, but non-neglecting, simplica-
The substitution principles say us what happen when a variable is substituted
Exclusion The most powerful simplication occurs when the exclusion principle is applicable.
ab + a b = b
(a + b)(a + b) = b.
Proof. For the rst form:
ab + a b = b
applying successively distribution, absorbtion and substitution results:
ab + a b = b(a + a ) = b1 = b.
For the second form we have the following sequence:
(a + b)(a + b) = (a + b)a + (a + b)b = aa + a b + ab + bb =
0 + (a b + ab + b) = a b + ab + b = a b + b = b.
De Morgan laws Some times we are interested to use inverting gates instead of non-inverting
gates, or conversely. De Morgan laws will help us.
a + b = (a b )
ab = (a + b )
a + b = (ab)
a b = (a + b)
B.4
Minimizing Boolean functions
Minimizing logic functions is the rst operation to be done after dening a logical function.
Minimizing a logical function means to express it in the simplest form (with minimal symbols).
To a simple form a small associated circuit is expected. The minimization process starts from
canonical forms.
B.4.1
Canonical forms
The initial denition of a logic function is usually expressed in a canonical form. The canonical
form is given by a truth table or by the rough expression extracted from it.
330
Denition B.7 A minterm associated to an n-input logic function is a logic product (AND
logic function) depending by all n binary variable.
Denition B.8 A maxterm associated to an n-input logic function is a logic sum (OR logic
function) depending by all n binary variable.
Denition B.9 The disjunctive normal form, DNF, of an n-input logic function is a logic
sum of minterms.
Denition B.10 The conjunctive normal form, CNF, of an n-input logic function is a logic
product of maxterms.
Example B.1 Let be the combinational multiplier for 2 2-bit numbers described in Figure B.4.
One number is the 2-bit number {a, b} and the other is {c, d}. The result is the 4-bit number
{p3, p2, p1, p0}. The logic equations result direct as 4 DNFs, one for each output bit:
p3 = abcd
p2 = abcd + abcd + abcd
p1 = abcd + abcd + abcd + abcd + abcd + abcd
p0 = a bc d + a bcd + abc d + abcd.
Indeed, the p3 bit takes the value 1 only if a = 1 and b = 1 and c = 1 and d = 1. The bit p2
is 1 only one of the following three 4-input ADNs takes the value 1: ab cd , ab cd, abcd . And so
on for the other bits.
Applying the De Morgan rule the equations become: p3 = ((abcd) )
p2 = ((ab cd ) (ab cd) (abcd ) )
p1 = ((a bcd ) (a bcd (ab c d) (ab cd) (abc d) (abcd ) )
p0 = ((a bc d) (a bcd) (abc d) (abcd) ) .
These forms are more ecient in implementation because involve the same type of circuits
(NANDs), and because the inverting circuits are usually faster.
ab
cd
p3
p2
p1
p0
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
Figure B.4: Combinatinal circuit represented a a truth table. The truth table of the
combinational circuit performing 2-bit multiplication.
The resulting circuit is represented in Figure B.5. It consists in two layers of ADNs. The
rst layer computes only minterms and the second adds the minterms thus computing the 4
outputs.
The logic depth of the circuit is 2. But in real implementation it can be bigger because of the
fact that big input gates are composed from smaller ones. Maybe a real implementation has the
depth 3. The propagation time is also inuenced by the number of inputs and by the fan-out of
the circuits.
The size of the resulting circuit is very big also: Smult2 = 54.
331
a
b
c
d
p3
p2
p1
p0
Figure B.5: Direct implementation of a combinational circuit. The direct implementation

starting from DNF of the 2-bit multiplier.
B.4.2
Algebraic minimization
Minimal depth minimization

Example B.2 Lets revisit the previous example for minimizing independently each function.
The least signicant output has the following form:
p0 = a bc d + a bcd + abc d + abcd.
We will apply the following steps:
p0 = (a bd)c + (a bd)c + (abd)c + (abd)c
to emphasize the possibility of applying twice the exclusion principle, resulting
p0 = a bd + abd.
Applying again the same principle results:
p0 = bd(a + a) = bd1 = bd.
The exclusion principle allowed us to reduce the size of the circuit from 22 to 2.
We continue with the next output:
p1 = a bcd + a bcd + ab c d + ab cd + abc d + abcd =
= a bc(d + d) + ab d(c + c) + abc d + abcd =
= a bc + ab d + abc d + abcd =
= bc(a + ad ) + ad(b + bc ) =
= bc(a + d ) + ad(b + c ) =
= a bc + bcd + ab d + ac d.
Now we used also the half-absorbtion principle reducing the size from 28 to 16.
Follows the minimization of p2:
p2 = ab cd + ab cd + abcd =
332
= ab c + abcd =
= ab c + acd
The p3 output can not be minimized. De Morgan law is used to transform the expressions to be
implemented with NANDs.
p3 = ((abcd) )
p2 = ((ab c) (acd ) )
p1 = ((a bc) (bcd ) (ab d) (ac d) )
p1 = ((abcd) ) .
Results the circuit from Figure B.6.
a
b
c
d
p3
p2
p1
p0
Figure B.6: Minimal depth minimiztion The rst, minimal depth minimization of the 2-bit
multiplier.
Multi-level minimization
Example B.3 The same circuit for multiplying 2-bit numbers is used to exemplify the multilevel
minimization. Results:
p3 = abcd
p2 = ab c + acd = ac(b + d ) = ac(bd)
p1 = a bc + bcd + ab d + ac d = bc(a + d ) + ad(b + c ) = bc(ad) + ad(bc) = (bc) (ad)
p0 = bd.
Using for XOR the following form:
x y = ((x y) ) = (xy + x y ) = (xy) (x y ) = (xy) (x + y)
results the circuit from Figure B.7 with size 22.
Many output circuit minimization

Example B.4 Inspecting carefully the schematics from Figure B.7 results: (1) the output p3
can be obtained inverting the NANDs output from the circuit of p2, (2) the output p0 is computed
by a part of the circuit used for p2. Thus, we are encouraged to rewrite same of the functions
in order to maximize the common circuits used in implementation. Results:
x y = (xy) (x + y) = ((xy) + (x + y) ) .
333
a
b
c
d
p3
p1
p2
p0
Figure B.7: Multi-level minimization. The second, multi-level minimization of the 2-bit multiplier.
p2 = ac(bd) = ((ac) + bd)
allowing the simplied circuit from Figure B.8. The size is 16 and the depth is 3. But, more
important: (1) the circuits contains only 2-input gates and (2) the maximum fan-out is 2. Both
last characteristics led to small area and high speed.
a
b
c
d
p3
p1
p2
p0
Figure B.8: Multiple-output minimization. The third, multiple-output minimization of the 2-bit
multiplier.
B.4.3
Veitch-Karnaugh diagrams
In order to apply eciently the exclusion principle we need to group carefully the minterms.
Two dimension diagrams allow to emphasize the best grouping. Formally, the two minterms are
adjacent if the Hamming distance in minimal.
Denition B.11 The Hamming distance between two minterms is given by the total numbers
of binary variable which occur distinct in the two minterms.
Example B.5 The Hamming distance between m9 = ab c d and m4 = a bc d is 3, because only
the variable b occurs in the same form in both minterms.
The Hamming distance between m9 = ab c d and m1 = a b c d is 1, because only the variable
which occurs distinct in the two minterms is a.
Two n-variable terms having the Hamming distance 1 are minimized, using the exclusion
principle, to one (n 1)-variable term. The size of the associated circuit is reduced from 2(n + 1)
to n 1.
A n-input Veitch diagram is a two dimensioned surface containing 2n squares, one for each
n-value minterm. The adjacent minterms (minterms having the Hamming distance equal with
334
1) are placed in adjacent squares. In Figure B.9 are presented the Veitch diagrams for 2, 3
and 4-variable logic functions. For example, the 4-input diagram contains in the left half all
minterms true for a = 1, in the upper half all minterms true for b = 1, in the two middle columns
all the minterms true for c = 1, and in the two middle lines all the minterms true for d = 1.
Results the lateral columns are adjacent and the lateral line are also adjacent. Actually the
surface can be seen as a toroid.
a
a
b
m3
m1
m2
m0
m6
m7
m3
m2
m4
m5
m1
m0
m4
m13 m15 m7
m5
m9 m11 m3
m1
m8 m10 m2
m0
a.
m12 m14 m6
b
c.
b.
Figure B.9: Veitch diagrams. The Veitch diagrams for 2, 3, and 4 variables.
Example B.6 Let be the function p1 and p2, two outputs of the 2-bit multiplier. Rewriting
them using minterms results::
p1 = m6 + m7 + m9 + m11 + m13 + m14
p2 = m10 + m11 + m14 .
In Figure B.10 p1 and p2 are represented.
a
1
b
1
1
d
1
1
p1
c
a.
p2
c
b.
Figure B.10: Using Veitch diagrams. The Veitch diagrams for the functions p1 and p2.
The Karnaugh diagrams have the same property. The only dierence is the way in which the
minterms are assigned to squares. For example, in a 4-input Karnaugh diagram each column is
associated to a pair of input variable and each line is associated with a pair containing the other
variables. The columns are numbered in Gray sequence (successive binary congurations are
adjacent). The rst column contains all minterms true for ab = 00, the second column contains
all minterms true for ab = 01, the third column contains all minterms true for ab = 11, the last
column contains all minterms true for ab = 10. A similar association is made for lines. The
Gray numbering provides a similar adjacency as in Veitch diagrams.
In Figure B.12 the same functions, p1 and p2, are represented. The distribution of the
surface is dierent but the degree of adjacency is identical.
In the following we will use Veitch diagrams, but we will name the them V-K diagrams to
be fair with both Veitch and Karnaugh.
335
ab
cd
00
01
11
10
ab
00
01
11
10
00
m0
m1
m3
m2
m0
m1
m3
m2
01
m4
m5
m7
m6
m4
m5
m7
m6
11
m12 m13 m15 m14
10
m8
m9 m11 m10
Figure B.11: Karnaugh diagrams. The Karnaugh diagrams for 3 and 4 variables.
ab
ab
00
cd
01
11
10
00
cd
00
01
11
10
00
01
11
10
01
11
p1
10
1
1
p2
Figure B.12: Using Karnaugh diagrams. The Karnaugh diagrams for the functions p1 and p2.
Minimizing with V-K diagrams
The rule to extract the minimized form of a function from a V-K diagram supposes:
to dene:
the smallest number
of rectangular surfaces containing only 1s
including all the 1s
each surface having a maximal area
and containing a power of two number of 1s
to extract the logic terms (logic product of Boolean variables) associated with each previously emphasized surface
to provide de minimized function adding logically (logical OR function) the terms associated with the surfaces.
Example B.7 Lets take the V-K diagrams from Figure B.10. In the V-K diagram for p1 there
are four 2-square surfaces. The upper horizontal surface is included in the upper half of V-K
diagram where b = 1, it is also included in the two middle columns where c = 1 and it is included
in the surface formed by the two horizontal edges of the diagram where d = 0. Therefore, the
associated term is bcd which is true for: (b = 1)AN D(c = 1)AN D(d = 0).
Because the horizontal edges are considered adjacent, in the V-K diagram for p2 m14 and
m10 are adjacent forming a surface having acd as associated term.
The previously known form of p1 and p2 result if the terms resulting from the two diagrams
are logically added.
336

bcd
a
-1
ac d
acd
a bc
b
d
-1
ab c
ab d
c
p1
/c
p2
a.
b.
Figure B.13: Minimizing with V-K diagrams. Minimizing the functions p1 and p2.
Minimizing incomplete dened functions

There are logic functions incompletely dened, which means for some binary input congurations
the output value does not matter. For example, the designer knows that some inputs do not
occur anytime. This lack in denition can be used to make an advanced minimization. In the
V-K diagrams the corresponding minterms are marked as dont cares with -. When the
surfaces are maximized the dont cares can be used to increase the area of 1s. Thus, some
dont cares will take the value 1 (those which are included in the surfaces of 1s) and some of
dont cares will take the value 0 (those which are not included in the surfaces of 1s).
a b
a
1
b
1
1
1
a c
a.
b.
Figure B.14: Minimizing incomplete dened functions. a. The minimization of y (Example

1.8) ignoring the dont care terms. b. The minimization of y (Example 1.8) considering the dont
care terms.
Example B.8 Let be the 4-input circuit receiving the binary codded decimals (from 0000 to
1001) indicating on its output if the received number is contained in the interval [2, 7]. It is
supposed the binary congurations from 1010 to 1111 are not applied on the input of the circuit.
If by hazard the circuit receives a meaningless input we do not care about the value generated by
the circuit on its output.
In Figure B.14a the V-K diagram is presented for the version ignoring the dont cares.
Results the function: y = a b + a c = a (b + c).
If dont cares are considered results the V-K diagram from Figure B.14b. Now each of the
two surfaces are doubled resulting a more simplied form: y = b + c.
B.5. PROBLEMS
337
V-K diagrams with included functions

For various reasons in a V-K diagram we need to include instead of a logic value, 0 or 1, a logic
function of variables which are dierent from the variables associated with the V-K diagram. For
example, a minterm depending on a, b, c, d can be dened as taking a value which is depending
on another logic 2-variable function by s, t.
A simplied rule to extract the minimized form of a function from a V-K diagram containing
included functions is the following:
1. consider rst only the 1s from the diagram and the rest of the diagram led only with 0s
and extract the resulting function
2. consider the 1s as dont cares for surfaces containing the same function and extract the
resulting function multiplying the terms with the function
3. add the two functions.
abc
bcd
a
b
1
a.
d
e
b
e
cde
1
1
acde
a
c
bc
d
e
c.
Figure B.15: An example of V-K diagram with included functions. a. The initial form.
b. The form considered in the rst step. c. The form considered in the second step.
Example B.9 Let be the function dened in Figure B.15a. The rst step means to dene the
surfaces of 1s ignoring the squares containing functions. In Figure B.15b are dened 3 surfaces
which provide the rst form depending only by the variables a, b, c, d:
bc d + a bc + b c
The second step is based on the diagram represented in Figure B.15c, where a surface (c d)
is dened for the function e and a smaller one (acd) for the function e. Results:
c de + acde
In the third step the two forms are added resulting:
f (a, b, c, d, e) = bc d + a bc + b c + c de + acde.
Sometimes, an additional algebraic minimization is needed. But, it deserves because including functions in V-K diagrams is a way to expand the number of variable of the functions
represented with a manageable V-K diagram.
B.5
Problems
Problem B.1
338
Appendix C
Basic circuits
Basic CMOS circuits implementing the main logic gates are described in this appendix. They
are based on simple switching circuits realized using MOS transistors. The inverting circuit
consists in a pair of two complementary transistors (see the third section). The main gates
described are the NAND gate and the NOR gate. They are built by appropriately connecting
two pairs of complementary MOS transistors (see the fourth section). Tristate buers generate
an additional, third state (the Hi-Z state) to the output of a logic circuit, when the output
pair of complementary MOS transistors are driven by appropriate signals (see the sixth section).
Parallel connecting a pair of complementary MOS transistors provides the transmission gate (see
the seventh section).
C.1
Actual digital signals
The ideal logic signals are 0 Volts for false, or 0, and VDD for true, or 1. Real signals are more
complex. The rst step in dening real parameters is represented in Figure C.1, where is dened
the boundary between the values interpreted as 0 and the values interpreted as 1.
VDD
v
6
6
Valid 1
1
2.5V
?
6
VHmin = VLmax
VDD /2
Valid 0
time
Figure C.1: Dening 0-logic and 1-logic. The circuit is supposed to interpret any value under
VDD /2 as 0, and any value bigger than VDD /2 are interpreted as 1.
This rst denition is impossible to be applied because supposes:

VHmin = VLmax .
There is no engineering method to apply the previous relation. A practical solution supposes:
VHmin > VLmax
generating a forbidden region for any actual logic signal. Results a more rened denition of
the logic signals represented in Figure C.2, where VL < VLmax and VH > VHmin .
339
340
APPENDIX C. BASIC CIRCUITS
VDD
v
Valid 1
Forbidden
region
VHmin
VLmax
VHmin
VLmax
Valid 0
time
Figure C.2: Dening the forbidden region for logic values. A robust design asks a net
distinction between the electrical values interpreted as 0 and the electrical values interpreted as 1.
In real applications weare faced with nasty realities. A signal generated to the output of a
gate is sometimes received to the input of the receiving gate distorted by parasitic signals. In
Figure C.3 the noise generator simulate the parasitic eects of the circuits switching in a small
neighborhood.
+
Receiver
Sender
gate
gate
noise generator
VDD
v
VOH
Valid 1
VOH
1 noise
margin
VIH
Forbidden
region
VIL
VOL
0 noise
margin
time
VIH
VIL
VOL
Valid 0
0
Figure C.3: The noise margin. The output signal must be generated with more restrictions to allow
the receivers to understand correct input signals loaded with noise.
Because of the noise captured from the environment a noise margin must be added to
expand the forbidden region with two noise margin regions, one for 0 level, N M0 , and another
for 1 level, N M1 . They are dened as follows:
N M0 = VIL VOL
N M1 = VOH VIH
making the necessary distinctions between the VOH , the 1 at the output of the sender gate, and
VIH , the 1 at the input of the receiver gate.
C.2. CMOS SWITCHES
C.2
341
CMOS switches
A logic gates consists in a network of interconnected switches implemented using the two type
of MOS transistors: p-MOS and n-MOS. How behaves the two type of transistors in specic
congurations is presented in Figure C.4.
A switch connected to VDD is implemented using a p-MOS transistor. It is represented in
Figure C.4a o (generating z, which means Hi-Z: no signal, neither 0, nor 1) and in Figure C.4b
it is represented on (generating 1 logic, or truth).
A switch connected to ground is implemented using a n-MOS transistor. It is represented in
Figure C.4c o (generating z, which means Hi-Z: no signal, neither 0, nor 1) and in Figure C.4e
it is represented on (generating 0 logic, or false).
VDD
VDD
z
VDD
VDD
VDD
z
VDD

z
a.
VDD
c.
b.
d.
Figure C.4: Basic switches. a. Open switch connected to VDD . b. Closed switch connected to VDD .
c. Open switch connected to ground. d. Closed switch connected to ground.
A MOS transistor works very well as an on-o switch connecting its drain to a certain
potential. A p-MOS transistor can be used to connect its drain to a high potential when its
gates is connected to ground, and an n-MOS transistor can connect its drain to ground if its gates
is connected to a high potential. This complementary behavior is used to build the elementary
logic circuits.
In Figure C.5 is presented the switch-resistor-capacitor model (SRC). If VGS < VT then the
transistor is o, if VGS VT then the transistor is on. In both cases the input of the transistor
behaves like a capacitor, the gate-source capacitor CGS .
When the transistor is on its drain-source resistance is:
RON = Rn
L
W
where: L is the channel length, W is the channel width, and Rn is the resistance per square.
The length L is a constant characterizing a certain technology. For example, if L = 0.13m this
means it is about a 0.13m process.
The input capacitor has the value:
CGS =
OX LW
.
d
The value:
COX =
OX
d
342
where: OX 3.90 is the permittivity of the silicon dioxide, is the gate-to-channel capacitance
per unit area of the MOSFET gate.
In this conditions the gate input current is:
iG = CGS
dvGS
dt
RON
CGS
CGS
S
VGS VT
VGS < VT
Figure C.5: The MOSFET switch. The switch-resistor-capacitor model consists in the two states:
OF (VGS < VT ), and ON (VGS VT ). In both states the input is dened by the capacitor CGS .
Example C.1 For an AND gate with low strength, with W = 1.8m, in 0.13m technology,
supposing COX = 4f F/m2 , results the input capacitance:
CGS = 4 0.13 1.8f F = 0.936f F
Assuming Rn = 5K, results for the same gate:
RON = 5
0.13
K = 361
1.8
C.3
C.3.1
The Inverter
The static behavior
The smallest and simplest logic circuit the invertor can be built using a pair of complementary
transistors, connecting together the two gates as input and the two drains as output, while the
n-MOS source is connected to ground (interpreted as logic 0) and the p-MOS source to VDD
(interpreted as logic 1). Results the circuit represented in Figure C.6.
The behavior of the invertor consist in combining the behaviors of the two switches previously
dened. For in = 0 pMOS is on and nMOS is of f the output generating VDD which means 1.
For in = 1 pMOS is of f and nMOS is on the output generating 0.
The static behavior of the inverter (or NOT) circuit can be easy explained starting from
the switches described in Figure C.4. Connecting together a switch generating z with a switch
generating 1 or 0, the connection point will generate 0 or 1.
C.3. THE INVERTER
343
VDD

A
a.
b.
Figure C.6: Building an invertor. a. The invertor circuit. b. The logic symbol for the invertor
circuit.
C.3.2
Dynamic behavior
The propagation time of an inverter can be analyzed using the two serially connected invertors
represented in Figure C.7. The delay of the rst invertor is generated by its capacitive load,
CL , composed by the wires connecting its output to the input of the next invertor and the CGS
input capacitor of the same invertor.
VA
time
i(t)
RON
v(t)
VB
VOH
+
VDD
CL
VOL
-
tpLH
- time
tpHL
Figure C.7: The propagation time.

The two delay times (see Figure C.7) associated to an invertor (to a gate in the general case)
are:
tpLH : the time interval between the moment the input switches in 0 and the output reaches
VIH , the level interpreted by the receiver as 1
tpHL : the time interval between the moment the input switches in 1 and the output reaches
VIL , the level interpreted by the receiver as 0
In order to compute tp we consider the equivalent circuit modelling the connection between
the two invertors. It contains RON of the rst invertor and CL associated to the wire and CGS
of the second invertor. Because the current i(t) is the same in RON and CGS we write:
VDD v
dv
= CL
RON
dt
344
resulting the following dierential equation:

RON CL
dv
+ v = VDD
dt
having the solution:

v(t) = VDD + Ke
t
ON CL
The constant K results from the initial condition:

v(0) = 0
if we intend to compute tpLH . Results:
K = VDD
The nal condition:
v(tp ) = VH
gives us the condition for computing
tpLH = RON CL ln(
VDD VH
)
VDD
Similar, tpHL is computed.1

The speed of a gate depends by its dimension and by the capacitive load it drives. For a big
W the value of RON is small charging or discharging CL faster.
C.3.3
Buering
It is usual to be confronted in designing a big system with the buering problem: a logic signal
(generated by a weak driver) must be used to drive a high value capacitor, CL (see Figure
C.8a) maintaining in the same time a high clock frequency. The rst step is to use a big invertor
(with a big W ) to drive CL (see Figure C.8b). But the resulting big invertor can not be driven
at a high speed because of its input capacitance is big (its W is too large compared with the
width of the small driver). In Figure C.8a is represented the resulting circuit: a big and strong
invertor, used to drive a big load, driven by a small and weak driver. How can be solved this
problem? The simplest solution is to use an intermediary invertor as buer (see Figure C.8c).
The problem is: how must be dimensioned the intermediary buer in order to reduce the total
propagation time of the circuit?
Lets consider the circuit from Figure C.8c, where, for both n-MOS and p-MOS transistors
the width are related as follows:
Wbig
W
=
=n
W
Wsmall
and Wp Wn allowing RON n RON p . What is the resulting improvement of the propagation
time for the buered solution? For the circuit from Figure C.8b the propagation time associated
to the driver is:
L
VDD VH
tsmall = Rn COX (L + 2L)n2 W ln(
)
W
VDD
1
The general form to be used is:

vC = initial value e time
t
constant
+ f inal value(1 e time
t
constant
).
C.3. THE INVERTER
345
For a certain process we can write:

tsmall = n2
where:
= Rn
L
VDD VH
COX (L + 2L)W ln(
)
W
VDD
is a constant.
Wbig >> Wsmall
Wsmall
CL
a.
Wbig >> Wsmall
Wsmall
Wsmall
W =?!
CL
CL
c.
b.
Figure C.8: Buered connection. a. An invertor with small W is not able to handle at high
frequency the big capacitor CL . b. The big invertor is added to drive the big CL , but it has a big W
imposing its big CGS as load for a too weak circuit. c. The buered connection with an intermediary
dimensioned buer.
For the circuit from Figure C.8c the propagation time associated to the rst two invertors
(we suppose VT and RON are the same for both n-MOS transistor and p-MOS transistor) is:
tbuf f ered = 2n.
Results the speed of the buered solution is increased by the factor:
tsmall
tbuf f ered
n
.
2
It is very easy to prove that the previous solution, to design the buer with an equidistant
area from the area of the driver and of the receiver, is optimal.
C.3.4
Power dissipation
The average power dissipated is the energy dissipated in a clock cycle divided by the clock cycle
time, T . Suppose the clock is applied to the input of an invertor. When clock = 0 the load
capacitor is loaded from the power supply with the charge:
QL = CL VDD
We assume in T /2 the capacitor is charged (else the frequency is too big for the investigated
circuit). When clock = 1 the same charge is transferred from the capacitor to ground. Therefore,
the charge QL is transferred from VDD to ground in the time T . The amount of energy used for
this transfer is VDD QL , and the dynamic power results:
pdyn =
VDD CL VDD
2
= CL VDD
fclock
T
There are two additional power consuming processes. One is due to the no-zero edge transition which allows a direct current through both transistors for a short period of time (see Figure
C.10). The second is generated by the leakage current. It will start to be very important in sub
65nm technologies.
346

VDD
RON p
vout
i
vout
CL
RON n
CL
Figure C.9: The main power consuming process. For VIN = 0 CL is loaded by the current
provided by RON p . The charge from CL is transferred to the ground by through RON n .
VIN
time
IDD
time
Figure C.10: Direct frow of current from VDD to ground. This current due to the non-zero
edge to the circuit input can be neglected.
C.4
NAND & NOR gates
For 2-input NAND and 2-input NOR gates the same principle will be applied, interconnecting
2 pairs of complementary transistors to obtain the needed behaviors.
There are two kind of interconnecting rules for the same type of transistors, p-MOS or
n-MOS. They can be interconnected serially or parallel.
A serial connection will establish an on conguration only if both transistors of the same
type are on, and the connection is o if at least one transistor is o.
A parallel connection will establish an on conguration if at least one is on, and the connection is o only if both are o.
Applying the previous rules result the circuits presented in Figures C.11 and C.12.
For the NAND gate the output is 0 if both n-MOS transistors are on, and the output is one
when at least on p-MOS transistor is on. Indeed, if A = B = 1 both n transistors are on and
both p transistors are o. The output corresponds with the denition, it is 0. If A = 0 or B = 0
the output is 1, because at least one p transistor is on and at least one n transistor is o.
A similar explanation works for the NOR gate. The main idea is to design a gate so as to
avoid the simultaneous connection of VDD and ground potential to the output of the gate.
How can be built 3-input NAND or a 3-input NOR? applying the same rule. For a 3-input
NAND 3 n-MOS transistors will be connected serially and 3 p-MOS transistors will be connected
parallel. Similar for the 3-input NOR gate.
How much this rule can be applied to built n-input gates? Not too much because of the
propagation time which is increased when too many serially connected RON resistors will be
C.4. NAND & NOR GATES
347
VDD
(AB)
(AB)
a.
b.
Figure C.11: The NAND gate. a. The internal structure of a NAND gate. b. The logic symbol
for NAND.
VDD

A
(A+B)
(A+B)
a.
b.
Figure C.12: The NOR gate. a. The internal structure of a NOR gate. b. The logic symbol for
NOR.
348
VDD
A
B
B
- (AB + CD)
(AB + CD)
C
C
D
b.
B
a.
Figure C.13: The AND-NOR gate. a. The circuit. b. The logic symbol for the AND-NOR gate.
used to transfer the electrical charge in or out from the load capacitor CL .
For example, an 8-input NAND gate is recommended to be designed as a binary tree of two
input gates, as follows:
(a b c d e f g h) = (((a b) + (c d) ) ((e f ) + (g h) ) )
For designing an AND or an OR gate we will use an additional NOT. The area will be a little
bigger, but the strength of the circuit will be more increased because the NOR circuit works as
a buer improving the time performance of the non-inverting gate.
C.5
AND-NOR gates
For implementing the logic function:

(AB + CD)
besides the solution of composing it from the previously described circuits, there is a direct
solution using 4 CMOS pairs of transistors, one associated for each input. The resulting circuit
is represented in Figure C.13.
The size of the circuit according to Denition 2.2 is 4. (Implementing the function using
2 NANDs, 2 invertors, and a NOR provides the size 8. Even if the de Morgan rule is applied
results 3 NANDs and and invertor, which means the size is 7.)
The same rule can be applied for implementing any NOR of ANDs. The price will be the
limited speed or the over-dimensioned transistors.
C.6. MANY-INPUT GATES
349
..
.. Cin
.
..
..
.
..
.. Cin
.
..
..
.
..
.. n Cin
.
..
..
.
..
.. Cin
.
..
..
.
..
.. Cin
.
..
..
.
a.
..
.. Cin
.
..
..
.
..
.. n Cin
.
..
..
.
..
.. Cin
.
..
..
.
b.
Figure C.14: How to manage a many-input gate. a An N AN D8 gate with fan-out n. b. The
log-depth equivalent circuit.
C.6
Many-Input Gates
There are two ways to increase the number of inputs of a certain gate. Building a gate having
an increased number of inputs using the same principle, or composing the function using an
appropriate number of 2-input gates organized as a balanced binary tree.
In the rst case, for example, a three-input NAND uses a similar arrangement as in Figure
C.11a, where instead of two parallel connected pMOS transistors and two serially connected
nMOS transistors are used 3 pMOSs and 3 nMOSs. Generally speaking, for each new input an
additional pair, nMOS & pMOS, is added.
Increasing in this way the number of inputs the propagation time is increased linearly because
of the serially connected channels of the nMOS transistors. The load capacitor is discharged to
the ground through m RON , where m represents the number of inputs.
The second solution is to build a balanced tree of gates. In the rst case the propagation
time is in O(n), while in the second is in O(log n) for implementations using transistors having
the same size.
For an m-input gate results a log2 m depth network of 2-input gates. For example, see Figure
C.14, where an 8-input NAND is implemented using a 3-level network of gates (rst to the 8input gate the divide & impera principle is applied, and then the De Morgan rule transformed
the rst level of four ANDs in four NANDs and the second level of two ANDs in two NORs).
While the maximum propagation time for the 8-input NAND is 8 RON (n Cin ), where
Cin is the value of the input capacitor in a typical gate and n is the fan-out of the circuit, the
maximum propagation time for the equivalent log-depth net of gates is (2 2 RON Cin ) +
2 RON (n Cin ). For n = 3 results a 2.4 times faster circuit if the log-depth version is
adopted, while for n = 4 the acceleration is 2.67.
Generally, for fan-in equal with m and fan-out equal with n result the acceleration for the
log-depth solutions, , expressed by the formula:
=
mn
2 (n 1 + log m)
350
Example: n = 4, m = 32, = 8.
The log-depth circuit has two advantages:
the intermediary (1 + log m) stages are loaded with a constant and minimal capacitor
Cin given by only one input
only the nal stage drives the real load of the circuit n Cin but its driving capability
does not depend by fan-in.
C.7
The Tristate Buers
A tristate circuit has the output able to generate three values: 0, 1, x (which means nothing).
The output value x is unable to impose a specic value, we say the output of the circuit is
unconnected or is o.
Two versions of this kind of circuit are presented in Figures C.15 and C.16.
VDD

enable
enable
out
in
out
enable
in
a.
enable
b.
Figure C.15: Tristate inverting buer. a. The circuit. b. The logic symbol for the inverting
tristate buer.
The inverting version of the tristate buer uses one additional pair of complementary transistors to disconnect the output from any potential. If enable = 0 the CMOS transistors connected
to the output are both o. Only if enable = 1 the circuit works as an inverter.
For the non-inverting version the two additional logic gates are used to control the gates
of the two output transistors. Only if enable = 0 the two logic gates transfer the input signal
inverted to the gates of the two output transistor.
C.8
The Transmission Gate
A simple and small version of a gate is the transmission gate which works connecting directly the
signal from a source to a destination. Figure C.17a represents the CMOS version. If enable = 1
then out = in because at least on transistors is on. If in = 0 the signal is transmitted by the
n-MOS transistor, else, if in = 1 the signal is transmitted by the p-MOS transistor.
C.8. THE TRANSMISSION GATE
351
VDD
in
enable
out
in
out
enable
a.
b.
Figure C.16: Tristate non-inverting buer. a. The circuit. b. The logic symbol for the noninverting tristate buer.
en
en
6
6
out
in
out
in
6
en
en
a.
b.
en
in1
en
out
en
in0
en
c.
Figure C.17: The transmission gate. a. The complementary transmission gate. b. The logic
symbol. c. An application: the elementary inverting multiplexer.
352
The transmission gate is not a regenerative gate in contrast to the previously described gates
which were regenerative gates. A transmission gate performs a true two-direction electrical
connection, with all its goods and bad involved.
C.9
# Memory Circuits
C.9.1
Flip-ops
C.9.2
Static memory cell
C.9.3
Array of cells
C.9.4
Dynamic memory cell
Appendix D
Standard cell libraries

Modern design procedures suppose standard cell libraries containing gates, latches, ip-ops,
and many other frequently used typical modules.
D.1
Main parameters
Each component of a cell library is characterized for area, propagation time, and power1 .
Each factory has three type of processes: slow, typical, and fast. A derating factor is associated with each process:
Kprocess (typical) = 1
Kprocess (slow) = 1.3
Kprocess (f ast) = 0.8
The power supply variation introduces two derating factors, one for the negative variations
and another for the positive variation:
Kvolt (10%) = 2.1/V
Kvolt (+10%) = 1.4/V
The temperature variation introduce the last two derating factors:
Ktemp (f rom 250 C to 400 C) = 0.00090 C
Ktemp (f rom 250 C to 1250 C) = 0.00070 C
Figure D.1 represents how the propagation time, tp , is measured in combinational circuits.
Figure D.2 represent temporal relations in a clocked circuit, where the active edge of clock
is the positive edge. The frequency of clock is:
fck =
1
tckw1 + tckw0
The following parameters are dened:

set-up time : tSU because a clocked circuit must receive the input data before the active edge
of clock (the circuit must learn before what to do)
hold time : tH because the input data can not disappears immediately after the active edge
of clock (the circuit must understand rmly what to do)
1
The values used in the following are typical values for a 13m process in a good factory.
353
354
APPENDIX D. STANDARD CELL LIBRARIES
input
1
0.5
time
pLH -
pHL -
output
0.5
time
inverted output
pHL-
tpLH
0.5
time
Figure D.1: Propagation time in combinational circuits.

recovery time : tR is necessary to change the control of the circuit from the imperium of
set/reset devices to the imperium of clock (the set/reset operation is very stressful and
the circuits must recover)
propagation time : tpHL or tpLH is the response time of the output of the circuit.
clock
1
tckw1
-tckw0-
0.5
time
tSU

-tH-
data input
1
0.5
time
set or reset
1
tR
0.5
time
output
1
tpHL

-
tpLH
0.5
time
Figure D.2: Time relations in a clocked system.

The propagation time for a circuit can be estimated using the following forms:
tp = Kprocess (1 + Kvolt VDD ) (1 + Ktemp T ) ttypical
ttypical = tintrinsic + Kload Cload
where:
D.2. BASIC CELLS
355
tp propagation time in ns taking into account all derating factors

ttypical propagation time in ns at nominal VDD ,, 250 C, for typical process
tintrinsic circuit delay in ns with no loaded output
Kload load factor expressed in ns/pF
Cload output load expressed in pF .
D.2
Basic cells
A standard library contains cells having the same height. An usual value is around 3.7m. The
dierences between inputs are ignored. The power is expressed for each input pin in W/M Hz.
The tables contain mean typical values.
D.2.1
Gates
Two input AND gate: AND2

Implementation
Strength
1
2
4
: y = ((a b) )
Width(m)
1.8
1.8
2.8
tintrinsic (LH/HL)
0.053 / 0.073
0.047 / 0.069
0.044 / 0.057
Zload (LH/HL)
4.28 / 2.2
1.9 / 1.1
0.96 / 0.56
Cpin
0.0014
0.002
0.004
Power
0.0044
0.006
0.012
Zload (LH/HL)
4.2 / 2.3
1.9 / 1.25
1.1 / 0.6
Cpin
0.0015
0.0025
0.004
Power
0.004
0.006
0.01
Zload (LH/HL)
4.3 / 2.2
1.9 / 1.2
0.97 / 0.56
Cpin
0.0016
0.0023
0.0042
Power
0.0047
0.0075
0.013
Zload (LH/HL)
4.3 / 2.5
1.9 / 1.2
1 / 0.6
Cpin
0.0017
0.0028
0.0054
Power
0.005
0.008
0.015
Two input OR gate: OR2

Implementation
Strength
1
2
4
: y = ((a + b) )
Width(m)
1.8
2.3
2.8
tintrinsic (LH/HL)
0.045 / 0.095
0.04 / 0.085
0.04 / 0.075
Three input AND gate: AND3

Implementation
Strength
1
2
4
: y = ((a b c) )
Width(m)
2.3
2.3
3.2
tintrinsic (LH/HL)
0.073 / 0.090
0.061 / 0.086
0.065 / 0.067
Three input OR gate: OR3

Implementation
Strength
1
2
4
: y = ((a + b + c) )
Width(m)
2.75
2.75
3.68
tintrinsic (LH/HL)
0.05 / 0.14
0.05 / 0.1
0.045 / 0.1
356
Four input AND gate: AND4

Implementation
Strength
1
2
4
: y = ((a b c d) )
Width(m)
2.8
3.2
4.6
tintrinsic (LH/HL)
0.082 / 0.097
0.075 / 0.092
0.073 / 0.082
Zload (LH/HL)
4.3 / 2.2
1.9 / 1.1
0.97 / 0.56
Cpin
0.0017
0.0027
0.0053
Power
0.0051
0.009
0.016
Zload (LH/HL)
4.3 / 2.8
2 / 1.3
1 / 0.65
Cpin
0.002
0.003
0.006
Power
0.0055
0.009
0.016
tintrinsic (LH/HL)
0.07 / 0.14
0.065 / 0.13
0.06 / 0.1
Zload (LH/HL)
4.3 / 2.4
1.9 / 1.3
1 / 0.6
Cpin
0.0017
0.0027
0.0053
Power
0.0056
0.0094
0.016
tintrinsic (LH/HL)
0.015 / 0.014
0.014 / 0.0135
0.013 / 0.014
0.013 / 0.013
0.0125 / 0.013
Zload (LH/HL)
2.9 / 2.7
1.9 / 1.9
0.95 / 1
0.48 / 0.48
0.12 / 0.13
Cpin
0.0017
0.0027
0.0053
0.0053
0.0053
Power
0.0026
0.0037
0.0067
0.0137
0.053
tintrinsic (LH/HL)
0.027 / 0.016
0.013 / 0.025
0.013 / 0.025
Zload (LH/HL)
4.2 / 2.4
1.9 / 1.2
1 / 0.7
Cpin
0.003
0.0054
0.01
Power
0.0028
0.0053
0.0095
tintrinsic (LH/HL)
0.026 / 0.014
0.025 / 0.0135
0.023 / 0.0134
Zload (LH/HL)
6.1 / 2
3 / 1
1.5 / 0.5
Cpin
0.003
0.0054
0.01
Power
0.003
0.0055
0.01
Four input OR gate: OR4

Implementation
Strength
1
2
4
: y = ((a + b + c + d) )
Width(m)
2.8
3.2
4.6
tintrinsic (LH/HL)
0.06/ 0.17
0.05 / 0.13
0.05 / 0.12
Four input AND-OR gate: ANDOR22

Implementation
Strength
1
2
4
: y = ((a b + c d) )
Width(m)
2.8
3.2
4.2
Invertor: NOT
Implementation
Strength
1
2
4
8
16
: y = a
Width(m)
0.92
1.38
1.84
2.76
7.36
Two input NAND gate: NAND2

Implementation
Strength
1
2
4
: y = (a b)
Width(m)
1.38
2.3
3.2
Two input NOR gate: NOR2

Implementation
Strength
1
2
4
: y = (a + b)
Width(m)
1.38
2.3
3.2
D.2. BASIC CELLS
357
Three input NAND gate: NAND3

Implementation
Strength
1
2
4
: y = (a b c)
Width(m)
1.84
3.22
4.6
tintrinsic (LH/HL)
0.035 / 0.023
0.03 / 0.021
0.031 / 0.022
Zload (LH/HL)
4.25 / 2.9
2 / 1.5
1.1 / 0.85
Cpin
0.003
0.0061
0.0105
Power
0.0048
0.0086
0.015
Zload (LH/HL)
7.7 / 2.3
3.8 / 1.2
1.7 / 0.6
Cpin
0.0032
0.0063
0.0133
Power
0.0058
0.0095
0.0195
Zload (LH/HL)
4.26 / 3.4
2.2 / 2
1 / 0.85
Cpin
0.0033
0.0056
0.0127
Power
0.0055
0.009
0.02
Zload (LH/HL)
8 / 2
4.5 / 1.1
2.4 / 0.6
Cpin
0.0036
0.007
0.013
Power
0.0061
0.012
0.02
Zload (LH/HL)
4.25 / 2.3
1.9 / 1.2
1.1 / 0.6
Cpin
0.0038
0.006
0.0072
Power
0.0072
0.012
0.018
Zload (LH/HL)
5.1 / 2.7
2.6 / 1.5
1.2 / 0.7
Cpin
0.0043
0.0073
0.0124
Power
0.006
0.0115
0.02
Three input NOR gate: NOR3

Implementation
Strength
1
2
4
: y = (a + b + c)
Width(m)
1.84
2.76
2.52
tintrinsic (LH/HL)
0.056 / 0.022
0.046 / 0.021
0.042 / 0.021
Four input NAND gate: NAND4

Implementation
Strength
1
2
4
: y = (a b c d)
Width(m)
2.3
3.7
7.35
tintrinsic (LH/HL)
0.04 / 0.03
0.035 / 0.025
0.034 / 0.024
Four input NOR gate: NOR4

Implementation
Strength
1
2
4
: y = (a + b + c + d)
Width(m)
2.3
4.14
7.82
tintrinsic (LH/HL)
0.06 / 0.022
0.063 / 0.023
0.061 / 0.023
Two input multiplexer: MUX2

Implementation
Strength
1
2
4
: y = s a + s b
Width(m)
3.7
4.15
5.5
tintrinsic (LH/HL)
0.09 / 0.075
0.085 / 0.07
0.09 / 0.075
Two input inverting multiplexer: NMUX2

Implementation
Strength
1
2
4
: y = s a + s b)
Width(m)
3.22
4.6
6.9
tintrinsic (LH/HL)
0.045 / 0.06
0.04 / 0.06
0.035 / 0.05
358
Two input XOR: XOR2

Implementation
Strength
1
2
4
D.2.2
: y = a b + a b
Width(m)
3.22
5.5
8.3
# Flip-ops
tintrinsic (LH/HL)
0.035 / 0.055
0.035 / 0.05
0.03 / 0.04
Zload (LH/HL)
4 / 2.2
2 / 1.1
1 / 0.6
Cpin
0.003
0.005
0.01
Power
0.007
0.012
0.02
Appendix E
Finite Automata
The nite automaton is a very elaborated concept. The digital synthesis tools take a big part
of the responsibilities in deciding how to implement a HDL denition of a nite automaton.
For this reason only few basic design aspects are discussed in this appendix.
E.1
Basic denitions in automata theory
Denition E.1 An automaton, A, is dened by the following 5-uple:

A = (X, Y, Q, f, g)
where:
X : the nite set of input variables
Y : the nite set of output variables
Q : the set of state variables
f : the state transition function, described by f : X Q Q
g : the output transition function, with one of the following two denitions:
g : X Q Y for Mealy type automaton
g : Q Y for Moore type automaton.
At each clock cycle the state of the automaton switches and the output takes the value according
to the new state (and the current input, in Mealys approach).
Denition E.2 A half-automaton, A1/2 , is dened by the following triplet:
A1/2 = (X, Q, f )
where X, y and f have the same meaning as in the previous denition.
An half-automaton is an automaton without output. It is only a concept theoretically
useful.
Denition E.3 A nite automaton, FA, is an automaton with Q a nite set.
FA is a complex circuit because the size of its denition depends by |Q|.
359
360
APPENDIX E. FINITE AUTOMATA
Denition E.4 A recursively dened n-state automaton, nSA, is an automaton with |Q|
O(f (n)).
An n SA has a nite (usually short) denition depending by one or many parameters. Its
size will depend by parameters. Therefore, it is a simple circuit.
Denition E.5 An initial state is a state having no predecessor state.
Denition E.6 An initial automaton is an automaton having a set of initial states, Q , which
is a subset of Q, Q Q.
Denition E.7 A strict initial automaton is an automaton having only one initial state,
Q = {q0 }.
A strict initial automaton is dened by:
A = (X, Y, Q, f, g; q0 )
and has a special input, called reset, used to led the automaton in the initial state q0 . If the
automaton is initial only, the input reset switches the automaton in one, specially selected,
initial state.
Denition E.8 The delayed (Mealy or Moore) automaton is an automaton with the output
values generated through a (delay) register, thus the current output value corresponds to the
previous internal state of the automaton, instead of the current value of the state, as in nondelayed variant.
Denition E.9 The delayed (Mealy or Moore) automaton is an automaton with the output
values generated through a (delay) register, thus the current output value corresponds to the
previous internal state of the automaton, instead of the current value of the state, as in nondelayed variant.
Theorem E.1 The time relation between the input value and the output value is the following
for the four types of automata:
1. for Mealy automaton the output to the moment t, y(t) Y depends on the current input
value, x(t) X, and by the current state, q(t) Q, i.e., y(t) = g(x(t), q(t))
2. for delayed Mealy automaton and Moore automaton the output corresponds with the input
value from the previous clock cycle:
y(t) = g(x(t 1), q(t 1)) for Mealy delayed automaton
y(t) = g(q(t)) = g(f (x(t 1), q(t 1)) for Moore automaton
3. for delayed Moore automaton the input transition acts on the output transition delayed
with two clock cycles:
y(t) = g(q(t 1)) = g(f (x(t 2), q(t 2)).
Proof The proof is evident starting from the previous two denitions.
The possibility emphasized by this theorem is that we dispose of automata with dierent time
reaction to the input variations. The Mealy automaton follows immediate the input transitions,
delayed Mealy and Moore automata react with one clock cycle delay to the input transitions
and delayed Moore automaton delays with two cycles the response to the input.
The symbols from the sets X, Y , and Q are binary coded using bits specied by X0 , X1 , . . .
for X, Y0 , Y1 , . . . for Y , Q0 , Q1 , . . . for Q.
E.2. HOW BEHAVES A FINITE AUTOMATA
E.2
361
How behaves a nite automata
In the real world of our mind we have the lling of a continuous owing time. But, the time
in the real word of the automata evolve sequentially, like a tick-tack. In a world evolving
sequentially all the events manifest in distinct and periodic moments of time. Times evolution
is marked by a periodic signal called clock (see Figure E.1). All events in a theoretical
sequential environment are triggered by the active edge of clock. In real life a lot of
things happen between the two successive active edges of the clock, but they are managed only
by engineers.
amplitude
tick
active edge
6
+
6
/
6
6

tack
time
Figure E.1: The sequential clock. The clock signal is cyclic one. It has the period T: the time
interval between two successive active edges (between two ticks).
While our mind perceives globally the string of letters
aaabb
and analyze it in continuous time, a sequential machine receives the same string letter by letter.
At each active edge of the clock another letter is applied to the input of a sequential machine.
In other words, each active edge of the clock triggers the switch of value applied to the input.
The internal state of the automaton switches synchronized by the same clock. Accordingly,
the output of the sequential machine changes synchronized by the same event.
The clock is the big boss allowing all the changes that must be performed in a sequential
synchronous system.
Example E.1 Let be the sequential machine, called Divide, represented in Figure E.2a. It
behaves as follows: its output takes the value 0 if the signal reset is activated ignoring the value
applied on in, then, when reset = 0, after each two 1s received on its input the output switch in
the complementary value (from 1 to 0, or from 0 to 1). The wave forms describing the behavior
of the system are represented in Figure E.2b.
Before receiving reset = 1 the state of the output is unknown, out = x (x stands here for
unknown).
The stream of 1s and 0s is meaningful for the machine only after it is reset. Therefore, the
stream of bits received in the example illustrated in Figure E.2b is: 1101110. The 0 applied to
the input in T0 is ignored by the machine because the input reset has priority.
The value generated on the output of the machine DIVIDER can not be explained investigating only the value applied in the same time to its input. For in=0 we nd sometimes out =
0, and other times out = 1. Similar, for in=1. It is obvious that an internal hidden variable
evolves generating a more complex behavior than one can be explained starting only from the
current value on input.
362
reset
?
in
out
clock
a.
clock
DIVIDER
6
6
time
reset
6
1
time
in
6
0
time
out
6
X
T0
T1
T2
T3
T4
T5
T6
T7
time
b.
Figure E.2: Divider: a simple sequential machine. a. The block diagram of the system. b.
The wave forms describing its behavior.
E.3
Representing nite automata
A nite automaton is represented by dening its transition functions f , the state transition
function, and g, the output transition function. For a half-automaton only the function f
dened.
E.3.1
Flow-charts
A ow-chart contains for each state a circle and for each type of transition an arrow. In each
clock cycle the automaton runs on an arrow going from the current state to the next state.
In our simple model the race on arrow is done in the moment of the active edge of the clock.
The ow-chart for a half-automaton
The rst version is a pure symbolic representation, where the ow chart is marked on each
circle with the name of the state, and on each arrow with the transition condition, if any. The
E.3. REPRESENTING FINITE AUTOMATA
363
initial states can be additionally marked with the minus sign (-), and the nal states can be
additionally marked with the plus sign (+).
reset
a
q0
b
R
q0 , -
q1
X0
q2 , +
q1
b
1
X0

q2
a.
b.
Figure E.3: Example of ow-chart for a half-automaton. The machine is a double b detector. It stops when the rst bb occurs.
The second version is used when the input are considered in the binary form. Instead of
arches are used rhombuses containing the symbol denoting a binary variable.
Example E.2 Let be a nite half-automaton that receives on its input strings containing symbols
from the alphabet X = {a, b}. The machine stops in the nal state when the rst sequence bb
is received. The rst version of the associated ow-chart is in Figure E.3a. Here is how the
machine works:
the initial state is q0 ; if a is received the machine remains in the same state, else, if b is
received, then the machine switch in the state q1
in the state q1 the machine knows that one b was just received; if a is received the
half-automaton switch back in q0 , else, if b is received, then the machine switch in q2
q2 is the nal state; the next state is unconditionally q2 .
The second version uses tests represented by a rhombus containing the tested binary input variable (see (Figure E.3b). The input I takes the binary value 0 for the the symbol a and the binary
value 1 for the symbol b.
The second version is used mainly when a circuit implementation is envisaged.
The ow-chart for a Moore automaton
When an automaton is represented the output behavior must be also included.
The rst, pure symbolic version contains in each circle besides, the name of the sate, the
value of the output in that sates. The output of the automaton shows something which is
meaningful for the user. Each state generates an output value that can be dierent from the
364
reset
q0
0
b
R
q0 /0, -
q1 /0
X0
q1
a
1
q2 /1, +
b
1
X0
q2

a.
b.
Figure E.4: Example of ow-chart for a Moore automaton. The output of this automaton
tells us: bb was already detected.
states name. The output set of value are used to classify the state set. The input events are
mapped into the state set, and the state set is mapped into the output set.
The second uses for each pair state/output one rectangle. Inside of the rectangle is the value
of the output and near to it is marked the state (by its name, by its binary code,, or both).
Example E.3 The problem solved in the previous example is revisited using an automaton. The
output set is Y = {0, 1}. If the output takes the value 1, then we learn that a double b was already
received. The state set Q = {q0 , q1 , q2 } is divided in two classes: Q0 = {q0 , q1 } and Q1 = {q2 }.
If the automaton stays in Q0 with out = 1, then it is looking for bb. If the automaton stays in
Q1 with out = 1, then it stopped investigating the input because a double b was already received.
The associated ow-chart is in, in the rst version represented by Figure E.4a. The states
q0 and q1 belong to Q0 because in the corresponding circles we have q0 /0 and q1 /0. The state q2
belongs to Q1 because in the corresponding circle we have q2 /1. Because the evolution from q2
does not depend by input, the arrow emerging from the corresponding circle is not labelled.
The second version (see Figure E.4b) uses three rectangles, one for each state.
A meaningful event on the input of a Moore automaton is shown on the output with a delay
of a clock cycle. All goes through the state set. In the previous example, if the second b from
bb is applied on the input in the period Ti of the clock cycle, then the automaton points out the
event in the period Ti+1 of the clock cycle.
The ow-chart for a Mealy automaton
The rst, pure symbolic version contains on each arrow besides, the name of the condition, the
value of the output generated in the state where the arrow starts with the input specied on
the arrow.
The Mealy automaton reacts on its outputs more promptly to a meaningful input event.
The output value depends on the input value from the same clock cycle.
The second, implementation oriented version uses rectangles to specify the outputs behavior.
Example E.4 Let us solve again the same problem of bb detection using a Mealy automaton.
The resulting ow-chart is in Figure E.5a. Now the output is activated (out = 1) when the
365
reset
q0
X0
a/0
q1
b/0
R
q0 , -
0
q1
a/0
X0
a/1, b/1 = -/1
q2 , +
b/1
q2

1
a.
b.
Figure E.5: Example of ow-chart for a Mealy automaton. The occurrence of the second b
from bb is detected as fast as possible.
automaton is in the state q1 (one b was detected in the previous cycle) and the input takes the
value b. The same condition triggers the switch in the state q2 . In the nal state q2 the output
is unconditionally 1. In the notation /1 the sign stands for dont care.
Figure E.5b represents the second representation.
We can say the Mealy automaton is a transparent automaton, because a meaningful change
on its inputs goes directly to its output.
E.3.2
Transition diagrams
Flow-charts are very good to oer an intuitive image about how automata behave. The concept
is very well represented. But, automata are also actual machines. In order to help us to provide
the real design we need dierent representation. Transition diagrams are less intuitive, but they
work better for helping us to provide the image of the circuit performing the function of a certain
automaton.
Transition diagrams uses Vetch-Karnaugh diagrams, VKD, for representing the transition
functions. The representation maps the VKD describing the state set of the automaton into the
VKDs dening the function f and the function g.
Transition diagrams are about real stu. Therefore, the symbols like a, b, q0 , . . . must be
codded binary, because a real machine work with bits, 0 and 1, not with symbols.
366
The output is already codded binary. For the input symbols the code is established by the
user of the machine (similarly the output codes have been established by the user). Let say,
for the input variable, X0 , was decided the following codication: a X0 = 0 and b X0 = 1.
Because the actual value of the state is hidden from the user, the designer has the freedom
to assign the binary values according to its own (engineering) criteria. Because the present
approach is a theoretical one, we do not have engineering criteria. Therefore, we are completely
free to assign the binary codes. Two option are presented:
option 1: q0 = 00, q1 = 01, q2 = 10
option 2: q0 = 00, q1 = 10, q2 = 11
For both the external behavior of the automaton must be the same.
Transition diagrams for half-automata
The transition diagram maps the reference VKD into the next state VKD, thus dening the
state transition function. Results a representation ready to be used to design and to optimize
the physical structure of a nite half-automaton.
Example E.5 The ow-chart from Figure E.3 has two dierent correspondent representations
as transition diagrams in Figure E.6, one for the option 1 of coding (Figure E.6a), and another
for the option 2 (Figure E.6b).
+
+
{S1
, S0
} = f (X0 , S1 , S0 )
S1
S0
S1
S0
- X0 0
0 X0
+
+
S1
, S0
S1 , S0
a.
+
+
{S1
, S0
} = f (X0 , S1 , S0 )
S1
S0
S1 , S0
S0
S1
1
X0 X0 X0 0
+
+
S1
, S0
b.
Figure E.6: Example of transition diagram for a half-automaton. a. For the option 1 of
coding. b. For the option 2 of coding.
In VKD S1 , S0 each box contains a 2-bit code. Three of them are used to code the states,
and one will be ignored. VKD S1+ , S0+ represents the transition from the corresponding states.
Thus, for the rst coding option:
from the state codded 00 the automaton switch in the state 0x, that is to say:
if X0 = 0 then the next state is 00 (q0 )
from the state codded 01 the automaton switch in the state x0, that is to say:
367

from the state codded 10 the automaton switch in the same state, 10 that is the nal state
the transition from 11 is not dened.
If in the clock cycle Ti the state of the automaton is S1 , S0 (dened in the reference VKD), then
in the next clock cycle, Ti+1 , the automaton switches in the state S1+ , S0+ (dened in the next
state VKD).
For the second coding option:
from the state codded 00 the automaton switch in the state X0 0, that is to say:
from the state codded 10 the automaton switch in the state X0 X0 , that is to say:
from the state codded 11 the automaton switch in the same state, 11 that is the nal state
the transition from 01 is not dened.
The transition diagram can be used to extract the Boolean functions of the loop of the
half-automaton.
Example E.6 The Boolean function of the half-automaton working as double b detector can
be extracted from the transition diagram represented in Figure E.6a (for the rst coding option).
Results:
S1+ = S1 + X0 S0
S0+ = X0 S1 S0
Transition diagrams Moore automata

The transition diagrams dene the two transition functions of a nite automaton. To the
VKDs describing the associated half-automaton is added another VKD describing the outputs
behavior.
Example E.7 The ow-chart from Figure E.4 have a correspondent representation in the transition diagrams from Figure E.7a or Figure E.7b. Besides the transition diagram for the state,
the output transition diagrams are presented for the two coding options.
For the rst coding option:
for the states coded with 00 and 01 the output has the value 0
for the state coded with 10 the output has the value 1
we do not care about how works the function g for the state coded with 11 because this code
is not used in dening our automaton (the output value can 0 or 1 with no consequences
on the automatons behavior).
368
+
+
{S1
, S0
} = f (X0 , S1 , S0 )
out = g(S1 , S0 )
S1
S0
S1
S0
- X0 0
0 X0
+
+
S1
, S0
S1 , S0
out
S1
S0
a.
+
+
{S1
, S0
} = f (X0 , S1 , S0 )
out = g(S1 , S0 )
S1
S0
S1
S0
out
S1 , S0
S0
S1
1
X0 X0 X0 0
+
+
S1
, S0
b.
Figure E.7: Example of transition diagram for a Moore automaton.
Example E.8 The resulting output function is:

out = S1 .
Now the resulting automaton circuit can be physically implemented, in the version resulting from
the rst coding option, as a system containing a 2-bit register and few gates. Results the circuit
in Figure E.8, where:
the 2-bit register is implemented using two resetable D ip-ops
the combinational loop for state transition function consists in few simple gates
the output transition function is so simple as no circuit are needed to implement it.
When reset = 1 the two ip-ops switch in 0. When reset = 0 the circuit starts to analyze
the stream received on input symbol by symbol. In each clock cycle a new symbol is received and
the automaton switches according to the new state computed by three gates.
Transition diagrams Mealy automata

The transition diagrams for a Mealy automaton are a little dierent from those of Moore, because
the output transition function depends also by the input variable. Therefore the VKD dening
g contains, besides 0s and 1s, the input variable.
Example E.9 Revisiting the same problem result, in Figure E.9 the transition diagrams associated to the ow-chart from Figure E.5.
The two functions f are the same. The function g is dened for the rst coding option
(Figure E.9a) as follows:
in the state coded by 00 (q0 ) the output takes value 0
in the state coded by 01 (q1 ) the output takes value x
in the state coded by 10 (q2 ) the output takes value 1
369
loop combinational circuit

in = X0
+
S1
+
S0
clock
reset
D
R
DFF
Q
D
DFF
S0
2-bit register
S1
out
Figure E.8: The Moore version of bb detector automaton.

+
+
{S1
, S0
} = f (X0 , S1 , S0 )
out = g(X0 , S1 , S0 )
S1
S0
X0
S1
S0
- X0 0
0 X0
+
+
S1
, S0
S1 , S0
out
S1
S0
a.
+
+
{S1
, S0
} = f (X0 , S1 , S0 )
out = g(X0 , S1 , S0 )
S1
S0
X0
out
S1
S0
S1 , S0
S0
S1
1
X0 X0 X0 0
+
+
S1
, S0
b.
Figure E.9: Example of transition diagram for a Mealy automaton.

in the state coded by 11 (unused) the output takes the dont care value
Extracting the function out results:
out = S1 + X0 S0
a more complex from compared with the Moore version. (But fortunately out = S1+ , and the
same circuits can be used to compute both functions. Please ignore. Engineering stu.)
E.3.3
Procedures
The examples used to explain how the nite automata can be represented are simple because
of obvious reasons. The real life is much more complex and we need tools to face its real
challenges. For real problems software tools are used to provide actual machines. Therefore,
software oriented representation must be provided for representing automata. The so called
Hardware Description Languages, HDLs, are widely used to manage complex applications. (The
Verilog HDL is used to exemplify the procedural way to specify a nite automaton.)
370
HDL representations for Moore automata

A HDL (Verilog, in our example) representation consists in a program module describing the
connections and the behavior of the automaton.
Example E.10 The same bb detector is used to exemplify the procedures used for the Moore
automaton representation.
module moore_automaton(out, in, reset, clock);
// input codes
parameter
a = 1b0,
b = 1b1;
// state codes
parameter
init_state = 2b00,
// the initial state
one_b_state = 2b01,
// the state for one b received
final_state = 2b10;
// the final state
// output codes
parameter
no = 1b0, // no bb yet received
yes = 1b1; // two successive b have been received
// external connections
input
in, reset, clock;
output
out;
reg
[1:0]
state; // state register
reg
out;
// output variable
// f: the state sequential transition function
if (reset) state <= init_state;
else case(state)
init_state : if (in == b) state <= one_b_state;
else
state <= init_state;
one_b_state : if (in == b) state <= final_state;
else
final_state :
state <= final_state;
default
state <= 2bx;
endcase
// g: the output combinational transition function
always @(state) case(state)
init_state : out = no;
one_b_state : out = no;
final_state : out = yes;
default
out = 1bx;
endcase
endmodule
HDL representations for Mealy automata

A Verilog description consists in a program module describing the connections and the behavior
of the automaton.
E.4. STATE CODDING
371
Example E.11 The same bb detector is used to exemplify the procedures used for the Mealy
automaton representation.
module mealy_automaton(out, in, reset, clock);
parameter
a = 1b0,
b = 1b1;
parameter
init_state = 2b00,
// the initial state
one_b_state = 2b01,
// the state for one b received
final_state = 2b10;
// the final state
parameter
no = 1b0, // no bb yet received
yes = 1b1; // two successive b have been receiveda
input
in, reset, clock;
output
out;
reg
[1:0]
state;
reg
out;
if (reset) state <= init_state;
else case(state)
init_state : if (in == b) state <= one_b_state;
else
one_b_state : if (in == b) state <= final_state;
else
final_state :
state <= final_state;
default
state <= 2bx;
endcase
always @(state or in) case(state)
init_state : out = no;
one_b_state : if (in == b) out = yes;
else
out = no;
final_state : out = yes;
default
out = 1bx;
endcase
endmodule
The procedural representations are used as inputs for automatic design tools.
E.4
State codding
The function performed by an automaton does not depend by the way its states are encoded,
because the value of the state is a hidden variable. But, the actual structure of a nite
automaton and its proper functioning are very sensitive to the state encoding.
The designer uses the freedom to code in dierent way the internal state of a nite automaton
for its own purposes. A nite automaton is a concept embodied in physical structures. The
transition from concept to an actual structure is a process with many traps and corner cases.
Many of them are avoided using an appropriate codding style.
Example E.12 Let be a rst example showing the structural dependency by the state encoding.
The automaton described in Figure E.10a has three state. The rst codding version for this
372
automaton is: q0 = 00, q1 = 01, q2 = 10. We compute the next state Q1 , Q+

0 , and the output
Y1 , Y0 using the rst two VK transition diagrams from Figure E.10b:
Q+
1 = Q0 + X0 Q1

Q+
0 = Q1 Q0 X0
Y1 = Q0 + X0 Q1
Y0 = Q1 Q0 .
The second codding version for the same automaton is: q0 = 00, q1 = 01, q2 = 11. Only the
code for q2 is dierent. Results, using the last two VK transition diagrams from Figure E.10b:
Q1
Q0
q0
X0
00
Q1 Q0
Q1
0
Q0
10
0 X0 X0
01
q1
q2
Q1
1
Q0
Q+
Q+
1
0
0 X0 1
Y1 Y0
(11)
Q1
1
Q0
Q1
- X0 1
Q0
Q+
Q+
1
0
a.
- X0 1
Y1 Y0
b.
Figure E.10: A 3-state automaton with two dierent state encoding. a. The ow-chart
describing the behavior. b. The VK diagrams used to implement the automaton: the reference diagram
for states, two transition diagrams used for the rst code assignment, and two for the second state
assignment.
CK
Q+
0
X0
D
D-FF1
Q Q
Q+
1
D
D-FF0
Q Q
Y1
Y0
Figure E.11: The resulting circuit It is done for the second state assignment of the automaton
dened in Figure E.10a.
E.4. STATE CODDING
373

Q+
1 = Q1 Q0 + X0 Q1 = (Q1 + (Q0 + X0 ) )
Q+
0 = Q1
Y1 = Q1 Q0 + X0 Q1 = (Q1 + (Q0 + X0 ) )
Y0 = Q0 .
Obviously the second codding version provides a simpler and smaller combinational circuit
associated to the same external behavior. In Figure E.11 the resulting circuit is represented.
E.4.1
Minimal variation encoding
Minimal variation state assignment (or encoding) refers to the codes assigned to successive
states.
Denition E.10 Codding with minimal variation means successive state are codded with minimal Hamming distance.
qi
000
qi
000
qj
001
X0
X0
qj
ql
001
010
qk
?
qk
101
a.
ql
011
b.
Figure E.12: Minimal variation encoding. a. An example. b. An example where the minimal
variation encoding is not possible.
Example E.13 Let be the fragment of a ow chart represented in Figure E.12a. The state qi is
followed by the state qj and the assigned codes dier only by the least signicant bit. The same
for qk and ql which both follow the state qj .
Example E.14 Some times the minimal variation encoding is not possible. An example is
presented in Figure E.12b, where qk can not be codded with minimal variation.
The minimal variation codding generates a minimal dierence between the reference VK diagram and the state transition diagram. Therefore, the state transition logical function extracted
form the VK diagram can be minimal.
374
qi
000
qi
010
1
X0
qj
001
qj
qk
011
111
X1
(001)
qk
100
(011)
a.
X0
ql
101
(101)
b.
Figure E.13: Examples of reduced dependency encoding. a. The transition from the state
is conditioned by the value of a single 1-bit variable. b. The transition from the state is conditioned by
two 1-bit variables.
E.4.2
Reduced dependency encoding
Reduced dependency encoding refers to states which conditionally follow the same state. The
reduced dependency is related to the condition tested.
Denition E.11 Reduced dependency encoding means the states which conditionally follow a
certain state to be codded with binary congurations which diers minimal (have the Hamming
distance minimal).
Example E.15 In Figure E.13a the states qj and qk follow, conditioned by the value of 1-bit
variable X0 , the state qi . The assigned codes for the rst two dier only in the most signicant
bit, and they are not related with the code of their predecessor. The most signicant bit used to
code the successors of qi depends by X0 , and it is X0 . We say: the next states of qi are X0 11,
for X0 =0 the next state is 111, and for X0 =1 it is 011. Reduced dependency means: only one
bit of the codes associated with the successors of qi depends by X0 , the variable tested in qi .
Example E.16 In Figure E.13b the transition from the state qi depends by two 1-bit variable,
X0 and X1 . A reduced dependency codding is possible by only one of them. Without parenthesis
is a reduced dependency codding by the variable X1 . With parenthesis is a reduced dependency
codding by X0 . The reader is invited to provide the proof for the following theorem.
Theorem E.2 If the transition from a certain state depends by more than one 1-bit variable,
the reduced dependency encoding can not be provided for more than one of them.
The reduced dependency encoding is used to minimize the transition function because it
allows to minimize the number of included variables in the VK state transition diagrams. Also,
we will learn soon that this encoding style is very helpful in dealing with asynchronous input
variables.
E.4.3
Incremental codding
The incremental encoding provides an ecient encoding when we are able to use simple circuits
to compute the value of the next state. An incrementer is the simple circuit used to design
the simple automaton called counter. The incremental encoding allows sometimes to center the
implementation of a big half-automaton on a presetable counter.
E.5. MINIMIZING FINITE AUTOMATA
375
Denition E.12 Incremental encoding means to assign, whenever it is possible, for a state
following qi a code determined by incrementing the code of qi .
Incremental encoding can be useful for reducing the complexity of a big automaton, even if
sometimes the price will be to increase the size. But, as we more frequently learn, bigger size is
a good price for reducing complexity.
E.4.4
One-hot state encoding
The register is the simple part of an automaton and the combinational circuits computing the
state transition function and the output function represent the complex part of the automaton.
More, the speed of the automaton is limited mainly by the size and depth of the associated combinational circuits. Therefore, in order to increase the simplicity and the speed of an automaton
we can use a codding stile which increase the dimension of the register reducing in the same
time the size and the depth of the combinational circuits. Many times a good balance can be
established using the one-hot state encoding.
Denition E.13 The one-hot state encoding associates to each state a bit, and consequently
the state register has a number of ip-ops equal with the number of states.
All previous state encodings used a log-number of bits to encode the state. The size of the
state register will grow, using one-hot encoding, from O(log n) to O(n) for an n-state nite
automaton. Deserves to pay sometimes this price for various reasons, such as speed, signal
accuracy, simplicity, . . ..
E.5
Minimizing nite automata
There are formal procedure to minimize an automaton by minimizing the number of internal
states. All these procedures refer to the concept. When the conceptual aspects are solved remain
the problems related with the minimal physical implementation. Follow a short discussion about
minimizing the size and about minimizing the complexity.
E.5.1
Minimizing the size by an appropriate state codding
There are some simple rules to be applied in order to generate the possibility to reach a minimal
implementation. Applying all of these rules is not always possible or an easy task and the result
is not always guarantee. But it is good to try to apply them as much as possible.
A secure and simple way to optimize the state assignment process is to evaluate all possible
codding versions and to choose the one which provide a minimal implementation. But this is
not an eective way to solve the problem because the number of dierent versions is in O(n!).
For this reason are very useful some simple rules able to provide a good solution instead of an
optimal one.
A lucky, inspired, or trained designer will discover an almost optimal solution applying the
following rule in the order they are enounced.
Rule 1 : apply the reduced dependency codding style whenever it is possible. This rule allows
a minimal occurrence of the input variable in the VK state transition diagrams. Almost all the
time this minimal occurrence has as the main eect reducing the size of the state transition
combinational circuits.
376
Rule 2 : the states having the same successor with identical test conditions (if it is the case)
will have assigned adjacent codes (with the Hamming distance 1). It is useful because brings in
adjacent locations of a VK diagrams identical codes, thus generating the conditions to maximize
the arrays dened in the minimizing process.
Rule 3 : apply minimal variation for unconditioned transitions. This rule generates the
conditions in which the VK transition diagram diers minimally from the reference diagram,
thus increasing the chance to nd bigger surfaces in the minimizing process.
Rule 4 : the states with identical outputs are codded with minimal Hamming distance (1 if
possible). Generates similar eects as Rule 2.
To see at work these rules lets take an example.
Example E.17 Let be the nite automaton described by the ow-chart from Figure E.14. Are
proposed two codding versions, a good one (the rst), using the codding rules previously listed,
and a bad one (the second with the codes written in parenthesis), ignoring the rules.
For the rst codding version results the expressions:
Q+
2 = Q2 Q0 + Q2 Q1
Q+
1 = Q1 Q0 + Q2 Q1 Q0 + Q2 Q0 X0
Q+
0 = Q0 + Q2 Q1 X0
Y2 = Q2 + Q1 Q0
Y1 = Q2 Q1 Q0 + Q2 Q1
Y0 = Q2 + Q1 + Q0
the resulting circuit having the size SCLCver1 = 37.
For the second codding version results the expressions:
Q+
2 = Q2 Q1 Q0 + Q1 Q0 + Q2 Q0 X0 + Q1 Q0 X0
Q+
1 = Q1 Q0 + Q2 Q1 + Q2 X0
Q+
0 = Q1 Q0 + Q2 Q1 + Q2 X0
Y2 = Q2 Q0 + Q2 Q1 + Q2 Q1 Q0 + Q1 Q0
Y1 = Q2 Q0 + Q2 Q1
Y0 = Q2 + Q1 + Q0
the resulting circuit having the size SCLCver2 = 50.
E.5.2
Minimizing the complexity by one-hot encoding
Implementing an automaton with one-hot encoded states means increasing the simple part of
the structure, the state register. It is expected at least a part of this additional structure to be
compensated by a reduced combinational circuit used to compute the transition functions. But,
for sure the entire complexity is reduced because of a simpler combinational circuit.
Example E.18 Let be the automaton described by the ow-chart from Figure E.15, for which
two codding version are proposed: a one-hot encoding using 6 bits (Q6 . . . Q1 ), and a compact
binary encoding using only 3 bits (Q2 Q1 Q0 ).
The outputs are Y6 , . . . , Y1 each active in a distinct state.
E.5. MINIMIZING FINITE AUTOMATA
377
000
Q2
011
(000)
Q1
110
111
011
010
100
101
001
000
001
011
(011)
Q0
Q2 Q1 Q0
0
1
X0
011
010
100
001
(010)
(101)
1
X0
100
110
101
111
(110)
(001)
101
111
101
101
(100)
(111)
Q2
Q1
Q2
111
000
1X0 0
111
101
000
01X0
001
Q1
111
101
100
001
101
101
011
011
Version 1
Q0
Q+
Q+
Q+
2
1
0
Q0
Y2 Y1 Y0
Q2
Q1
Q2
100
000
000
111
X0 X0 X0 X0 X0 X0
Q1
101
101
011
100
101
001
111
011
Version 2
Q+
Q+
Q+
2
1
0
111
011
Q0
Q0
Y2 Y1 Y0
Figure E.14: Minimizing the structure of a nite automaton. Applying appropriate codding
rules the occurrence of the input variable X0 in the transition diagrams can be minimized, thus resulting
smaller Boolean forms.
378
Q1 = 1
Y0=1
000
Q2 = 1
X0
Q3 = 1
Y2=1
Y3=1
011
0
Q4 = 1
Y4=1
X0
Q5 = 1
111
0
Y5=1
010
X0
Q6 = 1
Y6=1
110
100
Figure E.15: Minimizing the complexity using one-hot encoding.

+
Version 1: with one-hot encoding The state transition functions, Q+
i , i = 1, . . . , Q6 ,
can be written directly inspecting the denition. Results:
Q+ 1 = Q4 + Q5 + Q6
Q+ 2 = Q1 X0
Q+ 3 = Q1 X0
Q+ 4 = Q2 X0
Q+ 5 = Q2 X0 + Q3 X0
Q+ 6 = Q3 X 0
Because in each state only one output bit is active, results:
Yi = Qi , pentru i = 1, . . . , 6.
The combinational circuit associated with the state transition function is very simple, and for
outputs no circuits are needed. The size of the entire combinational circuit is SCLC,var1 =
18, with the big advantage that the outputs come directly from a ip-op without additional
unbalanced delays or other parasitic eects (like dierent kinds of hazards).
Version 2: compact binary codding The state transition functions for this codding version
(see Figure E.15 for the actual binary codes) are:
Q+ 2 = Q2 Q0 + Q0 X0 + Q2 Q1 X0
Q+ 1 = Q2 Q0 + Q2 Q1 + Q0 X0
Q+ 0 = Q2 Q1
For the output transition function an additional decoder, DCD3 , is needed. The resulting combinational circuit has the size SCLC,var2 = 44, with the additional disadvantage of generating the
outputs signal using a combinational circuit, the decoder.
E.6. PARASITIC EFFECTS IN AUTOMATA
E.6
379
Parasitic eects in automata
A real automaton is connected to the external world from which it receives of where it sends
signals only partially are controlled. This happens mainly when the connection is not sequential,
mediated by a synchronous register, because sometimes this is not possible. The designer controls
very well the signals on the loop. But, the uncontrolled arriving signals can by very dangerous
for the proper functioning of an automaton. Similarly, an uncontrolled output signal can have
hazardous behaviors.
E.6.1
Asynchronous inputs
An automaton is implemented as a synchronous circuit changing its internal states at each active
(positive or negative) edge of clock. Let us remember the main restrictions imposed by the setup time and hold time related to the active edge of a clock applied to a ip-op. No input signal
can change in the time interval beginning tSU before the clock transition and ending tH after
the clock transition. Call it the prohibited time interval. But, if at least one input of a certain
nite automaton determines a switch on at least one input of the state register, then no one can
guarantee a proper functioning of that automaton.
Let be a nite automaton with one input, X0 , changing unrelated with the system clock.
Its transition can determine a transition on the input of a state ip-op in the prohibited time
interval. We call this kind of variable asynchronous input variable or simply asynchronous
variable, and we use for it the notation X0 . If, in a certain state the automaton test X0 and
switches in 1X0 X0 0 (which means in 1000 if X0 = 0, or 1110 is X0 = 1), then we are in trouble.
The actual behavior of the automaton will allow also the transition in 1X0 A0 and in 1X0 X0 0,
which means the actual transition of the automaton will be in fact in 1xx0, where x {0, 1}.
Indeed, if X0 determine the transition of two state ip-ops in the prohibited time interval, any
binary conguration can be loaded in that ip-ops, not only 11 or 00.
What is the solution for this pathological behavior induced by s asynchronous variable?
To use reduced dependency codding for the transition from the state in which X0 is tested.
If the state assignment will allow, for example, a transition to 11X0 0, then the behavior of
the automaton becomes coherent. Indeed, if X0 determine a transition in the prohibited time
interval on only one state ip-op, then the next state will be only 1110 or 1100. In both cases
the automaton behaves according to its denition. If the transition of X0 is considered is correct,
but even if the transition is not catched it will be considered at the net clock cycle.
Example E.19 In Figure E.16 is dened a 3-state automaton with the asynchronous input
variable X0 . Two code assignment are proposed. The rst one uses the minimal variation kind
of codding, and the second uses for the transition from the state q0 a reduced dependency codding.
The rst codding is:
q0 = 01, q1 = 00, q2 = 10, q3 = 11.
Results the following circuits for state transition:
Q+
1 = Q0 + Q1 X0
Q+
0 = Q1 + Q0 X0 .
The transition from the state Q1 Q0 = 01 is dangerous for the proper functioning of the nite
automaton. Indeed, from q0 the transition is dened by:
+
Q+
1 = X0 , Q0 = X0
and the transition of X0 can generate changing signals on the state ip-ops in the prohibited
time interval. Therefore, the state q0 can be followed by any state.
380
q0
01 [01]
0
00
[00]
q1
10
[11]
q2
X0
1
q3
11 [10]
CK
Version 1
D
X0
1
Q
Q1
0
Q
Q
Q0
Q+
0
01
X0 X0
11
10
Q+
, Q+
1
0
Q+
1
CK
Version 2
X0
1
Q
0
Q
Q1
Q
Q+
0
Q0
Q+
1
10
X0 0
01
11
Q+
, Q+
1
0
Figure E.16: Implementing a nite automaton with an asynchronous input.

The second codding, with reduced (minimal) dependency, is:
q0 = 01, q1 = 00, q2 = 11, q3 = 10
Results the following equations describing the loop circuits:

Q+
1 = Q1 Q0 + Q1 Q0 + Q0 X0
Q+
0 = Q0 .
The transition from the critical state, q0 , is

+
Q+
1 = A, Q0 = Q0 .
Only Q+
1 depends by the asynchronous input.
The size, the depth and the complexity of the resulting circuit is similar, but the behavior is
correct only for the second version. The correctness is achieved only by a proper encoding.
Obviously, transition determined by more than one asynchronous variable must be avoided,
because, as we already know, the reduced dependency codding can be done only for one asynchronous variable in each state. But, what is the solution for more than one asynchronous input
variable? Introducing new states in the denition of the automaton, so as in each state no more
than one asynchronous variable will be tested.
E.6.2
381
The Hazard
Some additional problems must be solved to provide accurate signals to the outputs of the
immediate nite automata. The output combinational circuit introduces, besides a delay due
to the propagation time through the gate used to build it, some parasitic eects due to a
kind of indecision in establishing the output value. Each bit on the output is computed
using a dierent network o gates and the eect of an input switch reaches the output going
trough dierent logic path. The propagation trough these various circuits can provide hazardous
transient behaviors on certain outputs.
Hazard generated by asynchronous inputs
A rst form of hazardous behavior, or simply hazard, is generated by the impossibility to have
synchronous transitions to the input of a combinational circuit.
Let be circuit from Figure E.17a representing the typical gates receiving the signal A and
B, ideally represented in Figure E.17b. Ideally means the two signals switches synchronously.
They are considered ideal because no synchronous signal can be actually generated. In Figure
E.17c and Figure E.17d two actual relations between the signals A and B are represented (other
two are possible, but our purpose this two cases will allow to emphasize the main eects of the
actual asynchronicity).
Ideally, the AND gate must have the output continuously on 0, and the OR and XOR gates on
1. Because of the inherent asynchronnicity between the input signals some parasitic transitions
occur to the outputs of the three gates (see Figure E.17c and Figure E.17d). Ideally, to the
inputs of the three gates are applied only two binary congurations: AB = 10 and AB = 01.
But, because of the asynchronicity between the two inputs, all possible binary congurations
are applied, two of them for long time (AB = 10 and AB = 01) and the other two (AB = 00
and AB = 11) only for short (transitory) time. Consequently, transitory eects are generated,
by hazard, on the outputs of the three circuits.
Some times the transitory unexpected eects can be ignored including them into the transition time of the circuit. But, there are applications where they can generate big disfunctionalities. For example, when one of the hazardous output is applied on a set or reset input of a
latch.
In order to oer an additional explanation for this kind of hazard VK diagrams are used in
Figure E.18, where in the rst column of diagrams the ideal case is presented (the input switches
directly to the desired value). In the next two column the input reach the nal value through an
intermediary value. Some times the intermediary value is associated with a parasitic transition
of the output.
When between two subsystems multi-bit binary congurations are transferred, parasitic conguration must be considered because of the asynchronicity. The hazardous eects can be
healed being patient waiting for the hazardous transition to disappear. But, we can wait
only if we know when the transition occurred, i.e., the hazard is easy to be avoided in synchronous
systems.
Simply, when more than one input of a combinational is changing we must expect hazardous
transitions at least on some outputs.
Propagation hazard
Besides the hazard generated by the two or many switching inputs there exists hazard due to the
transition of only one input. In this case the internal propagations inside of the combinational
circuit generate the hazard. It could by a sort of asynchronicity generated by the dierent
propagation paths inside the circuit.
382
A
A
6
-
B
The ideal
situation
a.
The actual
situations
c.
6
-
d.
6
-
6
-
0
E
6
-
0
C
0
E
0
D
0
C
E
b.
6
-
Figure E.17: How the asynchronous inputs generate hazard.

Let be a simple example of the circuit represented in Figure E.19a, where two input are
stable (A = C = 1) and only one input switches. The problem of asynchronoous inputs is not
an issue because only one input is in transition. In Figure E.19b the detailed wave forms allow
us to emphasize a parasitic transition on the output D. For A = C = 1 the output must stay
on 1 independent by the value applied on B. The actual behavior of the circuit introduces a
parasitic (hazardous) transition in 0 due to the switch of B from 1 to 0. An ideal circuit with
zero propagation times should maintain its output on 1.
A simple way to explain this kind of hazard is to say that in the VK diagram of the circuit
(see Figure E.19c) when the input ies from one surface of 1s to another it goes through the 0
surface generating a temporary transition to 0. In order to avoid this transitory journey through
the 0 surface an additional surface (see Figure E.19d) is added to transform the VK diagram in
a surface containing two contiguous surfaces, one for 0s and one for 1s. The resulting equation
of the circuit has an additional term: AC. The circuit with the same logic behavior, but without
hazardous transitions is represented in Figure E.19e.
Example E.20 Let be the function presented in VK diagram from Figure E.20a. An immediate
solution is shown in Figure E.20b, where a square surface is added in the middle. But this
solution is partial because ignores the fact that the VK diagram is dened as a thor, with a
A
B
383
-6
IDEAL
A < B
B < A
AND
1
1
1
1
-6
1
1
IDEAL
A < B
B < A
OR
B
1
IDEAL
B
1

?
A < B
B
1
?
B < A
XOR
Figure E.18: VK diagrams explaining the hazard due to the asynchronous inputs. A < B
means the input A switch before the input B, and A > B means the input B switch before
the input A.
three-dimensional adjacency. Consequently the surfaces A BCD and A B CD are adjacent,
and the same for AB C D and A B C D. Therefore, the solution to completely avoid the hazard
is presented in Figure E.20c, where two additional surfaces are added.
Theorem E.3 If the expression of the Boolean function
f (xn1 , . . . x0 )
takes the form
xi + xi
for at least one combination of the other variables than xi , then the actual associated circuit
generates hazard when xi switches. (The theorem of hazard)
Example E.21 The function f (A, B, C) = AB + BC, is hazardous because: f (1, B, 1) =
B + B.
The function g(A, B, C, D) = AD + BC + A B is hazardous because: g(A, 0, , 1) = A +
A , and g(0, B, 1, ) = B + B . Therefore, there are 4 input binary conguration generating

hazardous conditions.
Dynamic hazard
The hazard generated by asynchronous inputs occurs in circuits after a rst level of gates. The
propagation hazard needs a logic sum of products (2 or 3 levels of gates). The dynamic hazard
is generated by similar causes but manifests in circuits having more than 3 layers of gates. In
Figure E.21 few simple dynamic hazards are shown.
384
A
X
Z
1
B
1
0
D
C
c.
b.
0
A
0
Y
a.
6
-
B
A
1
B
1
1
C
d.
e.
D
Figure E.19: The typical example of propagation hazard. a. The circuit. b. The wave forms.
c. The VK diagram of the function executed by the circuit. d. The added surface allowing the
behavior of the circuit to have a continuous 1 surface. e. The equivalent circuit without hazard.
There are complex and not very ecient techniques to avoid dynamic hazard. Usually it
is preferred to transform the logic in sums of products (enlarging the circuit) and to apply
procedures used to remove propagation hazard (enlarging again the circuit).
E.7
Fundamental limits in implementing automata
Because of the problems generated in the real world by the hazardous behaviors some fundamental limitations are applied when an actual automaton works.
The asynchronous input bits can be interpreted only independently in distinct
states. In each clock cycle the automaton interprets the bits used to determine the transition form the current state. If more than one of these bits are asynchronous the reduced
dependency coding style must be applied for all of them. But, as we know, this is impossible,
only one bit can be considered with reduced dependency. Therefore, in each state no more than
one tested bit can be asynchronous. If more than one is asynchronous, then the denition of the
automaton must be modied introducing additional states.
E.7. FUNDAMENTAL LIMITS IN IMPLEMENTING AUTOMATA
A
1
A
1
B
1
a.
B
1
D
1
385
D
1
c.
b.
Figure E.20: a. A hazardous combinational circuit. b. A partial solution to avoid the hazard.
c. A full protection with two additional surfaces.
6
6
-
6
0
6
-
Figure E.21: Examples of dynamic hazards.

Immediate Mealy automaton with asynchronous inputs has no actual implementation The outputs of an immediate Mealy automaton are combinational conditioned by inputs.
Therefore, an asynchronous input will determine untolerable asynchronous transitions on some
or on all of the outputs.
Delayed Mealy automaton can not be implemented with asynchronous input variables Even if all the asynchronous inputs are took into consideration properly when the state
code are assigned, the assemble formed by the state register plus the output register works
wrong. Indeed, if at least one state bit and one output bit change triggered by an asynchronous
input there is the risk that the output register to be loaded with a value unrelated with the
value loaded into the state register.
Hazard free Moore automaton with asynchronous inputs has no actual implementation Asynchronous inputs involve coding with reduced dependency encoding. Hazard free
outputs ask coding with minimal variation. But, these two codding styles are incompatible.
386
Appendix F
# Meta-stability
Any asynchronous signal applied the the input of a clocked circuit is a source of meta-stability
[webRef 1]. There is a dangerous timing window centered on the clock transition edge
specied by the sum of set-up time, edge transition time and hold time. If the data input of a
D-FF switches in this window, then there are three possible behaviors for its output:
the output does not change according to the change on the ip-ops input (the ip-op
does not catch the input variation)
the output change according to the change on the ip-ops input (the ip-op catches
the input variation)
the output goes meta-stable for tM S , then goes unpredictable in 1 or 0 (see the wave forms
[webRef 2]).
387
388
APPENDIX F. # META-STABILITY
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Loops and Complexity in Digital Systems

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Loops & Complexity

Lecture Notes on Digital Design

The price for the clarity and simplicity of a reasonable

A BIRDS-EYE VIEW ON DIGITAL SYSTEMS

1 WHATS A DIGITAL SYSTEM?

2 LETS TALK IN VERILOG!

3 GROWING & SPEEDING & FEATURING

4 THE TAXONOMY OF DIGITAL SYSTEMS

5 OUR FINAL TARGET

LOOPING IN THE DIGITAL DOMAIN

Concluding about combinational circuits . . . . . . . . . . . . . . . . . . . . . . . 149

D Standard cell libraries

Two input XOR: XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

WHATS A DIGITAL SYSTEM?

CHAPTER 1. WHATS A DIGITAL SYSTEM?

Talking about Apple, Steve said, The system

Framing the digital design domain

1.1. FRAMING THE DIGITAL DESIGN DOMAIN

CHAPTER 1. WHATS A DIGITAL SYSTEM?

1.2. SIMPLE INTRODUCTORY EXAMPLES

Simple introductory examples

CHAPTER 1. WHATS A DIGITAL SYSTEM?

1.2. SIMPLE INTRODUCTORY EXAMPLES

The Verilog code describing the module adder is:

CHAPTER 1. WHATS A DIGITAL SYSTEM?

1.2. SIMPLE INTRODUCTORY EXAMPLES

CHAPTER 1. WHATS A DIGITAL SYSTEM?

= 15, out = 1111

1.2. SIMPLE INTRODUCTORY EXAMPLES

sum = in1 + in0

CHAPTER 1. WHATS A DIGITAL SYSTEM?

cry = com[0] ? carry : 0

always @(posedge clk) if (com[1]) carry = cryOut;

The way this module is used is explained in the folowing simulation:

The result of simulation is:

1.2. SIMPLE INTRODUCTORY EXAMPLES

The result of synthesis is presented in Figure 1.6, where:

Figure 1.6: Sequential adder.

CHAPTER 1. WHATS A DIGITAL SYSTEM?

name1.name2 : selects the signal name2 from the module name1

Dierent embodiment of digital systems

1.4. CORRELATED DOMAINS

CHAPTER 1. WHATS A DIGITAL SYSTEM?

Embedded systems In an advanced stage of development of digital system the physical

= in0 + in1 + crIn

CHAPTER 1. WHATS A DIGITAL SYSTEM?

Problem 1.2 Draw the block schematic of the following design:

Synthesize it to test your solution.

LETS TALK IN VERILOG!

CHAPTER 2. LETS TALK IN VERILOG!

Pseudo-code languages & algorithms

From [Mindell 00] pag. 41

2.2. FINITE INPUT VS. INFINITE INPUT ALGORITHMS

A pseudo-program is a procedure and it can calls other procedures. Thus, an algorithm is

Finite input vs. innite input algorithms

CHAPTER 2. LETS TALK IN VERILOG!

pattern_1[7:0], ... , pattern_m[7:0],

Now we have three kinds of input variables: