What Is A Timing Diagram
What Is A Timing Diagram
What Is A Timing Diagram
The timing diagram is the diagram which provides information about the various conditions of signals
such as high/low, when a machine cycle is being executed. Without the knowledge of timing diagram
it is not possible to match the peripheral devices to the microprocessors. These peripheral devices
includes memories, ports etc. Such devices can only be matched with microprocessors with the help of
timing diagram.
Instruction cycle:
Assume that the microprocessor is executing an instruction. Instruction cycle is nothing but the time
taken to complete the execution of that instruction by the microprocessor. The 8085 instruction cycle
consists of 1 to 6 machine cycles.
Machine Cycle:
Machine cycle is nothing but the time required to complete one operation of accessing memory, I/O. It
is also the time required to complete one operation of acknowledging an external request. One
machine cycle may consist of 3 to 6 T-states.
T-state:
T-state is nothing but one subdivision of the operation performed in one clock period. These
subdivisions are internal state of the microprocessor synchronized with system clock.
2) What is Instruction Execution Cycle:
Once a program is in memory it has to be executed. To do this, each instruction must be looked at,
decoded and acted upon in turn until the program is completed. This is achieved by the use of what is
termed the 'instruction execution cycle', which is the cycle by which each instruction in turn is
processed. However, to ensure that the execution proceeds smoothly, it is is also necessary to
synchronise the activites of the processor.
To keep the events synchronised, the clock located within the CPU control unit is used. This produces
regular pulses on the system bus at a specific frequency, so that each pulse is an equal time following
the last. This clock pulse frequency is linked to the clock speed of the processor - the higher the clock
speed, the shorter the time between pulses. Actions only occur when a pulse is detected, so that
commands can be kept in time with each other across the whole computer unit.
The instruction execution cycle can be clearly divided into three different parts, which will now be
looked at in more detail. For more on each part of the cycle click the relevant heading, or use the next
arrow as before to proceed though each stage in order.
Fetch Cycle
The fetch cycle takes the address required from memory, stores it in the instruction register, and moves
the program counter on one so that it points to the next instruction.
Decode Cycle
Here, the control unit checks the instruction that is now stored within the instruction register. It
determines which opcode and addressing mode have been used, and as such what actions need to be
carried out in order to execute the instruction in question.
Execute Cycle
The actual actions which occur during the execute cycle of an instruction depend on both the
instruction itself, and the addressing mode specified to be used to access the data that may be required.
However, four main groups of actions do exist, which are discussed in full later on.
Asynchronous mode Asynchronous mode is also known as start-stop mode. This mode is used when
data to be transmitted is generated at random intervals. For example, when a user communicates with a
computer using a keyboard, the time interval between two successive keystrokes is random. This
means that the signal on the transmission line will be in idle state for a long time interval between
characters. With this type of communication, the receiver must be able to resynchronize at the start of
each new character received. To accomplish this, each transmitted character or byte is encapsulated
between an additional start bit and one or more stop bits. This mode is mainly used for the
transmission of characters between a keyboard and a computer. Asynchronous transmission can also
be used for the transmission of a block of characters or bytes between two computers. The time
interval between successive characters is a variable entity.