Placement Question-Unit 1 Vlsi Design

VLSI DESIGN
Unit-I
1. Which logic family combines the advantages of CMOS and TTL?
A. BiCMOS B. TTL/CMOS C. ECL
D. TTL/MOS
ANS:A
2. Which is not a MOSFET terminal?

A. Gate
B.Drain
ANS:D
C.Source
D.Base
3.What is meant by the fan-out of a logic gate?

a.The number of other gates that can be connected to one of the gate's inputs.
b.The amount of cooling required by the gate.
c.The number of other gates that can be connected to the gate's output.
d.The physical distance between the output pins on the device.
ANS:C
4.Which of the following statements is incorrect?

a.CMOS gates have logic levels close to the supply rails.
b.Most CMOS circuits operate from a single supply voltage of from 5 to 15 V.
c.CMOS gates have very good noise immunity that is typically 10% of the supply voltage.
d.When a CMOS gate is static it has negligible power consumption.
ANS:C
5. CMOS logic has the property of
A. increased capacitance and delay.
C. high noise margin.
B. decreased area.
D.low static power dissipation.
ANS:D
6. What is the cause of storage time in a bipolar transistor?

a.The inertia of the minority charge carriers.
b.The memory effect of the device.
c.The inertia of the majority charge carriers.
d.The time taken to remove excess charge stored in the base region as a result of saturation.
ANS:D
7. Which transistor element is used in CMOS logic?
A. FET
B. MOSFET
C. Bipolar
D. Unijunction
ANS:B
8. What is meant by the rise time of a waveform?

a.The time delay from when the input step changes by 50% to when the output step changes by 50%.
b.The time taken for the waveform to increase from 10% to 90% of the height of a step.
c.The time taken for the waveform to increase from 0% to 90% of the height of a step.
d.The time taken for the waveform to decrease from 90% to 10% of the height of a step.
ANS:B
9. PMOS and NMOS circuits are used largely in ________.
A. MSI functions
B. LSI functions
C. diode functions
D. TTL functions
10. Which is not a precaution for handling CMOS?
ANS:B
A. Devices should be placed with pins down on a grounded surface, such as a metal plate.
B. All tools, test equipment, and metal workbenches should be earth grounded.
C. CMOS devices should not be inserted into sockets or PC boards with the power on.
D. Wear wool clothes at all times.
ANS:D
11. Which factor does not affect CMOS loading?

A. Charging time associated with the output resistance of the driving gate
B. Discharging time associated with the output resistance of the driving gate
C. Output capacitance of the load gates
D. Input capacitance of the load gates
ANS:C
12. Which of the following statements is incorrect?

a. ECL is one of the fastest forms of electronic logic.
b. ECL has high power consumption.
c. ECL is widely used in high-speed applications.
d. ECL suffers from low noise immunity.
ANS:C
13. What are the modes in an Enhancement MOS transistor?

A.Accumulation mode
B.Depletion mode
C.Inversion mode
D.all of the above
Ans:D
14. Chip utilization depends on ___.

A. Only on standard cells
C. Only on macros
ANS:B
B. Standard cells and macros

d. Standard cells macros and IO pads
15. What are the advantages of Silicon-on-Insulator process?

A. No Latch-up
B. Due to absence of bulks transistor structures are denser than bulk silicon.
C. A&B
D. None of the above
ANS:C
16. CMOS means
a. Complimentary mean oxide Silicon
b. Complementary metal oxide Silicon
c. Compound mean oxide Silicon
d. Compound metal oxide Silicon
17. The fastest switching logic family is
A. CMOS.
B. TTL.
C. DTL.
ANS:B
D. ECL.
18. The charge coupled devices are implemented using

A. CMOS Technology
B. PMOS Technology
C. MOS Technology
D. NMOS Technology
19.Channel length is varied due to
Ans:D
ANS:C
Vds
C. Changes in Vds & Vgs
A. Changes in
B. Changes in Vgs
Ans: A
D. None of the above
20. Leakage power is inversely proportional to ___.

a. Frequency b. Load Capacitance
c. Supply voltage
d. Threshold Voltage
21. PMOS and NMOS circuits are used largely in_________

A.MSI function
B.LSI function
C. Diode function
D. TTL function
22. What are the steps involved in Twin-tub process?

A. Thin oxide Construction
B. Source & Drain Implantation
C. Metallization
D. all of the above
Ans: D
Ans: B
Ans: D
23. At what condition, nMOS transistor is in linear region?
A.Vgs<Vt
B. Vgs>Vt
C. Vds<Vgs -Vt
D. Vds.>Vgs -Vt
Ans:C
D. n/p =0
Ans: A
D. all of the above
Ans: D
24. At what value is suitable for CMOS inverter

A. n/p
=1
B. n/p =10
C. n/p =0.1
25. What are the different operating regions for an MOS transistor?
A. Cutoff region
B. Saturation region C. Linear region

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VLSI DESIGN

2. Which is not a MOSFET terminal?

3.What is meant by the fan-out of a logic gate?

4.Which of the following statements is incorrect?

6. What is the cause of storage time in a bipolar transistor?

8. What is meant by the rise time of a waveform?

11. Which factor does not affect CMOS loading?

12. Which of the following statements is incorrect?

13. What are the modes in an Enhancement MOS transistor?

14. Chip utilization depends on ___.

B. Standard cells and macros

15. What are the advantages of Silicon-on-Insulator process?

18. The charge coupled devices are implemented using

19.Channel length is varied due to

D. None of the above

20. Leakage power is inversely proportional to ___.

21. PMOS and NMOS circuits are used largely in_________

22. What are the steps involved in Twin-tub process?

23. At what condition, nMOS transistor is in linear region?

D. all of the above

24. At what value is suitable for CMOS inverter

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