Chapter02 ComputerSystemsOrganization

Computer Systems Organization
Chapter 2
Processors
Figure 2-1. The organization of a simple computer with

one CPU and two I/O devices.
CPU Organization
Figure 2-2. The data path of a typical von Neumann machine.
Instruction Execution (1)
Fetch next instruction from memory

Change program counter to point to next instruction
Determine type of instruction just fetched
If instruction uses a word in memory, locate it
Fetch word, if needed, into a CPU register.
Execute instruction.
Go to step 1 to begin executing following instruction
...
Figure 2-3. An interpreter for a simple computer (written in Java).

...
Figure 2-3. An interpreter for a simple computer (written in Java).

Benefits of machines with interpreted instructions
Ability to fix incorrectly implemented instructions in field,
even make up for design deficiencies in basic hardware
Opportunity to add new instructions at minimal cost,
even after delivery of machine
Structured design that permitted efficient development,
testing, documenting of complex instructions
Design Principles for Modern Computers
All instructions directly executed by hardware

Maximize rate at which instructions are issued
Instructions should be easy to decode
Only loads and stores should reference memory
Provide plenty of registers
Pipelining
Figure 2-4. (a) A five-stage pipeline. (b) The state of each stage as
a function of time. Nine clock cycles are illustrated
Superscalar Architectures (1)
Figure 2-5. Dual five-stage pipelines

with a common instruction fetch unit.
Superscalar Architectures (2)
Figure 2-6. A superscalar processor with five functional units.
Data Parallel Computers
Figure 2-7. The SIMD core of the Fermi graphics processing unit.
Multiprocessors (1)
Figure 2-8. (a) A single-bus multiprocessor.
Multiprocessors (1)
Figure 2-8(b) A multicomputer with local memories.
Primary Memory (1)

The part of computer where programs and data are stored
Bit: binary digit
Memory address: location in memory of a cell containing data
Primary Memory (2)
Figure 2-9. Three ways of organizing a 96-bit memory
Primary Memory (3)
Figure 2-10. Number of bits per cell for some historically

interesting commercial computers.
Byte Ordering (1)
Figure 2-11. (a) Big endian memory. (b) Little endian memory.
Byte Ordering (2)
Figure 2-12. (a) A personnel record for a big endian machine.

(b) The same record for a little endian machine.
Byte Ordering (3)
Figure 2-12. (c) The result of transferring the record from a

big endian to a little endian. (d) The result of byte swapping (c).
Error-Correcting Codes (1)
Figure 2-13. Number of check bits for a code

that can correct a single error.
Figure 2-14. (a) Encoding of 1100.

(b) Even parity added.
(c) Error in AC.
Figure 2-15. Construction of the Hamming code

for the memory word 1111000010101110 by
adding 5 check bits to the 16 data bits.
Cache Memory
Figure 2-16. The cache is logically between the CPU

and main memory. Physically, there are several
possible places it could be located.
Memory Packaging and Types
Figure 2-17. Top view of a DIMM holding 4 GB with eight

chips of 256 MB on each side. The other side looks the same.
Secondary Memory
Memory Hierarchies
Figure 2-18. A five-level memory hierarchy.
Magnetic Disks (1)
Figure 2-19. A portion of a disk track. Two sectors are illustrated.
Magnetic Disks (2)
Figure 2-20. A disk with four platters.
Magnetic Disks (3)
Figure 2-21. A disk with five zones. Each zone has many tracks.
SCSI Disks
Figure 2-22. Some of the possible SCSI parameters
RAID (1)
Figure 2-23. RAID levels 0 through 5. Backup and

parity drives are shown shaded.
RAID (2)
Figure 2-23. RAID levels 0 through 5. Backup and

parity drives are shown shaded.
Solid-State Disks
Figure 2-24. A flash memory cell.
CD-ROMs (1)
Figure 2-25. Recording structure of a Compact Disc or CD-ROM.
CD-ROMs (2)
Figure 2-26. Logical data layout on a CD-ROM.
CD-Recordables
Figure 2-27. Cross section of a CD-R disk and laser (not to scale).
A CD-ROM has a similar structure, except without the dye layer
and with a pitted aluminum layer instead of a reflective layer.
DVD (1)
Was Digital Video Disk
Now Digital Versatile Disk
New features
1. Smaller pits
2. A tighter spiral
3. A red laser
DVD (2)
Formats:
Single-sided, single-layer (4.7 GB)
Single-sided, dual-layer (8.5 GB)
Double-sided, single-layer (9.4 GB)
Double-sided, dual-layer (17 GB)
DVD (3)
Figure 2-28 A double sided, dual layer DVD disk.
Input/Output Buses (1)
Figure 2-29. Physical structure of a personal computer.
Buses (2)
Figure 2-30. Logical structure of a simple personal computer.
PCI and PCIe Buses (1)
Figure 2-31. A typical PC built around the PCI bus. The SCSI
controller is a PCI device.
PCI and PCIe Buses (2)
Figure 2-32. Sample architecture of a PCIe system

with three PCIe ports.
Terminals
Figure 2-33. (a) The construction of an LCD screen.

(b) The grooves on the rear and front plates are
perpendicular to one another.
Mice
Figure 2-34. A mouse being used to point to menu items.
Game Controllers (1)
Figure 2-35. The Wiimote video game controller motion sensors.
Game Controllers (2)
Figure 2-35. The Wiimote video game controller motion sensors.
Laser Printers (1)
Figure 2-36. Operation of a laser printer.
Laser Printers (2)
Figure 2-37. Halftone dots for various grayscale ranges. (a) 06.
(b) 1420. (c) 2834. (d) 5662. (e) 105111. (f) 161167.
Color Printing
Color monitors use transmitted light;
Color printers use reflected light.
Monitors have 256 intensities per color;
Color printers must halftone.
Monitors have a dark background;
Paper has a light background.
The RGB gamut of a monitor and the CMYK gamut of a
printer are different.
Modems
Figure 2-38. Transmission of the binary number 01001011000100

over a telephone line bit by bit. (a) Two-level signal. (b) Amplitude
modulation. (c) Frequency modulation. (d) Phase modulation.
Digital Subscriber Lines (1)
Figure 2-39. Operation of ADSL.
Digital Subscriber Lines (2)
Figure 2-40. A typical ADSL equipment configuration.
Internet over Cable (1)
Problems to overcome:
How to add Internet access without interfering with TV
programs.
How to have two-way traffic when amplifiers are
inherently one way.
Figure 2-41. Frequency allocation in a typical cable

TV system used for Internet access.
Figure 2-42. Typical details of the upstream and downstream

channels in North America. QAM-64 allows 6 bits/Hz but works
only at high frequencies. QPSK works at low frequencies but
allows only 2 bits/Hz.
Digital Cameras
Figure 2-43. A digital camera.
Character Codes (1)
Figure 2-44. The ASCII character set.
Character Codes (2)
Figure 2-44. The ASCII character set.
Character Codes (3)
Figure 2-45. The UTF-8 encoding scheme.
End
Chapter 2

Chapter02 ComputerSystemsOrganization

Uploaded by

Copyright:

Available Formats

Chapter02 ComputerSystemsOrganization

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter02 ComputerSystemsOrganization

Uploaded by

Copyright:

Available Formats

Computer Systems Organization

Figure 2-1. The organization of a simple computer with

Figure 2-2. The data path of a typical von Neumann machine.

Instruction Execution (1)

Fetch next instruction from memory

Instruction Execution (3)

Instruction Execution (4)

Figure 2-3. An interpreter for a simple computer (written in Java).

Instruction Execution (5)

Design Principles for Modern Computers

All instructions directly executed by hardware

Superscalar Architectures (1)

Figure 2-5. Dual five-stage pipelines

Superscalar Architectures (2)

Figure 2-6. A superscalar processor with five functional units.

Data Parallel Computers

Figure 2-8. (a) A single-bus multiprocessor.

Figure 2-8(b) A multicomputer with local memories.

Primary Memory (1)

Primary Memory (2)

Figure 2-9. Three ways of organizing a 96-bit memory

Primary Memory (3)

Figure 2-10. Number of bits per cell for some historically

Byte Ordering (1)

Byte Ordering (2)

Figure 2-12. (a) A personnel record for a big endian machine.

Byte Ordering (3)

Figure 2-12. (c) The result of transferring the record from a

Error-Correcting Codes (1)

Figure 2-13. Number of check bits for a code

Error-Correcting Codes (2)

Figure 2-14. (a) Encoding of 1100.

Error-Correcting Codes (3)

Figure 2-15. Construction of the Hamming code

Figure 2-16. The cache is logically between the CPU

Memory Packaging and Types

Figure 2-17. Top view of a DIMM holding 4 GB with eight

Figure 2-18. A five-level memory hierarchy.

Magnetic Disks (1)

Figure 2-19. A portion of a disk track. Two sectors are illustrated.

Magnetic Disks (2)

Figure 2-20. A disk with four platters.

Magnetic Disks (3)

Figure 2-22. Some of the possible SCSI parameters

Figure 2-23. RAID levels 0 through 5. Backup and

Figure 2-23. RAID levels 0 through 5. Backup and

Figure 2-24. A flash memory cell.

Figure 2-25. Recording structure of a Compact Disc or CD-ROM.

Figure 2-26. Logical data layout on a CD-ROM.

Figure 2-28 A double sided, dual layer DVD disk.

Input/Output Buses (1)

Figure 2-29. Physical structure of a personal computer.

Figure 2-30. Logical structure of a simple personal computer.

PCI and PCIe Buses (1)

PCI and PCIe Buses (2)

Figure 2-32. Sample architecture of a PCIe system

Figure 2-33. (a) The construction of an LCD screen.

Figure 2-34. A mouse being used to point to menu items.