PD - 14275D

IRFB4310PbF
IRFS4310PbF
IRFSL4310PbF
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits

HEXFET Power MOSFET

D

Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free

VDSS
RDS(on) typ.
max.
ID

S
D
G

S
D
G

S
D
G

D2Pak
IRFS4310PbF

TO-220AB
IRFB4310PbF

100V
5.6m:
7.0m:
130A

TO-262
IRFSL4310PbF

Absolute Maximum Ratings

Symbol

Parameter

Max.

Continuous Drain Current, VGS @ 10V

130

ID @ TC = 100C

Continuous Drain Current, VGS @ 10V

92

IDM

Pulsed Drain Current

550

PD @TC = 25C

Maximum Power Dissipation

W
W/C
V

Linear Derating Factor

2.0

Gate-to-Source Voltage

20

dV/dt
TJ

Peak Diode Recovery

14

Operating Junction and

TSTG

Storage Temperature Range

V/ns
C

-55 to + 175
300

Soldering Temperature, for 10 seconds

(1.6mm from case)

Avalanche Characteristics
EAS (Thermally limited)

Single Pulse Avalanche Energy

IAR

Avalanche Current

EAR

Repetitive Avalanche Energy

10lb in (1.1N m)

Mounting torque, 6-32 or M3 screw

c

300

VGS

Units

c
c

ID @ TC = 25C

980

mJ

See Fig. 14, 15, 22a, 22b,

A
mJ

Thermal Resistance
Symbol

Parameter

Typ.

Max.

0.50

Case-to-Sink, Flat Greased Surface , TO-220

0.50

Junction-to-Ambient, TO-220

62

40

RJC

Junction-to-Case

RCS
RJA
RJA

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Junction-to-Ambient (PCB Mount) , D Pak

jk

Units
C/W

1
01/31/06

IRF/B/S/SL4310PbF
Static @ TJ = 25C (unless otherwise specified)
Symbol

Parameter

V(BR)DSS
V(BR)DSS/TJ
RDS(on)
VGS(th)
IDSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current

IGSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage
Gate Input Resistance

RG

Min. Typ. Max. Units

100
0.064

5.6
7.0
2.0

4.0

20
250
200
-200

1.4

Conditions

V VGS = 0V, ID = 250A

V/C Reference to 25C, ID = 1mA
m VGS = 10V, ID = 75A
V VDS = VGS, ID = 250A
A VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125C
nA VGS = 20V
VGS = -20V
f = 1MHz, open drain

Dynamic @ TJ = 25C (unless otherwise specified)

Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)

Parameter

Min. Typ. Max. Units

Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)

160
170

46

62

26
110

68

78
7670
540
280
650
720.1

250

S
nC

Conditions
VDS = 50V, ID = 75A
ID = 75A
VDS = 80V
VGS = 10V
VDD = 65V
ID = 75A
RG = 2.6
VGS = 10V
VGS = 0V
VDS = 50V
= 1.0MHz
VGS = 0V, VDS = 0V to 80V
VGS = 0V, VDS = 0V to 80V

ns

pF

j, See Fig.11
h, See Fig. 5

Diode Characteristics
Symbol

Parameter

IS

Continuous Source Current

ISM

(Body Diode)
Pulsed Source Current

VSD
trr

(Body Diode)
Diode Forward Voltage
Reverse Recovery Time

Qrr

Reverse Recovery Charge

IRRM
ton

Reverse Recovery Current

Forward Turn-On Time

di

Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25C, L = 0.35mH
RG = 25, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
ISD 75A, di/dt 550A/s, VDD V(BR)DSS, TJ 175C.
Pulse width 400s; duty cycle 2%.

Min. Typ. Max. Units

130

550

Conditions
MOSFET symbol

showing the
integral reverse

p-n junction diode.

1.3
V TJ = 25C, IS = 75A, VGS = 0V
VR = 85V,

45
68
ns TJ = 25C
TJ = 125C
IF = 75A

55
83
di/dt = 100A/s

82
120
nC TJ = 25C
T
=
125C
120 180
J

3.3

A TJ = 25C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.

Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.

When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
footprint and soldering techniques refer to application note #AN-994.

R is measured at TJ approximately 90C.

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IRF/B/S/SL4310PbF
1000

1000

100
BOTTOM

10

BOTTOM

100

4.5V

60s PULSE WIDTH

Tj = 25C

4.5V
0.1

10

0.1

100

10

100

VDS, Drain-to-Source Voltage (V)

VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

3.0

RDS(on) , Drain-to-Source On Resistance

(Normalized)

1000

ID, Drain-to-Source Current()

60s PULSE WIDTH

Tj = 175C

10

100

TJ = 175C

10

TJ = 25C
VDS = 50V

60s PULSE WIDTH

1
3.0

4.0

5.0

6.0

7.0

ID = 75A
VGS = 10V
2.5

2.0

1.5

1.0

0.5

8.0

-60 -40 -20

VGS, Gate-to-Source Voltage (V)

12000

VGS, Gate-to-Source Voltage (V)

Coss = Cds + Cgd

Ciss

8000

6000

4000

2000

Coss
Crss
10

100

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage

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ID= 75A
VDS = 80V
VDS= 50V
VDS= 20V

16

12

0
1

20 40 60 80 100 120 140 160 180

Fig 4. Normalized On-Resistance vs. Temperature

20

VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd

10000

TJ , Junction Temperature (C)

Fig 3. Typical Transfer Characteristics

C, Capacitance (pF)

VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V

TOP

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

TOP

VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V

40

80

120

160

200

240

280

QG Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

IRF/B/S/SL4310PbF
10000

ID, Drain-to-Source Current (A)

ISD , Reverse Drain Current (A)

1000.0

TJ = 175C
100.0

10.0

TJ = 25C
1.0

OPERATION IN THIS AREA

LIMITED BY R DS (on)
1000

100

100sec

10

VGS = 0V
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

V(BR)DSS , Drain-to-Source Breakdown Voltage

140

ID, Drain Current (A)

Limited By Package

100
80
60
40
20
0
25

50

75

100

125

150

100

1000

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

120

10

VDS , Drain-toSource Voltage (V)

VSD , Source-to-Drain Voltage (V)

120

115

110

105

100
-60 -40 -20 0

175

20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (C)

T C , Case Temperature (C)

Fig 9. Maximum Drain Current vs.

Case Temperature

Fig 10. Drain-to-Source Breakdown Voltage

EAS, Single Pulse Avalanche Energy (mJ)

4.0
3.5
3.0

Energy (J)

10msec
DC

0.1

0.1

2.5
2.0
1.5
1.0
0.5
0.0

2400

I D
12A
17A
BOTTOM 75A
TOP

2000

1600

1200

800

400

0
0

20

40

60

80

100

VDS, Drain-to-Source Voltage (V)

Fig 11. Typical COSS Stored Energy

1msec

Tc = 25C
Tj = 175C
Single Pulse

120

25

50

75

100

125

150

175

Starting TJ, Junction Temperature (C)

Fig 12. Maximum Avalanche Energy Vs. DrainCurrent

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IRF/B/S/SL4310PbF
1

Thermal Response ( ZthJC )

D = 0.50
0.1

0.20
0.10
0.05

0.01

0.02
0.01

R1
R1
J
1

R2
R2
C
2

Ri (C/W) i (sec)
0.1962 0.00117
0.2542

0.016569

Ci= i/Ri
Ci= i/Ri

0.001

Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150C
and Tstart =25C (Single Pulse)

Duty Cycle = Single Pulse

Avalanche Current (A)

0.01
0.05

10

0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25C and
Tstart = 150C.

0.1
1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

EAR , Avalanche Energy (mJ)

1000

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A

800

600

400

200

0
25

50

75

100

125

150

175

Starting TJ , Junction Temperature (C)

Fig 15. Maximum Avalanche Energy vs. Temperature

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PD (ave) = 1/2 ( 1.3BVIav) = DT/ ZthJC

Iav = 2DT/ [1.3BVZth]
EAS (AR) = PD (ave)tav

IRF/B/S/SL4310PbF
20

ID = 1.0A
ID = 1.0mA
ID = 250A

4.0

16

IRRM - (A)

VGS(th) Gate threshold Voltage (V)

5.0

3.0

12

8
IF = 30A
VR = 85V

2.0

TJ = 125C
TJ = 25C
1.0

0
-75 -50 -25

25

50

75

100 125 150 175

100 200 300 400 500 600 700 800 900 1000

TJ , Temperature ( C )

dif / dt - (A / s)

Fig. 17 - Typical Recovery Current vs. dif/dt

20

500

16

400

QRR - (nC)

IRRM - (A)

Fig 16. Threshold Voltage Vs. Temperature

12

IF = 45A
VR = 85V

300

200
IF = 30A
VR = 85V

100

TJ = 125C
TJ = 25C

TJ = 125C
TJ = 25C
0

0
100 200 300 400 500 600 700 800 900 1000

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / s)

dif / dt - (A / s)

Fig. 19 - Typical Stored Charge vs. dif/dt

Fig. 18 - Typical Recovery Current vs. dif/dt

500

QRR - (nC)

400

300

200

100

IF = 45A
VR = 85V
TJ = 125C
TJ = 25C

0
100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / s)

Fig. 20 - Typical Stored Charge vs. dif/dt

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IRF/B/S/SL4310PbF
D.U.T

Driver Gate Drive

D.U.T. ISD Waveform

Reverse
Recovery
Current

RG

dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test

VDD

P.W.
Period
VGS=10V

Circuit Layout Considerations

Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer

D=

Period

P.W.

+
-

Body Diode Forward

Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt

Re-Applied
Voltage

Body Diode

VDD

Forward Drop

Inductor
Current
Inductor Curent
ISD

Ripple 5%

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET Power MOSFETs
V(BR)DSS
15V

DRIVER

VDS

tp

D.U.T

RG

+
V
- DD

IAS
VGS
20V

tp

0.01

I AS

Fig 22a. Unclamped Inductive Test Circuit

Fig 22b. Unclamped Inductive Waveforms

LD

VDS

VDS

90%
+
VDD -

10%

D.U.T

VGS

VGS
Pulse Width < 1s
Duty Factor < 0.1%

td(on)

Fig 23a. Switching Time Test Circuit

tr

td(off)

tf

Fig 23b. Switching Time Waveforms

Id
Vds
Vgs

L
VCC
DUT

Vgs(th)

1K

Qgs1 Qgs2

Fig 24a. Gate Charge Test Circuit

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Qgd

Qgodr

Fig 24b. Gate Charge Waveform

IRF/B/S/SL4310PbF
TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

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TO-220AB packages are not recommended for Surface Mount Application.

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IRF/B/S/SL4310PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

(;$03/( 7+,6,6$1,5//
/27&2'(
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3$57180%(5

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IRF/B/S/SL4310PbF
D2Pak (TO-263AB) Package Outline

Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information

7+,6,6$1,5)6:,7+
/27&2'(
$66(0%/('21::
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IRF/B/S/SL4310PbF
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)

FEED DIRECTION 1.85 (.073)

1.65 (.065)

1.60 (.063)
1.50 (.059)

11.60 (.457)
11.40 (.449)

0.368 (.0145)
0.342 (.0135)

15.42 (.609)
15.22 (.601)

24.30 (.957)
23.90 (.941)

TRL
10.90 (.429)
10.70 (.421)

1.75 (.069)
1.25 (.049)

4.72 (.136)
4.52 (.178)

16.10 (.634)
15.90 (.626)

FEED DIRECTION

13.50 (.532)
12.80 (.504)

27.40 (1.079)
23.90 (.941)
4

330.00
(14.173)
MAX.

NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

60.00 (2.362)
MIN.

26.40 (1.039)
24.40 (.961)
3

30.40 (1.197)
MAX.
4

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IRs Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 01/06

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11

Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/