Fdb045An08A0: N-Channel Powertrench Mosfet

FDB045AN08A0
N-Channel PowerTrench MOSFET

75 V, 80 A, 4.5 m
Features
Applications
RDS(on) = 3.9 m ( Typ.) @ VGS = 10 V, ID = 80 A
Synchronous Rectification for ATX / Server / Telecom PSU
QG(tot) = 92 nC ( Typ.) @ VGS = 10 V
Battery Protection Circuit
Low Miller Charge
Motor drives and Uninterruptible Power Supplies
Low Qrr Body Diode

UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82684
D
D
D2-PAK
MOSFET Maximum Ratings TC = 25C unless otherwise noted

Symbol
VDSS
VGS
Drain to Source Voltage
FDB045AN08A0
75
Units
V
Gate to Source Voltage
20
90
19
Parameter
Drain Current
ID
Continuous (TC < 137oC, VGS = 10V)
Continuous (Tamb = 25oC, VGS = 10V, with RJA = 43oC/W)

Pulsed
EAS
PD
TJ, TSTG
Figure 4
Single Pulse Avalanche Energy (Note 1)
600
mJ
Power dissipation
310
Derate above 25oC
2.0
W/oC
Operating and Storage Temperature
-55 to 175
Thermal Characteristics
o
RJC
Thermal Resistance Junction to Case
RJA
Thermal Resistance Junction to Ambient (Note 2)
62
oC/W
RJA
Thermal Resistance Junction to Ambient, 1in2 copper pad area
43
2002 Fairchild Semiconductor Corporation

FDB045AN08A0 Rev. C1
0.48
C/W
C/W
www.fairchildsemi.com
FDB045AN08A0 N-Channel PowerTrench MOSFET
November 2013
Device Marking
FDB045AN08A0
Device
FDB045AN08A0
Package
D2-PAK
Reel Size
330 mm
Tape Width
24 mm
Quantity
800 units
Electrical Characteristics TC = 25C unless otherwise noted

Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
75
-
250
VGS = 20V
100
nA
VGS = VDS, ID = 250A
ID = 80A, VGS = 10V
0.0039 0.0045
ID = 37A, VGS = 6V
0.0056 0.0084
ID = 80A, VGS = 10V,

TJ = 175oC
0.008
0.011
6600
pF
1000
pF
240
pF
92
138
nC
11
17
nC
27
nC
16
nC
21
nC
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250A, VGS = 0V
VDS = 60V
VGS = 0V
TC = 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage

Drain to Source On Resistance
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain Miller Charge
VDS = 25V, VGS = 0V,

f = 1MHz
VDD = 40V
ID = 80A
Ig = 1.0mA
Switching Characteristics (VGS = 10V)

tON
Turn-On Time
160
ns
td(ON)
Turn-On Delay Time
18
ns
tr
Rise Time
88
ns
td(OFF)
Turn-Off Delay Time
40
ns
tf
Fall Time
45
ns
tOFF
Turn-Off Time
128
ns
VDD = 40V, ID = 80A

VGS = 10V, RGS = 3.3
Drain-Source Diode Characteristics

ISD = 80A
1.25
ISD = 40A
1.0
Reverse Recovery Time
ISD = 75A, dISD/dt = 100A/s
53
ns
Reverse Recovered Charge
ISD = 75A, dISD/dt = 100A/s
54
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25C, L = 0.48mH, IAS = 50A.
2: Pulse Width = 100s

Package Marking and Ordering Information
POWER DISSIPATION MULTIPLIER
1.2
200
CURRENT LIMITED
BY PACKAGE
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
160
120
80
40
0.2
0
0
25
50
75
100
150
125
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs

Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs

Case Temperature
ZJC, NORMALIZED
THERMAL IMPEDANCE
DUTY CYCLE - DESCENDING ORDER

0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZJC x RJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance

2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)
1000
CURRENT AS FOLLOWS:
I=
VGS = 10V
100
50
10-5
175 - TC
25
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability

Typical Characteristics TC = 25C unless otherwise noted
2000
500
10s
1000
100
IAS, AVALANCHE CURRENT (A)
100s
1ms
10ms
10
OPERATION
N IN THI
AREA MAY BE
LIMITED BY rDS(ON)
DC
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
0.1
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
STARTING TJ = 150oC
150
VGS = 7V
VGS = 10V
120
TJ = 175oC
60
TJ = -55oC
VGS = 6V
90
60
VGS = 5V
TC = 25oC
PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX
30
0
4.0
100
Figure 6. Unclamped Inductive Switching

Capability
30
0
4.5
5.0
5.5
VGS , GATE TO SOURCE VOLTAGE (V)
6.0
Figure 7. Transfer Characteristics
0.5
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
1.5
Figure 8. Saturation Characteristics

2.5

NORMALIZED DRAIN TO SOURCE

ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE(m)
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
ID , DRAIN CURRENT (A)
10
.01
90
TJ = 25oC
STARTING TJ = 25oC

VDD = 15V
120
100
100
Figure 5. Forward Bias Safe Operating Area
150
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
6
VGS = 6V
5
4
VGS = 10V
20
40
1.5
1.0
60
0.5
-80
80
Figure 9. Drain to Source On Resistance vs Drain

Current
2.0
VGS = 10V, ID =80A
3
0

-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature
4
1.2
1.15
ID = 250A
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250A
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
1.00
0.95
-40
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature
10000
VGS , GATE TO SOURCE VOLTAGE (V)
10
CISS = CGS + CGD
C, CAPACITANCE (pF)
1.05
0.90
-80
200
Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature
COSS CDS + CGD
1000
CRSS = CGD
VGS = 0V, f = MHz

100
0.1
1.10
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 80A
ID = 10A
0
75
Figure 13. Capacitance vs Drain to Source

Voltage

VDD = 40V
25
50
Qg, GATE CHARGE (nC)
75
100
Figure 14. Gate Charge Waveforms for Constant

Gate Currents
VDS
BVDSS
tP
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
VGS
VDS
IAS
VDD
VDD
DUT
tP
0V
IAS
0
0.01
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 10V
Qgs2
VDD
DUT
VGS = 2V
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
90%
VDD
10%
10%
DUT
90%
VGS
VGS
Figure 19. Switching Time Test Circuit

90%
VGS
RGS
tf
50%
10%
PULSE WIDTH
50%
Figure 20. Switching Time Waveforms
Test Circuits and Waveforms
The maximum rated junction temperature, TJM , and the

thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the applications ambient
temperature, TA (oC), and thermal resistance RJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
RJA = 26.51+ 19.84/(0.262+Area) EQ.2

RJA = 26.51+ 128/(1.69+Area) EQ.3
60
RJA (o C/W)
(T
T )
JM
A
P D M = ----------------------------R JA
80
40
(EQ. 1)
In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a
significant influence on the parts current and maximum
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
20
0.1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting

Pad Area
1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designers preliminary application evaluation. Figure 21
defines the RJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R
JA
19.84
( 0.262 + Area )
(EQ. 2)
= 26.51 + -------------------------------------
Area in Inches Squared
JA
128
( 1.69 + Area )
(EQ. 3)
= 26.51 + ----------------------------------
Area in Centimeters Squared

Thermal Resistance vs. Mounting Pad Area
.SUBCKT FDB045AN08A0 2 1 3 ;
CA 12 8 1.5e-9
CB 15 14 1.5e-9
CIN 6 8 6.4e-9
rev March 2002
DRAIN
2
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
ESLC
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 4.81e-9
LSOURCE 3 7 4.63e-9
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
+
LGATE
DBREAK
5
51
ESG
RLDRAIN
RSLC1
51
RSLC2
EBREAK 11 7 17 18 82.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN
DPLCAP
EVTHRES
+ 19 8
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
MMED
MSTRO
RLGATE
LSOURCE
CIN
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9e-4
RGATE 9 20 1.36
RLDRAIN 2 5 10
RLGATE 1 9 48.1
RLSOURCE 3 7 46.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
12
S1A
S2A
13
8
14
13
S1B
CA
RLSOURCE
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
VBAT
5
8
EDS
19
IT
14
+
EGS
SOURCE
3
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}
.MODEL DBODYMOD D (IS = 2.4e-11 N = 1.04 RS = 1.76e-3 TRS1 = 2.7e-3 TRS2 = 2e-7 XTI=3.9 CJO = 4.35e-9 TT = 1e-8
M = 5.4e-1)
.MODEL DBREAKMOD D (RS = 1.5e-1 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.35e-9 IS = 1e-30 N = 10 M = 0.53)
.MODEL MMEDMOD NMOS (VTO = 3.7 KP = 9 IS =1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36)
.MODEL MSTROMOD NMOS (VTO = 4.4 KP = 250 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 3.05 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36e1 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -9e-7)
.MODEL RDRAINMOD RES (TC1 = 1.9e-2 TC2 = 4e-5)
.MODEL RSLCMOD RES (TC1 = 1.3e-3 TC2 = 1e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -6e-3 TC2 = -1.9e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.0 VOFF= -1.5)

VON = -1.5 VOFF= -4.0)
VON = -1.0 VOFF= 0.5)
VON = 0.5 VOFF= -1.0)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
PSPICE Electrical Model
REV March 2002

template FDB045AN08A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.4e-11, n1 = 1.04, rs = 1.76e-3, trs1 = 2.7e-3, trs2 = 2e-7, xti = 3.9, cjo = 4.35e-9, tt = 1e-8, m = 5.4e-1)
dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 1.35e-9, isl =10e-30, nl =10, m = 0.53)
m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 3.05, kp = 0.03, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)
LDRAIN
DPLCAP
10
c.ca n12 n8 = 1.5e-9

c.cb n15 n14 = 1.5e-9
c.cin n6 n8 = 6.4e-9
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
ESG
+
LGATE
GATE
1
RDRAIN
6
8
EVTHRES
+ 19 8
EVTEMP
RGATE + 18 22
9
20
21
LSOURCE
7
RSOURCE
S1A
S2A
14
13
13
8
S1B
CA
EBREAK
+
17
18
-
MMED
CIN
DBODY
MWEAK
MSTRO
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
12
11
16
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -9e-7

res.rdrain n50 n16 = 9e-4, tc1 = 1.9e-2, tc2 = 4e-5
res.rgate n9 n20 = 1.36
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 48.1
res.rlsource n3 n7 = 46.3
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.3e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -6e-3, tc2 = -1.9e-5
DBREAK
50
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.81e-9
l.lsource n3 n7 = 4.63e-9
DRAIN
2
RLSOURCE
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
-
19
IT
14
+
EGS
SOURCE
3
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 82.3

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
}

SABER Electrical Model
th
REV 23 March 2002
JUNCTION
FDB045AN08A0T
CTHERM1 th 6 6.45e-3
CTHERM2 6 5 3e-2
CTHERM3 5 4 1.4e-2
CTHERM4 4 3 1.65e-2
CTHERM5 3 2 4.85e-2
CTHERM6 2 tl 1e-1
RTHERM1
CTHERM1
RTHERM1 th 6 3.24e-3
RTHERM2 6 5 8.08e-3
RTHERM3 5 4 2.28e-2
RTHERM4 4 3 1e-1
RTHERM5 3 2 1.1e-1
RTHERM6 2 tl 1.4e-1
RTHERM2
CTHERM2
SABER Thermal Model

SABER thermal model FDB045AN08A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.45e-3
ctherm.ctherm2 6 5 = 3e-2
ctherm.ctherm3 5 4 = 1.4e-2
ctherm.ctherm6 2 tl = 1e-1
RTHERM3
CTHERM3
RTHERM4
rtherm.rtherm1 th 6 = 3.24e-3
rtherm.rtherm2 6 5 = 8.08e-3
rtherm.rtherm4 4 3 = 1e-1
rtherm.rtherm6 2 tl = 1.4e-1
}
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
tl

10
CASE
SPICE Thermal Model
Mechanical Dimensions
TO-263 2L (D2PAK)
Figure 22. 2LD, TO263, Surface Mount

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT263-002
Dimension in Millimeters
11
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

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RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILDS WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
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Rev. I66

12
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Fdb045An08A0: N-Channel Powertrench Mosfet

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FDB045AN08A0

N-Channel PowerTrench MOSFET

RDS(on) = 3.9 m ( Typ.) @ VGS = 10 V, ID = 80 A

Synchronous Rectification for ATX / Server / Telecom PSU

QG(tot) = 92 nC ( Typ.) @ VGS = 10 V

Battery Protection Circuit

Low Miller Charge

Motor drives and Uninterruptible Power Supplies

Low Qrr Body Diode

MOSFET Maximum Ratings TC = 25C unless otherwise noted

Drain to Source Voltage

Gate to Source Voltage

Continuous (TC < 137oC, VGS = 10V)

Continuous (Tamb = 25oC, VGS = 10V, with RJA = 43oC/W)

Single Pulse Avalanche Energy (Note 1)

Derate above 25oC

Operating and Storage Temperature

Thermal Resistance Junction to Case

Thermal Resistance Junction to Ambient (Note 2)

Thermal Resistance Junction to Ambient, 1in2 copper pad area

2002 Fairchild Semiconductor Corporation

FDB045AN08A0 N-Channel PowerTrench MOSFET

Electrical Characteristics TC = 25C unless otherwise noted

VGS = VDS, ID = 250A

ID = 80A, VGS = 10V

ID = 80A, VGS = 10V,

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate to Source Leakage Current

Gate to Source Threshold Voltage

Reverse Transfer Capacitance

Total Gate Charge at 10V

Threshold Gate Charge

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain Miller Charge

VDS = 25V, VGS = 0V,

Switching Characteristics (VGS = 10V)

Turn-On Delay Time

Turn-Off Delay Time

VDD = 40V, ID = 80A

Drain-Source Diode Characteristics

Reverse Recovery Time

ISD = 75A, dISD/dt = 100A/s

Reverse Recovered Charge

ISD = 75A, dISD/dt = 100A/s

Source to Drain Diode Voltage

2002 Fairchild Semiconductor Corporation

FDB045AN08A0 N-Channel PowerTrench MOSFET

Package Marking and Ordering Information

POWER DISSIPATION MULTIPLIER

TC , CASE TEMPERATURE (oC)

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Figure 2. Maximum Continuous Drain Current vs

DUTY CYCLE - DESCENDING ORDER

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance