TLE 4269

TLE 4269

5-V Low-Drop Fixed Voltage Regulator

Features

Output voltage tolerance 2 %

Very low current consumption
Early warning
Reset output low doown to VQ = 1 V
Overtemperature protection
Reverse polarity proof
Settable reset threshold
Very low drop voltage
Wide temperature range
Integrated pull up resistor at logic outputs

Type

Ordering Code Package

TLE 4269 A

Q67000-A9190

P-DIP-8-4

TLE 4269 G

Q67006-A9173

P-DSO-8-1 (SMD)

TLE 4269 GM Q67006-A9288

TLE 4269 GL

Q67006-A9192

P-DIP-8-4

P-DSO-8-1

P-DSO-14-4 (SMD)
P-DSO-20-6 (SMD)

New type
Functional Description
This device is a voltage regulator with a fixed 5-V
output, e.g. in a P-DSO-8-1 package. The maximum
operating voltage is 45 V. The output is able to drive a
150 mA load. It is short circuit protected and the
thermal shutdown switches the output off if the junction
temperature is in excess of 150 C. A reset signal is
generated for an output voltage of VQ < 4.6 V. The
reset threshold voltage can be decreased by external
connection of a voltage divider. The reset delay time
can be set by an external capacitor. Reset and sense
output have integrated pull up resistors. If the
integrated resistors are not desired TLE 4279 can be
used. It is also possible to supervise the input voltage
by using an integrated comparator to give a low voltage
warning.
Semiconductor Group

P-DSO-20-6

P-DSO-14-4

1998-11-01

TLE 4269

Pin Configuration
(top view)

P-DIP-8-4

P-DSO-8-1

SO

RE

GND

S
RE
D

1
2
3
4

8
7
6
5

Q
SO
R
GND

AEP01668

AEP01813

Pin Definitions and Functions (TLE 4269 A and TLE 4269 G)

Pin No.

Symbol

Function

Input; block directly to GND on the IC with a ceramic capacitor.

SI

Sense Input; if not needed connect to Q.

RE

Reset Threshold; if not needed connect to ground.

Reset Delay; to select delay time, connect to GND via external

capacitor.

GND

Ground

Reset Output; the open-collector output is internally linked to Q

via a 20 k pull-up resistor.

SO

Sense Output; the open-collector output is internally linked to the

output via a 20 k pull-up resistor.

5-V Output; connect to GND with a 10 F capacitor, ESR < 10 .

Semiconductor Group

1998-11-01

TLE 4269

Pin Configuration
(top view)
P-DSO-14-4

RE
D
GND
GND
GND
GND
R

1
2
3
4
5
6
7

14
13
12
11
10
9
8

SI

GND
GND
GND
Q
SO

AEP02248

Pin Definitions and Functions (TLE 4269 GM)

Pin No.

Symbol

Function

RE

Reset Threshold; if not needed connect to GND.

Reset Delay; connect to GND via external delay capacitor for

setting delay time.

3, 4, 5, 6

GND

Ground

Reset Output; open-collector output, internally connected to Q

via a pull-up resistor of 20 k.

SO

Sense Output; open-collector output, internally connected to Q

via a 20 k pull-up resistor.

5-V Output; connect to GND with a 10 F capacitor, ESR < 10 .

10, 11, 12 GND

Ground

13

Input; block to GND directly at the IC by a ceramic capacitor.

14

SI

Sense Input; if not needed connect to Q.

Semiconductor Group

1998-11-01

TLE 4269

Pin Configuration
(top view)

P-DSO-20-6
RE
D
N.C.
GND
GND
GND
GND
N.C.
N.C.
R

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

N.C.
GND
GND
GND
GND
N.C.
Q
SO

AEP01802

Pin Definitions and Functions (TLE 4269 GL)

Pin No.

Symbol

Function

RE

Reset Threshold; if not needed connect to GND.

Reset Delay; to select delay time connect to GND via external

capacitor.

4-7, 14-17

GND

Ground

10

Reset Output; the open-collector output is internally linked to

Q via 20 k pull-up resistor.

11

SO

Sense Output; the open-collector output is internally linked to

Q via 20 k pull-up resistor.

12

Output; connect to GND with a 10 F capacitor, ESR < 10 .

19

Input; block directly to GND at the IC by a ceramic capacitor.

20

SI

Sense Input; if not needed connect to Q.

Semiconductor Group

1998-11-01

TLE 4269

Circuit Description
The control amplifier compares a reference voltage, made highly accurate by resistance
balancing, with a voltage proportional to the output voltage and drives the base of the
series PNP transistor via a buffer. Saturation control as a function of the load current
prevents any over-saturation of the power element.
In the reset generator block a comparator compares a reference voltage independent of
the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V
the reset delay capacitor is discharged and the reset output is set to low. This low is
guaranteed down to an output voltage of 1 V. As the output voltage increases again,
from 4.6 V onward the reset delay capacitor is charged with constant current. When the
capacitor voltage reaches the upper switching threshold VdT, the reset returns to high. By
choosing the value of this capacitor, the reset delay time can be selected over a wide
range. With the reset threshold input RE it is possible to lower the reset threshold Vrt. If
pin RE is connected to pin Q via a voltage divider, for example, the reset condition is
reached when this voltage is decreased below the switching threshold Vre of 1.35 V.
Another comparator compares the signal of the pin SI, normally fed by a voltage divider
from the input voltage, with the reference and gives an early warning on the pin SO. It is
also possible to superwise an other voltage e.g. of a second regulator, or to build a
watchdog circuit with few external components.
Application Description
The input capacitor CI is necessary for compensating line influences. Using a resistor of
approx. 1 in series with CI, the oscillating circuit consisting of input inductivity and input
capacitance can be damped. The output capacitor CQ is necessary for the stability of the
regulating circuit. Stability is guaranteed at values 10 F and an ESR 10 within the
operating temperature range. For small tolerances of the reset delay the spread of the
capacitance of the delay capacitor and its temperature coefficient should be noted.

Semiconductor Group

1998-11-01

TLE 4269

Q
Error
Amplifier

20 k

20 k

Current and
Saturation
Control

Reference

Trimming

RE

Reference
SO

SI

AEB01669

Block Diagram
Semiconductor Group

1998-11-01

TLE 4269

Absolute Maximum Ratings

Tj = 40 to 150 C
Parameter

Symbol

Limit Values
min.

Unit

Notes

45

max.

Input
Input voltage

VI

40

Input current

II

internal limited

Input voltage

VSI

0.3

45

Input current

ISI

mA

Voltage

VRE

0.3

Current

IRE

10

10

mA

Voltage

VD

0.3

Current

ID

internal limited

IGND

50

mA

Voltage

VR

0.3

Current

IR

internal limited

Sense Input

Reset Threshold

Reset Delay

Ground
Current
Reset Output

Semiconductor Group

1998-11-01

TLE 4269

Absolute Maximum Ratings (contd)

Tj = 40 to 150 C
Parameter

Symbol

Limit Values
min.

max.

Unit

Notes

Sense Output
Voltage

VSO

0.3

Current

ISO

internal limited

Output voltage

VQ

0.3

Output current

IQ

mA

Junction temperature

Tj

150

Storage temperature

TStg

50

150

Input voltage

VI

45

Junction temperature

Tj

40

150

Rthja

100
200
70
70

K/W
K/W
K/W
K/W

P-DIP-8-4
P-DSO-8-1
P-DSO-14-4
P-DSO-20-6

Rthjc

60
60
30
30

K/W
K/W
K/W
K/W

P-DIP-8-4
P-DSO-8-1
P-DSO-14-4
P-DSO-20-6

5-V Output

Temperature

Operating Range

Thermal Data
Junction-ambient

Semiconductor Group

1998-11-01

TLE 4269

Characteristics
VI = 13.5 V; Tj = 40 C < Tj < 125 C
Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

Measuring
Condition

Output voltage

VQ

4.90

5.00

5.10

1 mA IQ 100 mA
6 V VI 16 V

Current limit

IQ

150

200

500

mA

Current consumption;
Iq = II IQ

Iq

150

300

IQ 1 mA, Tj < 85 C

Current consumption;
Iq = II IQ

Iq

250

700

IQ = 10 mA

Current consumption;
Iq = II IQ

Iq

mA

IQ = 50 mA

Drop voltage

Vdr

0.25

0.5

IQ = 100 mA1)

Load regulation

VQ

10

30

mV

IQ = 5 mA to 100 mA

Line regulation

VQ

10

40

mV

VI = 6 V to 26 V
IQ = 1 mA

Switching threshold

Vrt

4.50

4.60

4.80

Reset pull up

10

20

40

Reset low voltage

VR

0.1

0.4

Rintern

Delay switching
threshold

Vdt

1.4

1.8

2.2

Switching threshold

Vst

0.3

0.45

0.60

0.1

VQ < VRT

9.5

VD = 1 V

Reset Generator

Reset delay low voltage VD

Charge current
1)

Id

3.0

6.5

Drop voltage = VI VQ (measured when the output voltage has dropped 100 mV from the
nominal value obtained at 13.5 V input.)

Semiconductor Group

1998-11-01

TLE 4269

Characteristics (contd)
VI = 13.5 V; Tj = 40 C < Tj < 125 C
Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

Measuring
Condition

Delay time L H

td

17

28

ms

CD = 100 nF

Delay time H L

tt

CD = 100 nF

Switching voltage

Vre

1.26

1.35

1.44

VQ > 3.5 V

Sense threshold high

Vsi, high

1.24

1.31

1.38

Sense threshold low

Vsi, low

1.16

1.20

1.28

Sense output
low voltage

VSO, low

0.1

0.4

VSI < 1.20 V;

Vi > 3 V
Rintern

Sense pull up

10

20

40

Sense input current

ISI

0.1

Input Voltage Sense

Semiconductor Group

10

1998-11-01

TLE 4269

C
470 nF

1000 F

CQ
22 F

TLE 4269
S

VS
CD
100 nF

GND VR

VSO

RE

VQ

VRE

VD
AES01670

Measuring Circuit (P-DIP-8-4/P-DSO-8-1)

V
< t RR

V RT
VQ
dV d
=
dt C D

VDT
VST

VD
t RR

td

V RO
Power-on-Reset

Thermal
Shutdown

Voltage Dip
at Input

Undervoltage

Secondary
Spike

Overload
at Output

AED01542

Reset Timing Diagram

Semiconductor Group

11

1998-11-01

TLE 4269

Sense
Input
Voltage

VSI, High

VSI, Low

t
Sense
Output
High

Low

t
AED02559

Sence Timing Diagram

Semiconductor Group

12

1998-11-01

TLE 4269

Charge Current Id versus

Temperature Tj
d

Switching Voltage Vdt and Vst versus

Temperature Tj
AED01803

16
A
14

V = 13.5 V
V C = 1.0 V

12

AED01804

3.2
VD V
2.8

V = 13.5 V
2.4

10

2.0

1.6

1.2

0.8

Vdt

Vst
0.4

2
0
-40

40

80

0
-40

120 C 160

40

80

Tj

Tj

Drop Voltage Vdr versus

Output Current IQ

Reset Switching Threshold Vre

versus Temperature Tj
AED01805

500

V dr

120 C 160

Vre

mV

AED01806

1.7
V
1.6

400

1.5
1.4

300

1.3

Tj = 125 C
200

1.2

Tj = 25 C
1.1
100

1.0
0

30

60

90

120

mA

0.9
-40

180

Semiconductor Group

40

80

120 C 160

Tj

13

1998-11-01

TLE 4269

Current Consumption IQ versus

Input Voltage VI

Output Voltage VQ versus

Input Voltage VI

AED01807

30

q mA

VQ

25

10

20

RL = 33

15

10

RL = 100

RL = 200
0

10

20

RL = 50

RL = 50

AED01808

12

30

40 V 50

Output Voltage VQ versus

Temperature Tj
AED01809

1.6

AED01671

5.2

VQ

V = 13.5 V

1.5

V 10

Sense Threshold Vsi

versus Temperature Tj
V si

V
5.1

V = 13.5 V
5.0

1.4
Sense Output High

1.3

4.9

Sense Output Low

1.2

4.8

1.1

4.7

1.0
-40

40

80

4.6
-40

120 C 160

40

80

120 C 160

Tj

Tj

Semiconductor Group

14

1998-11-01

TLE 4269

Output Current IQ versus

Input Voltage VI

Current Consumption Iq versus

Output Current IQ
AED01810

350

AED01811

12

Q mA

q mA

300

10

V = 13.5 V
Tj = 25 C

250

Tj = 25 C

200
6

Tj = 125 C

150

100
2

50
0

10

20

30

40 V 50

20

40

60

80

mA

120

Current Consumption Iq versus

Output Current IQ
q

AED01812

1.6
mA
1.4

V = 13.5 V
Tj = 25 C

1.2
1.0
0.8
0.6
0.4
0.2
0

10

20

30

40 mA 50

Semiconductor Group

15

1998-11-01

TLE 4269

Package Outlines

GPD05583

P-DIP-8-4
(Plastic Dual In-line)

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information

Semiconductor Group

16

Dimensions in mm

1998-11-01

TLE 4269

P-DSO-14-4 (SMD)
(Plastic Dual Small Outline)

1.27
0.1

0.35 +0.15 2)

8 max.

4 -0.2 1)

0.19 +0.06

1.75 max

1.45 -0.2

0.2 -0.1

0.35 x 45

0.4 +0.8

0.2 14x
6 0.2

14

1
7
8.75 -0.21)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information
SMD = Surface Mounted Device
Semiconductor Group

17

GPS05093

Dimensions in mm

1998-11-01

TLE 4269

GPS05121

P-DSO-8-1 (SMD)
(Plastic Dual Small Outline)

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information
SMD = Surface Mounted Device
Semiconductor Group

18

Dimensions in mm
1998-11-01

TLE 4269

1.27
0.35

0.35 x 45

7.6 -0.2 1)

0.23 +0.0
9
8 ma
x

2.65 max

2.45 -0.2

0.2 -0.1

P-DSO-20-6 (SMD)
(Plastic Dual Small Outline)

0.4 +0.8

+0.15 2)

0.2 24x
20

0.1

10.3 0.3

11

GPS05094

1 12.8 1) 10
-0.2
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information
SMD = Surface Mounted Device
Semiconductor Group

19

Dimensions in mm

1998-11-01