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ISO5852S
SLLSEQ0A AUGUST 2015 REVISED SEPTEMBER 2015
ISO5852S High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver

with Split Outputs and Active Safety Features
1 Features
3 Description
The ISO5852S is a 5.7-kVRMS, reinforced isolated

gate driver for IGBTs and MOSFETs with split
outputs, OUTH and OUTL, providing 2.5-A source
and 5-A sink current. The input side operates from a
single 2.25-V to 5.5-V supply. The output side allows
for a supply range from minimum 15-V to maximum
30-V. Two complementary CMOS inputs control the
output state of the gate driver. The short propagation
time of 76 ns assures accurate control of the output
stage.
100-kV/s Minimum Common-Mode Transient

Immunity (CMTI) at VCM = 1500 V
Split Outputs to Provide 2.5-A Peak Source and
5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Soft Turn-Off (STO) during Short Circuit
Fault Alarm upon Desaturation Detection is
Signaled on FLT and Reset Through RST
Input and Output Under Voltage Lock-Out (UVLO)
with Ready (RDY) Pin Indication
Active Output Pull-down and Default Low Outputs
with Low Supply or Floating Inputs
2.25-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients
Shorter Than 20 ns
Operating Temperature: 40C to 125C Ambient
Surge Immunity 12800-VPK (according to IEC
61000-4-5)
Safety and Regulatory Certifications:
8000-VPK VIOTM and 2121-VPK VIORM
Reinforced Isolation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
5700-VRMS Isolation for 1 Minute per UL 1577
CSA Component Acceptance Notice 5A, IEC
60950-1, IEC 60601-1 and IEC 61010-1 End
Equipment Standards
CQC Certification per GB4943.1-2011
All Certifications are Planned
An internal desaturation (DESAT) fault detection

recognizes when the IGBT is in an overcurrent
condition. Upon a DESAT detect, a Mute logic
immediately blocks the output of the isolator and
initiates a soft-turn-off procedure which disables,
OUTH, and pulls OUTL to low over a time span of
2 s. When OUTL reaches 2 V with respect to the
most negative supply potential, VEE2, the gate driver
output is pulled hard to VEE2 potential turning the
IGBT immediately off.
When desaturation is active, a fault signal is sent
across the isolation barrier pulling the FLT output at
the input side low and blocking the isolator input.
Mute logic is activated through the soft-turn-off
period. The FLT output condition is latched and can
be reset only after RDY goes high, through a lowactive pulse at the RST input.
Device Information(1)
PART NUMBER
ISO5852S
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm 7.50 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.
Functional Block Diagram
2 Applications
Isolated IGBT and MOSFET Drives in

Industrial Motor Control Drives
Industrial Power Supplies
Solar Inverters
HEV and EV Power Modules
Induction Heating
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO5852S
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Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Function ...........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
5
6
7
Absolute Maximum Ratings ......................................

ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Rating.............................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 14

Detailed Description ............................................ 16
9.1 Overview ................................................................. 16
9.2 Functional Block Diagram ....................................... 16

9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 21
10 Application and Implementation........................ 22

10.1 Application Information.......................................... 22
10.2 Typical Applications .............................................. 22
11 Power Supply Recommendations ..................... 32

12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 PCB Material ......................................................... 32
12.3 Layout Example .................................................... 32
13 Device and Documentation Support ................. 33

13.1
13.2
13.3
13.4
13.5
Documentation Support ........................................

Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
14 Mechanical, Packaging, and Orderable

Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2015) to Revision A
Page
Moved Features: "100-kV/s Minimum Common-Mode Transient Immunity.." to the top of the list ..................................... 1
Changed from a 1-page Product Preview to the full datasheet. ........................................................................................... 1
Changed text "single 3-V To: 5.5-V supply" to "single 2.25-V to 5.5-V supply" in the Description ........................................ 1
Changed text "IGBT is in an overload condition" To: "IGBT is in an overcurrent condition" in the Description..................... 1
Changed text "and reduces the voltage at OUTL over a minimum time span of 2 s" To: "and pulls OUTL to low
over a time span of 2 s" in the Description........................................................................................................................... 1
Changed paragraph 3 of the Description ............................................................................................................................... 1
Changed the Functional Block Diagram, added STO on pin OUTL....................................................................................... 1
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Copyright 2015, Texas Instruments Incorporated
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5 Description (continued)
When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2.
If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low
impedance path preventing IGBT to be dynamically turned on during high voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits
monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low,
otherwise this output is high.
The ISO5852S is available in a 16-pin SOIC package. Device operation is specified over a temperature range
from 40C to 125C ambient.
6 Pin Configuration and Function

DW Package
16-Pin SOIC
Top View
16
GND1
DESAT
15
VCC1
GND2
14
RST
OUTH
13
FLT
VCC2
12
RDY
OUTL
11
IN-
CLAMP
10
IN+
VEE2
ISOLATION
VEE2
GND1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VEE2
1, 8
Output negative supply. Connect to GND2 for Unipolar supply application.
DESAT
Desaturation voltage input
GND2
Gate drive common. Connect to IGBT emitter.
OUTH
Positive gate drive voltage output
VCC2
Most positive output supply potential.
OUTL
Negative gate drive voltage output
CLAMP
Miller clamp output
GND1
9, 16
Input ground
IN+
10
Non-inverting gate drive voltage control input
IN-
11
Inverting gate drive voltage control input
RDY
12
Power-good output, active high when both supplies are good.
FLT
13
Fault output, low-active during DESAT condition
RST
14
Reset input, apply a low pulse to reset fault latch.
VCC1
15
Positive input supply (2.25-V to 5.5-V)
ISO5852S
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
GND1 - 0.3
0.3
35
17.5
0.3
0.3
35
Positive gate driver output voltage
VEE2 - 0.3
VCC2 + 0.3
Negative gate driver output voltage
VEE2 - 0.3
VCC2 + 0.3
2.7
5.5
VCC1
Supply voltage input side
VCC2
Positive supply voltage output side
(VCC2 GND2)
VEE2
Negative supply voltage output side
(VEE2 GND2)
V(SUP2)
Total supply output voltage
(VCC2 - VEE2)
V(OUTH)
V(OUTL)
I(OUTH)
Gate driver high output current
I(OUTL)
Gate driver low output current
V(LIP)
Voltage at IN+, IN-,FLT, RDY, RST
I(LOP)
Output current of FLT, RDY
V(DESAT)
Voltage at DESAT
V(CLAMP)
Clamp voltage
TJ
TSTG
(1)
Gate driver high output current

(max pulse width = 10 s, max duty
cycle = 0.2%)
GND1 - 0.3
VCC1 + 0.3
10
mA
GND2 - 0.3
VCC2 + 0.3
VEE2 - 0.3
VCC2 + 0.3
Junction temperature
40
150
Storage temperature
65
150
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
7.2 ESD Ratings

VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN
VCC1
Supply voltage input side
VCC2
V(EE2)
V(SUP2)
Total supply voltage output side (VCC2 VEE2)
V(IH)
High-level input voltage (IN+, IN-, RST)
V(IL)
Low-level input voltage (IN+, IN-, RST)
tUI
Pulse width at IN+, IN- for full output (CLOAD = 1 nF)
tRST
Pulse width at RST for resetting fault latch
800
TA
Ambient temperature
-40
NOM
MAX
UNIT
2.25
5.5
Positive supply voltage output side (VCC2 GND2)
15
30
Negative supply voltage output side (VEE2 GND2)
15
15
30
0.7 x VCC1
VCC1
0.3 x VCC1
40
V
ns
ns
125
ISO5852S
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7.4 Thermal Information

DW (SOIC)
THERMAL METRIC (1)
16 PINS
RJA
Junction-to-ambient thermal resistance
99.6
RJC(top)
Junction-to-case (top) thermal resistance
48.5
RJB
Junction-to-board thermal resistance
56.5
JT
Junction-to-top characterization parameter
29.2
JB
Junction-to-board characterization parameter
56.5
(1)
UNIT
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Power Rating

VALUE
PD
Maximum power dissipation (1)
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25C
PID
Maximum Input power dissipation
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25C
175
POD
Maximum Output power dissipation
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25C
1080
(1)
UNIT
1255
mW
Full chip power dissipation is de-rated 10.04 mW/C beyond 25C ambient temperature. At 125C ambient temperature, a maximum of
251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,
while ensuring that Junction temperature does not exceed 150C.
7.6 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25C, VCC1 = 5 V, VCC2
GND2 = 15 V, GND2 VEE2 = 8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.25
VOLTAGE SUPPLY
VIT+(UVLO1)
Positive-going UVLO1 threshold voltage

input side
VIT-(UVLO1)
Negative-going UVLO1 threshold voltage

input side
VHYS(UVLO1)
UVLO1 Hysteresis voltage (VIT+ VIT)

input side
0.2
VIT+(UVLO2)
Positive-going UVLO2 threshold voltage

output side
12
VIT-(UVLO2)
Negative-going UVLO2 threshold voltage

output side
VHYS(UVLO2)
UVLO2 Hysteresis voltage (VIT+ VIT)

output side
IQ1
Input supply quiescent current
2.8
4.5
mA
IQ2
Output supply quiescent current
3.6
mA
1.7
9.5
V
V
13
11
LOGIC I/O
VIT+(IN,RST)
Positive-going input threshold voltage (IN+,

IN-, RST)
VIT-(IN,RST)
Negative-going input threshold voltage

(IN+, IN-, RST)
VHYS(IN,RST)
Input hysteresis voltage (IN+, IN-, RST)
IIH
High-level input leakage at (IN+) (1)
IN+ = VCC1
IIL
Low-level input leakage at (IN-, RST) (2)
IN- = GND1, RST = GND1
IPU
Pull-up current of FLT, RDY
V(RDY) = GND1, V(FLT) = GND1
V(OL)
Low-level output voltage at FLT, RDY
I(FLT) = 5 mA
0.7 x VCC1
0.3 x VCC1
V
V
0.15 x VCC1
100
-100
100
A
0.2
GATE DRIVER STAGE

V(OUTPD)
Active output pull-down voltage
I(OUTH/L) = 200 mA, VCC2 = open
VOUTH
High-level output voltage
I(OUTH) = 20 mA
VOUTL
Low-level output voltage
I(OUTL) = 20 mA
I(OUTH)
High-level output peak current
IN+ = high, IN- = low,

V(OUTH) = VCC2 - 15 V
(1)
(2)
VCC2 - 0.5
VCC2 - 0.24
VEE2 + 13
1.5
V
VEE2 + 50
2.5
mV
A
IIH for IN-, RST pin is zero as they are pulled high internally
IIL for IN+ is zero, as it is pulled low internally
ISO5852S
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Electrical Characteristics (continued)

GND2 = 15 V, GND2 VEE2 = 8 V
PARAMETER
I(OUTL)
Low-level output peak current
I(OLF)
Low level output current during fault

condition
TEST CONDITIONS
IN+ = low, IN- = high,
V(OUTL) = VEE2 + 15 V
MIN
TYP
3.4
MAX
UNIT
A
130
mA
ACTIVE MILLER CLAMP

V(CLP)
Low-level clamp voltage
I(CLP) = 20 mA
I(CLP)
Low-level clamp current
V(CLAMP) = VEE2 + 2.5 V
V(CLTH)
Clamp threshold voltage
VEE2 + 0.015
VEE2 + 0.08
1.6
2.5
3.3
1.6
2.1
2.5
SHORT CIRCUIT CLAMPING

V(CLP-OUTH)
Clamping voltage
(VOUTH - VCC2)
IN+ = high, IN- = low, tCLP = 10 s,

I(OUTH) = 500 mA
1.1
1.3
V(CLP-OUTL)
Clamping voltage
(VOUTL - VCC2)

I(OUTL) = 500 mA
1.3
1.5
Clamping voltage
(VCLP - VCC2)

I(CLP) = 500 mA
1.3
Clamping voltage at CLAMP
IN+ = High, IN- = Low, I(CLP) = 20 mA
0.7
1.1
Clamping voltage at OUTL

(VCLP - VCC2)
IN+ = High, IN- = Low, I(OUTL) = 20

mA
0.7
1.1
0.58
mA
V(CLP-CLAMP)
V(CLP-OUTL)
DESAT PROTECTION
I(CHG)
Blanking capacitor charge current
V(DESAT) - GND2 = 2 V
0.42
0.5
I(DCHG)
Blanking capacitor discharge current
V(DESAT) - GND2 = 6 V
14
V(DSTH)
DESAT threshold voltage with respect to

GND2
8.3
V(DSL)
DESAT voltage with respect to GND2,

when OUTH/L is driven low
0.4
mA
9.5
7.7 Switching Characteristics

GND2 = 15 V, GND2 VEE2 = 8 V
MIN
TYP
MAX
tr
Output signal rise time at OUTH
PARAMETER
12
18
35
ns
tf
Output signal fall time at OUTL
12
20
37
ns
tPLH, tPHL
Propagation Delay
76
110
ns
tsk-p
Pulse Skew |tPHL tPLH|
20
ns
tsk-pp
Part-to-part skew
30 (1)
ns
tGF (IN,/RST)
Glitch filter on IN+, IN-, RST
30
40
ns
tDS
DESAT sense to 90% VOUTH/L

delay
553
760
ns
3.5
1.4
480
ns
800
ns
(90%)
TEST CONDITIONS
CLOAD = 1 nF
see Figure 41, Figure 42,
and Figure 43
CLOAD = 10 nF
tDS
(10%)
DESAT sense to 10% VOUTH/L

delay
tDS
(GF)
DESAT glitch filter delay
CLOAD = 1 nF
(FLT)
DESAT sense to FLT-low delay
see Figure 43
tLEB
Leading edge blanking time
see Figure 41 and Figure 42
tGF(RSTFLT)
Glitch filter on RST for resetting

FLT
CI
Input capacitance (2)
VI = VCC1/2 + 0.4 x sin (2ft), f = 1 MHz,

VCC1 = 5 V
CMTI
Common-mode transient immunity
VCM = 1500 V, see Figure 44
tDS
(1)
(2)
20
UNIT
330
310
400
300
2
100
120
ns
pF
kV/s
Measured at same supply voltage and temperature condition

Measured from input pin to ground.
ISO5852S
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-0.5
-0.5
IOH - Output Drive Current (A)
IOH - Output Drive Current (A)
7.8 Typical Characteristics
-1
-1.5
-2
-2.5
-3
VCC2 - VOUT = 2.5 V
VCC2 - VOUT = 5 V
VCC2 - VOUT = 10 V
-3.5
-4
-40
VCC2 - VOUT = 15 V
VCC2 - VOUT = 20 V
-1.5
-2
-2.5
-3
-3.5
-4
-25
-10
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
IOL - Output Drive Current (A)
6
5
4
3
2
0
-40
VOUT - VEE2 = 15 V
VOUT - VEE2 = 20 V
10
15
20
VCC2 - VOUTH/L Voltage (V)
25
30
D003
Figure 2. Output High Drive Current vs Output Voltage

7
VOUT - VEE2 = 2.5 V

VOUT - VEE2 = 5 V
VOUT - VEE2 = 10 V
D001
Figure 1. Output High Drive Current vs Temperature
IOL - Output Drive Current (A)
-1
TA = -40qC
TA = 25qC
TA = 125qC
5
4
3
2
TA = -40qC
TA = 25qC
TA = 125qC
1
0
-25
-10
20 35 50 65 80
95
110 125
D002
Figure 3. Output Low Drive Current vs Temperature
10
15
20
VOUTH/L - VEE2 Voltage (V)
25
30
D004
Figure 4. Output Low Drive Current vs Output Voltage
VDSTH - DESAT Threshold Voltage (V)
9.2
9.1
9
8.9
8.8
8.7
8.6
15 V Unipolar
30 V Unipolar
8.5
-40
-25
-10
20 35 50 65 80
95
110 125
D005
Unipolar: VCC2 - VEE2 = VCC2 - GND2

Figure 5. DESAT Threshold Voltage vs Temperature
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CH 3: 3 V/Div
CH 3: 3 V/Div
Typical Characteristics (continued)
500 ns / Div
50 ns / Div
CL = 1 nF
RGH = 0
VCC2 - VEE2 = VCC2 - GND2 = 20 V
RGL = 0
CL = 10 nF
RGH = 0
Figure 7. Output Transient Waveform
CH 3: 3 V/Div
CH 3: 3 V/Div
50 ns / Div
2 ms / Div
CL = 100 nF
RGH = 0
CL = 1 nF
RGH = 10
RGL = 0
RGL = 5
CH 3: 3 V/Div
CH 3: 3 V/Div
500 ns / Div
2 ms / Div
CL = 10 nF
RGH = 10
RGL = 5
CL = 100 nF
RGH = 10
RGL = 0
RGL = 5
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CH 4: 5 V/Div
RDY
CH 2: 10 V/Div
/FLT
OUT
DESAT
/FLT
CH 4: 5 V/Div
CH 3: 5 V/Div
DESAT
CH 1: 7.5 V/Div
CH 2: 10 V/Div
OUT
CH 3: 5 V/Div
CH 1: 7.5 V/Div
RDY
2 ms / Div
1 ms / Div
CL = 10 nF
RGH = 0
RGL = 0
DESAT = 220pF
Figure 12. Output Transient Waveform DESAT, RDY and FLT

CH 1: 15 V/Div
RGL = 0
DESAT = 220 pF
CH 1: 15 V/Div
CL = 10 nF
RGH = 0
CH 4: 5 V/Div
RDY
CH 2: 10 V/Div
CH 3: 5 V/Div
/FLT
DESAT
/FLT
CH 4: 5 V/Div
DESAT
OUT
CH 3: 5 V/Div
CH 2: 10 V/Div
OUT
RDY
2 ms / Div
1 ms / Div
CL = 10 nF
RGH = 0
CL = 10 nF
RGH = 0
RGL = 0
DESAT = 220 pF
3.4
2
1.9
ICC1 - Supply Current (mA)
3.2
RGL = 0
DESAT = 220pF
3
2.8
2.6
2.4
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
2.2
2
-40
-25
-10
IN+ = High
20 35 50 65 80
95
1.8
1.7
1.6
1.5
1.4
1.3
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
1.2
1.1
110 125
1
-40
-25
-10
D006
IN- = Low
IN+ = Low
Figure 16. ICC1 Supply Current vs Temperature
20 35 50 65 80
95
110 125
D007
IN- = Low
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2.5
4.5
2
1.5
1
0.5
4
3.5
3
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
2.5
VCC1 = 3 V
VCC1 = 5.5 V
0
0
50
100
150
200
Input Frequency - (kHz)
250
2
-40
300
-25
-10
D008
20 35 50 65 80
95
110 125
D010
Input frequency = 1 kHz

70
60
Figure 18. ICC1 Supply Current vs Input Frequency

5.5
4.5
4
3.5
3
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
2.5
50
40
30
20
10
VCC2 = 15 V
VCC2 = 30 V
2
0
50
100
150
200
Input Frequency - (kHz)
250
300
90
90
80
80
70
60
50
40
30
tpLH at VCC2 = 15 V
tpHL at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 30 V
20
10
-10
CL = 1nF
VCC1 = 5 V
20 35 50 65 80
RGH = 0
95
90
100
D011
70
60
50
40
30
tpLH at VCC1 = 3.3 V
tpHL at VCC1 = 3.3 V
tpLH at VCC1 = 5 V
tpHL at VCC1 = 5 V
10
0
-40
-25
-10
D012
RGL = 0
80
RGL = 5 , 20 kHz
20
110 125
Figure 22. Propagation Delay vs Temperature
10
30
40
50
60
70
Load Capacitance (nF)
Figure 21. ICC2 Supply Current vs Load Capacitance

100
Propagation Delay (ns)
Figure 20. ICC2 Supply Current vs Input Frequency

100
-25
20
RGH = 10
No CL
0
-40
10
D009
CL = 1nF
VCC2 = 15 V
20 35 50 65 80
RGH = 0
95
110 125
D013
RGL = 0
Figure 23. Propagation Delay vs Temperature
ISO5852S
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1200
1000
tpLH at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 15 V
tpHL at VCC2 = 30 V
800
Transistion Time (ns)
1000
VCC2 = 15 V
VCC2 = 30 V
900
800
600
400
700
600
500
400
300
200
200
100
0
0
0
10
20
30
40
50
60
70
RGH = 10
80
90
100
RGL = 5
Figure 24. Propagation Delay vs Load Capacitance
30
40
50
60
70
80
90
100
D015
RGL = 0
VCC1 = 5 V
Figure 25. tr Rise Time vs Load Capacitance

6000
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
5000
500
20
RGH = 0
VCC1 = 5 V
600
400
300
200
100
4000
3000
2000
1000
10
20
30
40
50
60
70
RGH = 0
80
90
100
10
20
30
40
50
60
70
D016
RGL = 0
RGH = 10
VCC1 = 5 V
Figure 26. tf Fall Time v. Load Capacitance
80
90
100
D017
RGL = 5
VCC1 = 5 V
Figure 27. tr Rise Time vs Load Capacitance

500
2000
tLEB - Leading Edge Blanking Time (ns)
VCC2 = 15 V
VCC2 = 30 V
1800
1600
10
D014
1400
1200
1000
800
600
400
200
0
0
10
20
RGH = 10
30
40
50
60
70
RGL = 5
80
90
100
480
460
440
420
400
380
360
340
VCC2 = 15 V
VCC2 = 30 V
320
300
-40
-25
D018
-10
20 35 50 65 80
95
110 125
D019
VCC1 = 5 V
Figure 28. tf Fall Time vs Load Capacitance
Figure 29. Leading Edge Blanking Time With Temperature
11
ISO5852S
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4
VCC2 = 15 V
VCC2 = 30 V
3.5
3
2.5
2
1.5
1
-40
-25
-10
20 35 50 65 80
95
VCC2 = 15 V
VCC2 = 30 V
1.20
1.15
1.10
-10
20 35 50 65 80
570
550
530
510
490
470
450
-40
95
110 125
20 35 50 65 80
95
110 125
D021
RGH = 0
RGL = 0
5
4.8
4.6
4.4
4.2
4
3.8
3.6
VCC1 = 5 V, VCC2 = 15 V
3.4
-40
-25
-10
20 35 50 65 80
95
110 125
D024
D022
Figure 33. Fault and RDY Low to RDY High Delay vs

Temperature
120
ICLP - Clamp Low-Level Current (A)
100
Reset To Fault Delay (ns)
-10
Figure 31. DESAT Sense to VOUT 90% Delay vs Temperature
Figure 32. DESAT Sence to Fault Low Delay vs Temperature
80
60
40
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
20
0
-40
-25
CL = 10 nF
/FLT and RDY Low to RDY High Delay (Ps)
tDESAT(/FLT) - DESAT Sense to /FLT Low Delay (Ps)
1.25
-25
VCC2 = 15 V
VCC2 = 30 V
590
RGL = 0
Figure 30. DESAT Sense to VOUT 10% Delay vs Temperature
1.05
-40
610
D020
RGH = 0
CL = 10 nF
110 125
tDESAT(90%) - DESAT Sense to 90% VOUT Delay (Ps)
tDESAT(10%) - DESAT Sense to 10% VOUT Delay (Ps)
-25
-10
20 35 50 65 80
95
110 125
4.5
4
3.5
3
2.5
2
1.5
1
V(CLAMP) = 2 V
V(CLAMP) = 4 V
V(CLAMP) = 6 V
0.5
0
-40
-25
D023
-10
20 35 50 65 80
95
110 125
D025
Figure 35. Miller Clamp Current vs Temperature

Figure 34. Reset to Fault Delay Across Temperature
12
ISO5852S
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Short Circuit Clamp Voltage on CLAMP (mV)

2
Active Pull Down Voltage (V)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
I(OUTH/L) = 100 mA
I(OUTH/L) = 200 mA
0.2
0
-40
-25
-10
20 35 50 65 80
95
110 125
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
1000
800
600
400
200
0
-40
-25
-10
20 35 50 65 80
95
110 125
800
600
400
20 mA at VCC2 = 15 V
250 mA at VCC2 = 15 V
200
0
-40
-25
-10
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
20 35 50 65 80
95
110 125
D029
1400
1200
1000
800
600
400
250 mA at VCC2 = 15 V
200
0
-40
-25
-10
D027
Figure 38. Short Circuit Clamp Voltage on OUTH Across

Temperature
ICHG - Blanking Capacitor Charging Current - (PA)
1000
Figure 37. Short Circuit Clamp Voltage on Clamp Across

Temperature
Short Circuit Clamp Voltage on OUTL (mV)
Short Circuit Clamp Voltage on OUTH (mV)
1400
1200
1200
D026
Figure 36. Active Pull Down Voltage vs Temperature
250 mA at VCC2 = 15 V
1400
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
20 35 50 65 80
95
110 125
D028
Figure 39. Short Circuit Clamp Voltage on OUTL Across

Temperature
-400
-420
-440
-460
-480
-500
-520
-540
-560
-580
-600
-40
VCC2 = 15 V
VDESAT = 6 V
-25
-10
20 35 50 65 80
95
110 125
D030
DESAT = 6 V
Figure 40. Blanking Capacitor Charging Current vs Temperature
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ISO5852S
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8 Parameter Measurement Information

IN-
0V
50 %
IN+
50 %
tr
tf
90%
50%
OUTH/L
10%
tPLH
tPHL
Figure 41. OUTH/L Propagation Delay, Non-Inverting Configuration

IN50 %
50 %
VCC1
IN+
tr
tf
90%
50%
OUTH/L
10%
tPLH
tPHL
Figure 42. OUTH/L Propagation Delay, Inverting Configuration
14
ISO5852S
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Parameter Measurement Information (continued)
Figure 43. DESAT, OUTH/L, FLT, RST Delay

ISO5852S
15
VCC2
VCC1
5
1F
0.1F
9, 16
14
10
S1
11
13
GND1
GND2
15V
VEE2 1, 8
RST
Isolation Barrier
2.25 V...5.5 V
IN+
IN-
FLT
CL
DESAT
12
CLAMP
RDY
OUTH
VCM
OUTL
Pass-Fail Criterion:
1nF OUT must remain stable
Figure 44. Common-Mode Transient Immunity Test Circuit

15
ISO5852S
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9 Detailed Description
9.1 Overview
The ISO5852S is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage
are separated by a Silicon dioxide (SiO2) capacitive isolation.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET
(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to
supply 2.5-A pull-up and 5-A pull-down currents to drive the capacitive load of the external power transistors, as
well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The
capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and
receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S also contains under
voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pull-down
feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The
ISO5852S also has an active Miller clamp which can be used to prevent parasitic turn-on of the external power
transistor, due to Miller effect, for unipolar supply operation.
9.2 Functional Block Diagram
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ISO5852S
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9.3 Feature Description

9.3.1 Supply and active Miller clamp
The ISO5852S supports both bipolar and unipolar power supply with active Miller clamp.
For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its
emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its
gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the
IGBT gate. Typical values of VCC2 and VEE2 for bipolar operation are 15-V and -8-V with respect to GND2.
For operation with unipolar supply, typically, VCC2 is connected to 15-V with respect to GND2, and VEE2 is
connected to GND2. In this use case, the IGBT can turn-on due to additional charge from IGBT Miller
capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the
CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.
Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage
transitions below 2-V the CLAMP current output is activated.
9.3.2 Active Output Pull-down
The Active output pull-down feature ensures that the IGBT gate OUTH/L is clamped to VEE2 to ensure safe IGBT
off-state, when the output side is not connected to the power supply.
9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1
drops below VIT-(UVLO1), irrespective of IN+, IN- and RST input till VCC1 goes above VIT+(UVLO1).
In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN- and
RST input till VCC2 goes above VIT+(UVLO2).
Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection
feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise,
RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for
operation.
9.3.4 Soft Turn-Off, Fault (FLT) and Reset (RST)
During IGBT overcurrent condition, a Mute logic initiates a soft-turn-off procedure which disables, OUTH, and
pulls OUTL to low over a time span of 2 s. When desaturation is active, a fault signal is sent across the isolation
barrier pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through
the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a
low-active pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for atleast the specified minimum duration (800ns), device input logic can be enabled or disabled.
9.3.5 Short Circuit Clamp
Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP
pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes
on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly
higher than the output side supply.
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ISO5852S
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Feature Description (continued)

9.3.6 High Voltage Feature Description
9.3.6.1 Package Insulation and Safety-Related Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
L(I01)
L(I02)
(1)
CTI
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
mm
Minimum external tracking (creepage)
Shortest terminal-to-terminal distance across the package

surface
mm
Tracking resistance (comparative

tracking index)
DIN EN 60112 (VDE 0303-11);

IEC 60112; Material Group I according to IEC 60664-1;
UL 746A
600
Per JEDEC package dimensions.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
9.3.6.2 Insulation Characteristics
PARAMETER
DTI
Distance through the insulation
VIOWM
Maximum isolation working voltage
TEST CONDITIONS
SPECIFICATION
Minimum internal gap (internal clearance)

Time dependent dielectric breakdown (TDDB) Test
UNIT
21
1500
VRMS
2121
VDC
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

VIORM
VPR
Maximum repetitive peak isolation voltage
Input to output test voltage
2121
Method A, After Input/Output safety test subgroup 2/3,
VPR = 1.2 x VIORM, t = 10 sec,
Partial discharge < 5 pC
2545
Method A, After environmental tests subgroup 1,

VPR = 1.6 VIORM, t = 10 sec (qualification)
3393
Method B1, 100% Production test,

VPR = 1.875 VIORM, t = 1 sec
3976
VPK
VIOTM
Maximum Transient isolation voltage
VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100%

production)
8000
VIOSM
Maximum surge isolation voltage
Test method per IEC 60065, 1.2/50 s waveform, VTEST =

1.6 x VIOSM = 12800 VPK (qualification) (1)
8000
RS
Insulation resistance
VIO = 500 V at TS
> 109
VIO = 500 V, TA = 25C
> 1012
RIO
Isolation resistance, input to output (2)
CIO
Barrier capacitance, input to output (2)
11
VIO = 500 V, 100C TA max
> 10
VIO = 0.4 x sin (2ft), f = 1 MHz
Pollution degree
pF
UL 1577
VISO
(1)
(2)
18
Withstanding Isolation voltage
VTEST = VISO, t = 60 sec (qualification),

VTEST = 1.2 VISO = 6840 VRMS, t = 1 sec (100%
production)
5700
VRMS
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
All pins on each side of the barrier tied together creating a two-terminal device
ISO5852S
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9.3.6.3 Regulatory Information

VDE
Plan to certify according to DIN V
VDE V 0884-10 (VDE V 088410):2006-12 and DIN EN 60950-1
(VDE 0805 Teil 1):2011-01
CSA
UL
Plan to certify under CSA Component

Acceptance Notice 5A, IEC 60950-1,
IEC 61010-1, and IEC 60601-1
Plan to certify under 1577 Component

Recognition Program
Reinforced Insulation Maximum

Transient isolation voltage, 8000 VPK;
Maximum surge isolation voltage,
8000 VPK,
Maximum repetitive peak isolation
voltage, 2121 VPK
Isolation Rating of 5700 VRMS;

Reinforced insulation per CSA 610101-12 and IEC 61010-1 (3rd Ed.), 300
VRMS max working voltage);
Reinforced insulation per CSA 609501- 07+A1+A2 and IEC 60950-1 (2nd
Single Protection, 5700 VRMS
Ed.), 800 VRMS max working voltage
(pollution degree 2, material group I) ;
2 MOPP (Means of Patient Protection)
per CSA 60601-1:14 and IEC 60601-1
Ed. 3.1, 250 VRMS (354 VPK) max
working voltage
Certification planned
(1)
CQC
(1)
Plan to certify according to GB

4943.1-2011
Reinforced Insulation, Altitude

5000m, Tropical climate, 250 VRMS
maximum working voltage
Production tested 6840 VRMS for 1 second in accordance with UL 1577.
9.3.6.4 IEC 60664-1 Rating Table

PARAMETER
Basic Isolation Group
Installation Classification
TEST CONDITIONS
Material Group
SPECIFICATION
I
Rated Mains Voltage 600 VRMS
I-IV
Rated Mains Voltage 1000 VRMS
I-III
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ISO5852S
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9.3.6.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
IS
Safety input, output or supply current
PS
Safety input, output, or total power
TS
Maximum ambient safety

temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
JA = 99.6C/W, VI = 2.75 V, TJ = 150C,

TA = 25C
456
JA = 99.6C/W, VI = 3.6 V, TJ = 150C,

TA = 25C
346
JA = 99.6C/W, VI = 5.5 V, TJ = 150C,

TA = 25C
228
JA = 99.6C/W, VI = 15 V, TJ = 150C,
TA = 25C
84
JA = 99.6C/W, VI = 30 V, TJ = 150C,
TA = 25C
42
JA = 99.6C/W, TJ = 150C, TA = 25C
1255 (1)
mA
150
Input, output, or the sum of input and output power should not exceed this value
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
500
1400
Safety Limiting Current (mA)
400
350
300
250
200
150
100
Power
1200
Safety Limiting Power (mW)
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = 5.5 V
VCC2 = 15 V
VCC2 = 30 V
450
1000
800
600
400
200
50
0
50
100
150
200
Figure 45. Thermal Derating Curve for Safety Limiting

Current per VDE
50
100
150
200
Figure 46. Thermal Derating Curve for Safety Limiting

Power per VDE
9.3.6.6 Surge Voltage Rating
V(Surge)
(1)
20
Surge immunity
1.2/50 s voltage surge pulse according to IEC 60065 (1)
VALUE
UNIT
12800
VPK
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
ISO5852S
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9.4 Device Functional Modes

In ISO5852S OUTH/L to follow IN+ in normal functional mode, FLT needs to be in high state.
Table 1. Function Table (1)
VCC1
VCC2
IN+
IN-
RST
RDY
OUTH/L
PU
PD
Low
Low
PD
PU
Low
Low
PU
PU
Low
High
Low
PU
Open
Low
Low
PU
PU
Low
High
Low
PU
PU
High
High
Low
PU
PU
High
Low
High
High
High
(1)
PU: Power Up (VCC1 2.25-V, VCC2 13-V), PD: Power Down (VCC1 1.7-V, VCC2 9.5-V), X: Irrelevant
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ISO5852S
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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information

The ISO5852S is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is
intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In
these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at
the system level eventually may determine, for example, the speed, position, and torque of the motor or the
output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a micro
controller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required by the MOSFETs
and IGBTs, on the other hand, are in the range of 30-V (using Unipolar Output Supply) to 15-V (using Bipolar
Output Supply), and need high current capability to be able to drive the large capacitive loads offered by those
power transistors. Not only that, the gate drive needs to be applied with reference to the Emitter of the IGBT
(Source for MOSFET), and by construction, the Emitter node in a gate drive system swings between 0 to the DC
bus voltage, that can be several 100s of volts in magnitude.
The ISO5852S is thus used to level shift the incoming 2.5-V, 3.3-V and 5-V control signals from the
microcontroller to the 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output Supply) drive required
by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller
side.
10.2 Typical Applications

Figure 47 shows the typical application of a three-phase inverter using six ISO5852S isolated gate drivers.
Three-phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for
high power applications such as High-Voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5852S
devices that are connected to one of the three load terminals. The operation of the three switches is coordinated
so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a sixstep line-to-line output waveform. In this type of applications, carrier-based PWM techniques are applied to retain
waveform envelope and cancel harmonics.
Figure 47. Typical Motor Drive Application

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ISO5852S
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Typical Applications (continued)

10.2.1 Design Requirements
Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the
input control signals, the input control to the ISO5852S is CMOS and can be directly driven by the
microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a
pullup resistor on the common drain FLT output signal, and a high-voltage protection diode between the IGBT
collector and the DESAT input. Further details are explained in the subsequent sections. Table 2 shows the
allowed range for Input and Output supply voltage, and the typical current output available from the gate-driver.
Table 2. Design Parameters
PARAMETER
VALUE
Input supply voltage
2.25-V to 5.5-V
Unipolar output supply voltage (VCC2 - GND2 = VCC2 - VEE2)
15-V to 30-V
Bipolar output supply voltage (VCC2 - VEE2)
15-V to 30-V
Bipolar output supply voltage (GND2 - VEE2)
0-V to 15-V
Output current
2.5-A
10.2.2 Detailed Design Procedure

10.2.2.1 Recommended ISO5852S Application Circuit
The ISO5852S has both, inverting and non-inverting gate control inputs, an active low reset input, and an open
drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 48 illustrates
a typical gate driver implementation with Unipolar Output Supply and Figure 49 illustrates a typical gate driver
implementation with Bipolar Output Supply using the ISO5852S.
A 0.1-F bypass capacitor, recommended at input supply pin VCC1 and 1-F bypass capacitor, recommended at
output supply pin VCC2, provide the large transient currents necessary during a switching transition to ensure
reliable operation. The 220 pF blanking capacitor disables DESAT detection during the off-to-on transition of the
power device. The DESAT diode (DDST) and its 1-k series resistor are external protection components. The RG
gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times.
The open-drain FLT output and RDY output has a passive 10-k pull-up resistor. In this application, the IGBT
gate driver is disabled when a fault is detected and will not resume switching until the micro-controller applies a
reset signal.
10R
10R
15
VCC1
2.25V...5V
ISO5852S
VCC2
15V
VEE2
IN-
DESAT
11
RDY
15V
DDST
10k
10k
FLT
OUTL
RST
OUTH
IN-
DESAT
CLAMP
FLT
OUTL
1N
DDST
RST
OUTH
RGL
14
RGH
220
pF
220
pF
Figure 48. Unipolar Output Supply
15V
RDY
13
RGH
14
VEE2
12
RGL
1F
1,8
IN+
11
CLAMP
13
GND2
10
1N
1F
3
GND1
12
VCC2
9.16
1,8
IN+
ISO5852S
0.1F
GND2
10
10k
2.25V...5V
GND1
10k
VCC1
0.1F
9.16
15
1F
Figure 49. Bipolar Output Supply
10.2.2.2 FLT and RDY Pin Circuitry

There is 50-k pull-up resistor internally on FLT and RDY pins. The FLT and RDY pin is an open-drain output. A
10-k pull-up resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive,
as shown in Figure 50.
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ISO5852S
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Fast common mode transients can inject noise and glitches on FLT and RDY pins due to parasitic coupling. This
is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT
and RDY pins.
10R
15
VCC1
ISO5852S
0.1F
2.25V-5.5V
9, 16
10k
GND1
10k
12
13
RDY
FLT
C
14
10
11
RST
IN+
IN-
Figure 50. FLT and RDY Pin Circuitry for High CMTI
10.2.2.3 Driving the Control Inputs
The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the
high-voltage output circuit to the low-voltage input side of the ISO5852S. For maximum CMTI performance, the
digital control inputs, IN+ and IN-, must be actively driven by standard CMOS, push-pull drive circuits. This type
of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5852S
output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain
configurations using pull-up resistors, must be avoided. There is a 20 ns glitch filter which can filter a glitch up to
20 ns on IN+ or IN-.
10.2.2.4 Local Shutdown and Reset
In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the
individual reset lines are asserted low independently to reset the motor controller after a fault condition.
10R
15
10R
VCC1
0.1F
2.25V-5.5V
10k
9, 16
GND1
10k
10k
12
13
13
FLT
C
ISO5852S
GND1
10k
12
RDY
VCC1
0.1F
2.25V-5.5V
9, 16
15
ISO5852S
RDY
FLT
C
14
10
11
RST
14
RST
10
IN+
IN+
11
IN-
IN-
Figure 51. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)
24
ISO5852S
www.ti.com
10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5852S can be configured to shutdown automatically in the event
of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of
multiple ISO5852S devices can be wired together forming a single, common fault bus for interfacing directly to
the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FLT
output disables all six gate drivers simultaneously.
10R
15
VCC1
ISO5852S
0.1F
2.25V-5.5V
9, 16
10k
GND1
10k
12
13
RDY
FLT
C
14
10
11
to other
to other
RSTs
FLTs
RST
IN+
IN-
Figure 52. Global Shutdown with Inverting Input Configuration
25
ISO5852S
www.ti.com
10.2.2.6 Auto-Reset
In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching
cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault
state until the gate control signal changes to the 'gate low' state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high
again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next
'on' cycle.
10R
15
10R
VCC1
ISO5852S
0.1F
2.25V-5.5V
9, 16
10k
10k
13
GND1
10k
12
13
FLT
C
ISO5852S
9, 16
GND1
RDY
VCC1
0.1F
2.25V-5.5V
10k
12
15
RDY
FLT
C
14
10
11
RST
14
RST
10
IN+
IN+
11
IN-
IN-
Figure 53. Auto Reset for Non-inverting and Inverting Input Configuration
26
ISO5852S
www.ti.com
10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes
of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100- to 1-k resistor is connected in
series with the DESAT diode.
Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of
the DESAT input to GND2 potential at low voltage levels.
ISO5852S
VCC2
5
1F
GND2
15V
3
1F
VEE2
15V
1, 8
DDST
RS
DESAT
CLAMP
OUTL
OUTH
2
7
RGL
VFW-Inst
RGH
220
pF
VFW
Figure 54. DESAT Pin Protection with Series Resistor and Schottky Diode
27
ISO5852S
www.ti.com
10.2.2.8 DESAT Diode and DESAT Threshold

The DESAT diodes function is to conduct forward current, allowing sensing of the IGBTs saturated collector-toemitter voltage, V(DESAT), (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the
short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the
IGBT. This results in a charging current I(CHARGE) = C(D-DESAT) x dVCE/dt, charging the blanking capacitor. C(D-DESAT)
is the diode capacitance at DESAT.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ C(BLANK) / C(D-DESAT).
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = V(DESAT), the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 9 V n x VF (where n is the number of DESAT diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be
chosen.
10.2.2.9 Determining the Maximum Available, Dynamic Output Power, POD-max
The ISO5852S maximum allowed total power consumption of PD = 251 mW consists of the total input power, PID,
the total output power, POD, and the output power under load, POL:
PD = PID + POD + POL
(1)
PID = VCC1-max ICC1-max = 5.5 V 4.5 mA = 24.75 mW
(2)
POD = (VCC2 VEE2) x ICC2-max = (15 V ( 8 V )) 6 mA = 138 mW
(3)
POL = PD PID POD = 251 mW 24.75 mW 138 mW = 88.25 mW
(4)
With:
and:
then:
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
POL-WC = 0.5 fINP QG
(VCC2
ron-max
roff-max
+
- VEE2 )
roff-max + RG
ron-max + RG
where
fINP = signal frequency at the control input IN+

QG = power device gate charge
VCC2 = positive output supply with respect to GND2
VEE2 = negative output supply with respect to GND2
ron-max = worst case output resistance in the on-state: 4
roff-max = worst case output resistance in the off-state: 2.5
RG = gate resistor
(5)
Once RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 55 shows a simplified
output stage model for calculating POL-WC.
28
ISO5852S
www.ti.com
ISO5852S
VCC2
15V
ron-max
RG
OUTH/L
QG
roff-max
8V
VEE2
Figure 55. Simplified Output Model for Calculating POL-WC

10.2.2.10 Example
This examples considers an IGBT drive with the following parameters:
ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE2 = 8 V
(6)
Applying the value of the gate resistor RG = 10 .

Then, calculating the worst-case output power consumption as a function of RG, using Equation 5 ron-max = worst
case output resistance in the on-state: 4 , roff-max = worst case output resistance in the off-state: 2.5 , RG =
gate resistor yields
4
2.5
POL-WC = 0.5 20 kHz 650 nC (15 V - ( - 8 V) )

+
= 72.61 mW
4 + 10 2.5 + 10
(7)
Because POL-WC = 72.61 mW is below the calculated maximum of POL = 88.25 mW, the resistor value of RG = 10
is suitable for this application.
29
ISO5852S
www.ti.com
10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in
Figure 56) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10
pair for up to 15 A maximum.
ISO5852S
VCC2
5
1F
GND2
15V
3
1F
VEE2
1, 8
1N
DESAT
CLAMP
OUTL
OUTH
15V
DDST
2
7
10
rG
10
220
pF
Figure 56. Current Buffer for Increased Drive Current
30
ISO5852S
www.ti.com
CH 2: 10 V/Div
CH 2: 10 V/Div
CH 1: 5 V/Div
CH 1: 5 V/Div
10.2.3 Application Curve
5 ms / Div
CL = 1 nF
VCC2 - GND2 = 15 V
(VCC2 - VEE2 = 23 V)
RGH = 10
GND2 - VEE2 = 8 V
5 ms / Div
RGL = 10
Figure 57. Normal Operation - Bipolar Supply
CL = 1 nF
RGH = 10
RGL = 10
Figure 58. Normal Operation - Unipolar Supply
31
ISO5852S
www.ti.com
11 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1-F bypass capacitor is recommended at
input supply pin VCC1 and 1-F bypass capacitor is recommended at output supply pin VCC2. The capacitors
should be placed as close to the supply pins as possible. Recommended placement of capacitors needs to be 2mm maximum from input and output power supply pin (VCC1 and VCC2).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 59). Layer stacking should
be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and
low-frequency signal layer.
Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects between the gate driver and the microcontroller and
power transistors. Gate driver control input, Gate driver output OUTH/L and DESAT should be routed in the
top layer.
Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for
the return current flow. On the driver side, use GND2 as the ground plane.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2. On the gate-driver VEE2 and VCC2 can be used as power planes. They can share
the same layer on the PCB as long as they are not connected together.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,
routing etc. see Application Note SLLA284, Digital Isolator Design Guide.
12.2 PCB Material

Standard FR-4 epoxy-glass is recommended as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
12.3 Layout Example

High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 59. Recommended Layer Stack
32
ISO5852S
www.ti.com
13 Device and Documentation Support

13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
ISO5852S Evaluation Module (EVM) Users Guide, SLLU207
Digital Isolator Design Guide, SLLA284
Isolation Glossary (SLLA353)
13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
33
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
ISO5852SDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-250C-1 YEAR
-40 to 125
ISO5852S
ISO5852SDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO5852S
(1)
The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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Product

ISO5852S High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver

The ISO5852S is a 5.7-kVRMS, reinforced isolated

100-kV/s Minimum Common-Mode Transient

An internal desaturation (DESAT) fault detection

BODY SIZE (NOM)

(1) For all available packages, see the orderable addendum at

Functional Block Diagram

Isolated IGBT and MOSFET Drives in

Absolute Maximum Ratings ......................................

Parameter Measurement Information ................ 14

9.2 Functional Block Diagram ....................................... 16

10 Application and Implementation........................ 22

11 Power Supply Recommendations ..................... 32

13 Device and Documentation Support ................. 33

Documentation Support ........................................

14 Mechanical, Packaging, and Orderable

Changed from a 1-page Product Preview to the full datasheet. ........................................................................................... 1

Changed paragraph 3 of the Description ............................................................................................................................... 1

Changed the Functional Block Diagram, added STO on pin OUTL....................................................................................... 1

Submit Documentation Feedback

Copyright 2015, Texas Instruments Incorporated

Product Folder Links: ISO5852S

SLLSEQ0A AUGUST 2015 REVISED SEPTEMBER 2015

6 Pin Configuration and Function

Output negative supply. Connect to GND2 for Unipolar supply application.

Desaturation voltage input

Gate drive common. Connect to IGBT emitter.

Positive gate drive voltage output

Most positive output supply potential.

Negative gate drive voltage output

Miller clamp output

Non-inverting gate drive voltage control input

Inverting gate drive voltage control input

Power-good output, active high when both supplies are good.

Fault output, low-active during DESAT condition

Reset input, apply a low pulse to reset fault latch.

Positive input supply (2.25-V to 5.5-V)

Submit Documentation Feedback

Copyright 2015, Texas Instruments Incorporated

Product Folder Links: ISO5852S

Positive gate driver output voltage

Negative gate driver output voltage

Supply voltage input side

Positive supply voltage output side

Negative supply voltage output side

Total supply output voltage

Gate driver high output current

Gate driver low output current

Voltage at IN+, IN-,FLT, RDY, RST

Output current of FLT, RDY

Gate driver high output current

7.2 ESD Ratings

Charged-device model (CDM), per JEDEC specification JESD22C101 (2)

7.3 Recommended Operating Conditions

Supply voltage input side

Total supply voltage output side (VCC2 VEE2)

High-level input voltage (IN+, IN-, RST)

Low-level input voltage (IN+, IN-, RST)