L4988

Low drop voltage regulator

Datasheet − production data

Features

Max DC supply voltage VS 40V

Max output voltage tolerance ΔV0 +/-2%
Max dropout voltage Vdp 500 mV
'!0'#&4 '!0'#&4
Output current I0 200 mA
Quiescent current Iqn 75 µA(1) SO-8 SO-20
1. Typical value with watchdog disabled.

Description
■ Operating DC supply voltage range 5.6V to
The L4988 is a monolithic integrated 5V voltage
31V
regulator with a low drop voltage at currents up to
■ Reset circuit sensing the output voltage down 200mA. The output voltage regulating element
to 1V consists in a p-channel MOS and the regulation is
■ Programmable reset pulse delay with external performed regardless of input voltage transients
capacitor up to 40V. The high precision of the output voltage
is obtained with a pre-trimmed reference voltage.
■ Watchdog
The L4988 is protected against short circuit and
■ Programmable watchdog timer with external an over-temperature protection switches off the
capacitor device in case of extremely high power dissipa-
■ Enable input for enabling/disabling the tion. The L4988 is active when the Enable is high.
watchdog functionality State of the art features like reset and watchdog
make this device particularly suitable to supply
■ Thermal shutdown and short circuit protection
microprocessor systems in automotive
■ Wide temperature range (Tj = -40°C to 150°C) applications.

Table 1. Device summary

Order codes
Package
Tube Tape & reel

SO8 L4988D L4988DTR

SO20 (16+2+2) L4988MD L4988MDTR

April 2012 Doc ID 13617 Rev 5 1/32

This is information on a product in full production. www.st.com 1
Contents L4988

Contents

1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 SO-20 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 SO-20 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 13617 Rev 5

L4988 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Watchdog Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. SO-20 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 13617 Rev 5 3/32

List of figures L4988

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Output voltage vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Drop Voltage vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Current consumption vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Current consumption vs. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Current limitation vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Short Circuit Current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Short Circuit Current vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. VWEn_high vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. VWEN_LOW vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Vrhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. Vrlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. Vwhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. Vwlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18. Icr & Icwc vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19. Idr & Icwd vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 20. Twop vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 21. PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 22. Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 23. Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. L4988 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 26. Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 29. SO-8 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . 19
Figure 30. SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 31. SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 32. SO-20 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 33. SO-20 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . 22
Figure 34. SO-20 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 35. SO-20 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 36. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 37. SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 38. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 39. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 40. SO-20 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 41. SO-20 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4/32 Doc ID 13617 Rev 5

L4988 Block diagram and pin configuration

1 Block diagram and pin configuration

Figure 1. Block diagram

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Doc ID 13617 Rev 5 5/32

Block diagram and pin configuration L4988

Table 2. Pins description

Pin
SO8(D) S020(MD) Function
name

Watchdog Enable input

WEn 1 1
If high watchdog functionality is active
Gnd 2 4 Ground reference
Ground.
Gnd 5, 6, 15, 16
Connected these pins to a heat spreader ground
Reset output.
Res 3 7 It is pulled down when output voltage goes below Vo_th
or frequency at Wi is too low.
Reset timing adjust.
Vcr 4 10 A capacitor between Vcr pin and gnd, sets the reset
delay time (trd)
Watchdog timer adjust
Vcw 5 11 A capacitor between Vcw pin and gnd, sets the time
response of the watchdog monitor.
Watchdog input.
Wi 6 14 If the frequency at this input pin is too low, the Reset
output is activated.
Voltage regulator output
Vo 7 17 Block to ground with a capacitor >100nF (needed for
regulator stability)
Supply voltage
Vs 8 20
Block to ground directly at IC pin with a capacitor
2, 3, 8, 9, 12,
N.C. Not connected
13, 18, 19

Figure 2. Pins configuration

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6/32 Doc ID 13617 Rev 5

L4988 Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Table 3. Absolute maximum ratings
Symbol Parameter Value Unit

VVsdc DC supply voltage -0.3 to 40 V

IVsdc Input current Internally limited
VVo DC output voltage -0.3 to 6(1) V
IVo DC output current Internally limited
VWi Watchdog input voltage -0.3 to VVo + 0.3 V
Vod Open Drain output voltage -0.3 to VVo + 0.3 V
Iod Open Drain output current Internally limited
Vcr Reset delay voltage -0.3 to VVo + 0.3 V
Vcw Watchdog delay voltage -0.3 to VVo + 0.3 V
VWEn Watchdog Enable input voltage -0.3 to VVo +0.3 V
Tj Junction temperature -40 to 150 “C
VESD ESD voltage level (HBM-MIL STD 883C) ±2 kV
VESD ESD voltage level (CDM AEC-Q100-011) 750 V
1. Using the typical application schematic with Cout= 10 µF and Iout=0 A, when the regulator is switched-on,
an overshoot exceeding 6 V could occur.This behavior does not impact the reliability of the regulator.

2.2 Thermal data

Table 4. Thermal data
Symbol Parameter S08 S016+2+2 Unit

Rth-jamb Thermal resistance junction to ambient 130(1) 51(2) °C/W

2
1. With copper area 2 cm ; for details see Figure 29.
2. With copper area 6 cm2 ; for details see Figure 33.

Doc ID 13617 Rev 5 7/32

Electrical specifications L4988

2.3 Electrical characteristics

Vs =5.6V to 31V, Tj= -40°C to +150°C unless otherwise specified.

Table 5. General
Pin Symbol Parameter Test condition Min. Typ. Max. Unit

Vs = 6 to 31V
Vo Vo_ref Output voltage 4.9 5.0 5.1 V
Io = 1 to 200mA
Vo Ishort Short circuit current Vs = 13.5V(1) 200 280 500 mA
(1)
Vo Ilim(2) Output current limitation Vs = 13.5V 200 350 600 mA
Vs = 6 to 31V
Vs, Vo Vline Line regulation voltage 25 mV
Io = 1 to 200mA
Vo Vload Load regulation voltage Io = 1 to 200mA 25 mV
Vs, Vo Vdp(3) Drop voltage Io = 200mA 270 500 mV
Vs, Vo Vdp(3) Drop voltage Io = 150mA 200 400 mV
Vs, Vo SVR Ripple rejection fr = 100 Hz(4) 60 dB
Vs=13.5V,
Vs, Vo Iqn_200 Quiescent current Io=200mA, 1.9 2.5 mA
WEn = high
Vs=13.5V,
Vs, Vo Iqn_50 Quiescent current Io= 50mA, 500 700 µA
WEn = high
Vs=13.5V,
Vs, Vo Iq_1_we Quiescent current Io< 1mA, 93 200 µA
WEn = high
Vs=13.5V,
Vs, Vo Iq_1_wd Quiescent current Io< 1mA, 75 150 µA
WEn = low
Thermal protection
Tw 150 190 °C
temperature
Thermal protection
Tw_hy 10 °C
temperature hysteresis
1. See Figure 3.
2. Measured output current when the output voltage has dropped 100mV from its nominal value obtained at
Vs=13.5V and Io= 75mA.
3. Vs-Vo measured when the output voltage has dropped 100mV from its nominal value obtained at
Vs=13.5V and Io= 75mA.
4. Guaranteed by design.

8/32 Doc ID 13617 Rev 5

L4988 Electrical specifications

Table 6. Reset
Pin Symbol Parameter Test condition Min. Typ. Max. Unit

Rext = 5kΩ to Vo,

Res Vres_l Reset output low voltage 0.4 V
Vo > 1V
Reset output high leakage
Res IRes_h VRes = 5V 1 µA
current
Res R_p_u Pull up internal resistance With respect to Vo 12 25 50 kΩ

Vo out of regulation Vs = 6 to 31V, Below

Res Vo_th 6% 8% 10%
threshold Io = 1 to 200mA Vo_ref

Vcr Vrlth Reset timing low threshold Vs = 13.5V 10% 13% 16% Vo_ref
Vcr Vrhth Reset timing high threshold Vs =13.5V 44% 47% 50% Vo_ref
Vcr Icr Charge current Vs = 13.5V 8 17.6 30 µA
Vcr Idr Discharge current Vs = 13.5V 8 17.6 30 µA
Res Trr_2 Reset reaction time(1) Vo = Vo_th -100mV 100 275 1000 µs
Vs = 13.5V,
Res Trd Reset delay time 65 150 ms
Ctr = 1nF
1. When Vo becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset
condition in this particular case.

Table 7. Watchdog
Pin Symbol Parameter Test condition Min. Typ. Max. Unit

Wi Vih Input high voltage Vs = 13.5V 3.5 V

Wi Vil Input low voltage Vs = 13.5V 1.5 V
Wi Vih Input hysteresis Vs = 13.5V 500 mV
Wi Ii Pull down current Vs = 13.5V 10 20 µA
Vcw Vwhth High threshold Vs = 13.5V 44% 47% 50% Vo_ref
Vcw Vwlth Low threshold Vs = 13.5V 10% 13% 16% Vo_ref
Vs = 13.5V,
Vcw Icwc Charge current 4 8 14 µA
Vcw = 0.1V
Vs = 13.5V,
Vcw Icwd Discharge current 1.0 2.1 4.5 µA
Vcw = 2.5V
Vs = 13.5V,
Vcw Twop Watchdog period 25 50 90 ms
Ctw = 47nF
Vs = 13.5V,
Res twol Watchdog output low time 6 10.5 22 ms
Ctw = 47nF

Doc ID 13617 Rev 5 9/32

Electrical specifications L4988

Table 8. Watchdog Enable

Pin Symbol Parameter Test condition Min. Typ. Max. Unit

WEn VEn_l Enable input low voltage 1 V

WEn VEn_h Enable input high voltage 3 V
WEn VEn_hy Enable input hysteresis 500 800 1100 mV
WEn I_leak Pull down current WEn = 5V 2 8 20 µA

10/32 Doc ID 13617 Rev 5

L4988 Electrical specifications

2.4 Electrical characteristics curves

Figure 3. Output voltage vs. Tj Figure 4. Output voltage vs. Vs

Vo_ref (V) Vo_ref (V)

5,5 10

5,4 Vs= 13.5V 9

I0 = 75mA
5,3 8

5,2 7
I0 = 75 mA
Tj = 25 °C
5,1 6

5 5

4,9 4

4,8 3

4,7 2

4,6 1

4,5 0
-50 -25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35
Tj(°C ) Vs (V )

Figure 5. Drop Voltage vs. Output Current Figure 6. Current consumption vs. Output
Current

Vdp (V) Iqn (µA)

0,35 1800

0,3
1500
Vs= 13.5 V
Tj= 25 °C
0,25
1200 WEn= High
Tj= 125 °C
0,2
900
0,15

Tj= 25 °C 600
0,1

300
0,05

0 0
0 50 100 150 200 250 0 40 80 120 160 200 240
Io (mA) Io (mA)

Figure 7. Current consumption vs. Input Figure 8. Current limitation vs. Tj

Voltage
Iqn(µA ) Ilim (mA)
2400 600
Tj = 25 °C
WEn = High
2000 500

Io= 200mA
1600 400
Vs= 13.5V

1200 300

Io= 100mA
800 200

Io = 50mA
400 100

Io = 1mA
0 0
0 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 150

Vs (V ) Tj(°C )

Doc ID 13617 Rev 5 11/32

Electrical specifications L4988

Figure 9. Current limitation vs. Input Voltage Figure 10. Short Circuit Current vs. Tj

Ilim (mA) Ishort (mA)

400 600

375 500

Tj = 25 °C
350 400 Vs= 13.5V

325 300
Tj = 125 °C

300 200

275 100

250 0
0 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 150
Vs (V ) Tj(°C )

Figure 11. Short Circuit Current vs. Input Figure 12. VWEn_high vs. Tj
Voltage

Ishort (mA ) Vwen_high (V)

360 4

3,5
330 Vs= 5.6V to 31V

3
300 Tj = 25 °C

2,5

270 Tj = 150 °C
2

240
1,5

210 1
0 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 150
Vs (V ) Tj(°C )

Figure 13. VWEN_LOW vs. Tj Figure 14. Vrhth vs. Tj

Vwen_low (V) Vrhth (% Vo_ref )

2 60

1,9 55

1,8 Vs= 5.6V to 31V 50 Vs= 5.6V to 31V

1,7 45

1,6 40

1,5 35

1,4 30
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj(°C ) Tj(°C )

12/32 Doc ID 13617 Rev 5

L4988 Electrical specifications

Figure 15. Vrlth vs. Tj Figure 16. Vwhth vs. Tj

Vrlth (% Vo_ref) Vwhth (% Vo_ref )

50 60

55
40 Vs= 5.6V to 31V

50 Vs= 5.6V to 31V

30

45

20
40

10
35

0 30
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj(°C ) Tj(°C )

Figure 17. Vwlth vs. Tj Figure 18. Icr & Icwc vs. Tj

Vwlth (% Vo_ref) Icr & Icwc (µA)

50 30

Vs= 5.6V to 31V

25
40 Vs= 5.6V to 31V

20
30 Icr

15

20
10
Icwc

10
5

0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj(°C ) Tj(°C )

Figure 19. Idr & Icwd vs. Tj Figure 20. Twop vs. Tj

Idr & Icwd (µA) Twop (ms)

30 80

25
Vs= 5.6V to 31V 70

Vs= 5.6V to 31V

20 60 Ctw= 47nF
Idr

15 50

10 40

5 30
Icwd

0 20
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Tj(°C ) Tj(°C )

Doc ID 13617 Rev 5 13/32

Electrical specifications L4988

Figure 21. PSRR

C0 = 4.7µF
PSRR [dB]
80

70

60

50

40

30

20

10

0
0,1 1 10 100 1000 10000
FREQUENCY [KHz]

2.5 Test circuit and waveforms plot

2.5.1 Load regulation

Figure 22. Load regulation test circuit



'!0'2)

14/32 Doc ID 13617 Rev 5

L4988 Electrical specifications

Figure 23. Maximum load variation response

V 0 [1
[1V / d
div]

I 0 [50
50mA / di
div]

0,00E+00 5,00E-05 1,00

00E-04 1,50E-04 2,00E-04 2,50E-04 3,00E-04 3,50E-04 4,00E-04

Time [s]
GAPGRI00073

Doc ID 13617 Rev 5 15/32

Application information L4988

3 Application information

Figure 24. L4988 application schematic

6I 6S 6O

# #
#S 7KHUPDO
SURWHFWLRQ

6CW

#TW
:DWFKGRJ
7I

9ROWDJHUHIHUHQFH
7%N
2ES
6CR 5HVHW
#TR

'ND

'!0'2)

Note: The input capacitor Cs > 200nF is necessary for the smoothing of line disturbances. The
output capacitor C01 > 100nF is necessary for the stability of the regulation loop. In order to
damp output voltage oscillations during high load current surges, it is recommended to put
an additional electrolytic capacitor C02 > 10µF at the output pin.

3.1 Voltage regulator

Voltage regulator uses a p-channel mos transistor as a regulating element. With this
structure a very low dropout voltage at currents up to 200mA is obtained. The output voltage
is regulated up to transient input supply voltage of 40V. No functional interruption due to
over-voltage pulses is generated. A short circuit protection to GND is provided. The high
precision of the output voltage is obtained with a pre-trimmed reference voltage.

16/32 Doc ID 13617 Rev 5

L4988 Application information

Figure 25. Behavior of output current versus regulated voltage Vo

6O

6O?REF

)SHORT )LIM )OUT

("1($'5

3.2 Reset
The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with
the in-ternal reference voltage and a resistor output divider. If the output voltage becomes
lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is
guaranteed for an output voltage Vo greater than 1V.
When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.
This delay is obtained by an internal oscillator.
The oscillator period is given by:
Tosc = [(Vrhth-Vrlth) x Ctr] / Icr + [(Vrhth-Vrlth) x Ctr] / Idr
where:
Icr: is an internally generated charge current
Idr: is an internally generated discharge current
Vrhth, Vrlth: are two voltages defined with the output voltage and a resistor output
divider
Ctr: is an external capacitance.
trd is given by:
trd = 512 x Tosc
Reset is active when En is high.

Doc ID 13617 Rev 5 17/32

Application information L4988

Figure 26. Reset timing diagram

7I

6 OUT?TH
6O TRR
4 OSC
TRR 6 RHTH
6 CR 6 RLTH

TRD4 OSC

2ES
'!0'#&4

3.3 Watchdog
A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the
constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is
generated. To prevent this the microcontroller must generate a positive edge during the
discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to
calculate the minimum time t, during which the micro-controller must output the positive
edge, the following equation can be used:
(Vwhth-Vwlth) x Ctw = Icwd x t
Every Wi positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, Vwhth, the current switches from charging to discharging. The result is a
saw-tooth voltage at the watchdog timer capacitor Ctw.

Figure 27. Watchdog timing diagram

7I
4WO P
6WHTH
6WLTH
6CW
6WLTH
TWOL

2ES
'!0'2)

18/32 Doc ID 13617 Rev 5

L4988 Package and PCB thermal data

4 Package and PCB thermal data

4.1 SO-8 thermal data

Figure 28. SO-8 PC board

*$3*&)7

Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB
thickness = 2mm, Cu thickness = 35µm , Copper areas: from minimum pad lay-out to 8cm2)

Figure 29. SO-8 Rthj-amb Vs. PCB copper area in open box free air condition
24(J?AMBVS#UHEATSINKAREA



24(JAMB
24(J?AMB #7










     
0#"#UHEATSINKAREACM>
'!0'#&4

Doc ID 13617 Rev 5 19/32

Package and PCB thermal data
, 
L4988
0AC K AG EAN D 0#" T H ER M AL D AT A

Figure 30. SO-8 thermal impedance junction ambient single pulse

=7+ƒ&:


&OOTPRINT

 CM




       
7LPHV

'!0'2)

Equation 1: pulse calculation formula

Z = R ⋅δ+Z (1 – δ)
THδ TH THtp

where δ = tP/T

Figure 31. SO-8 thermal fitting model of a single channel

*$3*&)7

20/32 Doc ID 13617 Rev 5

L4988 Package and PCB thermal data

Table 9. SO-8 thermal parameter

Area/island (cm2) Footprint 2

R1 (°C/W) 4.21
R2 (°C/W) 2.11
R3 (°C/W) 2
R4 (°C/W) 41
R5 (°C/W) 40
R6 (°C/W) 58 40
C1 (W.s/°C) 0.00029
C2 (W.s/°C) 0.0024
C3 (W.s/°C) 0.03
C4 (W.s/°C) 0.04
C5 (W.s/°C) 0.1
C6 (W.s/°C) 1.05 2

Doc ID 13617 Rev 5 21/32

Package and PCB thermal data L4988

4.2 SO-20 thermal data

Figure 32. SO-20 PC board

.
*$3*&)7

Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm,PCB
thickness = 2mm, Cu thickness=35μm , Copper areas: from minimum pad lay-out to 8cm2).

Figure 33. SO-20 Rthj-amb Vs. PCB copper area in open box free air condition

57+MBDPEYV&XKHDWVLQNDUHD



57+MDPE

57+MBDPEƒ&:








       
3&%&XKHDWVLQNDUHDFPA ("1($'5

22/32 Doc ID 13617 Rev 5

L4988 Package and PCB thermal data

Figure 34. SO-20 thermal impedance junction ambient single pulse

=7+ƒ&:


&X FP
&X IRRWSULQW




      
7LPHV
("1($'5

Equation 2: pulse calculation formula

Z = R ⋅δ+Z (1 – δ)
THδ TH THtp
where δ = tP/T

Figure 35. SO-20 thermal fitting model of a single channel

*$3*&)7

Doc ID 13617 Rev 5 23/32

Package and PCB thermal data L4988

Table 10. SO-20 thermal parameter

Area/island (cm2) Footprint 2

R1 (°C/W) 4.21
R2 (°C/W) 2.11
R3 (°C/W) 2.2
R4 (°C/W) 10
R5 (°C/W) 15
R6 (°C/W) 35 18
C1 (W.s/°C) 0.00029
C2 (W.s/°C) 0.0024
C3 (W.s/°C) 0.015
C4 (W.s/°C) 0.15
C5 (W.s/°C) 1.5
C6 (W.s/°C) 4 7

24/32 Doc ID 13617 Rev 5

L4988 Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 SO-8 package information

Figure 36. SO-8 package dimensions

'!0'#&4

Doc ID 13617 Rev 5 25/32

Package and packing information L4988

Table 11. SO-8 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 1.75

A1 0.10 0.25

A2 1.25

b 0.28 0.48

c 0.17 0.23

D(1) 4.80 4.90 5.00

E 5.80 6.00 6.20

E1(2) 3.80 3.90 4.00

e 1.27

h 0.25 0.50

L 0.40 1.27

L1 1.04

k 0° 8°

ccc 0.10

1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.

26/32 Doc ID 13617 Rev 5

L4988 Package and packing information

5.3 SO-20 package information

Figure 37. SO-20 package dimensions

("1($'5

Table 12. SO-20 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 2.35 2.65

A1 0.10 0.30

B 0.33 0.51

C 0.23 0.32

D(1) 12.60 13.00

E 7.40 7.60

e 1.27

H 10.0 10.65

h 0.25 0.75

L 0.40 1.27

Doc ID 13617 Rev 5 27/32

Package and packing information L4988

Table 12. SO-20 mechanical data (continued)

Millimeters
Symbol
Min. Typ. Max.

k 0° 8°

ddd 0.10

1. “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs
shall not exceed 0.15mm per side.

5.4 SO-8 packing information

Figure 38. SO-8 tube shipment (no suffix)
"
# Base q.ty 100
Bulk q.ty 2000
Tube length (± 0.5) 532
!
A 3.2
B 6
C (± 0.1) 0.6
All dimensions are in mm.

'!0'2)

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L4988 Package and packing information

Figure 39. SO-8 tape and reel shipment (suffix “TR”)

Doc ID 13617 Rev 5 29/32

Package and packing information L4988

5.5 SO-20 packing information

Figure 40. SO-20 tube shipment (no suffix)

Base Q.ty 40
Bulk Q.ty 800
#
"
Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6

! All dimensions are in mm.

'!0'2)

Figure 41. SO-20 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty 1000

Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
D 20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (+ 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

GAPGRI00080

30/32 Doc ID 13617 Rev 5

L4988 Revision history

6 Revision history

Table 13. Document revision history

01

Date Revision Changes

01-Jun-2007 1 Initial release

Added features table.
Added list of tables and figures.
30-Aug-2007 2 Updated Section 2.3: Electrical characteristics.
Added Section 4: Package and PCB thermal data.
Added SO-8 packing information and SO-20 packing information.
13-Feb-2008 3 Update Section 2.3: Electrical characteristics.
Document restructured.
Changed Figure 1: Block diagram.
Updated features table on cover page: changed quiescent current
value from 80 to 75 µA.
Updated Table 5: General:
– changed Ishort typical value from 250 to 280 mA
– changed Iqn_50 typical value from 550 to 500 µA
04-Jun-2008 4 – changed Iq_1_we typical value from 130 to 93 µA
– changed Iq_1_wd typical value from 80 to 75 µA.
Updated Table 7: Watchdog:
– changed Vwlth values in Vo_ref percentages
– changed Vwhth values in Vo_ref percentages.
Added Figure 24: L4988 application schematic.
Added Section 2.4: Electrical characteristics curves.
Added Section 2.5: Test circuit and waveforms plot.
05-Apr-2012 5 Update Table 3: Absolute maximum ratings.

Doc ID 13617 Rev 5 31/32

 L4988

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32/32 Doc ID 13617 Rev 5