L6498

High voltage high and low-side 2 A gate driver

Datasheet - production data

Description
The L6498 is a high voltage device manufactured
SO-8 SO-14
with the BCD6 “OFF-LINE” technology. It is a
single chip half-bridge gate driver for the
N-channel power MOSFET or IGBT.
The high-side (floating) section is designed to
Features stand a DC voltage rail up to 500 V, with 600 V
transient withstand voltage. The logic inputs are
 Transient withstand voltage 600 V CMOS/TTL compatible down to 3.3 V for easy
 dV/dt immunity ± 50 V/ns in full temperature interfacing control units such as microcontrollers
range or DSP.

 Driver current capability: Both device outputs can sink 2.5 A and source 2
– 2 A source typ. at 25 °C A, making the L6498 particularly suited for
medium and high capacity power
– 2.5 A sink typ. at 25 °C
MOSFETs\IGBTs.
 Short propagation delay: 85 ns
The outputs cannot be simultaneously driven high
 Switching times 25 ns rise/fall with 1 nF load thanks to an integrated interlocking function.
 3.3 V, 5 V TTL/CMOS inputs with hysteresis
The independent UVLO protection circuits
 Integrated bootstrap diode present on both the lower and upper driving
 Interlocking function sections prevent the power switches from being
operated in low efficiency or dangerous
 UVLO on both high-side and low-side sections
conditions.
 Compact and simplified layout
The integrated bootstrap diode as well as all of
 Bill of material reduction the integrated features of this driver make the
 Flexible, easy and fast design application PCB design simpler and more
compact, and help to reduce the overall bill of
material.
Applications
 Motor driver for home appliances, factory
automation, industrial drives and fans
 HID ballasts
 Power supply units
 DC-DC converters
 Induction heating
 Wireless chargers
 Industrial inverters
 UPS
 Welding

September 2017 DocID030318 Rev 3 1/20

This is information on a product in full production. www.st.com
Contents L6498

Contents

1 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2 SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/20 DocID030318 Rev 3

L6498 Block diagrams

1 Block diagrams

Figure 1. Block diagram SO-8

 

 




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Figure 2. Block diagram SO-14

 

 




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Pin description and connection diagram L6498

2 Pin description and connection diagram

Figure 3. Pin connection SO-8 (top view)

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Figure 4. Pin connection SO-14 (top view)

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Table 1. Pin description

Pin no.
Pin name Type Function
SO-8 SO-14

1 1 HIN I High-side driver logic input (active high)

2 2 LIN I Low-side driver logic input (active high)
3 - GND P Device ground
(1)
4 6 LVG O Low-side driver output
5 7 VCC P Lower section supply voltage
6 11 OUT P High-side (floating) common voltage
7 12 HVG(1) O High-side driver output
8 13 BOOT P Bootstrapped supply voltage
- 3 SGND P Signal ground
- 5 PGND P Power ground
- 4, 8, 9, 10, 14 NC - Not connected
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low.

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L6498 Electrical data

3 Electrical data

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings(1)
Value
Symbol Parameter Unit
Min. Max.

VCC Supply voltage -0.3 21 V

VPGND Low-side driver ground VCC - 21 VCC + 0.3 V
VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V
Boot DC voltage -0.3 500 V
VBOOT
Boot transient withstand voltage (Tpulse < 1 ms) - 620 V
Vhvg High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V
Vlvg Low-side gate output voltage (P)GND - 0.3 VCC + 0.3 V
Vi Logic input pins voltage -0.3 15 V
dVOUT/dt Allowed output slew rate - 50 V/ns
PTOT Total power dissipation (TA = 25 °C) SO-14 - 1 W
TJ Junction temperature - 150 °C
Tstg Storage temperature -50 150 °C
ESD Human body model 2 kV
1. Each voltage referred to GND\SGND unless otherwise specified.

3.2 Thermal data

Table 3. Thermal data
Symbol Parameter Package Value Unit

SO-8 185
Rth(JA) Thermal resistance junction to ambient °C/W
SO-14 120

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Electrical data L6498

3.3 Recommended operating conditions

Table 4. Recommended operating conditions
Symbol Pin Parameter Test condition Min. Max. Unit

VCC VCC Supply voltage - 10 20 V

VPS(1) SGND - PGND Low-side driver ground - -5 +5 V
VBO(2) BOOT - OUT Floating supply voltage - 9.3 20 V
DC output voltage - - 9(3) 480 V
VOUT OUT
OUT transient withstand voltage Tpulse < 1 ms - 600 V
fSW - Maximum switching frequency HVG, LVG load CL = 1 nF - 800 kHz
TJ - Junction temperature - -40 125 °C
TA - Ambient temperature(4) - -40 125 °C
1. VPS = VPGND - SGND.
2. VBO = VBOOT - VOUT.
3. LVG off. VCC = 12.5 V. Logic is operational if VBOOT > 5 V.
4. Maximum ambient temperature is actually limited by TJ.

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L6498 Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics (VCC = 15 V; TJ = +25 °C; PGND = SGND

Symbol Pin Parameter Test condition Min. Typ. Max. Unit

Low-side section supply

VCC_hys VCC UV hysteresis - 0.5 0.6 0.72 V

VCC _thON VCC UV turn ON threshold - 8.7 9.3 9.8 V
VCC _thOFF VCC UV turn OFF threshold - 8.2 8.7 9.2 V
VCC vs.
(S)GND Undervoltage quiescent supply VCC = 7 V
IQCCU - 160 210 µA
current LIN = GND; HIN = GND
VCC = 15 V
IQCC Quiescent current - 340 480 µA
LIN = 5 V; HIN = GND

High-side floating section supply(1)

VBO_hys VBO UV hysteresis - 0.48 0.6 0.7 V

VBO_thON VBO UV turn ON threshold - 8.0 8.6 9.1 V
VBO_thOFF VBO UV turn OFF threshold - 7.5 8.0 8.5 V
BOOT vs.
OUT Undervoltage VBO quiescent VBO = 7 V
IQBOU - 20 30 µA
current LIN = GND; HIN = 5 V
VBO = 15 V
IQBO VBO quiescent current - 90 120 µA
LIN = GND; HIN = 5 V
ILK - High voltage leakage current Vhvg = VOUT = VBOOT = 600 V - - 8 µA
RDS(on) - Bootstrap diode on resistance(2) - - 175 - 

Output driving buffers

LVG/HVG ON
High/low-side source short- 1.7 2 - A
Iso TJ = 25 °C
circuit current
Full temperature range 1.4 - - A
LVG, HVG
LVG/HVG ON
High/low-side sink short-circuit 2 2.5 - A
Isi TJ = 25 °C
current
Full temperature range 1.55 - - A

Logic inputs

Low level logic threshold

Vil - 0.95 - 1.45 V
LIN, HIN voltage
vs. (S)GND High level logic threshold
Vih - 2 - 2.5 V
voltage
IHINh HIN vs. HIN logic “1” input bias current HIN = 15 V 120 200 260 µA
IHINl (S)GND HIN logic “0” input bias current HIN = 0 V - - 1 µA
ILINl LIN vs. LIN logic “1” input bias current LIN = 15 V 120 200 260 µA
ILINh (S)GND LIN logic “0” input bias current LIN = 0 V - - 1 µA

DocID030318 Rev 3 7/20

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Electrical characteristics L6498

Table 5. Electrical characteristics (VCC = 15 V; TJ = +25 °C; PGND = SGND (continued)

Symbol Pin Parameter Test condition Min. Typ. Max. Unit

LIN, HIN
RPD Logic inputs pull-down resistor - 58 75 125 k
vs. (S)GND

Dynamic characteristics (see Figure 5)

HIN vs. High/low-side driver turn-on VOUT = 0 V;

ton - 85 120 ns
HVG; propagation delay VBOOT = VCC;
LIN vs. High/low-side driver turn-off CL = 1 nF;
toff LVG - 85 120 ns
propagation delay Vi = 0 to 3.3 V
Delay matching, HS and LS
MT - - - - 30 ns
turn-on/off(3)
tr Rise time CL = 1 nF - 25 - ns
LVG, HVG
tf Fall time CL = 1 nF - 25 - ns
1. VBO = VBOOT - VOUT.
2. RDSON is tested in the following way:
RDSON = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1 (VCC, VBOOT1) - I2(VCC, VBOOT2)]
where I1 is BOOT pin current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.
3. MT = max. (|ton (LVG) - toff (LVG)|, |ton (HVG) - toff (HVG)|, |toff (LVG) - ton (HVG)|, |toff (HVG) - ton (LVG)|).

Figure 5. Timing

 
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8/20 DocID030318 Rev 3

L6498 Truth table

5 Truth table

Table 6. Truth table

Input Output

LIN HIN LVG HVG

L L L L
L H L H
H L H L
(1)
H H L L(1)
1. Interlocking function.

DocID030318 Rev 3 9/20

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Typical application diagram L6498

6 Typical application diagram

Figure 6. Typical application diagram

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Figure 7. Suggested PCB layout (SO-8)

10/20 DocID030318 Rev 3

L6498 Typical application diagram

Figure 8. Suggested PCB layout (SO-14)

DocID030318 Rev 3 11/20

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Bootstrap driver L6498

7 Bootstrap driver

A bootstrap circuitry is needed to supply the high voltage section. This function is usually
accomplished by a high voltage fast recovery diode (Figure 9). In the L6498 an integrated
structure replaces the external diode.

CBOOT selection and charging

To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:

Equation 1
Q gate
C EXT = --------------
V gate

The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:

Equation 2
C BOOT >>>C EXT

if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has also to take into account
the leakage and quiescent losses.
HVG steady-state consumption is lower than 120 A, so if HVG TON is 5 ms, CBOOT has to
supply 0.6 C. This charge on a 1 F capacitor means a voltage drop of 0.6 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to SGND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value:
175 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to
take into account.
The following equation is useful to compute the drop on the bootstrap DMOS:

Equation 3
Q gate
V drop = I ch arg e R DS  on   V drop = ------------------R DS  on 
T ch arg e

where Qgate is the gate charge of the external power MOS, RDS(on) is the on resistance of
the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.

12/20 DocID030318 Rev 3

L6498 Bootstrap driver

For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:

Equation 4
30nC
V drop = ---------------  175  1V
5s

Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.

Figure 9. Bootstrap driver with external high voltage fast recovery diode

DBOOT

VCC BOOT

H.V.

HVG
CBOOT

OUT
TO LOAD

LVG

DocID030318 Rev 3 13/20

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Package information L6498

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

14/20 DocID030318 Rev 3

L6498 Package information

8.1 SO-8 package information

Figure 10. SO-8 package outline

Table 7. SO-8 package mechanical data

Dimensions (mm)
Symbol Notes
Min. Typ. Max.

A - - 1.75 -
A1 0.10 - 0.25 -
A2 1.25 - - -
b 0.28 - 0.48 -
c 0.17 - 0.23 -
D 4.80 4.90 5.00 -
E 5.80 6.00 6.20 -
E1 3.80 3.90 4.00 -
e - 1.27 - -
h 0.25 - 0.50 -
L 0.40 - 1.27 -
L1 - 1.04 - -
k 0 - 8 Degrees
ccc - - 0.10 -

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Package information L6498

Figure 11. SO-8 suggested land pattern

1.27

0.6
3.9

6.7

16/20 DocID030318 Rev 3

L6498 Package information

8.2 SO-14 package information

Figure 12. SO-14 package outline

Table 8. SO-14 package mechanical data

Dimensions (mm)
Symbol
Min. Typ. Max.

A 1.35 - 1.75
A1 0.10 - 0.25
A2 1.10 - 1.65
B 0.33 - 0.51
C 0.19 - 0.25
D 8.55 - 8.75
E 3.80 - 4.00
e - 1.27 -
H 5.80 - 6.20
h 0 - -
25 - 0.50 -
L 0.40 - 1.27
k 0 - 8
ddd - - 0.10

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Package information L6498

Figure 13. SO-14 suggested land pattern

1.27

0.6
4.0

6.7

18/20 DocID030318 Rev 3

L6498 Ordering information

9 Ordering information

Table 9. Device summary

Order code Package Packaging

L6498D SO-8 Tube

L6498DTR SO-8 Tape and reel
L6498LD SO-14 Tube
L6498LDTR SO-14 Tape and reel

10 Revision history

Table 10. Document revision history

Date Revision Changes

08-Feb-2017 1 Initial release.

Updated Table 5 on page 7 (replaced “INR_PD” by “RPD”,
added Test condition to “toff”).
26-Apr-2017 2
Updated order codes in Table 9 on page 19.
Minor modifications throughout document.
13-Sep-2017 3 Updated Table 4 on page 6 (added TA symbol and note 4.).

DocID030318 Rev 3 19/20

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 L6498

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20/20 DocID030318 Rev 3

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