EE 316 Digital Logic Design

Spring 2016
Course: EE 316; Unique Numbers 16025, 16030, 16035, 16040
Lecture: T-Th 11:00 AM 12:30 PM in RLM 6.104
Final Examination: Tuesday, May 17, 2016 9:00AM to 12:00PM
Lab Schedule: In ECJ 1.222
The labs are conducted by the Teaching Assistants
Unique Number
Day
Time
16025
F
10:00 11:00 AM
16030
W
11:00 AM NOON
16035
F
NOON 1:00 PM
16040
W
1:00 2:00 PM
Instructor:
Dr. Al Cuevas, Email: Use Canvas to e-mail
Office Hours: T-Th: 9:30 AM to 11:00 AM and/or T-Th: 12:30 PM to 2:00 PM (tentative)
Location: Academic Annex ACA 150; or by appointment
Phone: 512.522.3721 (Voice-only, No text messages.)
Teaching Assistants:
Poulami Das, Email: poulami@utexas.edu
Wei Ye, Email: weiye@utexas.edu
Kangjoo Lee, Email: kangjoolee1@utexas.edu
Amanda Akin, Email: amanda.akin@live.com
Jackson Jake Haenchen, Email: jackson_haenchen@utexas.edu
Text:
Fundamentals of Logic Design, 7th Edition, by Charles Roth and Larry Kinney. The latest edition of the
text is required. The book includes a CDROM with software that you will need to perform the labs.
Software:
You will be required to use the software that is on the CDROM: LogicAid and SimuAid.
NOTE: If you purchase a used book, make sure it has the CDROM. The University cannot
provide the software to you.
In addition, as we begin to work with the FPGA board (Basys3 from Digilent using the Xilinx Artix-7),
you will need to be familiar with the Xilinx Tool: Vivado WebPACK Edition. This version does not
require a software license and will work with the Artix-7 FPGA on the Basys3 board. See the Xilinx
website for more information: http://www.xilinx.com/support/download.html
Course Website:
Use of the cloud-hosted learning management system, Canvas, will be used throughout this course. In
addition, Piazza will be used for Q/A and student discussions.
Course Objectives:
The textbook for this course is organized by units. We will be covering all units except for Units 6 and
19. The important topics covered will be:
1. Binary Arithmetic and Boolean Algebra (Units 1-5)
2. Implementation of Logic Functions using NAND and NOR gates (Units 7-8)
3. Muxes, Decoders, and Programmable Logic Devices (Unit 9)
4. VHDL Hardware Description Language (Unit 10)
5. Design of Sequential Logic Circuits: latches, flip-flops, clocks, using both state charts as well as
VHDL (Units 11-18)
6. System Level Design with VHDL (Unit 20)

In addition, special topics will be included throughout the semester that are not covered by the book.
You will be tested on this material.
Catalog Description:
Boolean algebra; analysis and design of combinational and sequential logic circuits; state machine
design and state tables and graphs; simulation of combinational and sequential circuits; applications to
computer design; and introduction to hardware description languages (HDLs) and field-programmable
gate arrays (FPGAs).
Prerequisites:
Computer Science 429 or Electrical Engineering 306 with a grade of at least C-.
Attendance:
You are expected to attend each and every lecture.
Grading Policy:
Homework
Pop Quizzes
Labs
Mid-Term Exam 1
Mid-Term Exam 2
Final Exam

5%
5%
30%
15%
15%
30%

A = 90%100%
B = 80%89%
C = 70%79%
D = 60%69%
F = 0%59%

The numerical course grade is computed by weighting the raw scores as indicated above. Letter grades
are determined via the following scale. Plus and minus grades are not used in these sections. A
course/instructor survey will be conducted at the end of the semester via the standard MEC form.
The examinations will consist of a number of questions for which the answers are to be recorded on an
answer sheet. Only the answers on the answer sheet are graded.
There are no make-up examinations. Excused absence from an examination must be approved in
advance. Absence is excused only in extreme circumstances (serious illness, death in the immediate
family, etc.). Requests for excused absences should be made in writing and must be supported by
appropriate documentation. Unexcused absence from an examination will result in a grade of zero for
that examination.
By UT Austin policy, you must notify me of your pending absence at least fourteen days prior to the
date of observance of a religious holiday. If you must miss a class, an examination, a work assignment,
or a project in order to observe a religious holiday, you will be given an opportunity to complete the
missed work within a reasonable time after the absence.
There is no re-grading of examinations, unless you feel that there is an error. In this case, you should
submit a written request. Verbal requests will not be considered.
The fourth class day is the last day of the official add/drop period. Drops after this time must be
approved by the Deans office.
University policies on scholastic dishonesty will be strictly enforced. Students who violate University
rules on scholastic dishonesty (including, but not limited to, cheating, plagiarism, collusion, or falsifying
academic records) are subject to disciplinary penalties, including failure in the course or dismissal from
the University.
Disabilities: Upon request the University of Texas at Austin provides appropriate academic adjustments
for qualified students with disabilities. For more information, contact the Division of Diversity and

Community Engagement, Services for Students with Disabilities at 512-471-6259 or

http://www.utexas.edu/diversity/ddce/ssd/
Web-based, password-protected class sites are associated with all academic courses taught at the
University. Electronic class rosters are a component of the sites. Students who do not want their names
to be included in these electronic class rosters must restrict their directory information in the Office of
the Registrar, Main Building, Room 1.
Occupants of buildings on The University of Texas at Austin campus are required to evacuate buildings
when a fire alarm is activated. Alarm activation or announcement requires exiting and assembling
outside. Familiarize yourself with all exit doors of each classroom and building you may occupy.
Remember that the nearest exit door may not be the one you used when entering the building.
Students requiring assistance in evacuation shall inform their instructor in writing during the first week
of class. In the event of an evacuation, follow the instruction of faculty or class instructors. Do not reenter a building unless given instructions by the following: Austin Fire Department, The University of
Texas at Austin Police Department, or Fire Prevention Services office.

Lecture Schedule:
The following lecture schedule is approximate. It indicates the topics, their order and probable
examination dates, but it is subject to change.
Days
1/19, 1/21
1/26
1/28, 2/2
2/4, 2/9
2/11, 2/16
2/18, 2/23
2/25
3/1
3/3
3/8, 3/10
3/22, 3/24
3/29, 3/31
4/5, 4/7
4/12
4/14
4/19
4/21
4/26, 4/28
5/3
5/5

Unit
Topic
Units 1-2
Introduction, Number Systems and Conversion
Units 2-3
Boolean Algebra
Units 4-5
Applications of Boolean Algebra, Karnaugh Maps
Unit 7
Multi-level logic with NAND and NOR gates
Unit 8
Combinational Circuit Design and Simulation using gates
Unit 9
Multiplexers, Decoders, and Programmable Logic Devices
Unit 10
Introduction to VHDL
Exam Review
Midterm Exam#1: (Units 1-8)
Unit 11
Latches and Flip-flops
Unit 12
Registers and Counters
Unit 13
Analysis of Clocked Sequential Circuits
Unit 14-15
State graphs and tables, State minimization
Unit 16
Sequential Circuit Design
Midterm Exam#2: (Units 9-14)
Unit 16
Sequential Circuit Design
Unit 17
VHDL for Sequential Logic
Unit 18
Circuits for Arithmetic Operations
Unit 20
VHDL for Digital System Design
Stopwatch: Counter design, Clock design, 7-Segment Multiplex
Special Topics
Design

Homework:
Homework problems will be assigned almost every week. You are expected to submit your homework
at the beginning of class. No late submission will be graded.
Below is a tentative list of homework problems and due dates. Announcements will be made in class
and on Canvas regarding changes. If no changes are announced, assume the list below.
Each homework assignment will be worth 100 points.
1.4(a), 1.7(b,c), 1.8, 1.10(a,d), 1.19(b), 1.37(a,c,e), 2.3(a,f), 2.5(a,b), 2.6(a,f),
2.8(a), 2.9, 2.12(a,f), 2.15(a), 2.16(a), 2.21, 2.22(a), 2.24(a)
3.11, 3.12, 3.14(a,e), 3.15(a), 3.16(b), 3.19(a), 3.21(a,b), 3.25(f), 3.32(c),
3.38(a), 4.9(a-d), 4.13, 4.16, 4.23, 4.24, 4.35, 4.40
5.6(a, c), 5.7(b), 5.9(b), 5.14(d, f), 5.22(a,c,e,g), 5.25(c,d), 5.34

HW1:

1/28

HW2:

2/4

HW3:

2/11

HW4:

2/18

HW5:
HW6:
HW7:
HW8:

2/25

7.2(a,b), 7.8(a), 7.10, 7.17, 7.20, 7.21(a-b), 7.22, 7.25(a), 7.30, 7.39, 7.42,
7.45(a)
8.2, 8.3, 8.6, 8.7, 8.10, 8.11, 8.16

3/10

9.1, 9.6, 9.11, 9.14, 9.16, 9.19, 9.31, 9.41, 10.10, 10.11, 10.14(a), 10.15

3/24

11.13, 11.14, 11.18, 11.26, 12.6, 12.9, 12.13, 12.21(a-c), 12.26, 12.36

4/7

13.2, 13.4, 13.7, 13.11, 13.18

HW9:

4/21

HW10:
HW11:

4/28

14.12, 14.14, 14.18, 14.36, 15.2, 15.8, 15.12(a,c,d), 15.17, 15.18, 15.24,
15.37(a-b), 15.38(c), 16.21(a), 16.23(a-b), 16.33(a)
17.3, 17.4, 17.8, 17.11, 17.18(a,c,d), 17.20(a-b), 17.24, 17.28(a)

do not

18.9, 18.12(a), 18.19(a), 18.28(a-b)

submit

Lab Schedule:
You are expected to sign up for one of the lab sessions associated with the class. The labs will be
conducted in ECJ 1.222. Lab weeks run from Monday to Friday, starting the week of 1/25/16.
Lab assignments are due on the Due by date by the end of students lab section. Submissions need
to be made online through Canvas. After submitting on Canvas, students still need to have the lab
checked out by any TA. If the wait is too long, students can come back and checkout anytime during
the week after the lab is due. Labs turned in late receive 5% penalty per working day (up to a week,
after which there is no credit) that it is late. Labs need to be checked out within a week after the due
date, after which students will not receive any credit for the lab. Early submission of labs receives 5%
extra credit if submitted 2 working days early for most labs (there is no early bonus for Lab 1). Note that
there are some labs for which early submission bonus will not apply, and this will be announced. Early
submission is encouraged and can save time on the checkout process. Please put name and lab
section on lab submissions.
The number of points assigned to each lab is shown in parentheses.
Week

Lab

Week 2 Lab 1 (100 pts)

Week 3 No lab
Week 4 Lab 2 (100 pts)
Week 5 Lab 3.1 (50 pts)
Lab 3.2 (150
pts)
Week 7 No new lab
Week 6

Week 8 Lab 4 (100 pts)

Lab 5.1 (150
pts)
Week 9
Lab 5.2 (50 pts)
Week 10 No new lab
Lab 6.1 (150
pts)
Week 11

Topic

Demo (by
TA)

Unit 4 - Design a 4-input 1-output circuit and

1/25-1/29
verify with SimUaid. (4.13 or 4.14)
Problem solving session
2/1-2/5
Unit 8 - Design logic for a 7 segment display
2/8-2/12
using DesignAid and SimUaid. (8.A-8.S)
Unit 10 - Download your design from Lab 2 to
2/15-2/19
the Xilinx board.
Unit 10 - Design an adder/decoder/mux/ROM in
2/22-2/26
VHDL using DirectVHDL. (10.A-10.N)
Problem Review
2/29-3/4
Unit 12 - Use SimUaid to design a circuit that
counts in a specified sequence. (12.10.a3/7-3/11
12.10.n)
5.1 Unit 16 - Design a state machine;
implement in output and next-state logic with
inv, 2/3/4 ip NAND/NOR (16.1-16.14)
3/21-3/25
5.2 Unit 16 - Write your design and testbench
from 5.1 in VHDL and download to the Xilinx
board.
Problem Review / Lab Review
3/28-4/1
Unit 17 - Simulate a sequential design in VHDL
(17.A - 17.M)
4/4-4/8

Lab 6.2 (50 pts)

Week 12 No new lab
Problem Review / Lab Review
4/11-4/15
Unit 20 - Design a multiplier/divider with VHDL
Week 13 Lab 7 (100 pts)
4/18-4/22
(20.A-20.W)
Week 15 Final Review
Problem Review / Lab Review
4/25-5/6

Due By
2/1-2/5
N/A
2/15-2/19
2/22-2/26
3/7-3/11
N/A
3/21-3/25

5.1 4/4-4/8
5.2 4/4-4/8

N/A
4/18-4/22
N/A
5/2-5/6
N/A