AN1177

Op Amp Precision Design: DC Errors

Author:

Kumen Blake
Microchip Technology Inc.

INTRODUCTION
Engineers that use op amps in their circuits; especially
those new to analog or op amp circuit design. Also
intended for engineers that want to understand op amp
DC specifications.

Description
This application note covers the essential background
information and design theory needed to design a
precision DC circuit using op amps. Topics include:

Op Amp DC Specifications
Circuit Analysis
Circuit Optimization
Advanced Topics
References

This application note is limited to voltage feedback

(traditional) op amps. Those interested in current feedback op amps will benefit from the information here; the
DC specifications and op amp DC model have many
similarities.
For those that are interested, a simple circuit for
measuring input offset voltage has been included in
Appendix A: Input Offset Measurement Circuit.

DC SPECIFICATIONS
There are a small number of DC specifications that
describe errors at the input of an op amp. This section
organizes these specifications into those related to the
input offset and the others related to input bias
currents.

Ideal Op Amp
Figure 1 shows the ideal, DC model for op amps (the
external circuitry is not shown). All error sources are
ignored and the open-loop gain (AOL) is infinite. The
output voltage is related to the input voltages as shown
in Equation 1.
VN
VI

FIGURE 1:

AOL

VOUT

Ideal, DC Op Amp Model.

EQUATION 1:
V OUT = A OL ( V N V I )
When negative feedback is applied, the ideal op amps
infinite gain forces VN and VI to be exactly equal; this is
the virtual short that some authors talk about. [ 1, 2]
When positive feedback is applied (e.g., when used as
a comparator), VOUT swings as far negative or positive
as it can (to the rails), depending on the sign of the difference (VN VI).

Op Amp Model with DC Errors

Figure 2 shows a physically based, DC model for op
amps. VPLUS and VMINUS are the external input voltages, while VN and VI are the internal input voltages.
VOST represents the total input offset voltage error. The
non-inverting bias current (IBN) and inverting bias current (IBI) represent the physical currents seen at each
of the two input pins. AOL is the finite DC open-loop
gain.

2008 Microchip Technology Inc.

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It is important to understand the units for these
specifications. An engineer not used to op amp data
sheets may be confused by the units shown. The
following list should clear up the confusion.

VDD
VOST
VPLUS
VMINUS

VN
VI

IBN

AOL

VOUT

IBI
VSS

FIGURE 2:
Amp Model.

Physically Biased, DC Op

Input Offset Related Specifications

A positive VOST creates a positive shift in the output
voltage (VOUT). The DC voltages are:

EQUATION 2:
V N = V PLUS + V OST
V I = V MINUS
V OUT = A OL ( V N V I )
= A OL ( ( V PLUS V MINUS ) + V OST )
The total input offset voltage (VOST) collects the
following specifications into one, easy to use
parameter:
Input Offset Voltage (VOS):
- Specified offset
- Describes VOST at a specific bias point
DC Open-Loop Gain (AOL):
- AOL = VOUT/VOST
Common Mode Rejection Ratio (CMRR):
- CMRR = VCM/VOST
- VCM is the common mode input voltage
(average of VPLUS and VMINUS)
Power Supply Rejection Ratio (PSRR):
- PSRR = (VDD VSS)/VOST
Input Offset Drift with Temperature (VOS/TA):
- Describes how VOST changes with TA;
actually VOST/TA
- TA is the ambient temperature

VOS units are: mV or V

AOL units do not usually report the relationship
shown above:
- V/V for 1/AOL = VOST/VOUT
- dB for 20log(AOL)
CMRR units are similar to the AOL units:
- V/V for 1/CMRR = VOST/VCM
- dB for 20log(CMRR)
PSRR units are similar to the AOL units:
- V/V for 1/PSRR = VOST/(VDD VSS)
- dB for 20log(PSRR)
VOS/TA units are: V/C or nV/C
Note:

Notice that the gains AOL, CMRR and

PSRR, when reported in V/V, are actually
their reciprocals. This form of the gains is
best for statistical analyses; the values
tend to have a Gaussian distribution.

Sometimes PSRR is split in two pieces: PSRR+ that is

related to changes in VDD (VDD) and PSRR that is
related to changes in VSS (VSS).
These quantities are lumped together in the following
equation, where the changes in bias voltages are from
those specified for VOS (all units are converted to either
V or V/V):

EQUATION 3:
V OUT V CM V
V OS
DD V SS
V OST = V OS + -------------------- + ----------------- + ----------------- + --------------- + T A ---------------A
CMRR PSRR PSRR
TA
OL

Notice that all of the specifications will give a positive

change in VOST when the corresponding changes are
positive.

Input Current Related Specifications

The input bias currents (IBN and IBI) create voltage
drops across external resistances, which cause VOUT
to shift. By convention, the currents going into the pins
VPLUS and VMINUS are positive.
Traditionally, these physically based currents have
been mathematically transformed into the equivalent
pair of currents IB (input bias current) and IOS (input offset current). These are the average of IBN and IBI, and
their difference, respectively:

EQUATION 4:
( I BN + I BI )
I B = -------------------------2
I OS = I BN I BI

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This model makes sense for traditional op amps that
have IBN and IBI nearly equal. This means that, in this
case, IB is much larger than IOS. This happens because
these currents are caused by similar physically
phenomena (e.g., matched transistor pair with similar
input bias currents). Figure 2 shows how these
specified currents are modeled in a circuit.
VDD
VOST
VPLUS
VMINUS

VN
VI

AOL

VOUT

CIRCUIT ANALYSIS
Using a few simple techniques, it is easy to analyze the
DC error performance of op amp circuits. Several
common circuits illustrate these techniques.

Resistance Seen by the Non-inverting

Input
Figure 4 is a simple circuit with a source and several
impedances attached to the non-inverting input. The
process of calculating the equivalent resistance seen
by the non-inverting input will be described using this
circuit as the starting point.
R1

IB + IOS/2

IB IOS/2

L1

V1

C1

U1
VOUT

R2

VSS

FIGURE 3:
Equivalent DC Model for
Traditional Op Amps.
Some newer op amp architectures have IOS near to the
same magnitude as IB. This happens because the
physical causes of IBN and IBI are not physically related
(they are independent or uncorrelated). Most data
sheets still use IB and IOS as the specifications.
The input currents depend strongly on architecture,
type of input transistors, and temperature. As
discussed before, traditional parts have IB >> IOS.
Some of the newer architectures have IOS and IB of
about the same size.
Most op amps have ESD diodes at the inputs. PN
junction ESD diodes tend to have small reverse
leakage at room temperature. These leakage currents
increase by a factor of 2 for each 10C increase in
temperature. Since the ESD diodes tend to match well,
the differences between leakage currents tend to be
small. These leakage currents are a part of the input
bias currents. When an input goes outside the supply
voltage(s) the ESD diodes are tied to, the forward
current can grow to be very large.
CMOS inputs transistors have very small input bias
currents. Most of these op amps use ESD diodes at the
input for protection; the reverse leakage currents of
these ESD diodes are the dominant input bias currents.
Electrometer grade op amps minimize input currents.
They typically use FET transistors at the input that give
currents in the femto-ampere (1015A) range.
Bipolar inputs have larger input bias currents. They are
the input differential pairs base currents, which do not
change much with supply voltage. They will change
significantly with temperature (e.g., a 4 range
between -40C and +125C). These op amps usually
use ESD diodes, which increase the bias currents;
especially at high temperatures.

2008 Microchip Technology Inc.

FIGURE 4:

Simple Circuit.

The first step is to replace all external components with

their DC equivalent for a Thevenin analysis:

Voltage sources become 0V (short circuit)

Current sources become 0A (open circuit)
Resistors are left as is
Capacitors become (open circuit)
Inductors become 0 (short circuit)

Figure 5 shows the resulting circuit when this is done to

those components attached to the non-inverting input
of the op amp in Figure 4. A test source (VX) has been
added to help in the Thevenin analysis.
IX

R1

VX
R2

FIGURE 5:
Equivalent DC Circuit for
Non-inverting Input.
The equivalent resistance seen by the non-inverting
input, for this example, is:

EQUATION 5:
V
R NEQ = -----XIX
= R 1 || R 2
This resistance is used in the error calculations for the
non-inverting bias current (IBN) source. Figure 6 shows
how this is accomplished; the error at the op amp input
is calculated at this point of the process.

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AN1177
IBN

IX

U1

VX

VOUT

VIBN
RNEQ

R3
R2
VIBN = -IBN RNEQ

FIGURE 6:
Application to Non-inverting
Bias Current Error Calculations.

FIGURE 9:
Inverting Input.

The error voltage (VIBN) shown in Figure 6 can be

placed in an equivalent circuit diagram that does not
explicitly show the current IBN. This will make the
analysis easier, and more consistent, in later steps.
This new equivalent circuit is shown in Figure 7 (IBN is
already included in VIBN). The VIBN source, when it is
positive, will produce a positive change in VOUT.

The equivalent resistance seen by the inverting input,

for this example, is:

Equivalent DC Circuit for the

EQUATION 6:
V
R IEQ = -----XIX
= R 2 || R 3

0
R1
V1

L1
C1

U1
VOUT

VIBN

This resistance is used in the error calculations for the

inverting bias current (IBI) source. Figure 10 shows
how this is done for the error at the op amp output,
referred to the input.

R2
U1

VIBN = -IBN RNEQ

FIGURE 7:
Application to Non-inverting
Bias Current Error Calculations.

IBI

This equivalent circuit has the same connections as the

original one (Figure 4) to simplify the analysis; this will
be useful later on as we combine all of the error terms.

RIEQ
VIBI

Resistance Seen by the Inverting Input

Figure 8 is a non-inverting gain amplifier. The process
discussed in the last section will be used here to
calculate the resistance seen by the inverting input.

VOUT

V1
R2

FIGURE 8:

R3

Non-inverting Gain Circuit.

VIBI = IBI RIEQ

FIGURE 10:
Application to Inverting Bias
Current Error Calculations.
Note:

U1

VOUT

Since the op amps inverting input voltage

must equal its non-inverting input voltage,
VIBI is shown as a change in VOUT referred
to the input.

The error voltage (VIB) shown in Figure 10 is placed in

an equivalent circuit diagram that does not explicitly
show the current IBI; see Figure 11 (IBI is already
included in VIBI). The VIBI source, when it is positive,
will produce a positive change in VOUT.

The same process of generating a Thevenin equivalent

applies here, with one short cut:
The op amps output (VOUT) is treated as a
voltage source
- It becomes a short to ground
Figure 9 shows the resulting circuit at the inverting
input, with the test source (VX).

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The following examples will show how this concept is
applied in common op amp circuits.

U1

VOUT

Note:

0
VIBI
R2

The concept of noise gain is central to

understanding op amp behavior. For
instance, it simplifies op amp bandwidth,
noise and stability analyses.

Output DC Error

R3
VIBI = IBI RIEQ

FIGURE 11:
Application to Inverting Bias
Current Error Calculations.
The resistors R2 and R3 are shown with the same
connections as the original circuit (Figure 8) to simplify
the analysis; this will be explained in the next section.

Combined Input Voltage Errors and Noise

Gain
All of the DC errors at an op amps input (VOST, VIBN
and VIBI) can be combined into one equivalent voltage
source (VIE) at the non-inverting input pin (see
Figure 12):

Now we can quickly calculate the output error of the op

amp (VOE) using the information we have developed.
The principle of superposition gives:

EQUATION 9:
V OE = G N V IE
= G N ( V OST + V IBN + V IBI )

Examples
UNITY GAIN BUFFER
Figure 13 shows a unity gain buffer using an op amp.
The op amps DC model is shown inside the dashed
box.

EQUATION 7:
IBN VOST

V IE = V OST + V IBN + V IBI

U1

VIN

VOUT

VIE
VINk

Feedback
and
Signal Path
Circuitry

IBI
U1

VOUT

FIGURE 13:

Unity Gain Buffer.

Because the resistances seen by the op amp inputs are

zero and GN = 1 V/V, the output voltage is simply:

FIGURE 12:
Circuit Diagram Illustrating
the Concept of Noise Gain.
Noise gain (GN) is the DC gain from VIE (at the noninverting input pin) to VOUT when the op amp operates
in a closed-loop condition, when all other (external)
energy sources are zero. GN is positive for stable feedback loops. This gain can be obtained with any reasonable circuit analysis method. In equation form, we
have:

EQUATION 8:
V OUT
G N = ------------V IE
Where:
VINk

0V

1 to n

2008 Microchip Technology Inc.

EQUATION 10:
V OUT = V IN + V OST
Lets use Microchips MCP601 op amp to illustrate this
design. Well assume that VCM, VDD and VOUT vary
across their complete ranges. Well use an arbitrary
estimate of the worst-case value for VOS/TA (see the
data sheet for the official specifications). R1 and R3 will
be 0.1% resistors.
Note:

Since the MCP601s common mode input

voltage range (VCMR), at +25C, is limited
to the range -0.3V and VDD 1.2V, there
will be large output errors when VCM
approaches VDD.

DS01177A-page 5

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EXAMPLE 1:

EXAMPLE 2:
Maximum VOST = 3.8 mV

Maximum VOE = VOST:

Selected Resistors (see Figure 14):

VOS < 2.00 mV

VOUT/AOL (2.65V)/(100 kV/V)
0.03 mV

R3

20.0 k

VDD/PSRR (1.40V)/(10.0 kV/V)

0.14 mV

R2

2.21 k

R1

2.00 k

GN

10.05 V/V

VCM/CMRR (4.3V (-0.3V))/(5.62 kV/V)

0.82 mV = 0.41 mV
TA(VOS/TA) (100C) (12 V/C)
1.20 mV
VOST 3.8 mV

Figure 14 shows a non-inverting gain amplifier with an

LC low-pass filter at the input. The op amps DC model
is shown inside the dashed box.
R1

C1

L1

RNEQ

2.00 k

VIBN

-(5 nA + 0.5 nA)(2.00 k) = -11 V

Maximum VIBN:

NON-INVERTING AMPLIFIER

VIN

Maximum VIBN:

RIEQ

1.99 k

VIBN

(5 nA 0.5 nA)(1.99 k) = 9 V

Maximum VOE:
VOE

38 mV

INVERTING AMPLIFIER
Figure 15 shows an inverting gain amplifier. The op
amps DC model is shown inside the dashed box.

IBN VOST
IBN VOST

U1
VOUT

R1

U1
VOUT

R1

IBI

IBI
R2

R3

FIGURE 14:

VIN
R2

Non-inverting Gain Amplifier.

The output voltage with error is:

R3

FIGURE 15:

Inverting Gain Amplifier.

The output voltage with error is:

EQUATION 11:
V OE = G N ( V OST + V IBN + V IBI )

EQUATION 12:
V OE = G N ( V OST + V IBN + V IBI )

V OUT = G N V IN + V OE

V OUT = ( G N 1 ) V IN + V OE

Where:
Where:
GN

1 + R3/R2

RNEQ

R1

RIEQ

R2||R3

VIBN

IBNRNEQ

VIBI

IBIRIEQ

The MCP601 VOST calculations in Example 1 can be

used for a gain of +10 V/V example:

DS01177A-page 6

GN

1 + R3/R2

RNEQ

R1

RIEQ

R2||R3

VIBN

IBNRNEQ

VIBI

IBIRIEQ

Notice that Example 2 is easily modified for an inverting

gain of -9 V/V; the resistors and VOE are the same (only
the signal gain is changed).

2008 Microchip Technology Inc.

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DIFFERENCE AMPLIFIER

CIRCUIT OPTIMIZATION

Figure 16 shows a difference amplifier. The op amps

DC model is shown inside the dashed box. Notice that
this circuit can be analyzed quickly using superposition.

There are a few, simple design techniques that can

quickly help a designer reach an acceptable accuracy.

Gain Selection
R1

R2

VP

VREF
IBN VOST
U1
VOUT
IBI

VM
R3

R4

FIGURE 16:

Difference Amplifier.

The output voltage with error is:

EQUATION 13:
V OE = G N ( V IE + V IBN + V IBI )
V OUT = ( G N 1 ) ( V P V M ) + V REF + V OE
Where:
R2

R1

R4

R3

GN

1 + R2/R1 = 1+R4/R3

RNEQ

R1||R2

RIEQ

R3||R4

VIBN

IBNRNEQ

VIBI

IBIRIEQ

Using the MCP601 in a differential amplifier with gain

10 V/V gives (similar to Example 2):

Set any amplifier next to a signal source (e.g., temperature sensor) to the highest reasonable gain. This will
cause any later gains to be small; typically they will be
at a gain of 1 V/V.
This design technique minimizes the impact most of the
analog signal processing components have on the
overall error. It also allows the designer to reduce cost
by specifying more precise components only where
they are needed.

Minimizing Bias Current Errors

For the examples shown in Figure 13 through
Figure 16, it is instructive to convert the bias current
error voltages to the equivalent form using the specified
currents:

EQUATION 14:
V IBN + V IBI = I BN R NEQ + I BI R IEQ
R IEQ + R NEQ
= I B ( R IEQ R NEQ ) I OS ---------------------------------

2
Minimizing the resistances helps minimize these errors
for all op amps.
Many op amps bias current (IB) have a much larger
maximum specification than their offset current (IOS). In
that case, set RN_EQ = RI_EQ for the best performance.
When IOS is much smaller than IB, the resistor tolerance (RTOL) needs to be good enough to prevent IB
from becoming a significant contributor to the error:

EQUATION 15:
I OS
RTOL << 4 -------IB

EXAMPLE 3:
Maximum VOST = 3.8 mV
Selected Resistors (see Figure 16):
R1 = R3

2.00 k

R2 = R4

20.0 k

GN

11.00 V/V

(GN1)

10.00 V/V, the differential gain

Maximum Error Voltages:

VIBN

-(5 nA + 0.5 nA)(1.82 k) = -10 V

VIBN

(5 nA 0.5 nA)(1.82 k) = 8 V

VOE

42 mV

2008 Microchip Technology Inc.

Large input resistances can also cause a significant

shift in the input common mode voltage (VCM). In some
cases, this can significantly reduce the input common
mode voltage range (VCMR):

EQUATION 16:
R

+R

IEQ
NEQ
V CM = I B -------------------------------
2

V CMR_EQ = V CMR + V CM

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ADVANCED TOPICS

Op Amp Selection
The op amp needs to support the level of DC precision
required by the design. Table 1 shows four general op
amp architectures that give trade-offs between
performance, cost and design complexity.

TABLE 1:

OP AMP CAPABILITIES(1)
Performance for Each Architecture

Parameter

General
Purpose

Trimmed

Autocalibrated

Autozeroed

VOS
VOS/TA

VOS Aging

AOL

CMRR

PSRR

IB

IOS

Note 1:

The performance numbers signify: 1 = okay,

2 = good, 3 = better and 4 = best.

Process and Environmental Variations

Methods to evaluate a designs variation in
performance are commonly understood in the industry.
Examples include worst case analysis (all tolerances at
minimum or maximum) and RSS (Root Sum of
Squares a statistical approach).
The following list gives important op amp behaviors to
include when evaluating process and environmental
changes (almost all have a Gaussian distribution):
VOS
- All VOS values for duals and quads are
statistically independent (zero correlation)
1/AOL, 1/CMRR and 1/PSRR (in units of V/V)
VOS/TA
Offset Aging
- Increases with time
- Only specified on auto-zeroed op amp data
sheets
IB and IOS
- CMOS inputs (with ESD diodes) have an
exponential relationship with temperature
(double every 10C increase)
- Bipolar inputs typically double at -40C and
are halved at +125C
- Are typically uncorrelated

DS01177A-page 8

PCB Layout
Printed Circuit Board (PCB) layout can have a significant effect on DC precision. Effects that need to be
considered include:
Ground Loops Poor grounding techniques and
inattention to current return paths can cause
significant shifts in DC voltages
Crosstalk Other signals on a PCB can find
sneak paths through the ground, power supplies
and traces

Input Common Mode Voltage Range

A commonly overlooked error source is allowing the
signal to go outside the input voltage range. This most
commonly occurs when using a non-rail-to-rail input op
amp in unity gain; the input will cause an output error
when the VCMR is exceeded; this error grows quickly.

Output Voltage Range

There will be a significant error, that grows very quick,
when the output voltage range is exceeded. The VOL
and VOH specifications usually shown in op amp data
sheets describe non-linear behavior (i.e., when used as
a comparator). When the output approaches either
limit, VOST can increase significantly before reaching
the hard limits. For the most stringent designs, keep
VOUT within the range that the data sheet shows for the
AOL specification.

Noise
The data sheets input noise density specifications can
be used to calculate an op amps integrated output
noise (random variation in output voltage). This helps
determine the range of expected errors at any point in
time; it also can significantly reduce the output range
when there is a very high gain.

Non-linear Distortion
Non-linear distortion converts a sinewave at one
frequency into a Fourier series of tones; the undesired
tone frequencies are the harmonic distortion products.
One of these undesired tones is at zero frequency
(DC); non-linear distortion can produce DC shifts.
For example, a simple sinewave that is processed by
an amplifier with a quadratic (polynomial) response will
produce:

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Oscillations

EQUATION 17:
V IN = V M sin ( 2ft )
2

V OUT = A 0 + A 1 V IN + A 2 V IN
= A 0 + A 1 V M sin ( 2 ft ) + A 2 ( V M sin ( 2 ft ) )
= B 0 + B 1 sin ( 2 ft ) + B 2 cos ( 4 ft )

Where:
2

A2 VM
B 0 = A 0 + ------------2
B1 = A1 VM
2
A2 VM

B 2 = ----------------2
All other even order harmonic distortion terms cause a
shift in DC bias too. The quadratic term, however,
usually dominates.
Using mildly non-linear components in the signal path
can cause this effect. The cure is to select higher
quality components.
More commonly, higher frequency signals will be rerouted through a non-linear element. A common
example is discussed in detail in the next section.

EMI
Electro-magnetic Interference (EMI) at high frequencies (i.e., near and above the op amps Gain Bandwidth
Product) easily couples to the inputs of any component
on a PCB; op amps are no exception to this rule.
Because the op amp has little control over this energy,
and the ESD diodes are very fast, the latter will rectify
high frequency EMI.
The rectification of the EMI energy produces both high
frequency energy and a significant DC shift at the op
amp inputs. This appears as an unexpectedly large
VOST on many measurement boxes; they average out
the high frequency component. To see if this is an issue
with your design, use a fast oscilloscope at short time
scales.
The most effective cures for EMI problems are handled
at the PCB design level. The coupling paths include
power supply lines, magnetic loops and capacitive
metal areas.
It is possible to improve performance with high
frequency filters at the op amp inputs. Usually, however, the improvements are small. Also, the filters may
affect the feedback networks stability, causing
unexpected behaviors.

2008 Microchip Technology Inc.

We sometimes see an op amp circuit that is unstable

enough to oscillate. When this does happen, many
puzzling symptoms appear. The supply current
increases, the DC voltages in a circuit can shift,
voltages can wander and intermittent glitches can be
seen.
To find this problem, use a fast oscilloscope and
change the time scale; it may be necessary to gain up
a signal to see oscillations much smaller than 0.1V.
To verify the source of oscillation (unstable behavior),
modify component values (e.g., place a capacitor in
parallel) in different feedback loops. A change in
oscillation frequency usually indicates that the unstable
loop has been affected.
Note:

Op amps, by themselves, cannot be either

stable or unstable. The feedback loop
design (interaction of op amp and passive
components) sets the stability.

SUMMARY
This application note has covered the topic of precision
design using (voltage feedback) op amps in some
detail. It shows how all of the DC errors can be referred
to the input; they appear as an additional change in
input offset voltage. It gives results for the most
common op amp circuits: unity gain buffer, non-inverting gain amplifier, inverting gain amplifier and
difference amplifier. Tips on optimizing performance
and coverage of advanced topics help the designer
with more difficult designs. The references give
additional information on related topics.

REFERENCES
Textbook on Circuit Level Design
[1]

Paul R. Gray and Robert G. Meyer, Analysis

and Design of Analog Integrated Circuits, 2nd
Ed., John Wiley & Sons, 1984.

Textbook on Transistor Level Design

[2]

Paul R. Gray and Robert G. Meyer, Analysis

and Design of Analog Integrated Circuits, 2nd
Ed., John Wiley & Sons, 1984.

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APPENDIX A:

INPUT OFFSET
MEASUREMENT
CIRCUIT

This appendix shows a simple test circuit that can be

used on the bench to evaluate most op amps input
offset voltage and bias current performance. A simpler
circuit is discussed first, which only measures VOST. It
is then expanded to include IBN and IBI measurements.
The limitations of these circuit are also discussed.

A.1

A.1.1

CIRCUIT DESIGN

The goal is to make GN reasonably large and the error

terms (with VOST, IBN and IBI) as small as possible. The
following design choices will give good results (since
GNVOST is chosen to be so large):

EQUATION A-2:
( 25mV )
G N ------------------------------( max V OST )
R 3 typical load resistance
R3
R 2 = --------------GN 2
R
R 1 = ------3GN

Basic Input Offset Test Circuit

The circuit shown in Figure A-1 supports quick op amp

VOST measurements (VOS, AOL, CMRR, PSRR and
VOS/TA). VP sets the op amps VCM. VM sets the
nominal VOUT value. R1 isolates U1s input from VP and
is used to cancel IB induced errors. The two resistors
R3 set an inverting gain of -1 V/V for VM. R2 increases
the noise gain, but does not affect the gains seen by VP
and VM. VDD and VSS are the supply voltages, which
can be varied for PSRR measurements.

R1

Solving for VOST, and assuming that the bias current

errors are negligible, gives:

VDD
U1

VP

The 25 mV used to estimate GN gives VOUT a reasonable output range. For instance, the MCP601s AOL
specification requires VOUT to be 0.1V from the rails;
the GNVOST term will make this 0.05V to 0.15V from the
rails.

VOUT

EQUATION A-3:
V OUT#1 ( 2V P V M )
V OST ---------------------------------------------------GN

R2
VSS
VM
R3

FIGURE A-1:

R3

Offset Test Circuit.

The common mode input voltage and output voltage

are:

V OST
V CM = V P + --------------- I BN R 1
2
V OST
= V P + --------------- ( I B + I OS )R 1
2
V OUT = 2V P V M + V OST G N I BN G N R 1 + I BI R 3

= 2V P V M + V OST G N + I B ( R 3 G N R 1 )
R3 + GN R1
I OS ---------------------------
2
Where:

Note:

2 + R3/R2

VCM contains a VOST/2 term because it is

the average of the two input voltages (one
with VOST and the other without). Usually,
this makes only a small difference.

DS01177A-page 10

EXAMPLE A-1:
VOST 3.8 mV

EQUATION A-1:

GN

Lets use Microchips MCP601 op amp to illustrate this

design (similar to Example 2 on page 6). R3 is reduced
to minimize the impact of IBN and IBI.

Design Selections:
GN

(25 mV)/(3.8 mV)

6.6 V/V 5 V/V

R3

100 k 20.0 k

R2

6.65 k

R1

4.02 k

Impact on VCM and VOUT accuracy:

VCM

VP 1.9 mV

VOUT

2VP VM + VOSTGN 0.01 mV

The error in VCM, divided by CMRR (5.62 kV/V),

produces a 0.3 V error in VOUT. It also reduces the
input common mode voltage range by 2.0 mV, which is
negligible for most purposes. Thus, the estimated VOUT
has errors, dominated by the bias currents, of about
0.04%.

2008 Microchip Technology Inc.

AN1177
A.1.2

MEASUREMENT STRATEGY

Now that we have a circuit, it pays to have a strategy to

measure those points needed. Lets assume the goal is
to double check the MCP601s data sheet specifications at +25C.

TABLE A-1:

MEASUREMENT POINTS

Nominal Bias
Point

Target Parameters
Meas.
No. V
DD VCM VOUT V
OS AOL CMRR PSRR
(V) (V)
(V)

The common mode input voltage and output voltage

are:

EQUATION A-4:
V OST
V CM = V P + ------------ I BN R NEQ
2
V OST
= V P + ------------ ( I B + I OS )R NEQ
2
V OUT = 2V P V M + G N ( V OST I BN R NEQ + I BI R IEQ )
= 2V P V M + G N V OST + I B G N ( R IEQ R NEQ )
R IEQ + R NEQ
+ I OS G N --------------------------------

2
Where:

2.7 1.35 1.35

1.35

0.1

GN

2 + R3/R2

1.35

2.6

RNEQ

-0.3

2.5

=
=

R1, SW4 = short

R1+R4, SW4 = open

3.8

2.5

RIEQ

5.5 2.75 2.75

=
=

R3/GN, SW5 = short

(R3/GN)+R5, SW5 = open

2.75

0.1

2.75

5.4

5.0

A.2.1

CIRCUIT DESIGN

See Section Input Offset Related Specifications

on page 2 for the equations relating these measurements and the specifications.

We now add to the design equations estimates of R4,

R5, C4 and C5. The capacitors are much larger than
most op amps common mode input capacitance (for
stability, noise and speed).

A.2

EQUATION A-5:

Complete Input Offset Test Circuit

The circuit in Figure A-2 functions like Figure A-1, plus

it has R4 and R5 to measure IBN and IBI. SW4 and SW5
short R4 and R5 for all VOST related measurements. C4
and C5 help maintain stability and reduce noise.
SW4
R1
VP
R2
R5

VDD
U1

VOUT

VSS

C5
R3
VM

R3

R4

(25 mV) / (GN max |IBN|)

R5

(25 mV) / (GN max |IBI|)

C4

C5 = 100 pF

The practical way to use this circuit is as follows.

Measure all of the VOST related parameters with SW4
and SW5 shorted; the circuit behaves exactly as
described in A.1 Basic Input Offset Test Circuit.

C4
R4

Select GN, R3, R2 and R1 as before

SW5

FIGURE A-2:
Offset Test Circuit with Bias
Current Capabilities.

To measure IBN and IBI, take three measurements at a

single bias point with different switch selections:

TABLE A-2:
Meas.
No.

Switches
Emphasize
SW1

SW2

short

short

VOST

open

short

VOST and IBNR4

short

open

VOST and IBIR5

3
Note 1:

2008 Microchip Technology Inc.

SWITCH SELECTIONS

The change in VCM caused by R4, in Meas. No.

2, can be substantial.

DS01177A-page 11

AN1177
Subtracting these measurements gives the following
simple results:

EQUATION A-6:
( V OUT#2 V OUT#1 )
I BN = ------------------------------------------------R4
V OUT#3 V OUT#1
I BI = -----------------------------------------R5
R3
V OUT#1 ( 2V P V M )
V OST = --------------------------------------------------- + I BN R 1 I BI -----G
GN
V OUT#1 ( 2V P V M )
--------------------------------------------------GN
( I BN + I BI )
I B = -------------------------2
I OS = I BN I BI
Lets continue Example A-1, which uses the MCP601,
for measurements up to +85C:
VOST 3.8 mV
TA +85C
Additional Design Selections:
=

R5

= (25 mV) / ((5 V/V) (60 pA))

= 83.3 M 20.0 M

GNR4 = GNR5 = 100 M

C4

C5

= 100 pF

Example Output Values:

IBNGNR4

MEASUREMENT STRATEGY

Lets double check the MCP601s data sheet bias

current specifications, for one temperature, at
VDD = 2.7V and 5.5V.

TABLE A-3:

BIAS CURRENT
MEASUREMENT POINTS

Nominal Bias
Switch
Point
Settings
Meas.
Target
No. V
Parameter
DD VCM VOUT SW
4 SW5
(V) (V)
(V)
1

2.7 1.35 1.35 short short

open short

0.10 mV, IBN = 1 pA

6.0 mV, IBN = 60 pA

The 20 M is comprised of two, easy to obtain, 10 M

resistors in series. Using a 18-bit ADC to measure
VOUT should be adequate. Lets continue Example A-2
at +125C by using a different value for R4 and R5:

EXAMPLE A-3:
VOST < 3.8 mV

VOST
IBN

short open

5.5 2.75 2.75 short short

open short

IBN

short open

IBI

See Equation A-6

equations.

EXAMPLE A-2:

R4

A.2.2

A.3

for

the

parameter

IBI
VOST

extraction

Limitations of These Test Circuits

Some of the more important limitations are:

VCM is not accurately controlled (especially for
CMRR)
The common mode input range may be exceeded
when IBNR4 is very large
The VOST resolution is not better than10 V to
20 V
Temperature gradients on the PCB cause thermojunction voltages
VOUT needs to be measured accurately in order to
maintain reasonable accuracy on the extracted
parameters. For instance, with VDD = 5.5V and a
maximum VOSTGN of 0.1V, an ADC at VOUT
would need at least 16 bits in order to resolve
VOST to 0.1%
Measurements can be slower than with other
solutions

TA = +125C
Additional Design Selections:
R4

R5

= (25 mV) / ((5 V/V) (5 nA))

= 1 M

GNR4 = GNR5 = 5 M
C4

C5

= 100 pF

Example Output Values:

IBNGNR4

0.25 mV, IBN = 50 pA

25 mV, IBN = 5 nA

This means that a 16-bit ADC is sufficient for this

temperature.

DS01177A-page 12

2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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2008 Microchip Technology Inc.

DS01177A-page 13

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DS01177A-page 14

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