A versatile low-power Power Line FSK Transceiver

R. Cappellettil, A. Baschirotto2
1 STMicrolelectronics
Via Tolomeo 1 - Cornaredo (MI) - ltalia
2 University of Lecce - Dept. of Innovation Engineering
Via per Arnesano - 73100 Lecce - ltalia

Abstract PLM's is necessary to cover the entire application

A versatile low-power half-duplex FSK transceiver spectrum.
for power line communication network applications is In this paper a new PLM is presented. The proposed
presented. The proposed Power-Line Modem (PLM) device is a half-duplex FSK modem with 8
satisfies the requirement of several protocols for both communication channels. The device allows 4
power-line communications and home automation possible baud rates and 2 possible deviations for each
applications. The device operation is fully controlled channel. Channel, baud rate, and deviation can be
and programmed through an internal 24bit register. It selected via software, properly setting an internal 24bit
operates from a single 9V supply (5V is possible if no register. This can be done also remotely through a
power delivery is required). During transmission, the serial interface.
PLM is able to deliver 1W on 16R, while during The proposed PLM gives significant advantages
reception it dissipates only 3.5mA. The PLM is with respect to competitive solutions in the following
realized in a O.6pm BCD technology. terms:
supported communication protocols: the realized
Introduction device appears to be the only one (up to now) able
Power mains are the most popular and distributed to satisfy the requirements of several protocols like:
communication media in the world. Electrical power is CENELEC EN 50065-1, EHS 1.3 (issued by
distributed at 50Hz or 60Hz, and so higher EHSA-European Home System Automation),
frequencies can be used to exchange data. This CONVERGENCE 0.3 (issued by EHS 1.3), for what
concept is exploited in two popular communication concerns low baud rate devices, and ENEL
systems: DH028/29;
power-line communications: to exchange data increased number of implemented functions
between the utility companies and the power (watchdog, clock output, output current/voltage
consumers. It is useful to remotely monitor and limitation, preamble detection, time-out, band in
control power distribution through intelligent use): this allows also to reduce the requirement for
meters; the counterparts (mainly the microprocessor);
home automation communication: to exchange data reduced number of external components: a
between different electronics devices in the same minimum of only 5 external components is
area. required. This means low cost and small room
For these applications, a number of different space:
communication protocols have been developed and reduced power consumption in Rx-mode: the
standardized: they differ depending on the application proposed device consumes 3.5mA, while it is able
and the system they are designed for. to detect signal in the range 0.5mVrms-2.5Vrms
The key blocks for these power-line communication (i.e. with 74dB dynamic input range);
systems are the Power Line Modems (PLM) which large power delivery in Tx-mode (up to 5Vrms on
allows the different counterparts to communicate. 25R load).
Typical requirements for a PLM are: low-power The power consumption reduction has been
consumption, small number of required external achieved with an extremely careful design both at
counterparts, low cost microprocessor, large number system and at circuit level of the overall PLM. Analog
of implemented functions, compatibility with a number and digital worlds are widely used and the signal is
of communication protocols. Several PLM's [l-31 have converted several times in its processing in order to
already been presented in literature and on the optimize the power consumption. Notice that
market. Each one of them is suited for just one of the alternative solutions with the same dynamic range over
two above communication systems and satisfy few the same bandwidth (=1OOkHz) results in architecture
communication protocols. In this situation, a number of using ZA solutions. These approaches require a large

14-6-1
0-7803-5809-0/00/$10.000 2000 IEEE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE 323
 OSR and so a la!ge sampling frequency and a large can be used when the supply voltage is too low to
power consumption. guarantee proper circuit operation;
low cost application board is needed. A small
Device architecture number of external components is needed: the
Fig. 1 shows the architecture of the proposed PLM, minimum count is two capacitors and the quartz for
while Fig. 2 shows the application board where the the oscillator, one capacitor for the input coupling
proposed PLM is operating with the coupling to the and one for the output coupling, and one capacitor
mains, the counterpart microprocessor, and with a for the regulated supply voltage. In addition, the
switching supply. In order to reduce the number of PLM supplies and external clock (Mclk pin) and
external components needed to realize the external regulated supply voltage which can be
communication node, several auxiliary functions have passed to the microprocessor, avoiding additional
been implemented internally to the PLM, as listed in circuitry (quarz, etc ...) in the application board;
the following: it satisfy a number of protocols and, thus, it covers a
line front-end number of possible applications (power line
linear regulator 5V-1OOmA communication, home automation). This is
sub-threshold oscillator at 16MHz achieved by giving the possibility of programming
zero-crossing comparator four possible baud-rate (600Hz, 1.2kHz, 2.4kH2,
microprocessor oscillator and 4.8kHz), and 2 frequency devation (0.5 and 1).
busy channel detection
power line interface Receiving section
The device allows to operate with 8 channels: 6 of During the reception, the input signal (RAI) is passed
them are reserved for the energy suppliers, 1 for the through a programmable Sallen&Key bandpass
home automation for protocol access and 1 for the filter (with center frequency accorded to the input
other home automation band. channel), it is amplified through a wide dynamic
The proposed PLM gives the following relevant range AGC (0.5mVrms to 2.5Vrms) and then it is
advantages accurately filtered by the programmable
the clock signal is realized from an external quarz Sallen&Key filter for the channel selection.
w=m #AM
and from an internal circuitry operating in
subthreshold region in order to reduce power
consumption. The quarz clock frequency is 16MHz.
In addition, this frequency is used only in a small
part of the circuit, while the major part of it is
operated at lower clock rate in order to reduce
power consumption;
additional functions are implemented in the device
in order to use of a low-performance
microprocessor. For instance a WatchDog
operation (WatchDog time-out is 1.5s) is
implemented; it allows to detect wrong behaviour of
the microprocessor and to reset it; the same signal Fig. 1 - The proposed Power Line Modem

k-i
Fig. 2 - Board schematic

324 14-6-2
 This produces a low out-of-band noise FSK signal connected to the CL pin, as shown in Fig. 3 which
which is then multiplied by a local oscillator to obtain corresponds to the rule:
the signal component at the intermediate frequency. 887.5
This signal is finally demodulated and supplied to the RCL [Q] =
pin RxD. The relative clock is externally available at the fi . lrms [A] + 0.007
CLR/T pin and it can be used for synchronize the 350
readung the data at pin RxB. Digital signal CD/PD
checks the presence of the signal energy in the 300
selected channel. This information allows to know if 250
there is energy in the band and if there is a modulation
at the selected baud-rate. It is finally available (BU pin) ;200
the knowledge of the presence in the selected band
of signal larger than 80dBpV. This information is used - 150
in home automation application, in order to allow signal
transmission only if there is not signal energy larger
1 -
100
than 80dBpV on the line. To reduce power
1.5 2 2.5 3 3.5 4
consumption, during reception the transmitter section RCL [kOhm]
is turned off. Fig. 3 - Output current vs. RCL
Transmitting section
During the transmission, the input signal (TxD) can Both the voltage and current loop act by means of
be referred to the signal CLR/T which gives a the ALC. Two voltage thresholds are used for each
synchronization to the baud-rate frequency selected loop inside which the loop is active. The two loops
in the control register. Signal TxD is supplied to the have different thresholds and the current loop is
FSK modulator which generates two tones centered dominant. This control loop system does not reduce
at the selected channel with deviation selected by the the linearity performance of the device.
data in the control register. The modulated signal is Transmission can be syncronized with the mains
filtered by a programmable gm-C bandpass filter (this zero-cossing. Zero-crossing is also available in pin
reduces harmonics and, so, electromagnetics noise). Zcout to turn on and off electrical devices, to avoid
The resulting signal is supplied to the power stage overload voltage on the switches.
which drives through the pin ATOP1 and ATOP2 the The output signal can be at large power or at low
line driver. The integrated power line interface is power. The full device is powered with a 9V supply.
composed of a Class AB Double Ended (Bridge) However the only section operating at 9V is the power
stage, which reduces even harmonics. Peak-to-peak line interface. An internal voltage regulator converts
output voltage is controlled through the Automatic the 9V to 5V (100mA) to supply the rest of the circuit
Level Control (ALC) by means of RVLI, and RVL2 and, eventually, also the microprocessor. Thus in the
resistors. This allows to maintains constant the output applications where an external line driver is used, the
signal amplitude despite of the power line impedance proposed PLM can be powered with only 5V supply,
variations. There is also a current control loop which halving the power consumption.
limits the peak current delivered from the ATOP1 and An additional operational amplifier is available for the
ATOP2 pins. The output current limit (up to implementation with the eventual external
500mApeak) is set by means of a resistor (RCL) components of extra analog functions.

,f + &$!!pis,"r +"
" J
......
_. .. RxD
....

Fig. 4 - The analog/digital FSK demodulator

from the IF filter and is firstly squared by a comparator.

Power minimization example: the This digital-amplitude signal is supplied to the
FSK demodulator correlator, which is a digital block where the delay T is
As an example of the power optimization the FSK realized with an accurate delay chain. In this case the
demodulator is analyzed. The scheme of this section highest operating frequency (16MHz) in the system is
is shown in Fig. 4. The analog input signal is coming used in order to achieve an accurate delay time. A

14-6-3 325
trade-off is present between the choice of this performance in both transmission and reception
sampling frequency and the image frequency operation.
rejection relative to the operation of the mixer
preceeding the IF filter. The digital signal at the output Reference
of the correlator is then supplied to an analog filtering [ l ] J. Boxho, G. Evens, B. Goffart, D. Macq, "An analog
section. This is composed by an anti-aliasing filter and front end for multi standard power line carrier
by a switched-capacitor filter which guarantees modem" , Power Line Communication World
accurate filtering to strong reject the carrier signal Congress, May, 19-20, 1999, Brussels
(Q40kHz) and amplify the in-band signal. Different [2] C. Boscand, "An integrated modem for power line
communication MTC-30585", IIR Power Line
signal passbands are possible (depending on the CommunicationWorld Congress, May 1999
adopted communication standard) and so a [3] "ST7537HSl - Home automation modem",
programmable cut-off frequency has been http://www.st.com
implemented. Three cascaded blocks operating at
1MHz have been used. A first sample&hold stage,
which allows to avoid continuous-time path to the
output. A notch filter rejecting the carrier at 40kHz and
an accurate low-pass filter whose dc-gain and quality
factor areconstant, while the pole frequency can be
digitally programmed in order to select the desired cut-
off frequency. Possible cut-off frequencies are
1.2kHz, 2.4kHz, 4.8kHz. The SC filter frequency
responses are shown in Fig. 5. Carefull design allows
to reduce the power consumption of the entire SC
section (including AAF) to be less than 100pA.
The image frequency is also rejected by the transfer
function of this SC filter. The output signal is then
squared and supplied to the output after a digital low-
pass filtering which rejects the eventual spurious
spikes.
30
Fig. 6 - Chip photagraph
20

10 General aspects
go Technolo
-a-10
Poxer supply

-e
U
3 -20
-
.-
-30
Power line driver

Maximum clock rate 16MHz

a -40
Communication channels 8
-50 Frequency de viation 2
-60
102 103 104 105 106 I Transmitter I I
Frequency [Hz]
Fig. 5 - Programmable SC filter frequency response Maximum output power 7w
Maximum output current 5OOmApeak
Experimental results THD (RL=ZkR, 2kHz,5Vrms) -60 d5
The device has been realized in a 0.6pm BCD ALC Dynamic Range 30dB
technology, which allows to realize in the same die ALC step I 0.93 d5
analog, digital and power devices. Fig. 6 shows the Receiver
chip photograph. The device is powered with a single
I
9V supply and consumes 3.5mA in RX-mode (this is
almost a factor of ten lower than competitive products). I Current consumption
Input sensitivity I
I
3.5mA
1mVrm.s
In TX-mode, the device is able to deliver 1W with a
5Vrms amplitude (output current and voltage are also
undercontrol). A single 5V supply can be used when
I Maximum input signal
Input impedance I
Table I - PLM Performance summary
2.5vrms
750kR

no power output is needed. Table I reports the PLM

326 14-6-4