156 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO.

3, AUGUST 1979

A McMurray Inverter Controller

FREDERICK RODRIGUES AND THOMAS H. BARTON, FELLOW, IEEE

Abstract-The specifications of a highly flexible controller for a

three-phase McMurray inverter are defined and the construction of a
suitable controller is described. The controller is capable of operation
in either the six step or pulsewidth modulation mode and incorporates
safe start-up and shut-down procedures. The operation of the controller
is illustrated by a series of inverter and controller oscillograms.

INTRODUCTION
A
T HE MCMURRAY INVERTER, because of its excellent
square waveform, its high efficiency, and capability of
high-frequency operation is used as the three-phase power
-,
~~~0
LY Cy T
source for the experimental investigation of variable-speed, TA2y 02y T2y
variable-frequency ac drives in the authors' laboratory. The UU
T
inverter controller described here provides an interface be-
tween the inverter and other equipment modules such as
TAI8 DIn Tin
pulsewidth modulation (PWM) controllers and drive con-
trollers. As such it accepts a standardized input pulse train T+ B
LB CB
and generates firing pulses for the inverter main and auxiliary
TA2n D2B TZn
thyristors. It also ensures the safe start-up and shut-down of
the inverter, is self contained with its own power supply, and Fig. 1. A three-phase McMurray inverter. The three phases are identi-
is shielded against the various and intense noise sources of a fied as red R, yellow Y, and blue B.
power electronics laboratory.
As befits a controller designed for use in an experimental capacitor charges as shown. To turn off Ti, the auxiliary
laboratory, major design aims were flexibility, simplicity of thyristor TA1 is fired, thus permitting C to discharge. The
operation, and reliability. combination of L and C is lightly damped so that the dis-
THE MCMURRAY INVERTER
charge of C is essentially accomplished by a half sinusoid of
current. The first portion of this current passes in the reverse
The McMurray inverter [11 is widely known and used and direction through TI, rapidly driving its current to zero. The
only the briefest description, sufficient to define the controller excess discharge current flows through the inverse parallel
specification, will be given here. A three-phase inverter is connected feedback diode Dl.
shown in Fig. 1, where the components of a phase are identi- This situation, TI carrying zero current and reverse biased
fied by a final letter, R for the red phase, Y for the yellow by the forward drop of Dl, persists for a few tens of micro-
phase, and B for the blue phase. Each phase comprises a pair seconds, sufficient for TI to recover its voltage blocking capa-
of main thyristors T1 and 12, a pair of feedback diodes DI bility. The other main thyristor, P2, may then be triggered,
and D2, a pair of auxiliary thyristors TA 1 and TA2, a com- thus connecting the output to the dc negative bus.
mutating inductor L, and a commutating capacitor C. When The operation of the commutation circuit is such that the
T1 is triggered, the output is connected to the positive dc bus. capacitor voltage reverses to a value somewhat higher than the
When T2 is triggered, the output is connected to the negative dc supply voltage so that it is appropriately charged for the
dc bus. Thus the output is a square wave whose peak to peak next commutation which will tum off T2 and turn on T1.
amplitude is VDC. The three units are operated sequentialy A McMurray inverter controller must, therefore, produce an
so as to give outputs mutually displaced by 120, thus pro- auxiliary thyristor pulse to initiate commutation, followed,
ducing a three-phase square-wave output. with an appropriately adjusted delay, by a main thyristor
We will commence the analysis of operation by assuming the pulse. A three-phase unit, as shown in Fig. 1, requires six
main thyristor T1 to be conducting, and the commutating auxiliary and six main pulses appropriately spaced in time.
The matter is somewhat more complicated when the load
Manuscript received November 27, 1978; revised February 24, 1979. draws a lagging current. The load current reversal lags the
F. Rodrigues was with the University of Calgary, Calgary, Alta, voltage reversal so that the incoming main thyristor T2 only
Canada. He is now with the Ballarat College of Advanced Education,
Victoria, Australia. carries current momentarily, the load current almost im-
T. H. Barton is with the Faculty of Engineering, The University of mediately transferring to its feedback diode D2. The main
Calgary, Calgary, Alta., Canada T2N 1N4. thyristor must be ready to carry the current at some later

0018-9421/79/0800-0156$00.75 1979 IEEE

RODRIGUES AND BARTON: McMURRAY INVERTER CONTROLLER 157

TAI -
1I h I IMPLEMENTATION
3~~~L The controller accomplishes the tasks described above and
T2
to- "tb
r-I -I
in addition has been well screened from the high-power
pulse noise found in a power electronics laboratory. The
TA2 controller design, construction, and testing has been described
TI tL L Ih elsewhere [2] in detail which would be inappropriate here in
view of the many different ways in which the various tasks can
Fig. 2. The timing relationships between the gate pulses of a McMurray be accomplished. Here we outline our own solutions so as to
inverter. The main and auxiliary thyristor pulses for one phase are
shown. draw attention to the task and indicate a possible approach to
its accomplishment. To this end a functional block diagram of
instant in the cycle when it reverses. This instant is indeter- the controller is shown in Fig. 3.
minate, depending on the characteristics of the load and the
frequency and, for maximum flexibility, we have opted to Inputs
deliver a second trigger pulse to the main thyristor at the Input signals to our controller consist of pulse trains, each
appropriate instant. pulse indicating that the inverter should switch from one dc
bus to the other. The controller is required to operate single-
Thyristor Trigger Pulses phase, three-phase, and pulsewidth-modulated inverters. To
The temporal relationships between the various trigger pulses accomplish this there are two inputs to the INPUT unit of
are illustrated in Fig. 2. Pulse 1 triggers TA 1 and initiates Fig. 3. The first of these is a uniform pulse stream at six times
turnoff of Ti. After a brief delay ta sufficient for recovery of the inverter frequency, and the second comprises three sepa-
Tl, pulse 2 is applied to T2 to effect the transfer from the rate pulsewidth-modulated streams which are derived from a
positive to the negative bus and to ensure that the capacitor separate controller [3].
voltage is always built up to a value independent of the load The first pulse stream is passed through a divide-by-six ring
current. After a further delay tb depending on the load counter in the INPUT unit to produce six output pulse trains,
characteristics, pulse 3 is applied to T2 so that it may pick up each of one-sixth frequency and equispaced at 600 intervals.
the load current. Corresponding pulses, but delayed by 1800, After shaping, amplification, and isolation by the AUXILIARY
GATE PULSE PROCESSOR and the AUXILIARY GATE PULSE
are sent to TA2 and Ti.
If the load conditions are well defined, unfortunately not AMPLIFIER, each of these pulse trains serves as the trigger
the case in our situation, it is generally simpler to send a high- pulses for one of the six auxiliary thyristors.
frequency train of trigger pulses to a main thyristor so as to The PWM input comprises six pulse streams, two for each
span the gap between pulses 2 and 3 under all conditions.
phase. One of each pair indicates a switch from the positive
For a three-phase inverter, similar trigger pulses are sent to to the negative dc bus and the other indicates the reverse
the other two phases with the appropriate 1200 or 2400 delay. process. The six inputs bypass the ring counter and go directly
A single input pulse stream, at six times the inverter output to the six input channels of the AUXILIARY GATE PULSE
PROCESSOR.
frequency, is sufficient to define the timing relationships.
For an inverter employing PWM, a separate PWM timing
pulse stream is required for each phase. Generation of the Main Thyristor Pulses
The arrival of a pulse at a channel of the auxiliary gate pulse
Starting processor starts a clock in the corresponding channel of the
MAIN GATE PULSE PROCESSOR. After a brief delay, the time
For a positive sequence system, the main thyristors are ta on Fig. 2 which is preset within the limits 20-250 gs, a
tumed off in the order pulse is delivered to the MAIN GATE PULSE AMPLIFIER where,
T1R, T2B, TI Y, T2R, T1B, T2 Y, T1R, etc. after amplification and isolation, it triggers the appropriate
main thyristor.
The inverter can be started at any point in this sequence. As-
suming that we commence by triggering T1R, T2B, and TI Y Follow-Up Thiggering of th e Main Thyristors
at 600 intervals, the commutating capacitors must be initially Because of our desire for maximum flexibility we preferred
charged, as follows: to use follow-up triggering of the main thyristors rather
CR positively than continuous triggering. The conditions under which a
CY positively follow-up pulse is delivered are determined by the CURRENT
CB negatively. ZERO DETECTOR and the SENSE LOGIC unit.
The CURRENT ZERO DETECTOR employs optoisolators to
Shut-Down detect the voltage across each main thyristor. If this is greater
The inverter cannot be switched off by simply removing all than +10 v the thyristor is taken to be forward biased and
firing pulses, since those thyristors which are conducting will nonconducting and a logic "1'" signal is passed to the SENSE
continue to conduct; they must be commutated off. This is LOGIC unit. This unit also receives signals from the AUXILIARY
accomplished by continuing firing of the auxiliary thyristors and MAIN GATE PROCESSORS which it interprets to indicate
for a few cycles after blocking the main thyristors. whether the main thyristor in question is in a portion of the
 158 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 3, AUGUST 1979

TO GATES OF
AUXILIARY THYRISTORS

TFREE-PHASE SIGNALS

CCONrROL AND INPUF/OUTRTL

SIGNALS
Fig. 3. The functional block diagram of the controller.

2*
2

Fig. 5. Inverter output to an active load showing several transfers of

current between the main thyristor and its feedback diode. Trace
1, 50 V/div, is the load voltage and trace 2, s A/div is the load cux-
rent. The horizontal scale is 100 ,us/div.

derived follow-up trigger pulses. References to the current

trace shows negligible discontinuity as the current passes
through zero.
5 Since the current in an inductive load may be rising quite
slowly through zero, there is a possibility that the thyristor
may not at first latch on. Further trigger pulses are generated
6
at 20-,s intervals until conduction is firmly established.
Under some circumstances, it is possible for the current to
Fig. 4. The inverter output voltage, trace I, output current, trace 2, and the transfer several times between the thyristor and its feedback
corresponding SENSE LOGIC signals, traces 3, 4, 5, and 6. The scales per
diode during the conducting half cycle. The follow-up system
centimeter of oscilloscope graticute
takes care of this situation, as illustrated by Fig. 5, where the
are:

output voltage, 1 50 V/div

output current, 2 5 A/ div current, after a brief period through the diode, transfers to
logic signals, 3, 4, 5,
horizontal
and 6 5
100
V/div the thyristor, then goes back to the diode, and then ends the
uis/div.
half cycle by flowing once more through the thyristor.
cycle when it may conduct or when it must block. If conduc- Pulse Amplification and Isolation
tion is permidssible, a trigger pulse is delivered to the thyristor Firing pulses of about 25-ps width, peak amplitude 3 A are
via the main gate pulse processor and amplifier. This feature generated and delivered to the thyristor gates by blocking
of the controller is illustrated by Fig. 4 which shows, in traces oscillators. A blocking oscillator feedback transformer has one
1 and 2, the output voltage and current of a single-phase isolated output winding feeding the thyristor gate. Isolation is
inverter supplying an inductive load. High levels in traces 3 further improved by coupling the trigger signal into the block-
and 4 show the periods when the main thyristors are non- ing oscillator by optoisolators, by using a separate power
conducting and forward biased. Traces 5 and 6 show the supply for the blocking oscillators, and by well-shielding the
RODRIGUES AND BARTON: McMURRAY INVERTER CONTROLLER 159

2 b

Fig. 6. The initial charging current, trace 1, 20 A/div, and the inter- Fig. 7. The starting sequence. Trace I is the ENABLE signal, trace 2 is the
lock signal, trace 2, 5 V/div. The horizontal scale is 10 ms/div. output current, trace 3 is the trigger pulse to TA I R and trace 4 is the
trigger pulse to TA2R. The scales percentimeterofoscilloscopegraticule
output stages from the low-level logic of the remainder of the are:
trace 1. 3. and 4 5 V/div
apparatus. trace 2 10 A/div
horizontal 0.5 ms/div.
Capacitor Charging
The CONTROL unit has three inputs activated by the CHARGE,
START, and STOP units. The START signal is inactive until the
commutating capacitors have been correctly charged as de-
scribed earlier.
On pressing the CHARGE button, T1R and TA2R are triggered 2
simultaneously. This charges commutation capacity CR pos-
itively. Thirty milliseconds later TI Y and TA2Y are triggered
to charge CY positively and, after a further 30-ms delay, T2B 3
and TA 1B are triggered to charge CB negatively.
The sequential charging of the three capacitors has two use-
ful effects. First, only one load terminal is connected to the 4
dc supply at a time so that, even though the circuit breaker
between the load and the inverter may be closed, no load
current can flow during the charging process.
Secondly, the drain on the dc supply is reduced. The peak Fig. 8. The shut-down process. Trace I is the DISABLE signal, a low level
blocks trigger pulses to the main thyristor. Trace 2 is the ENABLE signal, a
charging current per phase is of the order of two to four times high level is required to make the START pushbutton operative. Trace 3 is
the rated current so that simultaneous charging would draw the load current and trace 4 is the trigger pulses to the auxiliary thyristor
about six or more times the rated current. TA I R. The scales per centimeter of oscilloscope graticule are:
traces 1, 2, and 4 5 V/div
The upper trace of Fig. 6 shows the supply current during trace 3 5 A/div
the charging process. The three charging pulses are well horizontal 0.5 ms/div.
separated, giving ample time for thyristor recovery before the
next pulse, but still completing the process in well under one with a trigger pulse to TA2R, trace 4. Since the commutating
tenth of a second. The lower trace shows the ENABLE signal capacitor CR is positively charged, nothing happens and no
which is delivered to the START unit once charging is completed. load current flows as shown by trace 2.
The upper traces of Fig. 6 show some negative current flow. Shortly after the trigger pulse to TA2R a trigger pulse is sent
This is because a modified McMurray inverter was employed to TlR as described earlier under the heading, "Generation of
[4]. It has a voltage clamp on the commutation capacitors the main thyristor pulses." The follow-up trigger feature then
and the negative current is associated with the operation of fires T2Y to establish a conducting path between the dc sup-
this clamp. ply and the load. T1R picks up current as shown in trace 2
and, in the normal sequence of events, is commutated by a
Starting trigger pulse to TAIR, trace 3.
The ENABLE signal generated by the CHARGE unit at the
end of the charging process activates the START unit. Pressing Shut-Down
the START button can then initiate firing pulses, in the correct Pressing the STOP pushbutton generates a DISABLE signal
sequence, to the main and auxiliary thyristors of the inverter. which inhibits the further production of main thyristor trigger
Fig. 7 illustrates this process with respect to the red phase. pulses. Auxiliary thyristor trigger pulses are allowed for three
The upper trace is the ENABLE signal. Pressing the START more cycles, sufficient to ensure that all the main thyristors
button after receipt of this starts the inverter firing sequence have been commutated off.
160 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 3, AUGUST 1979

further triggering and requires the complete start-up process

before conduction can be reestablished.
The chances of success are maximnized by detecting the cur-
rent in each output line and, when it becomes excessive, either
positively or negatively, instantaneously 1) blocking all main
thyristors, 2) commutating the conducting thyristors.
We have not incorporated this feature in our controller and,
for protection, we rely entirely on fast acting fuses in the dc
2 input to ac output from the inverter.
CONCLUSIONS
The requirements which must be fulfilled by a highly flex-
ible controller for a McMurray inverter have been defined. An
Fig. 9. The output current, trace 1, 5 A/div, and output voltage, trace implementation based almost entirely on digital logic circuits
2, 50 V/div, of one phase of the inverter. The horizontal scale is 0.5 has been briefly described.
ms/div. The success of the controller is illustrated by Figs. 9 and 10.
Fig. 9 shows the phase voltage and current when the inverter
is supplying a three-phase inductive load. Fig. 10 shows the
corresponding quantities when the inverter is operating in the
PWM mode with a frequency ratio of 9:1 and a modulation
index of 0.8.
The circuit implementation which we have employed is de-
scribed in detail in [2]. However, these are not put forward
in any sense as the best methods; there are no doubt many
alternative circuit solutions to the control task. As an ex-
2
ample, we employed separate analog timers for the various
delays. We now feel that this could have been better accom-
plished using a central digital clock and counters.
It is possible that this timing function could be accomplished
in a more flexible manner using a microprocessor and software.
Fig. 10. The inverter output with pulsewidth modulation. Trace 1 is REFERENCES
the current, 5 A/div, and trace 2 is the voltage, 5 A/div. The horizon-
tal scale is 2 ms/div. [1] W. McMurray, "SCR inverter commutated by an auxiliary im-
pulse," IEEE Trans. Commun. Electron., vol. 83, pp. 824-829,
1964.
The action of this unit is illustrated by Fig. 8. Trace 1 is the [2] F. E. Rodrigues, "A McMurray inverter controller," M.Sc. thesis,
University of Calgary, Canada, 1978.
stop signal. Trace 4 shows pulses continuing to the auxiliary [3] T. L. Grant and T. H. Barton, "A highly flexible controller for
thyristor TAIR during the period of the disable signal. Trace a pulse width modulated inverter," in IEEE-IAS Conf: Rec., pp.
3 shows the decay of load current. Trace 2 shows the ENABLE 486-492, Oct. 1978.
[4] L. J. Penkowski and K. E. Pruzinsky, "Fundamentals of a pulse
signal, produced by the CHARGE unit, which goes LOW shortly width modulated power circuit," IEEE Trans. Ind. Appl., pp. 584-
before the end of the disable period. This effectively inhibits 592, Sept./Oct. 1972.