®

TOP221-227
®
TOPSwitch-II Family
Three-terminal Off-line PWM Switch
Product Highlights
• Lowest cost, lowest component count switcher solution AC
• Cost competitive with linears above 5W IN
• Very low AC/DC losses – up to 90% efficiency
• Built-in Auto-restart and Current limiting
• Latching Thermal shutdown for system level protection
• Implements Flyback, Forward, Boost or Buck topology D
• Works with primary or opto feedback CONTROL
C
• Stable in discontinuous or continuous conduction mode TOPSwitch
• Source connected tab for low EMI
S
• Circuit simplicity and Design Tools reduce time to market
PI-1951-091996

Description Figure 1. Typical Flyback Application.

The second generation TOPSwitch-II family is more cost easier. The standard 8L PDIP package option reduces cost in
effective and provides several enhancements over the first lower power, high efficiency applications. The internal lead
generation TOPSwitch family. The TOPSwitch-II family extends frame of this package uses six of its pins to transfer heat from
the power range from 100W to 150W for 100/115/230 VAC the chip directly to the board, eliminating the cost of a heat sink.
input and from 50W to 90W for 85-265 VAC universal input. TOPSwitch incorporates all functions necessary for a switched
This brings TOPSwitch technology advantages to many new mode control system into a three terminal monolithic IC: power
applications, i.e. TV, Monitor, Audio amplifiers, etc. Many MOSFET, PWM controller, high voltage start up circuit, loop
significant circuit enhancements that reduce the sensitivity to compensation and fault protection circuitry.
board layout and line transients now make the design even

OUTPUT POWER TABLE

TO-220 (Y) Package1 8L PDIP (P) or 8L SMD (G) Package2
PART Single Voltage Input 3 Wide Range Input PART Single Voltage. Input 3 Wide Range Input
100/115/230 VAC ±15% 85 to 265 VAC 100/115/230 VAC ±15% 85 to 265 VAC
ORDER ORDER
4,6
NUMBER P MAX
PMAX4,6 NUMBER PMAX
5,6
PMAX5,6
TOP221Y 12 W 7W TOP221P or TOP221G 9W 6W
TOP222Y 25 W 15 W TOP222P or TOP222G 15 W 10 W
TOP223Y 50 W 30 W TOP223P or TOP223G 25 W 15 W
TOP224Y 75 W 45 W TOP224P or TOP224G 30 W 20 W
TOP225Y 100 W 60 W
TOP226Y 125 W 75 W
TOP227Y 150 W 90 W
Notes: 1. Package outline: TO-220/3 2. Package Outline: DIP-8 or SMD-8 3. 100/115 VAC with doubler input 4. Assumes appropriate
heat sinking to keep the maximum TOPSwitch junction temperature below 100 °C. 5. Soldered to 1 sq. in.( 6.45 cm2), 2 oz. copper clad
(610 gm/m2) 6. PMAX is the maximum practical continuous power output level for conditions shown. The continuous power capability
in a given application depends on thermal environment, transformer design, efficiency required, minimum specified input voltage, input
storage capacitance, etc. 7. Refer to key application considerations section when using TOPSwitch-II in an existing TOPSwitch design.
July 2001
 TOP221-227

VC
CONTROL 0
DRAIN
ZC INTERNAL
1 SUPPLY
SHUTDOWN/
SHUNT REGULATOR/ AUTO-RESTART
ERROR AMPLIFIER
+
- ÷8
5.7 V
-
4.7 V
+ 5.7 V

- VI
LIMIT
IFB THERMAL S Q
SHUTDOWN
POWER-UP R Q CONTROLLED
RESET TURN-ON
GATE
DRIVER
OSCILLATOR

DMAX

CLOCK

SAW - S Q
LEADING
+ R Q EDGE
BLANKING
PWM
COMPARATOR
MINIMUM
ON-TIME
DELAY
RE

SOURCE

PI-1935-091696

Figure 2. Functional Block Diagram.

Pin Functional Description

Tab Internally
DRAIN Pin: Connected to SOURCE Pin
Output MOSFET drain connection. Provides internal bias
current during start-up operation via an internal switched high-
voltage current source. Internal current sense point. DRAIN
SOURCE
CONTROL Pin: CONTROL
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal Y Package (TO-220/3)
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor. SOURCE 1 8 SOURCE (HV RTN)

SOURCE Pin: SOURCE 2 7 SOURCE (HV RTN)

Y package – Output MOSFET source connection for high
SOURCE 3 6 SOURCE (HV RTN)
voltage power return. Primary side circuit
common and reference point.
CONTROL 4 5 DRAIN

P and G package – Primary side control circuit common and

P Package (DIP-8)
reference point.
G Package (SMD-8)
PI-2084-040401

SOURCE (HV RTN) Pin: (P and G package only)

Output MOSFET source connection for high voltage power return. Figure 3. Pin Configuration.

D
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 TOP221-227

TOPSwitch-II Family Functional Description

TOPSwitch is a self biased and protected linear control current-
Auto-restart
to-duty cycle converter with an open drain output. High
IB
efficiency is achieved through the use of CMOS and integration DMAX
of the maximum number of functions possible. CMOS process Slope = PWM Gain

Duty Cycle (%)

significantly reduces bias currents as compared to bipolar or
discrete solutions. Integration eliminates external power
resistors used for current sensing and/or supplying initial start-
up bias current.

During normal operation, the duty cycle of the internal output DMIN
MOSFET decreases linearly with increasing CONTROL pin
ICD1 2.0 6.0
current as shown in Figure 4. To implement all the required IC (mA)
control, bias, and protection functions, the DRAIN and PI-2040-050197

CONTROL pins each perform several functions as described Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.
below. Refer to Figure 2 for a block diagram and to Figure 6 for
timing and voltage waveforms of the TOPSwitch integrated
circuit.

IC
Charging CT
5.7 V
4.7 V
VC
0

Off
VIN
DRAIN

0
Switching
(a)
ICD2
IC ICD1 Discharging CT
Charging CT Discharging CT
5.7 V
4.7 V
VC
8 Cycles
0
95%
5%

Off Off Off

VIN
DRAIN

0
Switching Switching
(b)
CT is the total external capacitance
connected to the CONTROL pin
PI-1956-092496

Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.

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 TOP221-227

TOPSwitch-II Family Functional Description (cont.)

Control Voltage Supply Oscillator
CONTROL pin voltage VC is the supply or bias voltage for the The internal oscillator linearly charges and discharges the
controller and driver circuitry. An external bypass capacitor internal capacitance between two voltage levels to create a
closely connected between the CONTROL and SOURCE pins sawtooth waveform for the pulse width modulator. The oscillator
is required to supply the gate drive current. The total amount sets the pulse width modulator/current limit latch at the beginning
of capacitance connected to this pin (CT) also sets the auto- of each cycle. The nominal frequency of 100 kHz was chosen
restart timing as well as control loop compensation. VC is to minimize EMI and maximize efficiency in power supply
regulated in either of two modes of operation. Hysteretic applications. Trimming of the current reference improves the
regulation is used for initial start-up and overload operation. frequency accuracy.
Shunt regulation is used to separate the duty cycle error signal
from the control circuit supply current. During start-up, Pulse Width Modulator
CONTROL pin current is supplied from a high-voltage switched The pulse width modulator implements a voltage-mode control
current source connected internally between the DRAIN and loop by driving the output MOSFET with a duty cycle inversely
CONTROL pins. The current source provides sufficient current proportional to the current into the CONTROL pin which
to supply the control circuitry as well as charge the total generates a voltage error signal across RE. The error signal
external capacitance (CT). across RE is filtered by an RC network with a typical corner
frequency of 7 kHz to reduce the effect of switching noise. The
The first time VC reaches the upper threshold, the high-voltage filtered error signal is compared with the internal oscillator
current source is turned off and the PWM modulator and output sawtooth waveform to generate the duty cycle waveform. As
transistor are activated, as shown in Figure 5(a). During normal the control current increases, the duty cycle decreases. A clock
operation (when the output voltage is regulated) feedback signal from the oscillator sets a latch which turns on the output
control current supplies the VC supply current. The shunt MOSFET. The pulse width modulator resets the latch, turning
regulator keeps VC at typically 5.7 V by shunting CONTROL off the output MOSFET. The maximum duty cycle is set by the
pin feedback current exceeding the required DC supply current symmetry of the internal oscillator. The modulator has a
through the PWM error signal sense resistor RE. The low minimum ON-time to keep the current consumption of the
dynamic impedance of this pin (ZC) sets the gain of the error TOPSwitch independent of the error signal. Note that a minimum
amplifier when used in a primary feedback configuration. The current must be driven into the CONTROL pin before the duty
dynamic impedance of the CONTROL pin together with the cycle begins to change.
external resistance and capacitance determines the control loop
compensation of the power system. Gate Driver
The gate driver is designed to turn the output MOSFET on at a
If the CONTROL pin total external capacitance (CT) should controlled rate to minimize common-mode EMI. The gate drive
discharge to the lower threshold, the output MOSFET is turned current is trimmed for improved accuracy.
off and the control circuit is placed in a low-current standby
mode. The high-voltage current source turns on and charges the Error Amplifier
external capacitance again. Charging current is shown with a The shunt regulator can also perform the function of an error
negative polarity and discharging current is shown with a amplifier in primary feedback applications. The shunt regulator
positive polarity in Figure 6. The hysteretic auto-restart voltage is accurately derived from the temperature compensated
comparator keeps VC within a window of typically 4.7 to 5.7 V bandgap reference. The gain of the error amplifier is set by the
by turning the high-voltage current source on and off as shown CONTROL pin dynamic impedance. The CONTROL pin
in Figure 5(b). The auto-restart circuit has a divide-by-8 clamps external circuit signals to the VC voltage level. The
counter which prevents the output MOSFET from turning on CONTROL pin current in excess of the supply current is
again until eight discharge-charge cycles have elapsed. The separated by the shunt regulator and flows through RE as a
counter effectively limits TOPSwitch power dissipation by voltage error signal.
reducing the auto-restart duty cycle to typically 5%. Auto-
restart continues to cycle until output voltage regulation is Cycle-By-Cycle Current Limit
again achieved. The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
Bandgap Reference limit comparator compares the output MOSFET ON-state drain-
All critical TOPSwitch internal voltages are derived from a source voltage, VDS(ON) with a threshold voltage. High drain
temperature-compensated bandgap reference. This reference current causes VDS(ON) to exceed the threshold voltage and turns
is also used to generate a temperature-compensated current the output MOSFET off until the start of the next clock cycle.
source which is trimmed to accurately set the oscillator frequency The current limit comparator threshold voltage is temperature
and MOSFET gate drive current.
D
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 TOP221-227

VIN

VIN
DRAIN
0

VOUT
0

IOUT
0

1 2 8 1 2 8 1
• • • • • •
VC VC(reset)
0

1 2 8 1 2 8 1

IC 0 • • • • • •

1 2 1 3 1

PI-2030-042397

Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, and (3) Power Down Reset.

compensated to minimize variation of the effective peak current becomes regulated, VC regulation returns to shunt mode, and
limit due to temperature related changes in output MOSFET normal operation of the power supply resumes.
RDS(ON).
Overtemperature Protection
The leading edge blanking circuit inhibits the current limit Temperature protection is provided by a precision analog
comparator for a short time after the output MOSFET is turned circuit that turns the output MOSFET off when the junction
on. The leading edge blanking time has been set so that current temperature exceeds the thermal shutdown temperature
spikes caused by primary-side capacitances and secondary-side (typically 135 °C). Activating the power-up reset circuit by
rectifier reverse recovery time will not cause premature removing and restoring input power or momentarily pulling the
termination of the switching pulse. CONTROL pin below the power-up reset threshold resets the
latch and allows TOPSwitch to resume normal power supply
The current limit can be lower for a short period after the leading operation. VC is regulated in hysteretic mode and a 4.7 V to
edge blanking time as shown in Figure 12. This is due to 5.7 V (typical) sawtooth waveform is present on the CONTROL
dynamic characteristics of the MOSFET. To avoid triggering pin when the power supply is latched off.
the current limit in normal operation, the drain current waveform
should stay within the envelope shown. High-voltage Bias Current Source
This current source biases TOPSwitch from the DRAIN pin and
Shutdown/Auto-restart charges the CONTROL pin external capacitance (CT) during
To minimize TOPSwitch power dissipation, the shutdown/ start-up or hysteretic operation. Hysteretic operation occurs
auto-restart circuit turns the power supply on and off at an auto- during auto-restart and overtemperature latched shutdown.
restart duty cycle of typically 5% if an out of regulation The current source is switched on and off with an effective duty
condition persists. Loss of regulation interrupts the external cycle of approximately 35%. This duty cycle is determined by
current into the CONTROL pin. VC regulation changes from the ratio of CONTROL pin charge (IC) and discharge currents
shunt mode to the hysteretic auto-restart mode described above. (ICD1 and ICD2). This current source is turned off during normal
When the fault condition is removed, the power supply output operation when the output MOSFET is switching.

D
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 TOP221-227

D2 L1
UF5401 3.3 µH
+5 V
C2 C3
+ 330 µF 100 µF
R3 C1 10 V VR1 10 V
47 kΩ 2.2 nF RTN
1 kV

D1
UF4005 R2
100 Ω
D3
1N4148 R1
Wide-Range
DC Input T1 10 Ω

U1
+
D
C4
TOP221P 100 µF
TOPSwitch-II
CONTROL 16 V
C
U2 12 V Non-Isolated
PC817A
S
C5
47 µF
- 10 V -

PI-2115-040401

Figure 7. Schematic Diagram of a 4 W TOPSwitch-II Standby Power Supply using an 8 lead PDIP.

Application Examples
Following are just two of the many possible TOPSwitch vary from 100 V to 380 V DC which corresponds to the full
implementations. Refer to the Data Book and Design Guide universal AC input range. The TOP221 is packaged in an 8 pin
for additional examples. power DIP package.

4 W Standby Supply using 8 Lead PDIP The output voltage (5 V) is directly sensed by the Zener diode
(VR1) and the optocoupler (U2). The output voltage is determined
Figure 7 shows a 4 W standby supply. This supply is used in by the sum of the Zener voltage and the voltage drop across the
appliances where certain standby functions (e.g. real time LED of the optocoupler (the voltage drop across R1 is negligible).
clock, remote control port) must be kept active even while the The output transistor of the optocoupler drives the CONTROL
main power supply is turned off. pin of the TOP221. C5 bypasses the CONTROL pin and provides
control loop compensation and sets the auto-restart frequency.
The 5 V secondary is used to supply the standby function and
the 12 V non-isolated output is used to supply power for the The transformer’s leakage inductance voltage spikes are snubbed
PWM controller of the main power supply and other primary by R3 and C1 through diode D1. The bias winding is rectified
side functions. and filtered by D3 and C4 providing a non-isolated 12 V output
which is also used to bias the collector of the optocoupler’s
For this application the input rectifiers and input filter are sized output transistor. The isolated 5 V output winding is rectified by
for the main supply and are not shown. The input DC rail may D2 and filtered by C2, L1 and C3.

D
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 TOP221-227

D2 L1
MUR420 3.3 µH
+12 V
VR1 C2 C3
P6KE200 330 µF 220 µF
35 V 35 V
RTN
BR1 D1
L2 400 V BYV26C D3
22 mH 1N4148 R1
C1 100 Ω
47 µF
400 V C4
U1 0.1 µF
C6 D TOP224P
R2
0.1 µF TOPSwitch-II T1 220 Ω
250 VAC CONTROL
C U2
PC817A
R3
S
F1 6.8 Ω
C7 VR2
J1 3.15 A
C5 1 nF 1N5241B
L 47 µF 250 VAC 11 V
Y1
N

PI-2019-033197

Figure 8. Schematic Diagram of a 20 W Universal Input TOPSwitch-II Power Supply using an 8 lead PDIP.

20 W Universal Supply using 8 Lead PDIP

Figure 8 shows a 12 V, 20 W secondary regulated flyback power leading-edge voltage spikes caused by transformer leakage
supply using the TOP224P in an eight lead PDIP package and inductance. The power secondary winding is rectified and
operating from universal 85 to 265 VAC input voltage. This filtered by D2, C2, L1, and C3 to create the 12 V output voltage.
example demonstrates the advantage of the higher power 8 pin R2 and VR2 provide a slight pre-load on the 12 V output to
leadframe used with the TOPSwitch-II family. This low cost improve load regulation at light loads. The bias winding is
package transfers heat directly to the board through six source rectified and filtered by D3 and C4 to create a TOPSwitch bias
pins, eliminating the heatsink and the associated cost. Efficiency voltage. L2 and Y1-safety capacitor C7 attenuate common
is typically 80% at low line input. Output voltage is directly mode emission currents caused by high voltage switching
sensed by optocoupler U2 and Zener diode VR2. The output waveforms on the DRAIN side of the primary winding and the
voltage is determined by the Zener diode (VR2) voltage and the primary to secondary capacitance. Leakage inductance of L2
voltage drops across the optocoupler (U2) LED and resistor R1. with C1 and C6 attenuates differential-mode emission currents
Other output voltages are possible by adjusting the transformer caused by the fundamental and harmonics of the trapezoidal or
turns ratio and value of Zener diode VR2. triangular primary current waveform. C5 filters internal
MOSFET gate drive charge current spikes on the CONTROL
AC power is rectified and filtered by BR1 and C1 to create the pin, determines the auto-restart frequency, and together with
high voltage DC bus applied to the primary winding of T1. The R1 and R3, compensates the control loop.
other side of the transformer primary is driven by the integrated
TOPSwitch-II high-voltage MOSFET. D1 and VR1 clamp

D
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 TOP221-227

Key Application Considerations

General Guidelines • Short interruptions of AC power may cause TOPSwitch to
enter the 8-count auto-restart cycle before starting again.
• Keep the SOURCE pin length very short. Use a Kelvin This is because the input energy storage capacitors are not
connection to the SOURCE pin for the CONTROL pin completely discharged and the CONTROL pin capacitance
bypass capacitor. Use single point grounding techniques at has not discharged below the internal power-up reset
the SOURCE pin as shown in Figure 9. voltage.

• Minimize peak voltage and ringing on the DRAIN voltage • In some cases, minimum loading may be necessary to keep
at turn-off. Use a Zener or TVS Zener diode to clamp the a lightly loaded or unloaded output voltage within the
drain voltage below the breakdown voltage rating of desired range due to the minimum ON-time.
TOPSwitch under all conditions, including start-up and
overload. The maximum recommended clamp Zener ReplacingTOPSwitch with TOPSwitch-II
voltage for the TOP2XX series is 200 V and the
corresponding maximum reflected output voltage on the There is no external latching shutdown function in
primary is 135 V. Please see Step 4: AN-16 in the 1996-97 TOPSwitch-II. Otherwise, the functionality of the
Data Book and Design Guide or on our Web site. TOPSwitch-II devices is same as that of the TOPSwitch family.
However, before considering TOPSwitch-II as a 'drop in'
• The transformer should be designed such that the rate of replacement in an existing TOPSwitch design, the design
change of drain current due to transformer saturation is should be verified as described below.
within the absolute maximum specification (∆ID in 100 ns
before turn off as shown in Figure 13). As a guideline, for The new TOPSwitch-II family offers more power capability
most common transformer cores, this can be achieved by than the original TOPSwitch family for the same MOSFET
maintaining the Peak Flux Density (at maximum ILIMIT RDS(ON). Therefore, the original TOPSwitch design must be
current) below 4200 Gauss (420 mT). The transformer reviewed to make sure that the selected TOPSwitch-II
spreadsheets Rev. 2.1 (or later) for continuous and Rev.1.0 replacement device and other primary components are not over
(or later) for discontinuous conduction mode provide the stressed under abnormal conditions.
necessary information.
The following verification steps are recommended:
• Do not plug TOPSwitch into a “hot” IC socket during test.
External CONTROL pin capacitance may be charged to • Check the transformer design to make sure that it meets the
excessive voltage and cause TOPSwitch damage. ∆ID specification as outlined in the General Guidelines
section above.
• While performing TOPSwitch device tests, do not exceed
maximum CONTROL pin voltage of 9 V or maximum • Thermal: Higher power capability of the TOPSwitch-II
CONTROL pin current of 100 mA. would in many instances allow use of a smaller MOSFET
device (higher RDS(ON)) for reduced cost. This may affect
• Under some conditions, externally provided bias or supply TOPSwitch power dissipation and power supply efficiency.
current driven into the CONTROL pin can hold the Therefore thermal performance of the power supply must
TOPSwitch in one of the 8 auto-restart cycles indefinitely be verified with the selected TOPSwitch-II device.
and prevent starting. To avoid this problem when doing
bench evaluations, it is recommended that the VC power • Clamp Voltage: Reflected and Clamp voltages should be
supply be turned on before the DRAIN voltage is applied. verified not to exceed recommended maximums for the
TOPSwitch can also be reset by shorting the CONTROL TOP2XX Series: 135 V Reflected/200 V Clamp. Please
pin to the SOURCE pin momentarily. see Step 4: AN-16 in the Data Book and Design Guide and
readme.txt file attached to the transformer design
• CONTROL pin currents during auto-restart operation are spreadsheets.
much lower at low input voltages (< 36 V) which increases
the auto-restart cycle time (see the IC vs. DRAIN Voltage • Agency Approval: Migrating to TOPSwitch-II may require
Characteristic curve). agency re-approval.

D
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 TOP221-227

TO-220 PACKAGE

Bias/Feedback High Voltage

Return Return Kelvin-connected
auto-restart/bypass capacitor C5 Do not bend SOURCE pin.
C S D and/or compensation network Keep it short.

CONTROL
SOURCE
Bend DRAIN pin

DRAIN
C5
PC Board forward if needed
Bias/Feedback for creepage.
Input
Kelvin-connected
auto-restart/bypass High-voltage Return
capacitor C5
C5 Bias/Feedback Input
and/or compensation
network Bias/Feedback Return
TOP VIEW

DIP-8/SMD-8 PACKAGE

Bias/Feedback
Return SOURCE

SOURCE
High Voltage
C5 Return

CONTROL DRAIN
Kelvin-connected
Bias/Feedback auto-restart/bypass capacitor C5
Input
and/or compensation network

TOP VIEW PI-2021-041798

Figure 9. Recommended TOPSwitch Layout.

Design Tools
The following tools available from Power Integrations greatly All data sheets, application literature and up-to-date versions of
simplify TOPSwitch based power supply design. the Transformer Design Spreadsheets can be downloaded from
our Web site at www.powerint.com. A diskette of the
• Data Book and Design Guide includes extensive application Transformer Design Spreadsheets may also be obtained by
information sending in the completed form provided at the end of this data
sheet.
• Excel Spreadsheets for Transformer Design - Use of this
tool is strongly recommended for all TOPSwitch designs.

• Reference design boards – Production viable designs that

are assembled and tested.

D
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 TOP221-227

ABSOLUTE MAXIMUM RATINGS(1)

DRAIN Voltage ............................................ -0.3 to 700 V Operating Junction Temperature(3) ................ -40 to 150 °C
DRAIN Current Increase (∆ID) in 100 ns except during Lead Temperature(4) ................................................ 260 °C
blanking time ......................................... 0.1 x ILIMIT(MAX)(2) Thermal Impedance: Y Package (θJA)(5) .................70 °C/W
CONTROL Voltage ..................................... - 0.3 V to 9 V (θJC)(6) ...................2 °C/W
CONTROL Current ............................................... 100 mA P/G Package:
Storage Temperature ..................................... -65 to 150 °C (θJA) .........45 °C/W(7); 35 °C/W(8)
Notes: (θJC)(6)...............................11 °C/W
1. All voltages referenced to SOURCE, TA = 25 °C. 5. Free standing with no heatsink.
2. Related to transformer saturation – see Figure 13. 6. Measured at tab closest to plastic interface or SOURCE pin.
3. Normally limited by internal circuitry. 7. Soldered to 0.36 sq. inch (232 mm2), 2 oz. (610 gm/m2) copper clad.
4. 1/16" from case for 5 seconds. 8. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 gm/m2) copper clad.

Conditions
(Unless Otherwise Specified)
Parameter Symbol Min Typ Max Units
See Figure 14
SOURCE = 0 V; TJ = -40 to 125 °C

CONTROL FUNCTIONS
Output fOSC IC = 4 mA, TJ = 25 °C 90 100 110 kHz
Frequency

Maximum DMAX 64 67 70 %
IC = ICD1 + 0.4 mA, See Figure 10
Duty Cycle

Minimum DMIN 0.7 1.7 2.7 %

Duty Cycle IC = 10 mA, See Figure 10

PWM IC = 4 mA, TJ = 25 °C
-21 -16 -11 %/mA
Gain See Figure 4

PWM Gain See Note A %/mA/°C

-0.05
Temperature Drift

External IB See Figure 4 mA

0.8 2.0 3.3
Bias Current

Dynamic IC = 4 mA, TJ = 25 °C
ZC 10 15 22 Ω
Impedance See Figure 11

Dynamic Impedance %/°C

0.18
Temperature Drift
SHUTDOWN/AUTO-RESTART
VC = 0 V -2.4 -1.9 -1.2
CONTROL Pin IC TJ = 25 °C mA
Charging Current VC = 5 V -2 -1.5 -0.8

Charging Current See Note A %/°C

0.4
Temperature Drift

D
10 7/01
 TOP221-227

Conditions
(Unless Otherwise Specified)
Parameter Symbol Min Typ Max Units
See Figure 14
SOURCE = 0 V; TJ = -40 to 125 °C

SHUTDOWN/AUTO-RESTART (cont.)
Auto-restart VC(AR) S1 open 5.7 V
Threshold Voltage

UV Lockout S1 open 4.4 4.7 5.0 V

Threshold Voltage

Auto-restart S1 open 0.6 1.0 V

Hysteresis Voltage

Auto-restart TOP221-222 2 5 9
S1 open %
Duty Cycle TOP223-227 2 5 8

Auto-restart S1 open 1.2 Hz

Frequency

CIRCUIT PROTECTION
di/dt = 40 mA/µs, TOP221Y 0.23 0.25 0.28
TJ = 25 °C TOP221P or G
di/dt = 80 mA/µs, TOP222Y
0.45 0.50 0.55
TJ = 25 °C TOP222P or G
di/dt = 160 mA/µs, TOP223Y
0.90 1.00 1.10
TJ = 25 °C TOP223P or G
Self-protection ILIMIT di/dt = 240 mA/µs, TOP224Y A
Current Limit 1.35 1.50 1.65
TJ = 25 °C TOP224P or G
di/dt = 320 mA/µs,
TOP225Y 1.80 2.00 2.20
TJ = 25 °C
di/dt = 400 mA/µs,
TOP226Y 2.25 2.50 2.75
TJ = 25 °C
di/dt = 480 mA/µs,
TOP227Y 2.70 3.00 3.30
TJ = 25 °C

≤ 85 VAC 0.75 x
Initial Current See Figure 12 (Rectified Line Input) ILIMIT(MIN)
Limit IINIT TJ = 25 °C A
265 VAC 0.6 x
(Rectified Line Input) ILIMIT(MIN)

Leading Edge IC = 4 mA,

tLEB 180 ns
Blanking Time TJ = 25 °C

D
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 TOP221-227

Conditions
(Unless Otherwise Specified)
Parameter Symbol Min Typ Max Units
See Figure 14
SOURCE = 0 V; TJ = -40 to 125 °C

CIRCUIT PROTECTION (cont.)

Current Limit tILD IC = 4 mA 100 ns
Delay

Thermal Shutdown 125 135 °C

IC = 4 mA
Temperature

Power-up Reset VC(RESET) S2 open 2.0 3.3 4.3 V

Threshold Voltage
OUTPUT
TOP221 TJ = 25 °C 31.2 36.0
ID = 25 mA TJ = 100 °C 51.4 60.0
TOP222 TJ = 25 °C 15.6 18.0
ID = 50 mA TJ = 100 °C 25.7 30.0
TOP223 TJ = 25 °C 7.8 9.0
ID = 100 mA TJ = 100 °C 12.9 15.0
ON-State TOP224 TJ = 25 °C
RDS(ON) 5.2 6.0 Ω
Resistance
ID = 150 mA TJ = 100 °C 8.6 10.0
TOP225 TJ = 25 °C 3.9 4.5
ID = 200 mA TJ = 100 °C 6.4 7.5
TOP226 TJ = 25 °C 3.1 3.6
ID = 250 mA TJ = 100 °C 5.2 6.0
TOP227 TJ = 25 °C 2.6 3.0
ID = 300 mA TJ = 100 °C 4.3 5.0
See Note B
OFF-State IDSS 250 µA
Current VDS = 560 V, TA = 125 °C

See Note B
Breakdown BVDSS 700 V
Voltage ID = 100 µA, TA = 25 °C

Rise tR 100 ns
Time
Measured in a Typical Flyback

Fall Converter Application.

tF 50 ns
Time

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 TOP221-227

Conditions
(Unless Otherwise Specified)
Parameter Symbol Min Typ Max Units
See Figure 14
SOURCE = 0 V; TJ = -40 to 125 °C

OUTPUT (cont.)
DRAIN Supply See Note C 36 V
Voltage

Shunt Regulator VC(SHUNT) IC = 4 mA 5.5 5.7 6.0 V

Voltage

Shunt Regulator ±50 ppm/°C

Temperature Drift
Output TOP221-224 0.6 1.2 1.6
ICD1
CONTROL Supply/ MOSFET Enabled TOP225-227 0.7 1.4 1.8
mA
Discharge Current
ICD2 Output MOSFET Disabled 0.5 0.8 1.1

NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in
magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in
magnitude with increasing temperature.

B. The breakdown voltage and leakage current measurements can be accomplished as shown in Figure 15 by using
the following sequence:

i. The curve tracer should initially be set at 0 V. The base output should be adjusted through a voltage sequence
of 0 V, 6.5 V, 4.3 V, and 6.5 V, as shown. The base current from the curve tracer should not exceed 100 mA. This
CONTROL pin sequence interrupts the Auto-restart sequence and locks the TOPSwitch internal MOSFET in the
OFF State.
ii. The breakdown and the leakage measurements can now be taken with the curve tracer. The maximum
voltage from the curve tracer must be limited to 700 V under all conditions.

C. It is possible to start up and operate TOPSwitch at DRAIN voltages well below 36 V. However, the CONTROL pin
charging current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle. Refer
to the characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage for low voltage operation
characteristics.

D
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 TOP221-227

120

PI-1939-091996
CONTROL Pin Current (mA)
100

t2
80
t1
HV 90% 90% 60

40
DRAIN t
D= 1 Dynamic
=
1
VOLTAGE t2 Impedance Slope
20
10%
0V 0
0 2 4 6 8 10
PI-2039-040401
CONTROL Pin Voltage (V)
Figure 10. TOPSwitch Duty Cycle Measurement. Figure 11. TOPSwitch CONTROL Pin I-V Characteristic.
PI-2022-033001

tLEB (Blanking Time)

1.3
1.2
DRAIN Current (normalized)

1.1
1.0
100 ns
0.9
0.8 tLEB
IINIT(MIN) @ 85 VAC ∆ID
0.7
0.6 IINIT(MIN) @ 265 VAC
0.5 DRAIN
0.4 ILIMIT(MAX) @ 25 °C CURRENT
0.3 ILIMIT(MIN) @ 25 °C
0.2
0.1
0 0A
0 1 2 3 4 5 6 7 8
Time (µs) PI-2031-040401

Figure 12. Self-protection Current Limit Envelope. Figure 13. Example of ∆ID on Drain Current Waveform with
Saturated Transformer.

D
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 TOP221-227

470 Ω
5W S2

D
CONTROL 470 Ω
C
TOPSwitch
S1
S 40 V
0.1 µF 47 µF 0-50 V

NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
2. For P package, short all SOURCE and SOURCE (HV RTN) pins together.
PI-1964-110696

Figure 14. TOPSwitch General Test Circuit.

Curve
Tracer

C B E

D
CONTROL
C
TOPSwitch
S

6.5 V
4.3 V

NOTE: This CONTROL pin sequence interrupts the Auto-restart sequence and
locks the TOPSwitch internal MOSFET in the OFF State.
PI-2109-040401

Figure 15. Breakdown Voltage and Leakage Current Measurement Test Circuit.

D
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 TOP221-227

BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS

The following precautions should be followed when testing Auto-restart mode, there is only a 12.5% chance that the control
TOPSwitch by itself outside of a power supply. The schematic pin oscillation will be in the correct state (DRAIN active state)
shown in Figure 14 is suggested for laboratory testing of so that the continuous DRAIN voltage waveform may be
TOPSwitch. observed. It is recommended that the VC power supply be
turned on first and the DRAIN power supply second if continuous
When the DRAIN supply is turned on, the part will be in the drain voltage waveforms are to be observed. The 12.5% chance
Auto-restart mode. The CONTROL pin voltage will be of being in the correct state is due to the 8:1 counter. Temporarily
oscillating at a low frequency from 4.7 to 5.7 V and the DRAIN shorting the CONTROL pin to the SOURCE pin will reset
is turned on every eighth cycle of the CONTROL pin oscillation. TOPSwitch, which then will come up in the correct state.
If the CONTROL pin power supply is turned on while in this

Typical Performance Characteristics

BREAKDOWN vs. TEMPERATURE FREQUENCY vs. TEMPERATURE
1.1 1.2

PI-1123A-033001
PI-176B-051391

1.0
Breakdown Voltage (V)

(Normalized to 25 °C)
(Normalized to 25 °C)

Output Frequency
0.8

1.0 0.6

0.4

0.2

0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)

CURRENT LIMIT vs. TEMPERATURE IC vs. DRAIN VOLTAGE

1.2 2 PI-1145-103194
PI-1125-033001

VC = 5 V

1.0
Charging Current (mA)

1.6
(Normalized to 25 °C)

CONTROL Pin
Current Limit

0.8
1.2
0.6

0.8
0.4

0.2 0.4

0 0
-50 -25 0 25 50 75 100 125 150 0 20 40 60 80 100
Junction Temperature (°C) DRAIN Voltage (V)

D
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 TOP221-227

Typical Performance Characteristics (cont.)

OUTPUT CHARACTERISTICS COSS vs. DRAIN VOLTAGE

3 1000

PI-1940-033001

PI-1941-033001
TCASE=25 °C Scaling Factors:
TCASE=100 °C
TOP227 1.00

DRAIN Capacitance (pF)

TOP226 0.83
DRAIN Current (A)

TOP225 0.67
2 TOP224 0.50
TOP223 0.33
TOP222 0.17
TOP221 0.09
100
Scaling Factors:
TOP227 1.00
1 TOP226 0.83
TOP225 0.67
TOP224 0.50
TOP223 0.33
TOP222 0.17
TOP221 0.09
0 10
0 2 4 6 8 10 0 200 400 600
DRAIN Voltage (V) DRAIN Voltage (V)

DRAIN CAPACITANCE POWER

500

PI-1942-033001
Scaling Factors:
TOP227 1.00
400 TOP226 0.83
TOP225 0.67
TOP224 0.50
Power (mW)

300 TOP223 0.33

TOP222 0.17
TOP221 0.09

200

100

0
0 200 400 600
DRAIN Voltage (V)

D
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TOP221-227

TO-220/3
DIM inches mm

A .460-.480 11.68-12.19
J
B .400-.415 10.16-10.54 B K
C .236-.260 5.99-6.60
D .240 - REF. 6.10 - REF. P
C Notes:
E .520-.560 13.21-14.22 1. Package dimensions conform to
F .028-.038 .71-.97 O JEDEC specification TO-220 AB for
standard flange mounted, peripheral
G .045-.055 1.14-1.40 lead package; .100 inch lead spacing
A (Plastic) 3 leads (issue J, March 1987)
H .090-.110 2.29-2.79 2. Controlling dimensions are inches.
3. Pin numbers start with Pin 1, and
J .165-.185 4.19-4.70 N continue from left to right when
K .045-.055 1.14-1.40 viewed from the top.
4. Dimensions shown do not include
L .095-.115 2.41-2.92 mold flash or other protrusions. Mold
L flash or protrusions shall not exceed
M .015-.020 .38-.51 D .006 (.15 mm) on any side.
17.91-18.16 5. Position of terminals to be
N .705-.715 measured at a position .25 (6.35 mm)
O .146-.156 3.71-3.96 from the body.
E 6. All terminals are solder plated.
P .103-.113 2.62-2.87

F M
G
H Y03A
PI-1848-040901

DIP-8
D S .004 (.10)
DIM inches mm
8 5

-E-
A 0.370-0.385 9.40-9.78
B 0.245-0.255 6.22-6.48
C 0.125-0.135 3.18-3.43
G 0.015-0.040 0.38-1.02
H 0.120-0.135 3.05-3.43 B
J1 0.060 (NOM) 1.52 (NOM)
J2 0.014-0.022 0.36-0.56
K 0.010-0.012 0.25-0.30
L 0.090-0.110 2.29-2.79
M 0.030 (MIN) 0.76 (MIN) 1 4
N 0.300-0.320 7.62-8.13 A -D-
P 0.300-0.390 7.62-9.91 M J1 N
Q 0.300 BSC 7.62 BSC

Notes:
1. Package dimensions conform to JEDEC C
specification MS-001-AB for standard dual
in-line (DIP) package .300 inch row spacing
(PLASTIC) 8 leads (issue B, 7/85).. -F-
2. Controlling dimensions are inches.
3. Dimensions shown do not include mold
flash or other protrusions. Mold flash or H K
G
protrusions shall not exceed .006 (.15) on
any side. Q
4. D, E and F are reference datums on the J2
molded body. L P P08A
PI-2076-040901

D
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 TOP221-227

SMD-8
D S .004 (.10) Heat Sink is 2 oz. Copper DIM inches mm
As Big As Possible
8 5
-E- A 0.370-0.385 9.40-9.78
B 0.245-0.255 6.22-6.48
C 0.125-0.135 3.18-3.43

E S .010 (.25)
G 0.004-0.012 0.10-0.30
B P .420 H 0.036-0.044 0.91-1.12
J1 0.060 (NOM) 1.52 (NOM)
.046 .060 .060 .046 J2 0.048-0.053 1.22-1.35
J3 0.032-0.037 0.81-0.94
.080 J4 0.007-0.011 0.18-0.28
Pin 1
1 4 K 0.010-0.012 0.25-0.30
L L 0.100 BSC 2.54 BSC
.086
.186 M 0.030 (MIN) 0.76 (MIN)
A -D- .286 P 0.372-0.388 9.45-9.86
M J1 Solder Pad Dimensions α 0-8° 0-8°

Notes:
1. Package dimensions conform to JEDEC
specification MS-001-AB (issue B, 7/85)
C
K except for lead shape and size.
2. Controlling dimensions are inches.
-F- 3. Dimensions shown do not include mold
.004 (.10) flash or other protrusions. Mold flash or
J3 J4 protrusions shall not exceed .006 (.15) on
α G any side.
G08A J2 .010 (.25) M A S H 4. D, E and F are reference datums on the
molded body.
PI-2077-042601

D
7/01 19
 TOP221-227

Revision Notes Date

C - 12/97
1) Updated package references.
D 7/01
2) Corrected Spelling.
3) Corrected Storage Temperature θJC and updated nomenclature in parameter table.
4) Added G package references to Self-Protection Current Limit parameter.
5) Corrected font sizes in figures.

For the latest updates, visit our Web site: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.

The PI Logo, TOPSwitch, TinySwitch and EcoSmart are registered trademarks of Power Integrations, Inc.
©Copyright 2001, Power Integrations, Inc.

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