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Cad of Electronics Lab

The document describes the design, simulation and analysis of several digital logic circuits including: 1) A 2-input NAND and NOR gate 2) A full adder 3) A 4-bit adder/subtractor 4) An up/down and mod-m counter 5) A mod-5 counter 6) A basic ROM The circuits are modeled using VHDL code and are analyzed through simulation.

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Vaibhav Pandey
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128 views4 pages

Cad of Electronics Lab

The document describes the design, simulation and analysis of several digital logic circuits including: 1) A 2-input NAND and NOR gate 2) A full adder 3) A 4-bit adder/subtractor 4) An up/down and mod-m counter 5) A mod-5 counter 6) A basic ROM The circuits are modeled using VHDL code and are analyzed through simulation.

Uploaded by

Vaibhav Pandey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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CAD OF ELECTRONICS LAB (PCS-854)

1. Design, simulation and analysis of two input NAND and NOR gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nand_nor_top is
Port ( A1 : in STD_LOGIC; -- NAND gate input 1
A2 : in STD_LOGIC; -- NAND gate input 2
X1 : out STD_LOGIC; -- NAND gate output
B1 : in STD_LOGIC; -- NOR gate input 1
B2 : in STD_LOGIC; -- NOR gate input 2
Y1 : out STD_LOGIC); -- NOR gate output
end nand_nor_top;

architecture Behavioral of nand_nor_top is


begin
X1 <= A1 nand A2; -- 2 input NAND gate
Y1 <= B1 nor B2; -- 2 input NOR gate
end Behavioral;

2. Design, simulation and analysis of FULL ADDER

library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end Full_Adder;

architecture bhv of Full_Adder is


begin
sum <= (X xor Y) xor Cin;
Cout <= (X and (Y or Cin)) or (Cin and Y);
end bhv;

3. Design, simulation and analysis of 4 bit Adder Subtractor


library ieee;
use ieee.std_logic_1164.all;
entity addsub is
port( OP: in std_logic;
A,B : in std_logic_vector(3 downto 0);
R : out std_logic_vector(3 downto 0);
Cout, OVERFLOW : out std_logic);
end addsub;

architecture struct of addsub is


component Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end component;
signal C1, C2, C3, C4: std_logic;
signal TMP: std_logic_vector(3 downto 0);

begin
TMP <= A xor B;
FA0:Full_Adder port map(A(0),TMP(0),OP, R(0),C1);-- R0
FA1:Full_Adder port map(A(1),TMP(1),C1, R(1),C2);-- R1
FA2:Full_Adder port map(A(2),TMP(2),C2, R(2),C3);-- R2
FA3:Full_Adder port map(A(3),TMP(3),C3, R(3),C4);-- R3
OVERFLOW <= C3 XOR C4 ;
Cout <= C4;
end struct;

4. Design, simulation and analysis of Up/ Down, Mod-m counter.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity up_dn_counter_top is
Port ( CLK : in STD_LOGIC; -- input clock
-- LEDs to display count
LED : out STD_LOGIC_VECTOR (7 downto 0);
DIR : in STD_LOGIC); -- direction of counter (up or down)
end up_dn_counter_top;

architecture Behavioral of up_dn_counter_top is


signal clk_div : STD_LOGIC_VECTOR (3 downto 0) := X"0";
signal count : STD_LOGIC_VECTOR (7 downto 0) := X"00";
begin

-- clock divider
process (CLK)
begin
if (CLK'Event and CLK = '1') then
clk_div <= clk_div + '1';
end if;
end process;

-- up/down counter
process (clk_div(3), DIR)
begin
if (clk_div(3)'Event and clk_div(3) = '1') then
if (DIR = '1') then
count <= count + '1'; -- counting up
elsif (DIR = '0') then
count <= count - '1'; -- counting down
end if;
end if;
end process;

-- display count on LEDs


LED <= not count;

end Behavioral;
5. Design, simulation and analysis Mod-5 counter.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mod5 Is
PORT( CLK,CLR:IN BIT;
QOUT:BUFFER INTEGER RANGE 0 to 7);
END mod5;

ARCHITECTURE arc OF mod5 is


BEGIN
PROCESS (CLK,CLR)
BEGIN

IF (CLK'EVENT and CLK='1') THEN


QOUT<=QOUT +1;
IF (QOUT=2) THEN
QOUT<=6;
QOUT<=QOUT + 1;

END IF;
END IF;
END PROCESS;
END arc;

6.Design, simulation and analysis of ROM.

library ieee;
use ieee.std_logic_1164.all;

entity ROM is
port ( address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(7 downto 0) );
end entity ROM;

architecture behavioral of ROM is


type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);
constant my_Rom : mem := (
0 => "00000000",
1 => "00000001",
2 => "00000010",
3 => "00000011",
4 => "00000100",
5 => "11110000",
6 => "11110000",
7 => "11110000",
8 => "11110000",
9 => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000");
begin
process (address)
begin
case address is
when "0000" => data <= my_rom(0);
when "0001" => data <= my_rom(1);
when "0010" => data <= my_rom(2);
when "0011" => data <= my_rom(3);
when "0100" => data <= my_rom(4);
when "0101" => data <= my_rom(5);
when "0110" => data <= my_rom(6);
when "0111" => data <= my_rom(7);
when "1000" => data <= my_rom(8);
when "1001" => data <= my_rom(9);
when "1010" => data <= my_rom(10);
when "1011" => data <= my_rom(11);
when "1100" => data <= my_rom(12);
when "1101" => data <= my_rom(13);
when "1110" => data <= my_rom(14);
when "1111" => data <= my_rom(15);
when others => data <= "00000000";
end case;
end process;
end architecture behavioral;

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