Circuit Design with VHDL, Volnei A.

Pedroni, MIT Press, 2004

Circuit Design with VHDL

Volnei A. Pedroni
MIT Press – Aug. 2004

VHDL Code from Some of the Examples

Example 4.3: Generic parity generator
Solution 1:
------------------------------------------------
ENTITY parity_gen IS
GENERIC (n: INTEGER := 7);
PORT (input: IN BIT_VECTOR (n-1 DOWNTO 0);
output: OUT BIT_VECTOR (n DOWNTO 0));
END parity_gen;
------------------------------------------------
ARCHITECTURE parity OF parity_gen IS
BEGIN
PROCESS (input)
VARIABLE temp1: BIT;
VARIABLE temp2: BIT_VECTOR (output'RANGE);
BEGIN
temp1 := '0';
FOR i IN input'RANGE LOOP
temp1 := temp1 XOR input(i);
temp2(i) := input(i);
END LOOP;
temp2(output'HIGH) := temp1;
output <= temp2;
END PROCESS;
END parity;
------------------------------------------------

Solution 2:
------------------------------------------------
ENTITY parity_generator IS
GENERIC (n: INTEGER := 7);
PORT (input: IN BIT_VECTOR (n-1 DOWNTO 0);
output: OUT BIT_VECTOR (n DOWNTO 0));
END parity_generator;
------------------------------------------------
ARCHITECTURE parity OF parity_generator IS
BEGIN
PROCESS (input)
VARIABLE temp: BIT;
BEGIN
temp := '0';
FOR i IN input'RANGE LOOP
temp := temp XOR input(i);
END LOOP;
output <= (temp & input);
END PROCESS;
END parity;
------------------------------------------------

Simulation results (from either solution) are shown below.

 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

Example 6.3: Shift register

--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------------
ENTITY shiftreg IS
GENERIC (n: INTEGER := 4); --number of stages
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END shiftreg;
--------------------------------------------------------------
ARCHITECTURE behavior OF shiftreg IS
SIGNAL internal: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
internal <= (OTHERS => '0');
ELSIF (clk'EVENT AND clk='1') THEN
internal <= (d & internal(internal'LEFT DOWNTO 1));
END IF;
END PROCESS;
q <= internal(0);
END behavior;
--------------------------------------------------------------

Example 6.7: Two-digit BCD counter with SSD output

-----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------------------------
ENTITY counter IS
PORT (clk, reset: IN STD_LOGIC;
digit1, digit2: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END counter;
-----------------------------------------------------------
ARCHITECTURE counter OF counter IS
BEGIN
PROCESS(clk, reset)
VARIABLE temp1: INTEGER RANGE 0 TO 10;
VARIABLE temp2: INTEGER RANGE 0 TO 10;
BEGIN
----counter:----------------------
IF (reset=’1’) THEN
temp1 := 0;
temp2 := 0;
ELSIF (clk’EVENT AND clk=’1’) THEN
temp1 := temp1 + 1;
IF (temp1=10) THEN
temp1 := 0;
temp2 := temp2 + 1;
IF (temp2=10) THEN
temp2 := 0;
END IF;
END IF;
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

END IF;
----BCD to SSD conversion:--------
CASE temp1 IS
WHEN 0 => digit1 <= ”1111110”; --7E
WHEN 1 => digit1 <= ”0110000”; --30
WHEN 2 => digit1 <= ”1101101”; --6D
WHEN 3 => digit1 <= ”1111001”; --79
WHEN 4 => digit1 <= ”0110011”; --33
WHEN 5 => digit1 <= ”1011011”; --5B
WHEN 6 => digit1 <= ”1011111”; --5F
WHEN 7 => digit1 <= ”1110000”; --70
WHEN 8 => digit1 <= ”1111111”; --7F
WHEN 9 => digit1 <= ”1111011”; --7B
WHEN OTHERS => NULL;
END CASE;
CASE temp2 IS
WHEN 0 => digit2 <= ”1111110”; --7E
WHEN 1 => digit2 <= ”0110000”; --30
WHEN 2 => digit2 <= ”1101101”; --6D
WHEN 3 => digit2 <= ”1111001”; --79
WHEN 4 => digit2 <= ”0110011”; --33
WHEN 5 => digit2 <= ”1011011”; --5B
WHEN 6 => digit2 <= ”1011111”; --5F
WHEN 7 => digit2 <= ”1110000”; --70
WHEN 8 => digit2 <= ”1111111”; --7F
WHEN 9 => digit2 <= ”1111011”; --7B
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END counter;
-----------------------------------------------------------

Example 6.10: Leading zeros

-----------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------------
ENTITY LeadingZeros IS
PORT (data: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
zeros: OUT INTEGER RANGE 0 TO 8);
END LeadingZeros;
-----------------------------------------------
ARCHITECTURE behavior OF LeadingZeros IS
BEGIN
PROCESS (data)
VARIABLE count: INTEGER RANGE 0 TO 8;
BEGIN
count := 0;
FOR i IN data'RANGE LOOP
CASE data(i) IS
WHEN '0' => count := count + 1;
WHEN OTHERS => EXIT;
END CASE;
END LOOP;
zeros <= count;
END PROCESS;
END behavior;
-----------------------------------------------

Simulation results from this code are shown below.

 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

Example 6.11: RAM implementation

--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------
ENTITY ram IS
GENERIC (bits: INTEGER := 8; --# of bits per word
words: INTEGER := 16); --# of words in memory
PORT (wr_ena, clk: IN STD_LOGIC;
addr: IN INTEGER RANGE 0 TO words-1;
data_in: IN STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0));
END ram;
--------------------------------------------------------
ARCHITECTURE ram OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
SIGNAL memory: vector_array;
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='1') THEN
IF (clk'EVENT AND clk='1') THEN
memory(addr) <= data_in;
END IF;
END IF;
END PROCESS;
data_out <= memory(addr);
END ram;
--------------------------------------------------------

Example 8.5: Traffic-light controller

--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------
ENTITY tlc IS
PORT (clk, stby, test: IN STD_LOGIC;
r1, r2, y1, y2, g1, g2: OUT STD_LOGIC);
END tlc;
--------------------------------------------------------
ARCHITECTURE behavior OF tlc IS
CONSTANT timeMAX : INTEGER := 2700;
CONSTANT timeRG : INTEGER := 1800;
CONSTANT timeRY : INTEGER := 300;
CONSTANT timeGR : INTEGER := 2700;
CONSTANT timeYR : INTEGER := 300;
CONSTANT timeTEST : INTEGER := 60;
TYPE state IS (RG, RY, GR, YR, YY);
SIGNAL pr_state, nx_state: state;
SIGNAL time : INTEGER RANGE 0 TO timeMAX;
BEGIN
--------Lower section of state machine:----
PROCESS (clk, stby)
VARIABLE count: INTEGER RANGE 0 TO timeMAX;
BEGIN
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

IF (stby='1') THEN
pr_state <= YY;
count := 0;
ELSIF (clk'EVENT AND clk='1') THEN
count := count + 1;
IF (count=time) THEN
pr_state <= nx_state;
count := 0;
END IF;
END IF;
END PROCESS;
--------Upper section of state machine:----
PROCESS (pr_state, test)
BEGIN
CASE pr_state IS
WHEN RG =>
r1<='1'; r2<='0'; y1<='0'; y2<='0'; g1<='0'; g2<='1';
nx_state <= RY;
IF (test='0') THEN time <= timeRG;
ELSE time <= timeTEST;
END IF;
WHEN RY =>
r1<='1'; r2<='0'; y1<='0'; y2<='1'; g1<='0'; g2<='0';
nx_state <= GR;
IF (test='0') THEN time <= timeRY;
ELSE time <= timeTEST;
END IF;
WHEN GR =>
r1<='0'; r2<='1'; y1<='0'; y2<='0'; g1<='1'; g2<='0';
nx_state <= YR;
IF (test='0') THEN time <= timeGR;
ELSE time <= timeTEST;
END IF;
WHEN YR =>
r1<='0'; r2<='1'; y1<='1'; y2<='0'; g1<='0'; g2<='0';
nx_state <= RG;
IF (test='0') THEN time <= timeYR;
ELSE time <= timeTEST;
END IF;
WHEN YY =>
r1<='0'; r2<='0'; y1<='1'; y2<='1'; g1<='0'; g2<='0';
nx_state <= RY;
END CASE;
END PROCESS;
END behavior;
--------------------------------------------------------------------

Example 9.2: Signed comparator

------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; --necessary!
------------------------------------------
ENTITY comparator IS
GENERIC (n: INTEGER := 7);
PORT (a, b: IN SIGNED(n DOWNTO 0);
x1, x2, x3: OUT STD_LOGIC);
END comparator;
------------------------------------------
ARCHITECTURE signed_comp OF comparator IS
BEGIN
x1 <= '1' WHEN a > b ELSE '0';
x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0';
END signed_comp;
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

------------------------------------------

Simulation results from this code are shown below.

Example 9.3: Carry-lookahead adder

-----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------------------------
ENTITY CLA_Adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin: IN STD_LOGIC;
s: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: OUT STD_LOGIC);
END CLA_Adder;
-----------------------------------------------------------
ARCHITECTURE CLA_Adder OF CLA_Adder IS
SIGNAL c: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL p: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL g: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
---- PGU: ---------------------------------
G1: FOR i IN 0 TO 3 GENERATE
p(i) <= a(i) XOR b(i);
g(i) <= a(i) AND b(i);
s(i) <= p(i) XOR c(i);
END GENERATE;
---- CLAU: --------------------------------
c(0) <= cin;
c(1) <= (cin AND p(0)) OR g(0);
c(2) <= (cin AND p(0) AND p(1)) OR (g(0) AND p(1)) OR g(1);
c(3) <= (cin AND p(0) AND p(1) AND p(2)) OR
(g(0) AND p(1) AND p(2)) OR
(g(1) AND p(2)) OR
g(2);
c(4) <= (cin AND p(0) AND p(1) AND p(2) AND p(3)) OR
(g(0) AND p(1) AND p(2) AND p(3)) OR
(g(1) AND p(2) AND p(3)) OR
(g(2) AND p(3)) OR
g(3);
cout <= c(4);
END CLA_Adder;
-----------------------------------------------------------

Example 9.8: Playing with a seven-segment display

a ab b bc c cd
time1 time2 time1 time2 time1

time2
time2

fa f ef e de d
time1 time2 time1 time2 time1
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

Solution 1 (see state transition diagram above):

-----------------------------------------------------------
ENTITY ssd_game IS
PORT (clk, stop: IN BIT;
dout: OUT BIT_VECTOR(6 DOWNTO 0));
END ssd_game;
-----------------------------------------------------------
ARCHITECTURE fsm OF ssd_game IS
CONSTANT time1: INTEGER := 4; --actual value is 80
CONSTANT time2: INTEGER := 2; --actual value is 30
TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);
SIGNAL present_state, next_state: states;
SIGNAL count: INTEGER RANGE 0 TO 5;
SIGNAL flip: BIT;
BEGIN
-------Lower section of FSM:------------
PROCESS (clk, stop)
BEGIN
IF (stop='1') THEN
present_state <= a;
ELSIF (clk'EVENT AND clk='1') THEN
IF ((flip='1' AND count=time1) OR
(flip='0' AND count=time2)) THEN
count <= 0;
present_state <= next_state;
ELSE count <= count + 1;
END IF;
END IF;
END PROCESS;
-------Upper section of FSM:------------
PROCESS (present_state)
BEGIN
CASE present_state IS
WHEN a =>
dout <= "1000000"; --Decimal 64
flip<='1';
next_state <= ab;
WHEN ab =>
dout <= "1100000"; --Decimal 96
flip<='0';
next_state <= b;
WHEN b =>
dout <= "0100000"; --Decimal 32
flip<='1';
next_state <= bc;
WHEN bc =>
dout <= "0110000"; --Decimal 48
flip<='0';
next_state <= c;
WHEN c =>
dout <= "0010000"; --Decimal 16
flip<='1';
next_state <= cd;
WHEN cd =>
dout <= "0011000"; --Decimal 24
flip<='0';
next_state <= d;
WHEN d =>
dout <= "0001000"; --Decimal 8
flip<='1';
next_state <= de;
WHEN de =>
dout <= "0001100"; --Decimal 12
flip<='0';
next_state <= e;
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

WHEN e =>
dout <= "0000100"; --Decimal 4
flip<='1';
next_state <= ef;
WHEN ef =>
dout <= "0000110"; --Decimal 6
flip<='0';
next_state <= f;
WHEN f =>
dout <= "0000010"; --Decimal 2
flip<='1';
next_state <= fa;
WHEN fa =>
dout <= "1000010"; --Decimal 66
flip<='0';
next_state <= a;
END CASE;
END PROCESS;
END fsm;
-----------------------------------------------------------

Solution 2 (more generic and with the proper function for stop):
-------------------------------------------------------------------------
ENTITY ssd_game IS
GENERIC (fclk: INTEGER := 50000; --clock frequency in kHz
delay1: INTEGER := 250; --desired long delay in ms
delay2: INTEGER := 40); --desired short delay in ms
PORT (clk, stop: IN BIT;
dout: OUT BIT_VECTOR(6 DOWNTO 0));
END ssd_game;
-------------------------------------------------------------------------
ARCHITECTURE fsm OF ssd_game IS
CONSTANT time1: INTEGER := fclk*delay1; --use 4 for initial simulations
CONSTANT time2: INTEGER := fclk*delay2; --use 2 for initial simulations
TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);
SIGNAL present_state, next_state: states;
--Optional:
--ATTRIBUTE enum_encoding: STRING;
--ATTRIBUTE enum_encoding OF states: TYPE IS "sequential";
SIGNAL delay: INTEGER RANGE 0 TO time1;
BEGIN
-------Lower section of FSM:---------------
PROCESS (clk, stop)
VARIABLE count: INTEGER RANGE 0 TO time1;
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (stop='0') THEN
count := count + 1;
IF (count=delay) THEN
count := 0;
present_state <= next_state;
END IF;
END IF;
END IF;
END PROCESS;
-------Upper section of FSM:---------------
PROCESS (present_state)
BEGIN
CASE present_state IS
WHEN a =>
dout <= "1000000"; --Decimal 64
delay <= time1;
next_state <= ab;
WHEN ab =>
dout <= "1100000"; --Decimal 96
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

delay <= time2;

next_state <= b;
WHEN b =>
dout <= "0100000"; --Decimal 32
delay <= time1;
next_state <= bc;
WHEN bc =>
dout <= "0110000"; --Decimal 48
delay <= time2;
next_state <= c;
WHEN c =>
dout <= "0010000"; --Decimal 16
delay <= time1;
next_state <= cd;
WHEN cd =>
dout <= "0011000"; --Decimal 24
delay <= time2;
next_state <= d;
WHEN d =>
dout <= "0001000"; --Decimal 8
delay <= time1;
next_state <= de;
WHEN de =>
dout <= "0001100"; --Decimal 12
delay <= time2;
next_state <= e;
WHEN e =>
dout <= "0000100"; --Decimal 4
delay <= time1;
next_state <= ef;
WHEN ef =>
dout <= "0000110"; --Decimal 6
delay <= time2;
next_state <= f;
WHEN f =>
dout <= "0000010"; --Decimal 2
delay <= time1;
next_state <= fa;
WHEN fa =>
dout <= "1000010"; --Decimal 66
delay <= time2;
next_state <= a;
END CASE;
END PROCESS;
END fsm;
-----------------------------------------------------------

Simulation results from this code are shown below.

Example 11.6: Overloaded “+” operator

------Package:------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------------------------
PACKAGE my_package IS
 Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

FUNCTION "+" (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;

END my_package;
--------------------------------------------------------------------------
PACKAGE BODY my_package IS
FUNCTION "+" (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE result: STD_LOGIC_VECTOR;
VARIABLE carry: STD_LOGIC;
BEGIN
carry := '0';
FOR i IN a'REVERSE_RANGE LOOP
result(i) := a(i) XOR b(i) XOR carry;
carry := (a(i) AND b(i)) OR (a(i) AND carry) OR (b(i) AND carry);
END LOOP;
RETURN result;
END "+";
END my_package;
--------------------------------------------------------------------------

------Main code (for testing the function):-----------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
------------------------------------------------------
ENTITY add_bit IS
PORT (a: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END add_bit;
------------------------------------------------------
ARCHITECTURE my_arch OF add_bit IS
CONSTANT b: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT c: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
BEGIN
y <= a + b + c; -- overloaded "+" operator
END my_arch;
-------------------------------------------------------