َْ

ِ
ْ‫ ًِْ
َو رْ ُز‬
ِ ْ‫ب زد‬
 ‫َر‬
My Lord! Advance me in Knowledge and true
understanding

MICROPROCESSOR BASED SYSTEM

Lecture3
Dr. Shahrul Naim Sidek
snaim@iiu.edu.my
Hardware Architecture of 68000
Microprocessor (Chapter 7)
Hardware Reliability and Testability
Design for Reliability and Testability
• where are times spent on Embedded µP based system

Task % Total Dev. Time

Hardware Dev 10% - 40%
Software Dev 20% - 50% or more
System Integration 10% - 40%
Test & QA 10% - 50%

Reliability
• reliable design will have long MTBF (Mean Time Between Failures)
and short MTTR (Mean Time to Repair)
• design approach with consideration to components tolerance & the
way h/w failures can affect the system -> increase the reliability
Hardware Reliability and Testability
Why Hardware Fails
• The blunder – obvious errors. Example: wrong connection, specify
wrong gates can be avoided by confirming it through simulation
prototype
• Logic Fan-out – driving logic gates larger than spec. (TTL gate can
feed up to 10 digital gates/devices)
• The stuck at fault – some logic output permanently stuck at 0 or stuck
at 1. Example: some bit on address/data bus grounded due to short
circuit between PCB tracks.
• Timing tolerance – overlooked timing parameters of devices such as
access time of ROM / RAM, gate delays, setup time& hold time
• Faulty IC, Faulty PCB, not enough power etc
Hardware Reliability and Testability
Design for Testability
• Objective: to design µP based systems such that faults can be located
with minimum effort.
• 2 things necessary to achieve testability
• Ability to monitor activity within a µP based systems
• Ability to influence this activity
• A µP based systems should be designed so that as many internal
signals as possible are available off board for monitoring and
influencing.
• May required extra connector to be added to the board for test
purposes. This provides facility for automatic testing.
• May not be possible for low cost, high volume system
Hardware Reliability and Testability
Design for Testability (cont)
• Maximize access to the input & output – provides test points & test input
paths
• Self testing – run self test routine when system is switch on or during
operation. Test main components ROM, RAM, I/O & indicates
success/failure.
• Adopt a modular approach to design – decompose the design into parts
that interact in well-defined, limited ways. System testing can be done
part by part.
• Place “important” devices in sockets – testing/replacing IC easier, but
sockets are less reliable and cost more than ICs!!!
• Avoid using marginal design – never design h/w that operates close to
the guarantee parameters. (tolerance design)
SECTION 7.1-7.4

CPU Spec & Pin Description: General

32-bit Data and Address Registers
16-bit Data Bus
24-bit Address Bus (16MB)
14 Addressing Modes
Memory-Mapped Input/Output
Program Counter
Over 70 Instructions
5 Main Data Types
7 interrupt levels
Clock speeds: 4MHz to 12.5MHz
Synchronous and asynchronous data transfers
CPU Spec & Pin Description: Input / Output
CPU Spec & Pin Description: Input / Output
Vcc, GND and CLK
5V
• Deals with processor power
and clock input
Vcc Vcc
• Operate at 5V +/- 5%
• Dissipate 1.5W (8 Mhz Clock CLK
Clock
Speed) circuit
68000
• Clock has 50% duty cycle
Crystal

Gnd Gnd
CPU Spec & Pin Description: Input / Output
Function Code Output
• This group of signals is used to
FC2 FC1 FC0 Cycle Type (Currently output encoded processor
executing) status.
0 0 0 Reserved • Indicates the current internal
processing state of the 68000
0 0 1 User Data
• These codes are only valid when
0 1 0 User Program AS* signal is active (AS* is low)
0 1 1 Reserved • Ex.: Use 3-to-8 decoder 74LS138
1 0 0 Reserved
AS* 6
1 0 1 Supervisor Data FC 28
0
INTACK*

1 1 0 Supervisor Program FC1 27

FC 26
2
1 1 1 Interrupt acknowledge
Interrupt acknowledge cycle encoder
CPU Spec & Pin Description: Input / Output
4

D0-D7 D0-D7
E, VMA*, VPA*

6800 • Control older peripheral

68000 (8 bits – ex. 6800)
1 Peripheral
A1-A23 2
Peripheral • VPA* (Valid peripheral
add. CS2 address : Input)
AS*
decoder
LDS* • VMA* (Valid memory
address : Output)
E E • E is derived from 10
3
CLK cycles (i.e. 1 E-
VMA* CS1
CLK = 6 lows , 4 highs
VPA* of CLK )
• Synchronous data
transfer
CPU Spec & Pin Description: Input / Output
CPU Spec & Pin Description: Input / Output
RESET* (in/out), HALT* (in/out), BERR* (input)
• Are used for system control
• BERR* (Bus error) – addressed illegal memory location etc
• BERR* Only = start EXCEPTION, TERMINATE bus cycle
• BERR* + HALT* = TERMINATE cycle, buses high-impedance state (do
nothing), until HALT deactivate, RE- RUN previous CYCLE
• RESET*+ HALT*
• as input pins: set both low for a min. 100ms - after power on or to reset
processor
• as output pin: using instruction set, RESET, HALT(output low for 124
clock cycles)
• HALT* anytime by external device – move to high impedance (open state)
CPU Spec & Pin Description: Input / Output
Tristate Signal Levels
+5V
1
Vcc
0
0V

High Low High High Low High

impedance
RESET

HALT
T >= 100ms Execution
begin
CPU Spec & Pin Description: Input / Output
IPL0*, IPL1*, IPL2 * (Input IPL2 IPL1 IPL0 Interrupt
pins) Level
1 1 1 0 (lowest,
• Interrupt control none)

• Used by external circuitry to 1 1 0 1

request encoded priority 1 0 1 2
level of hardware interrupt 1 0 0 3
0 1 1 4
• 0 – No interrupt (all input
0 1 0 5
high), 7 – Highest Priority
(all low) 0 0 1 6
0 0 0 7 (Highest,
non
maskable)
CPU Spec & Pin Description: Input / Output
BR* (in), BG* (out) & BGACK* (in)
• Bus arbitration ctrl– place 68000 in wait state, use h/w controller – to ctrl
bus
Step By Step
1. Requesting device called bus master activates BR* (Bus Request) input.
2. 68000 response to bus master by BG* (Bus Grant) output low (released
control at the end of the current cycle)
3. New bus master assert BGACK *(Bus Grant Ack) to take control. These
condition must be met BEFORE bus master may activate BGACK*.
• BG* active
• AS* inactive (show processor not using the bus)
• DTACK* inactive (show no external device using the bus)
• BGACK* inactive (ensure no other bus master is using the bus)
CPU Spec & Pin Description: Input / Output

Add
A1-A23
bus

68000
1
BR
2 Alternate bus
BG master
3
BGACK

Data
D0-D15
bus
Control
AS, LDS, UDS, DTACK
bus
CPU Spec & Pin Description: Input / Output
BR* (in), BG* (out) & BGACK* (in)
CPU Spec & Pin Description: Input / Output
AS*, R/W*, UDS*, LDS* & DTACK*
• Asynchronous bus control (Asynchronous data transfer) contains 5 signals
• AS, R/W*, UDS*, LDS* – Output
• DTACK* – Input
• AS* (Address Strobe) – signal to indicate valid memory add. exist in add
bus
• R/W* – determine cycle : read or write cycle
• UDS* (Upper Data Strobe) – 8-15bit / LDS* (Lower Data Strobe) – 0-7 bit,
used to gate 8 bit info to/from 68000 bus. Choose which to activate.
• DTACK* (data transfer ack.) used by external circuit to perform
asynchronous data transfer.
• How do we perform sync. data transfer ?????
CPU Spec & Pin Description: Input / Output
A1 through A23, D0 Through D15
• Address and Data busses
• Address bus – A0: UDS, LDS
• A1 – A23 unidirectional (output only)
• D0 through D15 bidirectional
• Except interrupt acknowledge cycle, A1-A3 interrupt level, others high, D0-D7
(transmit interrupt vector number by external device)
CPU Spec & Pin Description: Bus Buffering
• Buffering address and Data Bus

Bidirectional Data Bus Unidirectional add bus

A0

DB15
DB8
DB0

DB7

74LS244

74LS244

74LS244
LS245

LS245
Dir

Dir
EN

EN

EN

EN

EN
D15

LSD
D0

D7

D8

A14

A15
USD
R/W

A1

A6

A7

A22
A23
CPU
CPU Spec & Pin Description:
+5V +/- 5%
Input / Output
D0 – D15
CLK
VCC VCC
Data bus
A1 – A23
Add Bus
FC0
FC1 AS
Processor Status FC2 R/W
UDS Asyn Bus Ctrl
LDS
DTACK
E
68000 Peripheral Ctrl VMA BR

(Old) VPA BG Bus Arbitration Ctrl

BGACK
BERR
RESET IPL0
Sys Ctrl
HALT IPL1 Intrpt Ctrl
Gnd Gnd IPL2
CPU Spec & Pin Description: Summary
Signal Input Output Tristate
CLK

FC0 - FC2


1
E

VMA


0
VPA

BERR

RESET


HALT


IPL0 - IPL2

BR

BG
High Low High High Low High
impedance
BGACK

AS


R/W


USD


LDS


DTACK

A1 - A23


D0 - D15



System Timing: Architecture
3 Bus Architecture Realization
• Asynchronous data transfers
• Involves master-slave transfer. Master = µP, Slave = memory/ I-O
• Master initiates the data transfer, Slave response to it
• Example of an asynchronous read/write cycle from memory
 Asynchronous Data transfer
System Timing: A. µP generates valid memrory add &
3 Bus Architecture Realization assert address strobe (AS*) at B
B. AS* cause memory to place data on
Add
A
data bus
Bus Add Valid
C. Data on data bus becomes valid
AS* D. Memory informs µP about valid data
(from µP) B
E on data bus by DTACK* signal
E. µP reads data on data bus and
Data
C negates it AS* telling memory that it
High
bus Data Valid finishes reading data
Z
F. Memory negates data DTACK* to
complete read cycle
D F
DTACK*
This are fully interlocked hand shake
(From memory)
sequence.
- memory access can be extended until
an acknowledge signal is received.
System Timing: Bus Control
M68000 Asynchronous Bus Control
Address Strobe (AS*)
• three-state signal indicates the info on the address bus is valid address.
Read/Write (R/W*)
• three-state signal defines data bus transfer as read or write cycle. The
R/W* signal relates to the data strobe signals as describes below
Upper and Lower Data Strobes (UDS*, LDS*)
• three-state signal and R/W* control the flow of data on the data bus. Next
table lists the combination of these signals and the corresponding data on
the bus.
• When R/W* is high, the processor reads from the data bus, alternatively
when the R/W* is low, the processor drives the data bus. In 8-bit mode,
UDS* is always forced high and the LDS* signal is used.
System Timing: Bus Control (Cont)
M68000 Asynchronous Bus Control
Data Transfer Acknowledge (DTACK*)
• input signal indicates data transfer is completed.
• when processor recognizes DTACK during read/write cycle, data is
latched/written, and the bus cycle is terminated.

UDS LSD R/W D8-D15 (even byte) D0-D7 (odd byte)

High High - No valid data No valid data
Low Low High Valid data bits 8-15 Valid data bits 0-7
High Low High No valid data Valid data bits 0-7
Low High High Valid data bits 8-15 No valid data
Low Low Low Valid data bits 8-15 Valid data bits 0-7
High Low Low Valid data bits 0-7 Valid data bits 0-7
Low High Low Valid data bits 8-15 Valid data bits 8-15
Study Questions – Chapter 7
No. 2,5,11,13,14,17,18,24,27,28