َْ

ِ
ْ‫ ًِْ
َو رْ ُز‬
ِ ْ‫ب زد‬
 ‫َر‬
My Lord! Advance me in Knowledge and true
understanding

MICROPROCESSOR BASED SYSTEM

Lecture 6 and 7
Dr. Shahrul Naim Sidek
snaim@iiu.edu.my
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Memory System Design
(Chapter 8)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

Section 8.10

DMA (Direct Memory Access)

• DMA is a process in which a device (slave) requests the use of the
master’s buses (address, data and control) for its own use
• In a microprocessor-based system, the master is usually the CPU
• Once the slave device has control of the bus, it can read or write to the
system memory as necessary. When the slave device is finished, it
releases control of the master’s buses, and the system returns to normal
• DMA is used to achieve faster data transfer rates than those attainable with
the CPU
• To perform DMA on the 68000,
three signals are used
• Bus Request (BR*)
• Bus Grant (BG*)
• Bus Grant Acknowledge (BGACK*)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 DMA (Direct Memory Access) cont
Why DMA is faster.
• Consider the problem of writing a block of memory to an output port, one
byte at a time. The following tasks must be performed
• Initialize memory and output port addresses
• Repeat until all bytes are transferred:
• Read byte from memory
• Write byte to output port
• Increment memory address
• Check to see if all bytes transferred
• Wait until output port ready for next byte

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 DMA (Direct Memory Access) cont
Why DMA is faster.
• With this approach, only a fraction of the memory cycles are used for the
actual data transfer
• the speed of the data transfer is much less than the maximum
rate at which data can be read from the memory
• DMA is performed with a device called DMA controller (DMAC), which can
be thought of a very specialized microprocessor, except for
• unlike a data transfer performed by the CPU, no instructions
need to be fetched during the transfer to tell the DMAC how to
perform the transfer
• thus, all memory cycles are available for transferring data

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 DMA (Direct Memory Access) cont
• Ex: Shared video card / Hard disks

Request The Bus

1) Assert Bus Request (BR)
Grant Bus Arbitration
1) Assert Bus Grant (BG)
Acknowledge Bus Mastership
1) External arbitration determines next
bus master
2) Next bus master waits for current
cycle to complete
Terminate Arbitration 3) Next bus master asserts bus grant
1) Negate BG (and wait for BGACK) to acnowledge (BGACK) to become
be negated) new master
4) Bus master negates (BR)

Operate As Bus Master

1) Perform data transfer (Read and
write cycles) according to the same
rules the processor uses

Release Bus Matership

1) Negate BGACK

Rearbitrate or resume processor

operation

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Software Architecture
Chapter 3 and Chapter 4

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

Section 3.1-3.6

M68000: Registers Set

• 8 data registers (D0-D7)
• 8 address registers (A0-A7)
There are TWO A7 registers
User Stack Pointer (USP)
Supervisor Stack Pointer (SSP)
• Program Counter (PC)
• Status Register / Condition Code Register (SR/CCR)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 M68000: Status Condition Register
More significant byte: SR
Only modifiable in supervisor mode
Least significant byte: CCR
For user-level programs
Bit Meaning
Behavior depends on instruction T Tracing for run-time debugging

S Supervisor or User Mode

I System responds to interrupts with a level
higher than I
System byte User byte
15 13 10 9 8 4 3 2 1 0 C Set if a carry or borrow is generated. Cleared
T - S - - I2 I1 I0 - - - X N Z V C otherwise
V Set if a signed overflow occurs. Cleared
Trace Bit Extend otherwise

Supervisor state Negative Z Set if the result is zero. Cleared otherwise

N Set if the result is negative. Cleared
Zero otherwise

Interupt Mask Overflow X Retains information from the carry bit for
multi-precision arithmetic
Carry

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 M68000: Condition Register
Example:
Add the numbers $19 and $70 and show the effect on the CCR bits
The following piece of code performs the operation
MOVE.B #$70,D0
ADD.B #$19,DO
To illustrate the behavior of the CCR we will perform a signed
addition in base 2

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 M68000: Memory Organization
24-bit addresses
16MB can be addressed
3 data widths
BYTE: 8-bit, can be at even or odd address
WORD: 16-bit, must be at x2 address
LONGWORD:32-bit, must be at x4 address
Big-endian order
Words are stored with the lower 8-bits in the higher of
the two storage locations
As opposed to little-endian processors, like the Intel
80x86 family

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Assembly Language: Review Data Representation
Three bases will be used thoroughly
Decimal
32110 = 3×102 + 2×101 + 1×100
Hexadecimal
AB616 = 10×162 + 11×161 + 6×160
Binary
1012 = 1×22 + 0×21 + 1×20
Express the following numbers in base 10
011110
FF0516
10002
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Assembly Language: Review 2s Complement
How to express negative numbers in binary?
Sign-Magnitude:
Use the Most Significant Bit to encode the sign
01112=+710
11112=-710
2s Complement:

* The most commonly used form

Binary number (+510) 0 0 0 0 0 1 0 1
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1s complement 1 1 1 1 1 0 1 0
Add 1 + 1
2s complement (-510) 1 1 1 1 1 0 1 1

Subtraction is made very easy (perform the operation 5-7)

The range of numbers that can be represented is from -2n-1 to +2n-1-1
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Assembly Language: Register Transfer Language
RTL: A notation that describes the micro-processors actions clearly and
Unambiguously.
We’ll use a simplified version,
100 means “#100”
[M(4)] means “contents stored in memory location 4”
[MAR] means “contents stored in MAR”
[M(4)]=100 means “memory location 4 contains #100”
[MAR]=100 means “MAR contains #100”
[PC]←4 means “load number 4 onto PC”
[M(4)]←100+[M(4)] means “add #100 to contents of memory location
4 and save”
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Assembly Language: Programming
Source file : all instruction mnemonics needed to execute a program
Assembler (EASy68k)
Object file : actual binary information specially for the machine

Source file (*.X68)

Assembler (EASy68k)

Listing file (*.L68) S-record file (*.S68)

-original code + code -printable object code
generated by assembler -useful for d/load over serial line

Linker : link several object files to form final object file

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Instruction: Format
Instruction format is
<label> opcode<.field> <operands> <;comments>
<label> pointer to the instruction’s memory location
opcode operation code (i.e., MOVE, ADD)
<.field> defines width of operands (B,W,L)
<operands> data used in the operation
<;comments> for program documentation
Instruction RTL
MOVE.W #100,D0 [D0]←100
MOVE.W 100,D0 [D0]←[M(100)]
EXAMPLES: ADD.W D0,D1 [D1]←[D1]+[D0]
MOVE.W D1,100 [M(100)]←[D1]
data DC.B 20 [data] ←20

Rev 1.0 Microprocessor Based SystemBRA label

(MCT 2219) [PC] ←label SBAH Jul’07
Instruction: Operand
• Operands can be;
registers
constants
memory addresses
• Basic addressing modes (to be expanded);
Dn: data register direct MOVE.L D0, D1
An: address register indirect MOVE.L (A0), D1
#n: immediate MOVE.L #10, D1
n: absolute MOVE.L $08FF00, D1
• Immediate operands can be specified in several formats
Hexadecimal: prefixed by $
Octal: prefixed by @
Decimal: prefixed by & (or nothing)
Binary: prefixed by %
ASCII: within single quotes ‘abc’
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Instruction: First program

Label Operands
Opcode Comments

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Instruction: First program (cont)

Assembler Status

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Instruction: First program (cont)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Instruction: Second program

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Instruction: EASy68K Simulator
On Your Own
Read through the help menu to understand further on the
software.

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07