Laboratory Manual Microprocessor 8085: SL - No. Name of The Experiments No

Laboratory manual
Microprocessor 8085
Electronics Lab
Department of Physics
Gauhati University
Page
Sl.No. Day Name of the Experiments
No.
1 1 Induction to 8085 Microprocessor
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1. INTRODUCTION TO MICROPROCESSOR 8085
Aim: To study the microprocessor 8085
Architecture of 8085 Microprocessor
a) General purpose registers
2
It is an 8 bit register i.e. B, C, D, E, H, L. The combination of 8 bit register is known
as register pair, which can hold 16 bit data. The HL pair is used to act as memory pointer is
accessible to program.
b) Accumulator
It is an 8 bit register which hold one of the data to be processed by ALU and stored
the result of the operation.
c) Program counter (PC)

It is a 16 bit pointer which maintains the address of a byte entered to line stack.
d) Stack pointer (Sp)
It is a 16 bit special purpose register which is used to hold line memory address for
line next instruction to be executed.
e) Arithmetic and logical unit
It carries out arithmetic and logical operation by 8 bit address it uses the accumulator
content as input the ALU result is stored back into accumulator.
f) Temporary register
It is an 8 bit register associated with ALU hold data, entering an operation, used by
the microprocessor and not accessible to programs.
g) Flags
Flag register is a group of fire, individual flip flops line content of line flag register
will change after execution of arithmetic and logic operation. The line states flags are
i) Carry flag (C)

ii) Parity flag (P)
iii) Zero flag (Z)
iv) Auxiliary carry flag (AC)
v) Sign flag (S)
3
h) Timing and control unit
Synchronous all microprocessor, operation with the clock and generator and control
signal from it necessary to communicate between controller and peripherals.
i) Instruction register and decoder
Instruction is fetched from line memory and stored in line instruction register decoder
the stored information.
j) Register Array
These are used to store 8 bit data during execution of some instruction
PIN Description
Address Bus
1. The pins Ao – A15 denote the address bus.
2. They are used for most significant bit
Address / Data Bus

1. AD0 – AD7 constitutes the address / Data bus
2. These pins are used for least significant bit
ALE : (Address Latch Enable)
1. The signal goes high during the first clock cycle and enables the lower order
address bits.
IO / M
1. This distinguishes whether the address is for memory or input.
2. When this pins go high, the address is for an I/O device.
S0 – S1
S0 and S1 are status signal which provides different status and functions.
4
RD
1. This is an active low signal
2. This signal is used to control READ operation of the microprocessor.
WR
1. WR is also an active low signal
2. Controls the write operation of the microprocessor.
HOLD
1. This indicates if any other device is requesting the use of address and data bus.
HLDA
1. HLDA is the acknowledgement signal for HOLD
2. It indicates whether the hold signal is received or not.
INTR
1. INTE is an interrupt request signal
2. IT can be enabled or disabled by using software
INTA
1. Whenever the microprocessor receives interrupt signal
2. It has to be acknowledged.
RST 5.5, 6.5, 7.5

1. These are nothing but the restart interrupts
2. They insert an internal restart junction automatically.
TRAP
1. Trap is the only non-maskable interrupt
2. It cannot be enabled (or) disabled using program.
RESET IN
5
1. This pin resets the program counter to 0 to 1 and results interrupt enable and
HLDA flip flops.
X1, X2
These are the terminals which are connected to external oscillator to produce the
necessary and suitable clock operation.
SID
This pin provides serial input data
SOD
This pin provides serial output data
VCC and VSS

1. VCC is +5V supply pin
2. VSS is ground pin
Pin Diagram and Pin description of 8085
6
INSTRUCTION SETS OF 8085:
7
1. Control
2. Logical
3. Branching
4. Arithmetic
5. Data Transfer
CONTROL INSTRUCTIONS:
Opcode Operand Explanation Description
of
Instruction
NOP none No No operation is performed. The instruction is fetched
operation and decoded. However no operation is executed.
Example: NOP
HLT none Halt and The CPU finishes executing the current instruction and
enter wait halts any further execution. An interrupt or reset is
state necessary to exit from the halt state.
Example: HLT
DI none Disable The interrupt enable flip-flop is reset and all the
interrupts interrupts except the TRAP are disabled. No flags are
affected.
Example: DI
EI none Enable The interrupt enable flip-flop is set and all interrupts
interrupts are enabled. No flags are affected. After a system reset
or the acknowledgement of an interrupt, the interrupt
enable flipflop is reset, thus disabling the interrupts.
This instruction is necessary to reenable the interrupts
(except TRAP).
Example: EI
RIM none Read This is a multipurpose instruction used to read the
interrupt status of interrupts 7.5, 6.5, 5.5 and read serial data
mas input bit. The instruction loads eight bits in the
accumulator with the following interpretations.
Example: RIM
SIM none Set interrupt This is a multipurpose instruction and used to
mask implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output. The instruction interprets the accumulator
contents as follows.
Example: SIM
LOGICAL INSTRUCTIONS:
8
Opcode Operand Explanation of Description
Instruction
CMP R Compare The contents of the operand (register or memory) are
register or M compared with the contents of the accumulator.
M memory with Both contents are preserved . The result of the
accumulator comparison is shown by setting the flags of the PSW
as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M
CPI 8-bit data Compare The second byte (8-bit data) is compared with the
immediate with contents of the accumulator. The values being
accumulator compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW
as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
ANA R Logical AND The contents of the accumulator are logically ANDed
register or with M the contents of the operand (register or
M memory with memory), and the result is placed in the accumulator.
accumulator If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are
modified to reflect the result of the operation. CY is
reset. AC is set.
Example: ANA B or ANA M
ANI 8-bit data Logical AND The contents of the accumulator are logically ANDed
immediate with with the 8-bit data (operand) and the result is placed
accumulator in the accumulator. S, Z, P are modified to reflect the
result of the operation. CY is reset. AC is set.
Example: ANI 86H
XRA R Exclusive OR The contents of the accumulator are Exclusive ORed
modified to reflect the result of the operation. CY and
AC are reset.
Example: XRA B or XRA M
XRI 8-bit data Exclusive OR The contents of the accumulator are Exclusive ORed
result of the operation. CY and AC are reset.
Example: XRI 86H

ORA R Logical OR The contents of the accumulator are logically ORed
9
modified to reflect the result of the operation. CY and
AC are reset.
Example: ORA B or ORA M

ORI 8-bit data Logical OR The contents of the accumulator are logically ORed
result of the operation. CY and AC are reset.
Example: ORI 86H

RLC none Rotate Each binary bit of the accumulator is rotated left by
accumulator one position. Bit D7 is placed in the position of D0 as
left well as in the Carry flag. CY is modified according to
bit D7. S, Z, P, AC are not affected.
Example: RLC
RRC none Rotate Each binary bit of the accumulator is rotated right by
accumulator one position. Bit D0 is placed in the position of D7 as
right well as in the Carry flag. CY is modified according to
bit D0. S, Z, P, AC are not affected.
Example: RRC
RAL none Rotate Each binary bit of the accumulator is rotated left by
accumulator one position through the Carry flag. Bit D7 is placed
left through in the Carry flag, and the Carry flag is placed in the
carry least significant position D0. CY is modified
according to bit D7. S, Z, P, AC are not affected.
Example: RAL
RAR none Rotate Each binary bit of the accumulator is rotated right by
accumulator one position through the Carry flag. Bit D0 is placed
right through in the Carry flag, and the Carry flag is placed in the
carry most significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Example: RAR
CMA none Complement The contents of the accumulator are complemented.
accumulator No flags are affected.
Example: CMA
CMC none Complement The Carry flag is complemented. No other flags are
carry affected.
Example: CMC
STC none Set Carry Set Carry
Example: STC
BRANCHING INSTRUCTIONS:
10
Opcode Operan Explanation Description
d of Instruction
JMP 16-bit Jump The program
address unconditionall sequence is
y transferred to the
memory location
specified by the 16-
bit address given in
the operand.
Example: JMP
2034H or JMP XYZ
Flag 16-bit Jump The program
Opcode Description address conditionally sequence is
Status
transferred to the
JC Jump on Carry CY = 1 memory location
JNC Jump on no Carry CY = 0 specified by the 16-
JP Jump on positive S=0
the operand based
JM Jump on minus S=1 on the specified flag
JZ Jump on zero Z=1 of the PSW as
described below.
JNZ Jump on no zero Z=0
Jump on parity Example: JZ 2034H
JPE P=1 or JZ XYZ
even
JPO Jump on parity odd P = 0
Opcode Description Flag Status 16-bit Unconditional The program
address subroutine call sequence is
CC Call on Carry CY = 1 transferred to the
CNC Call on no Carry CY = 0 memory location
specified by the 16-
CP Call on positive S=0
CM Call on minus S=1 the operand. Before
CZ Call on zero Z=1 the transfer, the
address of the next
CNZ Call on no zero Z=0 instruction after
CPE Call on parity even P = 1 CALL (the contents
of the program
CPO Call on parity odd P = 0 counter) is pushed
onto the stack.
Example: CALL
2034H or CALL
XYZ
RET none Return from The program
subroutine sequence is
unconditionall transferred from the
y subroutine to the
calling program.
11
The two bytes from
the top of the stack
are copied into the
program
counter,and
program execution
begins at the new
address.
Example: RET
Flag none Return from The program
Opcode Description subroutine sequence is
Status
conditionally transferred from the
RC Return on Carry CY = 1 subroutine to the
RNC Return on no Carry CY = 0 calling program
based on the
RP Return on positive S=0
specified flag of the
RM Return on minus S=1 PSW as described
RZ Return on zero Z=1 below. The two
bytes from the top
RNZ Return on no zero Z=0 of the stack are
Return on parity copied into the
RPE P=1 program counter,
even
and program
Return on parity execution begins at
RPO P=0
odd the new address.
Example: RZ
PCHL none Load program The contents of
counter with registers H and L
HL contents are copied into the
program counter.
The contents of H
are placed as the
high-order byte and
the contents of L as
the low-order byte.
Example: PCHL
RST 0-7 Restart The RST instruction
is equivalent to a 1-
byte call instruction
to one of eight
memory locations
depending upon the
number. The
instructions are
generally used in
conjunction with
interrupts and
12
inserted using
external hardware.
However these can
be used as software
instructions in a
program to transfer
program execution
to one of the eight
locations. The
addresses are:
Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four

additional interrupts
and these interrupts
generate RST
instructions
internally and thus
do not require any
external hardware.
These instructions
and their Restart
addresses are:
Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
ARITHMATIC INSTRUCTIONS:
13
Opcode Operand Explanation Description
of Instruction
ADD R Add register or The contents of the operand (register or memory)
memory, to are added to the contents of the accumulator and the
M accumulator result is stored in the accumulator. If the operand is
a memory location, its location is specified by the
contents of the HL registers. All flags are modified
to reflect the result of the addition.
Example: ADD B or ADD M

ADC R Add register to The contents of the operand (register or memory)
accumulator and M the Carry flag are added to the contents of the
M with carry accumulator and the result is stored in the
accumulator. If the operand is a memory location,
its location is specified by the contents of the HL
registers. All flags are modified to reflect the result
of the addition.
Example: ADC B or ADC M

ADI 8-bit Add The 8-bit data (operand) is added to the contents of
data immediate to the accumulator and the result is stored in the
accumulator accumulator. All flags are modified to reflect the
result of the addition.
Example: ADI 45H

ACI 8-bit Add The 8-bit data (operand) and the Carry flag are
data immediate to added to the contents of the accumulator and the
accumulator result is stored in the accumulator. All flags are
with carry modified to reflect the result of the addition.
Example: ACI 45H

LXI Reg. Load register The instruction loads 16-bit data in the register pair
pair, 16- pair immediate designated in the operand.
bit data
Example: LXI H, 2034H or LXI H, XYZ
DAD Reg. Add register The 16-bit contents of the specified register pair are
pair pair to H and L added to the contents of the HL register and the sum
registers is stored in the HL register. The contents of the
source register pair are not altered. If the result is
larger than 16 bits, the CY flag is set. No other flags
are affected.
Example: DAD H
SUB R Subtract The contents of the operand (register or memory )
register or are subtracted from the contents of the accumulator,
M memory from and the result is stored in the accumulator. If the
accumulator operand is a memory location, its location is
specified by the contents of the HL registers. All
flags are modified to reflect the result of the
14
subtraction.
Example: SUB B or SUB M

SBB R Subtract The contents of the operand (register or memory )
source and and M the Borrow flag are subtracted from the
M borrow from contents of the accumulator and the result is placed
accumulator in the accumulator. If the operand is a memory
location, its location is specified by the contents of
the HL registers. All flags are modified to reflect the
result of the subtraction.
Example: SBB B or SBB M

SUI 8-bit Subtract The 8-bit data (operand) is subtracted from the
data immediate contents of the accumulator and the result is stored
from in the accumulator. All flags are modified to reflect
accumulator the result of the subtraction.
Example: SUI 45H

SBI 8-bit Subtract The contents of register H are exchanged with the
data immediate contents of register D, and the contents of register L
from are exchanged with the contents of register E.
accumulator
with borrow Example: XCHG
INR R Increment The contents of the designated register or memory)
register or are incremented by 1 and the result is stored in the
M memory by 1 same place. If the operand is a memory location, its
location is specified by the contents of the HL
registers.
Example: INR B or INR M

INX R Increment The contents of the designated register pair are
register pair by incremented by 1 and the result is stored in the same
1 place.
Example: INX H
DCR R Decrement The contents of the designated register or memory
register or are M decremented by 1 and the result is stored in
M memory by 1 the same place. If the operand is a memory location,
its location is specified by the contents of the HL
registers.
Example: DCR B or DCR M

DCX R Decrement The contents of the designated register pair are
register pair by decremented by 1 and the result is stored in the
1 same place.
Example: DCX H
DAA none Decimal adjust The contents of the accumulator are changed from a
accumulator binary value to two 4-bit binary coded decimal
(BCD) digits. This is the only instruction that uses
15
the auxiliary flag to perform the binary to BCD
conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered
to reflect the results of the operation.
If the value of the low-order 4-bits in the

accumulator is greater than 9 or if AC flag is set, the
instruction adds 6 to the low-order four bits.
If the value of the high-order 4-bits in the

accumulator is greater than 9 or if the Carry flag is
set, the instruction adds 6 to the high-order four bits.
Example: DAA
DATA TRANSFER INSTRUCTIONS:

Opcode Operand Explanation of Description
Instruction
MOV Rd, Rs Copy from This instruction copies the contents of the source
source(Rs) to register into the destination register; the contents
M, Rs destination(Rd) of the source register are not altered. If one of the
operands is a memory location, its location is
Rd, M specified by the contents of the HL registers.
Example: MOV B, C or MOV B, M

MVI Rd, data Move immediate The 8-bit data is stored in the destination register
8-bit or memory. If the operand is a memory location,
M, data its location is specified by the contents of the HL
registers.
Example: MVI B, 57H or MVI M, 57H

LDA 16-bit Load The contents of a memory location, specified by a
address accumulator 16-bit address in the operand, are copied to the
accumulator. The contents of the source are not
altered.
Example: LDA 2034H

LDAX B/D Reg. Load The contents of the designated register pair point
pair accumulator to a memory location. This instruction copies the
indirect contents of that memory location into the
accumulator. The contents of either the register
pair or the memory location are not altered.
Example: LDAX B
LXI Reg. Load register The instruction loads 16-bit data in the register
pair, 16- pair immediate pair designated in the operand.
bit data
Example: LXI H, 2034H or LXI H, XYZ
LHLD 16-bit Load H and L The instruction copies the contents of the
16
address registers direct memory location pointed out by the 16-bit address
into register L and copies the contents of the next
memory location into register H. The contents of
source memory locations are not altered.
Example: LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator are copied into
address the memory location specified by the operand.
This is a 3-byte instruction, the second byte
specifies the low-order address and the third byte
specifies the high-order address.
Example: STA 4350H

STAX Reg. Store The contents of the accumulator are copied into
pair accumulator the memory location specified by the contents of
indirect the operand (register pair). The contents of the
accumulator are not altered.
Example: STAX B
SHLD 16-bit Store H and L The contents of register L are stored into the
address registers direct memory location specified by the 16-bit address
in the operand and the contents of H register are
stored into the next memory location by
incrementing the operand. The contents of
registers HL are not altered. This is a 3-byte
instruction, the second byte specifies the low-
order address and the third byte specifies the high-
order address.
Example: SHLD 2470H

XCHG none Exchange H and The contents of register H are exchanged with the
L with D and E contents of register D, and the contents of register
L are exchanged with the contents of register E.
Example: XCHG
SPHL none Copy H and L The instruction loads the contents of the H and L
registers to the registers into
stack pointer the stack pointer register, the contents of the H
register provide the high-order address and the
contents of the L register provide the low-order
address. The contents of the H
and L registers are not altered.
Example: SPHL
XTHL none Exchange H and The contents of the L register are exchanged with
L with top of the stack location pointed out by the contents of
stack the stack pointer register. The contents of the H
register are exchanged with the next stack location
(SP+1); however, the contents of the stack pointer
17
register are not altered.
Example: XTHL
PUSH Reg. Push register The contents of the register pair designated in the
pair pair onto stack operand are copied onto the stack in the following
sequence. The stack pointer register is
decremented and the contents of the highorder
register (B, D, H, A) are copied into that location.
The stack pointer register is decremented again
and the contents of the low-order register (C, E, L,
flags) are copied to that location.
Example: PUSH B or PUSH A

POP Reg. Pop off stack to The contents of the memory location pointed out
pair register pair by the stack pointer register are copied to the low-
order register (C, E, L, status flags) of the
operand. The stack pointer is incremented by 1
and the contents of that memory location are
copied to the high-order register (B, D, H, A) of
the operand. The stack pointer register is again
incremented by 1.
Example: POP H or POP A

OUT 8-bit Output data from The contents of the accumulator are copied into
port accumulator to a the I/O port specified by the operand.
address port with 8-bit
address Example: OUT F8H
IN 8-bit Input data to The contents of the input port designated in the
port accumulator operand are read and loaded into the accumulator.
address from a port with
8-bit address Example: IN 8CH
18
PROGRAMS:
AIM: ADD TWO NUMBERS
MEMORY LABEL MNEMONICS HEX COMMENT

LOCATION OPCODE OPERAND CODE
8000 MVI A,02H 3E Load 02 in the
8001 02 accumulator
8002 ADI 04H C6 Add 04 with 02
8003 04
8004 STA 8050 32 Store at memory
8005 50 location 8050
8006 80
8007 HLT 76 Stop
Steps for execution of the program:
1. Reset the microprocessor by pressing “RESET”

2. For typing the OPCODE press “Exam Memory”
3. Then type the starting address of the program , i.e. 8000 in this case.
4. Then press “NEXT” and enter the HEX Code for the corresponding OPCODE
5. Then press “NEXT” and enter the HEX Code for the corresponding OPERAND
e.g. enter 3E in the memory location 8000 and 02 in 8001
6. Repeat the steps 4 and 5 up to the end of the program.
7. Then press “NEXT”
8. Then press “RESET”
9. Then press “GO”
10. Then type the starting address of the program , i.e. 8000 in this case
11. Then press “EXECUTE”
13. Then press “Exam Memory”
14. Enter the memory location assigned for the result, i.e. 8050 in this case.
15. Press “NEXT”
19
AIM: SUBTRACT TWO NUMBERS:

8000 MVI A,13H 3E Load 13H in the
8001 13 accumulator
8002 SUI 10H D6 Subtract 10H from 13H
8003 10
8004 STA 8050 32 Store at memory
8005 50 location 8050
8006 80
8007 HLT 76 Stop

3. Then type the starting address of the program, i.e. 8000 in this case.
4. Then press “NEXT” and enter the HEX Code for the corresponding OPCODE.
5. Then press “NEXT” and enter the HEX Code for the corresponding OPERAND.
e.g. enter 3E in the memory location 8000 and 13 in 8001.
14. Enter the memory location assigned for the result, i.e. 8050 in this case.
20
AIM: ADD TWO 8-BIT NUMBERS AND SAVE THE RESULT
8000 LXI H,9000H 21 Load HL
8001 00 pair
8002 90 immediately
with 9000H
8003 MOV A,M 7E Move data
from
memory to
A
8004 INX H 23 Increment
the content
of HL pair
8005 MOV B,M 46 Move data
from
memory to B
8006 ADD B 80 Add the
content of B
with the
content of A
8007 STA 8050 32 Store the
8008 50 result in
8009 80 memory
location
8050
800A HLT 76 Stop

14. Enter the memory location assigned for the result.
21
AIM: ADD TWO 8-BIT NUMBERS AND SAVE THE RESULT AND
CARRY IN TWO CONSECUTIVE MEMORY LOCATIONS:
MEMORY MNEMONICS HEX
LABEL COMMENT
8000 OE
MVI C,00H Move immediately 00H in to C
8001 00
8002 21
8003 LXI H,8000H 00 Load HL pair with 8000H
8004 80
8005 MVI A,M 7E Move the content of memory to A
8006 INX H 23 Increment content of HL pair
8007 MOV B,M 46 Move memory content to B
8008 ADD B 80 Add the content of B with A
8009 D2
Jump to memory location 800D if
800A JNC GO 800D 0D
carry is not zero
800B 90
800C INR C 0C Increment the content of C
800D 32
Store the content of A in memory
800E GO STA 8050H 50
location 8050
800F 80
8010 MOV A,C 79 Move data from C to A
8011 32
Store the content of A in memory
8012 STA 8051H 51
location 8051
8013 80
8014 HLT 76 Stop

22
AIM: ADD FIVE 8-BIT DATA STORED IN FIVE CONSECUTIVE
MEMORY LOCATIONS
LABEL COMMENT
9000 0E
MVI C,00H Initialize C register
9001 00
9002 21
Load memory location with the
9003 LXI H,8000H 00
memory location 8000
9004 80
9005 MVI A,M 7E Move memory content to A
9006 INX H 23 Increment HL pair
9007 MOV B,M 46 Move data from memory to B
9008 ADD B 80 Add the content of B to A
900A MOV B,M 46 Move data from memory to B
900B ADD B 80 Add the content of B to A
900C INX H 23 Increment HL pair
900D MOV B,M 46 Move data from memory to B
900E ADD B 80
900F INX H 23 Increment HL pair
9011 ADD B 80
9014 ADD B 80 Add the content of B to A
9015 D2
9016 JNC GO 9019 19 Jump if carry is not zero
9017 90
9018 INR C 0C Increment the content of C
9019 32
Store the content of A in the
901A GO STA 8050 50
901B 80
901C 79
MOV A,C Move data from C to A
901D 32
901E 32
Store the content of A in the
901F STA 8001H 01
9020 80
9021 HLT 76 Stop

3. Load data in five consecutive memory locations. (e.g. load in 8000 to 8004)
23
24
MULTIPLY TWO 8-BIT NUMBERS AND SAVE THE RESULT AND CARRY IN
TWO CONSECUTIVE MEMORY LOCATIONS:

LABEL COMMENT
9000 XRA A AF Clear A
9001 MOV B,A 47 Move the content of A to B
9002 21
9003 LXI H,8000H 00 Load HL pair with 8000 address
9004 80
Move the content of the memory to
9005 MOV C,M 4E
C
9006 INX H 23 Increment of HL pair
9007 MOV D,M 56 Move the content of memory to D
9008 LOOP1 ADD C 89 Add the content of C to A
Make decrement of the content of
9009 DCR D 15
D
900A C2
LOOP1
900B JNZ 08 Jump if not zero
(9008)
900C 90
900D D2
900E JNC GO 9011 11 Jump if carry is not zero
900F 90
9010 INR B 04 Increment the content of B
9011 32
9012 GO STA 8050H 50 Store in memory location 8050
9013 80
9014 MOV A,B 78 Move the content of B to A
9015 32
9016 STA 8051H 51 Store in the memory location 8051
9017 80
9018 HLT 76 Stop
25

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Laboratory Manual Microprocessor 8085: SL - No. Name of The Experiments No

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Laboratory manual

1. INTRODUCTION TO MICROPROCESSOR 8085

Aim: To study the microprocessor 8085

Architecture of 8085 Microprocessor

a) General purpose registers

c) Program counter (PC)

d) Stack pointer (Sp)

e) Arithmetic and logical unit

i) Carry flag (C)

i) Instruction register and decoder

Address / Data Bus

ALE : (Address Latch Enable)

RST 5.5, 6.5, 7.5

VCC and VSS

2. VSS is ground pin

Pin Diagram and Pin description of 8085

Example: XRI 86H

Example: ORA B or ORA M

Example: ORI 86H

The 8085 has four

Example: ADD B or ADD M

Example: ADC B or ADC M

Example: ADI 45H

Example: ACI 45H

Example: SUB B or SUB M

Example: SBB B or SBB M

Example: SUI 45H

Example: INR B or INR M

Example: DCR B or DCR M

If the value of the low-order 4-bits in the

If the value of the high-order 4-bits in the

DATA TRANSFER INSTRUCTIONS:

Example: MOV B, C or MOV B, M

Example: MVI B, 57H or MVI M, 57H

Example: LDA 2034H

Example: LHLD 2040H

Example: STA 4350H

Example: SHLD 2470H

Example: PUSH B or PUSH A

Example: POP H or POP A

AIM: ADD TWO NUMBERS

MEMORY LABEL MNEMONICS HEX COMMENT

Steps for execution of the program:

1. Reset the microprocessor by pressing “RESET”

MEMORY LABEL MNEMONICS HEX COMMENT

Steps for execution of the program:

1. Reset the microprocessor by pressing “RESET”

Steps for execution of the program:

1. Reset the microprocessor by pressing “RESET”

Steps for execution of the program:

1. Reset the microprocessor by pressing “RESET”

Steps for execution of the program:

1. Reset the microprocessor by pressing “RESET”

MEMORY MNEMONICS HEX

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