Ad9371 2 PDF

Integrated, Dual RF Transceiver
with Observation Path

Data Sheet AD9371
FEATURES FUNCTIONAL BLOCK DIAGRAM
AD9371
Dual differential transmitters (Tx) RX1+ RX1
Dual differential receivers (Rx) RX1– RX2 LPF
DECIMATION,
pFIR,
JESD204B
Observation receiver (ORx) with 2 inputs RX2+ ADC DC OFFSET
QEC,
TUNING,
Sniffer receiver (SnRx) with 3 inputs RX2– LPF RSSI,
ADC OVERLOAD
Tunable range: 300 MHz to 6000 MHz
MICRO-
Tx synthesis bandwidth (BW) to 250 MHz RX_EXTLO+ LO RF
CONTROLLER
GENERATOR SYNTHESIZER
Rx BW: 8 MHz to 100 MHz RX_EXTLO– EXTERNAL
OPTION
Supports frequency division duplex (FDD) and time division TX1+
SPI
TX1 SPI
PORT
duplex (TDD) operation TX1– TX2 LPF
Fully integrated independent fractional-N radio frequency (RF) TX2+ DAC
JESD204B
pFIR,
synthesizers for Tx, Rx, ORx, and clock generation TX2– LPF QEC,
DAC INTERPOLATION
JESD204B digital interface
APPLICATIONS TX_EXTLO+ LO RF
CTRL I/F
TX_EXTLO– GENERATOR SYNTHESIZER
EXTERNAL GPIO
AUXADC
3G/4G micro and macro base stations (BTS) OPTION
AUXDAC
LO
3G/4G multicarrier picocells GENERATOR
DEV_CLK_IN+,
DEV_CLK_IN–
FDD and TDD active antenna systems RF
SYNTHESIZER
Microwave, nonline of sight (NLOS) backhaul systems CLOCK

GENERATOR
OBSERVATION
Rx
ORX1+
GENERAL DESCRIPTION ORX1–
ORX2+
The AD9371 is a highly integrated, wideband RF transceiver ORX2–
offering dual channel transmitters and receivers, integrated
synthesizers, and digital signal processing functions. The IC SNRXA+
SNIFFER
Rx LPF DECIMATION,
pFIR,
delivers a versatile combination of high performance and low SNRXA–
JESD204B
ADC AGC,
SNRXB+ DC OFFSET,
power consumption required by 3G/4G micro and macro BTS SNRXB– LPF QEC,
SNRXC+ TUNING,
equipment in both FDD and TDD applications. The AD9371 SNRXC–
ADC RSSI,
OVERLOAD
operates from 300 MHz to 6000 MHz, covering most of the
14651-001
licensed and unlicensed cellular bands. The IC supports receiver NOTES
1. FOR JESD204B PINS, SEE FIGURE 4.
bandwidths up to 100 MHz. It also supports observation receiver
Figure 1.
and transmit synthesis bandwidths up to 250 MHz to
accommodate digital correction algorithms. The high speed JESD204B interface supports lane rates up to
6144 Mbps. Four lanes are dedicated to the transmitters and four
The transceiver consists of wideband direct conversion signal lanes are dedicated to the receiver and observation receiver channels.
paths with state-of-the-art noise figure and linearity. Each complete
receiver and transmitter subsystem includes dc offset correction, The fully integrated phase-locked loops (PLLs) provide high
quadrature error correction (QEC), and programmable digital performance, low power fractional-N frequency synthesis for
filters, eliminating the need for these functions in the digital the transmitter, the receiver, the observation receiver, and the
baseband. Several auxiliary functions such as an auxiliary analog- clock sections. Careful design and layout techniques provide the
to-digital converter (ADC), auxiliary digital-to-analog converters isolation demanded in high performance base station applications.
(DACs), and general-purpose input/outputs (GPIOs) are integrated All voltage controlled oscillator (VCO) and loop filter components
to provide additional monitoring and control capability. are integrated to minimize the external component count.
An observation receiver channel with two inputs is included to A 1.3 V supply is required to power the core of the AD9371, and
monitor each transmitter output and implement interference a standard 4-wire serial port controls it. Other voltage supplies
mitigation and calibration applications. This channel also connects provide proper digital interface levels and optimize transmitter
to three sniffer receiver inputs that can monitor radio activity in and auxiliary converter performance. The AD9371 is packaged in a
different bands. 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Rev. B Document Feedback

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AD9371 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 5.5 GHz Band .............................................................................. 46
Applications ....................................................................................... 1 Theory of Operation ...................................................................... 54
General Description ......................................................................... 1 Transmitter (Tx) ......................................................................... 54
Functional Block Diagram .............................................................. 1 Receiver (Rx) ............................................................................... 54
Revision History ............................................................................... 2 Observation Receiver (ORx)..................................................... 54
Specifications..................................................................................... 3 Sniffer Receiver (SnRx) ............................................................. 54
Current and Power Consumption Specifications..................... 9 Clock Input.................................................................................. 54
Timing Specifications ................................................................ 10 Synthesizers ................................................................................. 55
Absolute Maximum Ratings.......................................................... 12 Serial Peripheral Interface (SPI) Interface .............................. 55
Reflow Profile .............................................................................. 12 GPIO_x AND GPIO_3P3_x Pins ............................................ 55
Thermal Resistance .................................................................... 12 Auxiliary Converters .................................................................. 55
ESD Caution ................................................................................ 12 JESD204B Data Interface .......................................................... 55
Pin Configuration and Function Descriptions ........................... 13 Power Supply Sequence ............................................................. 56
Typical Performance Characteristics ........................................... 16 JTAG Boundary Scan ................................................................. 56
700 MHz Band ............................................................................ 16 Outline Dimensions ....................................................................... 57
2.6 GHz Band .............................................................................. 26 Ordering Guide .......................................................................... 57
3.5 GHz Band .............................................................................. 36
REVISION HISTORY
3/2017—Rev. A to Rev. B Changes to Figure 105 Caption .................................................... 33
Change to Table 1............................................................................. 6 Changes to Figure 107 Caption .................................................... 34
Deleted Figure 230 through Figure 239; Renumbered Changes to Figure 115 Caption and Figure 116 Caption .......... 35
Sequentially ..................................................................................... 55 Changes to Figure 141 Caption .................................................... 40
Changes to Sniffer Receiver (SnRx) Section ............................... 55 Changes to Figure 164 Caption .................................................... 43
Changes to Figure 166 Caption .................................................... 44
11/2016—Rev. 0 to Rev. A Changes to Figure 174 Caption and Figure 175 ......................... 45
Changes to Table 1 ............................................................................ 6 Changes to Figure 194 and Figure 199 Caption ......................... 49
Changes to Table 2 ............................................................................ 9 Changes to Figure 222 Caption .................................................... 53
Changes to L3, L4 Description Column, Table 6; M3, M4 Changes to Figure 224 Caption .................................................... 54
Description Column, Table 6; and M13, M14 Description Added Figure 230 to Figure 235; Renumbered Sequentially .... 55
Column, Table 6 .............................................................................. 16 Added Figure 236 to Figure 239 ................................................... 56
Changes to Figure 46 Caption....................................................... 23 Added External LO Inputs Section .............................................. 58
Changes to Figure 48 Caption....................................................... 24
Changes to Figure 56 Caption and Figure 57 Caption .............. 25 7/2016—Revision 0: Initial Version
Changes to Figure 82 Caption....................................................... 30
Rev. B | Page 2 of 57
Data Sheet AD9371
SPECIFICATIONS
Electrical characteristics at ambient temperature range, VDDA_SER = 1.3 V, VDDA_DES = 1.3 V, JESD_VTT_DES = 1.3 V, VDDA_1P31 =
1.3 V, VDIG = 1.3 V, VDDA_1P8 = 1.8 V, VDD_IF = 2.5 V, and VDDA_3P3 = 3.3 V; all RF specifications based on measurements that
include printed circuit board (PCB) and matching circuit losses, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS (Tx)
Center Frequency 300 6000 MHz
Tx Large Signal Bandwidth (BW) 100 MHz
Tx Synthesis BW2 250 MHz Wider bandwidth for use in
digital processing algorithms
BW Flatness ±0.5 dB 250 MHz BW, compensated
by programmable finite
infinite response (FIR) filter
±0.15 dB Any 20 MHz BW span,
compensated by
programmable FIR filter
Deviation from Linear Phase 10 Degrees 250 MHz BW
Power Control Range 0 42 dB Increased calibration time,
reduced QEC3, LOL4
performance beyond 20 dB
Power Control Resolution 0.05 dB
ACLR5 (Four Universal Mobile −11.2 dBFS rms, 0 dB RF
Telecommunications System attenuation
(UMTS) Carriers)
700 MHz Local Oscillator (LO) −64 dB
2600 MHz LO −64 dB
3500 MHz LO −63 dB
5500 MHz LO −61 dB
In-Band Noise −155 dBFS6/Hz
Tx to Tx Isolation
700 MHz LO 70 dB
2600 MHz LO 65 dB
3500 MHz LO 65 dB
5500 MHz LO 65 dB
Image Rejection Up to 20 dB RF attenuation,
within large signal BW,
QEC3 active
700 MHz LO 65 dB
2600 MHz LO 65 dB
3500 MHz LO 65 dB
5500 MHz LO 50 dB
Maximum Output Power 0 dBFS, 1 MHz signal input,
50 Ω load, 0 dB RF attenuation
700 MHz LO 7 dBm
2600 MHz LO 7 dBm
3500 MHz LO 6 dBm
5500 MHz LO 4 dBm
Output Third-Order Intercept Point OIP3 −5 dBFS rms, 0 dB RF
attenuation
700 MHz LO 27 dBm
2600 MHz LO 27 dBm
3500 MHz LO 25 dBm
5500 MHz LO 25 dBm
AD9371 Data Sheet
Carrier Leakage After calibration, LOL
correction active, CW7 input
signal, 3 dB RF and 3 dB digital
attenuation, 40 kHz
measurement BW
700 MHz LO −81 dBFS6
Error Vector Magnitude (3GPP EVM Long-term evolution (LTE)
Test Signals) 20 MHz downlink,
5 dB RF attenuation
700 MHz LO −45 dB
2600 MHz LO −39 dB
3500 MHz LO −38.5 dB
5500 MHz LO −37.5 dB
Output Impedance 50 Ω Differential
RECEIVERS (Rx)
Gain Range 0 30 dB
Analog Gain Step 0.5 dB
BW Ripple ±0.5 dB 100 MHz BW, compensated
by programmable FIR filter
±0.2 dB Any 20 MHz span,
compensated by
programmable FIR filter
Rx Bandwidth 8 100 MHz Analog low-pass filter (LPF)
BW is 20 MHz minimum,
programmable FIR BW
configurable over the entire
range
Rx Alias Band Rejection 75 dB Due to digital filters
Maximum Recommended Input −14 dBm Input is a CW7 signal at a 0 dB
Power8 attenuation setting; this level
increases decibel for decibel
with attenuation
Noise Figure NF Maximum Rx gain, at
Rx port, matching losses
de-embedded
700 MHz LO 12 dB
2600 MHz LO 13.5 dB
3500 MHz LO 14 dB
5500 MHz LO 18 dB
Input Third-Order Intercept Point IIP3 Maximum Rx gain, third-
order intermodulation (IM3)
1 MHz offset from LO
700 MHz LO 22 dBm
2600 MHz LO 22 dBm
3500 MHz LO 20 dBm
5500 MHz LO 20 dBm
Input Second-Order Intercept IIP2 Maximum Rx gain, second-
Point order intermodulation (IM2)
1 MHz offset from LO
700 MHz LO 65 dBm
2600 MHz LO 65 dBm
3500 MHz LO 65 dBm
5500 MHz LO 57 dBm
Data Sheet AD9371
Image Rejection QEC3 active, within Rx BW
700 MHz LO 75 dB
2600 MHz LO 75 dB
3500 MHz LO 75 dB
5500 MHz LO 75 dB
Input Impedance 200 Ω Differential
Tx1 to Rx1 Signal Isolation and
Tx2 to Rx2 Signal Isolation
700 MHz LO 68 dB
2600 MHz LO 68 dB
3500 MHz LO 62 dB
5500 MHz LO 60 dB
Tx1 to Rx2 Signal Isolation and
Tx2 to Rx1 Signal Isolation
700 MHz LO 70 dB
2600 MHz LO 70 dB
3500 MHz LO 62 dB
5500 MHz LO 60 dB
Rx1 to Rx2 Signal Isolation
700 MHz LO 60 dB
2600 MHz LO 60 dB
3500 MHz LO 60 dB
5500 MHz LO 60 dB
Rx Band Spurs Referenced to −95 dBm No more than one spur at
RF Input at Maximum Gain this level per 10 MHz of Rx
BW; excludes harmonics of
the reference clock
Rx LO Leakage at Rx Input at Leakage decreases decibel
Maximum Gain for decibel with attenuation
for first 12 dB
700 MHz LO −65 dBm
OBSERVATION RECEIVER (ORx)
Gain Range 0 18 dB
Analog Gain Step 1 dB
BW Ripple ±0.5 dB 250 MHz RF BW, compensated
Deviation from Linear Phase 10 Degrees 250 MHz RF BW
ORx Bandwidth 250 MHz
ORx Alias Band Rejection 60 dB Due to digital filters
Maximum Recommended Input −13 dBm Input is a CW7 signal at 0 dB
Power8 attenuation setting; this level
increases decibel for decibel
with attenuation
Signal-to-Noise Ratio9 SNR Maximum gain at ORx port
700 MHz LO 60 dB
2600 MHz LO 60 dB
3500 MHz LO 60 dB
5500 MHz LO 59 dB 200 MHz BW, 245.76 MSPS
AD9371 Data Sheet
Input Third-Order Intercept Point IIP3 Maximum ORx gain,
IM3 1 MHz offset from LO
700 MHz LO 22 dBm
2600 MHz LO 22 dBm
3500 MHz LO 18 dBm
5500 MHz LO 18 dBm
Input Second-Order Intercept IIP2 Maximum ORx gain, IM2
Point 1 MHz offset from LO
700 MHz LO 65 dBm
2600 MHz LO 65 dBm
3500 MHz LO 65 dBm
5500 MHz LO 60 dBm
Image Rejection After online tone calibration
700 MHz LO 65 dB
2600 MHz LO 65 dB
3500 MHz LO 65 dB
5500 MHz LO 65 dB
Tx1 to ORx1 Signal and Tx2 to
ORx2 Signal Isolation
700 MHz LO 70 dB
2600 MHz LO 70 dB
3500 MHz LO 70 dB
5500 MHz LO 70 dB
Tx1 to ORx2 Signal and Tx2 to
ORx1 Signal Isolation
700 MHz LO 70 dB
2600 MHz LO 70 dB
3500 MHz LO 70 dB
5500 MHz LO 70 dB
SNIFFER RECEIVER (SnRx)
Gain Range 0 52 dB
Analog Gain Step 1 dB
BW Ripple ±0.5 dB 20 MHz RF BW, compensated
Rx Bandwidth 20 MHz
Rx Alias Band Rejection 60 dB Due to digital filters
Maximum Recommended Input −26 dBm Input is a CW7 signal at 0 dB
Power8 attenuation setting
Noise Figure NF Maximum gain at
SnRx port, matching losses
de-embedded, gain control
limited to the first 20 steps
700 MHz LO 5 dB
2600 MHz LO 5 dB
3500 MHz LO 7 dB
Input Third-Order Intercept Point IIP3 Maximum gain, IM3 1 MHz
offset from LO, gain control
700 MHz LO 1 dBm
2600 MHz LO 1 dBm
3500 MHz LO 1 dBm
Data Sheet AD9371
Input Second-Order Intercept IIP2 Maximum gain, IM2 1 MHz
Point offset from LO, gain control
700 MHz LO 45 dBm
2600 MHz LO 45 dBm
3500 MHz LO 45 dBm
Image Rejection After online tone calibration
700 MHz LO 75 dB
2600 MHz LO 75 dB
3500 MHz LO 75 dB
Tx1 to SnRx Signal and Tx2 to Applies to each SnRx input
SnRx Signal Isolation
700 MHz LO 60 dB
2600 MHz LO 60 dB
3500 MHz LO 60 dB
LO SYNTHESIZER
LO Frequency Step 2.3 Hz 1.5 GHz to 3 GHz, 76.8 MHz
phase frequency detector
(PFD) frequency
LO Spectral Purity −80 dBc Excludes integer boundary
spurs 1 kHz to 100 MHz
Spot Phase Noise
700 MHz LO
10 kHz −104 dBc
100 kHz −107 dBc
1 MHz −133 dBc
2600 MHz LO
10 kHz −93 dBc
100 kHz −97 dBc
1 MHz −123 dBc
3500 MHz LO
10 kHz −91 dBc
100 kHz −97 dBc
1 MHz −123 dBc
5500 MHz LO
10 kHz −98 dBc
100 kHz −100 dBc
1 MHz −110 dBc
Integrated Phase Noise Integrated from 1 kHz to
100 MHz
700 MHz LO 0.20 °rms
2600 MHz LO 0.49 °rms
3500 MHz LO 0.55 °rms
5500 MHz LO 0.75 °rms
EXTERNAL LO INPUT
Input Frequency fEXTLO 600 8000 MHz Input frequency must be 2×
the desired LO frequency
Input Signal Power 0 3 6 dBm 50 Ω matching at the source
AD9371 Data Sheet
REFERENCE CLOCK (DEV_CLK_IN
SIGNAL)
Frequency Range 10 320 MHz
Signal Level 0.3 2.0 V p-p AC-coupled, common-mode
voltage (VCM) = 618 mV; for
best spurious performance,
use a <1 V p-p input clock
AUXILIARY CONVERTERS
ADC
ADC Resolution 12 Bits
Input Voltage
Minimum 0.25 V
Maximum 3.05 V
DAC
DAC Resolution 10 Bits Includes four offset levels
Output Voltage
Minimum 0.5 V Reference voltage (VREF) = 1 V
Maximum 3.0 V VREF = 2.5 V
Drive Capability 10 mA
DIGITAL SPECIFICATIONS (CMOS),
GPIO_x, RX1_ENABLE,
RX2_ENABLE, TX1_ENABLE, TX2
ENABLE, SYNCINBx+,
SYNCOUTB0+, GP_INTERRUPT,
SDIO, SDO, SCLK, CSB, RESET
Logic Inputs
Input Voltage
High Level VDD_IF × VDD_IF V
0.8
Low Level 0 VDD_IF × V
0.2
Input Current
High Level −10 +10 μA
Low Level −10 +10 μA
Logic Outputs
Output Voltage
High Level VDD_IF × V
0.8
Low Level VDD_IF × V
0.2
DIGITAL SPECIFICATIONS (LVDS),
SYSREF_INx, SYNCOUTB0±,
SYNCINBx PAIRS
Logic Inputs
Input Voltage Range 825 1675 mV Each differential input in the
pair
Input Differential Voltage −100 +100 mV
Threshold
Receiver Differential Input 100 Ω Internal termination enabled
Impedance
Data Sheet AD9371
Logic Outputs
Output Voltage
High 1375 mV
Low 1025 mV
Differential 225 mV
Offset 1200 mV
DIGITAL SPECIFICATIONS (CMOS),
GPIO_3P3_x SIGNALS
Logic Inputs
Input Voltage
High Level VDDA_3P3 VDDA_3P3 V
× 0.8
Low Level 0 VDDA_3P3 V
× 0.2
Input Current
High Level −10 +10 μA
Low Level −10 +10 μA
Logic Outputs
Output Voltage
High Level VDDA_3P3 V
× 0.8
Low Level VDDA_3P3 V
× 0.2
1
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2
Synthesis bandwidth (BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation.
3
Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal.
4
Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal.
5
Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel.
6
dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting.
7
Continuous wave (CW) is a single frequency signal.
8
Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard
clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.
9
Signal-to-noise ratio is limited by the baseband quantization noise.
CURRENT AND POWER CONSUMPTION SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Test Conditions / Comments
SUPPLY CHARACTERISTICS
VDDA_1P3 Analog Supplies1 1.267 1.3 1.33 V
VDIG Supply 1.267 1.3 1.33 V
VDDA_1P8 Supply 1.71 1.8 1.89 V
VDD_IF Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range
VDDA_3P3 Supply 3.135 3.3 3.465 V
VDDA_SER, VDDA_DES, 1.14 1.3 1.365 V
JESD_VTT_DES Supplies
POSITIVE SUPPLY CURRENT (Rx MODE) Two Rx channels enabled, Tx upconverter disabled, 100 MHz
Rx BW, 122.88 MSPS data rate
VDDA_1P3 Analog Supplies1 1055 mA
VDIG Supply 625 mA Rx QEC2 enabled, QEC2 engine active
VDD_IF Supply (CMOS and LVDS) 8 mA
VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES, 375 mA
Total Power Dissipation 2.70 W
AD9371 Data Sheet
Parameter Min Typ Max Unit Test Conditions / Comments
POSITIVE SUPPLY CURRENT (Tx MODE) Two Tx channels enabled, Rx downconverter disabled, 200 MHz
Tx BW, 245.76 MSPS data rate (ORx disabled)
VDIG Supply 410 mA Tx QEC2 active
VDDA_1P8 Supply Full-scale CW3
405 mA Tx RF attenuation = 0 dB,
80 mA Tx RF attenuation = 15 dB
VDD_IF Supply 8 mA
Total Power Dissipation Typical supply voltages, Tx QEC2 active
3.70 W Tx RF attenuation = 0 dB
POSITIVE SUPPLY CURRENT (FDD MODE), 100 MHz Rx BW, 122.88 MSPS data rate; 200 MHz Tx BW,
2× Rx, 2× Tx, ORx ACTIVE 245.76 MSPS data rate; 200 MHz ORx BW, 245.76 MSPS data rate
VDIG Supply 1080 mA Tx QEC2 active
VDDA_1P8 Supply Full-scale CW3
VDD_IF Supply 8 mA
Total Power Dissipation Typical supply voltages, Tx QEC2 active
MAXIMUM OPERATING JUNCTION 110 °C Device designed for 10-year lifetime when operating at
TEMPERATURE maximum junction temperature
1
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2
QEC is the system for minimizing quadrature images of a desired signal.
3
Continuous wave (CW) is a single frequency signal.
TIMING SPECIFICATIONS
Table 3.
SERIAL PERIPHERAL INTERFACE (SPI) TIMING
SCLK Period tCP 20 ns
SCLK Pulse Width tMP 10 ns
CSB Setup to First SCLK Rising Edge tSC 3 ns
Last SCLK Falling Edge to CSB Hold tHC 0 ns
SDIO Data Input Setup to SCLK tS 2 ns
SDIO Data Input Hold to SCLK tH 0 ns
SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) tCO 3 8 ns
Bus Turnaround Time After Baseband Processor (BBP) Drives tHZM tH tCO ns
Last Address Bit
Bus Turnaround Time After AD9371 Drives Last Address Bit tHZS 0 tCO ns
DIGITAL TIMING
TXx_ENABLE Pulse Width 10 μs
RXx_ENABLE Pulse Width 10 μs
Data Sheet AD9371
JESD204B DATA OUTPUT TIMING
Unit Interval UI 162.76 1627.6 ps
Data Rate per Channel (Nonreturn to Zero (NRZ)) 614.4 6144 Mbps
Rise Time tR 24 35 ps 20% to 80% in 100 Ω load
Fall Time tF 24 35 ps 20% to 80% in 100 Ω load
Output Common-Mode Voltage VCM 0 1.8 V AC-coupled
Termination Voltage (VTT) = 1.2 V 735 1135 mV DC-coupled
Differential Output Voltage VDIFF 360 466 770 mV
Short-Circuit Current IDSHORT −100 +100 mA
Differential Termination Impedance ZRDIFF 80 100 120 Ω
Total Jitter 17 48.8 ps Bit error rate (BER) = 10−15
Uncorrelated Bounded High Probability Jitter UBHPJ 1.2 24.4 ps
Duty-Cycle Distortion DCD 3 8.1 ps
SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal tS 2.5 ns See Figure 2 and Figure 3
SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal tH −1.5 ns See Figure 2 and Figure 3
JESD204B DATA INPUT TIMING
Unit Interval UI 162.76 1627.6 ps
Data Rate per Channel (NRZ) 614.4 6144 Mbps
Input Common-Mode Voltage VCM 0.05 1.85 V AC-coupled
VTT = 1.2 V 720 1200 mV DC-coupled
Differential Input Voltage VDIFF 125 750 mV
VTT Source Impedance ZTT 1.2 30 Ω
Differential Termination Impedance ZRDIFF 80 106 120 Ω
VTT
AC-Coupled 1.27 1.33 V
DC-Coupled 1.14 1.26 V
Timing Diagrams
DEV_CLK_IN DELAY
AT DEVICE PINS IN REFERENCE TO SYSREF AT DIGITAL CORE
tS tS
t'H t'H
tH tH t'S
DEV_CLK_IN
14651-002
tH = –1.5ns t'H = +0.5ns

tS = +2.5ns CLK DELAY = 2ns t'S = +0.5ns
Figure 2. SYSREF_IN Signal Setup and Hold Timing

tS tS tS tS
tH tH tH tH
DEV_CLK_IN
SYSREF_IN
14651-003
tH = –1.5ns
VALID SYSREF_IN INVALID SYSREF_IN tS = +2.5ns
Figure 3. SYSREF_IN Signal Setup and Hold Timing Examples Relative to DEV_CLK_IN Signal
AD9371 Data Sheet
ABSOLUTE MAXIMUM RATINGS

REFLOW PROFILE
Table 4.
Parameter Rating The AD9371 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
VDDA_1P31 to VSSA −0.3 V to +1.4 V
temperature is 260°C.
VDDA_SER, VDDA_DES, and −0.3 V to +1.4 V
JESD_VTT_DES to VSSA THERMAL RESISTANCE
VDIG to VSSD −0.3 V to +1.4 V
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
VDD_IF to VSSA −0.3 V to +3.0 V
design is required.
Logic Inputs and Outputs to VSSD −0.3 V to VDD_IF + 0.3 V Table 5. Thermal Resistance
JESD204B Logic Outputs to VSSA −0.3 V to VDDA_SER Airflow
JESD204B Logic Inputs to VSSA −0.3 V to VDDA_DES Package Velocity1 (m/sec) θJA2, 3 (°C/W) θJC2, 4 (°C/W)
Input Current to Any Pin Except ±10 mA BC-196-12
Supplies JEDEC5 0.0 20.5 0.05
Maximum Input Power into RF Ports 23 dBm (peak) 1.0 18.5 N/A6
(Excluding Sniffer Receiver Inputs)
2.5 17.2 N/A6
Maximum Input Power into SNRXA±, 2 dBm (peak)
10-Layer PCB 0.0 14.1 0.05
SNRXB±, and SNRXC±
1.0 12.4 N/A6
Maximum Junction Temperature (TJ MAX) 110°C
2.5 11.6 N/A6
Operating Temperature Range −40°C to +85°C
1
Storage Temperature Range −65°C to +150°C Power dissipation is 3.0 W for all test cases.
2
Per JEDEC JESD51-7 for JEDEC JESD51-5 2S2P test board.
3
1
VDDA_1P3 refers to all analog 1.3 V supplies: VDDA_BB, VDDA_CLKSYNTH, Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
4
VDDA_TXLO, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_RXRF, Per MIL-STD 883, Method 1012.1.
5
VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, JEDEC entries refer to the JEDEC JESD51-9 (high K thermal test board).
6
VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. N/A means not applicable.
Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a ESD CAUTION
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet AD9371
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9371
TOP VIEW
(Not to Scale)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VSSA ORX2+ ORX2– VSSA RX2+ RX2– VSSA VSSA RX1+ RX1– VSSA ORX1+ ORX1– VSSA
A
VDDA_RXRF VSSA VSSA VSSA VSSA VSSA RX_EXTLO– RX_EXTLO+ VSSA VSSA VSSA VSSA VSSA VDDA_3P3
B
VSNRX_ VDDA_ VDDA_ VRX_

GPIO_3P3_0 GPIO_3P3_1 VSSA VDDA_RXLO VSSA VSSA AUXADC_1 AUXADC_2 GPIO_3P3_9 RBIAS
C VCO_LDO SNRXVCO RXVCO VCO_LDO
GPIO_3P3_3 SNRXC– SNRXB– SNRXA– GPIO_3P3_5 VSSA VSSA VSSA VSSA VDDA_1P8 AUXADC_3 GPIO_3P3_7 GPIO_3P3_8 GPIO_3P3_10
D
DEV_ DEV_
GPIO_3P3_4 SNRXC+ SNRXB+ SNRXA+ VDDA_BB VSSA VSSA VSSA TX_EXTLO– TX_EXTLO+ AUXADC_0 GPIO_3P3_6
E CLK_IN+ CLK_IN–
VDDA_ VTX_
GPIO_3P3_2 VDDA_RXTX VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA_TXLO GPIO_3P3_11
F TXVCO VCO_LDO
VDDA_ VDDA_ VDDA_ VDDA_ VDDA_

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA
G CALPLL CLKSYNTH SNRXSYNTH TXSYNTH RXSYNTH
TX2– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1+
H
GP_
TX2+ VSSA GPIO_18 RESET TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1–
J INTERRUPT
VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CSB GPIO_14 GPIO_9 VSSA VSSA
K
VSSA VSSA SYNCINB1– SYNCINB1+ GPIO_6 GPIO_7 VSSD VDIG VDIG VSSD GPIO_15 GPIO_8 VSSA VSSA
L
VCLK_ RX1_ TX1_ RX2_ TX2_

VSSA SYNCINB0– SYNCINB0+ VSSA GPIO_17 GPIO_16 VDD_IF SYNCOUTB0+ SYNCOUTB0–
M VCO_LDO ENABLE ENABLE ENABLE ENABLE
VDDA_CLK VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA_SER VDDA_DES SERDIN2– SERDIN2+ SERDIN3– SERDIN3+ VSSA
N
JESD_VTT_
VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA_SER VSSA SERDIN0– SERDIN0+ SERDIN1– SERDIN1+
P DES
14651-004
ANALOG DIGITAL DC POWER GROUND
INPUT/OUTPUT INPUT/OUTPUT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions

Pin No. Type1 Mnemonic Description
A1, A4, A7, A8, A11, A14, B2 to B6, I VSSA Analog ground.
B9 to B13, C5, C9, C10, D6 to D9,
E6, E9, E10, F3 to F10, G1 to G3, G5,
G10 to G14, H2 to H10, H13, J2, J13,
K1, K2, K13, K14, L1, L2, L13, L14,
M2, M9, N2, N7, N14, P1, P2, P3, P10
A2, A3 I ORX2+, ORX2− Differential Input for Observation Receiver 2. Do not
connect if these pins are unused.
A5, A6 I RX2+, RX2− Differential Input for Receiver 2. Do not connect if these pins
are unused.
A9, A10 I RX1+, RX1− Differential Input for Receiver 1. Do not connect if these pins
are unused.
AD9371 Data Sheet
A12, A13 I ORX1+, ORX1− Differential Input for Observation Receiver 1. Do not
connect if these pins are unused.
B1 I VDDA_RXRF 1.3 V Supply Input.
B7, B8 I/O RX_EXTLO−, RX_EXTLO+ Differential Rx External LO Input/Output. If used for
external LO, the input frequency must be 2× the desired
carrier frequency. Do not connect if these pins are unused.
B14 I VDDA_3P3 Supply Voltage for GPIO_3P3_x.
C1, C2, C13, D1, D5, D12 to D14, I/O GPIO_3P3_0 to GPIO_3P3_11 General-Purpose Inputs and Outputs Referenced to 3.3 V
E1, E14, F1, F14 Supply. See Figure 4 to match the ball location to the
GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also
function as auxiliary DAC outputs.
C3 O VSNRX_VCO_LDO Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 μF
capacitor.
C4 I VDDA_SNRXVCO 1.3 V Supply Input for Sniffer VCO Low Dropout (LDO)
Regulator.
C6 I VDDA_RXLO 1.3 V Supply for the Rx Synthesizer LO Generator. This pin
is sensitive to aggressors.
C7 I VDDA_RXVCO 1.3 V Supply Input for Receiver VCO LDO Regulator.
C8 O VRX_VCO_LDO Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 μF
capacitor.
C11 I AUXADC_1 Auxiliary ADC 1 Input Pin.
C12 I AUXADC_2 Auxiliary ADC 2 Input Pin.
C14 N/A RBIAS Bias Resistor Connection. This pin generates an internal
current based on an external 1% resistor. Connect a
14.3 kΩ resistor between this pin and ground (VSSA).
D2, E2 I SNRXC−, SNRXC+ Differential Input for Sniffer Receiver Input C. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
D3, E3 I SNRXB−, SNRXB+ Differential Input for Sniffer Receiver Input B. If these pins are
D4, E4 I SNRXA−, SNRXA+ Differential Input for Sniffer Receiver Input A. If these pins are
D10 I VDDA_1P8 1.8 V Tx Supply.
D11 I AUXADC_3 Auxiliary ADC 3 Input Pin.
E5 I VDDA_BB 1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs.
E7, E8 I DEV_CLK_IN+, DEV_CLK_IN− Device Clock Differential Input.
E11, E12 I/O TX_EXTLO−, TX_EXTLO+ Differential Tx External LO Input/Output. If these pins are
used for the external LO, the input frequency must be 2×
the desired carrier frequency. Do not connect if these pins
are unused.
E13 I AUXADC_0 Auxiliary ADC 0 Input Pin.
F2 I VDDA_RXTX 1.3 V Supply Input for Tx/Rx Baseband Circuits,
Transimpedance Amplifier (TIA), Tx Transconductance (Gm),
Baseband Filters, and Auxiliary DACs.
F11 I VDDA_TXVCO 1.3 V Supply Input for Transmitter VCO LDO Regulator.
F12 I VDDA_TXLO 1.3 V Supply for the Tx Synthesizer LO Generator. This pin is
sensitive to aggressors.
F13 O VTX_VCO_LDO Transmitter VCO LDO 1.1 V Output. Bypass this pin with a
1 μF capacitor.
G4 I VDDA_CALPLL 1.3 V Supply Input for Calibration PLL Circuits. Use a
separate trace on the PCB back to a common supply point.
G6 I VDDA_CLKSYNTH 1.3 V Clock Synthesizer Supply Input. This pin is sensitive
to aggressors.
G7 I VDDA_SNRXSYNTH 1.3 V Sniffer Rx Synthesizer Supply Input. This pin is
sensitive to aggressors.
G8 I VDDA_TXSYNTH 1.3 V Tx Synthesizer Supply Input. This pin is sensitive to
aggressors.
G9 I VDDA_RXSYNTH 1.3 V Rx Synthesizer Supply Input. This pin is sensitive to
aggressors.
Data Sheet AD9371
H1, J1 O TX2−, TX2+ Differential Output for Transmitter 2.
H11, H12, J3, J7, J8, J11, J12, K5 to K8, I/O GPIO_0 to GPIO_18 General-Purpose Inputs and Outputs Referenced to
K11, K12, L5, L6, L11, L12, M10, M11 VDD_IF. See Figure 4 to match the ball location to the
GPIO_x signal name.
H14, J14 O TX1+, TX1− Differential Output for Transmitter 1.
J4 I RESET Active Low Chip Reset.
J5 O GP_INTERRUPT General-Purpose Interrupt Signal.
J6 I TEST Test Pin Used for JTAG Boundary Scan. Ground this pin if
unused.
J9 I/O SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire
Mode.
J10 O SDO Serial Data Output.
K3, K4 I SYSREF_IN+, SYSREF_IN− LVDS SYSREF Clock Inputs for the JESD204B Interface.
K9 I SCLK Serial Data Bus Clock.
K10 I CSB Serial Data Bus Chip Select. Active low.
L3, L4 I SYNCINB1−, SYNCINB1+ LVDS Sync Signal Associated with ORx/Sniffer Channel
Data on the JESD204B Interface. Alternatively, these pins
can be set to a CMOS input using SYNCINB1+ as the input
and connecting SYNCINB1− with a 1 kΩ resistor to GND.
L7, L10 I VSSD Digital Ground.
L8, L9 I VDIG 1.3 V Digital Core Supply. Use a separate trace on the PCB
back to a common supply point.
M1 O VCLK_VCO_LDO Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 μF
capacitor.
M3, M4 I SYNCINB0−, SYNCINB0+ LVDS Sync Signal Associated with Rx Channel Data on the
JESD204B Interface. Alternatively, these pins can be set to
a CMOS input using SYNCINB0+ as the input and
connecting SYNCINB0− with a 1 kΩ resistor to GND.
M5 I RX1_ENABLE Enables Rx Channel 1 Signal Path.
M6 I TX1_ENABLE Enables Tx Channel 1 Signal Path.
M7 I RX2_ENABLE Enables Rx Channel 2 Signal Path.
M8 I TX2_ENABLE Enables Tx Channel 2 Signal Path.
M12 I VDD_IF CMOS/LVDS Interface Supply.
M13, M14 O SYNCOUTB0+, SYNCOUTB0− LVDS Sync Signal Associated with Transmitter Channel
Data on the JESD Interface. Alternatively, these pins can be
set to a CMOS output using SYNCOUTB0+ as the output
while leaving SYNCOUTB0− floating.
N1 I VDDA_CLK 1.3 V Clock Supply Input.
N3, N4 O SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. This
JESD204B lane can be used by the receiver data or by the
sniffer/observation receiver data.
N5, N6 O SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. This JESD204B lane can be
used by the receiver data or by the sniffer/observation
receiver data.
N8, P8 I VDDA_SER JESD204B 1.3 V Serializer Supply Input.
N9 I VDDA_DES JESD204B 1.3 V Deserializer Supply Input.
N10, N11 I SERDIN2−, SERDIN2+ RF CML Differential Input 2.
N12, N13 I SERDIN3−, SERDIN3+ RF CML Differential Input 3.
P4, P5 O SERDOUT1−, SERDOUT1+ RF CML Differential Output 1. This JESD204B lane can be
used by receiver data or by sniffer/observation receiver data.
P6, P7 O SERDOUT0−, SERDOUT0+ RF CML Differential Output 0. This JESD204B lane can be
used by receiver data or by sniffer/observation receiver data.
P9 I JESD_VTT_DES JESD204B Deserializer Termination Supply Input.
P11, P12 I SERDIN0−, SERDIN0+ RF CML Differential Input 0.
P13, P14 I SERDIN1−, SERDIN1+ RF CML Differential Input 1.
1
I is input, O is output, I/O is input/output, and N/A is not applicable.
AD9371 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS

700 MHz BAND
Temperature settings refer to the die temperature. The die temperature is 40°C for single trace plots.
–30 100
90
–40 +110°C
+40°C 80
RECEIVER LO LEAKAGE (dBm)
–40°C
–50
RECEIVER IIP2 (dBm)

70
–60 60
–70 50
40
–80
30
–90 +110°C
20 +40°C
–40°C
–100 10
14651-308
–110
14651-305
0 3 6 9 12 15
300 400 500 600 700 800 900 1000
RECEIVER LO FREQUENCY (MHz) f1 OFFSET FREQUENCY (MHz)
Figure 5. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, Figure 8. Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO, 0 dB Attenuation,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate 20 MHz RF Bandwidth, f2 = f1 + 1 MHz, 30.72 MSPS Sample Rate
45 100
40 90
+110°C
80
RECEIVER NOISE FIGURE (dB)
35 +40°C
–40°C
RECEIVER IIP2 (dBm)
70
30
60
25
50
20
40 f2 – f1, +110°C
f2 – f1, +40°C
15 f2 – f1, –40°C
30
f2 + f1, +110°C
10 20 f2 + f1, +40°C
f2 + f1, –40°C
5 10
0 0
14651-309
14651-306
0 3 6 9 12 15 4 6 8 10 12
RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)
Figure 6. Receiver Noise Figure vs. Receiver Attenuation, 700 MHz LO, Figure 9. Receiver IIP2 vs. Intermodulation Frequency, 900 MHz LO,
20 MHz Bandwidth, 30.72 MSPS Sample Rate, 20 MHz Integration Bandwidth 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
(Includes 1 dB Matching Circuit Loss)
30 40
+110°C 35
25 +40°C
–40°C 30
RECEIVER IIP3 (dBm)
20
25
15 20
15 +110°C
10 +40°C
10 –40°C
5 5
0
14651-310
0
14651-307
0 3 6 9 12 15
300 400 500 600 700 800 900 1000
f1 OFFSET FREQUENCY (MHz)
RECEIVER LO FREQUENCY (MHz)
Figure 7. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Figure 10. Receiver IIP3 vs. F1 Offset Frequency, 900 MHz LO,
Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate, 20 MHz 0 dB Attenuation, 20 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,
Integration Bandwidth (Includes 1 dB Matching Circuit Loss) 30.72 MSPS Sample Rate
Data Sheet AD9371
40 –40
+110°C
35 –50 +40°C
–40°C
RECEIVER DC OFFSET (dBFS)

30
–60
RECEIVER IIP3 (dBm)
25
–70
20
–80
15
f2 – 2f1, +110°C
f2 – 2f1, +40°C –90
10 f2 – 2f1, –40°C
f2 + 2f1, +110°C
f2 + 2f1, +40°C –100
5 f2 + 2f1, –40°C
0 –110
14651-314
14651-311
4 6 8 10 12 0 5 10 15 20 25 30
INTERMODULATION FREQUENCY (MHz) RECEIVER ATTENUATION (dB)
Figure 11. Receiver IIP3 vs. Intermodulation Frequency, 900 MHz LO, Figure 14. Receiver DC Offset vs. Receiver Attenuation, 800 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
0 –40
–10 +110°C +110°C

+40°C –50 +40°C
–20 –40°C –40°C
–30
RECEIVER IMAGE (dBc)
–60
RECEIVER HD2 (dBc)

–40
–70
–50
–60
–80
–70
–80 –90
–90
–100
–100
–110 –110
14651-312
14651-315
0 5 10 15 20 25 30 0 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)
Figure 12. Receiver Image vs. Receiver Attenuation, 800 MHz LO, Continuous Figure 15. Receiver HD2 vs. Receiver Attenuation, 800 MHz LO, CW Signal
Wave (CW) Signal 3 MHz Offset, 20 MHz RF Bandwidth, Background 3 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Tracking Calibration (BTC) Active, 30.72 MSPS Sample Rate Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
25 –40
20 +110°C +110°C
–50 +40°C
+40°C
–40°C –40°C
15
–60
RECEIVER GAIN (dB)
RECEIVER HD3 (dBc)
10
–70
5
–80
0
–90
–5
–10 –100
–15 –110
14651-313
14651-316
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 13. Receiver Gain vs. Receiver Attenuation, 800 MHz LO, CW Signal Figure 16. Receiver HD3 vs. Receiver Attenuation, 800 MHz LO, CW Signal
3 MHz Offset, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate 3 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
AD9371 Data Sheet
0 30
+110°C +110°C
–10 +40°C 25 +40°C

–40°C –40°C
RECEIVER EVM (dB)
–20 20
–30 15
–40 10
–50 5
–60 0
14651-317
14651-320
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –35 –30 –25 –20 –15 –10 –5 0 5 10
RECEIVER INPUT POWER (dBm) OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)
Figure 17. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power, Figure 20. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,
900 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, 703 MHz LO, 901 MHz CW Interferer, NF Integrated Over 7 MHz to 10 MHz,
BTC Active, 30.72 MSPS Sample Rate 20 MHz RF Bandwidth
–20 0
–30 –10 +110°C

+40°C
–40 –20 –40°C
Rx2 TO Rx1 CROSSTALK (dB)
TRANSMITTER IMAGE (dBc)

–50 –30
–60 –40
–70 –50
–80 –60
–90 –70
–100 –80
–110 –90
–120 –100
14651-318
14651-321
300 400 500 600 700 800 900 1000 0 5 10 15 30
RECEIVER LO FREQUENCY (MHz) RF ATTENUATION (dB)
Figure 18. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, Figure 21. Transmitter Image vs. RF Attenuation, 20 MHz RF Bandwidth,
100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO 900 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run with
Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW 10 MHz
Offset from LO, 3 dB Digital Backoff, 122.88 MSPS Sample Rate
30 0
–10 +110°C
25 +110°C +40°C
–20
+40°C –40°C
–40°C
–30
20
–40
15 –50
–60
10
–70
–80
5
–90
0 –100
14651-319
14651-322
–50 –45 –40 –35 –30 –25 –20 –10 –5 0 5 10

CLOSE-IN INTERFERER SIGNAL POWER (dBm) DESIRED OFFSET FREQUENCY (MHz)
Figure 19. Receiver Noise Figure vs. Close-In Interferer Signal Power, Figure 22. Transmitter Image vs. Desired Offset Frequency,
703 MHz LO, 709 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz, 20 MHz RF Bandwidth, 900 MHz LO, 0 dB RF Attenuation, Transmitter
20 MHz RF Bandwidth QEC Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image
Measured with CW Signal, 3 dB Digital Backoff, 122.88 MSPS Sample Rate
Data Sheet AD9371
10 –20
8 –30
6 –40
Tx1 TO Rx1 CROSSTALK (dB)

4 –50
Tx OUTPUT (dBm)
2 –60
0 –70
–2 –80
–4 +110°C –90
+40°C
–6 –40°C –100
–8 –110
–10 –120
14651-323
14651-326
300 400 500 600 700 800 900 1000 300 400 500 600 700 800 900 1000
FREQUENCY (MHz) RECEIVER LO FREQUENCY (MHz)
Figure 23. Tx Output Power, Transmitter QEC, and External LO Leakage Figure 26. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
Tracking Active, 10 MHz CW Offset Signal, 1 MHz Resolution Bandwidth, 20 MHz Receiver RF Bandwidth, 20 MHz Transmitter RF Bandwidth,
122.88 MSPS Sample Rate CW Signal 3 MHz Offset from LO
–60 –20
+110°C –30
–65
TRANSMITTER LO LEAKAGE (dBFS)
+40°C
–40

–40°C
–70
–50
–75
–60
–80 –70
–80
–85
–90
–90
–100
–95
–110
–100 –120
14651-324
14651-327
0 5 10 15 20 300 400 500 600 700 800 900 1000
RF ATTENUATION (dB) RECEIVER LO FREQUENCY (MHz)
Figure 24. Transmitter LO Leakage vs. RF Attenuation, 900 MHz LO, Transmitter Figure 27. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, 20 MHz Receiver RF
QEC and External LO Leakage Tracking Active, CW Signal 5 MHz Offset from LO, Bandwidth, 20 MHz Transmitter RF Bandwidth, CW Signal 3 MHz Offset from LO
6 dB Digital Backoff, 1 MHz Measurement Bandwidth (If Input Power to ORx
Channel Is Not Held Constant, Performance Degrades As Shown in This Plot)
–60 –20
900MHz, +110°C
900MHz, +40°C –30
–65
900MHz, –40°C
600MHz, +110°C –40
Tx2 TO Tx1 CROSSTALK (dB)
–70 600MHz, +40°C

600MHz, –40°C –50
300MHz, +110°C
–75 300MHz, +40°C –60
300MHz, –40°C
–80 –70
–80
–85
–90
–90
–100
–95
–110
–100 –120
14651-325
14651-328
–10 –5 0 5 10 300 400 500 600 700 800 900 1000

OFFSET FREQUENCY (MHz) TRANSMITTER LO FREQUENCY (MHz)
Figure 25. Transmitter LO Leakage vs. Offset Frequency, Figure 28. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
Transmitter QEC and External LO Leakage Tracking Active, 20 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
5 dB Digital Backoff, 1 MHz Measurement Bandwidth
AD9371 Data Sheet
–80 –60
–90 +110°C –70

+40°C
–40°C
TRANSMITTER NOISE (dBm/Hz)
–100
–80
LO PHASE NOISE (dBc)

–110
–90
–120
–100
–130
–110
–140
–120
–150
–130
–160
–170 –140
–180 –150
14651-329
14651-332
0 5 10 15 20 100 1k 10k 100k 1M 10M
RF ATTENUATION (dB) OFFSET FREQUENCY (Hz)
Figure 29. Transmitter Noise vs. RF Attenuation, 800 MHz LO, Figure 32. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
20 MHz Offset Frequency 710 MHz LO
–40 1.0
Tx ADJACENT CHANNEL LEAKAGE RATIO (dBc)
+110°C LOWER
Tx INTEGRATED PHASE NOISE (Degrees)

+40°C LOWER 0.9 +110°C
–45
–40°C LOWER +40°C
+110°C UPPER 0.8 –40°C
–50 +40°C UPPER
–40°C UPPER 0.7
–55
0.6
–60 0.5
0.4
–65
0.3
–70
0.2
–75
0.1
–80 0
14651-330
14651-333
0 4 8 12 16 20 300 400 500 600 700 800 900 1000
RF ATTENUATION (dB) TRANSMITTER LO FREQUENCY (MHz)
Figure 30. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, 900 MHz LO, Figure 33. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, Transmitter 20 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff
QEC and LO Leakage Tracking Active
–40 35
Tx ALTERNATE CHANNEL LEAKAGE RATIO (dBc)
+110°C LOWER
–45 +40°C LOWER
30
–40°C LOWER
+110°C UPPER
TRANSMITTER OIP3 (dBm)
–50 +40°C UPPER 25

–40°C UPPER
–55
20
–60
15
–65
+110°C
10 +40°C
–70 –40°C
–75 5
–80 0
14651-331
14651-334
0 4 8 12 16 20 0 2 4 6 8 10 12 14 16 18 20
RF ATTENUATION (dB) RF ATTENUATION (dB)
Figure 31. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, Figure 34. Transmitter OIP3 vs. RF Attenuation, 800 MHz LO,
900 MHz LO, 20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, 20 MHz RF Bandwidth, f1 = 10 MHz, f2 = 11 MHz, 3 dB Digital Backoff,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active 122.88 MSPS Sample Rate
Data Sheet AD9371
0 0
–10 –10 +110°C

+40°C
–20 –20 –40°C
TRANSMITTER HD2 (dBc)

–30 –30
Tx OUTPUT (dBm)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
14651-335
14651-338
700 725 750 775 800 825 850 875 900 0 5 10 15 20 25 30
FREQUENCY (MHz) RF ATTENUATION (dB)
Figure 35. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, Figure 38. Transmitter HD2 vs. RF Attenuation, 800 MHz LO,
20 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active, 810 MHz CW Desired Signal, 20 MHz RF Bandwidth,
LTE 10 MHz Signal, 800 MHz LO, 1 MHz Resolution Bandwidth, 122.88 MSPS Sample Rate
122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded
0 0
–10
–10 +110°C
–20 +40°C
–20 –40°C
–30 TRANSMITTER HD3 (dBc)
Tx OUTPUT (dBm)
–30
–40
–50 –40
–60
–50
–70
–60
–80
–70
–90
–100 –80
14651-336
14651-339
300 400 500 600 700 800 900 1000 1100 1200 1300 0 5 10 15 20
–20 10
TRANSMITTER OUTPUT POWER (dBm)
+110°C +110°C
–25 +40°C 5 +40°C
–40°C –40°C
TRANSMITTER EVM (dB)
–30 0
–35 –5
–40 –10
–45 –15
–50 –20
14651-337
14651-340
0 4 8 12 16 20 0 5 10 15 20
Figure 37. Transmitter EVM vs. RF Attenuation, 900 MHz LO, Figure 40. Transmitter Output Power vs. RF Attenuation, 800 MHz LO,
Transmitter LO Leakage and Transmitter QEC Tracking Active, 20 MHz RF 810 MHz CW Desired Signal, 20 MHz RF Bandwidth,
Bandwidth, LTE 20 MHz Downlink Signal, 122.88 MSPS Sample Rate 122.88 MSPS Sample Rate
AD9371 Data Sheet
0.10 30
OBSERVATION RECEIVER NOISE FIGURE (dB)

0.08 +110°C
+110°C
Tx ATTENUATION STEP ERROR (dB)
+40°C 25
0.06 –40°C +40°C
–40°C
0.04
20
0.02
0 15
–0.02
10
–0.04
–0.06
5
–0.08
–0.10 0
14651-341
14651-344
0 5 10 15 20 25 30 300 400 500 600 700 800 900 1000
RF ATTENUATION (dB) OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 41. Tx Attenuation Step Error vs. RF Attenuation, 800 MHz LO, Figure 44. Observation Receiver Noise Figure vs. Observation Receiver LO
810 MHz CW Desired Signal, 20 MHz RF Bandwidth, Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate 122.88 MSPS Sample Rate, 100 MHz Integration Bandwidth
0.5 80
0.4
70
OBSERVATION RECEIVER IIP2 (dBm)

DEVIATION FROM FLATNESS (dB)
0.3
60
0.2
50
0.1
0 40
–0.1 30
–0.2 +110°C
20 +40°C
–0.3 –40°C
10
–0.4
–0.5 0
14651-345
14651-342
–50 –40 –30 –20 –10 0 10 20 30 40 50 0 10 20 30 40 50 60 70 80 90 100 110

FREQUENCY OFFSET FROM LO (MHz) f1 OFFSET FREQUENCY (MHz)
Figure 42. Transmitter Frequency Response Deviation from Flatness vs. Figure 45. Observation Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO,
Frequency Offset from LO, 800 MHz LO, 20 MHz RF Bandwidth, 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,
6 dB Digital Backoff, 122.88 MSPS Sample Rate 122.88 MSPS Sample Rate
–40 80
OBSERVATION RECEIVER LO LEAKAGE (dBm)
+110°C 70
–50 +40°C
–40°C 60
–60
50
–70 40
30
–80
+110°C
20 +40°C
–40°C
–90
10
–100 0
14651-346
14651-343
300 400 500 600 700 800 900 1000 0 10 15 20 25 30 35 40 45 50 55 60

OBSERVATION RECEIVER LO FREQUENCY (MHz) INTERMODULATION FREQUENCY (MHz)
Figure 43. Observation Receiver LO Leakage vs. Observation Receiver LO Figure 46. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate 122.88 MSPS Sample Rate
Data Sheet AD9371
40 25
35 20
OBSERVATION RECEIVER GAIN (dB)

30 15
25 10
20 5
15 0
+110°C +110°C
10 +40°C –5 +40°C
–40°C –40°C
5 –10
0 –15
14651-347
14651-350
0 10 20 30 40 50 60 70 80 90 100 110 0 3 6 9 12 15 18
f1 OFFSET FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)
Figure 47. Observation Receiver IIP3 vs. f1 Offset Frequency, 900 MHz LO, Figure 50. Observation Receiver Gain vs. Observation Receiver Attenuation,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2f1 + 1 MHz, 800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth,
40 –40
OBSERVATION RECEIVER DC OFFSET (dBFS)

35 –50
+110°C
+40°C
30 –60 –40°C
25 –70
20 –80
15 –90
+110°C
10 +40°C –100
–40°C
5 –110
0 –120
14651-348
14651-351
5 10 15 20 25 30 35 40 45 50 55 60 0 3 6 9 12 15 18
INTERMODULATION FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)
Figure 48. Observation Receiver IIP3 vs. Intermodulation Frequency (2f2 − f1), Figure 51. Observation Receiver DC Offset vs. Observation Receiver
900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth, Attenuation, 800 MHz LO, 100 MHz RF Bandwidth,
0 0
OBSERVATION RECEIVER IMAGE (dBc)
+110°C
OBSERVATION RECEIVER HD2 (dBc)
–20 –20 +110°C

+40°C
+40°C
–40°C
–40°C
–40 –40
–60 –60
–80 –80
–100 –100
–120 –120
14651-349
14651-352
0 3 6 9 12 15 18 0 3 6 9 12 15 18
OBSERVATION RECEIVER ATTENUATION (dB) OBSERVATION RECEIVER ATTENUATION (dB)
Figure 49. Observation Receiver Image vs. Observation Receiver Attenuation, Figure 52. Observation Receiver HD2 vs. Observation Receiver Attenuation,
800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth, BTC Active, 800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation,
122.88 MSPS Sample Rate Input Power Increasing Decibel for Decibel with Attenuation,
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
AD9371 Data Sheet
0 90
–10 +110°C 80
+40°C
–20
SNIFFER RECEIVER IIP2 (dBm)

–40°C 70
–30
60
–40
50
–50
40
–60
30 +110°C
–70
+40°C
20 –40°C
–80
–90 10
–100 0
14651-353
14651-356
0 3 6 9 12 15 18 3 6 9 12 15
OBSERVATION RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)
Figure 53. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 56. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation, 600 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Input Power Increasing Decibel for Decibel with Attenuation,
–50 20
SNIFFER RECEIVER LO LEAKAGE (dBm)
–60 +110°C
+40°C SNIFFER RECEIVER IIP3 (dBm) 15
–40°C
–70
10
–80
–90 5
–100
0 +110°C
+40°C
–110
–40°C
–5
–120
–130 –10
14651-354
14651-357
300 400 500 600 700 3 6 9 12 15
SNIFFER RECEIVER LO FREQUENCY (MHz) INTERMODULATION FREQUENCY (MHz)
Figure 54. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 57. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 600 MHz
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30 0
–10 +110°C
SNIFFER RECEIVER NOISE FIGURE (dB)
+110°C
25 +40°C
SNIFFER RECEIVER IMAGE (dBc)
+40°C
–20 –40°C
–40°C
–30
20
–40
15 –50
–60
10
–70
–80
5
–90
0 –100
14651-355
14651-358
300 400 500 600 700 0 5 10 15 20

SNIFFER RECEIVER LO FREQUENCY (MHz) SNIFFER RECEIVER ATTENUATION (dB)
Figure 55. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, Figure 58. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate, 600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,
20 MHz Integration Bandwidth 30.72 MSPS Sample Rate
Data Sheet AD9371
–40 0
SNIFFER RECEIVER DC OFFSET (dBFS)
+110°C +110°C
–50 +40°C –10 +40°C
–40°C
SNIFFER RECEIVER EVM (dB)

–40°C
–60
–20
–70
–30
–80
–40
–90
–50
–100
–110 –60
14651-359
14651-362
0 5 10 15 20 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25
SNIFFER RECEIVER ATTENUATION (dB) SNIFFER RECEIVER INPUT POWER (dBm)
Figure 59. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, Figure 62. Sniffer Receiver EVM vs. Sniffer Receiver Input Power, 600 MHz LO,
600 MHz LO, CS Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active,
Input Power Increasing Decibel for Decibel with Attenuation, 30.72 MSPS Sample Rate
0 40
–10 +110°C 30 +110°C

+40°C
–20 –40°C +40°C
SNIFFER RECEIVER GAIN (dB)

SNIFFER RECEIVER HD2 (dBc)
20 –40°C
–30
10
–40
–50 0
–60
–10
–70
–20
–80
–30
–90
–100 –40
14651-360
14651-363
0 5 10 15 20 0 4 8 12 16 20 24 28 32 36 40 44 48 52
SNIFFER RECEIVER ATTENUATION (dB) SNIFFER RECEIVER ATTENUATION (dB)
Figure 60. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 600 MHz LO, Figure 63. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power Increasing 600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,
Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30.72 MSPS Sample Rate
–10
+110°C
–20 +40°C
–40°C
–30
–40
–50
–60
–70
–80
–90
–100
14651-361
0 5 10 15 20
SNIFFER RECEIVER ATTENUATION (dB)
Figure 61. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 600 MHz LO,
CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power
Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth,
AD9371 Data Sheet
2.6 GHz BAND
–30 100
90
–40
80
–50
RECEIVER IIP2 (dBm)

70
–60
60
–70 50
40
–80
+110°C
+40°C 30
–90 –40°C
20
–100 +110°C
10 +40°C
–40°C
–110 0
14651-008
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
0 5 10 15 20 25 30
14651-005
Figure 64. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, Figure 67. Receiver IIP2 vs. f1 Offset Frequency, 2600 MHz LO,
0 dB Receiver Attenuation, 40 MHz RF Bandwidth, 0 dB Attenuation, 40 MHz RF Bandwidth, f2 = f1 + 1 MHz,
45 100
40 90
80
35
RECEIVER IIP2 (dBm)
70
30
60
25
50
20
40
15
30
f2 – f1, +110°C
10 20 f2 – f1, +40°C
f2 – f1, –40°C
+110°C f2 + f1, +110°C
5 +40°C 10 f2 + f1, +40°C
–40°C f2 + f1, –40°C
0 0
14651-009
14651-006
0 3 6 9 12 15 5 10 15 20 25 30
40 MHz Bandwidth, 122.88 MSPS Sample Rate, 20 MHz Integration 0 dB Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Bandwidth (Includes 1.4 dB Matching Circuit Loss)
30 40
35
25
30
RECEIVER IIP3 (dBm)
20
25
15 20
+110°C 15
10 +40°C
–40°C 10
5 +110°C
5
+40°C
–40°C
0
14651-010
0
0 5 10 15 20 25 30
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
14651-007

Figure 66. Receiver Noise Figure vs. Receiver LO Frequency, Figure 69. Receiver IIP3 vs. f1 Offset Frequency, 2600 MHz LO,
0 dB Receiver Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 0 dB Attenuation, 40 MHz RF Bandwidth, f2 = 2 f1 + 2 MHz,
20 MHz Integration Bandwidth (Includes 1.4 dB Matching Circuit Loss) 122.88 MSPS Sample Rate
Data Sheet AD9371
40 –40
+110°C
+40°C
35 –50 –40°C

30 –60
RECEIVER IIP3 (dBm)
25 –70
20 –80
15 –90
10 f2 – 2f1, +110°C –100

f2 – 2f1, +40°C
f2 – 2f1, –40°C
5 f2 + 2f1, +110°C –110
f2 + 2f1, +40°C
f2 + 2f1, –40°C
0 –120
14651-014
14651-011
5 10 15 20 25 30 0 5 10 15 20 25 30
–40 –40
+110°C +110°C
+40°C +40°C
–40°C –50 –40°C
–50
–60
RECEIVER HD2 (dBc)

–60
–70
–70
–80
–80
–90
–90
–100
–100 –110
14651-012
14651-015
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 71. Receiver Image vs. Receiver Attenuation, 2600 MHz LO, Figure 74. Receiver HD2 vs. Receiver Attenuation, 2600 MHz LO, CW Signal 5 MHz
Continuous Wave (CW) Signal 5 MHz Offset, 40 MHz RF Bandwidth, Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate Decibel with Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
25 –40
+110°C +110°C
+40°C +40°C
20 –40°C –50 –40°C
15
–60
RECEIVER GAIN (dB)
RECEIVER HD3 (dBc)
10
–70
5
–80
0
–90
–5
–10 –100
–15 –110
14651-013
14651-016
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 72. Receiver Gain vs. Receiver Attenuation, 2600 MHz LO, CW Signal Figure 75. Receiver HD3 vs. Receiver Attenuation, 2600 MHz LO, CW Signal 5 MHz
5 MHz Offset, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Decibel with Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
AD9371 Data Sheet
0 30
+110°C +110°C
+40°C +40°C
–5 –40°C –40°C
25

–10
RECEIVER EVM (dB)
–15 20
–20
15
–25
–30 10
–35
5
–40
–45 0
14651-017
14651-020
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –40 –35 –30 –25 –20 –15 –10 –5 0
Figure 76. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power, Figure 79. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,
2600 MHz LO, 40 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, 2614 MHz LO, 2435 MHz CW Interferer, Noise Figure Integrated over
BTC Active, 122.88 MSPS Sample Rate 7 MHz to 10 MHz
0 0
+110°C
–10 –10 +40°C
–40°C
–20 –20

–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
14651-021
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
0 5 10 15 20
14651-018
RF ATTENUATION (dB)
Figure 77. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, 40 MHz Figure 80. Transmitter Image vs. RF Attenuation, 40 MHz RF Bandwidth,
RF Bandwidth, CW Tone 3 MHz Offset from LO 2600 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run
with Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW
10 MHz Offset from LO, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
30 0
+110°C
–10 +40°C
–40°C
25
–20
–30
20
–40
15 –50
–60
10
–70
–80
5
+110°C
+40°C –90
–40°C
0 –100
14651-022
14651-019
–50 –45 –40 –35 –30 –25 –20 –20 –15 –10 –5 0 5 10 15 20
Figure 78. Receiver Noise Figure vs. Close-In Interferer Signal Power, Figure 81. Transmitter Image vs. Desired Offset Frequency, 40 MHz RF
2614 MHz LO, 2625 MHz CW Interferer, Noise Figure Integrated over Bandwidth, 2300 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
7 MHz to 10 MHz, 40 MHz RF Bandwidth Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
CW Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
Data Sheet AD9371
10 0
8 –10
6 –20

4 –30
Tx OUTPUT (dBm)
2 –40
0 –50
–2 –60
–4 –70
–6 –80
+110°C
–8 +40°C –90
–40°C
–10 –100
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
14651-023
14651-026
Figure 82. Tx Output Power, Transmitter QEC, and External LO Leakage Active, Figure 85. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth, 40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
245.76 MSPS Sample Rate CW Signal 3 MHz Offset from LO
–60 0
+110°C
+40°C –10
–65 –40°C
–20

–70
–30
–75
–40
–80 –50
–60
–85
–70
–90
–80
–95 –90
–100 –100
14651-024
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
0 5 10 15 20
14651-027
RF ATTENUATION (dB)
Figure 83. Transmitter LO Leakage vs. RF Attenuation, 2300 MHz LO, Figure 86. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
External Transmitter QEC and LO Leakage Tracking Active, CW Signal 10 MHz 40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth CW Signal 3 MHz Offset from LO
(If Input Power to the ORx Channel Is Not Held Constant,
Device Performance Degrades as Shown in This Figure)
–60 0
1.8GHz, +110°C –10
–65 1.8GHz, +40°C
1.8GHz, –40°C
2.3GHz, +110°C –20
–70 2.3GHz, +40°C

2.3GHz, –40°C –30
2.8GHz, +110°C
–75 2.8GHz, +40°C
2.8GHz, –40°C –40
–80 –50
–60
–85
–70
–90
–80
–95 –90
–100 –100
14651-025
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
–30 –20 –10 0 10 20 30

14651-028
OFFSET FREQUENCY (MHz)

TRANSMITTER LO FREQUENCY (MHz)
Figure 84. Transmitter LO Leakage vs. Offset Frequency, External Transmitter Figure 87. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
QEC and LO Leakage Tracking Active, 6 dB Digital Backoff, 40 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
1 MHz Measurement Bandwidth
AD9371 Data Sheet
–80 –60
+110°C
–90 +40°C
–40°C –70
–100
–80

–110
–90
–120
–100
–130
–110
–140
–120
–150
–130
–160
–170 –140
–180 –150
14651-029
14651-032
0 5 10 15 20 100 1k 10k 100k 1M 10M
Figure 88. Transmitter Noise vs. RF Attenuation, 2600 MHz LO, Figure 91. LO Phase Noise vs. Offset Frequency,
10 MHz Offset Frequency 3 dB Digital Backoff, 2600 MHz
–40 1.0
Tx ADJACENT CHANNEL LEAKAGE RATIO (dB)
+110°C UPPER
+40°C UPPER

0.9
–45 –40°C UPPER
+110°C LOWER
+40°C LOWER 0.8
–50 –40°C LOWER
0.7
–55
0.6
–60 0.5
0.4
–65
0.3
–70
0.2
–75 +110°C
0.1 +40°C
–40°C
–80 0
14651-030
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
0 4 8 12 16 20
14651-033
RF ATTENUATION (dB)
TRANSMITTER LO FREQUENCY (MHz)
Figure 89. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, Figure 92. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, 40 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,
Transmitter QEC and LO Leakage Tracking Active 3 dB Digital Backoff
–40 35
Tx ALTERNATE CHANNEL LEAKAGE RATIO (dB)
+110°C UPPER +110°C

+40°C UPPER +40°C
–45 –40°C UPPER –40°C
+110°C LOWER 30
+40°C LOWER
25
–55
20
–60
15
–65
10
–70
–75 5
–80 0
14651-031
14651-034
0 4 8 12 16 20 0 2 4 6 8 10 12 14 16 18 20
Data Sheet AD9371
0 0
+110°C
–10 –10 +40°C
–40°C
–20 –20

–30 –30
Tx OUTPUT (dBm)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
14651-035
14651-038
2500 2525 2550 2575 2600 2625 2650 2675 2700 0 5 10 15 20
Figure 94. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, 40 MHz Figure 97. Transmitter HD2 vs. RF Attenuation, 2600 MHz LO,
RF Bandwidth, Transmitter QEC and Internal LO Leakage Active, LTE 10 MHz 2605 MHz CW Desired Signal, 40 MHz RF Bandwidth,
Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth, 245.76 MSPS Sample Rate 245.76 MSPS Sample Rate
0 0
+110°C
–10 +40°C
–10 –40°C
–20
–20

–30
Tx OUTPUT (dBm)
–30
–40
–50 –40
–60
–50
–70
–60
–80
–90 –70
–100 –80
14651-039
2100
2200
2300
2400
2500
2600
2750
2800
2900
3000
3100
0 5 10 15 20
14651-036
RF ATTENUATION (dB)
FREQUENCY (MHz)
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active, 2605 MHz CW Desired Signal, 40 MHz RF Bandwidth,
–20 10
+110°C +110°C
+40°C +40°C
–40°C
–40°C
–25 5
–30 0
–35 –5
–40 –10
–45 –15
–50 –20
14651-037
14651-040
0 4 8 12 16 20 0 5 10 15 20
Figure 96. Transmitter EVM vs. RF Attenuation, 2550 MHz LO, Transmitter LO Figure 99. Transmitter Output Power vs. RF Attenuation, 2600 MHz LO,
Leakage and Transmitter QEC Tracking Active, 200 MHz RF Bandwidth, 2605MHz CW Desired Signal, 40 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate 245.76 MSPS Sample Rate
AD9371 Data Sheet
0.10 30
+110°C

0.08 +40°C
–40°C
25
0.06
0.04
20
0.02
0 15
–0.02
10
–0.04
–0.06
5
+110°C
–0.08 +40°C
–40°C
–0.10 0
14651-041
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
0 2 4 6 8 10 12 14 16 18 20
14651-044
RF ATTENUATION (dB)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 100. Tx Attenuation Step Error vs. RF Attenuation, 2600 MHz LO, Figure 103. Observation Receiver Noise Figure vs. Observation Receiver
2610 MHz CW Desired Signal, 40 MHz RF Bandwidth, LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate 245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth
0.5 80
0.4
70

0.3
60
0.2
50
0.1
0 40
–0.1
30
–0.2
20
–0.3
10 +110°C
–0.4 +40°C
–40°C
–0.5 0
14651-045
14651-042
–100 –80 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 110

–40 80
+110°C
+40°C
–45 –40°C 70
–50 60
–55 50
–60 40
–65 30
–70 20
–75 10 +110°C
+40°C
–40°C
–80 0
14651-046
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
14651-043
5 15 25 35 45 55 65 75 85 95 105 115
INTERMODULATION FREQUENCY (MHz)
Figure 102. Observation Receiver LO Leakage vs. Observation Receiver Figure 105. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth, 2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
Data Sheet AD9371
40 25
+110°C +110°C
+40°C +40°C
35 –40°C 20 –40°C

30 15
25 10
20 5
15 0
10 –5
5 –10
14651-047
–15
14651-050
0 10 20 30 40 50 60 70 80 90 100 110 0 3 6 9 12 15 18
Figure 106. Observation Receiver IIP3 vs. f1 Offset Frequency, Figure 109. Observation Receiver Gain vs. Observation Receiver Attenuation,
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, 2600 MHz LO, CW Signal 25 MHz Offset,
f2 = 2f1 + 1 MHz, 245.76 MSPS Sample Rate 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
40 –40
+110°C +110°C

+40°C +40°C
35 –40°C –40°C
–50
30
–60
25
20 –70
15
–80
10
–90
5
0 –100
14651-048
14651-051
5 15 25 35 45 55 65 75 85 95 105 115 0 3 6 9 12 15 18
Figure 107. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), Figure 110. Observation Receiver DC Offset vs. Observation Receiver
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, Attenuation, 2600 MHz LO, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
0 0
+110°C +110°C
+40°C +40°C
–40°C –40°C
–20 –20
–40 –40
–60 –60
–80 –80
–100 –100
–120 –120
14651-049
14651-052
0 3 6 9 12 15 18 0 3 6 9 12 15 18
AD9371 Data Sheet
0 90
+110°C +110°C
+40°C +40°C
–40°C 80 –40°C
–20

70
–40 60
50
–60
40
–80 30
20
–100
10
–120 0
14651-053
14651-056
0 3 6 9 12 15 18 3 6 9 12
–40 20
+110°C +110°C
+40°C +40°C
–50 –40°C –40°C

SNIFFER RECEIVER IIP3 (dBm) 15
–60
10
–70
–80 5
–90
0
–100
–5
–110
–120 –10
14651-054
14651-057
2300 2400 2500 2600 2700 2800 0 2 4 6 8 10 12
Figure 113. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 116. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 2600 MHz
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30 0
+110°C +110°C
+40°C –10 +40°C
–40°C –40°C
25
–20
–30
20
–40
15 –50
–60
10
–70
–80
5
–90
0 –100
14651-055
14651-058
2300 2400 2500 2600 2700 2800 0 5 10 15 20

Figure 114. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, Figure 117. Sniffer Receiver Image vs. Sniffer Receiver Attenuation, 2600 MHz
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate, LO, CW Signal 1 MHz Offset, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
20 MHz Integration Bandwidth
Data Sheet AD9371
–40 0
+110°C +110°C
+40°C –5 +40°C
–50 –40°C –40°C

–10

–60 –15
–20
–70
–25
–80
–30
–90 –35
–40
–100
–45
–110 –50
14651-059
14651-062
0 5 10 15 20 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25
Figure 118. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, Figure 121. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, 2600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
Input Power Increasing Decibel for Decibel with Attenuation, BTC Active, 30.72 MSPS Sample Rate
0 40
+110°C +110°C
+40°C +40°C
–10 –40°C
–40°C 30
–20
SNIFFER RECEIVER GAIN (dB)

20
–30
10
–40
–50 0
–60
–10
–70
–20
–80
–30
–90
–100 –40
14651-060
14651-063
0 5 10 15 20 0 4 8 12 16 20 24 28 32 36 40 44 48 52
Figure 119. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, Figure 122. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, 2600 MHz LO, CW Signal 1 MHz Offset, 20 MHz RF Bandwidth,
Input Power Increasing Decibel for Decibel with Attenuation, 30.72 MSPS Sample Rate
0
+110°C
+40°C
–40°C
–20
–40
–60
–80
–100
–120
14651-061
0 5 10 15 20
Figure 120. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 2600 MHz LO,
CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power
Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth,
AD9371 Data Sheet
3.5 GHz BAND
–30 90
+110°C
–35 +40°C 80
–40°C
–40
70
RECEIVER IIP2 (dBm)

–45
60
–50
50
–55
40
–60
30
–65
20
–70
+110°C
10 +40°C
–75
–40°C
0
14651-067
–80
14651-064
5 10 15 20 25 30 35 40 45 50 55 60
3300 3400 3500 3600 3700 3800
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,
45 100
+110°C f2 – f1, +110°C
+40°C 90 f2 – f1, +40°C
40 –40°C f2 – f1, –40°C
f2 + f1, +110°C
80 f2 + f1, +40°C
35 f2 + f1, –40°C
RECEIVER IIP2 (dBm)
70
30
60
25
50
20
40
15 30
10 20
5 10
14651-068
0
14651-065
5 10 15 20 25 30 35 40 45 50 55 60
100 MHz Bandwidth, 153.6 MSPS Sample Rate, 50 MHz Integration Bandwidth 0 dB Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
(Includes 1 dB Matching Circuit Loss)
30 40
+110°C
+110°C +40°C
+40°C 35 –40°C
–40°C
25
30
RECEIVER IIP3 (dBm)
20 25
20
15
15
10
10
5 5
0
14651-069
0 5 10 15 20 25 30 35 40 45 50 55 60
14651-066
3300 3400 3500 3600 3700 3800

Figure 128. Receiver IIP3 vs. f1 Offset Frequency, 3500 MHz LO,
Figure 125. Receiver Noise Figure vs. Receiver LO Frequency,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2 f1 + 1 MHz,
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate,
50 MHz Integration Bandwidth (Includes 1 dB Matching Circuit Loss)
Data Sheet AD9371
40 –40
f2 – f1, +110°C +110°C
f2 – f1, +40°C +40°C
35 f2 – f1, –40°C –50 –40°C
f2 + f1, +110°C
f2 + f1, +40°C

30 f2 + f1, –40°C –60
RECEIVER IIP3 (dBm)
25 –70
20 –80
15 –90
10 –100
5 –110
0 –120
14651-070
14651-073
5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30
–40 –40
+110°C +110°C
+40°C +40°C
–50 –40°C –50 –40°C
–60 –60
–70 RECEIVER HD2 (dBc) –70
–80 –80
–90 –90
–100 –100
–110 –110
14651-071
14651-074
Figure 130. Receiver Image vs. Receiver Attenuation, 3500 MHz LO, Figure 133. Receiver HD2 vs. Receiver Attenuation, 3500 MHz LO, CW Signal
Continuous Wave (CW) Signal 17 MHz Offset, 100 MHz RF Bandwidth, 17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Background Tracking Calibration (BTC) Active, 153.6 MSPS Sample Rate Decibel with Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
25 –40
+110°C +110°C
+40°C +40°C
20 –40°C –50 –40°C
15
–60
RECEIVER GAIN (dB)
RECEIVER HD3 (dBc)
10
–70
5
–80
0
–90
–5
–10 –100
–15 –110
14651-072
14651-075
Figure 131. Receiver Gain vs. Receiver Attenuation, 3500 MHz LO, CW Signal Figure 134. Receiver HD3 vs. Receiver Attenuation, 3500 MHz LO, CW Signal
17 MHz Offset, 100 MHz RF Bandwidth, De-Embedded to Receiver Port, 17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel
153.6 MSPS Sample Rate for Decibel with Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
AD9371 Data Sheet
0 30
+110°C +110°C
+40°C +40°C
–5 –40°C –40°C
25

–10
RECEIVER EVM (dB)
–15 20
–20
15
–25
–30 10
–35
5
–40
–45 0
14651-076
14651-079
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0
Figure 135. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power, Figure 138. Receiver Noise Figure vs. Out of Band Interferer Signal Power,
3600 MHz LO, 100 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, 3614 MHz LO, 3665 MHz CW Interferer, Noise Figure Integrated over
BTC Active, 153.6 MSPS Sample Rate 7 MHz to 10 MHz
0
+110°C
–10 +40°C
–40°C
–20

–30
–40
–50
–60
–70
–80
–90
–100
14651-077
14651-080
3300 3400 3500 3600 3700 3800
Figure 136. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, Figure 139. Transmitter Image vs. RF Attenuation, 100 MHz RF Bandwidth,
100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO 3550 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run
with Two 20 MHz, LTE Downlink Carriers, Then Image Measured with CW
10 MHz Offset from LO, 6 dB Digital Backoff, 307.2 MSPS Sample Rate
30
+110°C +110°C
28 +40°C +40°C
–40°C –40°C
26
24
22
20
18
16
14
12
10
14651-078
14651-081
–50 –45 –40 –35 –30 –25 –20 –50 –40 –30 –20 –10 0 10 20 30 40 50
Figure 137. Receiver Noise Figure vs. Close-In Interferer Signal Power, Figure 140. Transmitter Image vs. Desired Offset Frequency, 100 MHz RF
3614 MHz LO, 3625 MHz CW Interferer, Noise Figure Integrated over Bandwidth, 3550 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
7 MHz to 10 MHz, 100 MHz RF Bandwidth Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Data Sheet AD9371
10 0
8 –10
6 –20

4 –30
Tx OUTPUT (dBm)
2 –40
0 –50
–2 –60
–4 –70
–6 –80
+110°C
–8 +40°C –90
–40°C
–10 –100
14651-082
14651-085
3300 3400 3500 3600 3700 3800 3300 3400 3500 3600 3700 3800
Figure 141. Tx Output Power, Transmitter QEC and Figure 144. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
External LO Leakage Active, 5 MHz CW Offset Signal, 100 MHz Receiver RF Bandwidth, 100 MHz Transmitter RF Bandwidth,
1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate CW Signal 3 MHz Offset from LO
–60 0
+110°C
+40°C –10
–65 –40°C
–20

–70
–30
–75
–40
–80 –50
–60
–85
–70
–90
–80
–95
–90
–100 –100
14651-086
14651-083
0 5 10 15 20 3300 3400 3500 3600 3700 3800

Transmitter QEC and External LO Leakage Tracking Active, CW Signal 10 MHz 100 MHz Receiver RF Bandwidth, 100 MHz Transmitter RF Bandwidth,
Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth CW Signal 3 MHz Offset from LO
(If Input Power to ORx Channel Is Not Held Constant,
Performance Degrades as Shown in This Plot)
0
3.3GHz, +110°C
3.3GHz, +40°C –10
3.3GHz, –40°C
3.55GHz, +110°C
–20
3.55GHz, +40°C
3.55GHz, –40°C
3.8GHz, +110°C –30
3.8GHz, +40°C
3.8GHz, –40°C –40
–50
–60
–70
–80
–90
–100
14651-084
14651-087
–30 –20 –10 0 10 20 30 3300 3400 3500 3600 3700 3800

Transmitter QEC and External LO Leakage Tracking Active, 100 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
AD9371 Data Sheet
–80 –60
+110°C
+40°C
–90 –40°C –70
–100
–80

–110
–90
–120
–100
–130
–110
–140
–120
–150
–130
–160
–170 –140
–180 –150
14651-088
14651-091
0 5 10 15 20 100 1k 10k 100k 1M 10M
Figure 147. Transmitter Noise vs. RF Attenuation, 3500 MHz LO, Figure 150. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
100 MHz Offset Frequency, Zeros Input Data 3500 MHz LO
–40 1.0
+110°C UPPER +110°C

+40°C UPPER +40°C

0.9
–45 –40°C UPPER –40°C
+110°C LOWER
+40°C LOWER 0.8
0.7
–55
0.6
–60 0.5
–65 0.4
0.3
–70
0.2
–75
0.1
–80 0
14651-089
14651-092
0 5 10 15 20 3300 3400 3500 3600 3700 3800
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, 100 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
–40 35
+110°C UPPER +110°C

+40°C UPPER +40°C
–45 –40°C UPPER 30 –40°C
+110°C LOWER
+40°C LOWER

25
–55
20
–60
15
–65
10
–70
–75 5
–80 0
14651-090
14651-093
0 5 10 15 20 0 2 4 6 8 10 12 14 16 18 20
Data Sheet AD9371
0 0
+110°C
–10 –10 +40°C
–40°C
–20 –20

–30 –30
Tx OUTPUT (dBm)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
14651-094
14651-097
3400 3425 3450 3475 3500 3525 3550 3575 3600 0 5 10 15 20
0 0
+110°C
–10 +40°C
–10 –40°C
–20
–20
–30 TRANSMITTER HD3 (dBc)
Tx OUTPUT (dBm)
–30
–40
–50 –40
–60
–50
–70
–60
–80
–70
–90
–100 –80
14651-095
14651-098
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 0 5 10 15 20
307.2 MSPS Sample Rate (Noise Floor Includes Test Equipment Response)
–20 10
+110°C +110°C
+40°C +40°C
–40°C 5 –40°C
–25
0
–30
–5
–35
–10
–40
–15
–45
–20
–50 –25
14651-096
14651-099
0 5 10 15 20 0 5 10 15 20
Figure 155. Transmitter EVM vs. RF Attenuation, 3500 MHz LO, Figure 158. Transmitter Output Power vs. RF Attenuation, 3500 MHz LO,
Transmitter LO Leakage, and Transmitter QEC Tracking Active, 3505 MHz CW Desired Signal, 100 MHz RF Bandwidth,
100 MHz RF Bandwidth, LTE 20 MHz Downlink Signal, 307.2 MSPS Sample Rate 2 dB Digital Backoff, 307.2 MSPS Sample Rate
AD9371 Data Sheet
0.10
+110°C
+40°C 30
0.08

–40°C
0.06
25
0.04
0.02 20
0
15
–0.02
–0.04
10
–0.06
–0.08 5
+110°C
+40°C
–0.10
14651-100
–40°C
0 2 4 6 8 10 12 14 16 18 20
0
14651-103
RF ATTENUATION (dB) 3300 3400 3500 3600 3700 3800
Figure 159. Tx Attenuation Step Error vs. RF Attenuation, 3500 MHz LO, Figure 162. Observation Receiver Noise Figure vs. Observation Receiver LO
3510 MHz CW Desired Signal, 100 MHz RF Bandwidth, Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth,
De-Embedded to Transmitter Port, 307.2 MSPS Sample Rate 307.2 MSPS Sample Rate, 120 MHz Integration Bandwidth
1.0 80
0.8
70
0.6
60
0.4
50
0.2
0 40
–0.2 30
–0.4
20
–0.6
10 +110°C
–0.8 +40°C
–40°C
0
14651-104
–1.0
14651-101
–100 –80 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 110
–40 80
+110°C
+110°C
+40°C +40°C
–45 –40°C 70 –40°C
–50 60
–55 50
–60 40
–65 30
–70 20
–75 10
–80 0
14651-105
14651-102
3300 3400 3500 3600 3700 3800 5 15 25 35 45 55 65 75 85 95 105 115

Data Sheet AD9371
40 25
+110°C +110°C
+40°C +40°C
35 –40°C 20 –40°C

30 15
25 10
20 5
15 0
10 –5
5 –10
14651-106
–15
14651-109
0 10 20 30 40 50 60 70 80 90 100 110 0 3 6 9 12 15 18
Figure 165. Observation Receiver IIP3 vs. f1 Offset Frequency, 3600 MHz LO, Figure 168. Observation Receiver Gain vs. Observation Receiver Attenuation,
0 dB Attenuation, 240 MHz RF Bandwidth, f2 = 2f1 + 1 MHz, 3500 MHz LO, CW Signal 25 MHz Offset, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate De-Embedded to Receiver Port, 307.2 MSPS Sample Rate
40 –40
+110°C +110°C

+40°C +40°C
35 –40°C –40°C
–50
30
–60
25
–70
20
–80
15
–90
10
5 –100
0 –110
14651-107
14651-110
5 15 25 35 45 55 65 75 85 95 105 115 0 3 6 9 12 15 18
3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth, Attenuation, 3500 MHz LO, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
0 0
+110°C +110°C
–10 +40°C +40°C
–40°C –40°C
–20
–20
–30
–40
–40
–50 –60
–60
–80
–70
–80
–100
–90
–100 –120
14651-108
14651-111
0 3 6 9 12 15 18 0 3 6 9 12 15 18
AD9371 Data Sheet
0 90
+110°C +110°C
–10 +40°C +40°C
–40°C 80 –40°C
–20

70
–30
60
–40
50
–50
40
–60
30
–70
20
–80
–90 10
–100 0
14651-112
14651-115
0 3 6 9 12 15 18 2 6 10 14 18
–40 20
+110°C +110°C
+40°C +40°C
–50 –40°C –40°C

SNIFFER RECEIVER IIP3 (dBm) 15
–60
10
–70
–80 5
–90
0
–100
–5
–110
–120 –10
14651-116
14651-113
3300 3400 3500 3600 3700 3800 0 2 4 6 8 10 12

Figure 172. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 175. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1),
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate 3500 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
20 0
+110°C +110°C
+40°C –10 +40°C
18
–40°C –40°C
16 –20
14 –30
12 –40
10 –50
8 –60
6 –70
4 –80
2 –90
0 –100
14651-117
14651-114
3300 3400 3500 3600 3700 3800 0 5 10 15 20 25 30 35 40 45 50

Figure 173. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, Figure 176. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate, 3500 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,
10 MHz Integration Bandwidth 38.4 MSPS Sample Rate
Data Sheet AD9371
–40 0
+110°C +110°C
+40°C +40°C
–40°C –5 –40°C
–50

–10
–60
–15
–70 –20
–80 –25
–30
–90
–35
–100
–40
–110 –45
14651-121
14651-118
0 5 10 15 20 –70 –65 –60 –55 –50 –45 –40 –35 –30
Figure 177. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, Figure 180. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation, 3600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
Input Power Increasing Decibel for Decibel with Attenuation, BTC Active, 38.4 MSPS Sample Rate
0 35
+110°C +110°C
–10 +40°C +40°C
–40°C 25 –40°C
–20
–30 SNIFFER RECEIVER GAIN (dB) 15
–40
5
–50
–5
–60
–70 –15
–80
–25
–90
–100 –35
14651-122
14651-119
0 5 10 15 20 0 5 10 15 20 25 30 35 40 45 50 55
Figure 178. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, Figure 181. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation, 3600 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,
Input Power Increasing Decibel for Decibel with Attenuation, De-Embedded to Receiver Port, 38.4 MSPS Sample Rate
0
+110°C
+40°C
–10 –40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
14651-120
0 5 10 15 20
Figure 179. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation,

3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation,
AD9371 Data Sheet
5.5 GHz BAND
–30 100
+110°C
90 +40°C
+110°C –40°C
–40 +40°C
–40°C 80
–50
RECEIVER IIP2 (dBm)

70
60
–60
50
–70 40
30
–80
20
–90
10
–100 0
14651-185
14651-223
5300 5400 5500 5600 5700 5800 5900 0 10 20 30 40 50 60
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,
45 100
40 90
+110°C
+40°C
80
35 –40°C
RECEIVER IIP2 (dBm)
70
30
60
25
50
20
40 f2 + f1, +110°C
15
f2 + f1, +40°C
30 f2 + f1, –40°C
f2 – f1, +110°C
10 20 f2 – f1, +40°C
f2 – f1, –40°C
5 10
0 0
14651-226
14651-224
0 3 6 9 12 15 15 20 25 30 35 40 45
100 MHz Bandwidth, 122.88 MSPS Sample Rate, 50 MHz Integration 0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Bandwidth (Includes 1.2 dB Matching Circuit Loss)
30 40
+110°C
+40°C
35 –40°C
25
30
RECEIVER IIP3 (dBm)
20
25
15 20
15
10 +110°C
+40°C 10
–40°C
5
5
0
14651-187
0
14651-225
0 10 20 30 40 50 60
5300 5400 5500 5600 5700 5800 5900
Figure 184. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Figure 187. Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO, 0 dB Attenuation,
Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 50 MHz 100 MHz RF Bandwidth, f2 = 2 f1 + 2 MHz, 122.88 MSPS Sample Rate
Integration Bandwidth (Includes 1.2 dB Matching Circuit Loss)
Data Sheet AD9371
40 –40
35 –50

+110°C
30 +40°C
–60
RECEIVER IIP3 (dBm)
–40°C
25
–70
20
–80
15
+110°C –90
10 +40°C
–40°C
5 –100
0 –110
14651-227
14651-230
10 15 20 25 30 35 0 5 10 15 20 25 30
–40 –40
+110°C –50
–50
+40°C +110°C
–40°C +40°C
–60 –40°C
RECEIVER HD2 (dBc)

–60
–70
–70
–80
–80
–90
–90
–100
–100 –110
14651-228
14651-231
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 189. Receiver Image vs. Receiver Attenuation, 5600 MHz LO, Figure 192. Receiver HD2 vs. Receiver Attenuation, 5600 MHz LO,
Continuous Wave (CW) Signal 10 MHz Offset, 100 MHz RF Bandwidth, CW Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation,
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate Input Power Increasing Decibel for Decibel with Attenuation,
20 –40
15 –50
10
–60
RECEIVER GAIN (dB)
RECEIVER HD3 (dBc)
5
–70
0
–80
–5
+110°C
–90 +40°C
–10 +110°C –40°C
+40°C
–40°C
–15 –100
–20 –110
14651-232
14651-229
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 190. Receiver Gain vs. Receiver Attenuation, 5600 MHz LO, Figure 193. Receiver HD3 vs. Receiver Attenuation, 5600 MHz LO,
CW Signal 10 MHz Offset, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate CW Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power
Increasing Decibel for Decibel with Attenuation,100 MHz RF Bandwidth,
AD9371 Data Sheet
0 0
–5 –10 +110°C
+110°C +40°C
+40°C
–40°C –20 –40°C
–10

–30
RECEIVER EVM (dB)
–15
–40
–20
–50
–25
–60
–30
–70
–35
–80
–40 –90
–45 –100
14651-233
14651-236
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 0 5 10 15 20
RECEIVER INPUT POWER (dBm) RF ATTENUATION (dB)
Figure 194. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power, Figure 197. Transmitter Image vs. RF Attenuation, 75 MHz RF Bandwidth,
5600 MHz LO, 100 MHz RF Bandwidth LTE, 20 MHz Uplink Centered at DC, 5600 MHz LO, 0 dB RF Attenuation, Transmitter Quadrature Error Correction
BTC Active, 122.88 MSPS Sample Rate (QEC) Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image
Measured with CW 10 MHz Offset from LO, 3 dB Digital Backoff,
0 0
–10 –10 +110°C

+40°C
–20 –20 –40°C
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
14651-234
14651-237
5300 5400 5500 5600 5700 5800 5900 –40 –30 –20 –10 0 10 20 30 40
RECEIVER LO FREQUENCY (MHz) DESIRED OFFSET FREQUENCY (MHz)
Figure 195. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, Figure 198. Transmitter Image vs. Desired Offset Frequency, 75 MHz RF
100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO Bandwidth, 5600 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
30 10
8
25
4
20
Tx OUTPUT (dBm)
15 0
–2
10 +110°C
+40°C –4 +110°C
–40°C +40°C
–40°C
–6
5
–8
0 –10
14651-235
14651-238
–40 –35 –30 –25 –20 –15 –10 –5 0 5300 5400 5500 5600 5700 5800 5900
OUT-OF-BAND INTERFERER SIGNAL POWER (dBm) RECEIVER LO FREQUENCY (MHz)
Figure 196. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power, Figure 199. Tx Output Power, Transmitter QEC, and External LO Leakage
5400 MHz LO, 5600 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz Active, 5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,
Data Sheet AD9371
–40 0
–10
–50
–20

–30
–60
–40
–70 –50
–60
+110°C
–80 +40°C
–40°C –70
–80
–90
–90
–100 –100
14651-239
14651-242
0 5 10 15 20 5300 5400 5500 5600 5700 5800 5900
External Transmitter QEC, and LO Leakage Tracking Active, CW Signal 100 MHz Receiver RF Bandwidth, 75 MHz Transmitter RF Bandwidth,
10 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth CW Signal 3 MHz Offset from LO
–60 –10
–20
–65
–30

–70
–40
–75
–50
–80 –60
–70
–85 5.9GHz, +110°C 5.3GHz, +110°C
5.9GHz, +40°C 5.3GHz, +40°C –80
–90 5.9GHz, –40°C 5.3GHz, –40°C
5.6GHz, +110°C –90
5.6GHz, +40°C
–95 5.6GHz, –40°C –100
–100 –110
14651-240
14651-243
–40 –30 –20 –10 0 10 20 30 40 5300 5400 5500 5600 5700 5800 5900
External Transmitter QEC and LO Leakage Tracking Active, 75 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
0 –80
–10 –90 +110°C

+40°C
–40°C
–20 –100
–30 –110
–40 –120
–50 –130
–60 –140
–70 –150
–80 –160
–90 –170
–100 –180
14651-241
14651-244
5300 5400 5500 5600 5700 5800 5900 0 5 10 15 20

Figure 202. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver RF Figure 205. Transmitter Noise vs. RF Attenuation, 5600 MHz LO,
Bandwidth, 75 MHz Transmitter RF Bandwidth, CW Signal 3 MHz Offset from LO 1 MHz Offset Frequency
AD9371 Data Sheet
–40 1.0

0.9
–45
0.8
–50
0.7
–55
0.6
–60 0.5
0.4
–65 +110°C LOWER
+40°C LOWER +110°C
0.3
–40°C LOWER +40°C
–70
+110°C UPPER –40°C
0.2
+40°C UPPER
0.1
–80 0
14651-245
14651-248
0 5 10 15 20 5300 5400 5500 5600 5700 5800 5900
5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, 75 MHz RF Bandwidth, CW 10 MHz Offset from LO, 3 dB Digital Backoff
Transmitter QEC and LO Leakage Tracking Active
–40 30
–45
25 +110°C
+40°C
–50 TRANSMITTER OIP3 (dBm) –40°C
20
–55
–60 15
–65 +110°C LOWER

+40°C LOWER 10
–40°C LOWER
–70
+110°C UPPER
+40°C UPPER 5
–80 0
14651-246
14651-249
0 5 10 15 20 0 5 10 15 20
–60 0
–70 –10
–20
–80
–30
Tx OUTPUT (dBm)
–90
–40
–100
–50
–110
–60
–120
–70
–130
–80
–140 –90
–150 –100
14651-247
14651-250
100 1k 10k 100k 1M 10M 5750 5775 5800 5825 5850 5875 5900 5925 5950
OFFSET FREQUENCY (Hz) FREQUENCY (MHz)
Figure 208. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff, Figure 211. Tx Output Power Spectrum, 3 dB Digital and 1 dB RF Backoff,
5850 MHz LO 40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth,
Data Sheet AD9371
0 0
–10
–10 +110°C
–20 +40°C
–40°C
–20

–30
Tx OUTPUT (dBm)
–30
–40
–50 –40
–60
–50
–70
–60
–80
–70
–90
–100 –80
14651-251
14651-254
5350 5450 5550 5650 5750 5850 5950 6050 6150 6250 6350 0 5 10 15 20
–20 10

+110°C
–25 5 +40°C
–40°C
+110°C
+40°C
–30 –40°C 0
–35 –5
–40 –10
–45 –15
–50 –20
14651-252
14651-255
0 5 10 15 20 0 5 10 15 20 25
Figure 213. Transmitter EVM vs. RF Attenuation, 5600 MHz LO, Transmitter Figure 216. Transmitter Output Power vs. RF Attenuation, 5850 MHz LO,
LO Leakage, and Transmitter QEC Tracking Active, 75 MHz RF Bandwidth, 5855 MHz CW Desired Signal, 75 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate 245.76 MSPS Sample Rate
0 0.10
–10 +110°C 0.08 +110°C

+40°C +40°C
–20 –40°C 0.06 –40°C
–30 0.04
–40 0.02
–50 0
–60 –0.02
–70 –0.04
–80 –0.06
–90 –0.08
–100 –0.10
14651-253
14651-256
0 5 10 15 20 0 5 10 15 20
Figure 214. Transmitter HD2 vs. RF Attenuation, 5850 MHz LO, 5855 MHz Figure 217. Tx Attenuation Step Error vs. RF Attenuation, 5850 MHz LO,
CW Desired Signal, 75 MHz RF Bandwidth, 245.76 MSPS Sample Rate 5855 MHz CW Desired Signal, 75 MHz RF Bandwidth, 245.76 MSPS Sample Rate
AD9371 Data Sheet
0.5 80
0.4
70

0.3
60
0.2
50
0.1
0 40
–0.1 30
–0.2 +110°C
20 +40°C
–0.3 –40°C
10
–0.4
–0.5 0
14651-221
14651-257
–100 –80 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 110
Frequency Offset from LO, 5850 MHz LO, 200 MHz Synthesis Bandwidth, 0 dB Attenuation, 200 MHz RF Bandwidth, f2 = f1 + 1 MHz,
–40 80
–45 70

+110°C
–50 +40°C 60
–40°C
–55 50
–60 40
–65 30
+110°C
–70 20 +40°C
–40°C
–75 10
–80 0
14651-260
14651-258
5300 5400 5500 5600 5700 5800 5900 10 20 30 40 50 60 70 80 90 100 110

30 40
35
25
30
20
25
15 20
15
+110°C
10 +40°C +110°C
–40°C 10 +40°C
–40°C
5
5
0
14651-222
0
14651-259
0 10 20 30 40 50 60 70 80 90 100 110
5300 5400 5500 5600 5700 5800 5900
OBSERVATION RECEIVER LO FREQUENCY (MHz) f1 OFFSET FREQUENCY (MHz)
Figure 220. Observation Receiver Noise Figure vs. Observation Receiver Figure 223. Observation Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO,
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth, 0 dB Attenuation, 200 MHz RF Bandwidth, f2 = 2 f1 + 1 MHz,
245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth 245.76 MSPS Sample Rate
Data Sheet AD9371
40 –40

35
–50 +110°C
+40°C
–40°C
30
–60
25
–70
20
–80
15
+110°C –90
10 +40°C
–40°C
5 –10
0 –110
14651-261
14651-264
5 15 25 35 45 55 65 75 85 95 105 115 0 3 6 9 12 15 18
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, Attenuation, 5850 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input,
245.76 MSPS Sample Rate 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
0 0
–10 +110°C –10


+40°C +110°C
–20 –40°C –20 +40°C
–40°C
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
14651-262
14651-265
0 3 6 9 12 15 18 0 3 6 9 12 15 18
Figure 225. Observation Receiver Image vs. Observation Receiver Figure 228. Observation Receiver HD2 vs. Observation Receiver Attenuation,
Attenuation, 5600 MHz LO, CW Signal 30 MHz Offset, 5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power
200 MHz RF Bandwidth, BTC Active, 245.76 MSPS Sample Rate Increasing Decibel for Decibel with Attenuation, 200 MHz RF Bandwidth,
25 0
20
OBSERVATION RECEIVER GAIN (dBc)
+110°C
+40°C –20 +110°C

–40°C +40°C
15 –40°C
–40
10
5 –60
0
–80
–5
–100
–10
–15 –120
14651-263
14651-266
0 3 6 9 12 15 18 0 3 6 9 12 15 18
Figure 226. Observation Receiver Gain vs. Observation Receiver Attenuation, Figure 229. Observation Receiver HD3 vs. Observation Receiver Attenuation,
5600 MHz LO, CW Signal 30 MHz Offset, 5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate Increasing Decibel for Decibel with Attenuation, 200 MHz RF Bandwidth,
AD9371 Data Sheet
THEORY OF OPERATION
The AD9371 is a highly integrated RF transceiver that can be RECEIVER (Rx)
configured for a wide range of applications. The device integrates The AD9371 contains dual receiver channels. Each Rx channel
all the RF, mixed-signal, and digital blocks necessary to provide is a direct conversion system that contains a programmable
transmit and receive functions in a single device. Programmability attenuator stage, followed by matched I and Q mixers that
allows the two receiver channels and two transmitter channels downconvert received signals to baseband for digitization.
to be used in TDD and FDD systems for 3G and 4G cellular
standards. To achieve gain control, a programmed gain index map is
implemented. This gain map distributes attenuation among the
The observation receiver channel has two inputs for use in various Rx blocks for optimal performance at each power level.
monitoring the transmitter outputs. This channel has a wide In addition, support is available for both automatic and manual
channel bandwidth that receives the entire transmit band and gain control modes.
feeds it back to the digital section for error correction purposes.
In addition, three sniffer receiver inputs can monitor different The receiver includes Σ-Δ ADCs and adjustable sample rates
radio frequency bands (one at a time). These channels share the that produce data streams from the received signals. The signals
baseband ADC and digital processing with the two ORx inputs. can be conditioned further by a series of decimation filters and
a fully programmable 72-tap FIR filter with additional decimation
The AD9371 contains four high speed serial interface links for settings. The sample rate of each digital filter block is adjustable
the transmit chain and four high speed serial interface links by changing the decimation factors to produce the desired
shared by the Rx, ORx, and SnRx channels (JESD204B, output data rate.
Subclass 1 compliant), providing a low pin count and reliable
data interface to a field-programmable gate array (FPGA) or OBSERVATION RECEIVER (ORx)
other custom integrated baseband solutions. The ORx operates in a similar manner to the main receivers.
The AD9371 also provides self calibration for dc offset, LO Each input is differential and uses a dedicated mixer. The ORx
leakage, and quadrature error correction using an integrated inputs share a baseband ADC and baseband section; therefore,
microcontroller core to maintain a high performance level only one can be active at any time. The mixed-signal and digital
under varying temperatures and input signal conditions. Firmware section is identical in design and operation to the main receiver
is supplied with the device to schedule all calibrations with no channels. This channel can monitor the Tx channels and
user interaction. The device includes test modes that allows implement error correction functions. It can also be used as a
system designers to debug designs during prototyping and general-purpose receiver.
optimize radio configurations. SNIFFER RECEIVER (SnRx)
TRANSMITTER (Tx) The sniffer receiver provides three differential inputs that can
The AD9371 employs a direct conversion transmitter monitor different frequency bands. Each input has a low noise
architecture consisting of two identical and independently amplifier (LNA) that is multiplexed to feed a single mixer. The
controlled channels that provide all the digital processing, output of this mixer stage is multiplexed with the ORx receiver
mixed signal, and RF blocks necessary to implement a direct mixers to feed the same baseband section. The SnRx bandwidth
conversion system. Both channels share a common frequency is limited to 20 MHz. This receiver can also be used as a general-
synthesizer. purpose receiver if the bandwidth and RF performance are
acceptable for a given application. The sniffer channel has
The digital data from the JESD204B lanes pass through a fully
limited operation from 400 MHz to 4000 MHz. Performance
programmable 96-tap FIR filter with optional interpolation.
cannot be guaranteed for LO settings above 4000 MHz.
The FIR output is sent to a series of conversion filters that
provide additional filtering and data rate interpolation prior to These receiver inputs also provide an LNA bypass mode that
reaching the DAC. Each DAC has an adjustable sample rate and removes the gain of the LNA when large signals are present.
is linear up to full scale. Note that no requirements for the LNA bypass mode are included
in Table 1; performance specifications are only relative to the
When converted to baseband analog signals, the in-phase (I) and
scenario in which the LNA is enabled.
quadrature (Q) signals are filtered to remove sampling artifacts,
and then the signals are fed to the upconversion mixers. At the CLOCK INPUT
mixer stage, the I and Q signals are recombined and modulated The AD9371 requires a differential clock connected to the
onto the carrier frequency for transmission to the output stage. DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the
Each transmit chain provides a wide attenuation adjustment clock input must be between 10 MHz and 320 MHz, and it must
range with fine granularity to help designers optimize SNR. have very low phase noise because this signal generates the RF
local oscillator and internal sampling clocks.
Data Sheet AD9371
SYNTHESIZERS manual gain mode, calibration flags, state machine states, and
RF PLL various receiver parameters are among the outputs that can be
monitored on these pins. In addition, certain pins can be
The AD9371 contains three fractional-N PLLs to generate the
configured as inputs and used in various functions such as
RF LOs used by the transmitter, receiver, and observation
setting the receiver gain in real time.
receiver. The PLL incorporates an internal VCO and loop filter
that require no external components. The internal VCO LDO The GPIO_3P3_x pins referenced to the VDDA_3P3 supply are
regulators eliminate the need for additional external power also included in the device and can provide control signals to
supplies for the PLLs. These regulators only require an external the external components such as VGAs or attenuators in the RF
bypass capacitor for each supply. section that typically use a higher reference voltage.
Clock PLL AUXILIARY CONVERTERS

The AD9371 contains a PLL synthesizer that generates all of the Auxiliary ADC Inputs (AUXADC_x)
baseband related clock signals and SERDES clocks. This PLL is The AD9371 contains an auxiliary ADC that is multiplexed to four
programmed based on the data rate and sample rate requirements input pins (AUXADC_0 through AUXADC_3). This block can
of the system. monitor system voltages without adding additional components.
External LO Inputs The auxiliary ADC is 12 bits with an input voltage range of 0.05 V
to VDDA_3P3 − 0.25 V. When enabled, the auxiliary ADC is
The AD9371 provides two external LO inputs to allow an
free running. Software reads of the output value provide the last
external synthesizer to be used with the device. These inputs
value latched at the ADC output.
must be 2× the desired LO frequency. Note that operation for
the external LO option is limited to a maximum of 4000 MHz. Auxiliary DACs (AUXDAC_x)
One input pair is dedicated to the receiver LO generation circuit The AD9371 contains 10 identical auxiliary DACs (AUXDAC_0
and the other input provides the input to the transmitter and to AUXDAC_9) that can supply bias voltages, analog control
observation receiver LO generation blocks. Note that the voltages, or other system functionality. The inputs of these auxiliary
observation receiver can obtain the LO from either the Tx LO DACs (AUXDAC_0 to AUXDAC_9) are multiplexed with the
generator block or its own dedicated PLL. When the sniffer GPIO_3P3_x pins according to Table 7. The auxiliary DACs are
channel is enabled, the LO for this block can only come from 10 bits and have an output voltage range of approximately 0.5 V
the dedicated internal observation channel PLL. to VDDA_3P3 − 0.3 V and have a current drive of 10 mA.
SERIAL PERIPHERAL INTERFACE (SPI) INTERFACE Table 7. AUXDAC Input Pin Assignments
The AD9371 uses a SPI to communicate with the baseband GPIO_3P3 Pin AUXDAC Output
processor (BBP). This interface can be configured as a 4-wire GPIO_3P3_9 AUXDAC_0
interface with dedicated receive and transmit ports, or it can be GPIO_3P3_7 AUXDAC_1
configured as a 3-wire interface with a bidirectional data GPIO_3P3_6 AUXDAC_2
communications port. This bus allows the BBP to set all device GPIO_3P3_10 AUXDAC_3
control parameters using a simple address data serial bus protocol. GPIO_3P3_0 AUXDAC_4
Write commands follow a 24-bit format. The first bit sets the GPIO_3P3_1 AUXDAC_5
bus direction of the bus transfer. The next 15 bits set the address GPIO_3P3_3 AUXDAC_6
where data is written. The final eight bits are the data being GPIO_3P3_4 AUXDAC_7
transferred to the specific register address. GPIO_3P3_5 AUXDAC_8
GPIO_3P3_8 AUXDAC_9
Read commands follow a similar format with the exception that
the first 16 bits are transferred on the SDIO pin, and the final JESD204B DATA INTERFACE
eight bits are read from the AD9371, either on the SDO pin in
The digital data interface for the AD9371 uses JEDEC Standard
4-wire mode or on the SDIO pin in 3-wire mode.
JESD204B Subclass 1. The serial interface operates at speeds of
GPIO_x AND GPIO_3P3_x PINS up to 6144 Mbps. The benefits of the JESD204B interface include a
The AD9371 general-purpose input/output signals referenced reduction in required board area for data interface routing and
to the VDD_IF supply can be configured for numerous functions. smaller package options due to the need for fewer pins. Digital
Some of these pins, when configured as outputs, are used by the filtering is included in all receiver and transmitter paths to provide
BBP as real-time signals to provide a number of internal settings proper signal conditioning and sampling rates to meet the
and measurements. This configuration allows the BBP to monitor JESD204B data requirements. Examples of the digital filtering
receiver performance in different situations. A pointer register configurations for the Tx and Rx paths are shown in Figure 230
selects what information is output to these pins. Signals used for and Figure 231, respectively.
AD9371 Data Sheet
Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD Lane Rates)
Tx/Tx Synthesis/ Tx Input Rx Output JESD204B Lane Rate JESD204B (No.
Rx Bandwidth (MHz) Rate (MSPS) Rate (MSPS) (Mbps), Two Tx/Two Rx of Lanes) Tx/Rx Reference Clock Options (MHz)
100/250/100 307.2 153.6 6144 4/2 122.88, 153.6, 245.76, 307.2
75/200/100 245.76 122.88 4915.2 4/2 122.88, 245.76
20/100/40 122.88 61.44 2457.6 4/2 122.88, 245.76
20/100/20 122.88 30.72 2457.6 4/1 122.88, 245.76
TRANSMITTER TRANSMITTER QUADRATURE DIGITAL

I/Q DAC HALF-BAND TRANSMITTER FIR ERROR
HALF-BAND GAIN JESD204B
14651-125
FILTER 2 (INTERPOLATION CORRECTION
FILTER 1 1, 2, 4)
Figure 230. Example Tx Data Path Filter Implementation
DEC5
RECEIVER RECEIVER RECEIVER RFIR QEC DIGITAL DC

ADC HALF-BAND HALF-BAND HALF-BAND (DECIMATION CORRECTION GAIN CORRECTION JESD204B
FILTER 3 FILTER 2 FILTER 1
14651-126
1, 2, 4) FILTER
Figure 231. Data Rx Data Path Filter Implementation
POWER SUPPLY SEQUENCE Table 9. Dual-Function Boundary Scan Test Pins

The AD9371 requires a specific power-up sequence to avoid Mnemonic JTAG Mnemonic Description
undesired power-up currents. The optimal power-on sequence GPIO_4 TRST Test access port reset
starts the process by powering up the VDIG and the VDDA_1P3 GPIO_5 TDO Test data output
(analog) supplies simultaneously. If they cannot power up GPIO_6 TDI Test data input
simultaneously, the VDIG supply must power up first. The GPIO_7 TMS Test access port mode select
VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies GPIO_18 TCK Test clock
must then power up after the VDIG and VDDA_1P3 supplies.
Note that the VDD_IF supply can power up at any time. It is Table 10. JTAG Modes
also recommended to toggle the RESET signal after power has Test Pin Level GPIO_0 to GPIO_3 Description
stabilized prior to configuration. Follow the reverse order of 0 XXXX1 Normal operation
the power-up sequence to power-down. 1 1001 JTAG mode with LVDS
JESD204B sync signals
Note that VDDA_1P3 refers to all analog 1.3 V supplies
1 1011 JTAG mode with CMOS
including the following: VDDA_BB, VDDA_CLKSYNTH, JESD204B sync signals
VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH,
1
X means don’t care.
VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH,
VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH,
VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
JTAG BOUNDARY SCAN
The AD9371 provides support for a JTAG boundary scan.
There are five dual-function pins associated with the JTAG
interface. These pins, listed in Table 9, are used to access the
on-chip test access port. To enable the JTAG functionality,
set the GPIO_0 through GPIO_3 pins according to Table 10
depending on how the desired JESD204B sync pin (that is,
SYNCINB0+, SYNCINB0−, SYNCINB1+, SYNCINB1−,
SYNCBOUTB0+, or SYNCBOUTB0−) is configured in the
software (LVDS or CMOS mode). Pull the TEST pin high to
enable the JTAG mode.
Data Sheet AD9371
OUTLINE DIMENSIONS
12.10
12.00 SQ A1 BALL
A1 BALL 11.90 PAD CORNER
CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
PIN A1
INDICATOR 10.40 SQ F
7.755 REF G
H
J
0.80 K
L
M
N
P
TOP VIEW BOTTOM VIEW
0.80 REF
8.165 REF
DETAIL A
1.27 0.91
1.18 0.84
1.09 DETAIL A 0.77
0.39
0.34
0.29
0.44 REF
SEATING 0.50 COPLANARITY

PLANE 0.45 0.12
0.40
BALL DIAMETER
03-02-2015-A
PKG-004569
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
Figure 232. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-196-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9371BBCZ −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-12
AD9371BBCZ-REEL −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-12
ADRV9371-N/PCBZ Evaluation Board, 2600 MHz Matching Circuits
ADRV9371-W/PCBZ Evaluation Board, 300 MHz to 6000 MHz Matching Circuits
1
Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D14651-0-3/17(B)

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Integrated, Dual RF Transceiver

with Observation Path

Fully integrated independent fractional-N radio frequency (RF) TX2+ DAC

Microwave, nonline of sight (NLOS) backhaul systems CLOCK

Rev. B Document Feedback

tH = –1.5ns t'H = +0.5ns

Figure 2. SYSREF_IN Signal Setup and Hold Timing

ABSOLUTE MAXIMUM RATINGS

Stresses at or above those listed under Absolute Maximum

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VSNRX_ VDDA_ VDDA_ VRX_

VDDA_ VDDA_ VDDA_ VDDA_ VDDA_

VCLK_ RX1_ TX1_ RX2_ TX2_

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

RECEIVER IIP2 (dBm)

RECEIVER DC OFFSET (dBFS)

–10 +110°C +110°C

RECEIVER HD2 (dBc)

RECEIVER HD3 (dBc)

RECEIVER NOISE FIGURE (dB)

–30 –10 +110°C

TRANSMITTER IMAGE (dBc)

–50 –45 –40 –35 –30 –25 –20 –10 –5 0 5 10

Tx1 TO Rx1 CROSSTALK (dB)

Tx2 TO Rx2 CROSSTALK (dB)

–70 600MHz, +40°C

–10 –5 0 5 10 300 400 500 600 700 800 900 1000

–90 +110°C –70

LO PHASE NOISE (dBc)

Tx INTEGRATED PHASE NOISE (Degrees)

–50 +40°C UPPER 25

–10 –10 +110°C

TRANSMITTER HD2 (dBc)

OBSERVATION RECEIVER NOISE FIGURE (dB)

OBSERVATION RECEIVER IIP2 (dBm)

–50 –40 –30 –20 –10 0 10 20 30 40 50 0 10 20 30 40 50 60 70 80 90 100 110

300 400 500 600 700 800 900 1000 0 10 15 20 25 30 35 40 45 50 55 60

OBSERVATION RECEIVER GAIN (dB)

OBSERVATION RECEIVER DC OFFSET (dBFS)

–20 –20 +110°C

SNIFFER RECEIVER IIP2 (dBm)

300 400 500 600 700 0 5 10 15 20

SNIFFER RECEIVER EVM (dB)

–10 +110°C 30 +110°C

SNIFFER RECEIVER GAIN (dB)

RECEIVER IIP2 (dBm)

f1 OFFSET FREQUENCY (MHz)

RECEIVER DC OFFSET (dBFS)

10 f2 – 2f1, +110°C –100

RECEIVER HD2 (dBc)

RECEIVER HD3 (dBc)

RECEIVER NOISE FIGURE (dB)

TRANSMITTER IMAGE (dBc)

TRANSMITTER IMAGE (dBc)

Tx1 TO Rx1 CROSSTALK (dB)