RF Agile Transceiver

Data Sheet AD9363

FEATURES FUNCTIONAL BLOCK DIAGRAM
Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit RX1B_P,
RX1B_N AD9363
DACs and ADCs RX1A_P,
RX1A_N ADC
Wide bandwidth: 325 MHz to 3.8 GHz
RX1C_P,
Supports time division duplex (TDD) and frequency division RX1C_N

duplex (FDD) operation RX2B_P,

RX2B_N
Tunable channel bandwidth (BW): up to 20 MHz RX2A_P,
P0_D11/

DATA INTERFACE
ADC TX_D5_x TO P0_D0/
RX2A_N
Receivers: 6 differential or 12 single-ended inputs TX_D0_x
RX2C_P,
Superior receiver sensitivity with a noise figure: 3 dB RX2C_N RX LO

Receive (Rx) gain control TX_MON1 TX LO

Real-time monitor and control signals for manual gain TX1A_P, DAC
P1_D11/
TX1A_N RX_D5_x TO P1_D0/
Independent automatic gain control (AGC) TX1B_P,
RX_D0_x

Dual transmitters: 4 differential outputs TX1B_N

Highly linear broadband transmitter TX_MON2

Transmit (Tx) error vector magnitude (EVM): −34 dB TX2A_P,

TX2A_N
DAC
Tx noise: ≤−157 dBm/Hz noise floor TX2B_P, RADIO

ADC

DAC

DAC
Tx monitor: 66 dB dynamic range with 1 dB accuracy TX2B_N GPO SWITCHING

Integrated fractional N synthesizers SPI

CTRL PLLs CLK_OUT
2.4 Hz local oscillator (LO) step size CTRL

CMOS/LVDS digital interface AUXADC AUXDACx XTALN

NOTES
APPLICATIONS 1. SPI, CTRL, P0_D11/TX_D5_x TO P0_D0/TX_D0_x, P1_D11/

10558-001
RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING
3G enterprise femtocell base stations CONTAIN MULTIPLE PINS.

4G femtocell base stations Figure 1.

Wireless video transmission

GENERAL DESCRIPTION
The AD9363 is a high performance, highly integrated RF agile sample rate.
transceiver designed for use in 3G and 4G femtocell applications. The transmitters use a direct conversion architecture that achieves
Its programmability and wideband capability make it ideal for a high modulation accuracy with ultralow noise. This transmitter
broad range of transceiver applications. The device combines an design produces a best-in-class Tx EVM of −34 dB, allowing
RF front end with a flexible mixed-signal baseband section and significant system margin for the external power amplifier (PA)
integrated frequency synthesizers, simplifying design-in by selection. The on-board Tx power monitor can be used as a
providing a configurable digital interface to a processor. The power detector, enabling highly accurate Tx power
AD9363 operates in the 325 MHz to 3.8 GHz range, covering measurements.
most licensed and unlicensed bands. Channel bandwidths from
less than 200 kHz to 20 MHz are supported. The fully integrated phase-locked loops (PLLs) provide low
power fractional N frequency synthesis for all receive and
The two independent direct conversion receivers have state-of- transmit channels. Channel isolation, demanded by FDD
the-art noise figure and linearity. Each Rx subsystem includes systems, is integrated into the design. All voltage controlled
independent automatic gain control (AGC), dc offset correction, oscillators (VCOs) and loop filter components are integrated.
quadrature correction, and digital filtering, thereby eliminating
the need for these functions in the digital baseband. The AD9363 The core of the AD9363 can be powered directly from a 1.3 V
also has flexible manual gain modes that can be externally regulator. The IC is controlled via a standard 4-wire serial port
controlled. Two high dynamic range ADCs per channel digitize and four real-time I/O control pins. Comprehensive power-down
the received I and Q signals and pass them through configurable modes are included to minimize power consumption during
decimation filters and 128-tap finite impulse response (FIR) normal use. The AD9363 is packaged in a 10 mm × 10 mm,
filters to produce a 12-bit output signal at the appropriate 144-ball chip scale package ball grid array (CSP_BGA).

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

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 AD9363 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 2.4 GHz Frequency Band .......................................................... 24
Applications ....................................................................................... 1 Theory of Operation ...................................................................... 28
Functional Block Diagram .............................................................. 1 General......................................................................................... 28
General Description ......................................................................... 1 Receiver........................................................................................ 28
Revision History ............................................................................... 2 Transmitter .................................................................................. 28
Specifications..................................................................................... 3 Clock Input Options .................................................................. 28
Current Consumption—VDD_INTERFACE........................... 8 Synthesizers ................................................................................. 28
Current Consumption—VDDD1P3_DIG and VDDAx Digital Data Interface................................................................. 29
(Combination of All 1.3 V Supplies) ....................................... 11 Enable State Machine ................................................................. 29
Absolute Maximum Ratings ..................................................... 15 SPI Interface ................................................................................ 30
Reflow Profile .............................................................................. 15 Control Pins ................................................................................ 30
Thermal Resistance .................................................................... 15 GPO Pins (GPO_3 to GPO_0) ................................................. 30
ESD Caution ................................................................................ 15 Auxiliary Converters.................................................................. 30
Pin Configuration and Function Descriptions ........................... 16 Packaging and Ordering Information ......................................... 32
Typical Performance Characteristics ........................................... 20 Outline Dimensions ................................................................... 32
800 MHz Frequency Band......................................................... 20 Ordering Guide .......................................................................... 32

REVISION HISTORY
11/2016—Revision D: Initial Version

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 Data Sheet AD9363

SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins (VDDA1P3_TX_LO, VDDA1P3_
TX_VCO_LDO, VDDA1P3_RX_LO, VDDA1P3_RX_VCO_LDO, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_TX_LO_BUFFER,
VDDA1P3_TX_SYNTH, VDDA1P3_RX_SYNTH, VDDD1P3_DIG, and VDDA1P3_BB) = 1.3 V, TA = 25°C, unless otherwise noted.

Table 1.
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
RECEIVERS, GENERAL
Center Frequency 325 3800 MHz
Rx Bandwidth 20 MHz
Gain
Minimum 0 dB
Maximum 74.5 dB At 800 MHz
73.0 dB At 2300 MHz (RX1A_x, RX2A_x)
72.0 dB At 2300 MHz (RX1B_x, RX1C_x, RX2B_x, RX2C_x)
Gain Step 1 dB
Received Signal Strength Indicator RSSI
Range 100 dB
Accuracy ±2 dB
RECEIVERS, 800 MHz
Noise Figure NF 2.5 dB Maximum Rx gain
Third-Order Input Intermodulation IIP3 −18 dBm Maximum Rx gain
Intercept Point
Second-Order Input Intermodulation IIP2 40 dBm Maximum Rx gain
Intercept Point
Local Oscillator (LO) Leakage −122 dBm At Rx front-end input
Quadrature
Gain Error 0.2 %
Phase Error 0.2 Degrees
Modulation Accuracy (EVM) −34 dB 19.2 MHz reference clock
Input Return Loss S11 −10 dB
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x 70 dB
RX1B_x to RX2B_x 55 dB
RX2_x to RX1_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x 70 dB
RX2B_x to RX1B_x 55 dB
RECEIVERS, 2.4 GHz
Noise Figure NF 3 dB Maximum Rx gain
Third-Order Input Intermodulation IIP3 −14 dBm Maximum Rx gain
Intercept Point
Second-Order Input Intermodulation IIP2 45 dBm Maximum Rx gain
Intercept Point
Local Oscillator (LO) Leakage −110 dBm At Rx front-end input
Quadrature
Gain Error 0.2 %
Phase Error 0.2 Degrees
Modulation Accuracy (EVM) −34 dB 40 MHz reference clock
Input Return Loss S11 −10 dB
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x 65 dB
RX1B_x to RX2B_x 50 dB

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 AD9363 Data Sheet
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
RX2x_x to RX1x_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x 65 dB
RX2B_x to RX1B_x 50 dB
RECEIVERS, 3.5 GHz
Noise Figure NF 3.3 dB Maximum Rx gain
Third-Order Input Intermodulation IIP3 −15 dBm Maximum Rx gain
Intercept Point
Second-Order Input Intermodulation IIP2 44 dBm Maximum Rx gain
Intercept Point
Local Oscillator (LO) Leakage −100 dBm At Rx front-end input
Quadrature
Gain Error 0.2 %
Phase Error 0.2 Degrees
Modulation Accuracy (EVM) −34 dB 40 MHz reference clock
Input Return Loss S11 −10 dB
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x 60 dB
RX1B_x to RX2B_x 48 dB
RX2x_x to RX1x_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x 60 dB
RX2B_x to RX1B_x 48 dB
TRANSMITTERS, GENERAL
Center Frequency 325 3800 MHz
Tx Bandwidth 20 MHz
Power Control Range 90 dB
Power Control Resolution 0.25 dB
TRANSMITTERS, 800 MHz
Output Return Loss S22 −10 dB
Maximum Output Power 8 dBm 1 MHz tone into 50 Ω load
Modulation Accuracy (EVM) −34 dB 19.2 MHz reference clock
Third-Order Output Intermodulation OIP3 23 dBm
Intercept Point
Carrier Leakage −50 dBc 0 dB attenuation
−32 dBc 40 dB attenuation
Noise Floor −157 dBm/Hz 90 MHz offset
Isolation
TX1x_x to TX2x_x 50 dB
TX2x_x to TX1x_x 50 dB
TRANSMITTERS, 2.4 GHz
Output Return Loss S22 −10 dB
Maximum Output Power 7.5 dBm 1 MHz tone into 50 Ω load
Modulation Accuracy (EVM) −34 dB 40 MHz reference clock
Third-Order Output Intermodulation OIP3 19 dBm
Intercept Point
Carrier Leakage −50 dBc 0 dB attenuation
−32 dBc 40 dB attenuation
Noise Floor −156 dBm/Hz 90 MHz offset
Isolation
TX1x_x to TX2x_x 50 dB
TX2x_x to TX1x_x 50 dB
TRANSMITTERS, 3.5 GHz
Output Return Loss S22 −10 dB
Maximum Output Power 7.0 dBm 1 MHz tone into 50 Ω load
Modulation Accuracy (EVM) −34 dB 40 MHz reference clock
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 Data Sheet AD9363
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
Third-Order Output Intermodulation OIP3 18 dBm
Intercept Point
Carrier Leakage −50 dBc 0 dB attenuation
−31 dBc 40 dB attenuation
Noise Floor −154 dBm/Hz 90 MHz offset
Isolation
TX1 to TX2 50 dB
TX2 to TX1 50 dB
1
When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

Table 2.
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
TX MONITOR INPUTS
(TX_MON1, TX_MON2)
Maximum Input Level 4 dBm
Dynamic Range 66 dB
Accuracy 1 dB
LO SYNTHESIZER
LO Frequency Step 2.4 Hz 2.4 GHz, 40 MHz reference clock
Integrated Phase Noise 0.3 °rms 100 Hz to 100 MHz
REFERENCE CLOCK (REF_CLK) REF_CLK is the input to the
XTALN pin
Input Frequency Range 10 80 MHz External oscillator
Input Signal Level 1.3 V p-p AC-coupled external oscillator
AUXILIARY ADC
Resolution 12 Bits
Input Voltage
Minimum 0.05 V
Maximum VDDA1P3_BB − V
0.05
AUXILIARY DAC
Resolution 10 Bits
Output Voltage
Minimum 0.5 V
Maximum VDD_GPO − 0.3 V
Output Current 10 mA
DIGITAL SPECIFICATIONS
(CMOS)
Logic Inputs
Input Voltage High VDD_INTERFACE × VDD_INTERFACE V
0.8
Input Voltage Low 0 VDD_INTERFACE × V
0.2
Input Current High −10 +10 μA
Input Current Low −10 +10 μA
Logic Outputs
Output Voltage High VDD_INTERFACE × VDD_INTERFACE V
0.8
Output Voltage Low 0 VDD_INTERFACE × V
0.2
DIGITAL SPECIFICATIONS (LVDS)
Logic Inputs
Input Voltage Range 825 1575 mV Each differential input in the
pair
Input Differential Voltage −100 +100 mV
Threshold
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 AD9363 Data Sheet
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
Receiver Differential Input 100 Ω
Impedance
Logic Outputs
Output Voltage High 1375 mV
Output Voltage Low 1025 mV
Output Differential 150 mV Programmable in 75 mV steps
Voltage
Output Offset Voltage 1200 mV
GENERAL-PURPOSE OUTPUTS
Output Voltage High VDD_GPO × 0.8 VDD_GPO V
Output Voltage Low 0 VDD_GPO × 0.2 V
Output Current 10 mA
SPI TIMING VDD_INTERFACE = 1.8 V
SPI_CLK
Period tCP 20 ns
Pulse Width tMP 9 ns
SPI_EN Setup to First tSC 1 ns
SPI_CLK Rising Edge
Last SPI_CLK Falling Edge to tHC 0 ns
SPI_ENB Hold
SPI_DI
Data Input Setup to tS 2 ns
SPI_CLK
Data Input Hold to tH 1 ns
SPI_CLK
SPI_CLK Rising Edge to
Output Data Delay
4-Wire Mode tCO 3 8 ns
3-Wire Mode tCO 3 8 ns
Bus Turnaround Time, Read tHZM tH tCO (MAX) ns After baseband processors
(Master) (BBP) drives the last address bit
Bus Turnaround Time, Read tHZS 0 tCO (MAX) ns After AD9363 drives the last
(Slave) data bit
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK_x Clock Period tCP 16.276 ns 61.44 MHz
DATA_CLK_x and FB_CLK_x tMP 45% of tCP 55% of tCP ns
Pulse Width
Tx Data TX_FRAME_x, P0_Dx, and
P1_Dx
Setup to FB_CLK_x tSTX 1 ns
Hold to FB_CLK_x tHTX 0 ns
DATA_CLK_x to Data Bus tDDRX 0 1.5 ns
Output Delay
DATA_CLK_x to tDDDV 0 1.0 ns
RX_FRAME_x Delay
Pulse Width
ENABLE tENPW tCP ns
TXNRX tTXNRXPW tCP ns FDD independent enable state
machine (ENSM) mode
TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode
Bus Turnaround Time TDD mode
Before Rx tRPRE 2 × tCP ns
After Rx tRPST 2 × tCP ns
Capacitive Load 3 pF
Capacitive Input 3 pF

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 Data Sheet AD9363
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK_x Clock Period tCP 16.276 ns 61.44 MHz
DATA_CLK_x and FB_CLK_x tMP 45% of tCP 55% of tCP ns
Pulse Width
Tx Data TX_FRAME_x, P0_Dx, and P1_Dx
Setup to FB_CLK_x tSTX 1 ns
Hold to FB_CLK_x tHTX 0 ns
DATA_CLK_x to Data Bus tDDRX 0.25 1.25 ns
Output Delay
DATA_CLK_x to tDDDV 0.25 1.25 ns
RX_FRAME_x Delay
Pulse Width
ENABLE tENPW tCP ns
TXNRX tTXNRXPW tCP ns FDD independent ENSM mode
TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode
Bus Turnaround Time TDD mode
Before Rx tRPRE 2 × tCP ns
After Rx tRPST 2 × tCP ns
Capacitive Load 3 pF
Capacitive Input 3 pF
DIGITAL DATA TIMING (LVDS)
DATA_CLK_x Clock Period tCP 4.069 ns 245.76 MHz
DATA_CLK_x and FB_CLK_x tMP 45% of tCP 55% of tCP ns
Pulse Width
Tx Data TX_FRAME_x and TX_Dx
Setup to FB_CLK_x tSTX 1 ns
Hold to FB_CLK_x tHTX 0 ns
DATA_CLK_x to Data Bus tDDRX 0 1.5 ns
Output Delay
DATA_CLK_x to tDDDV 0 1.0 ns
RX_FRAME_x Delay
Pulse Width
ENABLE tENPW tCP ns
TXNRX tTXNRXPW tCP ns FDD independent ENSM mode
TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode
Bus Turnaround Time
Before Rx tRPRE 2 × tCP ns
After Rx tRPST 2 × tCP ns
Capacitive Load 3 pF
Capacitive Input 3 pF
SUPPLY CHARACTERISTICS
1.3 V Main Supply 1.267 1.3 1.33 V
VDD_INTERFACE Supply
CMOS 1.2 2.5 V
LVDS 1.8 2.5 V
VDD_GPO Supply 1.3 3.3 3.465 V When unused, must be set to
1.3 V
Current Consumption
VDDx, Sleep Mode 180 µA Sum of all input currents
VDD_GPO 50 μA No load
1
When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

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 AD9363 Data Sheet
CURRENT CONSUMPTION—VDD_INTERFACE
Table 3. VDD_INTERFACE = 1.2 V
Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 45 μA Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DOUBLE
DATA RATE (DDR)
LTE10
Single Port 2.9 mA 30.72 MHz data clock, CMOS
Dual Port 2.7 mA 15.36 MHz data clock, CMOS
LTE20
Dual Port 5.2 mA 30.72 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port 1.3 mA 7.68 MHz data clock, CMOS
LTE10
Single Port 4.6 mA 61.44 MHz data clock, CMOS
Dual Port 5.0 mA 30.72 MHz data clock, CMOS
LTE20
Dual Port 8.2 mA 61.44 MHz data clock, CMOS
GSM
Dual Port 0.2 mA 1.08 MHz data clock, CMOS
WiMAX 8.75 MHz
Dual Port 3.3 mA 20 MHz data clock, CMOS
WiMAX 10 MHz
Single Port
TDD Rx 0.5 mA 22.4 MHz data clock, CMOS
TDD Tx 3.6 mA 22.4 MHz data clock, CMOS
FDD 3.8 mA 44.8 MHz data clock, CMOS
WiMAX 20 MHz
Dual Port
FDD 6.7 mA 44.8 MHz data clock, CMOS

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 Data Sheet AD9363
Table 4. VDD_INTERFACE = 1.8 V
Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 84 μA Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DDR
LTE10
Single Port 4.5 mA 30.72 MHz data clock, CMOS
Dual Port 4.1 mA 15.36 MHz data clock, CMOS
LTE20
Dual Port 8.0 mA 30.72 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port 2.0 mA 7.68 MHz data clock, CMOS
LTE10
Single Port 8.0 mA 61.44 MHz data clock, CMOS
Dual Port 7.5 mA 30.72 MHz data clock, CMOS
LTE20
Dual Port 14.0 mA 61.44 MHz data clock, CMOS
GSM
Dual Port 0.3 mA 1.08 MHz data clock, CMOS
WiMAX 8.75 MHz
Dual Port 5.0 mA 20 MHz data clock, CMOS
WiMAX 10 MHz
Single Port
TDD Rx 0.7 mA 22.4 MHz data clock, CMOS
TDD Tx 5.6 mA 22.4 MHz data clock, CMOS
FDD 6.0 mA 44.8 MHz data clock, CMOS
WiMAX 20 MHz
Dual Port
FDD 10.7 mA 44.8 MHz data clock, CMOS

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 AD9363 Data Sheet
Table 5. VDD_INTERFACE = 2.5 V
Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 150 μA Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DDR
LTE10
Single Port 6.5 mA 30.72 MHz data clock, CMOS
Dual Port 6.0 mA 15.36 MHz data clock, CMOS
LTE20
Dual Port 11.5 mA 30.72 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port 3.0 mA 7.68 MHz data clock, CMOS
LTE10
Single Port 11.5 mA 61.44 MHz data clock, CMOS
Dual Port 10.0 mA 30.72 MHz data clock, CMOS
LTE20
Dual Port 20.0 mA 61.44 MHz data clock, CMOS
GSM
Dual Port 0.5 mA 1.08 MHz data clock, CMOS
WiMAX 8.75 MHz
Dual Port 7.3 mA 20 MHz data clock, CMOS
WiMAX 10 MHz
Single Port
TDD Rx 1.3 mA 22.4 MHz data clock, CMOS
TDD Tx 8.0 mA 22.4 MHz data clock, CMOS
FDD 8.7 mA 44.8 MHz data clock, CMOS
WiMAX 20 MHz
Dual Port
FDD 15.3 mA 44.8 MHz data clock, CMOS

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 Data Sheet AD9363
CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES)
Table 6. TDD Mode, 800 MHz
Parameter Min Typ Max Unit Test Conditions/Comments
ONE Rx CHANNEL Continuous Rx
5 MHz BW 180 mA
10 MHz BW 210 mA
20 MHz BW 260 mA
TWO Rx CHANNELS Continuous Rx
5 MHz BW 265 mA
10 MHz BW 315 mA
20 MHz BW 405 mA
ONE Tx CHANNEL Continuous Tx
5 MHz BW
7 dBm 340 mA
−27 dBm 190 mA
10 MHz BW
7 dBm 360 mA
−27 dBm 220 mA
20 MHz BW
7 dBm 400 mA
−27 dBm 250 mA
TWO Tx CHANNELS Continuous Tx
5 MHz BW
7 dBm 550 mA
−27 dBm 260 mA
10 MHz BW
7 dBm 600 mA
−27 dBm 310 mA
20 MHz BW
7 dBm 660 mA
−27 dBm 370 mA

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 AD9363 Data Sheet
Table 7. TDD Mode, 2.4 GHz
Parameter Min Typ Max Unit Test Conditions/Comments
ONE Rx CHANNEL Continuous Rx
5 MHz BW 175 mA
10 MHz BW 200 mA
20 MHz BW 240 mA
TWO Rx CHANNELS Continuous Rx
5 MHz BW 260 mA
10 MHz BW 305 mA
20 MHz BW 390 mA
ONE Tx CHANNEL Continuous Tx
5 MHz BW
7 dBm 350 mA
−27 dBm 160 mA
10 MHz BW
7 dBm 380 mA
−27 dBm 220 mA
20 MHz BW
7 dBm 410 mA
−27 dBm 260 mA
TWO Tx CHANNELS Continuous Tx
5 MHz BW
7 dBm 580 mA
−27 dBm 280 mA
10 MHz BW
7 dBm 635 mA
−27 dBm 330 mA
20 MHz BW
7 dBm 690 mA
−27 dBm 390 mA

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 Data Sheet AD9363
Table 8. FDD Mode, 800 MHz
Parameter Min Typ Max Unit Test Conditions/Comments
ONE Rx CHANNEL, ONE Tx CHANNEL Continuous Rx and Tx
5 MHz BW
7 dBm 490 mA
−27 dBm 345 mA
10 MHz BW
7 dBm 540 mA
−27 dBm 395 mA
20 MHz BW
7 dBm 615 mA
−27 dBm 470 mA
TWO Rx CHANNELS, ONE Tx CHANNEL Continuous Rx and Tx
5 MHz BW
7 dBm 555 mA
−27 dBm 410 mA
10 MHz BW
7 dBm 625 mA
−27 dBm 480 mA
20 MHz BW
7 dBm 740 mA
−27 dBm 600 mA
ONE Rx CHANNEL, TWO Tx CHANNELS Continuous Rx and Tx
5 MHz BW
7 dBm 685 mA
−27 dBm 395 mA
10 MHz BW
7 dBm 755 mA
−27 dBm 465 mA
20 MHz BW
7 dBm 850 mA
−27 dBm 570 mA
TWO Rx CHANNELS, TWO Tx CHANNELS
5 MHz BW
7 dBm 790 mA
−27 dBm 495 mA
10 MHz BW
7 dBm 885 mA
−27 dBm 590 mA
20 MHz BW
7 dBm 1020 mA
−27 dBm 730 mA

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 AD9363 Data Sheet

Table 9. FDD Mode, 2.4 GHz

Parameter Min Typ Max Unit Test Conditions/Comments
ONE Rx CHANNEL, ONE Tx CHANNEL Continuous Rx and Tx
5 MHz BW
7 dBm 500 mA
−27 dBm 350 mA
10 MHz BW
7 dBm 540 mA
−27 dBm 390 mA
20 MHz BW
7 dBm 620 mA
−27 dBm 475 mA
TWO Rx CHANNELS, ONE Tx CHANNEL Continuous Rx and Tx
5 MHz BW
7 dBm 590 mA
−27 dBm 435 mA
10 MHz BW
7 dBm 660 mA
−27 dBm 510 mA
20 MHz BW
7 dBm 770 mA
−27 dBm 620 mA
ONE Rx CHANNEL, TWO Tx CHANNELS Continuous Rx and Tx
5 MHz BW
7 dBm 730 mA
−27 dBm 425 mA
10 MHz BW
7 dBm 800 mA
−27 dBm 500 mA
20 MHz BW
7 dBm 900 mA
−27 dBm 600 mA
TWO Rx CHANNELS, TWO Tx CHANNELS Continuous Rx and Tx
5 MHz BW
7 dBm 820 mA
−27 dBm 515 mA
10 MHz BW
7 dBm 900 mA
−27 dBm 595 mA
20 MHz BW
7 dBm 1050 mA
−27 dBm 740 mA

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 Data Sheet AD9363
ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE
Table 10. The AD9363 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
Parameter Rating
temperature is 260°C.
VDDx to VSSx −0.3 V to +1.4 V
VDD_INTERFACE to VSSx −0.3 V to +3.0 V THERMAL RESISTANCE
VDD_GPO to VSSx −0.3 V to +3.9 V Thermal performance is directly linked to printed circuit board
Logic Inputs and Outputs to VSSx −0.3 V to (PCB) design and operating environment.
VDD_INTERFACE + 0.3 V
Input Current to Any Pin Except ±10 mA Careful attention to PCB thermal design is required.
Supplies θJA is the natural convection junction to ambient thermal
RF Inputs (Peak Power) 2.5 dBm resistance measured in a one cubic foot sealed enclosure.
Tx Monitor Input Power (Peak Power) 9 dBm
θJC is the junction to case thermal resistance.
Package Power Dissipation (TJMAX − TA)/θJA
Maximum Junction Temperature (TJMAX) 110°C Table 11. Thermal Resistance
Temperature Range Package Airflow Velocity
Operating −40°C to +85°C Type (m/sec) θJA2 θJC3 Unit
Storage −65°C to +150°C BC-144-71 0 32.3 9.6 °C/W
Reflow 260°C 1.0 29.6 N/A4 °C/W
Stresses at or above those listed under Absolute Maximum 2.5 27.8 N/A4 °C/W
Ratings may cause permanent damage to the product. This is a 1
2
Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
stress rating only; functional operation of the product at these 3
Per MIL-STD-883, Method 1012.1.
or any other conditions above those indicated in the operational 4
N/A means not applicable.
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may ESD CAUTION
affect product reliability.

Rev. D | Page 15 of 32

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 AD9363 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 2 3 4 5 6 7 8 9 10 11 12

VDDA1P1_
A RX2A_N RX2A_P DNC VSSA TX_MON2 VSSA TX2A_N TX2A_P TX2B_N TX2B_P
TX_VCO
VSSA

VDDA1P3_ VDDA1P3_ TX_VCO_

B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO
TX_LO
TX_VCO_
LDO_OUT
VSSA
LDO

TEST/
C RX2C_P VSSA AUXDAC2 ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA

VDDA1P3_ VDDA1P3_ P0_D9/ P0_D7/ P0_D5/ P0_D3/ P0_D1/

D RX2C_N CTRL_OUT0 CTRL_IN3 CTRL_IN2 VSSD
RX_RF RX_TX TX_D4_P TX_D3_P TX_D2_P TX_D1_P TX_D0_P

VDDA1P3_ VDDA1P3_ P0_D11/ P0_D8/ P0_D6/ P0_D4/ P0_D2/ P0_D0/

E RX2B_P TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3
RX_LO TX_D5_P TX_D4_N TX_D3_N TX_D2_N TX_D1_N TX_D0_N
BUFFER
VDDA1P3_ P0_D10/ VDDD1P3_
F RX2B_N RX_VCO_ VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD TX_D5_N VSSD FB_CLK_P VSSD
DIG
LDO

RX_VCO_ VDDA1P1_ RX_ RX_ TX_ DATA_

G VSSA
LDO_OUT RX_VCO
CTRL_OUT7 EN_AGC ENABLE
FRAME_N FRAME_P FRAME_P
FB_CLK_N
CLK_P
VSSD

P1_D11/ TX_ DATA_ VDD_

H RX1B_P VSSA VSSA TXNRX VSSA VSSA VSSD
RX_D5_P FRAME_N
VSSD
CLK_N INTERFACE

VDDA1P3_ P1_D10/ P1_D9/ P1_D7/ P1_D5/ P1_D3/ P1_D1/

J RX1B_N VSSA RX_SYNTH SPI_DI SPI_CLK CLK_OUT RX_D5_N RX_D4_P RX_D3_P RX_D2_P RX_D1_P RX_D0_P

VDDA1P3_ VDDA1P3_ P1_D8/ P1_D6/ P1_D4/ P1_D2/ P1_D0/

K RX1C_P VSSA TX_SYNTH BB RESET SPI_EN RX_D4_N RX_D3_N RX_D2_N RX_D1_N RX_D0_N
VSSD

L RX1C_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA

M RX1A_P RX1A_N DNC VSSA TX_MON1 VSSA TX1A_P TX1A_N TX1B_P TX1B_N DNC XTALN

ANALOG I/O DC POWER

10558-002
DIGITAL I/O GROUND
DO NOT CONNECT

Figure 2. Pin Configuration, Top View

Table 12. Pin Function Descriptions

Pin No. Type1 Mnemonic Description
A1, A2 I RX2A_N, RX2A_P Receive Channel 2 Differential A Inputs. Alternatively, each pin can be used as a
single-ended input. Unused pins must be tied to ground.
A3, M3, M11 NC DNC Do Not Connect. Do not connect to these pins.
A4, A6, A12, GND VSSA Analog Ground. Tie these pins directly to the VSSD digital ground on the PCB
B1, B2, B12, (one ground plane).
C2, C7 to C12,
F3, G1, H2, H3,
H5, H6, J2, K2,
L2, L3, L7 to
L12, M4, M6
A5 I TX_MON2 Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground.
A7, A8 O TX2A_N, TX2A_P Transmit Channel 2 Differential A Outputs. Unused pins must be tied to 1.3 V.
A9, A10 O TX2B_N, TX2B_P Transmit Channel 2 Differential B Outputs. Unused pins must be tied to 1.3 V.
A11 P VDDA1P1_TX_VCO Transmit VCO Supply Input. Connect to B11.
B3 O AUXDAC1 Auxiliary DAC 1 Output. If using the auxiliary DAC, connect a 0.1 µF capacitor from
this pin to ground.
B4 to B7 O GPO_3 to GPO_0 3.3 V Capable General-Purpose Outputs.
B8 I VDD_GPO 2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. If the
VDD_GPO supply is not used, this supply must be set to 1.3 V.
B9 I VDDA1P3_TX_LO Transmit Local Oscillator (LO) 1.3 V Supply Input.
B10 I VDDA1P3_TX_VCO_LDO Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
B11 O TX_VCO_LDO_OUT Transmit VCO LDO Output. Connect to A11 and to a 1 μF bypass capacitor in series
with a 1 Ω resistor to ground.
C1, D1 I RX2C_P, RX2C_N Receive Channel 2 Differential C Inputs. Alternatively, use each pin as a single-ended
input. Unused pins must be tied to ground.
C3 O AUXDAC2 Auxiliary DAC 2 Output. If using the auxiliary DAC, connect a 0.1 µF capacitor from
this pin to ground.
C4 I TEST/ENABLE Test Input. Ground this pin for normal operation.
C5, C6, D5, D6 I CTRL_IN0 to CTRL_IN3 Control Inputs. Use these pins for manual Rx gain and Tx attenuation control.
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 Data Sheet AD9363
Pin No. Type1 Mnemonic Description
D2 I VDDA1P3_RX_RF Receiver 1.3 V Supply Input. Connect to D3.
D3 I VDDA1P3_RX_TX Receiver and Transmitter 1.3 V Supply Input.
D4, E4 to E6, O CTRL_OUT0, CTRL_OUT1 to Control Outputs. These pins are multipurpose outputs that have programmable
F4 to F6, G4 CTRL_OUT3, CTRL_OUT6 to functionality.
CTRL_OUT4, CTRL_OUT7
D7 I/O P0_D9/TX_D4_P Digital Data Port 0, Data Bit 9/Transmit Differential Input Bus, Data Bit 4. This is a dual
function pin. As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D4_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
D8 I/O P0_D7/TX_D3_P Digital Data Port 0, Data Bit 7/Transmit Differential Input Bus, Data Bit 3. This is a dual
function pin. As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D3_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
D9 I/O P0_D5/TX_D2_P Digital Data Port 0, Data Bit 5/Transmit Differential Input Bus, Data Bit 2. This is a dual
function pin. As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D2_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
D10 I/O P0_D3/TX_D1_P Digital Data Port 0, Data Bit 3/Transmit Differential Input Bus, Data Bit 1. This is a dual
function pin. As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D1_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
D11 I/O P0_D1/TX_D0_P Digital Data Port 0, Data Bit 1/Transmit Differential Input Bus, Data Bit 0. This is a dual
function pin. As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D0_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
D12, F7, F9, GND VSSD Digital Ground. Tie these pins directly to the VSSA analog ground on the PCB (one
F11, G12, H7, ground plane).
H10, K12
E1, F1 I RX2B_P, RX2B_N Receive Channel 2 Differential B Inputs. Alternatively, each pin can be used as a
single-ended input. Unused pins must be tied to ground.
E2 I VDDA1P3_RX_LO Receive LO 1.3 V Supply Input.
E3 I VDDA1P3_TX_LO_BUFFER Transmitter LO Buffer 1.3 V Supply Input.
E7 I/O P0_D11/TX_D5_P Digital Data Port 0, Data Bit 11/Transmit Differential Input Bus, Data Bit 5. This is a
dual function pin. As P0_D11, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 0. Alternatively, as TX_D5_P, it functions as part of the LVDS 6-
bit Tx differential input bus with internal LVDS termination.
E8 I/O P0_D8/TX_D4_N Digital Data Port 0, Data Bit 8/Transmit Differential Input Bus, Data Bit 4. This is a dual
function pin. As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D4_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
E9 I/O P0_D6/TX_D3_N Digital Data Port 0, Data Bit 6/Transmit Differential Input Bus, Data Bit 3. This is a dual
function pin. As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D3_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
E10 I/O P0_D4/TX_D2_N Digital Data Port 0, Data Bit 4/Transmit Differential Input Bus, Data Bit 2. This is a dual
function pin. As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D2_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
E11 I/O P0_D2/TX_D1_N Digital Data Port 0, Data Bit 2/Transmit Differential Input Bus, Data Bit 1. This is a dual
function pin. As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D1_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
E12 I/O P0_D0/TX_D0_N Digital Data Port 0, Data Bit 0/Transmit Differential Input Bus, Data Bit 0. This is a dual
function pin. As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D0_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
F2 I VDDA1P3_RX_VCO_LDO Receive VCO LDO 1.3 V Supply Input. Connect to E2.

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 AD9363 Data Sheet
Pin No. Type1 Mnemonic Description
F8 I/O P0_D10/TX_D5_N Digital Data Port 0, Data Bit 10/Transmit Differential Input Bus, Data Bit 5. This is a
dual function pin. As P0_D10, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 0. Alternatively, as TX_D5_N, it functions as part of the LVDS 6-
bit Tx differential input bus with internal LVDS termination.
F10, G10 I FB_CLK_P, FB_CLK_N Feedback Clock Inputs. These pins receive the FB_CLK signal that clocks in Tx data. In
CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.
F12 I VDDD1P3_DIG 1.3 V Digital Supply Input.
G2 O RX_VCO_LDO_OUT Receive VCO LDO Output. Connect to G3 and to a 1 μF bypass capacitor in series
with a 1 Ω resistor to ground.
G3 I VDDA1P1_RX_VCO Receive VCO Supply Input. Connect to G2.
G5 I EN_AGC Manual Control Input for Automatic Gain Control (AGC).
G6 I ENABLE Control Input. This pin moves the device through various operational states.
G7, G8 O RX_FRAME_N, Receive Digital Data Framing Outputs. These pins transmit the RX_FRAME signal that
RX_FRAME_P indicates whether the Rx output data is valid. In CMOS mode, use RX_FRAME_P as
the output and leave RX_FRAME_N unconnected.
G9, H9 I TX_FRAME_P, Transmit Digital Data Framing Inputs. These pins receive the TX_FRAME signal that
TX_FRAME_N indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as the input and tie
TX_FRAME_N to ground.
G11, H11 O DATA_CLK_P, Receive Data Clock Outputs. These pins transmit the DATA_CLK signal that the BBP
DATA_CLK_N uses to clock the Rx data. In CMOS mode, use DATA_CLK_P as the output and leave
DATA_CLK_N unconnected.
H1, J1 I RX1B_P, RX1B_N Receive Channel 1 Differential B Inputs. Alternatively, use each pin as a single-ended
input. Unused pins must be tied to ground.
H4 I TXNRX Enable State Machine Control Signal. This pin controls the data port bus direction. A
logic low selects the Rx direction; a logic high selects the Tx direction.
H8 I/O P1_D11/RX_D5_P Digital Data Port P1, Data Bit 11/Receive Differential Output Bus, Data Bit 5. This is a
dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D5_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
H12 I VDD_INTERFACE 1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).
J3 I VDDA1P3_RX_SYNTH Receiver Synthesizer 1.3 V Supply Input.
J4 I SPI_DI SPI Serial Data Input.
J5 I SPI_CLK SPI Clock Input.
J6 O CLK_OUT Output Clock. This pin can be configured to output either a buffered version of the
external input clock (the digital controlled crystal oscillator (DCXO)) or a divided-
down version of the internal ADC sample clock (ADC_CLK).
J7 I/O P1_D10/RX_D5_N Digital Data Port 1, Data Bit 10/Receive Differential Output Bus, Data Bit 5. This is a
dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D5_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
J8 I/O P1_D9/RX_D4_P Digital Data Port 1, Data Bit 9/Receive Differential Output Bus, Data Bit 4. This is a
dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D4_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
J9 I/O P1_D7/RX_D3_P Digital Data Port 1, Data Bit 7/Receive Differential Output Bus, Data Bit 3. This is a
dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D3_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
J10 I/O P1_D5/RX_D2_P Digital Data Port 1, Data Bit 5/Receive Differential Output Bus, Data Bit 2. This is a
dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D2_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
J11 I/O P1_D3/RX_D1_P Digital Data Port 1, Data Bit 3/Receive Differential Output Bus, Data Bit 1. This is a
dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D1_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.

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 Data Sheet AD9363
Pin No. Type1 Mnemonic Description
J12 I/O P1_D1/RX_D0_P Digital Data Port 1, Data Bit 1/Receive Differential Output Bus, Data Bit 0. This is a
dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D0_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K1, L1 I RX1C_P, RX1C_N Receive Channel 1 Differential C Inputs. Alternatively, use each pin as a single-ended
input. Tie unused pins to ground.
K3 I VDDA1P3_TX_SYNTH Transmitter Synthesizer 1.3 V Supply Input. Connect this pin to a 1.3 V regulator
through a separate trace to a common supply point.
K4 I VDDA1P3_BB Baseband 1.3 V Supply Input. Connect this pin to a 1.3 V regulator through a
separate trace to a common supply point.
K5 I RESET Asynchronous Reset Input. A logic low resets the device.
K6 I SPI_EN SPI Enable. Set this pin to logic low to enable the SPI bus.
K7 I/O P1_D8/RX_D4_N Digital Data Port 1, Data Bit 8/Receive Differential Output Bus, Data Bit 4. This is a
dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D4_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K8 I/O P1_D6/RX_D3_N Digital Data Port 1, Data Bit 6/Receive Differential Output Bus, Data Bit 3. This is a
dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D3_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K9 I/O P1_D4/RX_D2_N Digital Data Port 1, Data Bit 4/Receive Differential Output Bus, Data Bit 2. This is a
dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D2_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K10 I/O P1_D2/RX_D1_N Digital Data Port 1, Data Bit 2/Receive Differential Output Bus, Data Bit 1. This is a
dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D1_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K11 I/O P1_D0/RX_D0_N Digital Data Port 1, Data Bit 0/Receive Differential Output Bus, Data Bit 0. This is a
dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D0_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
L4 I RBIAS Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor to
ground.
L5 I AUXADC Auxiliary ADC Input. If this pin is unused, tie it to ground.
L6 O SPI_DO SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.
M1, M2 I RX1A_P, RX1A_N Receive Channel 1 Differential A Inputs. Alternatively, use each pin as a single-ended
input. Tie unused pins to ground.
M5 I TX_MON1 Transmit Channel 1 Power Monitor Input. If this pin is unused, tie it to ground.
M7, M8 O TX1A_P, TX1A_N Transmit Channel 1 Differential A Outputs. Tie unused pins to 1.3 V.
M9, M10 O TX1B_P, TX1B_N Transmit Channel 1 Differential B Outputs. Tie unused pins to 1.3 V.
M12 I XTALN Reference Frequency Connection. Connect the external clock source to XTALN.
1
I is input, NC is not connected, GND is ground, O is output, P is power, and I/O is input/output.

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 AD9363 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

ATTEN is the attenuation setting. fLO_RX and fLO_TX are the receive and transmit local oscillator frequencies, respectively.
800 MHZ FREQUENCY BAND
4.0 0
–40°C
–40°C +25°C
3.5 +25°C +85°C
+85°C

3.0 –4
Rx NOISE FIGURE (dB)

2.5

Rx EVM (dB)
2.0 –8

1.5

1.0 –12

0.5

0 –16

10558-007
10558-003

700 750 800 850 900 –56 –54 –52 –50 –48 –46 –44 –42 –40 –38 –36

RF FREQUENCY (MHz) INTERFERER POWER LEVEL (dBm)

Figure 3. Rx Noise Figure vs. RF Frequency Figure 6. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest
with PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset
5 14
–40°C –40°C
+25°C +25°C
4 +85°C +85°C
12

3
Rx NOISE FIGURE (dB)

10
RSSI ERROR (dB)

2
8
1

6
0

–1 4

–2 2

–3 0
10558-004

10558-008
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
–47 –43 –39 –35 –31 –27 –23
Rx INPUT POWER (dBm) INTERFERER POWER LEVEL (dBm)

Figure 4. RSSI Error vs. Rx Input Power, LTE 10 MHz Modulation Figure 7. Rx Noise Figure vs. Interferer Power Level, Enhanced Data Rates for
(Referenced to −50 dBm Input Power at 800 MHz) GSM Evolution (EDGE) Signal of Interest with PIN = −90 dBm, Continuous
Wave (CW) Blocker at 3 MHz Offset, Gain Index = 64
0 80
–40°C –40°C
+25°C +25°C
+85°C +85°C
–5 78

76
–10
Rx EVM (dB)

Rx GAIN (dB)

74
–15
72

–20
70

–25
68

–30 66
10558-006

10558-009

–72 –68 –64 –60 –56 –52 –48 –44 –40 –36 –32 700 750 800 850 900
INTERFERER POWER LEVEL (dBm) Rx LO FREQUENCY (MHz)

Figure 5. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest Figure 8. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting)
with PIN = −82 dBm, 5 MHz Orthogonal Frequency Division Multiplexing
(OFDM) Blocker at 7.5 MHz Offset
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 Data Sheet AD9363
20 0

Rx EMISSION AT LNA INPUT (dBm/750kHz)

15
–20
10

5 –40
IIP3 (dBm)

0
–60
–5
–40°C
–10 +25°C –80
+85°C
–15
–100
–20

–25 –120

10558-010

10558-013
20 28 36 44 52 60 68 76 0 2000 4000 6000 8000 10000 12000
Rx GAIN INDEX FREQUENCY (MHz)

Figure 9. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index, Figure 12. Rx Emission at LNA Input vs. Frequency, DC to 12 GHz, fLO_RX = 800
f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode MHz, LTE 10 MHz, fLO_TX = 860 MHz

100 10.0
–40°C
+25°C
90 +85°C
9.5
80

Tx OUTPUT POWER (dBm)

9.0
70
8.5
60
IIP2 (dBm)

50 8.0

40 7.5
30
7.0
20
–40°C 6.5
10 +25°C
+85°C
0 6.0

10558-014
10558-011

20 28 36 44 52 60 68 76 700 750 800 850 900

Rx GAIN INDEX Tx LO FREQUENCY (MHz)

Figure 10. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, Figure 13. Tx Output Power vs. Tx LO Frequency, Attenuation Setting = 0 dB,
f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode Single-Tone Output
–100
Tx POWER CONTROL STEP LINEARITY ERROR (dB)

0.5
–40°C –40°C
+25°C +25°C
+85°C 0.4 +85°C
–105
0.3
Rx LO LEAKAGE (dBm)

0.2
–110
0.1

–115 0

–0.1
–120
–0.2

–0.3
–125
–0.4

–130 –0.5
10558-012

10558-015

700 750 800 850 900 0 10 20 30 40 50

Rx LO FREQUENCY (MHz) ATTENUATION SETTING (dB)

Figure 11. Rx LO Leakage vs. Rx LO Frequency Figure 14. Tx Power Control Step Linearity Error vs. Attenuation Setting

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 AD9363 Data Sheet

Tx SECOND-ORDER HARMONIC DISTORTION (dBc)

0 –50
ATT 0dB ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C
ATT 3dB ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C
–10 ATT 6dB ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C
–55
Tx OUTPUT POWER (dBm/100kHz)

–20

–30
–60
–40

–50 –65

–60
–70
–70

–80
–75
–90

–100 –80

10558-016

10558-021
–15 –10 –5 0 5 10 15 700 750 800 850 900
FREQUENCY OFFSET FROM CARRIER FREQUENCY (MHz) FREQUENCY (MHz)

Figure 15. Tx Output Power vs. Frequency Offset from Carrier Frequency, Figure 18. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency
fLO_TX = 800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown)
0.5 –20

Tx THIRD-ORDER HARMONIC DISTORTION (dBc)

–40°C ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C
+25°C ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C
INTEGRATED Tx LO PHASE NOISE (°rms)

+85°C –25 ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C
0.4
–30

–35
0.3

–40

0.2
–45

–50
0.1
–55

0 –60
10558-019

10558-022
700 750 800 850 900 700 750 800 850 900
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 16. Integrated Tx LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK Figure 19. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency

–30 30
ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C –40°C
ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C +25°C
–35 ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C +85°C
25
Tx CARRIER REJECTION (dBc)

–40

20
Tx OIP3 (dBm)

–45

–50 15

–55
10
–60

5
–65

–70 0
10558-020

10558-023

700 750 800 850 900 0 4 8 12 16 20

FREQUENCY (MHz) Tx ATTENUATION SETTING (dB)

Figure 17. Tx Carrier Rejection vs. Frequency Figure 20. Tx Third-Order Output Intercept Point (OIP3) vs. Tx Attenuation Setting

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 Data Sheet AD9363
170 –30
–40°C ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C
+25°C ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C

Tx SINGLE SIDEBAND REJECTION (dBc)

+85°C –35 ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C
165

–40
160
Tx SNR (dB/Hz)

–45

155 –50

–55
150

–60
145
–65

140 –70

10558-024

10558-026
0 3 6 9 12 15 700 750 800 850 900
Tx ATTENUATION SETTING (dB) FREQUENCY (MHz)

Figure 21. Tx Signal-to-Noise Ratio (SNR) vs. Tx Attenuation Setting, Figure 22. Tx Single Sideband Rejection vs. Frequency,
LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset 1.5375 MHz Offset

Rev. D | Page 23 of 32

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 AD9363 Data Sheet
2.4 GHZ FREQUENCY BAND
4.0 0
–40°C
+25°C
3.5 +85°C
–5

3.0
Rx NOISE FIGURE (dB)

–10
2.5

RX EVM (dB)
2.0 –15

1.5
–20
1.0

–25
0.5 –40°C
+25°C
+85°C
0 –30

10558-027

10558-043
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 –60 –55 –50 –45 –40 –35 –30 –25 –20
RF FREQUENCY (MHz) INTERFERER POWER LEVEL (dBm)

Figure 23. Rx Noise Figure vs. RF Frequency Figure 26. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest
with PIN = −75 dBm, LTE 20 MHz Blocker at 40 MHz Offset
5 80
–40°C –40°C
+25°C +25°C
4 +85°C +85°C
78

3
76
RSSI ERROR (dB)

2
Rx GAIN (dB)

74
1

72
0

70
–1

–2 68

–3 66
10558-028

10558-029
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
INPUT POWER (dBm) Rx LO FREQUENCY (MHz)

Figure 24. RSSI Error vs. Input Power (Referenced to −50 dBm Input Power Figure 27. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting)
at 2.4 GHz)
0 20
–40°C –40°C
+25°C +25°C
+85°C 15 +85°C
–5
10

–10 5
RX EVM (dB)

IIP3 (dBm)

0
–15
–5

–20 –10

–15
–25
–20

–30 –25
10558-030
10558-042

–72 –68 –64 –60 –56 –52 –48 –44 –40 –36 –32 –28 20 28 36 44 52 60 68 76

INTERFERER POWER LEVEL (dBm) Rx GAIN INDEX

Figure 25. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest Figure 28. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,
with PIN = −75 dBm, LTE 20 MHz Blocker at 20 MHz Offset f1 = 30 MHz, f2 = 61 MHz

Rev. D | Page 24 of 32

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 Data Sheet AD9363
80 10.0
–40°C –40°C
+25°C +25°C
+85°C 9.5 +85°C
70

Tx OUTPUT POWER (dBm)

9.0
60
8.5
IIP2 (dBm)

50 8.0

7.5
40

7.0
30
6.5

20 6.0

10558-031

10558-033
20 28 36 44 52 60 68 76 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
Rx GAIN INDEX Tx LO FREQUENCY (MHz)

Figure 29. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, Figure 32. Tx Output Power vs. Tx LO Frequency, Attenuation Setting = 0 dB,
f1 = 60 MHz, f2 = 61 MHz Single-Tone Output

0.5

Tx POWER CONTROL STEP LINEARITY ERROR (dB)

–100
–40°C –40°C
+25°C +25°C
+85°C 0.4 +85°C
–105
0.3
Rx LO LEAKAGE (dBm)

0.2
–110
0.1

–115 0

–0.1
–120
–0.2

–0.3
–125
–0.4

–130 –0.5

10558-034
10558-032

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 0 10 20 30 40 50
Rx LO FREQUENCY (MHz) ATTENUATION SETTING (dB)

Figure 30. Rx Local Oscillator (LO) Leakage vs. Rx LO Frequency Figure 33. Tx Power Control Step Linearity Error vs. Attenuation Setting

0 0
ATT 0dB
ATT 3dB
Rx EMISSION AT LNA INPUT (dBm/750kHz)

ATT6dB
–20 –20
Tx OUTPUT POWER (dBm/100kHz)

–40 –40

–60 –60

–80 –80

–100 –100

–120 –120
10558-045
10558-044

0 2000 4000 6000 8000 10000 12000 –25 –20 –15 –10 –5 0 5 10 15 20 25
FREQUENCY (MHz) FREQUENCY OFFSET FROM CARRIER FREQUENCY (MHz)

Figure 31. Rx Emission at LNA Input vs. Frequency, DC to 12 GHz, Figure 34. Tx Output Power vs. Frequency Offset from Carrier Frequency,
fLO_RX = 2.4 GHz, LTE 20 MHz, fLO_TX = 2.46 GHz fLO_TX = 2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation
Variations Shown)

Rev. D | Page 25 of 32

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 AD9363 Data Sheet
0.5

Tx SECOND-ORDER HARMONIC DISTORTION (dBc)

–50
–40°C ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C
+25°C ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C
INTEGRATED Tx LO PHASE NOISE (°rms)

+85°C ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C
–55
0.4

–60
0.3

–65

0.2
–70

0.1
–75

0 –80

10558-035

10558-037
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 35. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK Figure 37. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency

–30 –20

Tx THIRD-ORDER HARMONIC DISTORTION (dBc)

ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C
ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C
–35 ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C –25 ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C
Tx CARRIER REJECTION (dBc)

–40 –30

–45 –35

–50 –40

–55 –45

–60 –50

–65 –55

–70 –60
10558-036

10558-038
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 36. Tx Carrier Rejection vs. Frequency Figure 38. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency

Rev. D | Page 26 of 32

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 Data Sheet AD9363
30 –30
–40°C ATT 0, –40°C ATT 0, +25°C ATT 0, +85°C
+25°C ATT 25, –40°C ATT 25, +25°C ATT 25, +85°C

Tx SINGLE SIDEBAND REJECTION (dBc)

+85°C –35 ATT 50, –40°C ATT 50, +25°C ATT 50, +85°C
25

–40
20
Tx OIP3 (dBm)

–45

15 –50

–55
10

–60
5
–65

0 –70

10558-039

10558-041
0 4 8 12 16 20 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
Tx ATTENUATION SETTING (dB) FREQUENCY (MHz)

Figure 39. Tx Third-Order Output Intercept Point (OIP3) vs. Tx Attenuation Setting Figure 41. Tx Single Sideband Rejection vs. Frequency,
3.075 MHz Offset

160
–40°C
+25°C
158 +85°C

156

154
Tx SNR (dB/Hz)

152

150

148

146

144

142

140
10558-040

0 3 6 9 12 15
Tx ATTENUATION SETTING (dB)

Figure 40. Tx Signal-to-Noise Ratio (SNR) vs. Tx Attenuation Setting,

LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset

Rev. D | Page 27 of 32

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 AD9363 Data Sheet

THEORY OF OPERATION
GENERAL TRANSMITTER
The AD9363 is a highly integrated radio frequency (RF) The transmitter section consists of two identical and indepen-
transceiver capable of being configured for a wide range of dently controlled channels that provide all digital processing,
applications. The device integrates all RF, mixed-signal, and mixed-signal, and RF blocks necessary to implement a direct
digital blocks necessary to provide all transceiver functions in a conversion system while sharing a common frequency synthe-
single device. Programmability allows this broadband transceiver sizer. The digital data received from the BBP passes through a
to be adapted for use with multiple communication standards, fully programmable 128-tap FIR filter with interpolation options.
including FDD and TDD systems. This programmability also The FIR output is sent to a series of interpolation filters that
allows the device to interface to various BBPs using a single 12- provide additional filtering and data rate interpolation prior to
bit parallel data port, dual 12-bit parallel data ports, or a 12-bit reaching the DAC. Each 12-bit DAC has an adjustable sampling
low voltage differential signaling (LVDS) interface. rate. Both the I and Q channels are fed to the RF block for
The AD9363 also provides self calibration and AGC systems to upconversion.
maintain a high performance level under varying temperatures After being converted to baseband analog signals, the I and Q
and input signal conditions. In addition, the device includes signals are filtered to remove sampling artifacts and provide band
several test modes that allow system designers to insert test tones shaping, and then they are passed to the upconversion mixers.
and create internal loopback modes to debug their designs At this point, the I and Q signals are recombined and modulated
during prototyping and optimize their radio configuration for a on the carrier frequency for transmission to the output stage.
specific application. The output stage provides attenuation control that provides a
range of output levels while keeping the output impedance at 50 Ω.
RECEIVER
A wide range of attenuation adjustment with fine granularity is
The receiver section contains all blocks necessary to receive RF included to help designers optimize SNR.
signals and convert them to digital data that is usable by a BBP.
Two independently controlled channels can receive signals from Self calibration circuitry is included in the transmit channel to
different sources, allowing the device to be used in multiple provide internal adjustment capability. The transmitter also
input, multiple output (MIMO) systems while sharing a provides a Tx monitor block that receives the transmitter output
common frequency synthesizer. and routes it back through an unused receiver channel to the
BBP for signal monitoring. The Tx monitor blocks are available
Each channel has three inputs that can be multiplexed to the only in TDD mode operation while the receiver is idle.
signal chain, making the AD9363 suitable for use in diversity
systems with multiple antenna inputs. The receiver is a direct CLOCK INPUT OPTIONS
conversion system that contains a low noise amplifier (LNA) The AD9363 uses a reference clock provided by an external
followed by matched in-phase (I) and quadrature (Q) amplifiers, oscillator or clock distribution device (such as the AD9548)
mixers, and band shaping filters that downconvert received connected to the XTALN pin. The frequency of this reference
signals to baseband for digitization. External LNAs can also clock can vary from 10 MHz to 80 MHz. This reference clock
be interfaced to the device, allowing designers the flexibility to supplies the synthesizer blocks that generate all data clocks,
customize the receiver front end for their specific application. sample clocks, and local oscillators inside the device.
Gain control is achieved by following a preprogrammed gain SYNTHESIZERS
index map that distributes gain among the blocks for optimal RF PLLs
performance at each level. This gain control can be achieved by
The AD9363 contains two identical synthesizers to generate the
enabling the internal AGC in either fast or slow mode or by
required LO signals for the RF signal paths—one for the receiver
using manual gain control, allowing the BBP to make the gain
and one for the transmitter. PLL synthesizers are fractional N
adjustments as needed. Additionally, each channel contains
designs that incorporate completely integrated VCOs and loop
independent RSSI measurement capability, dc offset tracking,
filters. In TDD mode, the synthesizers turn on and off as appropri-
and all circuitry necessary for self calibration.
ate for the Rx and Tx frames. In FDD mode, the Tx PLL and the
The receivers include 12-bit, sigma-delta (Σ-Δ) ADCs and adjust- Rx PLL can be activated at the same time. These PLLs require no
able sample rates that produce data streams from the received external components.
signals. The digitized signals can be conditioned further by a
series of decimation filters and a fully programmable 128-tap
FIR filter with additional decimation settings. The sample rate
of each digital filter block can also be adjusted by changing the
decimation factors to produce the desired output data rate.

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 Data Sheet AD9363
BB PLL ENABLE STATE MACHINE
The AD9363 also contains a baseband PLL (BB PLL) synthesizer The AD9363 transceiver includes an ENSM that allows real-
that generates all baseband related clock signals. These signals time control over the current state of the device. The device can
include the ADC and DAC sampling clocks, the DATA_CLK signal be placed in several different states during normal operation,
(see the Digital Data Interface section), and all data framing including
signals. The BB PLL is programmed from 700 MHz to 1400 MHz
• Wait—power save, synthesizers disabled
based on the data rate and sample rate requirements of the system.
• Sleep—wait with all clocks and the BB PLL disabled
DIGITAL DATA INTERFACE • Tx—Tx signal chain enabled
The AD9363 data interface uses parallel data ports (P0 and P1) • Rx—Rx signal chain enabled
to transfer data between the device and the BBP. The data ports • FDD—Tx and Rx signal chains enabled
can be configured in either single-ended CMOS format or dif- • Alert—synthesizers enabled
ferential LVDS format. Both formats can be configured in multiple
arrangements to match system requirements for data ordering The ENSM has two control modes: SPI control and pin control.
and data port connections. These arrangements include single SPI Control Mode
port data bus, dual port data bus, single data rate, double data In SPI control mode, the ENSM is controlled asynchronously by
rate, and various combinations of data ordering to transmit data writing to SPI registers to advance the current state to the next
from different channels across the bus at appropriate times. state. SPI control is considered asynchronous to the DATA_CLK
Bus transfers are controlled using simple hardware handshake signal because the SPI clock can be derived from a different
signaling. The two ports can be operated in either bidirectional clock reference and can still function properly. The SPI control
(TDD) mode or in full duplex (FDD) mode, where half the bits ENSM mode is recommended when real-time control of the
are used for transmitting data and half are used for receiving synthesizers is not necessary. SPI control can be used for real-
data. The interface can also be configured to use only one of the time control as long as the BBP can perform timed SPI writes
data ports for applications that do not require high data rates accurately.
and require fewer interface pins. Pin Control Mode
DATA_CLK Signal In pin control mode, the enable functions of the ENABLE pin
The AD9363 outputs the DATA_CLK signal that the BBP uses and the TXNRX pin allow real-time control of the current state.
to sample receiver data. The signal is synchronized with the The ENSM allows TDD or FDD operation, depending on the
receiver data such that data transitions occur out of phase with configuration of the corresponding SPI register. The ENABLE
DATA_CLK. The DATA_CLK can be set to a rate that provides and TXNRX pin control mode is recommended if the BBP has
single data rate (SDR) timing, where data is sampled on each rising extra control outputs that can be controlled in real time, allow-
clock edge, or it can be set to provide double data rate (DDR) ing a simple 2-wire interface to control the state of the device.
timing, where data is captured on both rising and falling clock To advance the current state of the ENSM to the next state,
edges. SDR or DDR timing applies to operation using either a drive the enable function of the ENABLE pin by either a pulse
single port or both ports. (edge detected internally) or a level.
FB_CLK Signal When a pulse is used, it must have a minimum pulse width of
For transmit data, the interface uses the FB_CLK signal as the one cycle of the FB_CLK signal. In level mode, the ENABLE
timing reference. The FB_CLK signal allows source synchro- and TXNRX pins are also edge detected by the AD9363 and
nous timing with rising edge capture for burst control signals must meet the same minimum pulse width requirement of one
and either rising edge capture (SDR mode) or both edge capture cycle of the FB_CLK signal.
(DDR mode) for transmit signal bursts. The FB_CLK signal In FDD mode, the ENABLE and TXNRX pins can be remapped
must have the same frequency and duty cycle as DATA_CLK. to serve as real-time Rx and Tx data transfer control signals. In
RX_FRAME and TX_FRAME Signals this mode, the ENABLE pin assumes the receive on (RXON)
function (controls when the Rx path is enabled and disabled), and
The device generates an RX_FRAME output signal whenever the TXNRX pin assumes the transmit on (TXON) function
the receiver outputs valid data. This signal has two modes: level (controls when the Tx path is enabled and disabled). The ENSM
mode (the RX_FRAME signal stays high as long as the data is must be controlled by SPI writes in this mode while the ENABLE
valid) and pulse mode (the RX_FRAME signal pulses with a 50% and TXNRX pins control all data flow. For more information
duty cycle). Similarly, the BBP must provide a TX_FRAME about RXON and TXON, see the AD9363 reference manual,
signal that indicates the beginning of a valid data transmission available from Integrated Wideband RF Transceiver Design
with a rising edge. Like the RX_FRAME signal, the TX_FRAME Resources.
signal stays high throughout the burst or it pulses with a 50% duty
cycle.

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 AD9363 Data Sheet
SPI INTERFACE AUXILIARY CONVERTERS
The AD9363 uses a serial peripheral interface (SPI) to communi- AUXADC
cate with the BBP. The SPI can be configured as a 4-wire interface The AD9363 contains an auxiliary ADC that monitors system
with dedicated receive and transmit ports, or it can be configured functions such as temperature or power output. The converter is
as a 3-wire interface with a bidirectional data communication 12 bits wide and has an input range of 0.05 V to VDDA1P3_BB −
port. This bus allows the BBP to set all device control parameters 0.05 V. When enabled, the ADC is free running. SPI reads
using a simple address data serial bus protocol. provide the last value latched at the ADC output. A multiplexer in
Write commands follow a 24-bit format. The first six bits set the front of the ADC allows the user to select between the AUXADC
bus direction and number of bytes to transfer. The next 10 bits set input pin and a built-in temperature sensor.
the address where data is to be written. The final eight bits are the AUXDAC1 and AUXDAC2
data to be transferred to the specified register address (MSB to
The AD9363 contains two identical auxiliary DACs that can
LSB). The AD9363 also supports an LSB first format that allows
provide power amplifier (PA) bias or other system functionality.
the commands to be written in LSB to MSB format. In this mode,
The auxiliary DACs are 10 bits wide, have an output voltage range
the register addresses are incremented for multibyte writes.
of 0.5 V to VDD_GPO − 0.3 V and a current drive of 10 mA, and
Read commands follow a similar format with the exception that can be directly controlled by the internal ENSM.
the first 16 bits are transferred on the SPI_DI pin, and the final
eight bits are read from the AD9363, either on the SPI_DO pin
POWERING THE AD9363
in 4-wire mode or on the SPI_DI pin in 3-wire mode. The AD9363 must be powered by the following three supplies:
the analog supply (VDDx = 1.3 V), the interface supply (VDD_
CONTROL PINS INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V).
Control Outputs (CTRL_OUT7 to CTRL_OUT0)
For applications requiring optimal noise performance, split and
The AD9363 provides eight simultaneous real-time output source the 1.3 V analog supply from low noise, low dropout
signals for use as interrupts to the BBP. These outputs can (LDO) regulators. Figure 42 shows the recommended method.
be configured to output a number of internal settings and 3.3V
measurements that the BBP uses when monitoring trans-ceiver
performance in different situations. The control output pointer ADP2164 1.8V
register selects the information that is output to these pins, and
the control output enable register determines which signals are ADP1755 1.3V_A

10558-074
activated for monitoring by the BBP. Signals used for manual
ADP1755 1.3V_B
gain mode, calibration flags, state machine states, and the ADC
output are among the outputs that can be monitored on these Figure 42. Low Noise Power Solution for the AD9363
pins. For applications where board space is at a premium, and
Control Inputs (CTRL_IN3 to CTRL_IN0) optimal noise performance is not an absolute requirement,
The AD9363 provides four edge detected control input pins. In provide the 1.3 V analog rail directly from a switcher, and adopt
manual gain mode, the BBP uses these pins to change the gain a more integrated power management unit (PMU) approach.
table index in real time. Figure 43 shows this approach.
1.3V
GPO PINS (GPO_3 TO GPO_0) ADP5040 ADP1755
LDO
VDDx
1.2A
The AD9363 provides four 3.3 V capable general-purpose logic BUCK
AD9363
output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins 300mA 1.8V
VDD_INTERFACE
control other peripheral devices such as regulators and switches LDO

via the AD9363 SPI bus, or they function as slaves for the 300mA 3.3V
10558-075

LDO VDD_GPO
internal AD9363 state machine.
Figure 43. Space Optimized Power Solution for the AD9363

Rev. D | Page 30 of 32

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 Data Sheet AD9363

APPLICATIONS INFORMATION
For additional information about how to program the AD9363 Analog Devices, Inc., provides complete drivers for the AD9363
device, see the AD9363 reference manual, and for additional for both bare metal/no operating system (no OS) and Linux
information about the AD9363 registers, see the AD9363 operating systems. The AD9361, AD9363, and AD9364 share
register map reference manual, both of which are available by the same application program interface (API). For the AD9361
registering at the Integrated Wideband RF Transceiver Design drivers, visit the following online locations:
Resources web page and clicking Download the AD9363
• Linux wiki page
Design File Package. The register map is provided as a
• No OS wiki page
convenient and informational resource about low level
operation of the device; however, it is not recommended for For support for these drivers, visit the following online
creating user software. locations:
• Linux Engineer Zone® page
• No OS Engineer Zone page

Rev. D | Page 31 of 32

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 AD9363 Data Sheet

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

10.10
10.00 SQ A1 BALL
A1 BALL 9.90 CORNER
CORNER 12 11 10 9 8 7 6 5 4 3 2 1

A
B
C
D
8.80 SQ E
F
G

0.80 H
J
K
L
M

TOP VIEW 0.60 BOTTOM VIEW

REF

DETAIL A

1.70 MAX
DETAIL A 1.00 MIN

0.32 MIN

0.50 COPLANARITY
SEATING
PLANE 0.45 0.12
0.40
BALL DIAMETER

11-18-2011-A
COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1.

Figure 44. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-7)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9363ABCZ −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-7
AD9363ABCZ-REEL −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-7
ADRV9363-W/PCBZ Evaluation Board, 325 MHz to 3800 MHz Matching Circuits
1
Z = RoHS Compliant Part.

©2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D10558-0-11/16(D)

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