VHDL Implementation of AES Algorithm

Purnima Gehlot Richa Sharma S. R. Biradar

Mody Institute of Mody Institute of Mody Institute of
Technology Technology Technology
and Science and Science and Science
Laxmangarh, Sikar Laxmangarh, Sikar Laxmangarh, Sikar
Rajasthan,India Rajasthan,India Rajasthan,India
purnima.gehlot20@gmail.com sharma.r0707@gmail.com srbiradar@gmail.com
organisation of paper is like this, First of all the description of all the
ABSTRACT modules of algorithms with appropriate diagram has been given, then
Security has become an increasingly important feature with the
the results of delay has been shown.
growth of electronic communication. The Symmetric, or secret key
algorithms, a cryptography method in which the same key value is
used in both the encryption and decryption calculations are becoming 2. DIFFERENT MODULES OF AES
more popular. The keys, in practice, represent a shared
secret between two or more users that can be used to maintain a
ALGORITHM
The AES consists of mainly two units which are Data processing
private information link. Secret key cryptography uses conventional unit and the other one is Key Expansion unit. The Data processing
algorithm that is Advanced Encryption Standard (AES) algorithm. unit have four main modules or transformations in which sub byte
The AES algorithm is capable of using cryptographic keys of 128, transform, shift rows, mix column and add round key are involved
192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. and the Key Expansion unit generate the round key for the next
This standard is based on the Rijndael algorithm. All the modules are round.
compared with different families of FPGA platforms. This
methodology uses VHDL implementation the modules in terms of 2.1 SUB BYTE TRANSFORM
Delay and Frequency.It uses Xilinx – 6.1 xst software and there delay
calculations has been done on FPGA families which are Spartan2, A byte-by-byte substitution during the forward process .The
corresponding substitution step used during decryption is called Inv
Spartan3 and Virtex2.
Sub Bytes. This step consists of using a 16 × 16 lookup table to find
Keywords replacement byte for a given byte in the input state array. The entries
in the lookup table are created by using the notions of multiplicative
AES, VHDL, FPGA,Encryption,Decryption,Cryptography. inverses in GF(28) and bit scrambling to destroy the bit-level
correlations inside each byte[1].

1. INTRODUCTION 2.2 SHIFT ROW TRANSFORM

Nowadays cryptography has a main role in embedded systems Cyclically shifts the rows of the State over different offsets. The
design. In many applications, the data requires a secured connection operation is almost the same in the decryption process except for the
which is usually achieved by cryptography. Cryptography is divided fact that the shifting offsets have different values [2]. The goal of this
in two categories first is symmetric key cryptography (sender and transformation is to scramble the byte order inside each 128-bit
receiver shares the same key) and the second one is asymmetric key block[1].
cryptography (sender and receiver shares different key)[1]. Here we
are concerned about symmetric key cryptography due to its use in 2.3 MIX COLUMN TRANSFORM
military application, embedded system design, financial and legal
files, medical reports, and bank services via Internet, telephone This process is for mixing up of the bytes in each column separately
conversations, and e-commerce transactions etc. Many symmetric during the forward process. The corresponding transformation during
key cryptographic algorithms were proposed, such as the Data decryption is denoted Inv Mix Columns and stands for inverse mix
Encryption Standard (DES), the Elliptic Curve Cryptography (ECC), column transformation [3]. The goal is here is to further scramble up
the Advanced Encryption Standard (AES) and other algorithms[1]. the 128-bit input block.
Here the hardware implementation of AES algorithm is presented to
increase the data transfer speed[2]. 2.4 ADD ROUND KEY AND KEY EXPANSION
Objective of the dissertation is to perform an efficient method of
In this operation, the round key is applied to the State by simple bit
implementing a AES algorithm with minimum delay and having high
performance in terms of delay while maintaining the proper by bit XOR [4]. Basically Key Expansion unit is used to generate the
functionality of the system. The software used for the implementation next round key as for three different key size, AES consist of 10, 12
of the algorithm is Xilinx 6.1 – xst and language used is VHDL (very or 14 rounds. So after every round a new round key need to be
high speed integrated circuit hardware description language). produced. So this unit produces that round key for each round[5].
Simulation of encryption process of the AES algorithm has been done This unit also utilize the concept of shifting the bytes and substitution
using the Xilinx software. Inputs will be converted into binary form of bytes which were used in Data processing unit[6].The whole
and given as input to the "Model-Sim Simulator" of Xilinx 6.1.The encryption unit is shown in Figure 1.
 Plain Text(128 Bits)

RoundKey(0) Plaintext/Ciphertext
128-bit Encryption/ Output
Clk1 128-Bit
Decryption
Sub Bytes En=1 or 0
128-Bit Key
Round Input
Shift Rows
Clk2 Key Schedule
Secret Key Generation
Mix Column
128/192/256
Figure 2: RTL for Encryption and Decryption
RoundKey(i)

Sub Bytes
4. CONCLUSION
Shift Rows As the cryptography is playing the major role in today’s world. So the
frequency is the main concern so that the time period can be
minimized. Here in this paper we have explained about the basics of
AES algorithm and the implementation of its modules by using
RoundKey(Nr) VHDL. Here the simulations are performed with different device
families. The software we have used is Xilinx6.1i and the waveforms
Cipher Text(128 Bits) are simulated with model sim simulator. The frequency calculations
are done as we want to achieve the minimum delay.

Figure1: The AES algorithm Encryption structure. 5. REFERENCES

[1] Xinmiao Zhang and Keshab K. Parhi “Implementation
Approaches for the Advanced Encryption Standard
3. RESULTS Algorithm” IEEE 2002.
The delay table have been generated as result is shown in Table 1. [2] Hui QIN, Tsutomu SASAO, Yukihiro IGUCHI “An FPGA
As dieeferent Delay calculations are done with different device Design of AES Encryption Circuit with 128-bit Keys”
families so here in this table the minimum delay is shown which is GLSVLSI’05, ACM 2005
obtained by virtex 2. The interface and RTL for Encryption and
Decryption is shown in Figure 2. [3] Chih-Peng Fanand and Jun-Kui Hwang “FPGA Implementations
Of High Throughput Sequential And Fully Pipelined AES
TABLE 1. DELAY AND FREQUENCY OF DIFFERENT MODULES Algorithm” International journal of Electrical Engineering,
vol.15, no.6, pp. 447-455, 2008.

[4] Mehran Mozaffari-Kermani and Arash Reyhani-Masoleh

“Efficient and High Performance Parallel Hardware Architecture
Modules Delay (ns) Frequency (MHz) for the AES-GCM” IEEE Transactions On Computers, vol.61,
no. 8, August 2012.
Sub Byte 10.69 93.54
[5] Saambhavi Baskaran and Pachamuthu Rajalakshmi “Hardware
Software Co-Design of AES on FPGA” ICACCI ’12,ACM
Shift Rows 7.158 139.70
August 2012.

Mix Column 8.168 122.428 [6] Ashwini M. Deshpande, Mangesh S. Deshpande and Devendra
N. Kayatanavar “FPGA Implementation of AES Encryption and
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