1

Switched Capacitor OTA Differential gm/ID

Design in Moderate-Inversion Region
Neil Hildick-Smith
Dept. of Electrical Engineering
Stanford University

Abstract—A fully differential OTA was designed for a Switched

Capacitor application using a systematic, gm/ID design flow.
Stringent settling and noise performance targets were attained by
employing a parallel Matlab-HSpice analysis that enabled double
bookkeeping between analytically and numeric domains.
By using a lookup-table based approach, the Matlab work
stream afforded the ability to systematically design in the weak-
moderate inversion region while still maintaining good corre-
lation between analysis and simulation. Meanwhile the perfor-
mance benefits gained by operating in weaker inversion allowed
all targets to be met while minimizing power consumption.
This paper follows the gm/ID -based design process from
requirements to an optimized OTA design. From there the
performance of the proposed stage is analyzed and compared
against the design targets. The end-to-end process will explored
in detailed with discussion of trade-offs added along the way.
Fig. 1. Visualization of key performance characteristics across inversion level.
Curves from Murmann and Jespers.[1]
TABLE I
P ERFORMANCE R EQUIREMENTS

Parameter Units Requirement Achieved One way to approach identifying the inversion level appro-
Settling Time1 ns 50 34.6 priate for a given design is to develop a figure of merit that
Dynamic Range dB 70 71.0 combines these two high-level performance characteristics.
Power Dissipation mW - 1.31 Assuming that a particular application values gain and speed
Dynamic Settling Error % 1.5 1.0
Static Settling Error % 0.3 0.239 equally, one can simply seek to maximize the product of these
two parameters (Figure 1b). The selected performance metric
is seen optimized in the region of moderate inversion. In the
particular case of the device technology used on this project
I. BACKGROUND (180nm Stanford process), the maxima is found around 12S/A.
This observation reveals moderate-weak inversion to be an
A. gm/ID Design intriguing and powerful design space. However, as enticingly

T HE fundamental principle of the gm/ID -technique dis-

cussed by Boris Murmann is to approach the design
process by focusing on width-independent figures of merit
as this space is, it also has its own set of complications.
Current in strong inversion is dominated by drift and therefore
the ideal drift model that serves as the basis for the classic
that are that are directly adjustable.[1] This line of approach square law is an appropriate approximation. This modeling
leads the designer to avoid focusing on metrics such as µCox assumption begins to fall-apart at lower levels of inversion.
and instead view the process through the lens of MOSFET As the MOSFET inversion level drops, the current mechanism
inversion level. increasingly becomes dominated by diffusion. As a result the
Gate overdrive voltage directly determines the inversion square law only holds at high levels of inversion (and then,
level and, with it, a host of key performance characteristics. only if short channel effect are taken into account).[1]
Figure 1 shows that for a given ID , a higher level of channel The end result is a lack of modeling expressions simulta-
inversion result in a greater transit frequency at the expense neously both accurate in moderate-weak inversion and simple
of gain. Meanwhile the opposite is true for lower-levels of enough for hand-bookkeeping. This is a critical shortcoming:
inversion; gain and large signal swing (due to low VD,sat ) is the region that results in most optimal design is also a region
maximized over speed. that confounds systematic design via traditional Square Law.
It is this shortcoming that the lookup table seeks to address.
1 A differential input step is applied that transitions from 0V at t=0 to
The thought process behind this approach is to pre-
the maximum input voltage in 0.1ns. The maximum input is defined as the
maximum output voltage used in the dynamic range calculation, divided by computed lookup tables of key values necessary for systematic
the closed-loop gain. design. For instance, instead of relying on hand-calculations
 2

Fig. 3. Overview of switch capacitor gain stage–shown here as a single-ended

implementation for clarity.

Fig. 2. Overview of work flow used to generate look-up tables. The output
of this onetime step is used as the basis for all subsequent analysis presented The basic Two-Stage with Compensation to the first-order has
in this paper. the same, high gain as the Telescopic Cascode (≈ (gmRo )2 )
but with higher output swing; here compensation is required
to prevent the introduction of two non-dominant poles (sym-
to determine ID or Csb , simulations are performed on the metrically at the between-stage nodes)–coming at the cost of
modeling file associated with the technology across four increased design complexity.
key parameter sweeps: L, Vgs , Vds , VS . From here multi- Meanwhile, although the Folded Cascode has worse noise
dimensional look-up tables are compiled that allow the de- performance than a basic Telescopic Cascode, it has the
signer to easily map a given sizing and operating conditions benefit of both a greater output swing and an output swing
to key design parameters.[1] decoupled from the input common-mode voltage. This noise
to output swing trade-off comes without a meaningful expense
B. Practicality Constraints to gain (at either low or high frequencies) relative to the basic
A series of constraints were imposed at the outset of the Telescopic Cascode.
design to ensure practical feasibility of the end-result.

TABLE II
P RACTICALITY C ONSTRAINTS

Parameter Constraint
Fanout ( C
C
L
) ≥1
S
CS
CF
2
Pole-Zero Cancellation dissallowed
(W/L)
Max Mirror Ratio 15 (W/L)max
min
Rail Voltage 1.8V

For example, closely placed pole-zero pairs (e.g. low fre-

quency mirror doublets, intentional pole-zero cancellation)
were disallowed due to the long setting tails they can intro- Fig. 4. An overview of the selected folded cascode architecture. The OTA is
shown with its accompanying capacitive feedback network.
duce. Likewise, the practicality constraints also were selected
to ensure the OTA can drive an output load with at least as The selected Folded Cascode architecture has a pair of
much capacitance presented by the input of the OTA–a ratio differential input transistors which feed into a differential
known as fanout. All of these rules were abided by. cascode stack. A key design decision that was made regarding
the input transistors was to introduce neutralization capacitors.
II. D ESIGN OVERVIEW This technique is commonly used to reduce the effect of
A. Architecture Selection Miller capacitance amplification. By choosing this neutraliza-
Having outlined the overarching design philosophy, we re- tion capacitor value to equal the Cgd of the input transistors
turn to the particular design at-hand: the gain stage of a Switch (MN 1a/b ), the capacitance seen at the gate and drain both
Capacitor application. Several architectures were considered become 2Cgd . This is demonstrated in the following equation,
including Telescopic Cascode, Current Mirror Cascode and where A is the gain presented across Cgd,1a/b by MN 1a/b and
basic Two-Stage with Compensation. Ultimately however a where Cn is set to Cgd,1a/b :
Folded Cascode architecture was selected. Cgd (1 − A) + Cn (1 + A) =
While a basic Telescopic Cascode architecture has a high
Cgd + Cn − Cgd A + Cn A = 2Cgd
gain (≈ (gmRo )2 ), its large stack of transistors results in a low
output swing given the VDD requirement; this in turn limits dy- In practice, use of lookup tables were used to ”predict”
namic range (DR) and would require a strict noise requirement. the value of Cgd,1a/b and thereby set Cn . As discussed
For the Current Mirror Cascode, its input-referred noise and later in Section II-C, this lookup technique proved highly
non-dominant pole scale with its current mirror ratio–making accurate in predicting not only Cgd,1 but the intrinsic and
the circuit better suited for low frequency (low DSE) operation. extrinsic capacitances of all the transistors. The use of this
 3

neutralization capacitor helped to lower the capacitance seen values (κ = 0.96, β = 0.25, gm/ID = 16S/A) and a 2D sweep
at Folded Cascode input, resulting in better bandwidth. This performed (Figure 5).
reduction of seen input capacitance (Cin ) also improved the
loop gain of the OTA due to its direct effect on the feedback
gain β (for detailed discussion, again, see Section II-C).

B. High-Level Sizing Methodology

A key decision made in the design flow was to have a single
gm/ID value shared by the cascode stack. An optimization
knob was built into the adopted Matlab flow that allowed for
the gm/ID of the input transistor pair (MN 1a/b ) to be scaled
relative to the cascode stack. This ratio between the two stages
was defined as X.

TABLE III
E FFECT OF X FACTOR ( WITH FIXED gm/ID,cascode = 15)
Fig. 5. Visualization of relationship between transistor lengths and loop gain.
The selected active load transistor and gain transistor channel lengths are
X Lo (dB) ST (ns) P (mW) rself N (µVrms ) DR (db) denoted by the white circle (0.7µm and 0.5µm, respectively).
0.8 51.56 39.4 0.95 0.137 258.0 70.16
1 51.67 34.6 1.39 0.177 70.96
1.2 50.89 32.1 1.92 0.220 225.1 71.34
From here, further optimizations were performed on the
OTA. Some of the remaining degrees of freedom that were ex-
plored include X, and the specific value of gm/ID,cascodestack .
While this knob provided revealing insights, the optimum
A gm/ID,cascodestack sweep from 10S/A to 25S/A was per-
was ultimately found near unity and as a result X=1 was
formed, and the resulting values plotted (Figure 6).
selected. See below for an informal exploration of the effects
of X on the operation of the circuit (Table III).
Overall, the optimization strategy focused on using the
performance targets to establish minimum acceptable values
for parameters. With minimum acceptable ranges, key remain-
ing degrees of freedom were iterated across in search of an
optimum. For example, the transient design specifications (e.g.
settling time, dynamic settling error, etc.) set the unity gain
frequency; knowing the desired OTA phase margin required
to achieve a critically damped response (e.i. 76◦ ), the location
of the desired non-dominant pole frequency was identified.
Derived equations (described later, Section II-C) used in
concert with the lookup-tables were then used to identify
the sizing+biasing required to attain the design specification-
derived circuit characteristics (e.g. ωp2 , ωu1 , etc).
One such degree of freedom was Length sizing. The tran-
sistors in the stage were divided into two groups based on
their function in the OTA: active load transistors and gain
transistors. The node at the input to the cascode stack acts Fig. 6. Effect of gm/ID,cascodestack on the OTA operation characteristics:
as a current divider with some of the signal going down into rself , PM and power consumption. The sweep was performed with X=1 (e.i.
the active loads (MN 2a/b ); this current division factor was all transistors had the same gm/ID ).
denoted as κ. Seeking to minimize κ across all frequencies,
As expected, a linear increase in gm/ID resulted in an
it was important to have the load transistor (MN 2a/b ) output
exponential increase in self loading as the devices get larger.
resistance due to channel length modulation (1/gds ) be large
Also as expected, the current consumption of the circuit
relative to the gain transistor (MN 3a/b ).2 This insight helped
decreases as the OTA moves into increasingly weak inversion;
guide length sizing.
one important observation made here was that the rate of
A second observation guiding length sizing was that the loop
power consumption decrease lessens as the OTA is pushed
gain of the OTA needed to be sufficiently large to meet the
further and further into weak inversion–becoming fairly flat
SSE specification. In order to understand the effect of channel
past gm/ID ≈ 15. Lastly, the phase margin can be observed
length on loop gain, some parameters were fixed to reasonable
as having a negative relationship to gm/ID ; as the OTA enters
2 At high frequencies the impedance looking up into the source of M
N 3a/b
weak inversion and the devices correspondingly increase in
is ≈ 1/gmN 3a/b . As 1/gmN 3a/b << 1/gdsN 2a/b , at high frequencies size, the node capacitances due to intrinsic and extrinsic
LN 3a/b
κ will be close to the ideal value of 1 largely independently of LN 2a/b
. At sources increase–bringing non-dominate poles to increasingly
low frequencies, κ will be more dependent on the length ratio. lower frequencies.
 4

Ultimately a mid-range gm/ID of 16S/A was selected to Once those variables were defined to meet the design
balanced competing demands on power, gain and self-loading. targets, attention was turned to derive other variables that
Lastly, it was important to take into account the effect of depended on both gm/ID and the above block of parameters.
self-loading. This mechanism has the potential to significantly The following equations were solved in the order in which
impact the performance of the design. By presenting additional they appear below, using information gain from each preceding
capacitance at the output–the capacitive feedback pathway– expressions and lookup function table information:3
and associated loop gain, is altered.
CL,total
CF = ≈ 686f F
(1 + rself )( C L CS
CS CF + 1 − β)
CL CS
CL = CF ≈ 1.37pF
CS CF
CS
CS = CL ≈ 1.37pF
CL
ωu1 CL,total
gm1 = ≈ 2.9
βκ
gm1 X
It = ≈ 179µA
gm/Idcascode−stack
gm1
Cgg,1 = ≈ 940.7
2πfT,1
Fig. 7. Plot of self-loading iterations, converges to within 0.1% of the final Cin = Cgg,1 + Cgd,1 ≈ 1.08pF
value (0.2078) in only four iterations.
Cdd3 + Cdd,4
rself = ≈ 0.208
To account for the effects of self-loading, a simple iterative CL + (1 − β)CF
procedure employed: rself was initially set to zero and the CF
βresult = ≈ 0.2182
sizing script run; the effective capacitive network values were CF + CS + Cin
re-sized to account for the additional capacitance introduced gm3 + gmb3
by the intrinsic and extrinsic drain capacitances of the output ωp2,result = ≈ 3.76Grad/s
Css,3 + Cdd,2 + Cdd,1 + Cgd,1
transistors; this loop was traversed until the resulting rself ωp2,result 180
values converged to a level of agreement of 0.1% (Figure 7). P Mresult = atan( ) ≈ 85.44◦
ωu1 π
C. Detailed Calculation of Key Parameters Many of these equations match those described by Mur-
The calculations for the design flow draws on the gm/ID mann and Jespers.[1] However, there are key differences
approach outlined by Murmann and Jespers.[1] Modifications introduced by the added neutralization capacitor; in particular,
were made to incorporate neutralization, which was not em- the differences are seen in the equations for Cin and in
ployed in the text’s treatment of the Folded Cascode. the capacitance seen for the non-dominant pole wp2 . It is
κ was initially fixed at 1 to ungate usage of the lookup important to note that the resultant capacitance should be
tables. Once the intrinsic gains used to calculate κ were 2Cgd , but since Cdd includes a Cgd , only one extra Cgd was
computed, the resulting κ (0.955) was seen to be very close added in the calculation.
to the initial assumption. Length sizing was selected via the
approach discussed in Section II-A. Overall the following set D. Discrepancies between Matlab and HSpice
of equations define variables which are largely set by the
performance targets: All of the values calculated both in HSpice and Matlab were
collected in Table IV. The residual was subsequently computed
gm/Idcascode−stack to asses degree of agreement.
X= =1 Overall, the bulk of parameters matched quite well. For
gm/Id1
2 example, the calculations of the various intrinsic/extrinsic
0.5Vod,peak
Pnoise = ≈ 50nV 2 /Hz capacitances of the transistors had excellent agreement with
10DR/10 the associated HSpice .op simulation. Likewise, the gm/ID
log(1/DSE) also matched. This confirms the validity of the design process,
ωu1 = ≈ 300M rad/s
ST which leaned heavily on the use of analytical equations and
1 − SSE lookup tables.
Lo,min = ≈ 332.3
SSE
2γp γn 3 β was fixed to 0.25 (or, 3/4*β
α=2+ +4 ≈ 6.88 max ) for the calculation. At the end, β
X X was independently re-calculated based on the selected sizing to verify that
1 the initial assumption was reasonable; this independent calculation has been
κ= gds1 2gds2
≈ 0.955 denoted βresult . Ideally, β would be iterated for convergence however–
1 + gm 1 X + gm 2 because the β optimum curve is shallow–exact convergence is non-critical.
4 Represents the difference between the C
αKBoltzmann T gd,1 value and the neutralization
CL,total = ≈ 2.27pF capacitor. The difference is the remaining miller capacitance that can, in turn,
βPnoise experience miller amplification.
 5

Fig. 8. A detailed schematic of the selected Folded Cascode OTA implementation. All transistors have been annotated with sizing information, gm/ID , and
(for PMOS devices only) bulk connection. All capacitor values have been noted along all with DC currents and bias voltages.

TABLE IV a result of the presence of an inadvertent LHP zero that

M ATLAB -HS PICE D ISCREPANCIES was discovered to occur before the non-dominant pole. As a
Parameter Units Matlab HSPICE Residual result, even when the gm/ID was selected to produce a phase
Power mW 1.29 1.31 -1.52% margin of 76◦ , the simulated phase margin was high, roughly
Lo dB 50.43 52.41 -3.77% 87◦ . Despite exhaustive attempts to bring down the phase
Settling Time ns 10 34.62 -71.1%
Phase Margin ◦ 85.44 86.44 -1.15%
margin, the presence of this LHP zero confounded all such
Dynamic Settling Error % 0.1 1.00 -90% efforts. Because of this, it was decided to choose a gm/ID
Static Settling Error % 0.3 0.239 25.5% that produced better results for the loop gain and the other
Vod,peak V 1 1.19 -15.9%
N oise µVrms 233.6 238.3 -1.97%
specifications, sacrificing phase margin (and resulting settling
fu1 MHz 47.7 42.45 -12.4% time) optimization.
fp2 MHz 599 163 267%
Cgd,1 − Cn 4 fF 0 0.29 -
βresult - 0.25 0.218 14.6% III. P ERFORMANCE A NALYSIS
A. Frequency Response
The bode plot in Figure 9 shows the frequency performance
The HSpice noise performance was an almost perfect match
of the OTA. The low frequency loop gain (Lo ) can be seen
with the Matlab defined target. This target noise performance
to be 51.67dB. The unity loop gain frequency (fu1 ) and
was directly derived from the design requirement specification
associated phase margin (PM) are 42.45MHz and 86.44◦ ,
on the dynamic range (70dB), and the predicted Vod,peak
respectively.
which also presented good alignment. Using the equation for
pnoise from earlier, we get that the maximum allowable total
integrated noise should be around 250µV rms.
However, while there is good alignment for many param-
eters, phase margin and the associated settling performance
sees poor alignment. The design flow sought to chose a gm/ID
value that would result in a critically damped system (76◦
PM). However, the HSpice simulations turned out to not match
this goal. Almost everything but the phase margin matched
the Matlab results (this includes all of the capacitances, the
gm/ID values of the transistors, etc.). As will be discussed
in the conclusion, it is hypothesized that the poor matching
of the phase margin (and therefore ST) results were likely Fig. 9. Bode plots from AC simulation of the OTA in HSpice.
 6

A .pz analysis of the open-loop behavior of the OTA reveals C. Common Mode Transient Response
the locations of the various poles and zeros. The design goal The output voltage versus time is shown in Figure 11. Of
of having the non-dominant pole be ≈ 4x away from the first note here is the symmetry as Vop and Vop swing apart.
pole is evident and appears to be properly executed. However,
both the non-dominant pole (fp2 ) and the unwanted LHP Zero
appear around 170MHz (Table V).

TABLE V
O PEN -L OOP L OW F REQUENCY P OLE -Z ERO L OCATIONS

Type Plane Location (MHz)

Pole LHP 45.82
Pole LHP 162.9
Zero LHP 176.9

This unfortunately close proximity results in the aforemen-

tioned LHP Zero largely canceling the effect of the true fp2 –
resulting in a bode plot that, given naive assumptions, would
instead appear to have its fp2 at around 1GHz. It is this effect
that is causing the poor settling time of the amplifier.

B. Differential Transient Response

The transient step response of the OTA is shown in Figure
10. The first-order natural-log nature of the step response is
clearly shown in the plot as the total error of the waveform
converges towards the SSE.
Fig. 11. Transient simulation of OTA output from a step response. Differential
and common mode excursions are shown in addition to the input waveform.

Additionally, the transconductance of the voltage controlled

current source (VCCS) used in the common mode feedback
(CMFB) circuit is also of import. If the CMFB VCCS
transconductance were greater than that of MN 1a/b , there
would be instability in the CMFB feedback loop. A gmCM F B
of 2.3mS was selected in order to give margin on gmN 1a/b
(2.94mS) and therefore, not only just avoid instability, but also
avoid ringing in the CMFB network.

D. Noise Performance
In the below, simulated plots (Figures 12 one can see
that the total integrated noise levels off at around 1 GHz
(≈ 238µV rms). In combination with the measured Vod,peak
(see Section III-E), this results in a dynamic range of 70.96dB,
which meets the desired specification.
Fig. 10. Transient simulation of the OTA response to an input step of 10mV.

A small negative dip is seen in the output waveform when

the input step is first applied (t=10ns on the plot). This is a
result of the fact that right after the input step application,
the amplifier has no effect and instead the input waveform is
simply being capacitively divided by the feedback capacitors.
In other words, the presence of a non-minimum phase zero in
the system causes the step response to begin in the opposite
direction of the step.
The input step is small (10mV) and as a result no slewing is
seen in the plot. Slew performance was not part of the design
specifications; however, were performance under large step
input relevant, and the design were not meeting requirements,
current through the cascode stack branch would need to be
increased. Fig. 12. Input and output referred noise of the OTA across frequencies.
 7

E. Output Range .include /usr/class/ee214b/hspice/ee214b_hspice.sp

* parameters
.param vocdes = 0.900
.param vsc_param = 1.067
.param vm2g_param = 0.541
.param vm3g_param = 0.811
.param vm4g_param = 1.003
.param vm5g_param = 1.273
.param it_param = 358.062u
.param cs_param = 1373.054f
.param cl_param = 1373.054f
.param cf_param = 686.527f
.param cn_param = 145.656f
.param w1_param = 222.160u
.param w2_param = 177.325u
.param w3_param = 56.772u
.param w4_param = 229.195u
.param w5_param = 356.950u
.param l1_param = 0.500u
.param l2_param = 0.700u
Fig. 13. Effect of input swing on OTA differential gain. .param l3_param = 0.500u
.param l4_param = 0.500u
A DC sweep simulation was performed in order to asses .param l5_param = 0.700u

gain performance in the presence of large differential inputs. * input sources

Maximum output voltage swing was defined as the point at vdd vdd 0 1.8
vsc vsc 0 ’vsc_param’
which the gain drops by 30%. This definition ascribes a ±1.2V vsd vsd 0 dc 0
swing to this design, a sizable fraction of the total rail voltage. xin vsd vsc vip_c vim_c balun

* LSTB analysis
IV. C ONCLUSION vlstb_a vip_g vip ac 0
vlstb_b vim_g vim ac 0
Equations describing capacitance and pole locations, noise
and gain were derived for a Folded Cascode with neutraliza- * Output current measurement
vop_meas vop vop_c dc 0
tion. As a result this project provided a valuable outlet for the vom_meas vom vom_c dc 0
application of the analytical foundation built in EE214A.
* biasing
However perhaps more importantly, beyond analysis, the vm2g n_m2g 0 ’vm2g_param’
techniques taught in EE214B afforded the ability to gain vm3g n_m3g 0 ’vm3g_param’
vm4g n_m4g 0 ’vm4g_param’
exposure to Analog IC design. In doing so, this project vm5g n_m5g 0 ’vm5g_param’
helped flush-out intuition on the effect a given parameter has
* OTA circuit
on performance. The relationship between gm/ID and OTA it vdd vx_t ’it_param’
operation benchmarks such as speed, power consumption, loop m1a vx_ab vip_g vx_t vx_t pch W=’w1_param’ L=’l1_param’
m1b vx_ba vim_g vx_t vx_t pch W=’w1_param’ L=’l1_param’
gain, and self-loading was clearly revealed. Matlab plotting of m2a vx_ba n_m2g 0 0 nch W=’w2_param’ L=’l2_param’
parameter sweeps help clarify these relationships and visualize m2b vx_ab n_m2g 0 0 nch W=’w2_param’ L=’l2_param’
m3a vop n_m3g vx_ba 0 nch W=’w3_param’ L=’l3_param’
ways to tune the various knobs to try and meet specifications m3b vom n_m3g vx_ab 0 nch W=’w3_param’ L=’l3_param’
in the face of a wide, poorly-constrained design-space. m4a vop n_m4g n_m54a vdd pch W=’w4_param’ L=’l4_param’
m4b vom n_m4g n_m54b vdd pch W=’w4_param’ L=’l4_param’
The OTA managed to meet all performance targets. The m5a n_m54a n_m5g vdd vdd pch W=’w5_param’ L=’l5_param’
gain stage excels on many of the specifications (DR and SSE), m5b n_m54b n_m5g vdd vdd pch W=’w5_param’ L=’l5_param’
d1a 0 vx_t dwell 10p *size (see L2-3 slide 39)
however leaves further room for improvement of transient d1b 0 vx_t dwell 10p *size (see L2-3 slide 39)
performance. The slightly excessively high phase margin and
* feedback capacitors
therefore non-critically damped response which results in a cn_m vim_g vx_ab ’cn_param’
settling time that could be further optimized. cn_p vip_g vx_ba ’cn_param’
cs_m vim_c vim ’cs_param’
Ultimately the designer learned many lessons through the cs_p vip_c vip ’cs_param’
course of this project. These lessons came from carefully cl_p vop_c 0 ’cl_param’
cl_m vom_c 0 ’cl_param’
and systematically developing an design flow that emphasized cf_mp vim vop_c ’cf_param’
plotting results to assist observation-making and designing a cf_pm vip vom_c ’cf_param’
r_sm vim_c vim 10gig
fully stand-alone Matlab script for optimization. r_sp vip_c vip 10gig

R EFERENCES * CMFB circuit

xout vod voc vop_c vom_c balun
[1] P. J. Boris Murmann, Systematic Design of Analog CMOS Circuits: Using roc_des n_ocdes 0 10gig
Pre-Computed Lookup Tables, 2017, sections 6.2-6.4. rod vod 0 10gig
voc_des n_ocdes 0 ’vocdes’
g_cmfb vdd vx_t n_ocdes voc 2.3m
A PPENDIX A
HSPICE N ETLIST * Analysis
.op
The final HSpice netlist of the OTA has been reproduced .ac dec 100 100 10G
.lstb mode=diff vsource=vlstb_a,vlstb_b
below. The Analysis section varies with the type of analysis .probe ac lstb(db) lstb(p)
performed however all simulations in this report otherwise .option post brief accurate
.end
have the same netlist.
 8

A PPENDIX B vth -437.0898m -437.0898m 427.4368m 427.4368m

vdsat -96.8473m -96.8473m 97.1637m 97.1637m
HSPICE . OP O UTPUT vod -94.8836m -94.8836m 113.5632m 113.5632m
beta 36.0965m 36.0965m 75.9226m 75.9226m
Operating point results on the simulation has been placed gam eff 536.2556m 536.2556m 585.6125m 585.6125m
below. This log includes information on devices, node voltages gm 2.9354m 2.9354m 5.8336m 5.8336m
gds 26.6862u 26.6862u 115.0617u 115.0617u
and supplies. gmb 932.9517u 932.9517u 1.6601m 1.6601m
cdtot 290.2931f 290.2931f 243.4462f 243.4462f
****** operating point information tnom= 25.000 temp= 25.000 cgtot 938.4808f 938.4808f 992.4089f 992.4089f
****** cstot 1.0311p 1.0311p 1.0810p 1.0810p
****** operating point status is all simulation time is 0. cbtot 571.6862f 571.6862f 558.8805f 558.8805f
node =voltage node =voltage node =voltage
cgs 744.4906f 744.4906f 844.9253f 844.9253f
cgd 145.9409f 145.9409f 88.5374f 88.5374f
+0:n_m2g = 541.0000m 0:n_m3g = 811.0000m 0:n_m4g = 1.0030
+0:n_m54a = 1.6006 0:n_m54b = 1.6006 0:n_m5g = 1.2730
subckt
+0:n_ocdes = 900.0000m 0:vdd = 1.8000 0:vim = 1.0670
element 0:m3a 0:m3b 0:m4a 0:m4b
+0:vim_c = 1.0670 0:vim_g = 1.0670 0:vip = 1.0670
model 0:nch 0:nch 0:pch 0:pch
+0:vip_c = 1.0670 0:vip_g = 1.0670 0:voc = 897.8260m
region Saturati Saturati Saturati Saturati
+0:vod = -31.5920n 0:vom = 897.8260m 0:vom_c = 897.8260m
id 181.5793u 181.5793u -181.5793u -181.5793u
+0:vop = 897.8260m 0:vop_c = 897.8260m 0:vsc = 1.0670
ibs 0. 0. 0. 0.
+0:vsd = 0. 0:vx_ab = 199.1007m 0:vx_ba = 199.1007m
ibd 0. 0. 0. 0.
+0:vx_t = 1.5990
vgs 611.8993m 611.8993m -597.5668m -597.5668m
vds 698.7252m 698.7252m -702.7408m -702.7408m
vbs -199.1007m -199.1007m 199.4332m 199.4332m
**** voltage sources vth 502.5724m 502.5724m -500.0327m -500.0327m
subckt
vdsat 100.9183m 100.9183m -102.4280m -102.4280m
element 0:vdd 0:vlstb_a 0:vlstb_b 0:vm2g 0:vm3g 0:vm4g
vod 109.3269m 109.3269m -97.5341m -97.5341m
volts 1.8000 0. 0. 541.0000m 811.0000m 1.0030
beta 35.3864m 35.3864m 36.1222m 36.1222m
current -727.7426u 0. 0. 0. 0. 0.
gam eff 584.8962m 584.8962m 530.9439m 530.9439m
power 1.3099m 0. 0. 0. 0. 0.
gm 2.9100m 2.9100m 2.9228m 2.9228m
gds 29.1512u 29.1512u 30.2315u 30.2315u
subckt
gmb 750.8721u 750.8721u 863.5396u 863.5396u
element 0:vm5g 0:voc_des 0:vom_meas 0:vop_meas 0:vsc 0:vsd
cdtot 66.4606f 66.4606f 314.9324f 314.9324f
volts 1.2730 900.0000m 0. 0. 1.0670 0.
cgtot 236.8460f 236.8460f 967.6789f 967.6789f
current 0. -90.0000p 3.1592a 16.0193f 0. 0.
cstot 257.3487f 257.3487f 1.0382p 1.0382p
power 0. 81.0000p 0. 0. 0. 0.
cbtot 137.5668f 137.5668f 567.0864f 567.0864f
total voltage source power dissipation= 1.3099m watts
cgs 196.6666f 196.6666f 774.8717f 774.8717f
cgd 26.9498f 26.9498f 150.6263f 150.6263f
**** current sources
subckt
subckt
element 0:it
element 0:m5a 0:m5b
volts 201.0266m
model 0:pch 0:pch
current 358.0620u
region Saturati Saturati
power -71.9800u
id -181.5793u -181.5793u
total current source power dissipation= -71.9800u watts
ibs 0. 0.
ibd 0. 0.
**** resistors vgs -527.0000m -527.0000m
subckt
vds -199.4332m -199.4332m
element 0:r_sm 0:r_sp 0:roc_des 0:rod
vbs 0. 0.
r value 10.0000g 10.0000g 10.0000g 10.0000g
vth -424.3598m -424.3598m
v drop 0. 0. 900.0000m -31.5920n
vdsat -100.3703m -100.3703m
current 0. 0. 90.0000p -3.1592a
vod -102.6402m -102.6402m
power 0. 0. 81.0000p 9.981e-26
beta 39.9607m 39.9607m
gam eff 536.2723m 536.2723m
**** voltage-controlled current sources gm 2.9191m 2.9191m
subckt
gds 50.8361u 50.8361u
element 0:g_cmfb
gmb 935.5380u 935.5380u
v drop 201.0266m
cdtot 573.8956f 573.8956f
current 6.5221u
cgtot 1.9976p 1.9976p
cstot 2.1718p 2.1718p
**** voltage-controlled voltage sources cbtot 1.1656p 1.1656p
subckt xin xin xout xout
cgs 1.6502p 1.6502p
element 1:e1 1:e2 2:e1 2:e2
cgd 244.2459f 244.2459f
volts 0. 0. -15.7960n -15.7960n
current 0. 0. 1.5796a 1.5796a

**** diodes
subckt A PPENDIX C
element 0:d1a 0:d1b M ATLAB : D ESIGN F LOW
model 0:dwell 0:dwell
id -100.0000a -100.0000a This first Matlab script accepts parameters constrained by
vd -1.5990 -1.5990
req 0. 0. the design requirement specifications, in addition to a small
cap 1.1549f 1.1549f collection of design knobs (Lactiveload , Lgain , X, Vod,peak ,
**** mosfets
Vds,activeload ). Using this input information, sizing+biasing
subckt is calculated iteratively until self-loading effects have fully
element 0:m1a 0:m1b 0:m2a 0:m2b
model 0:pch 0:pch 0:nch 0:nch converged and returned in a vector corresponding to a range
region Saturati Saturati Saturati Saturati of gm/ID values.
id -182.2920u -182.2920u 363.8713u 363.8713u
ibs 0. 0. 0. 0. % LENGTH SIZING
ibd 0. 0. 0. 0. addpath(’/usr/class/ee214b/matlab/hspice_toolbox’);
vgs -531.9734m -531.9734m 541.0000m 541.0000m addpath(’/usr/class/ee214b/matlab’);
vds -1.3999 -1.3999 199.1007m 199.1007m load 180nch.mat;
vbs 0. 0. 0. 0. load 180pch.mat;
 9

gm_gds1 = lookup(pch,’GM_GDS’,’GM_ID’,gm_Id./X,’VDS’,Vdd-
settling_error = 0.003; %from design spec Vt_comp-n_m23,’L’,L_gain,’VSB’,0)’;
G = 2; %from design spec gm_gds2 = lookup(nch,’GM_GDS’,’GM_ID’,gm_Id,’VDS’,n_m23,’
beta_max = 1/(1+G); L’,L_load,’VSB’,0)’;
beta = 0.75*beta_max; gm_gds3 = lookup(nch,’GM_GDS’,’GM_ID’,gm_Id,’VDS’,n_m34-
k = 0.95; n_m23,’L’,L_gain,’VSB’,n_m23)’;
L_gain = linspace(1,0.18,100); gm_gds4 = lookup(pch,’GM_GDS’,’GM_ID’,gm_Id,’VDS’,n_m45-
L_load = linspace(1,0.18,100); n_m34,’L’,L_gain,’VSB’,Vdd-n_m45)’;
gm_gds5 = lookup(pch,’GM_GDS’,’GM_ID’,gm_Id,’VDS’,Vdd-
gm_Id_2 = 16; n_m45,’L’,L_load,’VSB’,0)’;
gm_Id_3 = 16;
gm_Id_4 = 16; k = 1./(1+1./gm_gds1/X + 2./gm_gds2); %(1./gm_gds4)./(1./
gm_Id_5 = 16; gm_gds4 + 1./gm_gds1/X + 2./gm_gds2); %Murmann
gm_gds2 = lookup(nch,’GM_GDS’,’GM_ID’,gm_Id_2,’VDS’,0.2,’L’, suggest 0.9
L_load); Cl_tot = alpha./beta*k_b*T/p_noise; %Murmann p34
gm_gds3 = lookup(nch,’GM_GDS’,’GM_ID’,gm_Id_3,’VDS’,0.7,’L’, Cf = (Cl_tot)./(1+rself(length(rself)))./(Cl_Cs*Cs_Cf+(1-
L_gain); beta)); %Murmann p32
gm_gds4 = lookup(pch,’GM_GDS’,’GM_ID’,gm_Id_4,’VDS’,0.7,’L’, Cl = Cf.*Cl_Cs*Cs_Cf;
L_gain); Cs = Cl./Cl_Cs;
gm_gds5 = lookup(pch,’GM_GDS’,’GM_ID’,gm_Id_5,’VDS’,0.2,’L’, gm_1 = wu_1.*Cl_tot./beta./k;
L_load); It = gm_1./gm_Id.*X;
ft_1 = lookup(pch, ’GM_CGG’,’GM_ID’,gm_Id./X,’L’, L_gain,
for i = 1:length(gm_gds2) %L_load ’VSB’, 0, ’VDS’, Vdd-Vt_comp-n_m23)’/2/pi;
for j = 1:length(gm_gds3) %L_gain Cgg_1 = gm_1./(2*pi.*ft_1);
L0(i,j) = beta*k/(1/((1+gm_gds5(i)*gm_gds4(j))) + w_1 = It./lookup(pch,’ID_W’,’GM_ID’,gm_Id./X,’L’, L_gain,
1/((1+1/3*gm_gds2(i))*gm_gds3(j))); ’VSB’, 0, ’VDS’, Vdd-Vt_comp-n_m23)’;
end Cgd_1 = w_1.*lookup(pch, ’CGD_W’,’GM_ID’,gm_Id./X, ’L’,
end L_gain, ’VSB’, 0, ’VDS’,Vdd-Vt_comp-n_m23)’;
L0_minimum = (1-settling_error)/(settling_error); %L13-14 gm_3 = gm_Id.*It;
Slide 8 Cin = Cgg_1+Cgd_1; %before neutralization: Cin = Cgg_1+
Cgd_1.*gm_1./gm_3
figure(99);
imagesc(L_gain,L_load,L0) % COMPUTE RESULTING BENCHMARKS (rself, k, PM)
xlabel(’L_{gain} (um)’); w_2 = 2*It./lookup(nch, ’ID_W’, ’GM_ID’, gm_Id, ’L’,
ylabel(’L_{load} (um)’); L_load, ’VSB’, 0, ’VDS’, n_m23)’;
ylabel(colorbar,’Low Frequency Loop Gain’); w_3 = It./lookup(nch, ’ID_W’, ’GM_ID’, gm_Id, ’L’, L_gain
title(’Length Sizing Given Fixed K (K=0.95)’,’fontweight’,’ , ’VSB’, n_m23, ’VDS’, n_m34-n_m23)’;
bold’); w_4 = It./lookup(pch, ’ID_W’, ’GM_ID’, gm_Id, ’L’, L_gain
%% Part 3 (Limited Sweeping) , ’VSB’, Vdd-n_m45, ’VDS’, n_m45-n_m34)’;
% DESIGN/TECHNOLOGY SPECIFICATIONS w_5 = It./lookup(pch, ’ID_W’, ’GM_ID’, gm_Id, ’L’, L_load
close all; , ’VSB’, 0, ’VDS’, Vdd-n_m45)’;
clc; gmb_3 = gm_3.*lookup(nch,’GMB_GM’,’GM_ID’,gm_Id,’VDS’,
settling_error = 0.003; n_m34-n_m23,’VSB’,n_m23,’L’, L_gain)’;
settling_time = 10E-9; Cdd_1 = w_1.*lookup(pch,’CDD_W’,’GM_ID’,gm_Id./X,’VDS’,
dynamic_error = 0.001; Vdd-Vt_comp-n_m23,’VSB’, 0,’L’,L_gain)’;
Cl_Cs = 1; Cdd_2 = w_2.*lookup(nch,’CDD_W’,’GM_ID’,gm_Id,’VDS’,n_m23
Cs_Cf = 2; ,’VSB’, 0,’L’,L_load)’;
gamma_n = 0.84; Cdd_3 = w_3.*lookup(nch,’CDD_W’,’GM_ID’,gm_Id,’VDS’,n_m34
gamma_p = 0.88; -n_m23,’VSB’,n_m23,’L’,L_gain)’;
G = 2; Cdd_4 = w_4.*lookup(pch,’CDD_W’,’GM_ID’,gm_Id,’VDS’,n_m45
k_b = 1.38E-23; -n_m34,’VSB’, Vdd-n_m45,’L’,L_gain)’;
T = 300; %kelvin Css_3 = Cdd_3./lookup(nch,’CDD_CSS’, ’GM_ID’, gm_Id, ’VDS
DR = 70; %dB ’, n_m34-n_m23, ’VSB’,n_m23,’L’,L_gain)’;
Vdd = 1.8; %V
Vt_comp = 0.2; %V rself_new = (Cdd_3 + Cdd_4)./(Cl + (1-beta)*Cf); %Murmann
Vth = 0.5; %Threshold voltage (V) p32
%[min_residual, index] = min(abs(PM_result-76));
% ADJUSTABLE DESIGN PARAMETERS [min_residual, index] = min(abs(gm_Id-16));
beta_frac = 0.75; %larger can lead to smaller devices rself(length(rself)+1) = rself_new(index);
vod_peak = 1; end
L_load = 0.7;
L_gain = 0.5; figure;
rself = 0; %intial plot(rself,’-o’)
gm_Id = [10:0.05:25]; set(gca,’xtick’,0:length(rself))
X = 1; %x=gm_Id4/gm_Id1 set(gca,’xlim’,[0,length(rself)])
Vds_load = 0.2; %V (adjustable, no less than ˜100mV) title(’Self-loading Effect across Computation Iterations’,’
Vds_gain = Vdd/2-Vds_load; fontweight’,’bold’);
n_m45 = Vdd-Vds_load; xlabel(’Iteration #’);
n_m34 = Vdd/2; ylabel(’R_{self}’);
n_m23 = Vds_load;
beta_result = Cf./(Cf+Cs+Cin);
% Calculations directly from specifications wp_2_result = (gm_3 + gmb_3)./(Css_3 +Cdd_2 + Cdd_1 + Cgd_1)
beta_max = 1/(1+G); ; %nondominant pole frequency (Murmann)
beta = beta_frac.*beta_max; PM_result = atan(wp_2_result./wu_1)*180/pi;
p_noise = 0.5*vod_peakˆ2/(10ˆ(DR/10)); gm_Id_result = gm_Id(index)
wu_1 = log10(1/dynamic_error)/settling_time; %PM_result(index)
L0 = (1-settling_error)/(settling_error); %L13-14 Slide 8 k_result = k(index) %Murmann p32
alpha = 2*gamma_p*(1+gamma_p/gamma_p*X + 2*gamma_n/gamma_p*X
); figure;
subplot(3,1,1);
plot(gm_Id, rself_new);
% SIZING SECTION (finding capacitances, currents, gm1 and title(’Effect of gm/Id’,’fontweight’,’bold’);
gm3) xlabel(’gm/Id (S/A)’);
while ((length(rself) == 1) || (abs(rself(length(rself))- ylabel(’r_{self}’);
rself(length(rself)-1)) > 0.001)) subplot(3,1,2);
plot(gm_Id, PM_result);
 10

xlabel(’gm/Id (S/A)’); A PPENDIX E

ylabel(’Phase Margin (degrees)’);
subplot(3,1,3);
M ATLAB : S IMULATION R ESULTS E XTRACTION
plot(gm_Id, It.*10ˆ3);
xlabel(’gm/Id (S/A)’); The third and final script extracts and generates key figures.
ylabel(’Bias Current (mA)’);
%Loop Gain (part3_loop.sp)
m = loadsig(’part3_loop.ac0’);
lssig(m);
A PPENDIX D f = evalsig(m,’HERTZ’);
M ATLAB : S IZING /B IASING E VALUATION lstb_mag = evalsig(m,’lstb_db’); %dB
lstb_phase = evalsig(m,’lstb_phase’);
This Matlab is automatically run immediately after the
figure;
preceding script (Appendix C). It accepts the sparse set of subplot(2,1,1);
sizing+biasing constraints found in the previous script and uses semilogx(f, lstb_mag);
xlabel(’Frequency [Hz]’);
lookup function calls to flush-out the sizing and biasing of all ylabel(’Magnitude [dB]’);
the transistors in the circuit. Lastly, it automatically, updates title(’Loop Gain Bode Plot Simulation’);
grid;
the ’.sp’ HSpice netlist file to include the Matlab results.
Note: for brevity, only the transcription operation into the subplot(2,1,2);
semilogx(f, lstb_phase);
netlist used for LSTB analysis is reproduced below. The other ylabel(’Phase [deg]’);
transcriptions (for transient, Vod,peak and noise simulations) xlabel(’Frequency [Hz]’);
grid;
follow identical form.
Vgs_1 = lookupVGS(pch,’GM_ID’,gm_Id(index)/X,’VDS’,Vdd- %% Transient Simulation (small step)
Vt_comp-n_m23, ’VSB’,0,’L’,L_gain); m = loadsig(’part3_trans.tr0’);
Vgs_2 = lookupVGS(nch,’GM_ID’,gm_Id(index),’VDS’,n_m23, ’VSB lssig(m);
’,0,’L’,L_load);
Vgs_3 = lookupVGS(nch,’GM_ID’,gm_Id(index),’VDS’,n_m34-n_m23 time = evalsig(m, ’TIME’);
, ’VSB’, n_m23,’L’,L_gain); vid_step = evalsig(m, ’v_vsd’);
Vgs_4 = lookupVGS(pch,’GM_ID’,gm_Id(index),’VDS’,n_m45-n_m34 vod_step = evalsig(m, ’v_vod’);
, ’VSB’, Vdd-n_m45,’L’,L_gain);
Vgs_5 = lookupVGS(pch,’GM_ID’,gm_Id(index),’VDS’,Vdd-n_m45, cs_cf = 2; %Defined by spec
’VSB’, 0,’L’,L_load); ideal_vod_step = cs_cf*vid_step(length(vid_step));
static_ge = (vod_step(length(vod_step))-ideal_vod_step)/
Cl_selected = Cl; %(min_index) ideal_vod_step;
Cf_selected = Cf; %(min_index)
Cs_selected = Cs; %(min_index) settling_time = 0;%This section loops through to find the
Cn_selected = Cgd_1(index); settling time
Vg_selected = [Vdd-Vt_comp-Vgs_1 Vgs_2 Vds_load+Vgs_3 Vdd- for i = 1:length(vod_step)
Vds_load-Vgs_4 Vdd-Vgs_5]; %[vsc, nm2g, *nm3g, *mn4g, if(vod_step(i) > 0.999*vod_step(length(vod_step)))%0.999
mn5g] *=optimizable defined by dynamic spec
W_selected = [w_1(index) w_2(index) w_3(index) w_4(index) settling_time = time(i);
w_5(index)]; break;
It_selected = 2*It(index); %It*2 (value of current source in end
HSpice) end
fu_1 = wu_1/2/pi
Rself_selected = rself_result(index) figure;
subplot(2,1,1);
hold all;
%OUTPUT RESULTS TO HSPICE NETLIST plot(time, vod_step);
A = regexp( fileread(’part3_loop_template.sp’), ’\n’, ’split plot(time, ones(length(time),1)*ideal_vod_step);
’); legend(’Vod (simulated)’,’Ideal Output’);
A{5} = sprintf(’.param vocdes = %10.3f’,Vdd/2); xlim([0 40E-9]);
A{6} = sprintf(’.param vsc_param = %10.3f’,Vg_selected(1)); ylim([-ideal_vod_step/10 1.2*ideal_vod_step]);%Sets the y-
A{7} = sprintf(’.param vm2g_param = %10.3f’,Vg_selected(2)); axis to look nice
A{8} = sprintf(’.param vm3g_param = %10.3f’,Vg_selected(3)); xlabel(’Time (s)’);
A{9} = sprintf(’.param vm4g_param = %10.3f’,Vg_selected(4)); ylabel(’Vod (V)’);
A{10} = sprintf(’.param vm5g_param = %10.3f’,Vg_selected(5)) string = sprintf(’Transient Response (settling time = %2.2
; fns)’, 1E9*settling_time);
A{11} = sprintf(’.param it_param = %10.3fu’,It_selected title(string);
*10ˆ6); grid;
A{12} = sprintf(’.param cs_param = %10.3ff’,Cs_selected hold off;
*10ˆ15);
A{13} = sprintf(’.param cl_param = %10.3ff’,Cl_selected subplot(2,1,2);
*10ˆ15); end_value = vod_step(length(vod_step));
A{14} = sprintf(’.param cf_param = %10.3ff’,Cf_selected percent_error = 100*(vod_step-end_value)./end_value;
*10ˆ15); plot(time,percent_error);
A{15} = sprintf(’.param cn_param = %10.3ff’,Cn_selected legend(’Percent Error’);
*10ˆ15); xlim([settling_time-5E-9 settling_time+5E-9]);
A{16} = sprintf(’.param w1_param = %10.3fu’,W_selected(1)); ylim([-0.5 0.1]);%In units of percent
A{17} = sprintf(’.param w2_param = %10.3fu’,W_selected(2)); xlabel(’Time (s)’);
A{18} = sprintf(’.param w3_param = %10.3fu’,W_selected(3)); ylabel(’Percent Error (%)’);
A{19} = sprintf(’.param w4_param = %10.3fu’,W_selected(4)); title(’Percent Error to Steady State Value’);
A{20} = sprintf(’.param w5_param = %10.3fu’,W_selected(5)); grid;
A{21} = sprintf(’.param l1_param = %10.3fu’,L_gain);
A{22} = sprintf(’.param l2_param = %10.3fu’,L_load); %Plots of output common voltage, output differential current
A{23} = sprintf(’.param l3_param = %10.3fu’,L_gain); , differential
A{24} = sprintf(’.param l4_param = %10.3fu’,L_gain); %input
A{25} = sprintf(’.param l5_param = %10.3fu’,L_load);
fid = fopen(’part3_loop.sp’, ’w’); voc = evalsig(m, ’v_voc’);
fprintf(fid, ’%s\n’, A{:}); vop = evalsig(m, ’v_vop’);
fclose(fid); vom = evalsig(m, ’v_vom’);
iop = evalsig(m, ’i_vop_meas’);
 11

iom = evalsig(m, ’i_vom_meas’);

iod = iop-iom; figure
vid = evalsig(m, ’v_vsd’).*1000; semilogx(f, integ_sqrt);
xlabel(’f [Hz]’);
figure; ylabel(’Sqrt(Integral) [Vrms]’);
subplot(3,1,1); axis([min(f) max(f) 0 1.2*total_integrated_noise]);
hold all; string=sprintf(’Total Integrated Noise: Sqrt(Noise)=%2.2
plot(time,voc); fuVrms’, 1E6*total_integrated_noise);
plot(time,vop); title(string);
plot(time,vom); grid;
legend(’Voc’,’Vop’,’Vom’);
xlim([0 40E-9]);
xlabel(’Time (s)’); DR = 10*log10(0.5*v_odpeakˆ2/(total_integrated_noise)ˆ2)
ylabel(’Vout (V)’);
title(’Transient Response Output Voltage’);
hold off;

subplot(3,1,2);
hold all;
plot(time,iod);
plot(time,iop);
plot(time,iom);
legend(’Ioc’,’Iop’,’Iom’);
xlim([0 40E-9]);
xlabel(’Time (s)’);
ylabel(’Iout (A)’);
title(’Transient Response Output Current’);
hold off;

subplot(3,1,3);
hold all;
plot(time,vid);
legend(’Vid’);
xlim([0 40E-9]);
ylim([-2 12]);%sets the y axis to look nice
xlabel(’Time (s)’);
ylabel(’Vin (mV)’);
title(’Transient Response Input Voltage’);
hold off;
%% Vod_peak Analysis
m = loadsig(’part3_peak.sw0’);
lssig(m);
vod = evalsig(m, ’v_vod’);
vsd = evalsig(m, ’v_vsd’);
gain = vod./vsd;

figure;
plot(vod, gain);
xlabel(’Vod (V)’);
ylabel(’Vod/Vsd’);
title(’Differential Output Swing’);
grid;

diff_gain_goal = max(gain)*0.7; %30 percent drop from peak

[residual_value, residual_index] = min(abs(gain -
diff_gain_goal));
v_odpeak = abs(vod(residual_index(1)))
v_sdpeak = v_odpeak/2;

%% Noise Simulation
m = loadsig(’part3_ac.ac0’);
lssig(m);
f = evalsig(m, ’HERTZ’);
no = evalsig(m, ’outnoise’);
ni = evalsig(m, ’innoise’);
integ = cumtrapz(f, no);
integ_sqrt = sqrt(integ);
total_integrated_noise = integ_sqrt(end);

% Plot the results

figure;
subplot(2,1,1)
loglog(f, no);
xlabel(’f [Hz]’);
ylabel(’PSD [Vˆ2/Hz]’);
axis([min(f) max(f) min(no)/10 10*max(no)]);
title(’Output Noise’);
grid;

subplot(2,1,2)
loglog(f, ni);
xlabel(’f [Hz]’);
ylabel(’PSD [Vˆ2/Hz]’);
axis([min(f) max(f) min(ni)/10 10*max(ni)]);
title(’Input Noise’);
grid;