Incorporating Advanced Instrumentation Capabilities

into a PXI Digital Multimeter Instrument

Jeff Robins Michael Dewey
Geotest-Marvin Test Systems Geotest – Marvin Test Systems
Irvine, CA, USA Irvine, CA, USA

Abstract—The use of card modular instrumentation for ATE reduce the overall footprint of the ATE system. However,
systems offers test engineers many benefits - including lower providing equivalent or better DMM performance in a PXI
acquisition costs, a more compact system footprint, and higher form factor presents significant design challenges which are
performance when compared to "box based" ATE architecture. detailed in the following sections.
In particular, upgrading to the PXI architecture can decrease
both the physical and budgetary footprints, while still meeting II. BACKGROUND: HIGH-PERFORMANCE DMM
the overall test requirements. However, for T&M instrument CHARACTERISTICS & ARCHITECTURE
suppliers, incorporating the features and capabilities associated
with advanced instrumentation into the PXI form-factor can High-performance DMMs are generally categorized by
present several design challenges, particularly in the areas of measurement resolution in digits: 4.5 digits, 5.5 digits, etc. The
volume / real estate, noise, power consumption, and measurement resolution of a DMM is defined as follows:
stability. Additionally, these demanding requirements can be
further challenged when the instrument is required to operate Number of digits =
beyond the "normal" temperature range associated with
commercial instrumentation.
log10((span of range) / (resolution of range) or

This paper discusses the requirements and techniques used to (range resolution) = (span of range) / (10(Number of digits))
develop a PXI-based, high performance DMM. A review of the
required performance parameters is presented along with an Using a 6.5 digit DMM and a 10V (+/-10V) range, the DMM’s
analysis of the alternative design methods employed in order to resolution is (2x10V)/(106.5) or 6.3uV[1]. Common practice is
achieve the necessary performance capabilities without to round the actual number of digits to the nearest half-digit.
compromising the overall capabilities of the hardware. Areas
Therefore a 6.5 digit DMM can actually have a resolution as
covered in this paper include a discussion of design techniques
which includes the use of multi-function circuitry to reduce low as 6.251 digits or as high as 6.750 digits, which results in a
overall volume requirements, the conversion of purely analog resolution ranging from 11.2uV to 3.6uV.
circuitry into a mixed signal format to reduce volume and power High-performance DMMs have a specified
requirements, minimizing power supply noise when replacing a measurement drift compared to hand-held or low performance
mains-based power supply with isolated and non-isolated DC/DC DMMs. In many cases where the resolution of a high-
circuitry and the requirement to operate over an extended performance DMM is not required, the low drift, both in
temperature range. Additionally, a review of the overall temperature and time, may be the guiding reason in choosing a
mechanical design with attention to the need to accommodate the high-performance DMM. If a guaranteed absolute accuracy is
noise and airflow considerations associated with the PXI
required for an extended period of time and/or over a large
architecture is discussed.
temperature range, then a high-performance DMM, calibrated
Index Terms— DMM, PXI, digital multimeter, modular with a suitable source, can stretch calibration intervals to
instrumentation, mixed signal multiple years. In many cases the savings from yearly
calibration costs will cover the extra cost of a high-
I. INTRODUCTION performance DMM many times over during the product’s
lifetime.
Measuring voltage, current, resistance and, many times, High-performance DMMs employ integrating analog
frequency is an integral part of most test procedures. A high to digital converters (ADCs). For advanced integrating
performance DMM (Digital Multimeter) is required for most converters, adding one bit of resolution to an existing design
automated test systems and fulfills the need for an automated requires either a doubling of integration time or a redesign of
test instrument that can provide high accuracy and stable the circuit so that it functions twice as fast. Adding extra bits
baseband measurements. Many times this requirement is met by redesigning the circuit runs into problems with injected
by incorporating a bench-top DMM as part of an ATE system. noise and complexity. Doubling the time of the integration
However, with the increasing use of card modular based ATE leads to a halving of the conversion rate and many times moves
systems such as PXI, the incorporation of a PXI-based, high- the integration time out of the converter’s “sweet spot” where
performance, DMM offers test engineers the ability to further noise is the lowest. The “sweet spot” is a balance between

978-1-4673-0700-0/12/$31.00 ©2012 IEEE

noise reduction which is associated with setting the integration specifications, the minimum spacing for reinforced insulation is
time to a multiple of the line frequency and measurement drift 3mm – creating significant mechanical assembly challenges for
of the DMM, mainly due to drifting of the internal voltage a two-board assembly. 10mm was chosen for the spacing
reference. Most high-performance DMMs have a sweet spot between the 2 board assembly, allowing for a combined height
between 2 and 5 line cycles. A longer integration time of 6.7mm (0.3mm was allocated for process variations) for
decreases the noise in the circuit by averaging the input components positioned between the two boards and where
voltage, but the error due to the voltage reference drift becomes safety spacing is required. The Earth-grounded shield of the
larger than the reduction in noise. The drift is caused by both PXI connector, the banana jack connectors and the transformer
aging and 1/f noise. The 1/f noise that is seen will be very low providing power supply isolation, limited the usable area on the
in frequency and will appear mostly as drift. A DMM can be bottom CCA (interface CCA) to 12.1k mm2 and the usable area
designed so that the resolution is higher during a reading taken of the top CCA (measurement CCA) to 13.5k mm2, resulting in
in the “sweet spot,” but there isn’t much that can be done to a combined usable area of 25.6k mm2 – a reduction in area of
decrease the noise and drift from the reference, thereby limiting 43% compared to a bench top DMM. With both sides of the
the integration time and the possible resolution of an integrator- CCA's used for IC's and passive components, extensive use of
based DMM. 3D modeling was required to ensure that the boards fit together
The same process that allows an integration-based and that the necessary safety spacing requirements were met.
ADC to attain a higher level of resolution at a slower rate, Figure 2 details the assembled PXI DMM with the two board
limits its speed at low resolution. For most high-performance assembly.
DMMs on the market, the highest rate is limited to less than
10k readings per second at a resolution of 3.5 digits, which is
less than 12 bits. ADC’s with 12 or more error free bits are
readily available on the market and most are multiple orders of
magnitude faster than the integration-based converters. For
instance, the PXI DMM described in this paper uses an ADC
running at 3M samples per second, with an error-free resolution
of over 15-bits.
III. IMPLEMENTING A PXI DMM

A. Mechanical Design .
Replicating the features and capabilities associated with a Figure 2 – PXI DMM
bench-top DMM (Figure 1) into a 3U PXI form factor presents
significant challenges.
B. Power Supplies
Most bench-top DMMs use an AC isolating transformer
with linear regulators to create the needed rail voltages. Lower
voltages generally pass through a series of regulators to reach
the target rail voltage, thereby minimizing the number of taps
and rectifier circuits needed. The AC line frequencies are
easily filtered out by the linear regulators. However, this
power supply method produces a large amount of dissipated
power and is not very efficient from a real estate usage
Figure 1 – Typical Bench-Top DMM standpoint.
The dimensions of a bench-top DMM are approximately A PXI DMM has the advantage of using DC voltages
210mm x 315mm x 85mm, representing an overall volume of from the PXI backplane, which eliminates the need for a large
5600k mm3 (343 inches3). The dimensions of a single-slot PXI isolation transformer and multiple rectification stages on the
card are approximately 100mm x 160mm x 20mm, card. In most cases the logic can operate directly from the
representing a volume of 320k mm3 (19.5 inches3) and supplied 5V and/or 3.3V rails. In cases where other rails are
requiring a volume reduction of 94 percent. Note that a needed, a small linear regulator or a buck-converter can supply
benchtop DMM also includes a transformer, connectors, a the needed voltages without producing a large amount of
display CCA (circuit card assembly) and a fan. The dissipated power. However, the backplane voltages are not
approximate area available within a bench-top DMM for isolated from Earth-ground and therefore cannot be used
circuitry is 45k mm2. With a generous volume within the unit, directly by any circuitry requiring isolation.
meeting the necessary isolation and routing needs for safety For the PXI DMM design, a push-pull forward converter is
spacing is not a challenge. used to provide isolated power to the DMM. The push-pull
For a single slot, 3U PXI card, available board area is 16k forward converter was chosen because of the low voltages
mm2 and if two boards are utilized, this area can be doubled. available for switching and the moderately low power
However, in order to meet the 300V, CAT II device safety requirements. The isolated voltage is passed through DC/DC
converters to provide multiple positive and negative, low the 128-bit multiplication result needs to be divided by a 64-bit
current “dirty” rails. These rails are then sent through multi- integer, which can be easily done in software, but not quickly.
pole low pass filters to remove the higher frequency switching Consequently, to speed up the computation, a custom 128-bit
noise and finally through linear regulators. This process by 128-bit division peripheral was created in Verilog and
provides clean voltages at a high efficiency. Conducted noise instantiated in the FPGA. The resulting implementation
is kept to a minimum by the low pass filters and by selecting provides for a computation process that is much faster than
switching frequencies that are above the input frequency range performing the computation as double math or performing the
of the integrating converter. Radiated noise is reduced by fixed-point division in software.
placing an inner shield between the isolated DC/DC converters Early in the design process, the CPU speed was identified
and the measurement circuits. The result is a low noise as a limiting factor. It was determined that polling based
environment that is compatible with the performance communication and processor managed peripheral
requirements associated with a 6.5 digit DMM. communication routines would require too much CPU time,
limiting the DMM’s acquisition rate. Consequently, logic-
based state machines were implemented wherever possible,
C. Reducing Logic Circuit Size
with interrupts used for servicing the various measurement and
Programmable logic has been used in the past to provide communication events. The end result is a system which runs
special purpose peripheral functionality for the processors used comfortably at 100 MHz, and provides a large degree of
to control bench-top DMMs. In addition, much of the glue flexibility and capability. Most tasks are handled outside of the
logic has been migrated into the programmable logic. main processor including communicating across the isolation
However, in many cases separate ICs, many times with their barrier, transferring data to the PCI bus and reading the PWM
own RAM chips, have been used to provide communication outputs from the temperature sensors. For reading of data from
between the DMM’s processor, Ethernet, GPIB and/or USB the digitizer, processor interaction is limited to setting up,
interfaces. The result is that even with an FPGA, real estate starting the acquisition, and then waiting for completion of the
requirements for digital logic can become extensive on the acquisition. Offset corrections and statistical analysis of the
Earth-grounded side of the DMM. This extra circuitry increases digitized data is performed by logic instantiated in the FPGA,
the power requirements and routing complexity of the board as minimizing the CPU’s interaction with the data acquisition and
well. post calculation of results.
For a PXI DMM, use of an FPGA is essential in order
minimize real estate. By using a medium size FPGA to
integrate the processor, any required peripherals, most glue E. Analog Input Circuitry and Signal Conditioning
logic and the PCI interface; it is possible to combine all of Bench-top DMMs dedicate substantial real estate to
these functions into a single package, with a small footprint of isolation and input signal conditioning circuitry. The input
just 19mm x 19mm. Further reductions are achieved by using section needs to maintain safety spacing so that hazardous
multi-channel digital isolators and serial flash memory to store impulses applied to the input will not reach the user. In
the FPGA image - the soft-core processor’s code and all addition, the latest IEC/UL 61010 specification adds the
calibration data. As a result, overall power usage of the Earth- requirement that those same impulses, when applied to any
grounded digital logic is reduced to less than 1W and the input and for any function other than current measure mode,
required real estate area is reduced to less than 1.6k mm2. cannot damage the DMM. Consequently, protection of all four
DMM inputs - the Lo and High inputs as well as the High and
D. Measurement Signal Processing & Module Control
Lo 4-wire sense inputs must be protected. This requirement
An Altera NIOS 32-bit soft-core processor, operating at increases the required protection circuitry and associated real
100MHz is used for processor operations. However, the estate. To address these protection requirements, the design
processor speed is limited by the speed of the logic in the employs a 3-pole gas discharge tube device, surface-mount
FPGA and the size of the FPGA. In addition, the processor varistors and high-pulse capacitors, reducing overall space
does not have a double precision floating point unit, which requirements.
severely limits the speed at which it can perform math High input voltages need to be divided down to a level that
functions. A double precision floating point (double) math the signal conditioning circuitry can use. In many cases the
function can require between 3k and 5k processor clock cycles dividers used for DC measurements are time and temperature
which is much too slow for this application. As a result, fixed stable but are highly unstable over frequency. Consequently,
point math is used to perform most multiplications or divisions. two dividers are typically used with a relay to select for AC or
The DMM returns raw measurements and stores correction DC operation. However, this topology is incompatible with a
values internally as 64-bit fixed point integers. Every DMM design that is spaced constrained. For the PXI DMM, one
measurement requires at least the multiplication of two 64-bit divider is employed that is time and temperature stable as well
integers and the division of the result by a 64-bit integer. The as frequency stable up to 1 GHz. The frequency stability of the
multiplication of two 64-bit integers can be done easily and divider also reduces the amount of AC compensation circuitry
quickly in software. The result, which would take about 3k that is normally present in bench-top designs.
clock cycles to compute if using double math, takes only about Over-voltage protection is an integral part of a DMM
100 clock cycles using a fixed point computation. However, design and most bench-top DMMs provide over-voltage
protection using two methods. The first method employs a “PROT_NV”, except the voltage drop is across Q2 and R4. R2
large resistance value on the inputs to DMM. Note that the and R4 limit the current required to flow through K1 and K2's
power dissipated by the input resistors goes up with the square MOSFETs to maintain control. Based on a voltage drop of
of the voltage: 0.65V across Q1 or Q2 and a 20k resistor, the current required
to reach the 1.4V limit is about 38uA. When the input voltage
W = (V2)/R. is between “PROT_PV” + 1.4V and “PROT_NV” minus 1.4V,
BLK1 stops the current flowing into the base of Q3, which
At the maximum rated DC input voltage, this resistance can be causes K1 and K2 to be fully on. When K1 and K2 are fully
dissipating more than 1W. Typically, the resistance value is on, the input resistance is low enough for use as an AC signal
made up of multiple resistors, distributing the dissipated power path.
and high voltage across multiple devices. Safety spacing is not The method described above is very similar to the dual
required, but functional spacing still limits the area required for MOSFET method employed for over- voltage control, in that
these resistors. The presence of this resistance on the input also there is a constant voltage and the wattage increases linearly
creates a low pass filter, making it unusable for AC signal path with the voltage. However, the PhotoMOS implementation
measurements. Consequently, this method is used only on the requires much less area. Only the two pins connecting the
resistance sense inputs. series SSRs need to be isolated from the rest of the circuitry.
The second method uses source-connected MOSFETs to For this design, the constant current is about 38uA, the low
provide a 2-way variable resistance. The gates of the side of the SSR protection is about 13.4V and the rated input
MOSFETs are driven by a photovoltaic, which provides an voltage is 300V resulting in a dissipated power of 11 mW:
optically isolated voltage source, but at low current. A small (300V-13.4V)*(38uA) = 11mW, which is considerably less
amount of current is always allowed to flow through the power when compared to the series resistance method.
MOSFETs when in over-voltage mode, which allows a
feedback circuit to dynamically control the resistance of the
MOSFET pair by limiting the output of the photovoltaic. This
method operates under a constant current condition, so the
dissipated power goes up linearly with the voltage (W = VI).
When a large negative amplitude voltage is applied to the
input, the MOSFETs’ source terminals are a diode drop from
the input voltage, which means that the sources and gates of the
MOSFETs, the output of the photovoltaic, a load resistor and
capacitor for the photovoltaic, and any circuitry used to load
down the photovoltaic must be isolated from the rest of the
input circuitry. The required isolation and physically large
MOSFETs require more space and a more complex layout
when compared to the series resistance method. However,
unlike the resistance protection scheme this implementation
provides a viable signal path for measuring AC signals.
Figure 3 – Input Protection Circuit
To achieve the needed over-voltage protection and yet
minimize required real estate, the PXI DMM employs
Panasonic PhotoMOS solid state relays (SSRs) on all isolated Most high-performance bench-top DMMs use an analog
inputs. These integrated devices provide an optically isolated, circuit, which converts an AC input signal to a DC value. This
low capacitance, high voltage, variable 2-way resistance in a type of circuit requires a temperature and time stable capacitor
small package. Two of these devices in series provide 800V of in the range of 2.2uF, which is physically large. For example,
input protection, which is higher than the activation voltage of the Vishay MKT 1822-522-065 capacitor has the following
the gas discharge tubes that provide impulse protection. dimensions: 7.5mm x 13.5mm x 18.0mm (W x H x L). With a
height of 13.5 mm, this component is incompatible with a dual
Figure 3 shows the basic SSR input circuit. The input
voltage enters through the “input” node and flows through the board implementation. Consequently, the decision was made to
MOSFETs of K1 and K2. R3 limits any inrush current. If the perform RMS measurements using a sampling technique with a
voltage is 0.65V higher than “PROT_PV”, then current will fixed-point square root function. Due to the nature of the RMS
flow through Q1, which is a JFET and is used as an extremely formula, the DC ground error must be removed before using
low current leakage current diode. When the current flow is the samples for computation. This adjustment is done in the
capture peripheral logic, providing the CPU with corrected data
high enough to cause a 1.4V drop across Q1 and R2, BLK1
causes current to flow into the base of Q3, which lowers the and minimizing CPU computation time. The ground offset is
voltage across K1 and K2's diodes. The drop in voltage also determined during a self - calibration period. Note that by
lowers the current flowing through the diodes and therefore calculating the RMS mathematically, any limitations associated
raises the resistance across the MOSFETs of K1 and K2. The with crest factor are eliminated as long as the peak input value
same mechanism happens when the voltage is less than falls within the limits of the instrument’s range. And as an
additional benefit, the use of a digitizing function provides the
user with an isolated, 3MS/s digitizer which can be used for IV. CONCLUSION
general purpose data acquisition applications. Developing a card modular DMM based on the 3U PXI
form factor presents significant challenges. However, by
leveraging the latest advances in both analog and digital circuit
F. Extending a DMM’s Operating Temperature Range technologies, a 6.5 digit, performance DMM can be produced
that provides equal performance to a bench-top DMM with a
High performance DMMs are inherently laboratory
much smaller form factor and with expanded capabilities.
instruments. They provide a high resolution, low error, stable
Some the key advances include:
measurement, but only when used in a laboratory-like
environment. However, a DMM can be used outside its
laboratory environment, but the quality of the measurement • An 80% reduction in total power dissipated, from
will degrade and operation is guaranteed only within the 70 VA for a bench top DMM to 13W for the PXI
commercial temperature range (0C to 50C). Measurement DMM
degradation can be kept to a minimum by using components • A 94% reduction in overall size of the PXI DMM,
with temperature stable values, however, the overall compared to a bench top DMM
temperature range of operation will still be limited. This can be • The addition of an isolated / floating 3MS/s , 16
mitigated by procuring components that are specified for bit digitizer for AC and data acquisition
industrial or military temperature ranges, but the system as a measurements
whole must be carefully designed to handle the demands • Extended operating temperature range for
associated with operating over an extended temperature range. ruggedized / field environments
Providing a PXI DMM that can work over an extended
temperature range (-20 to +70 C) offers end users the option to With judicious use of FPGA logic and embedded software
deploy PXI systems in the field and on the flight line (reference functions, users now have available to them an advanced,
L. Gutterman’s Autotestcon 2009 paper: “PXI Based Flight- feature rich 6.5 digit DMM for the PXI platform for field or
Line Test Sets”). For high temperature operation, careful layout depot level ATE applications.
and board cuts are required to minimize self-heating effects.
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use the maximum amount of current to bring the voltage
reference up to the target temperature. This presents a large
load on the isolated power supply and can cause the system to
go into current limit on startup. To limit the load to a
reasonable amount of current, startup current is limited to the
reference and a defined power-on sequence is employed. At
turn on, all of the switching power supplies start-up one at a
time, with the next power supply in the sequence waiting until
the previous power supply has reached at least 90% of its final
level. When all of the power supplies are operating, the heater
is enabled and once the heater current drops to a reasonable
level, the analog supply’s LDO (low drop out) regulators are
enabled. Finally, after all of the analog circuitry is up and
running the digital supply LDOs are enabled. The complete
sequence requires about 10s at room temperature, but can
require up to 1 minute at -20 C. Temperature monitoring is
provided at all times by the FPGA, providing the user with a
status of the isolated circuitry – i.e. warming or ready. All of
the Earth-grounded circuitry operates at -20 C, allowing the
user to always have access to the device, without waiting for
warm-up.