Micro

NG

CMOS
DESIGN

BANG-SUP SONG
Micro
CMOS
DESIGN
Circuits and Electrical Engineering Series
Series Editor
Wai-Kai Chen

MicroCMOS Design
Bang-Sup Song

FORTHCOMING

Multiple-Base Number System: Theory and Applications

Vassil Dimitrov, Graham Jullien, and Roberto Muscedere
Micro
CMOS
DESIGN
BANG-SUP SONG

Boca Raton London New York

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Taylor & Francis Group, an informa business
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Contents

Preface............................................................................................................................................ xiii
Acknowledgments.........................................................................................................................xv
The Author................................................................................................................................... xvii

1. Amplifier Basics.......................................................................................................................1
1.1 Driving-Point and Transfer Functions........................................................................ 1
1.2 Frequency Response...................................................................................................... 2
1.3 Stability Criteria.............................................................................................................5
1.4 Operational Amplifier (Opamp) in Negative Feedback...........................................6
1.5 Phase Margin..................................................................................................................9
1.6 Transient Response...................................................................................................... 12
1.7 Feedback Amplifier...................................................................................................... 14
1.8 Feedback Effect............................................................................................................. 16
1.8.1 Linear Range Improvement.......................................................................... 18
1.9 Left-Half or Right-Half Plane Zero............................................................................ 19
1.10 Stability of Feedback Amplifiers................................................................................22
1.10.1 Frequency-Dependent Feedback Factor......................................................22

2. Amplifier Design................................................................................................................... 27
2.1 Abstract Low-Frequency Model of Transistors....................................................... 27
2.1.1 Large Signals................................................................................................... 27
2.1.2 Small Signals................................................................................................... 28
2.1.3 Transconductance gm and Output Resistance ro. ....................................... 29
2.1.4 Small-Signal Model........................................................................................ 30
2.1.5 Body Effect....................................................................................................... 31
2.2 Driving-Point Resistances at Low Frequencies........................................................ 32
2.3 Resistance Reflection Rules........................................................................................34
2.3.1 Local Shunt Feedback..................................................................................... 37
2.4 Three Basic Amplifier Configurations...................................................................... 39
2.5 Nine Amplifier Combinations................................................................................... 41
2.5.1 CS-CS................................................................................................................ 41
2.5.2 CS-CG............................................................................................................... 41
2.5.3 CS-CD...............................................................................................................44
2.5.4 CG-CS, CG-CG, CG-CD.................................................................................44
2.5.5 CD-CS............................................................................................................... 45
2.5.6 CD-CG.............................................................................................................. 45
2.5.7 CD-CD.............................................................................................................. 46
2.6 Differential Pair............................................................................................................ 46
2.6.1 Common-Mode Rejection.............................................................................. 46
2.6.2 Symmetric Transfer Function....................................................................... 47
2.7 Gain Boosting............................................................................................................... 48
2.7.1 Doublet Constraints........................................................................................ 49
2.7.2 Other Gain-Boosting Concepts..................................................................... 50

v
vi Contents

2.8 Biasing........................................................................................................................... 51
2.8.1 Cascode Biasing for Maximum Swing........................................................ 52
2.8.2 Current Source Matching.............................................................................. 53
2.9 Voltage and Current Sources......................................................................................54
2.9.1 VGS and ∆VGS-Referenced Current Sources..................................................54
2.9.2 Bandgap Reference......................................................................................... 55
References................................................................................................................................ 59

3. Operational Amplifier (Opamp)......................................................................................... 61

3.1 Small-Signal Model of the Operational Amplifier.................................................. 61
3.2 Opamp Frequency Compensation............................................................................64
3.2.1 Shunt Compensation......................................................................................64
3.2.2 Pole-Splitting Miller Compensation............................................................65
3.3 Phase Margin of Two-Stage Miller-Compensated Opamps.................................. 69
3.4 Right-Half Plane Zero Cancellation in Two-Stage Opamps.................................. 70
3.4.1 Inserting a Series Resistance......................................................................... 71
3.4.2 Using Source Follower for Feedback............................................................ 72
3.4.3 Boosting Gm with Extra Gain Stage.............................................................. 73
3.5 Transient Response of Opamp in Feedback............................................................. 73
3.5.1 Slew Rate.......................................................................................................... 74
3.5.2 Maximum Power Bandwidth........................................................................ 75
3.6 Opamp Design Examples...........................................................................................77
3.6.1 Telescopic Triple Cascode Opamp................................................................77
3.6.2 Folded-Cascode Opamp................................................................................ 79
3.6.3 Gain-Boosted Cascode Opamp.....................................................................80
3.6.4 Two-Stage Opamp.......................................................................................... 81
3.7 Common-Mode Feedback........................................................................................... 82
3.7.1 Common-Mode Loop Requirements...........................................................83
3.7.2 Continuous-Time Common-Mode Feedback..............................................84
3.8 Offset Cancellation...................................................................................................... 85
3.9 Opamp Input Capacitance.......................................................................................... 88
3.10 Opamp Offset............................................................................................................... 89
3.11 Opamp Noise................................................................................................................ 91
3.12 Opamp Common-Mode Rejection............................................................................. 93
References................................................................................................................................ 94

4. Data Converter Basics........................................................................................................... 95

4.1 Analog-to-Digital Converter Basics........................................................................... 95
4.1.1 Aliasing by Sampling..................................................................................... 95
4.1.2 Quantization Noise........................................................................................ 95
4.1.3 Signal-to-Noise Ratio...................................................................................... 98
4.1.4 Differential and Integral Nonlinearity...................................................... 100
4.1.5 DNL-Related Low-Level Distortion........................................................... 101
4.1.6 Nyquist-Rate Sampling versus Oversampling......................................... 103
4.2 Sample and Hold........................................................................................................ 104
4.2.1 Charge Injection and Clock Feed-Through............................................... 106
4.2.2 Nonlinearity of Sampling Switch............................................................... 107
4.2.3 Bottom-Plate Sampling................................................................................ 108
4.2.4 Clock Boosting.............................................................................................. 110
Contents vii

4.2.5 Clock Feed-Through Effect on Offset........................................................ 113

4.2.6 kT/C Noise and Clock Jitter.......................................................................... 114
4.3 Flash Analog-to-Digital Converter.......................................................................... 117
4.3.1 Kickback and Sparkle Noise........................................................................ 118
4.4 Comparator................................................................................................................. 120
4.4.1 Preamplifier................................................................................................... 120
4.4.2 Regenerative Latch........................................................................................ 123
4.4.3 Comparator Design...................................................................................... 125
4.5 ADC Testing................................................................................................................ 126
4.5.1 ADC Figure of Merit..................................................................................... 129
4.6 Averaging and Interpolation Techniques............................................................... 129
4.6.1 Offset Averaging........................................................................................... 129
4.6.2 Interpolation.................................................................................................. 131
4.7 Low-Voltage Circuit Techniques.............................................................................. 134
4.7.1 Low Bound of Analog Supply..................................................................... 134
4.7.2 Switched-Opamp Technique....................................................................... 136
4.7.3 Current-Mode Circuits................................................................................. 136
4.8 Digital-to-Analog Converter Basics......................................................................... 138
4.8.1 DAC Accuracy Considerations................................................................... 139
4.8.2 Limited Slew Rate......................................................................................... 139
4.8.3 Code-Dependent Time Constant................................................................ 141
4.8.4 Glitches........................................................................................................... 141
4.8.5 Word Clock Jitter........................................................................................... 142
References.............................................................................................................................. 142

5. Nyquist-Rate Data Converters.......................................................................................... 145

5.1 Analog-to-Digital Converter Architectures........................................................... 145
5.2 Slope-Type ADC......................................................................................................... 147
5.3 Successive Approximation Register ADC.............................................................. 149
5.3.1 Accuracy Considerations............................................................................. 151
5.3.2 SAR ADC with R + C, C + R, or C + C
Combination Digital-to-Analog Converter............................................... 151
5.4 Subranging and Multistep ADC.............................................................................. 154
5.4.1 Residue........................................................................................................... 154
5.4.2 Evolution of Multistep and Pipeline Architectures................................. 156
5.5 Pipelined ADC........................................................................................................... 157
5.5.1 Residue Plot................................................................................................... 158
5.5.2 Capacitor-Array Multiplying DAC............................................................. 159
5.5.3 Accuracy Considerations............................................................................. 161
5.5.4 Digital Correction......................................................................................... 162
5.5.5 Generalized N-Bit Pipeline Stage............................................................... 164
5.5.6 Trilevel Multiplying Digital-to-Analog Converter (MDAC)................... 165
5.5.7 Capacitor Matching...................................................................................... 169
5.5.8 Opamp Gain Requirement.......................................................................... 170
5.5.9 Opamp Bandwidth Requirement............................................................... 172
5.5.10 Noise Considerations................................................................................... 174
5.5.11 Optimum Number of Bits per Stage.......................................................... 174
5.5.12 Scaling Pipelined ADC................................................................................ 175
5.5.13 S/H-Free Pipelined ADC............................................................................. 176
viii Contents

5.6 Folding ADC............................................................................................................... 177

5.6.1 Accuracy Considerations............................................................................. 179
5.6.2 Cascaded Folding.......................................................................................... 181
5.7 Other ADCs................................................................................................................ 183
5.7.1 Algorithmic ADC.......................................................................................... 183
5.7.2 Time-Interleaving ADC............................................................................... 184
5.7.3 Opamp-Sharing ADC.................................................................................. 187
5.7.4 Dynamic Low-Voltage Low-Power Design............................................... 189
5.7.5 Time-Domain ADC...................................................................................... 190
5.8 Stand-Alone DACs..................................................................................................... 192
5.8.1 Resistor-String DAC..................................................................................... 192
5.8.2 Current-Steering DAC.................................................................................. 194
5.8.3 Segmented DAC for Monotonicity............................................................. 195
References.............................................................................................................................. 196

6. Oversampling Data Converters........................................................................................ 199

6.1 Concept of Quantizer in Feedback.......................................................................... 199
6.1.1 Active Filter by Feedback............................................................................. 199
6.1.2 Loop Stability................................................................................................ 201
6.1.3 Quantization Noise Shaping....................................................................... 201
6.1.4 Loop Filter and Bandwidth Requirements............................................... 203
6.2 ∆Σ Modulator.............................................................................................................. 205
6.2.1 Quantization Error Estimation................................................................... 206
6.2.2 Quantization Noise Shaping....................................................................... 207
6.2.3 Signal-to-Quantization Noise..................................................................... 208
6.2.4 Stability and Integrator Overload............................................................... 209
6.3 High-Order Architectures........................................................................................ 212
6.3.1 Direct Multiloop Feedback.......................................................................... 212
6.3.2 Single-Loop Feedback.................................................................................. 213
6.3.3 Cascaded Modulators................................................................................... 215
6.4 Discrete-Time (DT) versus Continuous-Time (CT) Modulators.......................... 216
6.5 Discrete-Time Modulator Design............................................................................ 217
6.5.1 Switched-Capacitor Integrators.................................................................. 217
6.5.2 Multibit Integrator versus Multiplying Digital-to-Analog
Converter........................................................................................................ 220
6.5.3 Multilevel Feedback Digital-to-Analog Converters................................. 221
6.5.4 Design Considerations.................................................................................223
6.5.5 Broadband Modulators................................................................................ 224
6.6 Band-Pass Modulator Design................................................................................... 227
6.7 Continuous-Time Modulator Design...................................................................... 230
6.7.1 Continuous-Time ∆Σ Modulator................................................................. 230
6.7.2 Built-In Anti-Aliasing and Blocker Filtering............................................. 230
6.7.3 DAC Pulse Position and Pulse Width Jitters............................................. 232
6.7.4 Current DAC versus Switched-Capacitor DAC........................................234
6.7.5 Integrators for SC-DAC................................................................................ 236
6.7.6 Quantizer Meta-Stability............................................................................. 237
6.7.7 CT Modulator Architectures....................................................................... 238
6.7.8 Integrator Design Considerations.............................................................. 240
Contents ix

6.7.9 G m-C Integrators........................................................................................... 241

6.7.10 RC Integrators................................................................................................ 241
6.7.11 Feedback Path Design.................................................................................. 244
6.7.12 Filter Time-Constant Calibration................................................................ 245
6.8 Interpolative Oversampling DAC............................................................................ 249
6.8.1 ∆Σ Modulator as Digital Truncator............................................................ 249
6.8.2 One-Bit or Multibit DAC.............................................................................. 250
6.8.3 Monotonic Oversampling Bitstream DAC................................................ 251
6.8.4 Postfiltering Requirement............................................................................ 251
References.............................................................................................................................. 252

7. High-Resolution Data Converters.................................................................................... 255

7.1 Nonlinearity of the Analog-to-Digital Converter................................................. 255
7.1.1 Inaccurate Residue in Pipelined Analog-to-Digital
Converters...................................................................................................... 256
7.1.2 Missing Codes and Nonmonotonicity....................................................... 257
7.2 Evolution of High-Resolution ADC Design........................................................... 259
7.2.1 Device and Supply Voltage Scaling............................................................ 259
7.2.2 Broadband High Spurious-Free Dynamic Range
Applications................................................................................................... 259
7.2.3 High-Resolution ADC Techniques............................................................. 260
7.2.4 Inherently Linear Analog Techniques....................................................... 261
7.2.5 Self-Calibration of Successive Approximation Register ADC................ 262
7.3 Digital Calibration of ADC....................................................................................... 263
7.3.1 Digital Calibration Concept........................................................................ 264
7.3.2 Multiplying Digital-to-Analog Converter
Capacitor Error Calibration......................................................................... 264
7.3.3 Linear MDAC Gain Error Calibration....................................................... 266
7.3.4 MDAC Gain Nonlinearity Calibration...................................................... 267
7.4 Digital Background Calibration............................................................................... 268
7.4.1 Background Capacitor Error Measurement.............................................. 270
7.4.2 Gain Error Measurement by Pseudo-Random Dithering....................... 271
7.4.3 Constraints in PN Dithering....................................................................... 274
7.4.4 Signal-Dependent PN Dithering................................................................ 274
7.5 Digital Processing for Gain Nonlinearity.............................................................. 278
7.5.1 Weakly Nonlinear Gain Error..................................................................... 278
7.5.2 Gain Nonlinearity Measurement by PN Dithering................................. 279
7.5.3 Measurement by Signal Correlation.......................................................... 280
7.5.4 Multilevel PN Dithering.............................................................................. 281
7.5.5 Accuracy Considerations for Background Error Measurement............ 281
7.6 Calibration by Zero-Forcing Least-Mean-Square Feedback................................284
7.6.1 LMS Feedback Concept................................................................................284
7.6.2 Self-Trimming................................................................................................284
7.6.3 LMS Adaptation for Digital Background Calibration............................. 286
7.7 Calibration of Time-Interleaving ADC................................................................... 288
7.7.1 Offset Mismatch............................................................................................ 288
7.7.2 Gain Mismatch.............................................................................................. 289
7.7.3 Sample-Time Error........................................................................................ 289
x Contents

7.8 Calibrated Continuous-Time (CT) ∆Σ Modulators................................................ 291

7.8.1 Pipeline versus Continuous-Time ∆Σ Modulator..................................... 291
7.8.2 Noise Leakage in CT Cascaded ∆Σ Modulator......................................... 292
7.8.3 Continuous-Time to Discrete-Time Transform......................................... 293
7.8.4 CT-to-DT Transform of Integrators............................................................ 294
7.8.5 CT-to-DT Transform of Resonators............................................................ 295
7.8.6 Half-Cycle Delay Effect................................................................................ 297
7.8.7 Noise Transfer Function (NTF) for Single-Loop
CT ∆Σ Modulator.......................................................................................... 298
7.8.8 NCF for CT Cascaded ∆Σ Modulator.........................................................300
7.8.9 STF and Built-In Anti-Aliasing in Cascaded CT-DSM............................ 301
7.8.10 Noise Leakage Cancellation in CT Cascaded Modulators..................... 302
7.8.11 Operational Amplifier Finite DC Gain and Bandwidth Effect.............. 303
7.9 Calibration of Current-Steering DAC......................................................................305
7.9.1 Static DAC Nonlinearity Error....................................................................305
7.9.2 Dynamic DAC Nonlinearity Error.............................................................306
7.9.3 DAC in Feedback........................................................................................... 307
References..............................................................................................................................308

8. Phase-Locked Loop Basics................................................................................................. 311

8.1 Phase Noise................................................................................................................. 311
8.1.1 Jitter versus Integrated Root-Mean-Square Phase
Noise............................................................................................................... 312
8.1.2 Amplitude-Modulation to Phase-Modulation
Conversion..................................................................................................... 313
8.1.3 Voltage-Controlled Oscillator Phase Noise............................................... 313
8.1.4 Single-Sideband (SSB) and Double-Sideband (DSB)
Phase Noises.................................................................................................. 315
8.1.5 Effect of Frequency Division on Phase Noise........................................... 317
8.2 Phase-Locked Loop Operation................................................................................ 318
8.2.1 Linear Model of PLL..................................................................................... 319
8.2.2 Second-Order PLL........................................................................................ 320
8.2.3 Stability of Second-Order PLL.................................................................... 323
8.2.4 Loop Filter with a Pole and a Zero............................................................. 324
8.3 Phase Noise Transfer Function................................................................................ 325
8.3.1 SSB Phase Noise Effect on Blocker............................................................. 327
8.3.2 Integrated Root-Mean-Square Phase Noise Effect
on Phase Modulation and Frequency Modulation.................................. 328
8.3.3 PLL as FM Demodulator.............................................................................. 330
8.4 Phase Detector............................................................................................................ 331
8.4.1 Multiplier as Phase Detector....................................................................... 331
8.4.2 Up/Down State Machine as Phase Detector............................................. 333
8.4.3 Phase Frequency Detector...........................................................................334
8.5 Charge-Pumped Phase-Locked Loop..................................................................... 335
8.5.1 Stability of Charge-Pumped PLL............................................................... 336
8.5.2 Loop Filter of Charge-Pumped PLL........................................................... 336
8.5.3 Reference Spur.............................................................................................. 338
8.5.4 Charge-Pump Circuits.................................................................................340
Contents xi

8.6 PLL Bandwidth Constraints..................................................................................... 341

8.6.1 Capture and Lock-In Ranges......................................................................342
8.6.2 Settling Requirement...................................................................................343
8.6.3 PLL versus Second-Order ∆Σ Modulator..................................................344
8.7 High-Q LC VCO.........................................................................................................345
8.7.1 LC Components in CMOS...........................................................................345
8.7.2 Oscillation Condition for LC VCO............................................................. 347
8.7.3 Phase Noise of LC VCO............................................................................... 349
8.7.4 1/f Noise Up-Conversion............................................................................. 352
8.7.5 Low Phase Noise Design for LC VCO....................................................... 353
8.7.6 Current versus Voltage Limiting................................................................ 354
8.7.7 Other Noise Sources in PLL........................................................................ 356
8.8 Low-Q Ring-Oscillator VCO.................................................................................... 357
8.8.1 Oscillation Condition for Ring-Oscillator VCO....................................... 357
8.8.2 Phase Noise of Ring-Oscillator VCO......................................................... 358
8.8.3 Q Effect on VCO Phase Noise..................................................................... 360
8.8.4 Low Phase Noise Design for Ring-Oscillator VCO................................. 361
8.9 Prescaler......................................................................................................................364
8.9.1 Pulse Swallower............................................................................................ 365
References.............................................................................................................................. 366
9. Frequency Synthesis and Clock Recovery..................................................................... 367
9.1 Phase-Locked Loop Applications............................................................................ 367
9.1.1 General Clock Generation........................................................................... 368
9.1.2 Low-Jitter Clock Generation........................................................................ 368
9.2 Digital PLL.................................................................................................................. 369
9.2.1 Time-to-Digital Converter........................................................................... 370
9.3 Frequency Synthesis.................................................................................................. 371
9.3.1 Integer-N versus Fractional-N Synthesizers............................................. 372
9.3.2 Fractional Spur.............................................................................................. 373
9.3.3 Spur Cancellation by Digital-to-Analog Converter................................. 375
9.3.4 Spur Shaping by ∆Σ Divider-Ratio Modulator......................................... 375
9.3.5 Phase-Frequency Detector/Charge-Pump Nonlinearity........................ 378
9.3.6 Bandwidth Constraint of Fractional-N Synthesizers............................... 379
9.4 Spur-Canceled Fractional-N Frequency Synthesizer............................................ 380
9.4.1 DAC-Based Spur Cancellation.................................................................... 380
9.4.2 Adaptive DAC Gain Calibration................................................................. 383
9.4.3 Minimum DAC Pulse Width.......................................................................384
9.4.4 Quantization Noise of the Spur-Canceling DAC..................................... 385
9.4.5 Sign-Sign LMS Algorithm........................................................................... 386
9.4.6 ∆Σ Divider Ratio Modulator........................................................................ 386
9.4.7 Calibration of VCO Frequency.................................................................... 388
9.5 Data Symbols.............................................................................................................. 389
9.5.1 Impulse Symbol............................................................................................ 390
9.5.2 Binary Pulse Symbol.................................................................................... 391
9.6 Data Channel Equalization...................................................................................... 393
9.6.1 Linear Equalizer............................................................................................ 393
9.6.2 Decision-Feedback Equalizer...................................................................... 394
9.6.3 Zero versus Cosine Equalizers................................................................... 395
xii Contents

9.7 Clock and Data Recovery.......................................................................................... 397

9.7.1 CDR with Band-Pass Filter.......................................................................... 398
9.7.2 Oversampling Digital CDR......................................................................... 399
9.7.3 Delay-Locked Loop for CDR....................................................................... 399
9.7.4 PLL for CDR...................................................................................................400
9.8 NRZ Phase Detector.................................................................................................. 401
References.............................................................................................................................. 403
Preface

From the early 1970s, the digitization of media has dramatically changed our lives, and
shaped the way in which we consume digital information. Because digital systems ben-
efit greatly from advanced complementary metal-oxide semiconductor (CMOS) technolo-
gies, they will prevail in the foreseeable cloud-computing and predominantly portable
multimedia era through wireless networks. In all digital systems, the processed data are
transmitted and received through wireline or wireless channels in the analog form. They
are also stored and recovered through magnetic or optical media. Most digital systems
are based on massive systems-on-chip (SoCs) with multiple analog/radio-frequency (RF)
interfaces. Analog/RF designs in this SoC environment require designers to be familiar
with both system- and transistor-level design aspects. As the complexity of SoCs grows,
analog/RF systems need to be designed using abstract concepts of the large components,
such as operational amplifiers (opamps), analog-to-digital converters (ADCs), and phase-
locked loops (PLLs).
This book aims to introduce analog design methodologies with specific emphasis on
analog systems that can be integrated into SoCs. The design starts from extracting an
abstract concept of both bipolar junction transistor (BJT) and metal-oxide semiconductor
(MOS) transistors, and builds larger systems using them. Readers may notice that this
book does not focus on the analysis but on the design aspect. Analog design concepts are
presented without resorting to derivations of lengthy equations for analysis. More intui-
tive approaches are taken based on the core design concepts. There are four introductory
chapters that emphasize the fundamentals of feedback stability (Chapter 1), the transistor/
amplifier concept (Chapter 2), data converter basics (Chapter 4), and PLL basics (Chapter 8).
The other five main chapters discuss opamps (Chapter 3), Nyquist-rate converters (Chapter
5), oversampling converters (Chapter 6), high-resolution converters (Chapter 7), and syn-
thesizers and clock recovery (Chapter 9). All feedback systems such as opamps, ∆Σ modu-
lators, and PLLs are presented consistently using common basic circuit concepts and the
same parameters for linear small-signal analysis.
This book is mainly written and organized to give proper perspectives on the various
designs of data converters and PLLs, which are the two most common analog circuit com-
ponents in SoCs. The materials covered in the book are suitable for graduate-level students
and advanced engineers in the field, though the four introductory chapters are written
for engineers with an undergraduate background. Readers are advised to review the four
introductory chapters to become familiar with the basic circuit concepts before they move
on to the main chapters for practical designs of microCMOS systems.

Bang-Sup Song
La Jolla, California

xiii
Acknowledgments

Many thanks go to my graduate students Seung-Hoon Lee, Unku Moon, Tzishiung Shu,
Sung-Ung Kwak, Myung-Jun Choe, Alex Bugeja, Woogeun Rhee, Hsinshu Chen, Chun
Huat Heng, Seung-Tak Ryu, Sourja Ray, Supisa Lerstaveesin, and Yunshiang Shu, and
also to my industry friends M. Tompsett, K. Bacrania, D. Soo, P. Lakers, S. Gillig, T. Cho,
D. Kang, Y. Konno, K. Tomioka, Y. Aiba, K. Yamazoe, K. Hamashita, J. Kamiishi, T. Suzuki,
S. Takeuchi, K. Koyama, and T. Yoshioka. Without their contributions, this book would
not exist.
Special thanks go to Professor Wai-Kai Chen, University of Illinois, Chicago; the staff at
Taylor & Francis/CRC Press; and also to Drs. Chong Lee and John Hong, Qualcomm, for
their encouragement.

xv
The Author

Bang-Sup Song, Ph.D., received a B.S. from Seoul National University, Korea, in 1973,
an M.S. from Korea Advanced Institute of Science in 1975, and a Ph.D. from the University
of California–Berkeley in 1983. From 1975 to 1978, he was a member of the research staff
at the Agency for Defense Development, Korea. From 1983 to 1986, he was a member of
the technical staff at AT&T Bell Laboratories, Murray Hill, New Jersey, and was also a
visiting faculty member in the Department of Electrical Engineering, Rutgers University,
New Jersey. From 1986 to 1999, Dr. Song was a professor in the Department of Electrical
and Computer Engineering and the Coordinated Science Laboratory at the University of
Illinois at Urbana. In 1999, Dr. Song joined the faculty of the Department of Electrical and
Computer Engineering, University of California, San Diego, where he is endowed with the
position of Charles Lee Powell Chair Professor in Wireless Communication.
Dr. Song received a Distinguished Technical Staff Award from AT&T Bell Laboratories
in 1986, a Career Development Professor Award from Analog Devices in 1987, and a Xerox
Senior Faculty Research Award from the University of Illinois in 1995. His Institute of
Electrical and Electronics Engineers (IEEE) activities have been in the capacities of an asso-
ciate editor and a program committee member for the IEEE Journal of Solid-State Circuits,
IEEE Transactions on Circuits and Systems, International Solid-State Circuits Conference, and
International Symposium on Circuits and Systems. Dr. Song is an IEEE fellow.

xvii
1
Amplifier Basics

Amplifiers operate mostly in a linear mode, and their performance is improved by

­applying feedback. Basic circuit concepts such as complex transfer function, poles,
­frequency and transient responses, trade-off of gain for bandwidth and linearity, feed-
­forward zero, and stability criteria of feedback systems are essential to understand, design,
and operate amplifier circuits properly.

1.1  Driving-Point and Transfer Functions

Consider any electrical networks with one or two ports as shown in Figure 1.1. We can
define the voltage on each port and the current flowing into each terminal. Here, the volt-
age and current are small signal and frequency dependent.
In the one-port case shown on the left side, the following two ratios of the voltage and
current can be defined as

vi ( s) i ( s)
Z( s) = , and Y ( s) = i . (1.1)
ii ( s) vi ( s)

The former is the driving-point impedance, and the latter is the driving-point admittance.
Their units are Ω and 1/Ω, respectively. At low frequencies, they are commonly called
driving-point resistance and conductance, respectively. That is, if the input and output are
referred to the same port, the term driving point is used. Similarly, in the two-port case as
shown on the right side, the four ratios can be defined as follows:

vo ( s) i ( s) v ( s) i ( s)
Av ( s) = , Ai ( s) = o , Z( s) = o , and Y ( s) = o , (1.2)
vi ( s) ii ( s) ii ( s) vi ( s)

where Av(s) and Ai(s) are the unit-less transfer functions called the voltage and current
gains, respectively. The latter two definitions are the same as in Equation (1.1) for the one-
port network, but they are now called transimpedance and transadmittance as the input
and output ports are referred to two ports. The prefix trans relates voltages and currents
in two different terminals. Of course, at low frequencies, they are more commonly called
transresistance and transconductance, respectively.

1
2 MicroCMOS Design

ii ii io
vi Network vi Network vo

One-port network Two-port network

FIGURE 1.1
Driving-point and transfer concepts.

1.2  Frequency Response

In the small-signal steady state, impedances of reactive components such as inductor
and capacitor are frequency dependent as sL and 1/sC, where s is the frequency of jω.
The unit of ω is rad/sec. Note that the angular frequency ω is defined as the amount of
angle rotation per second, and the ordinary frequency f in the Hertz (Hz) unit is defined
as the number of rotations per second. Because one rotation covers an angle of 2π radian,
there exists a 2π difference in the relation of ω = 2πf. In steady state, all transfer functions
of electronic circuits can be represented using a general transfer function H(s), which is
a ratio of two polynomials N(s) and D(s) as follows:

N ( s) b1 sm + b2 sm−1 +  + bm
H ( s) = = . (1.3)
D( s) a1 sn + a2 sn−1 +  + an

The solutions of D(s) = 0 are poles, and those of N(s) = 0 are zeros. Poles and zeros affect
both the frequency and transient responses.
If s is replaced by jω, the steady-state frequency response is obtained. The frequency
response is expressed as a complex transfer function H(jω), which can be written in a
vector form:

H ( jω ) = H R (ω ) + jH I (ω ) = M(ω )e jθ(ω ) . (1.4)

For the gain and phase-response plots, the magnitude and phase responses in Equation
(1.4) can be rewritten as follows:

M(ω ) = H ( jω ) = H R2 (ω ) + H I2 (ω ). (1.5)

H I (ω )
θ(ω ) = H ( jω ) = tan −1 . (1.6)
H R (ω )

The following is an example of the frequency response defined in Equation (1.4) with
three poles and two zeros:
Amplifier Basics 3

 jω   jω 
ao  1 +   1+
 ω z1   ω z 2 
H ( jω ) = , (1.7)
 jω   jω   jω 
 1 + ω   1 + ω   1 + ω 
p1 p2 p3

where ωp1, ωp2, ωp3, ωz1, and ωz2 are pole and zero frequencies. Note that the frequency
is normalized to each pole or zero frequency. This factorized transfer function is a
convenient form to use for analysis. It enables designers to handle the gain and phase
responses separately. Therefore, the most common amplifier design strategy is to
set the direct current (DC) gain parameter and to consider the high-frequency effect
individually.
At low frequencies where ω/ωp or ω/ωz is far smaller than 1, all imaginary terms can be
ignored, and the transfer function is very close to the real number ao with no significant
phase shift. Therefore, ao in the voltage or current gain transfer function is commonly
called a small-signal, low-frequency, or DC gain. In general, the small-signal parameter
ao can be any of the small-signal low-frequency parameters such as driving-point resis-
tance, driving-point conductance, voltage gain, current gain, transresistance, or transcon-
ductance as defined in Equations (1.1) and (1.2). Now at high frequencies where ω/ωp or ω/
ωz is no longer negligible compared to 1, the imaginary terms begin to contribute to the
transfer function, and its gain and phase vary with frequency. Both the gain and phase
responses given by Equations (1.5) and (1.6) can be derived for the example of Equation
(1.7) as follows:

 jω   jω   ω2   ω2 
ao  1 +   1+   1+ 2  1+ 2 
 ω z1   ω z2   ω z1   ω z2 
M(ω ) = = ao . (1.8)
 jω   jω   jω   ω 2   ω  2  ω2 
 1 + 1 + 1 + 1 + 1 + 1 +
ω p 1   ω p 2   ω p 3   ω 2p 1   ω 2p 2   ω 2p 3 

ω ω ω ω ω
θ(ω ) = tan −1 + tan −1 − tan −1 − tan −1 − tan −1 . (1.9)
ω z1 ω z2 ω p1 ω p22 ω p3

Consider an example of a transfer function with a DC gain of 100 dB (105), one zero at
107 rad/sec, and three poles at 10, 106, and 108 rad/sec, respectively. Then, the transfer func-
tion of Equation (1.7) is given by

 jω 
105  1 + 7 
 10 
H ( jω ) = . (1.10)
 jω   jω   jω 
 1 + 10   1 + 106   1 + 108 
4 MicroCMOS Design

Both gain and phase responses can be derived by plugging the real numbers from Equation
(1.10) into Equations (1.8) and (1.9).

 ω2 
 1 + 1014 
M(ω ) = 105 . (1.11)
 ω2   ω2   ω2 
1 + 1 + 1 +
 102   1012   1016 

ω ω ω ω
θ(ω ) = tan −1 − tan −1 − tan −1 6 − tan −1 8 . (1.12)
107 10 10 10

The standard Bode plots are these two separate gain and phase responses as sketched
in Figure 1.2 using the log scale for gain and frequency. The solid straight lines in the plots
are just for illustration, and the actual gain and phase responses should make smooth
transitions across the pole and zero frequencies as sketched with dotted lines. The over-
all gain slope varies from –6 dB/oct to –12 dB/oct, and the phase delay is maintained at
about –90° at low frequencies but approaches –180° gradually at high frequencies. The
zero in the middle makes some irregularities both in the gain and phase slopes.
Note that gain increases and phase leads after passing zero frequencies, while gain
decreases and phase lags after passing pole frequencies. That is, the magnitude decreases
as a function of 1/ω after each pole, which is equivalent to the gain slope of –6 dB/oct or
–20 dB/dec in the Bode gain plot. Here in the unit, the frequency multiples of octave (×2)
and decade (×10) are abbreviated as oct and dec, respectively. At a pole frequency, the gain
drops by about –3 dB, which is equivalent to the attenuation by 1/ 2 . The phase delay
is a nonlinear tan–1 function, and at the pole frequency, the phase delay is –45°, which is
–tan–11. The same can be said for each zero with the gain slope of 6 dB/oct or 20 dB/dec,

log M(ω)
ωp1 = 10
Ao = 105
(100 dB) –6 dB/oct ωp2 = 106
ωz1 = 107
ωp3 = 108
log ω

–12 dB/oct
θ(ω)

log ω

–90°

–180°

FIGURE 1.2
Bode gain and phase plots.
Amplifier Basics 5

and the gain of 3 dB and the phase lead of 45° at the zero frequency. These simplified
graphical representations of the open-loop Bode gain and phase plots are convenient for
stability analysis.

1.3  Stability Criteria

Every circuit node inside a network makes its own pole that is complex, and it character-
izes the way the circuit node behaves both in the steady-state and transient conditions.
Poles are associated with their unique natural frequencies. Note that poles are only deter-
mined by the circuit parameters, regardless of the external sources. If the pole at the ith
circuit node is assumed to be pi, then its transient response is characterized by an expo-
nential function. So the transient response of a network can be the linear sum of all natural
responses contributed by all of its poles as follows:

vo (t) = ko + k1e p1t + k2 e p2t + k3e p3t +  , (1.13)

where pi is a pole, and ki is a constant set by the transient condition. Zeros only affect the
transient condition, not the natural response. Because pi is a complex number, it has both
real and imaginary parts like pi = α + jω. The real part represents the exponential enve-
lope, and the imaginary part is the frequency component. If poles are negative real poles,
the natural response is a pure decaying exponential because the real part of pi is negative.
Otherwise, it is a sinusoid decaying exponentially.

e pit = e(α + jω )t = e αt e jωt = e αt (cos ω t + j sin ω t). (1.14)

The real part of Equation (1.14) is the natural response of the complex conjugate poles, and
the imaginary part is its quadrature image. Therefore, for any system to be exponentially
stable, the real parts of its poles should be negative (α < 0) so that any transients may decay
exponentially over time.
Figure 1.3 shows three cases with the same negative real pole but with different transfer
functions. The circuit on the left side is the Norton’s equivalent circuit of the low-pass filter

vo R vo 1 vo sRC
= = =
ii 1 + sRC vi 1 + sRC vi 1 + sRC

R C
vo vo vo

ii C R vi C vi R

FIGURE 1.3
Single resistance-capacitance (RC) pole cases.
6 MicroCMOS Design

jω jω

α α

FIGURE 1.4
Location of poles in the complex s-plane.

shown in the middle. The circuit on the right is a high-pass filter. They all have the same
time constant of resistance-capacitance (RC), and the negative real pole is at –1/RC. The
high-pass filter has a zero at DC due to the capacitor in the signal pass. Note that signal feed-
forward through a capacitor always creates a zero. The natural responses of the three are the
same because they have the same pole. Because the signal is attenuated by 3 dB at the pole,
the pole frequency is also called –3 dB bandwidth or cut-off frequency, as defined below:

1 1 1
ω −3 dB = = , f−3 dB = , ω −3 dB = 2 πf−3 dB , (1.15)
RC τ 2 πRC

where the units for ω−3dB, f−3dB, and τ are rad/sec, Hz, and sec, respectively. Only the time
constant τ affects the exponential decay of the natural response, and it is set by the net-
work parameter RC regardless of the signal source.
If there is no feedback applied to any networks that consist of transistors, resistors, and
capacitors, their poles are always negative real as shown in Figure  1.4. If they include
inductors, poles become complex conjugate but remain in the open left-half complex
s-plane. Therefore, all networks without feedback such as open-loop amplifiers are always
stable.
Stability is a concern only in feedback amplifiers. If the feedback loop gain is increased,
poles may move into the right-half complex s-plane, thereby causing instability. Stability of
the feedback network can be analyzed using either the Root-Locus method in the complex
s-plane or the Bode gain and phase plots. The latter is far simpler, as the former is dif-
ficult to obtain analytically without using computers. Simplified Bode plots as shown in
Figure 1.2 are handy for all stability analysis.

1.4  Operational Amplifier (Opamp) in Negative Feedback

An opamp can be considered a device or a circuit block that amplifies a differential input
with a very high DC gain. Its input resistance is also very high. Most low-frequency feed-
back amplifier designs using opamps start with an assumption that opamps are ideal, and
only the stability and finite bandwidth effects are considered later. The open-loop transfer
function of the opamp is approximated as a single pole roll-off as explained using the Bode
plots in Figure 1.5.
Amplifier Basics 7

log M(ω)

+ ωp
a(s) ao
− –6 dB/oct
ωunity = aoωp

ao log ω
a(s) =
1 + s/ωp

θ(ω)
DC Gain (G) = ao
Bandwidth (B) = ωp
log ω
GB = aoωp = ωunity
−45°
−90°

FIGURE 1.5
An opamp and its open-loop gain and phase responses.

log M(ω)

ωp ωk = (1 + To)ωp
vi + ao
− a(s) vo ao ωunity = aoωp
−
1 + To
log ω
f
θ(ω)

f : Feedback Factor, 0 ≤ f ≤ 1 log ω

DC loop gain To = aof −45°
−90°

FIGURE 1.6
An opamp-based feedback amplifier.

Assume that opamp has a DC gain of ao and a single negative real pole at –ωp, which sets
the open-loop –3 dB bandwidth to be ωp. The phase delay at the pole frequency is about
–45°, and the total phase delay after one pole becomes –90°. Therefore, the gain-bandwidth
(GB) product is aoωp, which is the frequency where the open-loop gain becomes unity. This
open-loop unity-gain frequency is marked as ωunity. Note that opamp is a high-gain ampli-
fier, but its open-loop bandwidth is very narrow. Therefore, the excess gain can be traded
for wider bandwidth with negative feedback.
Figure  1.6 shows a closed-loop feedback amplifier using an opamp. In this standard
negative feedback example, the output is attenuated by f and subtracted from the input.
The forward gain of the opamp is a(s), and the feedback factor is f, which is assumed to be
8 MicroCMOS Design

independent of frequency with a value ranging from 0 to 1. If f = 0, there is no feedback, and
the amplifier is an open-loop amplifier with the gain of a(s). If f = 1, the whole output is fed
back and subtracted from the input. This feedback condition is called the ­worst-case unity-
gain feedback. The loop gain T(s) and the closed-loop gain H(s) can be defined as follows:

T ( s)  = a( s) f .
vo ( s) a( s) a( s) (1.16)
H ( s) = = = .
vi ( s) 1 + a( s) f 1 + T ( s)

The following relation between the two low-frequency (DC) parameters, DC loop gain To
and closed-loop DC gain Ho, clearly explains the feedback effect that the gain decreases as
the loop gain increases.

To = ao f .
ao ao a 1 (1.17)
Ho = = ≈ o = .
1 + ao f 1 + To To f

The negative feedback improves the amplifier performance drastically. Because the
open-loop DC gain ao is lowered by (1 + To) after feedback, the closed-loop DC gain Ho is
about 1/f as given in Equation (1.17) if the DC loop gain To is high. This implies that the
closed-loop DC gain is no longer affected by the open-loop DC gain ao, which heavily
depends on process, supply voltage, and temperature (PVT) variations. Although the DC
gain ao is reduced after feedback, all other parameters such as linearity, impedance, signal
range, bandwidth, and sensitivity to PVT are improved. One of the most notable trade-
off effects is that the closed-loop bandwidth ωk is widened by the same factor (1 + To) as
sketched using the solid line on the right side of Figure 1.6. Note that ωk is the frequency
where the feedback loop gain is unity. Therefore, ωk can be called either unity loop-gain
frequency or −3 dB bandwidth of the closed-loop gain.
This single-pole negative feedback is absolutely stable with a phase margin of 90° because
the total loop phase delay is only –90° at ωk. However, real opamps have many nondomi-
nant high-frequency poles, which contribute some phase shift at ωk. Therefore, the stability

−(1 + Το)ωp −ωp −ωp2 –ωp1 −ωp3 −ωp2 –ωp1

One pole Two poles Three poles

FIGURE 1.7
Three cases of Root Locus as To increases.
Amplifier Basics 9

of feedback amplifiers using opamps should be closely looked at. To ensure the stability
of a feedback amplifier with opamp, its poles of the transfer function that are the solutions
of 1 + T(s) = 0 should be in the open left-half complex s-plane. Three cases of Root Locus in
Figure 1.7 show the poles in the complex s-plane when the loop gain is increased.
In one- or two-pole cases, poles still stay in the open left-half plane, but in the three-pole
case, two complex conjugate poles are moving toward the right-half plane as To increases.
Therefore, three-pole opamps are conditionally stable only with low loop gain and would
be unstable for most usable feedback conditions. The situation gets far worse with more
poles than three.

1.5  Phase Margin

For an opamp to be stable with negative feedback applied, the total excess loop phase
delay should be less than 180° at the unity loop-gain frequency ωk where the loop gain is
unity, or the loop gain should be less than unity at the frequency where the total excess
loop phase delay is 180°. This is to prevent the negative feedback from becoming the posi-
tive feedback. The Bode gain plot of the open-loop transfer function a(s) can be easily
decomposed into two separate plots. One is the feedback loop gain T(s), and the other is
the closed-loop gain H(s) as shown in Figure 1.8.
The most important frequency to note is again the unity loop-gain frequency ωk. The
dotted line drawn horizontally in the open-loop gain plot indicates the feedback loop gain
of unity. The top portion above the line is the feedback loop gain, and what is left after
removing the top portion is the closed-loop gain. If the DC loop gain To is taken off from
the open-loop DC gain ao, the closed-loop gain Ho is left. At low frequencies, Ho is about
1/f. It is lower than the open-loop gain ao by the DC loop gain (1 + To) ~ To = aof. After
this gain trade-off, the closed-loop gain Ho now depends only on the passive feedback

log |T(jω)|

ωp
To ~ aof
log M(ω) ωk
ωp log ω
ao
To ~ aof ωk

~1/f ωunity
log ω

log |H(jω)|
ωk
ao
~ 1/f
1 + To ωunity
log ω

FIGURE 1.8
Bode gain plot with feedback.
10 MicroCMOS Design

­ etwork regardless of the open-loop gain ao. Therefore, the broad-banded closed-loop

n
amplifier with a lower gain Ho becomes more linear. Because the gain slope is –6 dB/oct,
the following gain–bandwidth relations still hold:

ω k = ( 1 + To ) ω p ≈ Toω p = ( ao f ) ω p = fω unity .
 a   a  (1.18)
GB =  o  ω k =  o  ( 1 + To ) ω p = aoω p = ω unity .
 1 + To   1 + To 

For frequencies higher than ωk, the closed-loop gain stays the same as the open-loop gain
because the feedback loop gain is less than unity.
The gain or phase margin (GM or PM) is defined as a room for extra loop gain or loop
phase until the negative feedback opamp becomes unstable. In order to define the GM,
another frequency ω180, which is the frequency where the extra loop phase delay becomes
–180°, should be defined. Using ωk and ω180, the GM and PM are graphically explained in
the Bode gain and phase plots of a three-pole feedback opamp in Figure 1.9.
Because each pole contributes a phase delay of 90°, a total of –270° phase delay by three poles
can cause a negative feedback opamp to be unstable with high loop gain. Two dotted lines are
drawn horizontally in both the gain and phase plots where the loop gain is unity and where
the phase shift is −180°, respectively. So, both GM and PM can be estimated as follows:

1
GM = , T ( jω 180 ) = −180o.
T ( jω 180 ) (1.19)
PM = 180o − T ( jω k ) , T ( jω k ) = 1.

However, it is not necessary to specify both GM and PM, and either one would suffice. In
practice, PM is more widely used. For the three-pole one-zero transfer function example

log M(ω)
ωp1
ao ωp2
To ~ aof ωk

~1/f GM
log ω
ωp3

θ(ω)
log ω
−45°
−90°
−135°
PM
−180°
ω180

FIGURE 1.9
Open-loop Bode plots of a three-pole opamp.
Amplifier Basics 11

given in Equation (1.10), PM can be estimated from Equation (1.19) as follows for any given
feedback factor f:

 ω 2k 
 1 + 1014 
105 f = 1.
 ω 2k   ω 2k   ω 2k 
 1 + 102   1 + 1012   1 + 1016  (1.20)

ωk ω ω ω
PM = 180o + tan −1 − tan −1 k − tan −1 k6 − tan −1 k8 .
107 10 10 10

After finding ωk from the gain plot, it can be used to estimate the PM in the phase plot.
In most feedback amplifiers, the optimum PM to target is greater than 60°. If PM is
smaller than 60°, the frequency response exhibits a slight peaking at the unity loop-gain
frequency, and the transient response tends to ring. If PM is 45°, the closed-loop gain at ωk
becomes

a ( jω k ) a ( jω k )
H ( jω k ) = = ≈ 1.3 a ( jω k ) . (1.21)
1 + T ( jω k ) 1 + e − j 135o

This implies that the frequency response would peak by about 30% at the pass-band edge
as sketched in Figure 1.10.
If PM = 0°, the loop gain becomes −1 at ωk because T(jωk) = exp(−j180°) in Equation (1.21).
Then the closed-loop gain becomes infinite, which means instability. Any noise power
at ωk will grow exponentially. Because ±jωk are the solutions of the denominator polyno-
mial D(s) = 0, they are poles of the closed-loop transfer function H(s). That is, two complex-
conjugate poles are at ±jωk on the imaginary axis. This also implies that the Root Locus of
two complex-conjugate poles are right on the imaginary axis. When the unity loop-gain
frequency ωk is close to the second pole, PM is about 45°. Therefore, to achieve a PM greater
than 60°, it is necessary to either move the second pole out to frequencies higher than ωk or
add a zero to compensate for the phase delay contributed by the second pole. However, if
the pole-zero cancellation occurs at lower frequencies than ωk, the transient response will
still settle slowly with the time constant of the canceled pole. In practice, to avoid peak-
ing in the frequency response and ringing in the transient response, PM greater than 60°
should be warranted without any pole-zero cancellation.

PM = 45°
log |H(jω)|

30%
~1/f

PM = 60°
log ω
ωk

FIGURE 1.10
Phase margin (PM) effect on the frequency response.
12 MicroCMOS Design

1.6  Transient Response

Let us consider a purely exponential transient response settling with a good PM. The
­open-loop response is still assumed to be one pole roll-off as follows:

ao aoω p ω unity
a( s) = ≈ = .
s s s (1.22)
1+
ωp

Then, the closed-loop transfer function is defined as

a( s) 1 1
H ( s) = ≈ .
1 + a( s) f f  s  (1.23)
 1 +
ω k 

Now if the step input with a magnitude Vstep is applied at t = 0, its Laplace transform is

Vstep
Vi ( s) = . (1.24)
s

From Equations (1.23) and (1.24), the output in the complex frequency domain is obtained
as

Vstep 1
Vo ( s) = H ( s)Vi ( s) = .
f  s  (1.25)
s 1 +
 ω k 

Therefore, by taking its inverse Laplace transform, the transient response is obtained as

Vstep  − 
t
1 1
vo (t) =  1− e τ , τ = = . (1.26)
f   ωk fω unity

As expected, the natural response to the step input is exponential and has a time constant
of 1/ωk, and the output step voltage is Vstep/f as shown in Figure 1.11.

t=0

Vstep/f

τ = 1/ωk

FIGURE 1.11
Transient response of a feedback amplifier.
Amplifier Basics 13

This most desirable exponential step response is achievable only with negative real
poles. However, complex-conjugate poles are generated in any feedback amplifier. In the
worst-case unity-gain feedback (f = 1), the step response of the voltage follower can exhibit
both exponentially decaying and sinusoidal natural responses as shown in Figure  1.12.
Depending on PM, one feature is more prominent than the other.
In real feedback opamps, the zero in the open-loop transfer function or poor PM can
cause the transient peaking or ringing, and excessive ringing due to poor PM should be
avoided. Assume that a feedback amplifier has a poor PM with two complex-conjugate
poles. In the complex-conjugate pole case, the following form of the closed-loop transfer
function H(s) is more convenient to use:

1 1 1 1
H ( s) = = ,
f  1 s s2  f  s s2  (1.27)
 1 + + 1 + 2ρ +
Q ω o ω 2o   ω o ω 2o 

where Q is the quality factor, and ρ is the damping factor. The complex poles in the s-plane
and the overshoot and ringing in the transient output are explained in Figure 1.13.
High Q means that the poles are closer to the imaginary axis. As a result, PM decreases,
and the ringing in the transient response lasts longer with a longer time constant. The
decaying time constant is inversely proportional to the distance from the imaginary
axis. That is, the higher the Q, the longer is the decaying time constant. The ringing

PM < 60°

−
vo
vi +
PM > 60°
t=0 t=0

FIGURE 1.12
Transient response of an opamp in a unity-gain feedback.

jω

ωο

α
ωο
2Q
t=0

FIGURE 1.13
Conjugate poles with ringing and overshoot in the transient response.
14 MicroCMOS Design

frequency is given as the vertical distance from the real axis in the complex s-plane.
Accurate analysis of the ringing is not worth the effort because ringing transient
responses are slow and nonlinear and should be avoided by all means when designing
feedback amplifiers.
Note that the transient response obtained based on the small-signal linear analysis
is only valid when the feedback opamp operates in a small-signal linear mode. With
a sudden large step input applied, the opamp input stage can be easily driven into a
nonlinear region, and real opamps behave nonlinearly and slew as will be discussed in
Chapter 3.

1.7  Feedback Amplifier

The feedback network shown in Figure  1.6 can be implemented using an opamp and a
resistive voltage divider as shown in Figure 1.14.
The Bode plots for the feedback loop gain and the closed-loop gain are included in the
figure with other important parameters. Again, the stability is determined by the excess
phase delay of the loop gain at the unity loop-gain frequency ωk. PM can be estimated as in
Equation (1.20). This configuration has a noninverting gain of ~1/f, and the input resistance
is high as the input looks into the opamp input. Although all opamps reject common-mode

log M(ω)
ωp1
ao
vi + ~aof ωk
a(s) vo
−
~1/f ωunity
R2
log ω
f
ωp2
R1
log |T(jω)|
ωp2
ao ~aof
a(s) = ωk
(1+s/ωp1) (1+s/ωp2)
log ω
R1
f=
R1 + R2
log |H(jω)|
R1
To = aox ωk
R1 + R2
~1/f
R1 + R2 ωunity
Ho = log ω
R1

ωp2

FIGURE 1.14
Opamp feedback with a resistive divider.
Amplifier Basics 15

Inverting R2
vo R2
=–
vi R1
R1
vi −
vo Ri = R1, Ro = Rop/To
a(s)
+
R1
f=
R1 + R2

Noninverting R2
vo R1 + R2
=
vi R1
R1
− Ri = ∞, Ro = Rop/To
a(s) vo
vi +
R1
f=
R1 + R2

FIGURE 1.15
Inverting and noninverting gain amplifiers.

signals, one drawback of this noninverting amplifier is the input ­common-mode swing.
For good PM greater than 60°, the nondominant pole ωp2 should be placed at far higher
frequencies than ωk in this example.
It is also possible to get the inverting gain from the same feedback amplifier. If the input
node is grounded to avoid the input common-mode swing, the signal can be applied
through the input resistor R1. Because the opamp input is a virtual ground, the resistor
R1 works as a voltage-to-current converter. The input current passes through the feedback
resistance R 2 and generates the negative output. Therefore, the same opamp feedback con-
figuration makes an inverting amplifier. Both inverting and noninverting amplifiers are
compared in Figure 1.15.
Although the gains of the two cases are different, both cases are identical in terms of
feedback as they use the same resistor-divider feedback network. That is, the feedback
factor f stays the same in both cases, as does the unity loop-gain frequency ωk. Note again
that the stability depends on the network parameters regardless of the signal applied.
Therefore, both amplifiers have the same PM.
Let’s see how the feedback factor f is related to the inverting feedback gain. If we relate
the output to the summing node after multiplying the open-loop gain a(s), the following
is obtained:

vo = − a( s){vi + ( vo − vi ) f }. (1.28)

Then, by rewriting it in the same closed-loop gain form, we obtain

vo − a( s)( 1 − f )
= . (1.29)
vi 1 + a( s) f
16 MicroCMOS Design

Inverting
R1 R2

R2
vo = − v
R1 i
vi

Noninverting R1 R2

R1 + R2
vo = vi
R1
vi

FIGURE 1.16
Inverting and noninverting gain amplifier concepts.

Approximating the DC (low-frequency) gain, f is replaced by R1/(R1 + R 2):

v o − ao ( 1 − f ) − ( 1 − f ) R
= ≈ =− 2. (1.30)
vi 1 + ao f f R1

This negative gain means that the low-frequency signal polarity is inverted because it is
equivalent to the 180° phase shift. Although feedback factor is identical, depending on
where the input is applied, the gain can be different, but the closed-loop bandwidth stays
the same for two cases. The inverting amplifier is more useful in most applications as its
input common-mode is grounded.
This concept of inverting and noninverting amplifiers is explained with a simple
­analogy in Figure 1.16. A straight line can be drawn crossing one reference point marked
by a darkened triangle, which is equivalent to the signal ground. As in the example,
depending on which part of the line is pushed (input), the other loose end moves by the
ratio of the distances from the reference point (output). The direction of movement repre-
sents the polarity of the input or output. If two points move in the same direction, the gain
is positive. Otherwise, the gain is negative. Because the resistances R1 and R 2 represent
the distance from the reference point, the input and output voltages are obtained by their
ratios as shown.

1.8  Feedback Effect

The input and output resistances of the inverting amplifier are modified by the shunt feed-
back. In general, shunt feedback lowers the impedance level.
Figure  1.17 shows the low-frequency equivalent circuits to find the input and output
resistances using the test signals vx and ix. Because the same current flows through R1 and
R 2, the following can be written:
Amplifier Basics 17

R2 R2

R1 ix R1
Ri
−
a(s) + vx − ixR1
+ −ao(vx − ixR1)
vx
−

+ Rop ix
a(s) Ro −aofvx
+
−
vx

f fvx f −

FIGURE 1.17
Input and output resistances of the inverting amplifier.

vx − ix R1 + ao ( vx − ix R1 ) = ix R2 . (1.31)

Then, the input resistance can be obtained as

vx R2
Ri = = R1 + ≈ R1 . (1.32)
ix 1 + ao

Due to this shunt feedback, the opamp input node becomes the virtual ground with
the resistance level of R 2/(1 + ao) ~ 0. However, the input resistance of the noninverting
­amplifier is still very high due to the high input resistance of the opamp.
Similarly from Figure 1.17, the output resistance of the inverting amplifier can be derived.
Ignore the current through the feedback network when looking into the output port,

vx + ao fvx
ix = . (1.33)
Rop

Then, the output resistance can be obtained as

vx Rop
Ro = = . (1.34)
ix 1 + ao f

As shown in Equation (1.34), the output resistance Rop of the opamp is reduced by the
amount of the loop gain.
18 MicroCMOS Design

1.8.1  Linear Range Improvement

There exist two high-gain amplifiers usually marked as a triangle in circuit diagrams.
One is the comparator, and the other is the opamp. The comparator is used as an open-
loop high-gain amplifier and even includes a digital latch to amplify a small seed signal
to either a high or low digital output. On the other hand, the opamp is always used as
a closed-loop feedback amplifier because the negative feedback allows trading gain for
bandwidth. Therefore, the stability should be warranted. The worst case is the unity-gain
feedback when f = 1 in the noninverting amplifier case. Because the output is subtracted
from the input without attenuation in the unity-gain feedback, the amplifier becomes a
voltage follower or a unity-gain buffer. That is, if the output is connected to the negative
input, the closed-loop gain is about unity.

ao
Ho = ≈ 1. (1.35)
1 + ao

As in the frequency response, the DC transfer characteristic is also modified when feed-
back is applied as shown in Figure 1.18. The high/low output swing (VH/VL) of the opamp
is limited due to the supply rails (VDD/VSS). In the open-loop case (f = 0), the opamp out-
put Vo changes approximately from VL to VH for a very small input from –VL/ao to VH/ao
because the DC gain ao is very high. Furthermore, the input offset voltage, which is defined
as an input voltage to make the output zero, is typically on the order of mV or two. As a
result, this open-loop configuration is of no use because it is impossible to bias the input
due to its high gain, and the bandwidth is too narrow.
With feedback, a wide bandwidth with a realistic gain is attained. As in the example,
when the feedback factor f is 0.1, the closed loop gain is ~1/f (~20 dB), and this feedback
amplifier now has a wider input range from –0.1 VL to 0.1 VH. The closed-loop bandwidth is
now widened by the same feedback factor from the narrow open-loop bandwidth ωp to 0.1
ωunity (fωunity). For the unity-gain feedback (f = 1), the input range is widest from –VL to VH
with the achievable maximum bandwidth of ωunity. However, the closed-loop gain is 0 dB.
That is, the feedback effect improves all amplifier parameters. In the unity-gain feedback

Vo

VH

VDD f = 0.1
Vi f=0
+ f=1
a(s) Vo
−VL −0.1VL
−
Vi
VSS
0.1VH VH
f

VL

FIGURE 1.18
DC transfer characteristics of the opamp and feedback amplifier.
Amplifier Basics 19

(f = 1), the open-loop gain is traded for the widest input range, the maximum bandwidth
ωunity, and the lowest output resistance.

1.9  Left-Half or Right-Half Plane Zero

Zeros do not affect the stability of the feedback amplifier, but they often let transient
responses overshoot due to its phase-leading characteristic. In circuits, there are a couple
of cases in which zeros can be created. Most of the time, zeros are created due to the feed-
forward of the signal. The most obvious case is when there is a series capacitor in the
signal path as explained in Figure 1.3. In this simple high-pass case, the zero is placed at
DC. Another case is when a pole in the feedback network becomes a zero. It is commonly
assumed that the feedback factor f is a frequency-independent constant, but in real circuits,
it can be frequency dependent. That is, if there is a pole in the frequency-dependent feed-
back factor f(s), it will become a zero of the closed-loop function because H(s) = a(s)/{1 + a(s)
f(s)}. Last, the zero insertion has been the common design tactic at the system level.
In most multistage feedback amplifiers or practical feedback systems such as PLL and ΔΣ
modulators, zeros are intentionally introduced to compensate for extra loop phase delay
for the stability reason. Assume that the feed-forward signal bypasses an amplifier that
has one pole and is directly added to the amplifier output after multiplied by the gain k as
shown in Figure 1.19.
Then, depending on the polarity of the gain stage, a zero is created either on the left
half or right half of the complex s-plane. Zeros in the left-half lead phase and raise gain as
frequency goes higher. They are harmless in most circuits except for the fact that they can
cause slow settling in the transient response. However, any feedback systems with zeros
on the right-half plane are difficult to stabilize.

log M(ω)
ωp
ωz
k ao

ωunity
k
log ω
vi +
a(s) vo θ(ω)
−
log ω
+a(s)
−90°
−a(s)
−180°

FIGURE 1.19
Creating zero by feed-forwarding.
20 MicroCMOS Design

If the amplifier gain is positive, the transfer function and the zero can be derived as
­follows because ao ≫ k.

s
ao + k
vo ( s) ao ω p
= +k≈ . (1.36)
vi ( s) s s
1+ 1+
ωp ωp

ao ω p ω unity
z≈− =− . (1.37)
k k

It is a negative-half plane zero if the gain is positive (ao > 0). Otherwise, the zero moves
to the right-half plane, and the phase lags like a pole. Therefore, the right-half plane zero
should be avoided in any feedback system because the delay it causes can easily make the
system unstable.
Only one right-half plane zero case exists. A Miller capacitance is added to frequency-
compensate two-stage opamps. The unexpected side effect of this pole-splitting Miller
compensation is that the input and output of the negative-gain amplifier are shorted
together by the capacitance at high frequencies as shown in Figure 1.20.
Assume that the capacitor shunts input and output of the inverting amplifier. Then the
transfer function and the right-half plane zero are given by

 g 
RC  s − m 
vo ( s)  C g (1.38)
= , ωz = m .
vi ( s) 1 + sRC C

log M(ω)

ωp
gmR

C ωz

1 log ω
vi −
gm vo θ(ω)
+
R
log ω

−90°

−180°

FIGURE 1.20
Right-half plane zero due to Miller capacitance.
Amplifier Basics 21

log M(ω)

ωp
gmR
Rz = 0, 2/gm
Rz ωz
C

1 log ω
vi − Rz = 1/gm
gm vo θ(ω)
+
R
log ω
Rz = 2/gm
−90° Rz = 1/gm
Rz = 0
−180°

FIGURE 1.21
Right-half plane zero cancellation.

The bandwidth is ωp = 1/RC, and the right-half plane zero is at the unity-gain bandwidth
of ωk = ωunity = gm/C. This implies that if the amplifier gain becomes lower than unity, the
signal passes through the capacitance without being inverted.
The simplest way to eliminate the right-half plane zero is to add a resistance Rz in series
with the capacitance. Then, Equation (1.38) can be rewritten as follows:

 g 
RC  s ( 1 − g mRz ) − m 
vo ( s)  C  1
= , ωz = . (1.39)
vi ( s) 1 + s ( R + Rz ) C  1 
 g − Rz  C
m

This becomes the same equation as Equation (1.38) if Rz = 0. Both the pole and right-half
plane zero change as the value of Rz increases. If Rz = 1/gm, the zero is completely canceled.
If Rz is further increased, the zero moves to the left-half plane. Once in the left-half plane, it
helps to lead the phase. With any nonzero value of Rz, the bandwidth becomes 1/(R + Rz)C.
However, because Rz is typically much smaller than R, this narrow-banding effect due to
the pole movement is minimal, but the zero movement should be considered. In the three
cases of Rz = 0, 1/gm, and 2/gm, the zero is placed at gm/C, ∞, and −gm/C, respectively, and
the Bode gain and phase plots are sketched in Figure 1.21.
To broadband feedback amplifiers, a left-half plane zero is intentionally added to cancel
the delay of a pole. The close-by pole-zero pair is called a doublet. The doublet is not det-
rimental to obtaining desired frequency and phase responses, but it affects the transient
response. This is because the spectrum of any transient input such as a step or an impulse
is spread over a wide range of frequencies. Let’s consider a transfer function with a pole wp
and a zero wz placed close by as follows:
22 MicroCMOS Design

s s
1+
vo ( s) ωz  ω p − ω z ω p
= = 1+  .
vi ( s) s  ω z  s (1.40)
1+ 1+
ωp ωp

For example, this transfer function responding to the unit step input of vi(s) = 1/s can be
derived by taking the inverse Laplace transform of vo(s):

 ω p − ω z  − −t 1
vo (t) = 1 +  e τ , τ= .
 ω z  ωp (1.41)

Note that the transient response has a slow-settling component given by the canceled pole.
Its magnitude is proportional to the distance of the zero from the pole. Therefore, when
accurate transient settling is required, the doublet should be placed only at higher fre-
quencies than the unity loop-gain frequency.

1.10  Stability of Feedback Amplifiers

As discussed earlier, open-loop opamps are not useful due to their high gain and the
­difficulty in biasing. Practical amplifiers with proper gain and bandwidth can be made
applying feedback. Figure 1.22 shows the four cases of opamps used in feedback.
The resistor feedback in Figure  1.22a is the most common amplifier configuration as
discussed earlier, and the feedback factor f affects the loop gain. It is stable if good PM is
assured at the unity loop-gain frequency. However, if the feedback resistance is large, an
extra pole in the feedback network due to the input capacitance of the opamp can contrib-
ute extra phase shift affecting the loop stability. Therefore, it is common to add a bypass
capacitance in parallel with the large feedback resistance to improve the PM.
Figure 1.22b is an integrator that is unstable at DC. Integrators are often used to make
active filters. However, the global negative feedback at a higher level makes them stable. For
example, in active filters, the resonator is stable although it is made of two DC-unstable inte-
grators with positive and negative polarities. The small-signal alternating current (AC) stabil-
ity can be warranted if the opamp is stable at the unity-gain frequency, because the feedback
capacitance shorts the opamp to be in unity-gain feedback at high frequencies. The opamp
input capacitance can lower the loop gain and the feedback factor at high frequencies.
The differentiator shown in Figure  1.22c is a unity-gain feedback amplifier at low
­frequencies, but it works like an open-loop amplifier at high frequencies. The capacitive
feedback amplifier shown in Figure 1.22d is the same as the amplifier shown in Figure 1.22a.
The difference is that it is unstable at DC because there is no DC path to the opamp input
node. In most switched-capacitor circuits, the opamp input is reset periodically.

1.10.1  Frequency-Dependent Feedback Factor

The feedback factor f is usually assumed to be independent of frequency. However,
­complicated feedback networks are in fact frequency dependent. In the simple examples
of the integrator and differentiator, an extra pole is introduced in the feedback network.
Amplifier Basics 23

− −

+ +

(a) (b)

− −

+ +

(c) (d)

FIGURE 1.22
Opamps in feedback.

Assume that the opamp used in both the integrator and differentiator has a single-
pole roll-off with a DC gain of ao and a bandwidth of ωp as shown in Figure 1.23. In the
­integrator case, the following relation can be written:

 sRC  ao
−  vi + ( vo − vi ) × × =v .
 (1 + sRC )   + s  o (1.42)
 1 w p 

Then the closed-loop transfer function and the feedback factor can be derived as follows:

1
vo ( s ) ao sRC
≈− ≈− .
vi ( s ) s 2 RC s
(1 + ao ) sRC + ω 1+
ao ω p (1.43)
p

sRC
f= .
1 + sRC

That is, the feedback factor is a high-pass filter, and above the closed-loop unity-gain
­frequency 1/RC, f remains constant at 1, which is the unity-gain feedback.
Because the feedback network includes a pole, the closed-loop response of the
­integrator has two poles as shown. At frequencies lower than 1/RC, Equation (1.43) can be
written as
24 MicroCMOS Design

C R

R C
νi − νi −
νo νo
+ +

log M(ω) log M(ω)

ωp ωp
Open Loop Open Loop
ao ao

ωunity ωunity
log ω log ω

1/aoRC 1/RC 1/RC

(ωunity/RC)1/2

FIGURE 1.23
Frequency responses of the integrator and differentiator.

vo ( s) ao −1
≈− ≈ . (1.44)
vi ( s) 1 + ( 1 + ao ) sRC sRC

It is the integrator as expected, and the dominant pole is at 1/(1 + ao)RC, which is expected
considering the Miller capacitance (1 + ao)C at the input node. At frequencies higher than
1/RC, Equation (1.43) can be approximated as

1
vo ( s) ao
≈− ≈ − sRC . (1.45)
vi ( s) s2 RC s
(1 + ao ) sRC + ω 1+
a ω
p o p

This places the nondominant pole at the open-loop unity-gain frequency ωunity = aoωpo as
sketched in Figure 1.23. Therefore, opamps used in the integrator should be compensated
up to the unity-gain frequency ωunity with the worst-case feedback factor of f = 1.
In the differentiator case also shown in Figure 1.23, the closed-loop transfer function is
similarly affected due to the frequency-dependent feedback network, which is now the
low-pass filter instead of the high-pass filter in the previous integrator case. Therefore,

vo ( s) ao sRC
=− .
vi ( s) s s2 RC
1 + ao + sRC + +
ωp ωp (1.46)
1
f= .
1 + sR C
Amplifier Basics 25

At frequencies lower than 1/RC, Equation (1.46) can be approximated as a differentiator.

vo ( s) a sRC
≈− o ≈ − sRC. (1.47)
vi ( s) 1 + ao

At frequencies higher than 1/RC, Equation (1.46) can be simplified as

vo ( s) ao sRC ao
≈− =− .
vi ( s) s 2 RC 1 + ao s (1.48)
1 + ao + sRC + 1+ +
ωp sR C ω p

The second term of the denominator shows that the transfer function is a differentiator
until the third term gets larger and becomes dominant. As the third term increases, the
transfer function follows the open-loop transfer function of the opamp.
The break frequency is obtained by equating the second term and the third term.

( 1 + ao ) ω p ω unity
ω bp ≈ ≈ . (1.49)
RC RC

There are two poles at this frequency, which is the geometric average of two frequencies
of 1/RC and ωunity as sketched in Figure 1.23. Therefore, opamps used in the differentiator
should be compensated up to this frequency ωbp, where the loop gain is unity.
In general, practical feedback factors are all frequency dependent at high frequencies.
However, all feedback systems can be assured to be exponentially stable if the loop phase
delay is less than 180° with sufficient PM at the unity loop-gain frequency whether the
feedback factor is frequency dependent or not.
Amplifier Design
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