COURSE NAME: DIGITAL CIRCUIT AND DESIGN VERILOG LAB #2
COURSE CODE: ECE2026
SLOT: L5+L6
PROGRAM: B.TECH
SCHOOL: ECE with (BML)
FACULITY NAME: Dr. JAYAKRISHNAN P
STUDENT NAME : Nurhassen Awoll
REG. NO.:18BML0103
SUB DATE : 12/08/2019
1.half_adder
Verilog code for half_adder
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule
Truth table
Input Output
a B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1
Wave form for half adder
RTL viewer for half adder
2,half_substractor
Verilog code for half_substractor
module half_subtractor(a,b,diff,borrow);
input a,b;
output diff,borrow;
wire a_n;
xor(diff,a,b);
and(borrow,a_n,b);
not(a_n,a);
endmodule
Truth table
input output
a b diff borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Wave form for half subtractor
RTL viewer for half subtractor
3.full_adder
Verilog code for full_adder
module full_adder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
wire w1,w2,w3;
and(w1,b,cin);
and(w2,a,cin);
and(w3,a,b);
xor(sum,a,b,cin);
or(carry,w1,w2,w3);
endmodule
Truth table
input output
a b cin sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
Wave form for full adder
RTL viewer for full adder
4.full_subtractor
Verilog code for full_subtractor
module full_subtractor(x,y,Bin,Bout,d);
input x,y,Bin;
output d,Bout;
wire w1,w2,w3;
not(x_n,x);
xor(d,x,y,Bin);
and(w1,Bin,y);
and(w2,y,x_n);
and(w3,Bin,x_n);
or(Bout,w1,w2,w3);
endmodule
Truth table
input output
a b bin diff bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Wave form for full subtractor
RTL viewer for full subtractor
5.decoder_3to8_
Verilog code for decoder_3to8
module decoder_3_8(a,b,c,d);
input d,b,c;
output [0:7] a;
not(d_n,d);
not(b_n,b);
not(c_n,c);
and(a[0],d_n,b_n,c_n);
and(a[1],d_n,b_n,c);
and(a[2],d_n,b,c_n);
and(a[3],d_n,b,c);
and(a[4],d,b_n,c_n);
and(a[5],d,b_n,c_n);
and(a[6],d_n,b,c);
and(a[7],d,b,c);
endmodule
Input output
a b C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Wave form for decoder
RTL viewer for decoder
6.demux_1_4
Verilog code for demux_1_4
module demux_1_4(I,s1,s0,y);
input[3:0] I;
input s0,s1;
output[3:0] y;
not(s1_n,s1);
not(s0_n,so);
and(y[0],I[0],s1_n,s0_n);
and(y[1],I[1],s1_n,s0);
and(y[2],I[2],s1,s0_n);
and(y[3],I[3],s1,s0);
endmodule
input output
I s1 S0 y3 y2 y1 y0
I 0 0 0 0 0 I
I 0 1 0 0 I 0
I 1 0 0 I 0 0
I 1 1 I 0 0 0
Wave form for DE multiplexer
RTL view for DE multiplexer
7.mux_4_1
Verilog code for mux_4_1
module mux_4_1(I,s1,s2,y);
input [0:3] I;
output y;
input s1,s2;
wire w1,w2,w3,w4;
not(s1_n,s1);
not(s2_n,s2);
and(w1,I[0],s1_n,s2_n);
and(w2,I[1],s1_n,s2);
and(w3,I[2],s1,s2_n);
and(w4,I[3],s1,s2);
or(y,w1,w2,w3,w4);
endmodule
input output
I0 I1 I2 I3 S1 S2 y
1 0 0 0 0 0 I0
0 1 0 0 0 1 I1
0 0 1 0 1 0 I2
0 0 0 1 1 1 I3
Wave form for 1 to 4 multiplexer
RTL viewer for 1 to 4 multiplexer
8. Encoder8:3
Verilog code for Encoder 8:3
module encoder_8_3(d,a,b,c);
input [7:0] d;
output a,b,c;
or(a,d[4],d[5],d[6],d[7]);
or(b,d[2],d[3],d[6],d[7]);
or(c,d[1],d[3],d[5],d[7]);
endmodule
Truth table
Input output
D0 D1 D2 D3 D4 D5 D6 D7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1
X X 1 0 0 0 0 0 0 1 0
X X X 1 0 0 0 0 0 1 1
X X X X 1 0 0 0 1 0 0
X X X X X 1 0 0 1 0 1
X X X X X X 1 0 1 1 0
X X X X X X X 1 1 1 1
Wave form for 8 to 3 encoder
RTL viewer for encoder
